Method for manufacturing semiconductor device, carrier, and sealing material

Abstract

In one example of a method for manufacturing a semiconductor device, a glass carrier 20 is bonded to a first surface 11 of a silicon substrate 10. A semiconductor chip 30 is mounted on a second surface 12 of the silicon substrate 10. Thereafter, the semiconductor chip 30 is sealed on the second surface 12 of the silicon substrate 10 to which the glass carrier 20 is bonded to form sealing material layers 40, 45. The warpage of the sealing material layers 40, 45 is prevented by utilizing the contraction of the glass carrier 20 at the time of sealing. The sealed semiconductor device may be further divided into individual pieces. This method can be used for, for example, 2.5D mounting of a semiconductor package.

Description

Method for manufacturing semiconductor device, carrier, and encapsulant

[0001] The present disclosure relates to a method for manufacturing a semiconductor device, a carrier, and an encapsulant.

[0002] In recent years, with the rapid advancement of high functionality of electronic devices represented by AI / HPC, etc., the size and density of semiconductor packages have been rapidly increasing. The package structure is not limited to the high density of surface mounting, and the package structure and mounting process have become more complex and diverse, such as inorganic (silicon) or organic interposer (Bridge die / RDL) technology, 2.xD mounting using the same, and 3D mounting (HBM / Chiplet) technology using TSV. For example, Resonac Co., Ltd. is mainly based on the 'Packaging Solution Center' and is developing technologies for the next-generation semiconductor packaging process from the perspective of customers (semiconductor manufacturers) by combining mounting processes and materials.

[0003] As a technology in such a semiconductor package field, Non-Patent Document 1 (see (b) of FIG. 1) discloses, for example, a method of mounting a semiconductor chip on a silicon wafer and then encapsulating the semiconductor chip.

[0004] Wei-Hong Lai et al., “A Comparative Study of 2.5D and Fan-out Chip on Substrate : Chip First and Chip Last”, 2020 IEEE 70th Electronic Components and Technology Conference (ECTC), p354-p360

[0005] In processes such as 2.5D mounting, after mounting a semiconductor chip on a silicon wafer, the semiconductor chip is encapsulated with an encapsulant. When performing this encapsulation, an encapsulant having a relatively higher linear expansion coefficient than the silicon wafer is used. Therefore, warping may occur in the encapsulated semiconductor device.

[0006] An object of the present disclosure is to provide a method for manufacturing a semiconductor device capable of reducing warping, and a carrier and an encapsulant used in the manufacturing method.

[0007] [1] In one aspect, this disclosure relates to a method for manufacturing a semiconductor device. This method for manufacturing a semiconductor device comprises the steps of: attaching a first carrier to a first surface of a substrate; mounting at least one semiconductor chip to a second surface of the substrate; and sealing the semiconductor chip on the second surface of the substrate to which the first carrier has been attached to form a sealing material layer.

[0008] In this manufacturing method, the semiconductor chip is encapsulated on a substrate to which the first carrier is attached. In this case, the first carrier prevents warping caused by the encapsulating material layer, thereby reducing warping.

[0009] Here, we will explain the relationship between the warping of the encapsulant layer (semiconductor device) and the encapsulant itself. In addition to the methods mentioned above, one way to reduce warping when forming the encapsulant layer is to reduce the elastic modulus of the encapsulant itself. In this case, warping is prevented by the elastic modulus of the substrate itself. Although this method is one solution, when semiconductor devices formed with low-elasticity encapsulants are assembled into individual components and mounted on a wiring board, they are heated to over 200°C during solder reflow. At that time, low-elasticity encapsulants tend to expand rapidly due to heating, due to their material design. For this reason, it is difficult to design a material that can achieve both reduced elastic modulus during encapsulation and prevention of expansion during heating, or it narrows the range of material selection for the encapsulant. Another method to reduce the elastic modulus is to reduce the amount of inorganic filler contained in the encapsulant and increase the resin content, but removing the inorganic filler increases the hygroscopicity. Increased hygroscopicity leads to a larger amount of moisture contained in the semiconductor device, and the rapid vaporization of moisture during solder reflow as mentioned above can adversely affect the semiconductor device. In contrast, the method described above reduces warping by attaching the first carrier to the substrate, thus reducing warping with simple means. Furthermore, compared to reducing warping solely with the encapsulating material, the range of encapsulating material selection can be broadened, allowing the use of an encapsulating material suitable for the characteristics of the semiconductor device. It should be noted that the manufacturing method described above may be used to further reduce warping by applying an encapsulating material with a reduced elastic modulus, and the present invention does not exclude the use of such an encapsulating material.

[0010] [2] In the method for manufacturing a semiconductor device described in [1] above, the first carrier is preferably a glass carrier. In this case, the shrinkage of the glass when it returns to room temperature from the time of heating can be used to suppress the shrinkage of the sealing material layer during sealing, thereby reducing the warping of the semiconductor device. Alternatively, the elastic modulus of the glass can be used to suppress the shrinkage of the sealing material layer during sealing, thereby reducing the warping of the semiconductor device.

[0011] [3] In the method for manufacturing a semiconductor device according to [1] or [2] above, the coefficient of linear expansion α1 below the glass transition temperature of the first carrier is preferably 0 to 20 ppm / K. In this case, the shrinkage of the first carrier can be used to suppress the shrinkage of the sealing material layer during sealing, thereby reducing the warping of the semiconductor device.

[0012] [4] In any of the semiconductor device manufacturing methods described in [1] to [3] above, the elastic modulus of the first carrier at room temperature may be 5 to 100 GPa. In this case, the high elastic modulus of the first carrier can be used to suppress the shrinkage of the sealing material layer during sealing and reduce the warping of the semiconductor device. Hereinafter, "room temperature" refers to, for example, 20°C, and the same applies hereafter.

[0013] [5] In any of the semiconductor device manufacturing methods described in [1] to [4] above, the ratio of the thickness of the first carrier to the thickness of the sealing material layer may be 0.3 or more and 1.5 or less. In this case, since the thickness of the first carrier and the sealing material layer are equal, the first carrier can reliably prevent warping caused by the sealing material layer.

[0014] [6] In any of the semiconductor device manufacturing methods described in [1] to [5] above, the coefficient of linear expansion α1 below the glass transition temperature of the sealing material layer may be 1 to 30 ppm / K. In this case, shrinkage of the sealing material layer during sealing can be suppressed, and warping of the semiconductor device can be reduced.

[0015] [7] Any of the semiconductor device manufacturing methods described in [1] to [6] above may further include a step of grinding the surface of the sealing material layer with the first carrier attached. In this case, since the sealing material layer is reliably supported by the first carrier, the grinding accuracy of the sealing material layer can be improved.

[0016] [8] Any of the semiconductor device manufacturing methods described in [1] to [7] above may further include a step of attaching a second carrier to the encapsulating material layer on the side opposite to the first carrier. In this case, the increase in warping when the substrate is thinned can be prevented by the second carrier provided on the opposite side of the encapsulating material layer.

[0017] [9] The method for manufacturing a semiconductor device described in [8] above may further include a step of separating the first carrier from the substrate after the second carrier has been attached to the encapsulating material layer. In this case, various treatments can be performed on the surface (first surface) of the substrate after the first carrier has been separated.

[0018]

[10] The semiconductor device manufacturing method described in [9] above may further include a step of reusing the separated first carrier. In this case, the first carrier can be reused. When the first carrier is a glass substrate such as a glass carrier, it is often expensive, and by reusing it, the manufacturing cost can be reduced. As for the method of reuse, for example, it can be reused as the first carrier in any of the methods described in [1] to [9] above, but is not limited to this and may be used in other methods as well.

[0019]

[11] The semiconductor device manufacturing method described in [8] above may further include a step of grinding off the first carrier from the substrate after the second carrier has been attached to the encapsulating material layer. In this case, when the first carrier is attached to the substrate, the two can be joined with a strong adhesive. This allows the first carrier to receive the force (warpage) applied to the substrate, thereby reliably reducing warpage.

[0020]

[12] Any of the semiconductor device manufacturing methods described in [8] to

[11] above may further include a step of injecting a protective material around the outer circumference of the sealing layer between the substrate and the second carrier. The outer circumference of the sealing layer may be smaller than the outer circumference of the substrate, or the outer edge of the sealing layer may be prone to chipping, which can cause cracks in the substrate, etc. Injecting a protective material around the outer circumference of the sealing layer can reduce the occurrence of cracks.

[0021]

[13] In any of the semiconductor device manufacturing methods described in [8] to

[12] above, the second carrier is preferably a glass carrier. In this case, the laser can be transmitted through it. This makes it possible, for example, to laser peel off the adhesive layer of the glass carrier.

[0022]

[14] In any of the semiconductor device manufacturing methods described in [8] to

[13] above, the coefficient of linear expansion α1 of the second carrier below the glass transition temperature may be smaller than the coefficient of linear expansion α1 of the first carrier below the glass transition temperature. In this case, even if the thickness of the first carrier is reduced by grinding or the like, changes in the amount of warping can be suppressed.

[0023]

[15] In any of the semiconductor device manufacturing methods described in [8] to

[14] above, the coefficient of linear expansion α1 below the glass transition temperature of the second carrier may be 2 to 5 ppm / K. In this case, the coefficient of linear expansion of the substrate and the coefficient of linear expansion of the second carrier become equal, so the increase in warping when a substrate with a small coefficient of linear expansion is thinned can be reliably prevented by the second carrier.

[0024]

[16] Any of the semiconductor device manufacturing methods described in [8] to

[15] above may further include the steps of: removing the second carrier and then separating the laminate including the substrate and the sealing material layer into individual pieces; and arranging the separated semiconductor components on the second substrate and mounting them by heating. In this case, a semiconductor device using semiconductor components with reduced warping can be easily manufactured.

[0025]

[17] The disclosure relates to another aspect, a carrier, which is a first carrier used in any of the semiconductor device manufacturing methods described in [1] to

[16] above. In this case, warping of the semiconductor device can be reduced by the simple means of a first carrier.

[0026]

[18] In the carrier described in

[17] above, the first carrier is preferably a glass carrier having a coefficient of linear expansion α1 below the glass transition temperature of 0 to 20 ppm / K and an elastic modulus of 5 to 100 GPa at room temperature. In this case, the first carrier can reliably reduce the warping of the semiconductor device.

[0027]

[19] The disclosure further relates to another aspect of a sealing material, which is used in a method for manufacturing any of the semiconductor devices described in [1] to

[18] above.

[0028]

[20] In the sealing material described in

[19] above, the coefficient of linear expansion α1 below the glass transition temperature of the sealing material may be 1 to 30 ppm / K. In this case, the warping of the semiconductor device can be reduced.

[0029] According to this disclosure, warping of semiconductor devices can be reduced.

[0030] Figures 1(a) to 1(e) are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment. Figures 2(a) to 2(d) are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment, illustrating each step performed after the step shown in Figure 1(e). Figures 3(a) to 3(c) are cross-sectional views illustrating a first modified example of the method for manufacturing a semiconductor device according to one embodiment, illustrating each step performed after the step shown in Figure 1(e). Figures 4(a) to 4(c) are cross-sectional views illustrating a second modified example of the method for manufacturing a semiconductor device according to one embodiment, illustrating each step performed after the step shown in Figure 1(c). Figures 5(a) to 5(c) are cross-sectional views illustrating a second modified example of the method for manufacturing a semiconductor device according to one embodiment, illustrating each step performed after the step shown in Figure 4(c). Figures 6(a) and 6(b) are cross-sectional views illustrating a second modified example of the method for manufacturing a semiconductor device according to one embodiment, illustrating each step performed after the step shown in Figure 4(c).

[0031] The embodiments of this disclosure will be described in detail below with reference to the drawings. In the following description, the same or corresponding parts will be denoted by the same reference numerals, and redundant descriptions will be omitted. Furthermore, unless otherwise specified, positional relationships such as top, bottom, left, and right will be based on the positional relationships shown in the drawings. Moreover, the dimensional ratios in the drawings are not limited to those shown.

[0032] In this specification, the term "layer" includes not only structures that are formed across the entire surface when observed in a plan view, but also structures that are formed in only a part of the surface. In this specification, the term "process" includes not only independent processes, but also processes that cannot be clearly distinguished from other processes, as long as their intended function is achieved.

[0033] In this specification, numerical ranges indicated using "~" represent a range that includes the numbers before and after "~" as the minimum and maximum values, respectively. In numerical ranges described in stages in this specification, the upper or lower limit of one stage of the numerical range may be replaced with the upper or lower limit of another stage of the numerical range. In numerical ranges described in this specification, the upper or lower limit of that numerical range may be replaced with the values ​​shown in the examples.

[0034] A method for manufacturing a semiconductor device according to one embodiment will be described with reference to Figures 1 and 2. In this semiconductor device manufacturing method, as shown in Figure 1(a), first, a substrate 10 is prepared. The substrate 10 is, for example, a silicon wafer. The thickness of the substrate 10 may be, for example, 0.1 mm or more and 0.8 mm or less. If the substrate 10 is a glass substrate, the thickness of the substrate 10 may be 2 mm or less. The substrate 10 is, for example, a disc-shaped member, and the diameter of the substrate 10 may be, for example, 300 mm. The substrate 10 may also be a rectangular panel shape. If the substrate 10 is a silicon wafer, the coefficient of linear expansion of the substrate 10 may be, for example, 2 to 5 ppm / K, and for example, 3 ppm / K.

[0035] A first carrier 20 is prepared. The first carrier 20 is, for example, a glass carrier. The thickness of the first carrier 20 may be, for example, 0.1 mm or more and 1.5 mm or less, and may be 0.7 mm or 1.1 mm. The ratio of the thickness of the first carrier 20 to the thickness of the sealing material layer 40, which will be described later, is preferably 0.3 or more and 1.5 or less, and more preferably 0.7 or more and 1.2 or less. The first carrier 20 has the same shape as the planar shape of the substrate 10, and is, for example, a disc-shaped member, and the diameter of the first carrier 20 may be, for example, 300 mm. The first carrier 20 may also be a rectangular panel shape.

[0036] The coefficient of linear expansion α1 of the first carrier 20 below the glass transition temperature Tg is preferably, for example, 0 to 25 ppm / K, more preferably 1 to 20 ppm / K, and may be 3 ppm / K or 12 ppm / K. Furthermore, the modulus of elasticity of the first carrier 20 at room temperature (20°C) is preferably, for example, 5 to 100 GPa.

[0037] Once the substrate 10 and the first carrier 20 are prepared, the first carrier 20 is attached to the first surface 11 of the substrate 10, as shown in Figures 1(a) and 1(b). This attachment may be done using an adhesive sheet for temporary fixing, or by using an adhesive that firmly adheres the first carrier 20 to the substrate 10.

[0038] Once the first carrier 20 is attached to the substrate 10, a plurality of semiconductor chips 30 (at least one semiconductor chip) are mounted on the second surface 12 of the substrate 10, as shown in Figure 1(c). While it is preferable that the first carrier 20 is attached to the substrate 10 before this mounting, the first carrier 20 may be attached to the substrate 10 after the plurality of semiconductor chips 30 have been mounted.

[0039] When the semiconductor chip 30 is mounted, as shown in Figure 1(d), the semiconductor chip 30 is sealed with a sealing material on the second surface 12 of the substrate 10 to which the first carrier 20 is attached, forming a sealing layer 40. This sealing ensures that the entire semiconductor chip 30 is located within the sealing layer 40. The sealing material used here is one of the various sealing materials used for sealing semiconductor packages. The coefficient of linear expansion α1 of the sealing material forming the sealing layer below the glass transition temperature Tg may be, for example, 1 to 30 ppm / K, 5 to 28 ppm / K, or 10 to 25 ppm. The coefficients of linear expansion of the sealing material and the first carrier 20 may be approximately the same at a certain temperature (e.g., the sealing temperature).

[0040] The thickness of the sealing layer 40 may be, for example, 0.3 mm to 1.1 mm, and may be 0.8 mm as an example. The thickness of the sealing layer 40 may be the same as that of the first carrier 20. The sealing layer 40 has the same shape as the planar shape of the substrate 10, for example, it is a disc-shaped layer. However, for sealing purposes, the sealing layer 40 may be slightly smaller (by a few mm) than the outer circumference of the substrate 10, and the diameter of the sealing layer 40 may be 297 mm as an example. If the first carrier 20 etc. is panel-shaped, the sealing layer 40 may also be rectangular panel-shaped.

[0041] Once the semiconductor chip 30 is sealed with the sealing material, the surface 41 of the sealing material layer 40 is ground using CMP or the like, as shown in Figure 1(e), to form the sealing material layer 45. This grinding exposes the upper surface 31 of the semiconductor chip 30 from the surface 41 of the sealing material layer 45. The thickness of the sealing material layer 45 after grinding may be 0.2 mm to 1 mm or less, and for example, a thickness of about 100 μm may be ground away.

[0042] When the sealing material layer 40 is ground to become the sealing material layer 45, as shown in (a) of FIG. 2, the second carrier 50 is attached on the sealing material layer 45 on the side opposite to the first carrier 20. The attachment of the second carrier 50 is performed by various adhesives (for example, adhesives manufactured by Tokyo Ohka Kogyo Co., Ltd., 3M Co., Ltd., and Nitto Denko Corporation). The second carrier 50 is, for example, a glass carrier. The thickness of the second carrier 50 may be, for example, 0.3 mm to 1.1 mm, and as an example, it may be 0.7 mm or 1.0 mm. The thickness of the second carrier 50 may be equivalent to the thickness of the first carrier 20. The second carrier 50 has the same shape as the planar shape of the substrate 10 and is, for example, a disk-shaped member. As an example, the diameter of the second carrier 50 may be 300 mm. The second carrier 50 may have a rectangular panel shape.

[0043] The linear expansion coefficient α1 of the second carrier 50 below the glass transition temperature Tg is preferably, for example, 0 to 10 ppm / K, and more preferably 1 to 6 ppm / K. The linear expansion coefficient of the second carrier 50 below the glass transition temperature Tg is preferably smaller than the linear expansion coefficient of the first carrier below the glass transition temperature Tg, and may be in the range of -3 ppm / K to 3 ppm / K, or -1 ppm / K to 1 ppm / K with respect to the linear expansion coefficient of the substrate 10 below the glass transition temperature Tg. Also, the elastic modulus of the second carrier 50 at room temperature (20°C) is preferably, for example, 5 to 100 GPa.

[0044] When the second carrier 50 is attached to the sealing material layer 45, as shown in (b) of FIG. 2, the first carrier 20 is separated from the substrate 10 by peeling. The separated first carrier 20 may be reused, such as by attaching it to another substrate 10. That is, it may be reused as the first carrier 20 shown in (a) of FIG. 1. However, the separated first carrier 20 may be reused in other manufacturing methods.

[0045] When the first carrier 20 is separated, as shown in (c) of FIG. 2, a protective material 60 may be injected by an injector C to the outer periphery of the encapsulant layer 40. As described above, the encapsulant layer 40 is slightly smaller than the outer peripheries of the substrate 10 and the second carrier 50 that are attached to both the upper and lower surfaces, and a gap S is formed. By filling the gap S with the protective material 60, it is possible to prevent cracks from occurring at the outer peripheral ends of the substrate 10 and the like. The protective material 60 may be a paste-like curable material, and for example, it may be a resin composition such as a capillary underfill (CUF) material, a liquid type encapsulant, a dam material, an edge bond material, or the like. The injected protective material 60 may be cured after injection. Note that it may not be necessary to inject the protective material 60 to the outer periphery of the encapsulant layer 40.

[0046] Subsequently, as shown in (d) of FIG. 2, the first surface 11 of the substrate 10 is ground. This grinding is performed using a grinder G or the like. Thereby, the substrate 10, which is a silicon wafer or the like, is thinned to become the substrate 15. Thereafter, the second carrier 50 is separated by peeling or the like.

[0047] As described above, a semiconductor device 100 (laminated body) having the substrate 15, the semiconductor chip 30, and the encapsulant layer 45 is manufactured. The semiconductor device 100 may be further separated into individual pieces (semiconductor members) to manufacture individual semiconductor devices (semiconductor devices). In this case, the separated semiconductor members are arranged on a wiring substrate (another substrate), heated by reflow or the like for mounting, and made into semiconductor devices.

[0048] [First Modified Example] Here, referring to FIG. 3, a first modified example of the manufacturing method of the semiconductor device according to the present embodiment will be described. In the manufacturing method according to the first modified example, the same steps as those shown in (a) to (e) of FIG. 1 are performed, and by these steps, a laminated body including the substrate 10, the first carrier 20, a plurality of semiconductor chips 30, and the encapsulant layer 45 is formed. When this laminated body is formed, as shown in (a) of FIG. 3, a second carrier 50 is attached on the encapsulant layer 40 on the side opposite to the first carrier 20. The second carrier 50 can be the same as that used in the above-described embodiment.

[0049] Once the second carrier 50 is attached, protective material 60 may be injected around the outer periphery of the sealing material layer 45 using an injection tool C, as shown in Figure 3(b). By sealing the gap S with protective material 60, cracks can be prevented from occurring at the outer edge of the substrate 10. The same protective material 60 used in the above-described embodiment can be used.

[0050] Next, as shown in Figure 3(c), the first carrier 20 is ground. This grinding is performed using a grinder G or the like. In the manufacturing method according to the first modified example, the first carrier 20 is removed from the substrate 10 by grinding. Furthermore, in the manufacturing method according to the first modified example, the first surface 11 of the substrate 10 is further ground using a grinder G or the like. As a result, the substrate 10, which is a silicon wafer or the like, is thinned to become a substrate 15. After that, the second carrier 50 is separated by peeling or the like.

[0051] As described above, a semiconductor device 100 having a substrate 15, a semiconductor chip 30, and a sealing material layer 45 can be manufactured by the manufacturing method according to the first modified example. Of course, the semiconductor device 100 may be further divided into individual pieces to manufacture individual semiconductor devices (semiconductor devices).

[0052] [Second Modification] Next, a second modification of the method for manufacturing a semiconductor device according to this embodiment will be described with reference to Figure 4. In the manufacturing method according to the second modification, the same steps as those shown in Figures 1(a) to 1(c) are performed to form a laminate comprising a substrate 10, a first carrier 20, and a plurality of semiconductor chips 30. Once this laminate is formed, as shown in Figure 4(a), the semiconductor chips 30 are sealed with a sealing material on the second surface 12 of the substrate 10 to which the first carrier 20 is attached, forming a sealing material layer 40A. This sealing ensures that not only the semiconductor chips 30, but also the substrate 10 and the first carrier 20 are entirely contained within the sealing material layer 40A. This sealing is known as full molding. The sealing material used here can be the same as that used in the embodiments described above.

[0053] Once the encapsulating layer 40A is formed, the outer periphery of the encapsulating layer 40A is cut off using a dicer D or the like, as shown in Figure 4(b). This cutting process exposes the outer periphery surfaces of the substrate 10 and the first carrier 20. As a result, the encapsulating layer 40A becomes a encapsulating layer 42A that mainly encapsulates the multiple semiconductor chips 30 on the substrate 10. The outer periphery surface of the cut-off encapsulating layer 42A and the outer periphery surfaces of the substrate 10 and the first carrier 20 may be flush.

[0054] Once the encapsulating layer 42A is formed, as shown in Figure 4(c), the encapsulating layer 42A is ground using CMP or the like to form the encapsulating layer 45A. This grinding exposes the upper surface 31 of the semiconductor chip 30 from the surface 41A of the encapsulating layer 45A. The thickness of the encapsulating layer 45A after grinding may be 0.2 mm or more and 1 mm or less, and for example, a thickness of about 100 μm may be ground away.

[0055] When the sealing material layer 42A is ground down to become the sealing material layer 45A, the second carrier 50 is attached to the sealing material layer 45A on the side opposite to the first carrier 20, as shown in Figure 5(a). The second carrier 50 is, for example, a glass carrier, and the same type used in the above-described embodiment can be used.

[0056] Once the second carrier 50 is attached, the first carrier 20 is separated from the substrate 10 by peeling, as shown in Figure 5(b). The separated first carrier 20 may be reused by attaching it to another substrate 10 or the like.

[0057] Once the first carrier 20 is separated, the first surface 11 of the substrate 10 is ground, as shown in Figure 5(c). This grinding is performed using a grinder G or the like. As a result, the substrate 10, which is a silicon wafer or the like, is thinned to become a substrate 15. After that, the second carrier 50 is separated by peeling or the like.

[0058] As described above, a semiconductor device 100A having a substrate 15, a semiconductor chip 30, and a sealing material layer 45A is manufactured. Alternatively, the semiconductor device 1A may be further divided into individual pieces to manufacture individual semiconductor devices (semiconductor devices).

[0059] In the second modified method for manufacturing a semiconductor device, as shown in Figure 6(a), the second carrier 50 is attached to the sealing material layer 45A, and then, similar to the first modified method, the first carrier 20 may be ground off and removed as shown in Figure 6(b). This grinding is performed using a grinder G or the like, and the first carrier 20 is removed from the substrate 10 by grinding. Alternatively, the first surface 11 of the substrate 10 may be further ground using the grinder G or the like. This thins the substrate 10, which may be a silicon wafer or the like, and makes it a substrate 15. After that, the second carrier 50 is separated by peeling or the like. A semiconductor device 100A can also be obtained by this method.

[0060] In the semiconductor device manufacturing method according to this embodiment, the semiconductor chip 30 is sealed on a substrate 10 to which the first carrier 20 is attached. In this case, the first carrier 20 prevents warping caused by the sealing material layers 40, 45, 40A, and 45A, thereby reducing warping.

[0061] In the semiconductor device manufacturing method according to this embodiment, the first carrier 20 is a glass carrier. This allows for the reduction of shrinkage of the sealing material layers 40, 45, 40A, and 45A during sealing by utilizing the shrinkage of the glass when it returns to room temperature from heating, thereby reducing the warping of the semiconductor devices 100 and 100A. Furthermore, by utilizing the elastic modulus of the glass, the shrinkage of the sealing material layers 40, 45, 40A, and 45A during sealing can be reduced, thereby reducing the warping of the semiconductor devices 100 and 100A.

[0062] In the semiconductor device manufacturing method according to this embodiment, the coefficient of linear expansion α1 of the first carrier 20 below the glass transition temperature Tg is preferably 0 to 20 ppm / K. This allows for the reduction of shrinkage of the sealing material layers 40, 45, 40A, and 45A during sealing by utilizing the shrinkage of the glass, thereby reducing the warping of the semiconductor devices 100 and 100A.

[0063] In the semiconductor device manufacturing method according to this embodiment, the elastic modulus of the first carrier 20 at room temperature may be 5 to 100 GPa. This allows the high elastic modulus of glass to be utilized to suppress the shrinkage of the sealing material layers 40, 45, 40A, and 45A during sealing, thereby reducing the warping of the semiconductor devices 100 and 100A.

[0064] In the semiconductor device manufacturing method according to this embodiment, the ratio of the thickness of the first carrier 20 to the thickness of the sealing material layers 40, 45, 40A, and 45A may be 0.3 or more and 1.5 or less. As a result, since the thickness of the first carrier 20 and the sealing material layers are equivalent, the first carrier 20 can reliably prevent warping caused by the sealing material layers 40, 45, 40A, and 45A.

[0065] In the semiconductor device manufacturing method according to this embodiment, the coefficient of linear expansion α1 of the sealing material layers 40, 45, 40A, and 45A below the glass transition temperature Tg may be 1 to 30 ppm / K. This suppresses the shrinkage of the sealing material layers 40, 45, 40A, and 45A during sealing, and reduces the warping of the semiconductor devices 100 and 100A.

[0066] The semiconductor device manufacturing method according to this embodiment may further include a step of grinding the surface of the sealing material layer with the first carrier attached. Since the sealing material layers 40, 45, 40A, and 45A are reliably supported by the first carrier 20, the grinding accuracy of the sealing material layers 40, 45, 40A, and 45A can be improved.

[0067] The semiconductor device manufacturing method according to this embodiment further includes a step of attaching a second carrier 50 on the sealing material layers 40, 45, 40A, and 45A, on the side opposite to the first carrier 20. This makes it possible to prevent an increase in warping when the substrate is thinned by 10 using the second carrier 50 provided on the opposite side of the sealing material layers 40, 45, 40A, and 45A.

[0068] The semiconductor device manufacturing method according to this embodiment further includes a step of separating the first carrier 20 from the substrate 10 after attaching the second carrier 50 to the sealing material layers 40, 45, 40A, and 45A. This allows various treatments to be performed on the surface of the substrate 10 after the first carrier 20 has been separated.

[0069] The semiconductor device manufacturing method according to this embodiment may further include a step of reusing the separated first carrier 20. This allows the first carrier 20 to be reused. In the case of the first carrier 20 being a glass substrate such as a glass carrier, it is often expensive, and reuse can reduce manufacturing costs.

[0070] In the semiconductor device manufacturing method according to this embodiment, the first carrier 20 may be removed from the substrate 10 by grinding after the second carrier 50 has been attached to the sealing material layers 40, 45, 40A, and 45A. This allows the first carrier 20 to be bonded to the substrate 10 with a strong adhesive when it is attached. Therefore, the force (warpage) applied to the substrate 10 can be absorbed by the first carrier 20, and the warpage can be reliably reduced.

[0071] The method for manufacturing a semiconductor device according to this embodiment may further include a step of injecting a protective material 60 into the outer periphery of the sealing material layers 40, 45, 40A, and 45A between the substrate 10 and the second carrier 50. The outer periphery of the sealing material layer may be smaller than the outer periphery of the substrate, or the outer edge of the sealing material layer may be prone to chipping, which can cause cracks in the substrate 10, etc. Injecting the protective material 60 into the outer periphery of the sealing material layers 40, 45, 40A, and 45A can reduce the occurrence of cracks.

[0072] In the semiconductor device manufacturing method according to this embodiment, the coefficient of linear expansion α1 of the second carrier 50 below the glass transition temperature Tg may be smaller than the coefficient of linear expansion α1 of the first carrier 20 below the glass transition temperature Tg. This makes it possible to suppress changes in the amount of warping even if the thickness of the first carrier 20 is reduced by grinding or the like.

[0073] In the semiconductor device manufacturing method according to this embodiment, the coefficient of linear expansion α1 of the second carrier 50 below the glass transition temperature Tg may be 2 to 5 ppm / K. As a result, the coefficient of linear expansion of the substrate 10 and the coefficient of linear expansion of the second carrier 50 become equal, and the second carrier 50 can reliably prevent an increase in warping when the substrate 10, which has a small coefficient of linear expansion, is thinned.

[0074] The method for manufacturing a semiconductor device according to this embodiment may further include the steps of: removing the second carrier 50 and then separating the laminate, which includes the substrate 10 and the sealing material layers 40, 45, 40A, and 45A, into individual pieces; and arranging the separated semiconductor components on the second substrate and mounting them by heating. This makes it possible to easily manufacture a semiconductor device using semiconductor components with reduced warping.

[0075] Although embodiments of the present disclosure have been described above, the present invention is not limited to the embodiments described above, and modifications may be made as appropriate without departing from the spirit of the invention.

[0076] 10, 15... Substrate, 11... First surface, 12... Second surface, 20... First carrier, 30... Semiconductor chip, 40, 40A, 42A, 45, 45A... Encapsulation layer, 41, 41A... Surface, 50... Second carrier, 60... Protective material, 100, 100A... Semiconductor device.

Claims

1. A method for manufacturing a semiconductor device, comprising: a step of attaching a first carrier to a first surface of a substrate; a step of mounting at least one semiconductor chip to a second surface of the substrate; and a step of sealing the semiconductor chip on the second surface of the substrate to which the first carrier has been attached to form a sealing material layer.

2. The method for manufacturing a semiconductor device according to claim 1, wherein the first carrier is a glass carrier.

3. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein the coefficient of linear expansion α1 of the first carrier below the glass transition temperature is 0 to 20 ppm / K.

4. The method for manufacturing a semiconductor device according to any one of claims 1 to 3, wherein the elastic modulus of the first carrier at room temperature is 5 to 100 GPa.

5. The method for manufacturing a semiconductor device according to any one of claims 1 to 4, wherein the ratio of the thickness of the first carrier to the thickness of the sealing material layer is 0.3 or more and 1.5 or less.

6. The method for manufacturing a semiconductor device according to any one of claims 1 to 5, wherein the coefficient of linear expansion α1 below the glass transition temperature of the sealing material layer is 1 to 30 ppm / K.

7. A method for manufacturing a semiconductor device according to any one of claims 1 to 6, further comprising the step of grinding the surface of the sealing material layer with the first carrier attached.

8. A method for manufacturing a semiconductor device according to any one of claims 1 to 7, further comprising the step of attaching a second carrier to the sealing material layer on the side opposite to the first carrier.

9. The method for manufacturing a semiconductor device according to claim 8, further comprising the step of separating the first carrier from the substrate after attaching the second carrier to the sealing material layer.

10. The method for manufacturing a semiconductor device according to claim 9, further comprising the step of reusing the separated first carrier.

11. The method for manufacturing a semiconductor device according to claim 8, further comprising the step of grinding off the first carrier from the substrate after the second carrier has been attached to the sealing material layer.

12. A method for manufacturing a semiconductor device according to any one of claims 8 to 11, further comprising the step of injecting a protective material onto the outer periphery of the sealing material layer between the substrate and the second carrier.

13. The method for manufacturing a semiconductor device according to any one of claims 8 to 12, wherein the second carrier is a glass carrier.

14. The method for manufacturing a semiconductor device according to any one of claims 8 to 13, wherein the coefficient of linear expansion α1 of the second carrier below the glass transition temperature is smaller than the coefficient of linear expansion α1 of the first carrier below the glass transition temperature.

15. The method for manufacturing a semiconductor device according to any one of claims 8 to 14, wherein the coefficient of linear expansion α1 of the second carrier below the glass transition temperature is 2 to 5 ppm / K.

16. A method for manufacturing a semiconductor device according to any one of claims 8 to 15, further comprising the steps of: separating the laminate including the substrate and the sealing material layer after removing the second carrier; and arranging the separated semiconductor components on another substrate and mounting them by heating.

17. A carrier which is a first carrier used in a method for manufacturing a semiconductor device according to any one of claims 1 to 16.

18. The carrier according to claim 17, wherein the first carrier is a glass carrier having a coefficient of linear expansion α1 below the glass transition temperature of 0 to 20 ppm / K and an elastic modulus of 5 to 100 GPa at room temperature.

19. A sealing material used in a method for manufacturing a semiconductor device according to any one of claims 1 to 16.

20. The sealing material according to claim 19, wherein the coefficient of linear expansion α1 of the sealing material below the glass transition temperature is 1 to 30 ppm / K.

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