Power conversion device

Abstract

A power conversion device (100) comprises: a first conversion circuit unit (20) and a second conversion circuit unit (30); and a plurality of current sensors (41-43). The first conversion circuit unit (20) has a first parallel section (28) branching from a power supply connection line (11) and converts a voltage between the first parallel section (28) and an inverter connection line (12). The second conversion circuit unit (30) has a second parallel section (38) that branches from the power supply connection line (11) in parallel with the first parallel section (28), and converts a voltage between the second parallel section (38) and the inverter connection line (12). The first current sensor (41) detects a first current (C1) flowing through the first parallel section (28). The second current sensor (42) detects a second current (C2) flowing through the second parallel section (38). The total current sensor (43) detects a pre-shunt current (Cb) that is the sum of the first current (C1) and the second current (C2).

Description

Power conversion device Cross-reference to related applications

[0001] This application is based on Japanese Patent Application No. 2024-177275 filed in Japan on October 9, 2024, and the content of the base application is incorporated herein by reference in its entirety.

[0002] The disclosure according to this specification relates to a power conversion device.

[0003] Patent Document 1 discloses, as a type of power conversion device, a vehicle control device that boosts the power of a battery by a first converter unit and a second converter unit and supplies it to the load side. This control device is provided with a first current sensor and a second current sensor that measure a first current flowing through the first converter unit, and a third current sensor that measures a second current flowing through the second converter unit. Then, the failure detection unit detects which current sensor has failed from the current values measured by each current sensor.

[0004] Japanese Unexamined Patent Application Publication No. 2023-68881

[0005] In the control device of Patent Document 1, all three current sensors are configured to detect the current in a parallel section where they branch off in parallel toward each converter unit. Therefore, the total current obtained by adding the first current flowing through the first converter unit and the second current flowing through the second converter unit is not detected by the control device of Patent Document 1.

[0006] An object of the present disclosure is to provide a power conversion device capable of detecting, in a configuration including a plurality of conversion circuit units such as converter units, in addition to each current in the parallel section after branching, the current obtained by adding these currents.

[0007] To achieve the above objective, one disclosed embodiment is a power conversion device comprising: an input-side connection line electrically connected to the input side; an output-side connection line electrically connected to the output side; a first conversion circuit section having a first parallel section branching from the input-side connection line and converting voltage between the first parallel section and the output-side connection line; a second conversion circuit section having a second parallel section branching from the input-side connection line in parallel with the first parallel section and converting voltage between the second parallel section and the output-side connection line; a first current detection unit for detecting a first current flowing through the first parallel section; a second current detection unit for detecting a second current flowing through the second parallel section; and a total current detection unit for detecting a total current which is the sum of the first current and the second current.

[0008] In this embodiment, the first and second currents flowing through the first and second parallel sections, which branch in parallel with each other, are detected by the first current detection and second current detection units. In addition, the total current, which is the sum of the first and second currents, is also detected by the total current detection unit. Therefore, in a configuration with multiple conversion circuit units, it becomes possible to detect not only the currents in the parallel sections after branching, but also the sum of these currents.

[0009] Furthermore, the reference numbers in parentheses in the claims are merely examples of correspondences with specific configurations in the embodiments described later, and do not in any way limit the technical scope. In addition, combinations of claims not explicitly stated in the claims are also possible, provided that they do not cause any particular problems with the combination.

[0010] This is a circuit diagram showing the configuration of a power converter according to the first embodiment of this disclosure. This is a circuit diagram showing the configuration of a power converter. This is a diagram showing the configuration of a housing including a plurality of current sensors. This is a diagram showing the details of the current values ​​before and after current division that are compared in the fault determination unit. This is a flowchart showing the details of the fault determination process performed in the fault determination unit. This is a flowchart showing the details of the fault sensor discrimination process performed as a sub-process of the fault determination process. This is a diagram showing the configuration of a power converter according to the second embodiment of this disclosure. This is a cross-sectional view showing the configuration of current sensors provided in the parallel section.

[0011] Several embodiments will be described below with reference to the drawings. In each embodiment, the same reference numerals are used for corresponding components, and redundant explanations may be omitted. If only a part of the configuration is described in each embodiment, the configuration of other embodiments described earlier can be applied to the other parts of that configuration. Furthermore, in addition to the combinations of configurations explicitly stated in the description of each embodiment, configurations from multiple embodiments can be partially combined even if not explicitly stated, as long as there are no particular problems with the combination.

[0012] (First Embodiment) The power converter 100 according to the first embodiment of the present disclosure shown in Figures 1 and 2 is a vehicle control device used in an electric vehicle. The power converter 100 is mounted on an electric vehicle and connected to a battery 110 and a motor 120. The power converter 100 converts the DC power supplied from the battery 110 into AC power that can be used by the motor 120. The power converter 100 converts the AC power generated by the motor 120 into DC power for storage in the battery 110.

[0013] The battery 110 is an energy storage device that stores power to drive the electric vehicle. The battery 110 includes a rechargeable secondary battery such as a lithium-ion battery or a nickel-metal hydride battery. The battery 110 functions as a DC power source that supplies power to the motor 120. The battery 110 may be configured to be rechargeable by an external power source electrically connected to the electric vehicle.

[0014] Motor 120 is a three-phase brushless permanent magnet synchronous motor comprising a stator having three phase windings, U-phase, V-phase, and W-phase, and a rotor integrated with permanent magnets. Motor 120 may also be an induction motor or the like. Motor 120 functions as a drive source (electric motor) for driving the electric vehicle and efficiently converts the power supplied from the battery 110 into driving force. Motor 120 also functions as a generator during regenerative braking of the electric vehicle, enabling the recharging of the battery 110 with energy recovered by the use of regenerative braking.

[0015] [Configuration of the power converter] The power converter 100 is composed of a boost circuit 10, an inverter 70, and a power controller 80, etc.

[0016] The boost circuit 10 is located between the battery 110 and the inverter 70. The boost circuit 10 consists of a power supply connection line 11, an inverter connection line 12, a negative electrode connection line 13, a first conversion circuit section 20, a second conversion circuit section 30, a first current sensor 41, a second current sensor 42, and a total current sensor 43, etc.

[0017] The power connection line 11 and the inverter connection line 12 are positive-side power lines provided between the battery 110, which is the input side of the boost circuit 10, and the inverter 70, which is the output side of the boost circuit 10. The power connection line 11 is electrically connected to the positive terminal of the battery 110. The power connection line 11 is formed by a busbar 52 (see Figure 3) capable of carrying a large current. The power supply voltage is applied to the power connection line 11 by the battery 110, and the current before it branches into the first current C1 and the second current C2 (hereinafter referred to as the pre-division current Cb) flows through it. The inverter connection line 12 is electrically connected to the positive side of the inverter 70. The current after the first current C1 and the second current C2 merge (hereinafter referred to as the post-merging current Ca) flows through the inverter connection line 12.

[0018] The negative electrode connection line 13 is a power line (N path) on the negative electrode side, located between the battery 110 and the inverter 70. A current equivalent to the pre-division current Cb and the post-merging current Ca (hereinafter referred to as the N path current Cn) flows through the negative electrode connection line 13. The negative electrode connection line 13 includes a power supply side section 13a and an inverter side section 13b. The power supply side section 13a is electrically connected to the negative electrode terminal of the battery 110. A smoothing capacitor 16 is provided between the power supply connection line 11 and the power supply side section 13a to stabilize the voltage between them. The inverter side section 13b is electrically connected to the negative electrode side of the inverter 70.

[0019] The first conversion circuit 20 and the second conversion circuit 30 function as DC-DC converters, converting a DC voltage between the battery 110 and the motor 120 to another DC voltage. The first conversion circuit 20 and the second conversion circuit 30 are connected in parallel to each other to the battery 110 and the inverter 70. The first conversion circuit 20 and the second conversion circuit 30 perform power conversion operations, including boost and buck operations, by rapidly repeating charging and discharging periods. Through boost operation, the first conversion circuit 20 and the second conversion circuit 30 boost the power supply voltage supplied from the battery 110 to a predetermined value and supply it to the inverter 70. Also, through buck operation, the first conversion circuit 20 and the second conversion circuit 30 lower the regenerative voltage supplied from the inverter 70 to a predetermined value and supply it to the battery 110.

[0020] The first conversion circuit section 20 includes two switching elements 21 and 22 and a reactor 23, and an inter-element connection section 25, a positive-side connection section 26, a negative-side connection section 27, and a first parallel section 28 connected to them. The switching elements 21 and 22 are composed of transistors and freewheeling diodes, etc. The transistors are MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors), etc. The switching elements 21 and 22 are connected in series with each other via the inter-element connection section 25. Switching element 21 has an upper arm configuration located on the positive-side (high-potential) side. Switching element 21 is electrically connected to the inverter connection line 12 by the positive-side connection section 26. Switching element 22 has a lower arm configuration located on the negative-side (low-potential) side. Switching element 22 is electrically connected to the negative-side connection line 13 by the negative-side connection section 27.

[0021] The reactor 23 is mainly composed of copper windings. The reactor 23 stores and releases energy. The reactor 23 is located in the middle of the first parallel section 28. The first parallel section 28 is a power line that branches off from the power supply connection line 11 and connects to the inter-element connection section 25. The first parallel section 28, like the power supply connection line 11, is formed by a busbar 51 (see Figures 3 and 8) capable of carrying a large current. The first current C1 flows through the reactor 23 and the first parallel section 28.

[0022] During the charging period of the first conversion circuit 20, the switching element 21 is in the off state and the switching element 22 is in the on state, and energy from the input side is stored in the reactor 23. On the other hand, during the discharge period of the first conversion circuit 20, the switching element 21 is in the on state and the switching element 22 is in the off state, and the energy stored in the reactor 23 is released to the output side.

[0023] The second conversion circuit section 30 includes two switching elements 31 and 32 and a reactor 33, and an inter-element connection section 35, a positive-side connection section 36, a negative-side connection section 37, and a second parallel section 38 connected to them. The switching elements 31 and 32 have substantially the same configuration as the switching elements 21 and 22 of the first conversion circuit section 20. The switching elements 31 and 32 are connected in series with each other via the inter-element connection section 35. Switching element 31 has an upper arm configuration located on the positive-side. Switching element 31 is electrically connected to the inverter connection line 12 via the positive-side connection section 36. Switching element 32 has a lower arm configuration located on the negative-side. Switching element 32 is electrically connected to the negative-side connection line 13 via the negative-side connection section 37.

[0024] The reactor 33 has substantially the same configuration as the reactor 23 of the first conversion circuit section 20 and stores and releases energy. The reactor 33 is located in the middle of the second parallel section 38. The second parallel section 38 is a power line that branches off from the power supply connection line 11 in parallel with the first parallel section 28 and is connected to the inter-element connection section 35. The second parallel section 38, like the power supply connection line 11 and the first parallel section 28, is formed by a busbar 53 (see Figures 3 and 8) capable of carrying a large current. The second current C2 flows through the reactor 33 and the second parallel section 38.

[0025] During the charging period of the second conversion circuit 30, the switching element 31 is in the off state and the switching element 32 is in the on state, and energy from the input side is stored in the reactor 33. On the other hand, during the discharge period of the second conversion circuit 30, the switching element 31 is in the on state and the switching element 32 is in the off state, and the energy stored in the reactor 33 is released to the output side. As will be described later, the cycle in which the second conversion circuit 30 repeats the charging and discharging periods is shifted by 180° with respect to the cycle in which the first conversion circuit 20 repeats the charging and discharging periods.

[0026] The first current sensor 41, the second current sensor 42, and the total current sensor 43 are mainly composed of a Hall IC 61 (see Figure 3). Each current sensor 41 to 43 detects the current flowing through the boost circuit 10 in real time and outputs the detection result (current value) to the power controller 80. The detection results of each current sensor 41 to 43 are used to optimize the power supply to the inverter 70 and the motor 120.

[0027] The first current sensor 41 and the second current sensor 42 are located in the parallel section HB (see Figure 2), which branches off from the power supply connection line 11, and individually measure the current after it has been divided into each path. Specifically, the first current sensor 41 is provided in the first parallel section 28. The first current sensor 41 is located on the element-to-element connection section 25 side with respect to the reactor 23. The first current sensor 41 detects the first current C1 flowing through the first parallel section 28 and the reactor 23. The first current sensor 41 outputs the real-time current value (hereinafter referred to as the first current value Iv1) of the first current C1 to the power controller 80. The first current value Iv1 is used by the power controller 80 to control the first conversion circuit section 20.

[0028] The second current sensor 42 is located in the second parallel section 38. The second current sensor 42 is positioned on the element-to-element connection section 35 side relative to the reactor 33. The second current sensor 42 detects the second current C2 flowing through the second parallel section 38 and the reactor 33. The second current sensor 42 outputs the real-time current value (hereinafter referred to as the second current value Iv2) of the second current C2 to the power controller 80. The second current value Iv2 is used by the power controller 80 to control the second conversion circuit section 30.

[0029] The total current sensor 43 is installed on the power supply connection line 11. The total current sensor 43 detects the pre-division current Cb flowing through the power supply connection line 11. The total current sensor 43 outputs the real-time current value (hereinafter referred to as the integrated current value Ivt) measured from the pre-division current Cb to the power controller 80.

[0030] The inverter 70 is located between the boost circuit 10 and the motor 120. The inverter 70 is a drive circuit that converts the DC power supplied from the boost circuit 10 into three-phase AC power and drives the motor 120. The inverter 70 consists of a positive power line 71, a negative power line 72, a group of switching elements on the upper and lower arms, output lines 73 connected to each of the three phases of the motor 120, and a plurality of inverter current sensors (hereinafter referred to as INV current sensors 75), etc.

[0031] The positive power line 71 is electrically connected to the inverter connection line 12. The negative power line 72 is electrically connected to the inverter side section 13b. A smoothing capacitor 18 is provided between the positive power line 71 and the negative power line 72 to stabilize the voltage between them. This smoothing capacitor 18 may be provided between the inverter connection line 12 and the inverter side section 13b as part of the boost circuit 10 configuration.

[0032] The INV current sensor 75, like the other current sensors 41-43, is primarily composed of a Hall IC 61 (see Figure 3). One INV current sensor 75 is provided for each of the multiple output lines 73. The output lines 73 are formed by busbars 54-56 (see Figure 3) capable of carrying large currents. The INV current sensor 75 detects the current flowing through the output lines 73 in real time and outputs the detection result (current value) to the power controller 80.

[0033] The power controller 80 is an on-board ECU (Electronic Control Unit) that comprehensively controls the powertrain system of an electric vehicle. The power controller 80 controls the boost circuit 10 and the inverter 70 based on information acquired from multiple sensors, including current sensors 41-43 and 75. The power controller 80 is equipped with a conversion control unit 81, an inverter control unit 82, and a fault detection unit 83.

[0034] The power controller 80 is composed of a microcontroller primarily consisting of a CPU (Central Processing Unit) coupled with RAM (Random Access Memory). In this configuration, the conversion control unit 81, the inverter control unit 82, and the fault detection unit 83 are functional units built based on programs stored in storage. The storage contains conversion control programs, circuit monitoring programs, and the like. The power controller 80 may also be composed of hardware circuits including an SoC, ASIC, and FPGA. SoC stands for System on Chip, ASIC stands for Application Specific Integrated Circuit, and FPGA stands for Field-Programmable Gate Array.

[0035] The conversion control unit 81 controls the power conversion operation of the first conversion circuit unit 20 and the second conversion circuit unit 30 by switching the on and off states of each switching element 21, 22, 31, and 32. Specifically, the conversion control unit 81 achieves voltage boosting from the battery 110 to the motor 120 and voltage reduction from the motor 120 to the battery 110 by adjusting the ratio of the on time of each switching element 21, 22, 31, and 32 using PWM (Pulse Width Modulation) control. The conversion control unit 81 optimizes the on and off timing of each switching element 21, 22, 31, and 32 by using current feedback control to bring the current values ​​Iv1 and Iv2 obtained from current sensors 41 and 42 closer to their respective target currents. As described above, the conversion control unit 81 operates the on and off timing of the switching elements 21 and 22 of the first conversion circuit unit 20 with a 180° shift relative to the on and off timing of the switching elements 31 and 32 of the second conversion circuit unit 30. As a result, the ripples in the output currents of each conversion circuit section 20 and 30 cancel each other out, so the ripple in the entire boost circuit 10 is significantly reduced.

[0036] The inverter control unit 82 controls the rotational speed and torque of the motor 120's rotor by switching the on and off states of each switching element. More specifically, the inverter control unit 82 monitors the rotor's rotational position and the current flowing through each phase in real time. The inverter control unit 82 performs current feedback control to bring the current value measured by the INV current sensor 75 closer to a target current set according to the torque command value. The inverter control unit 82 adjusts the on-time ratio of each switching element using PWM control to achieve optimal power supply according to the rotor's rotational position so that the torque of the motor 120 matches the torque command value.

[0037] The fault determination unit 83 monitors the first current value Iv1, the second current value Iv2, and the integrated current value Ivt, and detects abnormalities occurring in the first conversion circuit unit 20 and the second conversion circuit unit 30. Specifically, the fault determination unit 83 determines at least one fault in the first current sensor 41, the second current sensor 42, and the total current sensor 43 based on a comparison of the first current value Iv1, the second current value Iv2, and the integrated current value Ivt.

[0038] More specifically, the fault detection unit 83 compares the sum of the first current value Iv1 and the second current value Iv2 with the integrated current value Ivt (see Figure 4). The sum of the first current value Iv1 and the second current value Iv2 is the sum of multiple sensor measurements taken in the parallel section HB after the current division. On the other hand, the integrated current value Ivt is the sensor measurement taken in the power supply connection line 11 before the current division. The fault detection unit 83 calculates the difference between the sum of the first current value Iv1 and the second current value Iv2 and the integrated current value Ivt. If the calculated difference value VD exceeds a predetermined value (hereinafter referred to as the fault detection threshold ThF), the fault detection unit 83 determines that at least one of the current sensors 41 to 43 is faulty.

[0039] The failure detection threshold ThF is defined, for example, based on the measurement error Em1 occurring in the first current sensor 41 and the measurement error Em2 occurring in the second current sensor 42. The failure detection threshold ThF may also be defined by further considering the measurement error occurring in the total current sensor 43. The failure detection threshold ThF may be the sum of the maximum measurement errors Em1 and Em2 expected during measurement, or it may be the square root of the sum of the squares of the maximum expected measurement errors Em1 and Em2.

[0040] If the fault detection unit 83 determines that the total value and integrated current value Ivt deviate beyond the fault detection threshold ThF and that at least one current sensor 41 to 43 is faulty, it works in conjunction with the conversion control unit 81 to switch the boost circuit 10 to fail-safe mode. In fail-safe mode, the conversion control unit 81 continues the power conversion operations of the first conversion circuit unit 20 and the second conversion circuit unit 30, respectively, using the outputs of multiple (two) normal current sensors that are not faulty.

[0041] Furthermore, the fault detection unit 83 determines that at least one of the current sensors 41 to 43 is faulty if the difference value VD is equal to or greater than the fault detection threshold ThF. In addition, the direction of the first current C1, the second current C2, and the current before diversion Cb is defined as positive when directed from the battery 110 (input side) to the inverter 70 (output side), and negative when directed from the inverter 70 to the battery 110. That is, the fault detection unit 83 acquires the output of current sensors 41 to 43 that measure current in the positive direction (see Figure 4) as a positive value, and acquires the output of current sensors 41 to 43 that measure current in the negative direction as a negative value.

[0042] <Current Sensor Mounting Structure> Next, the specific mounting configuration of the multiple current sensors 41-43 and 75 will be explained in detail based on Figure 3.

[0043] The plurality of current sensors 41 to 43 provided in the boost circuit 10 and the plurality of INV current sensors 75 provided in the inverter 70 are integrated into one housing 60. The housing 60 is one of the numerous sub - assembly bodies that make up the power conversion device 100. The housing 60 includes a sensor housing 58 and a sensor substrate 59 that holds various Hall ICs 61.

[0044] The sensor housing 58 is a terminal block that serves as the base for the current sensors 41 to 43 and 75. A number of busbars 51 to 56 and a number of core parts 63 are provided in the sensor housing 58. The busbars 51 to 56 are embedded in the resin body of the sensor housing 58 by insert molding. One end of each of the busbars 51 to 56 is exposed on the outer surface of the sensor housing 58 as a connection terminal.

[0045] The core parts 63 are formed in an annular or polygonal - annular shape, or a cylindrical or polygonal - cylindrical shape by a magnetic material with a high magnetic permeability such as ferrite and silicon steel. The core parts 63 are provided one by one around each of the busbars 51 to 56 so as to surround the periphery of the busbars 51 to 56. At least one gap 64 is formed in the core parts 63. The Hall IC 61 is accommodated in the gap 64. The core parts 63 concentrate the magnetic field generated by the current in the busbars 51 to 56 and apply the amplified magnetic field to the Hall IC 61 disposed in the gap 64.

[0046] The sensor substrate 59 is a rigid printed wiring board made of paper phenolic or glass epoxy. A number of Hall ICs 61 that constitute the current sensors 41 to 43 and 75 are mounted on one mounting surface of the sensor substrate 59. That is, the Hall ICs 61 of the current sensors 41 to 43 included in the boost circuit 10 and the Hall ICs 61 of the INV current sensor 75 included in the inverter 70 are held on one sensor substrate 59. The sensor substrate 59 is held by the sensor housing 58. The plurality of Hall ICs 61 may be arranged in a row on the mounting surface of the sensor substrate 59, or may be arranged alternately on the mounting surface. The sensor substrate 59 is electrically connected to the main board of the power conversion device 100 and provides the sensor measurement values output from each of the current sensors 41 to 43 and 75 to the power controller 80 on the main board.

[0047] <Current Sensor Failure Determination Process> Next, the details of the failure determination process for monitoring the outputs of the current sensors 41 to 43 and detecting failures that occur in them will be described based on FIGS. 5 and 6, with reference to FIGS. 2 and 4. The failure determination process is started by the failure determination unit 83 in accordance with the start of the power conversion operation by the boost circuit 10. The failure determination process is repeatedly performed until the power conversion operation by the boost circuit 10 is completed.

[0048] In S11 of the failure determination process shown in FIG. 5, the failure determination unit 83 acquires the current values Iv1, Iv2, and Ivt output from the current sensors 41 to 43. In S12, the failure determination unit 83 compares the acquired current values before and after shunt. Specifically, the failure determination unit 83 calculates the difference value VD between the total value of the first current value Iv1 and the second current value Iv2 and the integrated current value Ivt. In S13, the failure determination unit 83 determines whether the difference value VD is less than or equal to the failure determination threshold ThF. When the difference value VD is less than or equal to the failure determination threshold ThF (S13: YES), the failure determination unit 83 determines that all of the current sensors 41 to 43 are normal. In this case, the failure determination unit 83 continues to monitor the current sensors 41 to 43 by repeating the processes of S11 to S13.

[0049] On the other hand, if the difference value VD exceeds the failure detection threshold ThF (S13: NO), the failure detection unit 83 performs a fault sensor discrimination process (see Figure 6) in S14. The fault sensor discrimination process is a sub-process in which the failure detection unit 83 determines which of the current sensors 41 to 43 has failed. In S15, based on the determination result of the fault sensor discrimination process, the failure detection unit 83 switches the power conversion operation by the conversion control unit 81 to fail-safe mode. The conversion control unit 81 continues the power conversion operation of the first conversion circuit unit 20 and the second conversion circuit unit 30 using the outputs of the two current sensors (normal detection unit) that are not faulty among the first current sensor 41, the second current sensor 42, and the total current sensor 43.

[0050] In the fault sensor detection process shown in Figure 6, the fault determination unit 83 performs a first test mode (S31) and a second test mode (S33) to identify the faulty current sensor. In the first test mode, of the first and second conversion circuits 20, only the first conversion circuit 20 performs the power conversion operation. In the first test mode, the power conversion operation of the second conversion circuit 30 is stopped. As a result, the second current C2 becomes zero, and the current before division Cb and the first current C1 become equal. In contrast, in the second test mode, of the first and second conversion circuits 30, only the second conversion circuit 30 performs the power conversion operation. In the second test mode, the power conversion operation of the first conversion circuit 20 is stopped. As a result, the first current C1 becomes zero, and the current before division Cb and the second current C2 become equal. The first and second test modes may each be performed once in the fault sensor detection process, or they may be repeated multiple times.

[0051] In S31 of the fault sensor detection process, the fault determination unit 83 operates the boost circuit 10 in first test mode. In S32, the fault determination unit 83 obtains the first current value Iv1 and the integrated current value Ivt measured in first test mode. Similarly, in S33, the fault determination unit 83 operates the boost circuit 10 in second test mode. In S34, the fault determination unit 83 obtains the second current value Iv2 and the integrated current value Ivt measured in second test mode.

[0052] In S35, the fault determination unit 83 compares the first current value Iv1 and the integrated current value Ivt measured in the first test mode. Specifically, the fault determination unit 83 determines whether the first current value Iv1 and the integrated current value Ivt deviate from each other by more than a predetermined value. The predetermined value is, for example, the maximum measurement error Em1 (see Figure 4) expected for the first current sensor 41. If the fault determination unit 83 determines that the difference between the two current values ​​Iv1 and Ivt is less than or equal to the predetermined value and that these current values ​​Iv1 and Ivt are approximately the same value (S35: YES), in S36, it compares the second current value Iv2 and the integrated current value Ivt measured in the second test mode.

[0053] In S36, the fault determination unit 83 determines whether the second current value Iv2 and the integrated current value Ivt are diverging from each other by more than a predetermined value. The predetermined value is, for example, the maximum measurement error Em2 (see Figure 4) expected for the second current sensor 42. If the difference between the second current value Iv2 and the integrated current value Ivt is less than or equal to the predetermined value, and the fault determination unit 83 determines that the second current value Iv2 and the integrated current value Ivt are approximately the same value (S36: YES), then in S38, the fault determination unit 83 determines that all current sensors 41 to 43 are normal. In this case, the fault determination unit 83 considers that it made a misjudgment in the main process and cancels the switching of the conversion control unit 81 to failsafe mode (see Figure 5, S15).

[0054] Conversely, if the difference between the second current value Iv2 and the integrated current value Ivt exceeds a predetermined value, and it is determined that the second current value Iv2 and the integrated current value Ivt are different values ​​(S36: NO), the fault determination unit 83 determines in S39 that the second current sensor 42 is faulty. In this case, the conversion control unit 81, based on the switch to fail-safe mode in the main process, continues the power conversion operation of the second conversion circuit unit 30 using the outputs of the normal first current sensor 41 and total current sensor 43. Specifically, the conversion control unit 81 uses the value obtained by subtracting the first current value Iv1 from the integrated current value Ivt as the second current value Iv2 and controls the second conversion circuit unit 30. Note that in fail-safe mode when the second current sensor 42 is faulty, the conversion control unit 81 may stop the power conversion operation of the second conversion circuit unit 30 and continue only the power conversion operation of the first conversion circuit unit 20.

[0055] On the other hand, if the difference between the first current value Iv1 and the integrated current value Ivt exceeds a predetermined value and the fault determination unit 83 determines that the first current value Iv1 and the integrated current value Ivt are different values ​​(S35: NO), the fault determination unit 83 compares the second current value Iv2 and the integrated current value Ivt in S37. If the fault determination unit 83 determines that the difference between the second current value Iv2 and the integrated current value Ivt is less than or equal to a predetermined value and that the second current value Iv2 and the integrated current value Ivt are approximately the same value (S37: YES), the fault determination unit 83 determines in S40 that the first current sensor 41 is faulty.

[0056] In this case, the conversion control unit 81, based on the switch to fail-safe mode in the main process, continues the power conversion operation of the first conversion circuit unit 20 using the outputs of the normal second current sensor 42 and total current sensor 43. Specifically, the conversion control unit 81 uses the current value obtained by subtracting the second current value Iv2 from the integrated current value Ivt as the first current value Iv1 and controls the first conversion circuit unit 20. In addition, the conversion control unit 81 may stop the power conversion operation of the first conversion circuit unit 20 in fail-safe mode when the first current sensor 41 fails, and continue only the power conversion operation of the second conversion circuit unit 30.

[0057] On the other hand, if the difference between the second current value Iv2 and the integrated current value Ivt exceeds a predetermined value, and it is determined that the second current value Iv2 and the integrated current value Ivt are different values ​​(S37: NO), the fault determination unit 83 determines in S41 that the total current sensor 43 is faulty. In this case, the conversion control unit 81 switches to fail-safe mode in the main process and continues both the power conversion operation of the first conversion circuit unit 20 using the first current value Iv1 and the power conversion operation of the second conversion circuit unit 30 using the second current value Iv2. The fault determination unit 83 may also determine in S41 that both the first current sensor 41 and the second current sensor 42 are faulty. In this case, the conversion control unit 81 restricts or stops both the power conversion operations of the first conversion circuit unit 20 and the second conversion circuit unit 30 in fail-safe mode.

[0058] (Summary of the First Embodiment) In the first embodiment described above, the first current C1 and the second current C2 flowing through the first parallel section 28 and the second parallel section 38, which branch in parallel with each other, are detected by the first current sensor 41 and the second current sensor 42. In addition, the pre-division current Cb, which is the sum of the first current C1 and the second current C2, is also detected by the total current sensor 43. Therefore, in a configuration that includes multiple conversion circuit sections 20 and 30, it becomes possible to detect not only the currents in the parallel sections 28 and 38 after branching, but also the sum of these currents.

[0059] As described above, if the pre-division current Cb is detected in addition to the first current C1 and second current C2, it becomes possible to compare the measured values ​​of these currents. Specifically, it becomes possible to compare the first current value Iv1 and the second current value Iv2 after division with the combined current value Ivt before division. According to Kirchhoff's first law, the sum of the first current value Iv1 and the second current value Iv2 should be equal to the combined current value Ivt. Therefore, based on the above comparison, it is possible to detect the occurrence of a sensor failure and identify the faulty current sensor.

[0060] In addition, in the first embodiment, there is only one current sensor each in the first parallel section 28, the second parallel section 38, and the power connection line 11. That is, there is no need to provide multiple current sensors in a single current path for redundancy. Therefore, the boost circuit 10 can be simplified and miniaturized.

[0061] Furthermore, the power converter 100 of the first embodiment includes a fault detection unit 83. The fault detection unit 83 determines a fault in at least one of the multiple current sensors 41 to 43 based on a comparison of the first current value Iv1 output by the first current sensor 41, the second current value Iv2 output by the second current sensor 42, and the integrated current value Ivt output by the total current sensor 43. In this way, the fault detection unit 83 can detect a fault in each of the current sensors 41 to 43 even if multiple current sensors are not provided in the same current path, by comparing the current values ​​Iv1, Iv2, and Ivt. As a result, the boost circuit 10 can be simplified and miniaturized.

[0062] Furthermore, the fault detection unit 83 of the first embodiment compares the sum of the first current value Iv1 and the second current value Iv2 with the integrated current value Ivt. If the sum and the integrated current value Ivt deviate by more than the fault detection threshold ThF, the fault detection unit 83 determines that at least one of the first current sensor 41, the second current sensor 42, and the total current sensor 43 is faulty. With this determination method, the fault detection unit 83 can detect the faults of each current sensor 41 to 43 with high accuracy.

[0063] In addition, in the first embodiment, multiple of the first current sensor 41, the second current sensor 42, and the total current sensor 43 are held on a single sensor board 59. With this configuration, the configuration of the power conversion device 100 can be simplified.

[0064] In the first embodiment, the total current sensor 43 is located on the power connection line 11. This total current sensor 43 can accurately measure the pre-division current Cb, which is the sum of the first current C1 and the second current C2.

[0065] Furthermore, in the first embodiment, if the failure detection unit 83 determines that any one of the current sensors 41 to 43 has failed, the conversion control unit 81 continues the power conversion operation of the first conversion circuit unit 20 and the second conversion circuit unit 30 using the outputs of the two current sensors that have not failed. This fail-safe mode ensures redundancy of the boost circuit 10 by allowing at least some of the power conversion operation to continue even if one current sensor fails.

[0066] In the first embodiment described above, the power connection line 11 corresponds to the "input side connection line," and the inverter connection line 12 corresponds to the "output side connection line." Also, the first current sensor 41 corresponds to the "first current detection unit," the second current sensor 42 corresponds to the "second current detection unit," and the total current sensor 43 corresponds to the "total current detection unit." Furthermore, the sensor board 59 corresponds to the "holder," the inverter 70 corresponds to the "output side," the battery 110 corresponds to the "input side," and the fault determination threshold ThF corresponds to the "predetermined value."

[0067] (Second Embodiment) The second embodiment of the present disclosure shown in Figures 7 and 8 is a modification of the first embodiment. In the power converter 200 of the second embodiment, a total current sensor 243 is provided instead of the total current sensor 43 (see Figure 2) of the first embodiment. The total current sensor 243 is located not on the power supply connection line 11 before the current division, but in the parallel section HB after the current division, between the reactors 23 and 33 and the inter-element connection sections 25 and 35. The total current sensor 243 is adjacent to the first current sensor 41 and the second current sensor 42. The total current sensor 243 is located in the first parallel section 28 and the second parallel section 38 and measures the first current C1 and the second current C2 simultaneously. The total current sensor 243 outputs the sum of the first current C1 and the second current C2, Ivg. The sum of Ivg is the value obtained by measuring the first current C1 and the second current C2 together, and corresponds to the value of the total current obtained by adding the first current C1 and the second current C2 together. The sensor measurement value from the total current sensor 243 is acquired by the power controller 80 as an integrated current value Ivt.

[0068] The total current sensor 243, like the first current sensor 41 and the second current sensor 42, is mainly composed of a Hall IC 61 (see Figure 8). In the second embodiment, the Hall IC 61s of the first current sensor 41, the second current sensor 42, and the total current sensor 243 are combined with a single core portion 263 to form an integrated structure. In other words, the first current sensor 41, the second current sensor 42, and the total current sensor 243 are held by a single holder, the core portion 263.

[0069] The core portion 263, like the core portion 63 of the first embodiment (see Figure 3), is formed in the shape of an annular or polygonal annular, or cylindrical or polygonal tube, using a magnetic material with high magnetic permeability. In the second embodiment, the busbar 51 forming the first parallel section 28 and the busbar 53 forming the second parallel section 38 are arranged adjacent to each other. The core portion 263 is provided so as to collectively surround the busbars 51 and 53. At least three gaps 64a to 64c are formed in the core portion 263.

[0070] The gap 64a is formed on the peripheral wall of the annularly formed core portion 263, at a position facing one end face of the band-shaped busbar 51. The Hall IC 61 of the first current sensor 41 is housed in the gap 64a. The Hall IC 61 placed in the gap 64a is subjected to a magnetic field mainly generated by the first current C1 flowing through the busbar 51. Therefore, the first current sensor 41 can detect the first current C1 using the Hall IC 61.

[0071] The gap 64b is formed on the peripheral wall of the core portion 263, facing one end face of the band-shaped busbar 53. The Hall IC 61 of the second current sensor 42 is housed in the gap 64b. The Hall IC 61 placed in the gap 64b is subjected to a magnetic field mainly generated by the second current C2 flowing through the busbar 53. Therefore, the second current sensor 42 can detect the second current C2 using the Hall IC 61.

[0072] The gap 64c is formed on the peripheral wall of the core portion 263 at a position equidistant from the two busbars 51 and 53. The Hall IC 61 of the total current sensor 243 is housed in the gap 64c. The Hall IC 61 placed in the gap 64c is subjected to a magnetic field generated by both the first current C1 flowing through the busbar 51 and the second current C2 flowing through the busbar 53. Therefore, the total current sensor 243 can detect the total current, which is the sum of the first current C1 and the second current C2, using the Hall IC 61.

[0073] In the second embodiment described so far, the same effects as in the first embodiment are achieved, and in a configuration that includes multiple conversion circuit sections 20 and 30, it becomes possible to detect not only the current in the parallel sections 28 and 38 after branching, but also the sum of these currents.

[0074] In addition, the total current sensor 243 of the second embodiment is located in the first parallel section 28 and the second parallel section 38, and outputs the sum of the first current C1 and the second current C2, Ivg. In this way, if the total current sensor 243 is configured to detect the first current C1 and the second current C2 together in the parallel section HB, the total current sensor 243 can be easily placed near the first current sensor 41 and the second current sensor 42. As a result, it becomes possible to integrate the total current sensor 243, the first current sensor 41, the second current sensor 42, and the related core section 263, etc. As a result, the boost circuit 10 can be simplified and miniaturized. In the second embodiment described above, the total current sensor 243 corresponds to the "total current detection unit".

[0075] (Other Embodiments) Although one embodiment of the present disclosure has been described above, the present disclosure is not to be construed as being limited to the above embodiment, and can be applied to various embodiments and combinations without departing from the gist of the present disclosure.

[0076] The power converters 100 and 200 in the above embodiment included a boost circuit 10, an inverter 70, and a power controller 80. However, the configuration of the power converter may be changed as appropriate. Specifically, the power converter of Modification 1 of the above embodiment includes a boost circuit 10, but does not include an inverter 70 and a power controller 80. This power converter is electrically connected to an external inverter 70 and power controller 80.

[0077] Furthermore, the power conversion device of Modification 2 of the above embodiment includes a boost circuit 10 and an inverter 70, but does not include a controller 80. This power conversion device is electrically connected to an external power controller 80. Furthermore, the power conversion device of Modification 3 of the above embodiment includes a boost circuit 10 and a power controller 80, but does not include an inverter 70. This power conversion device is electrically connected to an external inverter 70.

[0078] In Modification 4 of the First Embodiment described above, the total current sensor 43 is located on the inverter connection line 12 (see Figure 2). In Modification 4, the total current sensor 43 detects the combined current Ca (see Figure 2) flowing through the inverter connection line 12 and outputs an integrated current value Ivt measured from the combined current Ca. In this Modification 4, the current values ​​before and after merging are compared in the fault detection process (see Figure 5, S12).

[0079] Furthermore, in the modified versions 5 and 6 of the first embodiment described above, the total current sensor 43 is located on the negative electrode connection line 13. Specifically, the total current sensor 43 in modified version 5 is located in the power supply side section 13a (see Figure 2) and detects the N-path current Cn (see Figure 2) flowing through the power supply side section 13a. On the other hand, the total current sensor 43 in modified version 6 is located in the inverter side section 13b (see Figure 2) and detects the N-path current Cn flowing through the inverter side section 13b. The total current sensors 43 in the modified versions 5 and 6 output an integrated current value Ivt, which is the measured N-path current Cn. The direction of the N-path current Cn is defined as positive when it is directed from the inverter 70 (output side) to the battery 110 (input side), and negative when it is directed from the battery 110 to the inverter 70.

[0080] Furthermore, the positions of the first current sensor 41 and the second current sensor 42 may also be changed within the range of the parallel section HB. For example, the first current sensor 41 may be placed on the side of the power connection line 11 of the reactor 23 within the first parallel section 28. Similarly, the second current sensor 42 may be placed on the side of the power connection line 11 of the reactor 33 within the second parallel section 38. As described above, the positions of each current sensor may be changed as appropriate according to the physical structure of the boost circuit 10.

[0081] In the above embodiment, the Hall IC 61 combined with the core was used as a current sensor. However, the configuration of the current sensor may be changed as appropriate. For example, the current sensor may be configured to convert the voltage drop across the shunt resistor into a current and measure the value of this current. Furthermore, the current sensor may be configured to detect the magnetic field generated around the current flowing through a busbar or the like using the Hall IC 61, without using a core.

[0082] In the above embodiment, the current sensors 41-43 of the boost circuit 10 and the INV current sensor 75 of the inverter 70 were held together on the sensor board 59. However, the current sensors 41-43 of the boost circuit 10 and the INV current sensor 75 of the inverter 70 may be mounted on different printed circuit boards.

[0083] In the above embodiment, the vehicle-mounted battery 110 was configured as the input side of the boost circuit 10. However, the configuration of the input side of the boost circuit 10 may be changed as appropriate. For example, in modification 7 of the above embodiment, a fuel cell is connected to the input side of a power conversion device mainly consisting of the boost circuit 10. The power conversion device functions as an FDC (Fuel cell DC-DC Converter), boosting the fuel voltage (FC voltage) and supplying it to the inverter 70 on the output side. In addition to such fuel cells, for example, a solar panel and a generator may be configured as the input side of the boost circuit 10.

[0084] Furthermore, in the above embodiment, the inverter 70 was configured as the output side of the boost circuit 10. However, the configuration of the output side of the boost circuit 10 may be changed as appropriate. For example, a configuration that uses DC current, such as a DC motor, LED lighting device, and communication device, may be configured as the output side of the boost circuit 10.

[0085] The electric vehicles equipped with the power converters described herein are not limited to typical Personally Owned Vehicles (POVs) intended for personal ownership. Power converters may be installed in rental cars, manned taxis, rideshare vehicles, freight vehicles, and buses, etc. Furthermore, power converters may be installed in unmanned vehicles used in mobility services, construction machinery, agricultural machinery, railway vehicles, trams, and Dual Mode Vehicles (DMVs), etc. Power converters may also be installed in ships and electric aircraft such as drones and eVTOLs. Moreover, power converters may be configured as stationary units, not mounted on mobile vehicles, and installed in facilities that consume electricity.

[0086] In this disclosure, the term "connected" may mean that an element is directly connected to another element, or indirectly connected through an intermediary element. Similarly, the term "adjacent" may mean that an element is directly adjacent to another element without an intermediary element, or indirectly adjacent through an intermediary element.

[0087] The control unit and method described herein may be implemented by a dedicated computer comprising a processor programmed to perform one or more functions embodied by a computer program. Alternatively, the apparatus and method described herein may be implemented by a dedicated hardware logic circuit. Alternatively, the apparatus and method described herein may be implemented by one or more dedicated computers comprising a combination of a processor that executes a computer program and one or more hardware logic circuits. Furthermore, the computer program may be stored as instructions executed by the computer on a computer-readable non-transitional tangible recording medium.

[0088] (Disclosure of Technical Ideas) This specification discloses several technical ideas as described in the following paragraphs. Some paragraphs may be written in a multiple dependent form, where subsequent paragraphs optionally refer to preceding paragraphs. Furthermore, some paragraphs may be written in a multiple dependent form, where they refer to other multiple dependent forms. These paragraphs written in multiple dependent forms define several technical ideas.

[0089] (Technical Concept 1) A power conversion device comprising: an input-side connection line (11) electrically connected to an input side (110); an output-side connection line (12) electrically connected to an output side (70); a first conversion circuit unit (20) having a first parallel section (28) branching from the input-side connection line and converting voltage between the first parallel section and the output-side connection line; a second conversion circuit unit (30) having a second parallel section (38) branching from the input-side connection line in parallel with the first parallel section and converting voltage between the second parallel section and the output-side connection line; a first current detection unit (41) for detecting a first current (C1) flowing through the first parallel section; a second current detection unit (42) for detecting a second current (C2) flowing through the second parallel section; and a total current detection unit (43, 243) for detecting a total current which is the sum of the first current and the second current. (Technical Idea 2) The power conversion device according to Technical Idea 1, further comprising a fault determination unit (83) that determines a fault in at least one of the first current detection unit, the second current detection unit, and the total current detection unit based on a comparison of a first current value (Iv1) output by the first current detection unit, a second current value (Iv2) output by the second current detection unit, and an integrated current value (Ivt) output by the total current detection unit. (Technical Idea 3) The power conversion device according to Technical Idea 2, wherein the fault determination unit compares a total value obtained by adding the first current value and the second current value with the integrated current value, and determines that at least one of the first current detection unit, the second current detection unit, and the total current detection unit is faulty if the total value and the integrated current value deviate by more than a predetermined value (ThF). (Technical Idea 4) The power conversion device according to any one of Technical Ideas 1 to 3, wherein a plurality of the first current detection unit, the second current detection unit, and the total current detection unit are held in a single holder (59). (Technical Concept 5) The power conversion device according to any one of Technical Concepts 1 to 4, wherein the total current detection unit is located on any one of the input side connection line, the output side connection line, and the negative electrode side connection line (13) provided between the input side and the output side.(Technical Idea 6) The power conversion device according to any one of Technical Ideas 1 to 4, wherein the total current detection unit is located in the first parallel section and the second parallel section and outputs the sum of the first current and the second current (Ivg). (Technical Idea 7) The power conversion device according to Technical Idea 2 or 3, further comprising a conversion control unit (81) that, when a failure is determined by the failure determination unit in any one of the first current detection unit, the second current detection unit, and the total current detection unit, continues the power conversion operation of the first conversion circuit and the second conversion circuit using the outputs of the two normal detection units among the first current detection unit, the second current detection unit, and the total current detection unit that are not faulty.

Claims

1. A power conversion device comprising: an input-side connection line (11) electrically connected to an input side (110); an output-side connection line (12) electrically connected to an output side (70); a first conversion circuit unit (20) having a first parallel section (28) branching from the input-side connection line and converting voltage between the first parallel section and the output-side connection line; a second conversion circuit unit (30) having a second parallel section (38) branching from the input-side connection line in parallel with the first parallel section and converting voltage between the second parallel section and the output-side connection line; a first current detection unit (41) for detecting a first current (C1) flowing through the first parallel section; a second current detection unit (42) for detecting a second current (C2) flowing through the second parallel section; and a total current detection unit (43, 243) for detecting a total current which is the sum of the first current and the second current.

2. The power conversion device according to claim 1, further comprising a fault determination unit (83) that determines at least one fault in the first current detection unit, the second current detection unit, and the total current detection unit based on a comparison of a first current value (Iv1) output by the first current detection unit, a second current value (Iv2) output by the second current detection unit, and an integrated current value (Ivt) output by the total current detection unit.

3. The power conversion device according to claim 2, wherein the fault determination unit compares the sum of the first current value and the second current value with the integrated current value, and determines that at least one of the first current detection unit, the second current detection unit, and the total current detection unit is faulty if the sum of the first current value and the integrated current value deviate by more than a predetermined value (ThF).

4. The power conversion device according to claim 1, wherein a plurality of the first current detection unit, the second current detection unit, and the total current detection unit are held in a single holder (59).

5. The power conversion device according to claim 1, wherein the total current detection unit is located on any one of the input side connection line, the output side connection line, and the negative electrode side connection line (13) provided between the input side and the output side.

6. The power conversion device according to claim 1, wherein the total current detection unit is located in the first parallel section and the second parallel section and outputs the sum of the first current and the second current (Ivg).

7. The power conversion device according to claim 2 or 3, further comprising a conversion control unit (81) that, when the fault determination unit determines that any one of the first current detection unit, the second current detection unit, and the total current detection unit is faulty, continues the power conversion operation of the first conversion circuit unit and the second conversion circuit unit using the outputs of the two normal detection units among the first current detection unit, the second current detection unit, and the total current detection unit that are not faulty.

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