Thermal conductivity enhancement in post-diamond-growth apparatuses and processes

Abstract

In certain examples, a poly crystalline (PC) diamond layer is processed to enhance the layer's TC (thermal conductivity) by a localized anneal confined to a subset region of the layer's processing surface. The temperature(s) of the localized anneal is sufficiently high to have damaged the processing surface if all of the processing surface were subjected to an anneal at such temperature(s). The localized anneal truncates grains extending into or beyond the processing surface to set or correspond with a low roughness attribute (e.g., not more than 1 nm). In another example, the localized anneal is preceded by performing a global anneal. The localized anneal results in unique physical attributes of the PC diamond layer including, e.g., the processing surface not being anneal-damaged, truncated diamond grains sufficient to set or correspond with an RMS roughness measure, and the TC being set as a function of grain sizes in the PC diamond layer and its thickness.

Description

STFD.467PCT (S24-398) 1THERMAL CONDUCTIVITY ENHANCEMENTIN POST-DIAMOND-GROWTH APPARATUSES AND PROCESSESBACKGROUND

[0000] Aspects of the present disclosure are related generally to the field of semiconductors and particularly to the use of diamond for thermal management of semiconductors.

[0002] As semiconductor integrated circuits (ICs) evolve towards higher transistor densities and more compact designs, managing thermal issues has become increasingly challenging. The trend of increasing transistor density results in higher power density within a confined volume, generating substantial heat. Coupled with decreasing interconnect pitch, which limits the space available for heat dissipation and creates narrower pathways for heat to escape, these factors can lead to significant hotspots and localized overheating. Additionally, the buried high thermal resistance in ICs exacerbates these problems, making effective heat transfer between layers difficult and contributing to the formation of thermal gradients. These thermal challenges can induce mechanical stresses due to differential thermal expansion and contraction across the chip layers. Such stresses can compromise the structural integrity of the device, leading to potential failures or reduced longevity. To counteract these issues, enhancing vertical and lateral thermal conduction and utilizing high thermal conductivity insulators are critical. These measures improve heat spreading and reduce thermal resistance, thereby mitigating hotspots and thermal stress.

[0003] Diamond emerges as a promising solution due to its exceptional thermal conductivity, which ranges from 300 to 2500 W / m K — significantly higher than copper’s maximum thermal conductivity of 400 W / m K. This superior thermal conductivity enables diamond to efficiently conduct heat away from hot spots, ensuring stable operation and preventing overheating. Moreover, diamond's low coefficient of thermal expansion helps maintain the IC’s structural integrity, reducing thermal stress. Integrating diamond into semiconductor manufacturing processes poses challenges, particularly in terms of cost and process compatibility. Further challenging is finding a way to integrate diamond into such semiconductor manufacturing processes in a manner that is compatible with existing foundry processes.

[0004] Exemplary aspects of the present disclosure are directed to overcoming one or more of the above challenges and / or constraints.STFD.467PCT (S24-398) 2SUMMARY OF VARIOUS ASPECTS AND EXAMPLES[OG05 Various examples / embodiments presented by the present disclosure are directed to issues such as those addressed above and / or others which may become apparent from the following disclosure. For example, some of these disclosed aspects are directed to methods and devices that use or leverage from processing an as-grown PC (poly crystalline) diamond layer to realize an enhanced TC (temperature conductivity) with somewhat minimized roughness attributes. In certain specific examples, the processing surface has an average RMS roughness that is not greater than 1 nm.

[0006] In certain examples, a polycrystalline (PC) diamond layer is processed to enhance the layer’s TC (thermal conductivity) by a localized anneal confined to a subset region of the layer’s processing surface. The temperature of the localized anneal occurs with the subset region being exposed to one or more temperatures in a high temperature range sufficiently high enough to damage the processing surface if all of the processing surface were subjected to an anneal occurring within the high temperature range. The localized anneal reduces grain boundaries (e.g., by truncating grains extending into or beyond the processing surface) so as to set or correspond with a low roughness attribute (e.g., not more than 1 nm).

[0007] In another specific example according to the present disclosure, the abovereferenced localized anneal is preceded by performing a low-temperature global anneal, performed at a temperature that would not be expected result in an anneal-damaged PC diamond layer (e.g., oftentimes catastrophic damage) due to subjecting the processing surface to this low-temperature. Exemplary7damage in this regard includes one or more of: oxidation of the processing surface, graphitization of diamond grains in the PC diamond layer, delamination relative to a substrate on a side of the PC diamond layer opposite the processing surface, and void formation at an interface involving the PC diamond layer.

[0008] In other important aspects, the present disclosure is directed to an apparatus (e.g., semiconductor device, PC diamond layer, or an IC package such as a flip-chip device including at least one such PC diamond layer) as opposed to method of manufacturing such an apparatus. This follows as in each instance of the above-referenced localized anneal, the localized anneal results in the PC diamond layer having unique physical attributes including, as examples, the processing surface: not being anneal-damaged, having truncated diamond grains sufficient to set or correspond with an RMS roughness measure, and the TC being set as a function of grain sizes in the PC diamond layer and its thickness.

[0009] In certain other examples which may also build on the above-discussed aspects, such anneal-resulting apparatuses include a circuit layer, including active circuitry (e.g., GaNSTFD.467PCT (S24-398) 3 device, a SiC device, and / or a CMOS device), secured to the PC diamond layer, through a thermal interface material, wherein the TC has a planar characteristic (transferring heat in a planar direction), associated with the processing surface, that is: set as a function of diamond grain size along the processing surface and thickness of the PC diamond layer; and to reduce phonon scattering at or near an interface, during use of the active circuitry.

[0010] In yet more specific aspects, the above-characterized temperature range for the high-temperature localized annealing process is from approximately 600 °C to 1400 °C. This range is significantly higher than the temperatures ty pically employed in conventional global annealing processes for diamond or other wide-bandgap materials, which are generally limited to 400-800 °C in order to avoid damage such as in the form of surface oxidation, graphitization, and / or delamination.[001 ' ] The above discussion is not intended to describe each aspect, embodiment or every implementation of the present disclosure. The figures and detailed description that follow also exemplify various embodiments.BRIEF DESCRIPTION OF FIGURES

[0012] Various example embodiments, including experimental examples, may be more completely understood in consideration of the following detailed description in connection with the accompanying drawings, each in accordance with the present disclosure, in which:

[0013] FIG. 1 depicts a series of steps representative of different manufacturing processes as examples according to certain exemplary aspects of the present disclosure;

[0014] FIG. 2 is a set of cross-sectional views showing related aspects of diamond-grain morphology, according to certain exemplar}’ aspects of the present disclosure:

[0015] FIG. 3 is a graph, with cross-sectional views of thin and thick diamond layers on either side and with diamond thickness along the horizontal axis and thermal conductivity7along the vertical axis, of diamond-related attributes so as to highlight attributes according to certain exemplary aspects of the present disclosure; and

[0016] FIG. 4 is a set of related perspective views of diamond layers with RMS roughness of a processing surface before processing (top row of images with higher RMS- roughness values) and after processing (bottom row of images with lower RMS-roughness values), according to certain exemplary aspects of the present disclosure.[001 ?] While various embodiments discussed herein are amenable to modifications and alternative forms, aspects thereof have been show n by way of example in the drawings and will be described in detail. It should be understood, however, that the intention is not to limitSTFD.467PCT (S24-398) 4 the disclosure to the particular embodiments described. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the scope of the disclosure including aspects defined in the claims. In addition, the term “example” as used throughout this application is only by way of illustration, and not limitation.DETAILED DESCRIPTION

[0018] Aspects of the present disclosure are believed to be applicable to a variety of different types of apparatuses, systems and methods involving devices characterized at least in part by including an as-grown polysilicon (PC) diamond layer that is designed to be secured (bonded) to a circuit layer for dissipating heat, during operation of active circuitry within the circuit layer. In certain examples, a polycrystalline (PC) diamond layer is processed to enhance the layer’s TC (thermal conductivity ) by a localized anneal confined to a subset region of the layer’s processing surface. The temperature of the localized anneal is sufficiently high to have damaged the processing surface if all of the processing surface were subjected to such annealing at such temperature(s). The localized anneal reduces grain boundaries (e.g., by truncating grains extending into or beyond the processing surface) so as to set or correspond with a low roughness attribute (e.g., not more than 1 nm). In such examples according to the present disclosure, rather than applying uniform heating across the entire substrate, which risks catastrophic damage, exemplary embodiments of the present disclosure uses spatially confined, high-temperature annealing to selectively modify grain boundaries while preserving the integrity of the bulk material.|0019] In another example, the localized anneal is preceded by performing a global anneal. The localized anneal results in unique physical attributes of the PC diamond layer including, e g., the processing surface not being anneal -damaged, truncated diamond grains sufficient to set or correspond with an RMS roughness measure, and the TC being set as a function of grain sizes in the PC diamond layer and its thickness. While the present disclosure is not necessarily limited to such aspects, an understanding of specific examples in the following description may be understood from discussion in such specific contexts.

[0020] Consistent with the above aspects, such a manufactured device or method of such manufacture may involve aspects presented and claimed in U.S. Provisional Application Serial No. 63 / 705,959 filed on October 10, 2024 (STFD.467P1 / S24-398) with Appendices A- B, to which priority is claimed. To the extent permitted, such subject matter is incorporated by reference in its entirety generally and to the extent that further aspects and examples (such as experimental and / more-detailed embodiments) may be useful to supplement and / or clarify.STFD.467PCT (S24-398) 5Accordingly, in the following description various specific details are set forth to describe specific examples presented herein. However, it should be apparent that one or more other aspects, examples and / or variations thereof may be practiced without all the specific details given below. In other instances, well known features have not been described in detail so as not to obscure the description of the examples herein. Also, although aspects and features may in some cases be described in individual figures, it will be appreciated that features from one figure or embodiment can be combined with features of another figure or embodiment even though the combination is not explicitly shown or explicitly described as a combination (for ease of illustration, the same connotation and / or reference numerals may be used in different diagrams to refer to the same elements or additional instances of the same element).

[0021] In certain method-type examples of the present disclosure, a processing surface of the PC diamond layer experiences at least one anneal, including or corresponding to a localized anneal, to enhance the TC (thermal conductivity) of the PC diamond layer by using a temperature in a range sufficiently high to have damaged the processing surface if the localized anneal were applied as a global anneal at such high temperature(s), and that truncates parts of a plurality of grains along the processing surface to set or correspond with a roughness attribute. In certain device-type examples of the present disclosure and based on application of such a localized anneal, the processing surface of the PC diamond layer is uniquely changed as is evident, for example, by such an enhanced TC, by the processing surface if the localized anneal were applied to all of the processing surface at such temperature(s), by parts of grains along the processing surface recognizable as surface- truncated grains (caused by the localized anneal) and with the surface-truncated grains setting a suitably-low roughness attribute - without the processing layer being damaged by the high- temperature annealing of the processing surface (sometimes referred to as being “anneal damaged”).

[0022] In certain such examples, at least the localized annealing (if not also one or more global annealing efforts before the localized annealing) is realized by ion-beam planarization. In more-specific examples, the localized annealing is realized by ion-beam planarization in which the ion beams are sourced such that they are aligned to target the subset region (e.g., less than one percent of the overall processing surface ). In such global annealing, the ion beams are misaligned with no specificity for targeting any such subset region.

[0023] In accordance with certain exemplary aspects, the present disclosure is directed to a method of processing a surface-area side of a PC diamond layer to enhance its TC (thermal conductivity) by use of a localized anneal. The localized anneal is spatially confined to aSTFD.467PCT (S24-398) 6 subset region of the processing surface, with the anneal using a temperature range that is sufficiently high to have damaged the processing surface if the (localized) anneal were a global anneal as applied simultaneously to the entire the processing surface. In more particular examples, the localized anneal is part of a planarization (with aligned ion beams) that causes rough parts of the processing surface, attributable to grains extending into and / or above the processing surface to be truncated. This truncation operation is used to set or correspond with a roughness attribute.

[0024] With regards to specific temperatures corresponding to the high-temperature localized annealing and / or the low-temperature global annealing, in exemplary more-specific or experimental efforts, the above-characterized temperature range for the high-temperature localized annealing process is from approximately 600 °C to 1400 °C (or in some examples, 800 °C to 1400 °C). This range is significantly higher than the temperatures typically employed in conventional global annealing processes for diamond or other wide-bandgap materials, which are generally limited to 400 °C to 800 °C in order to avoid damage such as in the form of surface oxidation, graphitization, delamination and / or void formation at an interface involving the PC diamond layer.

[0025] Consistent with the present disclosure, such devices and / or methods may be used for producing a PC-diamond thermal management system (among other examples disclosed herein) that includes a few to several attributes. Such attributes include, for example: (a) at least one poly crystalline (PC) diamond layer having, on one of its sides, a processing surface that is not damaged (e.g., by one or more of processing-surface oxidation, graphitization of diamond grains, and delamination where the device may interface with a substrate or another layer such as a circuit layer); (b) the processing surface including a plurality of diamond grains being truncated along the processing surface to set or correspond with an RMS roughness measure of the processing surface; and / or (c) and a TC (thermal conductivity ) that is in a range from a lower threshold set as a function of grain sizes in the PC diamond layer and a thickness characterizing the PC diamond layer.

[0026] More particular examples manifest other details. For example, in certain of these more particular examples, the localized annealing is performed for additional subset regions of the processing surface to cause the TC of the PC diamond layer to be in TC range from 450 W / m / K to 900 W / m / K, to dissipate heat flux densities exceeding 1 kW / cm2, corresponding to the PC diamond layer having a thickness that is in a range from 70 nm to 200 nm. As noted above, while such particular examples and results of experimental efforts may call out specific aspects, the present disclosure is not so limited (e.g., such experimentalSTFD.467PCT (S24-398) 7 efforts may call out a thickness range from 70 to 200 nm but the above-characterized example methods may be used to realize PC diamond layers, with comparable attributes, as thin as 10 nm and as thick as 20 urn).

[0027] In some instances, after the localized annealing, the method includes securing a circuit layer (that includes active circuitry) to the PC diamond layer to spread heat generated by use of the active circuitry. The circuit layer can be bonded to the PC diamond layer directly or through another thin layer, such as an interlayer material (e.g., such as a silicon carbide (SiC) or aluminum nitride (AIN)) that accommodates the phonon mismatch and thermal expansion differences between PC diamond layer and the circuit layer. Further, in such examples, the TC has a planar characteristic, associated with the processing surface, that is set as a function of diamond grain size along the processing surface and thickness of the PC diamond layer, and that is to reduce phonon scattering at or near an interface, during use of the active circuitry’ and / or roughness along the processing surface being sufficiently reduced (rendered smooth) to facilitate further processing involving the processing surface. Examples of such further processing includes polishing, bonding to a circuit layer, and the like. Examples of active circuitry that may be implemented in the circuit layer, such as being secured adjacent the PC diamond layer, include fast-switching and / or high-power circuits (e.g., GaN device, a SiC device, and / or a CMOS device), and optionally any of a variety of package types including but not limited to flip-chip packages.

[0028] In one or more of the above more particular examples, the method may further include iteratively applying the localized anneal to a sufficient number of additional subset regions of the processing surface to realize, for an area corresponding to a portion of the processing surface that is larger than the additional subset regions, an RMS roughness is within a range from 0.8 to 10 nm, or within twenty percent of the roughness attribute which is set as a function of grain-size distribution. For example, by movement of the processing surface, relative to a source of ion beams, a beam scanning pattern may be effected in the form of one or more of raster, spiral and rotational. In more particular / experimental examples, the sample PC diamond layer is so processed by such movement, including rotating and shifting along an X-Y plane parallel to the layer’s processing surface. The beam may be controlled, relative to the surface, to scan the surface without stopping at a single point. The grain boundary removal process (e.g., resulting in a fine-grade planarization with truncated grains along the surface) can be controlled to happen over time (e.g., from 30 min to 30 hrs.) depending on the surface’s roughness and flatness, and / or size of the grains along the surface. As one example, the localized anneal may be used to reduce the grain boundariesSTFD.467PCT (S24-398) 8 along the surface and thereby cause the TC of the PC diamond layer to be in a range greater than about 800 W / m / K with the PC diamond layer being at a thickness of not greater than 150 nm, or a thickness in a range from 10 nm to 20 microns.

[0029] Turning now to the drawing, FIG. 1 depicts a series of steps representative of different processes, according to certain exemplary aspects of the present disclosure, involving a PC diamond layer 102 and, for support, a foundational structure referred to as substrate 104. In many but not all instances, the substrate 104 is separated from the PC diamond layer 102 before use of the PC diamond layer 102. Depending on the particular process being implemented, one or more of the steps 110-170 of FIG. 1 are optional as discussed, for example, further below.

[0030] In one example represented by such different processes in FIG. 1, the present disclosure is directed to subjecting a localized anneal to a processing surface of the poly crystalline (PC) diamond layer 102 by enhancing the PC diamond layer's thermal conductivity. The localized anneal is spatially confined to a subset region (less than all) of the processing surface (at the upwardly -facing side of the PC diamond layer), is performed in a temperature range sufficiently high to have damaged the processing surface if the localized anneal were applied to all of the processing surface, and reduces grain boundaries (sufficient to set a roughness attribute) at or near the surface by truncating parts of a plurality of grains that are along or extend beyond the processing surface. With specific reference to the steps in FIG. 1, this localized annealing is depicted at 160. As shown, this example uses ion beams aligned and spatially confined to target the subset region (e.g., at a low voltage such as in a range from 0.5 kV - 2.0 kV). In other examples, the ion beams need not be particularly aligned so long as a comparable result ensues in a practicable amount of anneal time. In such processing examples involving only step 160, typically the PC diamond layer would either be previously planed (e.g., a global ion-beam annealing as a coarse-grade planarization) and / or provided with a partially -smoothed processing surface such that aligned or misaligned use of the ion beams would not require an impracticable amount of anneal time to set or correspond with the roughness attribute of the processing surface as so desired.

[0031] In other examples that are consistent with the different processes represented by FIG. 1, one or more low-temperature globalized annealing steps (using misaligned, somewhat randomly directed beams) may be performed before the high-temperature localized annealing 160. As illustrated, assuming two such globalized annealing steps are performed, these efforts are shown at step 140, which involves high-voltage planarization (e.g., greater than 8 kV) and at step 150, which involves a medium voltage planarization (e.g., in a range from 2 kV to 6STFD.467PCT (S24-398) 9 kV). In connection with a more specific example including steps 140 and 150, the method begins at steps 110 and 120 where the PC diamond layer 102 is shown respectively having an upwardly -facing surface depicted with an as-grown hydrogen-terminated processing surface at 110 and, after exposing the surface to Oxygen, depicted with an Oxy gen-terminated processing surface at 120. At step 130, the PC diamond layer 102 is placed on a beam-ion mill for carrying out the first of the low-temperature globalized annealing steps 140 and 150.

[0032] As depicted in a more particular example, also according to the present disclosure, using each of the steps and values exemplified in FIG. 1, and as somewhat indicated in the above discussion, the process for planarization, thinning, and coalescence of diamond grains proceeds through the following sequence of steps. Step 110 corresponds with surface termination modification, and at step 120 the diamond surface is first converted from hydrogen termination to oxygen termination using an Ch-plasma treatment. Step 130 involves initial planarization via an ion-milling tool, with the PC diamond layer sample being set up in in an ion-milling system for controlled planarization by the ion-beam source. At step 140, higher-voltage global planarization is performed to improve surface stability and prepare the diamond for subsequent planarization. In specific examples, the global ion-beam annealing may be performed using misaligned beams at low RIE power (e.g., 50 W - 250 W) for approximately 1-5 minutes. The ion beams are deliberately misaligned to achieve improved uniformity across the sample surface, mitigating localized over-etching.

[0033] The next step, at 150, is a medium-powder planarization step. The surface roughness is further reduced to ~10 nm RMS using medium-energy ion beams (2-6 kV). This provides a smoother baseline for the final annealing step. This step 150 involves further global annealing also with beam misalignment for uniformity along the processing surface.

[0034] Step 160 of FIG. 1, as discussed above, depicts an example of the high- temperature localized annealing according to the present disclosure for a final planarization step. In this step of high-pow er planarization, the surface is planarized down to ~30 nm RMS roughness using high-energy ion beams (e.g., greater than 8 kV). This step removes larger aspirations and levels the processing surface. Such localized high-temperature annealing is applied at grain boundaries by aligning the beams to smaller areas, in conjunction with fine planarization (0.5-2 kV), to achieve an RMS roughness of <1 nm. This step promotes grain coalescence and reduces boundary density without subjecting the entire substrate to damaging global heating.

[0035] In one exemplary use of an ion milling tool according to the present disclosure, a focused ion beam (e.g., Ar+) is generated by a plasma ion source and then narrowed usingSTFD.467PCT (S24-398) 10 electrostatic lenses and apertures, to a spot size (subset) region of the processing surface that is smaller in diameter than 5 pm. Deflection plates may then be used to raster the beam across the diamond surface to deliver energy with high spatial precision. Depending on beam energy, current, and dwell time, the ions either sputter material away (resulting in grains being truncated where they extend at or across the plane of the processing surface) or deposit their kinetic energy as localized heat within a shallow interaction volume, and when operated in the latter regime the rapid thermalization of ion energy into lattice vibrations produces a confined “hot spot” that can anneal implantation damage or activate defects without globally heating the substrate, thereby enabling selective, micron-scale modification of diamond structures with minimal collateral effects.

[0036] In each of the above examples represented by FIG. 1, the high-temperature localized annealing 160 leads to the structure generally depicted at 170. This structure evidences the method used in developing it. For example, the PC diamond layer 102 as depicted at 170 includes one or more physical attributes resulting from the processing as follows: the processing surface is not anneal-damaged (e.g., as would be typical from a global anneal using misaligned beams); and at least one subset region of the processing surface includes a plurality of diamond grains being truncated along the processing surface to set or correspond with an RMS roughness measure of the processing surface, and / or is associated with a TC (thermal conductivity) that is in a range from a lower threshold set as a function of grain sizes in the PC diamond layer and a thickness characterizing the PC diamond layer. In more specific examples and as noted hereinabove, one or more other physical attributes resulting from the high-temperature localized annealing may be indicated by the range of the TC being from 450 W / m / K to 900 W / m / K, for which the PC diamond layer has a thickness that is in a range from 70 nm to 200 nm.

[0037] Also as is apparent after such post-growth processing of the PC diamond layer’s processing surface, measurable structural changes typically appear. These typical measurable structural changes include: the layer thickness being decreased by 20-30% and with uniformity being increased; surface roughness decreasing depending on conditions to as low as 1 nm; truncated grains and altered grain boundaries being visible in polycrystalline films; and thermal conductivity being enhanced by 50-100% after removing grain boundaries (replacing sp2 carbon with sp3 carbon). Post-growth structural changes in diamond, such as thickness, roughness, grain morphology, and thermal conductivity, translate directly into thermal management advantages. In high-pow-er / high-frequency electronics, this suppresses hotspots and extend the performance envelope. When such post-growth processed PCSTFD.467PCT (S24-398) 11 diamond is used in optical and photonic devices (e.g., GaN, SiC device, and / or a CMOS circuitry), it reduces scattering, stabilizes color centers, and mitigates thermal lensing. Together, such diamond attributes enable a cross-domain thermal platform, positioning diamond as a unifying material for next-generation semiconductor and photonic systems.

[0038] Advantageously and especially so when the PC diamond layer is secured to a circuit layer, the TC (being as high or in some cases much higher than the TC of copper) is extremely effective in spreading heat generated during operation of active circuitry (in the circuit layer). The thermal-management benefits are even more apparent, for example, when such the circuit layer's active circuitry includes fast-switching and / or high-power transistors and / or optics (e.g., including one or more of a GaN device, a SiC device, and a CMOS device). In such cases, the thermal -management benefits may be attributable to the TC having a planar (surface-like) characteristic associated with the processing surface, wherein the TC is set as a function of diamond grain size along the processing surface and thickness of the PC diamond layer, and / or is set to reduce phonon scattering at or near an interface, during use of the active circuitry.

[0039] FIG. 2 is a set of cross-sectional views showing related aspects of diamond-grain morphology, according to certain exemplary aspects of the present disclosure that, in certain specific examples, may be used in the aforementioned PC diamond layers such as layer 102 of FIG. 1. These aspects of diamond-grain morphology, for example, may involve grain structure modification through in-growth modifications, for example, with the in -growth modifications leading to the layer 102 (at steps 110 and 120 of FIG. 1) having highly - isotropic diamond grains. Highly-isotropic diamond grains are advantageous for any (or all) of vanous reasons; as examples, they manifest: fewer grain boundanes, lower phonon scattering rates, larger effective photon MFPs (mean free paths), higher in-plane TCs, and also importantly, a thinner PC diamond layer which can be used to provide a desired TC in place of a thicker PC diamond layer associated with the same TC. For example, the images in the lower right of FIG. 2 show lower phonon scattering rates with fewer grain boundaries (for more isotropic grains).

[0040] As shown along the top sequence of three images in FIG. 2, a thin and high thermally conductive PC diamond layer was developed for experimental purposes for heat spreading applications. Each of the images corresponds to the PC diamond layer being in the range of 100 nm to 20 pm. Such experimentation showed that the TC of the diamond layer is strongly dependent to the grain size and thickness of the diamond layer. A more isotropic diamond layer provides less phonon scattering through the diamond layer and higher TCSTFD.467PCT (S24-398) 12(FIG. 2). To illustrate exemplary grain sizes, the grains to the top and left of FIG. 1 show one such exemplary grain size as being 1.411 microns along the Y axis (vertical) and 1.873 microns along the X axis (horizontal to the processing surface).

[0041] Consistent with the examples illustrated in FIGs. 1 and 2, another specific example implementation according to the present disclosure is illustrated to the lower right of FIG. 2 in the form of the depicted PC diamond layer 205 secured to a circuit layer 220 (a dashed-line and including active circuitry such as the transistors therein generally representing switching devices as one or more of GaN ty pe, a CMOS ty pe and SiC ty pe). As depicted at an interface (or interfacial surface) between the PC diamond layer 205 and the circuit layer 220, an optional very-thin interlayer material 210 (e.g., such as a silicon carbide (SiC) or aluminum nitride (AIN)) may7be used.

[0042] A more particular example also in accordance with the present disclosure and represented by these parts of FIG. 2 correspond to a flip-chip package. The flip-chip package may include the PC diamond layer 205, the circuit layer 220 and optionally the interlayer material 210 (among other aspects not shown, such as solder bumps, interconnects, etc).

[0043] FIG. 3 is a graph showing how, in accordance with examples of the present disclosure, in-plane thermal conductivity7of PC diamond layers is a function of the thickness of the PC diamond layer. The graph of FIG. 3 depicts cross-sectional views of exemplary7thin diamond layers on the left side, and exemplary thick diamond layers on the right side.

[0044] Within the graph of FIG. 3, the horizontal axis is used to depict diamond thickness and the vertical axis is used to depict thermal conductivity7. The entries plotted on the graph correspond to experimental examples of the present disclosure (as indicated by the star-shaped entries), and testing of examples from previously-known literature according to efforts leading to the present disclosure. For each of the examples from previously -known literature, the corresponding data is indicated by a unique symbol (other than the star shaped entries), as in the map inset of FIG. 3. On the left side of FIG. 3, the exemplary thin diamond layers (as used for the plots in the graph) have nominal or average thickness measurements of 0.13 microns, 0.20 microns, and 0.25 microns. On the right side of FIG. 3, the exemplary7thick diamond layers (also used for the plots in the graph) have nominal or average thickness measurements of 3 microns, 8 microns, and 18 microns.

[0045] For each of the PC diamond layers (of different thicknesses), the TC was measured using time-domain thermoreflectance (TDTR), which tracks and / or relies on the heat transfer properties of the particular PC diamond layer under test. The plotted data sets inSTFD.467PCT (S24-398) 13 the graph of FIG. 3 summarize the TDTR measurement results for an exemplary (wide) range of diamond thicknesses from 100 nm to 20 pm along with the cross-section SEM images. [00461 The data plotted in the graph of FIG. 3 is revealing in significant and unexpected ways. First, the data shows that while the relationship, and degree of dependency, between these diamond attributes (i. e. , in-plane thermal conductivity and diamond thickness) varies, in each instance, the in-plane thermal conductivity of the PC diamond layer is a function of the thickness. Second, the data shows that thin diamond layers manifest a higher TC than the TC of thin copper. Third and also importantly, after the post-growth process involving the high- temperature localized annealing according to the present disclosure, the TC of the thin-film versions of the respective PC diamond layers increased to -800 W / m / K at -150 nm thickness. Moreover, the modification of the diamond layer using high-temperature localized annealing not only reduced phonon scattering near the surface but also provided a smoother surface suitable for fabrication steps that would typically follow (e.g., application of a thermally-conductive interface layer, further polishing of the PC diamond layer, and bonding the PC diamond layer to a circuit layer with or without an intervening thermally-conductive interface layer, etc.).[00 71 These results are surprising and counterintuitive. Conventional wisdom dictates that annealing diamond above 800 °C leads to oxidation, graphitization, or delamination. However, by spatially confining the anneal to micrometer-scale regions, the present disclosure demonstrates that temperatures as high as 1400 °C can be tolerated without catastrophic damage, while simultaneously enhancing phonon transport. This insight represents a non-obvious departure from prior art furnace anneals, and provides a pathway to wafer-scale integration of diamond heat spreaders in semiconductor foundries.

[0048] The beneficial impact of high-temperature localized annealing, according to the present disclosure, is shown in FIG. 4 with respect to three different exemplary PC diamond layers. As in the top row of FIG. 4, each of the three different PC diamond layers is shown with its RMS roughness along the processing surface before the high-temperature localized annealing. In the bottom row' of FIG. 4, each of the three different PC diamond layers is shown with its RMS roughness along the processing surface after the high-temperature localized annealing. The top row indicates the RMS-roughness values for the processing surfaces of the respective PC diamond layers as being 59 nm, 76 nm and 65 nm. After processing via the high-temperature localized annealing in accordance with the present disclosure, RMS-roughness values are shown being reduced significantly, from 59 nm to 7 nm, from 76 to 8 nm, and from 65 nm to 8.5 nm. In these and related proof-of-conceptSTFD.467PCT (S24-398) 14 experimental examples, comparative analysis relative to some previously-published results show RMS roughness improvements by an order of magnitude (e.g., from ~60 nm - 70 nm to less than 10 nm) and a 50-100% increase in thermal conductivity' relative to as -grown PC diamond, with this being due to such high-temperature localized annealing to remove grain boundaries along the processing surface to realize higher in-plane TC. The lower RMS roughness facilitates phonon transport at a higher rate than conventional thin film diamonds and results in achieving an impressively high TC (e.g., a higher TC than the TC of known materials in a comparable range of thicknesses). These results are surprising and unexpected.

[0049] Also surprising and unexpected is the lack of damage resulting from the high- temperature localized annealing as disclosed herein, particularly in view of previously-known efforts which teach that annealing above -800 °C leads to catastrophic degradation. More specifically, expected forms for damage and / or degradation include the following. Oxidation and Graphitization: at elevated temperatures in ambient or oxygen-containing environments, diamond readily oxidizes or converts to graphite. Delamination: due to the coefficient of thermal expansion mismatch between diamond and its underlying substrate, uniform heating can cause stress-induced delamination or cracking. The results disclosed with the high- temperature localized annealing according to the present disclosure demonstrates by annealing only a confined region of the PC diamond layer - as exposed to such high temperatures - beneficial grain boundary reduction can be realized w ithout triggering these types of degradations (aka failure modes). Since such processing is carried out under vacuum, oxidation is minimized, and because only a small fraction of the material is heated, thermal mismatch stresses are dramatically reduced or eliminated. In certain examples of the present disclosure, by confining the anneal spatially (locally) as discussed above (at temperatures as high as 1400 °C), beneficial grain boundary reduction is realized without triggering failure modes and while simultaneously enhancing phonon transport. These significant advancements, developed through such proof-of-concept experimental examples, also enable example embodiments, consistent with the present disclosure, involving wafer-scale integration of diamond heat spreaders in semiconductor foundries.

[0050] It is recognized and appreciated that as specific examples, the abovecharacterized figures and discussion are provided to help illustrate certain aspects (and advantages in some instances) which may be used in the manufacture of such structures and devices. These structures and devices include the exemplary structures and devices described in connection with each of the figures as well as other devices, as each such described embodiment has one or more related aspects w hich may be modified and / or combined withSTFD.467PCT (S24-398) 15 the other such devices and examples as described hereinabove may also be found in the Appendices of the above-referenced Provisional.

[0051] The skilled artisan would also recognize various terminology' as used in the present disclosure by way of their plain meaning. As examples, the Specification may describe and / or illustrates aspects useful for implementing the examples by way of various semiconductor materials / circuits which may be illustrated as or using terms such as layers, blocks, modules, device, system, unit, controller, and / or other circuit-ty pe depictions. Such semiconductor and / or semi conductive materials (including portions of semiconductor structure) and circuit elements and / or related circuitry may be used together with other elements to exemplify how certain examples may be carried out in the form or structures, steps, functions, operations, activities, etc. It would also be appreciated that terms to exemplify orientation, such as upper / lower, left / right, top / bottom and above / below, may be used herein to refer to relative positions of elements as shown in the figures. It should be understood that the terminology is used for notational convenience only and that in actual use the disclosed structures may be oriented different from the orientation shown in the figures. Thus, such terms should not be construed in a limiting manner.

[0052] The skilled artisan would also recognize that reference to a noun in the singular may refer to one from among one or more of, unless otherwise indicated (e.g., “a circuit” in various contexts is the same as referring to “circuitry” or circuits that may be used configure a circuit), and reference to certain open-ended terms should not be differentiated (e.g., “example” and “non-limiting example” are synonymous, and also are synonymous are terms such as comprising, including and having). Such aspects and circuit elements and / or related circuitry may be used together with other aspects to exemplify how certain examples may be carried out in the form or structures, steps, functions, operations, activities, etc. It should be understood that the terminology' is used for notational convenience only and that in actual use the disclosed structures may be oriented and / or ordered different from the orientation or ordering shown in the figures. Based upon the above discussion and illustrations, those skilled in the art will readily recognize that various modifications and changes may be made to the various embodiments without strictly following the exemplary embodiments and applications illustrated and described herein. Thus, these and similar terms should not be construed in a limiting manner.

Claims

STFD.467PCT (S24-398) 16What is Claimed:

1. A method comprising: on a poly crystalline (PC) diamond layer having a processing surface, enhancing the thermal conductivity (TC) of the PC diamond layer by a localized anneal that is spatially confined to a subset region of the processing surface, that occurs with the subset region being exposed to one or more temperatures in a high temperature range sufficiently high that would damage the processing surface if all of the processing surface were subjected to an anneal occurring in the high temperature range, and that truncates parts of a plurality’ of grains along the processing surface to set or correspond with a certain roughness attribute.

2. The method of claim 1, further including iteratively applying the localized anneal to additional subset regions of the processing surface.

3. The method of claim 1, further including iteratively applying the localized anneal to a sufficient number of additional subset regions of the processing surface to realize, for an area corresponding to a portion of the processing surface that is larger than the additional subset regions, an RMS roughness within a range from 0.8 to 10 nm, or within twenty percent of the roughness attribute which is set as a function of grain-size distribution.

4. The method of claim 1 , further including: at least one anneal to effect planarization via misaligned ion beams to target at least a relatively-large region of the processing surface that is at least a magnitude of order larger than the subset region; and securing a circuit layer to the PC diamond layer; wherein the circuit layer includes active circuitry' including at least one from among a GaN transistor, a SiC transistor, and a CMOS transistor, and the localized anneal includes using ion beams that are aligned to target the subset region.

5. The method of claim 1, further including repeating the localized anneal for additional subset regions of the processing surface to cause the TC of the PC diamond layer to be in TC range from 450 W / m / K to 900 W / m / K, and to dissipate heat flux densities exceeding1 kW / cm2, corresponding to the PC diamond layer having a thickness that is in a range from 70 nm to 200 nm.STFD.467PCT (S24-398) 176. The method of claim 1 , further including repeating the localized anneal to target additional subset regions of the processing surface until the processing surface manifests an RMS roughness for the subset regions of the processing surface after each said localized anneal, wherein the RMS roughness is not greater than approximately 1 nm, and not less than a threshold set at least in part as a function of grain sizes of the PC diamond layer and a thickness of the PC diamond layer.

7. The method of claim 1, further including performing at least one planarization step, using misaligned ion beams, and then further processing the processing surface using the localized anneal, wherein after further processing the processing surface using the localized anneal, the PC diamond layer has a thickness that is in a range from 70 nm to 200 nm.

8. The method of claim 1, wherein the subset region is a fractional region, corresponding to less than 1%, of the processing surface, and the localized anneal includes aligning ion beams to target the subset region and therein to cause a reduction in grain boundaries along the processing surface, and the method further includes applying the localized anneal to other subset regions, wherein the localized anneal is applied to other subset regions by movement of the processing surface, relative to a source of ion beams, to effect a beam scanning pattern corresponding to one or more of raster, spiral and rotational.

9. The method of claim 1, further including, as part of the localized anneal, causing ion beams to target the subset region while the ion beams are aligned, to effect a fine grade planarization of the processing surface by parts of the plurality of grains being truncated.

10. The method of claim 1, wherein the temperature range associated with the localized anneal is a range from 600 degrees C to 1400 degrees C.

11. The method of claim 1 , wherein the temperature range associated with the localized anneal is in a range having a lower limit of 800 degrees C.STFD.467PCT (S24-398) 1812. The method of claim 1, wherein the PC diamond layer has a thickness in a range from 10 nm to 20 microns, and further including securing the PC diamond layer to a circuit layer that includes active circuits, and using the PC diamond layer to spread heat generated by the circuit layer.

13. The method of claim 1, wherein the localized anneal is used to cause the TC of the PC diamond layer to be in a range greater than about 800 W / m / K with the PC diamond layer at a thickness of not greater than 150 nm.

14. The method of claim 1, wherein the temperature range is sufficiently high to have damaged the processing surface, in terms of one or a combination of: oxidation of the processing surface, graphitization of diamond grains in the PC diamond layer, delamination relative to a substrate on a side of the PC diamond layer opposite the processing surface, and void formation at an interface involving the PC diamond layer.

15. A method comprising: on a poly crystalline (PC) diamond layer having a processing surface, thinning the PC diamond layer by subjecting the processing surface to a global anneal that is not spatially confined to a subset region of the processing surface and that occurs in a temperature range sufficiently low to avoid damaging the processing surface; and enhancing the TC (thermal conductivity) of the PC diamond layer by a localized anneal that is spatially confined to the subset region of the processing surface, that is in a temperature range sufficiently high to have damaged the processing surface if the subset region were exposed by annealing in a temperature range sufficiently high that would damage the processing surface if all of the processing surface were subjected to annealing in the temperature range, and that truncates parts of a plurality of grains along the processing surface to set or correspond with a roughness measure of the processing surface.STFD.467PCT (S24-398) 1916. An apparatus comprising: a poly crystalline (PC) diamond layer having a processing surface, on one side of the PC diamond layer, that is not annealdamaged: and in at least one subset region of the processing surface including a plurality of diamond grains being truncated along the processing surface to set or correspond with an RMS roughness measure of the processing surface, and a thermal conductivity (TC) that is in a range from a lower threshold set as a function of grain sizes in the PC diamond layer and a thickness characterizing the PC diamond layer.

17. The apparatus of claim 16, wherein the range of the TC is from 450 W / m / K to 900 W / m / K, and the PC diamond layer has a thickness that is in a range from 70 nm to 200 nm, and wherein the processing surface is not anneal-damaged in that the processing surface does not manifest one or a combination of: oxidation of the processing surface, graphitization of diamond grains in the PC diamond layer, delamination relative to a substrate on a side of the PC diamond layer opposite the processing surface, and void formation at an interface involving the PC diamond layer.

18. The apparatus of claim 16, further including a circuit layer that includes active circuitry and that is secured to the PC diamond layer, through a thermal interface material, to spread heat generated by use of the active circuitry including at least one from among a GaN transistor, a SiC transistor, and a CMOS transistor, wherein the TC has a planar characteristic, associated with the processing surface, that is: set as a function of diamond grain size along the processing surface and thickness of the PC diamond layer, and to reduce phonon scattering at or near an interface, during use of the active circuitry.STFD.467PCT (S24-398) 2019. The apparatus of claim 16. further including a semiconductor device package configured to secure the PC diamond layer with a circuit layer that forms part of the semiconductor device package, the circuit layer including at least one from among a GaN transistor, a SiC transistor, and a CMOS circuit, wherein the PC diamond layer is configured to dissipate certain heat flux densities in excess of 1 kW / cm2, wherein the RMS roughness measure of the processing surface does not exceed 10 nm.

20. The apparatus of claim 16, further including a flip-chip type semiconductor device package configured to secure the PC diamond layer with a circuit layer that forms part of the semiconductor device package, wherein the PC diamond layer is integrated into the flip-chip package with an AIN or SiC interlayer to mitigate phonon mismatch.

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