Treatment method for final polishing process, and polished wafer

Abstract

The present application relates to a treatment method for a final polishing process, and a polished wafer. The treatment method for a final polishing process comprises: using a first polishing slurry to perform first polishing on a wafer; using a second polishing slurry to perform second polishing on the wafer, which has been subjected to the first polishing; and using a third polishing slurry to perform third polishing on the wafer, which has been subjected to the second polishing, wherein an alkaline additive is added into both the first polishing slurry and the second polishing slurry, and an alkaline additive is not added into the third polishing slurry.

Description

Processing methods for the final polishing process and polished wafers

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202411462415.0, filed in China on October 18, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of semiconductor manufacturing technology, and more specifically, to a processing method for a final polishing process and a polished wafer. Background Technology

[0004] In wafer production, typically, a crystal pulling furnace is first used to pull crystal rods, which are then cut into multiple crystal ingots. Each crystal ingot is then cut into thin initial wafers using methods such as multi-wire cutting. After the initial wafers undergo polishing, epitaxy, and other processes, the finished wafers can be obtained.

[0005] In the wafer polishing process, the typical sequence is double-sided polishing, primary cleaning, edge polishing, secondary cleaning, and final polishing. Final polishing is a crucial step in wafer surface treatment; its purpose is to remove any damage layers and surface irregularities that may have been introduced in previous processes, ensuring a high standard of flatness and cleanliness on the wafer surface. The quality of the wafer surface after the final polishing process directly determines the overall quality of the wafer.

[0006] However, the final polishing process mainly removes material by applying physical pressure to the wafer surface using abrasive particles in the polishing pad and polishing fluid. This material removal method has a low rate and is prone to causing defects on the wafer surface, which will have an adverse effect on the surface quality and performance of the wafer. Summary of the Invention

[0007] This section provides a general summary of the application, rather than a full disclosure of the entire scope or all features of the application.

[0008] The purpose of this application is to provide a processing method for the final polishing process, which can reduce defects on the wafer surface while removing damage from previous processes and performing mirror-finish repair.

[0009] To achieve the above objectives, according to a first aspect of this application, a processing method for a final polishing process is provided, comprising:

[0010] The wafer is first polished using the first polishing solution;

[0011] The wafer that has undergone the first polishing is then subjected to a second polishing using a second polishing slurry; and

[0012] A third polishing solution is used to perform a third polishing on the wafer that has undergone the second polishing.

[0013] The first and second polishing liquids both contain alkaline additives, while the third polishing liquid does not contain alkaline additives.

[0014] In some embodiments, the volume ratio of alkaline additives to solvent in the first polishing fluid can be greater than the volume ratio of alkaline additives to solvent in the second polishing fluid.

[0015] In some embodiments, the volume ratio of alkaline additive to solvent in the first polishing solution can be in the range of 1:2500 to 1:1500, and the volume ratio of alkaline additive to solvent in the second polishing solution can be in the range of 1:5000 to 1:2500.

[0016] In some implementations, the alkaline additive can be an inorganic base or an organic base.

[0017] In some embodiments, the alkaline additive may include KOH, NaOH, or NH4OH.

[0018] In some embodiments, the first polishing may be performed with a first target removal thickness, the second polishing may be performed with a second target removal thickness, and the third polishing may be performed with a third target removal thickness, wherein the first target removal thickness may be greater than the second target removal thickness, and the second target removal thickness may be greater than the third target removal thickness.

[0019] In some implementations, the ratio of the thickness removed from the first target, the thickness removed from the second target, and the thickness removed from the third target can be 6:3:1.

[0020] In some implementations, the sum of the first target removal thickness, the second target removal thickness, and the third target removal thickness can be greater than 150% of the thickness of the damaged layer of the wafer to be first polished.

[0021] According to a second aspect of this application, a polished wafer is provided, which is obtained by the processing method for the final polishing process according to the first aspect of this application, wherein the number of DIC defects with a size greater than 5 nm on the polished wafer is less than 5.

[0022] In some implementations, the number of DIC defects with a size greater than 5 nm on the polished wafer can be less than 3.

[0023] According to the above technical solution, the removal of the damage layer from the preceding process on the wafer surface and the mirror-finish repair can be completed step by step using three polishing steps. Furthermore, the first and second polishing steps, by combining chemical etching and physical abrasion, remove material from the wafer surface at an increased material removal rate, effectively shortening the time required to remove crystal defect areas from the wafer surface. This helps avoid the gradual amplification of defect areas and minute defects within them caused by physical abrasion, thereby reducing the risk of DIC defects and minimizing their formation on the wafer surface. Attached Figure Description

[0024] The features and advantages of embodiments of this application will become more readily understood from the following description with reference to the accompanying drawings. The drawings are not drawn to scale and some features may be enlarged or reduced to show details of specific components. In the drawings:

[0025] Figure 1 is a schematic diagram of a final polishing device according to related technologies.

[0026] Figure 2 is a schematic cross-sectional view of a polished wafer obtained by a processing method using related technologies for the final polishing process.

[0027] Figure 3 illustrates, for example, the schematic morphological features of a single DIC defect formed on a polished wafer.

[0028] Figure 4 is a flowchart of a processing method for a final polishing process according to an embodiment of this application.

[0029] Figure 5 is a comparison chart of the DIC defect test results of a series of polished wafers obtained by the processing method for the final polishing process using related technologies and a series of polished wafers obtained by the processing method for the final polishing process according to the embodiments of this application.

[0030] Figure 6 is another comparison chart of the DIC defect test results of a series of polished wafers obtained by the processing method for the final polishing process using related technologies and a series of polished wafers obtained by the processing method for the final polishing process according to the embodiments of this application.

[0031] Figure 7 is a schematic diagram of the distribution of DIC defects on the surface of a polished wafer obtained by using a processing method for the final polishing process with related technologies.

[0032] Figure 8 is a schematic diagram showing the distribution of DIC defects on the surface of a polished wafer obtained by the processing method for the final polishing process according to an embodiment of this application.

[0033] Figure 9 is a schematic diagram of an exemplary final polishing apparatus for performing a processing method for a final polishing process according to an embodiment of this application.

[0034] In the accompanying drawings, the same or corresponding technical features or components are represented by the same or corresponding reference numerals. Detailed Implementation

[0035] The present application will now be described in detail with reference to the accompanying drawings and exemplary embodiments. It should be noted that the following detailed description of the present application is for illustrative purposes only and is not intended to limit the scope of the application.

[0036] As mentioned earlier, before obtaining the finished wafer, it generally needs to go through manufacturing processes such as cutting, slicing, edge grinding, corrosive etching, double-sided grinding, double-sided polishing, edge polishing and final polishing.

[0037] Among the various polishing processes in the aforementioned manufacturing process, double-sided polishing is usually performed in an earlier stage, according to the order of implementation. Its purpose is to remove the damaged layer formed in the preceding processes such as cutting and double-sided grinding, and to improve the overall geometric characteristics of the wafer, such as flatness and thickness uniformity, mainly to make the wafer meet the basic physical properties.

[0038] Double-sided polishing is performed using double-sided polishing equipment. This equipment typically includes an upper and lower fixed disk arranged opposite each other, and a support disk positioned between them. The support disk holds the wafer to be polished. The upper and lower fixed disks each include an upper polishing pad and a lower polishing pad, respectively. In the double-sided polishing process, the upper and lower fixed disks simultaneously apply pressure to the wafer supported on the support disk, causing the upper and lower polishing pads to contact both sides of the wafer, respectively. The double-sided polishing of the wafer is achieved through the movement of the support disk relative to the upper and lower fixed disks.

[0039] Edge polishing is a process that is performed on the edges of the wafer. It is usually performed after double-sided polishing and aims to improve the flatness of the wafer edges and remove edge defects such as bumps and microcracks.

[0040] Edge polishing is performed using edge polishing equipment. Typically, edge polishing equipment includes a rotatable support disk and an edge polishing head. The support disk holds the wafer to be edge polished and rotates the wafer about its central axis. During edge polishing, the edge polishing head contacts the edge of the rotating wafer to polish its edges.

[0041] In the final stage of the various polishing processes in the aforementioned manufacturing process, the wafers that have already undergone polishing processes such as double-sided polishing and edge polishing will undergo a final polishing process. The final polishing process is usually performed on the front side of the wafer, and its purpose is to remove damage formed in the preceding processes, including the previous polishing steps, to achieve global planarization of the wafer surface. This is a fine finishing process to ensure that the wafer surface meets the quality standards required for subsequent device manufacturing (such as photolithography).

[0042] The final polishing process must be performed using a final polishing device capable of carrying out this fine work.

[0043] Figure 1 illustrates an exemplary final polishing apparatus 1 according to related art. As shown in Figure 1, the final polishing apparatus 1 includes a polishing head 2, a polishing table 3, and a polishing slurry supply line 4. The polishing head 2 holds the wafer to be polished at its lower part. The polishing table 3 has a polishing pad 5 disposed on its upper surface. The polishing slurry supply line 4 is used to supply polishing slurry to the polishing pad 5. During the polishing process, the wafer held by the polishing head 2 is pressed onto the polishing pad 5, so that the final polishing of the wafer is achieved by means of the relative rotation of the polishing pad 5 and the wafer.

[0044] Typically, the final polishing process includes rough polishing and fine polishing. In rough polishing, a polishing slurry with larger abrasive particles is used to remove micro-damage from the previous layer. In fine polishing, a polishing slurry with smaller abrasive particles is used to clean and mirror-finish the wafer surface, achieving the required flatness and smoothness.

[0045] In the final polishing process of related technologies, the polishing slurry used for final polishing removes the pre-damaged layer on the wafer surface solely through the physical grinding of abrasive particles. In this case, as mentioned above, different degrees of surface polishing effects are generally obtained by selecting abrasive particles of appropriate size. However, this purely physical grinding polishing process is prone to causing defects on the wafer surface.

[0046] Specifically, for heavily doped wafers, the wafers have high hardness due to their high oxygen content. At the same time, large crystal-originated particles (COPs) may accumulate at the center of the wafer, indicated by A on the polished wafer W shown in Figure 2. Therefore, after pre-processing such as double-sided grinding and low-temperature oxidation (LTO), the areas where COPs accumulate appear as crystal defect regions.

[0047] The inventors noted that due to the high surface hardness of heavily doped wafers and the low material removal rate during physical polishing, a considerable amount of time is required to remove crystal defect areas. This physical polishing process gradually enlarges the defect areas, causing small crystal defects within them to be magnified, thus forming Differential Interference Contrast (DIC) defects, indicated by B on the polished wafer W shown in Figure 2. It is understood that Figure 2 is not drawn to scale; for ease of understanding, both COP and DIC defects on the polished wafer W are schematically enlarged.

[0048] It should be understood that, in this application, a DIC defect refers to a step-like defect observed using differential interference contrast techniques, such as differential interference contrast microscopy. Figure 3 exemplarily illustrates the schematic morphological features of a single DIC defect. As shown in the figure, from an overall morphological perspective, a DIC defect is generally a raised step-like defect or a recessed pit-like defect. Furthermore, Figure 3 shows the span of the DIC defect in the horizontal direction and the span in the vertical direction, where the horizontal direction refers to the direction extending along the plane of the wafer surface, and the vertical direction is the direction perpendicular to the plane of the wafer surface.

[0049] Referring to Figure 3, the size of a DIC defect is characterized by its vertical span, i.e., the maximum height difference H. In other words, in this application, the size of a DIC defect refers to the height difference between its highest and lowest points. Specifically, the size of a DIC defect is the height difference, or elevation difference, between the highest and lowest points on the wafer surface at the location of the DIC defect, and its unit is nm.

[0050] It should be noted that the DIC defect in Figure 3 is exemplary and is only intended to illustrate the basic morphological features of the DIC defect, and does not mean that the DIC defect completely matches the morphology shown in Figure 3.

[0051] DIC defects are an important indicator affecting wafer quality and device performance. Excessive DIC defects not only reduce the yield and reliability of wafer products, but also limit the application of wafer products in high-end technology fields.

[0052] Therefore, it is desirable to propose a processing method for the final polishing process that can reduce the formation of DIC defects while removing damage from previous processes and performing mirror-finish repair on the wafer surface.

[0053] Referring to Figure 4, according to an embodiment of this application, a processing method for a final polishing process is provided, comprising:

[0054] S100: The wafer is first polished using the first polishing slurry;

[0055] S200: Perform a second polishing on the wafer that has undergone the first polishing using a second polishing slurry; and

[0056] S300: Perform a third polishing on the wafer after the second polishing using a third polishing slurry.

[0057] The first and second polishing liquids both contain alkaline additives, while the third polishing liquid does not contain alkaline additives.

[0058] It is understood that the first, second, and third polishing slurries are all solid-liquid mixtures containing abrasive particles. The abrasive particles are used to physically grind the wafer surface to remove surface material. Furthermore, the first, second, and third polishing slurries all contain solvents for dispersing or dissolving the abrasive particles and other additives such as chemical additives.

[0059] The steps described above are explained in detail below.

[0060] Step S100, also known as the first polishing step, is used to remove the previous process damage layer on the surface of the wafer.

[0061] Here, the pre-process damage layer on the surface of the wafer refers to the area where damage is introduced by the preceding processing (such as double-sided grinding) before the wafer begins to undergo the first polishing, such as mechanical damage like micro-scratches or cracks.

[0062] When an alkaline additive is added to the first polishing fluid, the first polishing fluid becomes alkaline, which allows the first polishing to combine the physical grinding action of abrasive particles with the chemical corrosion action generated by OH-, providing a very high material removal rate. This rapidly reduces the thickness of the damage layer from the previous process, shortens the time it takes for the defect area to expand into a DIC defect, and thus reduces the risk of forming a DIC defect.

[0063] In particular, the first polishing step can also utilize the tip stress principle of chemical etching to quickly remove severe damage. After the surface silicon oxide of the wafer is removed, OH- can be used to rapidly etch the wafer along the crystal lattice, thereby further reducing the risk of amplifying tiny crystal defects into DIC defects.

[0064] Step S200, also known as the second polishing step, is used to remove damage to the wafer surface caused by the physical abrasion and chemical etching of the first polishing step. An alkaline additive is added to the second polishing solution to achieve a relatively high material removal rate through the combination of material abrasion and chemical etching.

[0065] Step S300, also known as the third polishing step, is used to repair the damage to the wafer surface caused by the physical grinding and chemical etching of the second polishing, so as to achieve a mirror finish on the wafer surface and obtain a highly flat and smooth surface.

[0066] The third polishing solution does not contain alkaline additives to avoid excessive chemical corrosion of the wafer surface, thereby preventing the deterioration of the wafer surface flatness and ensuring the final quality of the wafer surface.

[0067] The above scheme utilizes three polishing steps to progressively remove the damage layer from previous processes on the wafer surface and achieve mirror-like repair. Furthermore, the first and second polishing steps, by combining chemical etching and physical abrasion, increase the material removal rate to thin the wafer, effectively shortening the time required to remove crystal defect areas from the wafer surface. This helps avoid the gradual amplification of defect areas and minute defects within them due to prolonged polishing, thereby reducing the risk of DIC defects.

[0068] The above approach can reduce the formation of DIC defects while performing pre-process damage removal and mirror-finishing repair on the wafer surface, which is beneficial for obtaining polished wafers with no damage layer, high mirror finish and reduced DIC defects.

[0069] According to embodiments of this application, a polished wafer is also provided, which is obtained by a processing method for a final polishing process according to embodiments of this application. The processing method for a final polishing process according to embodiments of this application includes the processing method for a final polishing process according to any of the above embodiments, and it is understood that it also includes the processing method for a final polishing process according to any of the embodiments mentioned below.

[0070] The number of DIC defects with a size of 5 nm or larger (i.e., greater than or equal to 5 nm) on the polished wafer obtained is less than 5.

[0071] Furthermore, the number of DIC defects with a size greater than 5nm on the polished wafer obtained in this way can be less than 3.

[0072] Specifically, the polished wafer is obtained by first polishing the wafer with a first polishing slurry, second polishing the wafer after the first polishing with a second polishing slurry, and third polishing the wafer after the second polishing with a third polishing slurry. The first and second polishing slurries contain alkaline additives, while the third polishing slurry does not contain alkaline additives.

[0073] Using a processing method for the final polishing process according to related technologies as Comparative Example A, and a processing method for the final polishing process according to an embodiment of this application as Example B, Figure 5 shows the statistical results of DIC defects of a series of polished wafers obtained in the case of Comparative Example A and a series of polished wafers obtained in the case of Example B in a box plot, wherein the vertical axis represents the number of DIC defects with a size of 5 nm or more on a single polished wafer.

[0074] Here, polished wafers specifically refer to wafers with a diameter of 300 mm or 12 inches.

[0075] As shown in Figure 5, the average number of DIC defects with a size greater than 5 nm on the polished wafer obtained by Comparative Example A was 2806.92, while the average number of DIC defects with a size greater than 5 nm on the polished wafer obtained by Example B was 0.166667. Therefore, it can be seen that the processing method for the final polishing process according to the embodiments of this application can effectively reduce the number of DIC defects on the polished wafer obtained therefrom.

[0076] Figure 6 shows the number of DIC defects larger than 5 nm in each of a series of polished wafers obtained in Comparative Example A and in Example B. Figure 6 illustrates the fluctuations in the number of DIC defects across the series of polished wafers.

[0077] As shown in Figure 6, the number of DIC defects in a series of polished wafers obtained in Example B is generally low and remains at a consistent level. This indicates that the processing method for the final polishing process according to the embodiments of this application has high reliability and stability in reducing DIC defects.

[0078] Furthermore, as shown in Figure 7, the polished wafer obtained in Comparative Example A exhibits a considerable number and dense distribution of DIC defects with dimensions greater than 5 nm on its surface. As shown in Figure 8, the polished wafer obtained in Example B exhibits an extremely small number of DIC defects with dimensions greater than 5 nm on its surface. Therefore, it is evident that the polished wafer obtained through the processing method for the final polishing process according to the embodiments of this application has a higher surface quality.

[0079] In some embodiments, the volume ratio of alkaline additive to solvent in the first polishing solution can be greater than the volume ratio of alkaline additive to solvent in the second polishing solution, so that the concentration of OH- in the first polishing solution is higher than the concentration of OH- in the second polishing solution.

[0080] In this case, the first polishing step has a stronger alkaline corrosion effect to achieve a relatively stronger polishing ability and a faster polishing rate, which enables the rapid removal of the damage layer from the previous process while reducing the thickness of the damage layer formed by physical action in this process.

[0081] The second polishing step has a weaker etching effect than the first polishing step, so that the polishing rate is relatively reduced. This is to remove the damage caused by the chemical etching in the first polishing step and the damage to the current layer, while avoiding the deterioration of parameters such as wafer flatness caused by too strong chemical action, thus achieving a relatively finer polishing effect than the first polishing step.

[0082] It is understood that the initial concentration of the alkaline additive added to the first polishing solution and the alkaline additive added to the second polishing solution can be the same. For example, the initial concentration of the alkaline additive can both be 50 wt%.

[0083] For alkaline additives with the same initial concentration, the amount of alkaline additive added to the solvent of the first polishing liquid can be greater than the amount of alkaline additive added to the solvent of the second polishing liquid.

[0084] In some embodiments, the volume ratio of alkaline additive to solvent in the first polishing solution can be in the range of 1:2500 to 1:1500, and the volume ratio of alkaline additive to solvent in the second polishing solution can be in the range of 1:5000 to 1:2500.

[0085] If the volume ratio of alkaline additives to solvents in the first polishing solution is higher than 1:1500, the chemical reaction will be too strong, which may lead to the deterioration of wafer flatness and other quality.

[0086] If the volume ratio of alkaline additives to solvents in the first polishing solution is less than 1:2500, the polishing rate of the first polishing process will be low, which is not conducive to suppressing the generation of DIC defects and is also not conducive to matching equipment capacity.

[0087] If the volume ratio of alkaline additives to solvents in the second polishing solution is less than 1:5000, the pH change of the second polishing solution will be too small, the chemical action will be insufficient, and it will not be able to effectively help reduce the formation of DIC defects.

[0088] In some implementations, the alkaline additive can be an inorganic base.

[0089] For example, alkaline additives may include KOH, NaOH, or NH4OH.

[0090] In some embodiments, the alkaline additive can be an organic base, such as aminomethylpropanol, quaternary ammonium salt, etc.

[0091] In some embodiments, the first polishing may be performed with a first target removal thickness, the second polishing may be performed with a second target removal thickness, and the third polishing may be performed with a third target removal thickness, wherein the first target removal thickness may be greater than the second target removal thickness, and the second target removal thickness may be greater than the third target removal thickness.

[0092] In this scenario, the wafer surface material can be removed by progressively decreasing the target removal amount. This not only helps to further reduce the probability of DIC defects, but also allows the amount to be removed in each step to be matched or adapted to the material removal rate of each polishing step. For example, a larger material removal rate can be matched with a larger amount to be removed, thereby optimizing the polishing process and improving the overall efficiency of the final polishing process.

[0093] In some implementations, the ratio of the first target removal thickness, the second target removal thickness, and the third target removal thickness can be 6:3:1 to better match the expected material removal rate of the three steps.

[0094] In addition, to ensure the stability of this process and to ensure sufficient removal of damage from previous processes, in some embodiments, the sum of the first target removal thickness, the second target removal thickness, and the third target removal thickness is greater than 150% of the thickness of the damaged layer of the wafer to be first polished.

[0095] It should be understood that the thickness of the preceding damaged layer is calculated based on the average value, and the damage layer may fluctuate due to process variations and spare parts replacements. In actual production, the fluctuation of the preceding damaged layer can be controlled within 20%. Based on this fluctuation range, the maximum actual damaged layer thickness can reach 120% of the average thickness of the preceding damaged layer. Combining statistical principles and the 1.5 Offset Sigma management practice in quality management, the maximum actual damaged layer thickness may reach approximately 150% of the average thickness of the preceding damaged layer. Therefore, by ensuring that the total target thickness removed is greater than the maximum possible actual damaged layer thickness, complete removal of damage from the preceding process can be ensured.

[0096] It should be noted that the damage layer here refers to the damage layer present on the wafer surface when the wafer is to be polished, or just before the first polishing. This damage layer is the area of ​​damage introduced onto the wafer surface by pre-polishing processes such as double-sided polishing.

[0097] It is understandable that the thickness of the damaged layer can be measured using a suitable measurement method depending on the wafer material, processing technology, and equipment conditions, and no restrictions are imposed here.

[0098] Figure 9 illustrates an exemplary final polishing apparatus 10 for performing embodiments according to this application. As shown in Figure 9, the final polishing apparatus 10 includes a polishing head 20, a polishing table 30, and a polishing slurry supply line 40. The polishing head 20 holds the wafer to be polished on its lower surface. A polishing pad 31 for contacting the wafer is provided on the upper surface of the polishing table 30. The polishing slurry supply line 40 provides polishing slurry to the polishing pad 31 so that the wafer is polished through contact between the polishing pad 31 and the wafer.

[0099] The final polishing equipment 10 may include a first container 50 for storing a first polishing slurry, a second container 60 for storing a second polishing slurry, and a third container 70 for storing a third polishing slurry. By configuring independent containers, it is convenient to adjust the order and amount of each polishing slurry used according to the corresponding polishing steps, thereby improving the flexibility and adaptability of the process.

[0100] The process of the final polishing process according to the embodiments of this application using the final polishing equipment 10 will be described below.

[0101] When performing final polishing on the wafer using the final polishing equipment 10, while the wafer is adsorbed and held by the polishing head 20, a certain flow rate of first polishing liquid is first supplied from the first container 50 to the polishing pad 31 via the polishing liquid supply line 40. After the polishing liquid is supplied to the polishing pad 31 and comes into contact with the wafer, the polishing head 20 and the polishing table 30 are driven to rotate relative to each other by the corresponding drive shafts of the polishing head 20 and the polishing table 30. Pressure is applied to the wafer by the polishing head 20 to complete the first polishing of the wafer.

[0102] Subsequently, similarly, a certain flow rate of second polishing fluid is supplied from the second container 60 to the polishing pad 31 via the polishing fluid supply line 40 for second polishing. Finally, a certain flow rate of third polishing fluid is supplied from the third container 70 to the polishing pad 31 via the polishing fluid supply line 40 for third polishing, thereby ultimately obtaining a polished wafer with the surface damage layer removed, the surface mirror-finished, and the number of DIC defects reduced.

[0103] Unless otherwise defined, the technical or scientific terms used in this application shall have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms “comprising” and “including” are open-ended, meaning that a system, apparatus, article, composition, formulation, or method that includes elements other than those listed after such terms in the claims is still considered to fall within the scope of the claims.

[0104] Although this application has been described with reference to exemplary embodiments, it should be understood that this application is not limited to the specific embodiments described and shown herein. Various changes can be made to the exemplary embodiments by those skilled in the art without departing from the scope defined by the claims of this application.

[0105] The features mentioned and / or shown in the above description of exemplary embodiments of this application can be combined in the same or similar manner with one or more other embodiments, combined with features in other embodiments, or substituted for corresponding features in other embodiments. These combined or substituted technical solutions should also be considered to be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A processing method for a final polishing process, comprising: The wafer is first polished using the first polishing solution; The wafer that has undergone the first polishing is then subjected to a second polishing using a second polishing fluid; as well as The wafer, after the second polishing, is then subjected to a third polishing using a third polishing solution. The first polishing liquid and the second polishing liquid both contain alkaline additives, while the third polishing liquid does not contain alkaline additives.

2. The process for finishing polishing process according to claim 1, wherein, The volume ratio of the alkaline additive to the solvent in the first polishing solution is greater than the volume ratio of the alkaline additive to the solvent in the second polishing solution.

3. The processing method for the final polishing process according to claim 1, wherein, The volume ratio of the alkaline additive to the solvent in the first polishing liquid is in the range of 1:2500 to 1:1500, and the volume ratio of the alkaline additive to the solvent in the second polishing liquid is in the range of 1:5000 to 1:2500.

4. The processing method for the final polishing process according to claim 1, wherein, The alkaline additive is an inorganic or organic alkali.

5. The processing method for the final polishing process according to claim 1, wherein, The alkaline additives include KOH, NaOH, or NH4OH.

6. The processing method for the final polishing process according to claim 1, wherein, The first polishing is performed with a first target removal thickness, the second polishing is performed with a second target removal thickness, and the third polishing is performed with a third target removal thickness, wherein the first target removal thickness is greater than the second target removal thickness, and the second target removal thickness is greater than the third target removal thickness.

7. The processing method for the final polishing process according to claim 6, wherein, The ratio of the thickness removed from the first target, the thickness removed from the second target, and the thickness removed from the third target is 6:3:

1.

8. The processing method for the final polishing process according to claim 6, wherein, The sum of the first target removal thickness, the second target removal thickness, and the third target removal thickness is greater than 150% of the thickness of the damaged layer of the wafer to be polished.

9. A polished wafer, obtained by the processing method for a final polishing process according to any one of claims 1 to 8, wherein the number of DIC defects with a size greater than 5 nm on the polished wafer is less than 5.

10. The polished wafer according to claim 9, wherein, The number of DIC defects with a size greater than 5nm on the polished wafer is less than 3.

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