Semiconductor structure and method for forming same

Abstract

The present application provides a semiconductor structure and a method for forming same. The semiconductor structure comprises: a semiconductor substrate, wherein a highly-doped epitaxial layer and a low-doped epitaxial layer are sequentially formed on a first surface of the semiconductor substrate, and the semiconductor substrate comprises a first region and a second region; a first portion of a semiconductor device, which is located on the low-doped epitaxial layer in the first region and uses the low-doped epitaxial layer in the first region as a channel; and a second portion of the semiconductor device, which is located in the low-doped epitaxial layer in the second region, wherein the second portion of the semiconductor device passes through the low-doped epitaxial layer and is electrically connected to the highly-doped epitaxial layer. The semiconductor structure and the method for forming same provided by the present application can improve the device reliability and device performance of existing silicon carbide devices.

Description

A semiconductor structure and its formation method Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] Power modules offer features such as thermal management, electrical insulation, mechanical protection, optimized electrical performance, and low thermal conductivity. Traditional silicon modules are used to package third-generation semiconductor chips such as silicon carbide and gallium nitride. However, the high parasitic stray parameters in the gate and power circuits hinder the third-generation semiconductor chips from achieving their superior performance. Traditional silicon carbide power modules are packaged on the back of the chip using a multi-layer substrate, resulting in high cost, high substrate resistance, high thermal resistance, and high parasitic inductance in the circuit.

[0003] Therefore, it is necessary to provide a more efficient and reliable technical solution to improve the reliability and performance of existing third-generation semiconductor devices such as silicon carbide and gallium nitride. Summary of the Invention

[0004] The purpose of this invention is to improve the reliability and performance of existing silicon carbide devices.

[0005] One aspect of this application provides a method for forming a semiconductor structure, comprising: providing a semiconductor substrate, wherein a highly doped epitaxial layer and a lightly doped epitaxial layer are sequentially formed on a first surface of the semiconductor substrate, the semiconductor substrate including a first region and a second region; forming a first portion of a semiconductor device on the lightly doped epitaxial layer of the first region using the lightly doped epitaxial layer of the first region as a channel; and forming a second portion of the semiconductor device in the lightly doped epitaxial layer of the second region, the second portion of the semiconductor device penetrating the lightly doped epitaxial layer and electrically connected to the highly doped epitaxial layer.

[0006] In some embodiments of this application, a method for forming a second portion of the semiconductor device in a lightly doped epitaxial layer in the second region includes: forming a trench in the second region that penetrates the lightly doped epitaxial layer and exposes the heavily doped epitaxial layer; forming a heavily doped contact layer in the lightly doped epitaxial layer on the sidewalls of the trench; forming an ohmic contact layer on the surfaces of the heavily doped epitaxial layer at the bottom of the trench and the heavily doped contact layer on the sidewalls of the trench; and forming a conductive layer in the trench that fills the trench and electrically connects the ohmic contact layer.

[0007] In some embodiments of this application, a method for forming a second portion of the semiconductor device in a lightly doped epitaxial layer in the second region includes: forming a highly doped contact layer in the second region that penetrates the lightly doped epitaxial layer and is electrically connected to the highly doped epitaxial layer; and forming a conductive layer on the top surface of the highly doped contact layer that is electrically connected to the highly doped contact layer.

[0008] In some embodiments of this application, a method for forming a second portion of the semiconductor device in a lightly doped epitaxial layer in the second region includes: forming a highly doped contact layer in the second region that penetrates the lightly doped epitaxial layer and is electrically connected to the highly doped epitaxial layer; forming an ohmic contact layer in the highly doped contact layer that penetrates the highly doped contact layer and is electrically connected to the highly doped epitaxial layer; and forming a conductive layer on the top surface of the ohmic contact layer and the highly doped contact layer that is electrically connected to the ohmic contact layer and the highly doped contact layer.

[0009] In some embodiments of this application, a method for forming a second portion of the semiconductor device in a lightly doped epitaxial layer in the second region includes: forming a conductive layer in the second region that electrically connects the lightly doped epitaxial layer to the heavily doped epitaxial layer.

[0010] In some embodiments of this application, the semiconductor substrate further includes a second surface opposite to the first surface, and the method of forming the semiconductor structure further includes forming a heat dissipation structure on the second surface.

[0011] In some embodiments of this application, the heat dissipation structure includes: a heat-dissipating metal layer or thermally conductive silicone grease.

[0012] In some embodiments of this application, the semiconductor substrate is made of undoped silicon carbide, the highly doped epitaxial layer is made of doped silicon carbide, and the low-doped epitaxial layer is made of doped silicon carbide.

[0013] In some embodiments of this application, the doping concentration of the highly doped epitaxial layer is greater than the doping concentration of the poorly doped epitaxial layer, and the doping concentration of the highly doped epitaxial layer is 1E18 to 1E21 cm⁻¹. -3 The doping concentration of the low-doped epitaxial layer is from 1E16 to 3E19 cm⁻¹. -3 .

[0014] In some embodiments of this application, the first region includes a core device region and a protection zone surrounding the core device region, and the second region includes a dicing region.

[0015] Another aspect of this application provides a semiconductor structure, comprising: a semiconductor substrate, wherein a highly doped epitaxial layer and a low-doped epitaxial layer are sequentially formed on a first surface of the semiconductor substrate, the semiconductor substrate including a first region and a second region; a first portion of a semiconductor device located on the low-doped epitaxial layer in the first region, with the low-doped epitaxial layer in the first region serving as a channel; and a second portion of the semiconductor device located in the low-doped epitaxial layer in the second region, the second portion of the semiconductor device penetrating the low-doped epitaxial layer and electrically connected to the highly doped epitaxial layer.

[0016] In some embodiments of this application, the second portion of the semiconductor device includes: a trench through the second region where a lightly doped epitaxial layer exposes the heavily doped epitaxial layer; a heavily doped contact layer in the lightly doped epitaxial layer located on the sidewalls of the trench; an ohmic contact layer on the surface of the heavily doped epitaxial layer at the bottom of the trench and the heavily doped contact layer on the sidewalls of the trench; and a conductive layer located in the trench, filling the trench and electrically connecting the ohmic contact layer.

[0017] In some embodiments of this application, the second portion of the semiconductor device includes: a lightly doped epitaxial layer penetrating the second region and a highly doped contact layer electrically connected to the highly doped epitaxial layer; and a conductive layer located on the top surface of the highly doped contact layer and electrically connected to the highly doped contact layer.

[0018] In some embodiments of this application, the second portion of the semiconductor device includes: a lightly doped epitaxial layer penetrating the second region and electrically connected to a highly doped epitaxial layer; an ohmic contact layer penetrating the highly doped contact layer and electrically connected to the highly doped epitaxial layer; and a conductive layer located on the top surface of the ohmic contact layer and the highly doped contact layer and electrically connected to the ohmic contact layer and the highly doped contact layer.

[0019] In some embodiments of this application, the second portion of the semiconductor device includes: a conductive layer electrically connected to the highly doped epitaxial layer through the second region.

[0020] In some embodiments of this application, the semiconductor substrate further includes a second surface opposite to the first surface, and the semiconductor structure further includes a heat dissipation structure located on the second surface.

[0021] In some embodiments of this application, the heat dissipation structure includes: a heat-dissipating metal layer or thermally conductive silicone grease.

[0022] In some embodiments of this application, the semiconductor substrate is made of undoped silicon carbide, the highly doped epitaxial layer is made of doped silicon carbide, and the low-doped epitaxial layer is made of doped silicon carbide.

[0023] In some embodiments of this application, the doping concentration of the highly doped epitaxial layer is greater than the doping concentration of the poorly doped epitaxial layer, and the doping concentration of the highly doped epitaxial layer is 1E18 to 1E21 cm⁻¹. -3 The doping concentration of the low-doped epitaxial layer is from 1E16 to 3E19 cm⁻¹. -3 .

[0024] In some embodiments of this application, the first region includes a core device region and a protection zone surrounding the core device region, and the second region includes a dicing region.

[0025] This application provides a semiconductor structure and a method for forming the same, which can improve the device reliability and device performance of existing silicon carbide devices. Attached Figure Description

[0026] The following accompanying drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals denote similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting and exemplary, and the drawings are for illustrative purposes only and are not intended to limit the scope of this application. Other embodiments may similarly fulfill the inventive intent of this application. It should be understood that the drawings are not drawn to scale. Wherein:

[0027] Figures 1 to 9 are schematic diagrams of the steps in the method for forming a semiconductor structure according to some embodiments of this application;

[0028] Figure 10 is a schematic diagram of the semiconductor structure described in some other embodiments of this application;

[0029] Figure 11 is a schematic diagram of the semiconductor structure described in some other embodiments of this application;

[0030] Figure 12 is a schematic diagram of the semiconductor structure described in some other embodiments of this application. Detailed Implementation

[0031] The following description provides specific application scenarios and requirements for this application, intended to enable those skilled in the art to make and use the content of this application. Various partial modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but rather to the widest scope consistent with the claims.

[0032] The technical solution of the present invention will be described in detail below with reference to the embodiments and accompanying drawings.

[0033] Figures 1 to 9 are schematic diagrams of each step in the method for forming a semiconductor structure according to the embodiments of this application. The method for forming a semiconductor structure according to the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0034] Referring to Figure 1, a semiconductor substrate 100 is provided, wherein a highly doped epitaxial layer 110 and a low-doped epitaxial layer 120 are sequentially formed on the first surface of the semiconductor substrate 100, and the semiconductor substrate 100 includes a first region 101 and a second region 102.

[0035] In some embodiments of this application, the semiconductor substrate 100 is made of undoped silicon carbide, the highly doped epitaxial layer 110 is made of doped silicon carbide, and the lightly doped epitaxial layer 120 is made of doped silicon carbide. The highly doped epitaxial layer 110 and the lightly doped epitaxial layer 120 have the same doping type, for example, N-type.

[0036] In some embodiments of this application, the doping concentration of the highly doped epitaxial layer 110 is greater than the doping concentration of the low-doped epitaxial layer 120, and the doping concentration of the highly doped epitaxial layer 110 is 1E18 to 1E21 cm⁻¹. -3 The doping concentration of the low-doped epitaxial layer 120 is from 1E16 to 3E19 cm⁻¹. -3 .

[0037] In some embodiments of this application, the thickness of the semiconductor substrate 100 is 2-200 micrometers, the thickness of the highly doped epitaxial layer 110 is 2-200 micrometers, and the thickness of the low-doped epitaxial layer 120 is 2-200 micrometers.

[0038] In some embodiments of this application, the method of sequentially forming the highly doped epitaxial layer 110 and the lightly doped epitaxial layer 120 on the first surface of the semiconductor substrate 100 includes: performing a first in-situ doping epitaxial growth process to form the highly doped epitaxial layer 110 on the first surface of the semiconductor substrate 100; and performing a second in-situ doping epitaxial growth process to form the lightly doped epitaxial layer 120 on the surface of the highly doped epitaxial layer 110. The dopant source gas concentration in the second in-situ doping epitaxial growth process is lower than the dopant source gas concentration in the first in-situ doping epitaxial growth process.

[0039] In some embodiments of this application, the first region 101 includes a core device region and a protection zone surrounding the core device region, and the second region 102 includes a dicing region.

[0040] Then, referring to Figures 2 to 9, a first portion of a semiconductor device is formed on the low-doped epitaxial layer 120 of the first region 101, using the low-doped epitaxial layer 120 of the first region 101 as a channel; a second portion of the semiconductor device is formed in the low-doped epitaxial layer 120 of the second region 102, the second portion of the semiconductor device penetrating the low-doped epitaxial layer 120 and electrically connected to the high-doped epitaxial layer 110.

[0041] It should be noted that the technical solution of this application is not limited to a specific type of semiconductor device. The semiconductor devices described in this application are, for example, any one or more of diodes, MOSFETs, IGBTs, and HMETs. Therefore, the specific structures of the first and second parts of the semiconductor device vary depending on the type of semiconductor device. For example, when the semiconductor device is a transistor, the first part includes a source portion and a gate portion, and the second part includes a drain portion. When the semiconductor device is a diode, the first part includes an anode, and the second part includes a cathode. When the semiconductor device is an IGBT, the first part includes an emitter portion and a gate portion, and the second part includes a collector portion. When the semiconductor device is an HMET, the first part includes a source portion and a gate portion, and the second part includes a drain portion. The basic structures and fabrication processes of semiconductor devices such as diodes, MOSFETs, IGBTs, and HMETs are known to those skilled in the art. This application uses only transistors as an example for illustration. Those skilled in the art should be able to understand the structure and process of other semiconductor devices in the technical solutions of this application based on the transistor examples disclosed in this application.

[0042] Furthermore, the technical solution of this application does not limit the formation order of the first part and the second part of the semiconductor device. When both the first part and the second part of the semiconductor device include multiple steps, the respective steps of the first part and the second part of the semiconductor device can be mixed together, rather than forming the first part first and then the second part.

[0043] As described above, this application will continue the description below using a transistor as an example of a semiconductor device.

[0044] Referring to Figure 2, a well region 121 and a first high-concentration implantation region 122 are formed in the lightly doped epitaxial layer 120 of the first region 101 using an ion implantation process. The well region 121 and the first high-concentration implantation region 122 have the same doping type, but the opposite doping type to that of the lightly doped epitaxial layer 120, for example, P-type. The well region 121 and the first high-concentration implantation region 122 belong to the first part of the semiconductor device.

[0045] In the technical solution of this application, the structure of the first part of the semiconductor device is the same as the conventional structure. The key difference is that the second part of the semiconductor device is improved and placed in the second region. Therefore, this application only provides a brief description of the first part of the semiconductor device and focuses on describing the second part. Therefore, the detailed structure and process of the well region 121 and the first high-concentration implantation region 122 will not be described in detail here. Similar situations will not be described separately later.

[0046] Referring to Figure 3, a trench 130 is formed in the second region 102, penetrating the lightly doped epitaxial layer 120 and exposing the heavily doped epitaxial layer 110. In some embodiments of this application, the angle between the sidewall and the bottom surface of the trench 130 can be a right angle or an obtuse angle. When the angle between the sidewall and the bottom surface of the trench 130 is an obtuse angle, it facilitates subsequent ion implantation into the lightly doped epitaxial layer on the sidewall of the trench to form a heavily doped contact layer.

[0047] Referring to Figure 4, a highly doped contact layer 140 is formed in the lightly doped epitaxial layer 120 on the sidewall of the trench 130 using an ion implantation process, and a second high-concentration implantation region 123 is formed in the well region 121. The highly doped contact layer 140 and the second high-concentration implantation region 123 can be formed simultaneously or separately. The highly doped contact layer 140 belongs to the second part of the semiconductor device, and the second high-concentration implantation region 123 belongs to the first part of the semiconductor device.

[0048] In some embodiments of this application, the highly doped contact layer 140 is N-type doped with a doping concentration of 1E18 to 1E21 cm⁻¹. -3 .

[0049] In some embodiments of this application, after forming the highly doped contact layer 140 and the second high-concentration implantation region 123, a high-temperature annealing process is performed on the semiconductor structure to activate all doped ions.

[0050] Referring to Figure 5, a field oxide 124 covering the first high-concentration implantation region 122 and a gate structure 125 partially covering the adjacent second high-concentration implantation region 123 are formed in the first region 101. The field oxide 124 and the gate structure 125 are part of the first portion of the semiconductor device and will not be described in detail here. The gate structure 125 may include, for example, a gate dielectric layer, a gate layer, and sidewalls. An interlayer dielectric layer (omitted here) is also formed on the top surface and sidewalls of the gate structure 125.

[0051] Referring to Figure 6, an ohmic contact layer 150 is formed on the surface of the highly doped epitaxial layer 110 at the bottom of the trench 130, the highly doped contact layer 140 on the sidewall of the trench 130, and the surface of the well region 121 and the second high-concentration implantation region 123.

[0052] In some embodiments of this application, the material of the ohmic contact layer 150 includes any one or more of Ni, AlNi, and TiAl.

[0053] Referring to FIG7, a conductive layer 160 is formed in the trench 130 to fill the trench 130 and electrically connect the ohmic contact layer 150. The conductive layer 160 also covers the field oxide 124 and the gate structure 125 and electrically connects the ohmic contact layer 150 in the first region 101.

[0054] In some embodiments of this application, the material of the conductive layer 160 includes any one or more of aluminum, copper, and aluminum-copper alloys.

[0055] Referring to Figure 8, an isolation structure 170 is formed above the field oxide 124, penetrating the conductive layer 160. The isolation structure 170 may also extend partially to the surface of the conductive layer 160.

[0056] In some embodiments of this application, the material of the isolation structure 170 includes polyimide.

[0057] Referring to Figure 8, in the technical solution of this application, the first part of the semiconductor device includes a well region 121, a first highly doped region 122, a second highly doped region 123, an ohmic contact layer 150, a gate structure 125, a field oxide 124, and a conductive layer 160 located in the first region 101. The conductive layer 160 includes a gate portion (gate structure 125) and a source portion (the conductive layer 160 of the first region 101 serves as the source contact). The second part of the semiconductor device includes a highly doped contact layer 140, an ohmic contact layer 150, and a conductive layer 160 located in the second region 102, including a drain portion (the conductive layer 160 of the second region 102 serves as the drain contact).

[0058] Referring to FIG9, in some embodiments of this application, the semiconductor substrate 100 further includes a second surface opposite to the first surface, and the method of forming the semiconductor structure further includes: forming a heat dissipation structure 180 on the second surface.

[0059] In some embodiments of this application, the heat dissipation structure 180 includes a thermal contact metal layer or thermal grease.

[0060] Compared to housing, molding, and smart p2 packaging technologies, the technical solution of this application can have low power loop parasitic inductance and low gate loop parasitic inductance.

[0061] Compared with traditional packaging technology, the technical solution of this application can save costs and reduce thickness because it does not have a substrate, solder and base plate, and has low thermal conductivity and high PC cycle capability.

[0062] Compared to simple chip processes, the technical solution of this application does not require substrate thinning, thus saving costs and having low substrate resistivity.

[0063] Figure 10 is a schematic diagram of the semiconductor structure described in some other embodiments of this application. The main difference between the embodiment shown in Figure 10 and the embodiment shown in Figure 9 is that the second part of the semiconductor device in the second region is different; the rest of the structure is similar or the same.

[0064] Referring to FIG10, in some other embodiments of this application, a method for forming a second portion of the semiconductor device in the low-doped epitaxial layer 120 of the second region 102 includes: forming a highly doped contact layer 140 in the second region 102 that penetrates the low-doped epitaxial layer 120 and is electrically connected to the highly doped epitaxial layer 110; and forming a conductive layer 160 on the top surface of the highly doped contact layer 140 that is electrically connected to the highly doped contact layer 140.

[0065] Furthermore, unlike the embodiment shown in FIG9, the conductive layer 160 in the first region 101 is fabricated separately, and not together with the conductive layer 160 in the second region 102. The field oxide 124 and the isolation structure 170 also cover the second region 102.

[0066] Figure 11 is a schematic diagram of the semiconductor structure described in some other embodiments of this application. The main difference between the embodiment shown in Figure 11 and the embodiment shown in Figure 10 is that an ohmic contact layer 150 is also formed in the highly doped contact layer 140, which penetrates the highly doped contact layer 140 and is electrically connected to the highly doped epitaxial layer 110.

[0067] Referring to FIG11, in some other embodiments of this application, a method for forming a second portion of the semiconductor device in the low-doped epitaxial layer 120 of the second region 102 includes: forming a highly doped contact layer 140 in the second region 102 that penetrates the low-doped epitaxial layer 120 and is electrically connected to the highly doped epitaxial layer 110; forming an ohmic contact layer 150 in the highly doped contact layer 140 that penetrates the highly doped contact layer 140 and is electrically connected to the highly doped epitaxial layer 110; and forming a conductive layer 160 on the top surface of the ohmic contact layer 150 and the highly doped contact layer 140 that is electrically connected to the ohmic contact layer 150 and the highly doped contact layer 140.

[0068] Figure 12 is a schematic diagram of the semiconductor structure described in some other embodiments of this application. The main difference between the embodiment shown in Figure 12 and the embodiment shown in Figure 10 is that the highly doped contact layer 140 is omitted, and the conductive layer 160 directly connects to the highly doped epitaxial layer 110 through the low-doped epitaxial layer 120.

[0069] Referring to FIG12, in some other embodiments of this application, a method for forming a second portion of the semiconductor device in the low-doped epitaxial layer 110 of the second region 102 includes: forming a conductive layer 160 in the second region 102 that penetrates the low-doped epitaxial layer 120 and is electrically connected to the high-doped epitaxial layer 110.

[0070] The embodiments of this application, while keeping the structure of the first region 101 basically unchanged, have designed various structures for realizing the electrical connection between the conductive layer 160 and the low-doped epitaxial layer 120 and the high-doped epitaxial layer 110.

[0071] This application provides a method for forming a semiconductor structure, which can improve the device reliability and device performance of existing silicon carbide devices.

[0072] Some embodiments of this application also provide a semiconductor structure, referring to FIG9, including: a semiconductor substrate 100, on which a highly doped epitaxial layer 110 and a low-doped epitaxial layer 120 are sequentially formed on a first surface, the semiconductor substrate 100 including a first region 101 and a second region 102; a first portion of a semiconductor device located on the low-doped epitaxial layer 120 in the first region 101 with the low-doped epitaxial layer 120 in the first region 101 as a channel; and a second portion of the semiconductor device located in the low-doped epitaxial layer 120 in the second region 102, the second portion of the semiconductor device penetrating the low-doped epitaxial layer 120 and electrically connected to the highly doped epitaxial layer 110.

[0073] In some embodiments of this application, the semiconductor substrate 100 is made of undoped silicon carbide, the highly doped epitaxial layer 110 is made of doped silicon carbide, and the lightly doped epitaxial layer 120 is made of doped silicon carbide. The highly doped epitaxial layer 110 and the lightly doped epitaxial layer 120 have the same doping type, for example, N-type.

[0074] In some embodiments of this application, the doping concentration of the highly doped epitaxial layer 110 is greater than the doping concentration of the low-doped epitaxial layer 120, and the doping concentration of the highly doped epitaxial layer 110 is 1E18 to 1E21 cm⁻¹. -3 The doping concentration of the low-doped epitaxial layer 120 is from 1E16 to 3E19 cm⁻¹. -3 .

[0075] In some embodiments of this application, the thickness of the semiconductor substrate 100 is 2-200 micrometers, the thickness of the highly doped epitaxial layer 110 is 2-200 micrometers, and the thickness of the low-doped epitaxial layer 120 is 2-200 micrometers.

[0076] In some embodiments of this application, the method of sequentially forming the highly doped epitaxial layer 110 and the lightly doped epitaxial layer 120 on the first surface of the semiconductor substrate 100 includes: performing a first in-situ doping epitaxial growth process to form the highly doped epitaxial layer 110 on the first surface of the semiconductor substrate 100; and performing a second in-situ doping epitaxial growth process to form the lightly doped epitaxial layer 120 on the surface of the highly doped epitaxial layer 110. The dopant source gas concentration in the second in-situ doping epitaxial growth process is lower than the dopant source gas concentration in the first in-situ doping epitaxial growth process.

[0077] In some embodiments of this application, the first region 101 includes a core device region and a protection zone surrounding the core device region, and the second region 102 includes a dicing region.

[0078] It should be noted that the technical solution of this application is not limited to a specific type of semiconductor device. The semiconductor devices described in this application are, for example, any one or more of diodes, MOSFETs, IGBTs, and HMETs. Therefore, the specific structures of the first and second parts of the semiconductor device vary depending on the type of semiconductor device. For example, when the semiconductor device is a transistor, the first part includes a source portion and a gate portion, and the second part includes a drain portion. When the semiconductor device is a diode, the first part includes an anode, and the second part includes a cathode. When the semiconductor device is an IGBT, the first part includes an emitter portion and a gate portion, and the second part includes a collector portion. When the semiconductor device is an HMET, the first part includes a source portion and a gate portion, and the second part includes a drain portion. The basic structures and fabrication processes of semiconductor devices such as diodes, MOSFETs, IGBTs, and HMETs are known to those skilled in the art. This application uses only transistors as an example for illustration. Those skilled in the art should be able to understand the structure and process of other semiconductor devices in the technical solutions of this application based on the transistor examples disclosed in this application.

[0079] Referring to Figure 9, in the technical solution of this application, the first part of the semiconductor device includes a well region 121, a first high-concentration doped region 122, a second high-concentration doped region 123, an ohmic contact layer 150, a gate structure 125, a field oxide 124, and a conductive layer 160 located in the first region 101. The conductive layer 160 includes a gate portion (gate structure 125) and a source portion (the conductive layer 160 of the first region 101 serves as the source contact).

[0080] Referring to FIG9, in some embodiments of this application, the second portion of the semiconductor device includes: a trench through which a low-doped epitaxial layer 120 exposes the high-doped epitaxial layer 110 in the second region 102; a high-doped contact layer 140 located in the low-doped epitaxial layer 120 on the sidewalls of the trench; an ohmic contact layer 150 located on the surface of the high-doped epitaxial layer 110 at the bottom of the trench and the high-doped contact layer 140 on the sidewalls of the trench; and a conductive layer 160 located in the trench, filling the trench and electrically connecting the ohmic contact layer 150.

[0081] In some embodiments of this application, the well region 121 and the first high-concentration implantation region 122 have the same doping type, and the doping type is opposite to that of the low-doped epitaxial layer 120, for example, P-type.

[0082] In some embodiments of this application, the highly doped contact layer 140 is N-type doped with a doping concentration of 1E18 to 1E21 cm⁻¹. -3 .

[0083] In some embodiments of this application, the material of the ohmic contact layer 150 includes any one or more of Ni, AlNi, and TiAl.

[0084] In some embodiments of this application, the conductive layer 160 also covers the field oxide 124 and the gate structure 125 and is electrically connected to the ohmic contact layer 150 in the first region 101.

[0085] In some embodiments of this application, the material of the conductive layer 160 includes any one or more of aluminum, copper, and aluminum-copper alloys.

[0086] Referring to Figure 9, an isolation structure 170 is also formed above the field oxide 124, penetrating the conductive layer 160. The isolation structure 170 may also extend partially to the surface of the conductive layer 160.

[0087] In some embodiments of this application, the material of the isolation structure 170 includes polyimide.

[0088] Referring to FIG9, in some embodiments of this application, the semiconductor substrate 100 further includes a second surface opposite to the first surface, and the semiconductor structure further includes a heat dissipation structure 180 located on the second surface.

[0089] In some embodiments of this application, the heat dissipation structure 180 includes a heat dissipation metal layer or thermally conductive silicone grease.

[0090] Compared to housing, molding, and smart p2 packaging technologies, the technical solution of this application can have low power loop parasitic inductance and low gate loop parasitic inductance.

[0091] Compared with traditional packaging technology, the technical solution of this application can save costs and reduce thickness because it does not have a substrate, solder and base plate, and has low thermal conductivity and high PC cycle capability.

[0092] Compared to simple chip processes, the technical solution of this application does not require substrate thinning, thus saving costs and having low substrate resistivity.

[0093] Referring to FIG10, in some other embodiments of this application, the second part of the semiconductor device includes: a low-doped epitaxial layer 120 penetrating the second region 102 and electrically connected to the high-doped epitaxial layer 110; and a conductive layer 160 located on the top surface of the high-doped contact layer 140 and electrically connected to the high-doped contact layer 140.

[0094] Referring to FIG11, in some other embodiments of this application, the second part of the semiconductor device includes: a highly doped contact layer 140 electrically connected to the highly doped epitaxial layer 110 through a low-doped epitaxial layer 120 in the second region 102; an ohmic contact layer 150 electrically connected to the highly doped epitaxial layer 110 through the highly doped contact layer 140; and a conductive layer 160 located on the top surface of the ohmic contact layer 150 and the highly doped contact layer 140 electrically connected to the ohmic contact layer 150 and the highly doped contact layer 140.

[0095] Referring to FIG12, in some other embodiments of this application, the second part of the semiconductor device includes a conductive layer 160 electrically connected to the highly doped epitaxial layer 110 through a low-doped epitaxial layer 120 in the second region 102.

[0096] The embodiments of this application, while keeping the structure of the first region 101 basically unchanged, have designed various structures for realizing the electrical connection between the conductive layer 160 and the low-doped epitaxial layer 120 and the high-doped epitaxial layer 110.

[0097] This application provides a semiconductor structure and a method for forming the same, which can improve the device reliability and device performance of existing silicon carbide devices.

[0098] In summary, after reading this application, those skilled in the art will understand that the foregoing application content is presented by way of example only and is not restrictive. Although not explicitly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.

[0099] It should be understood that the term "and / or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it may be directly on the other element, or there may be intermediate elements present. Conversely, the term "directly" means without intermediate elements. It should also be understood that the terms "comprising," "including," "comprise," or "including" as used in this application specify the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0100] It should also be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of this application, a first element in some embodiments may be referred to as a second element in other embodiments. The same reference numerals or the same reference signs denote the same elements throughout the specification.

[0101] Furthermore, this application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, differences from the illustrated shapes are foreseeable due to factors such as manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in shape caused, for example, by manufacturing processes. For instance, etched areas shown as rectangular typically have circular or curved features. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to illustrate the actual shape of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

Claims

1. A method of forming a semiconductor structure, comprising: include: A semiconductor substrate is provided, wherein a highly doped epitaxial layer and a low doped epitaxial layer are sequentially formed on a first surface of the semiconductor substrate, and the semiconductor substrate includes a first region and a second region; A first portion of a semiconductor device is formed on the low-doped epitaxial layer in the first region, using the low-doped epitaxial layer in the first region as a channel; A second portion of the semiconductor device is formed in the low-doped epitaxial layer of the second region, the second portion of the semiconductor device extending through the low-doped epitaxial layer and electrically connected to the high-doped epitaxial layer.

2. The method of forming a semiconductor structure of claim 1, wherein, A method for forming a second portion of the semiconductor device in a lightly doped epitaxial layer in the second region includes: A trench is formed in the second region that penetrates the low-doped epitaxial layer to expose the high-doped epitaxial layer; A highly doped contact layer is formed in the low-doped epitaxial layer on the sidewall of the trench; An ohmic contact layer is formed on the surfaces of the highly doped epitaxial layer at the bottom of the trench and the highly doped contact layer on the sidewall of the trench. A conductive layer is formed in the trench to fill the trench and electrically connect the ohmic contact layer.

3. The method of forming a semiconductor structure of claim 1, wherein, A method for forming a second portion of the semiconductor device in a lightly doped epitaxial layer in the second region includes: A highly doped contact layer is formed in the second region, penetrating the low-doped epitaxial layer and electrically connecting the highly doped epitaxial layer; A conductive layer electrically connected to the highly doped contact layer is formed on the top surface of the highly doped contact layer.

4. The method of forming a semiconductor structure of claim 1, wherein, A method for forming a second portion of the semiconductor device in a lightly doped epitaxial layer in the second region includes: A highly doped contact layer is formed in the second region, penetrating the low-doped epitaxial layer and electrically connecting the highly doped epitaxial layer; An ohmic contact layer is formed in the highly doped contact layer, which penetrates the highly doped contact layer and electrically connects to the highly doped epitaxial layer. A conductive layer is formed on the top surface of the ohmic contact layer and the highly doped contact layer to electrically connect the ohmic contact layer and the highly doped contact layer.

5. The method of forming a semiconductor structure of claim 1, wherein, A method for forming a second portion of the semiconductor device in a lightly doped epitaxial layer in the second region includes: A conductive layer is formed in the second region that penetrates the low-doped epitaxial layer and electrically connects to the high-doped epitaxial layer.

6. The method of forming a semiconductor structure of claim 1, wherein, The semiconductor substrate further includes a second surface opposite to the first surface, and the method of forming the semiconductor structure further includes forming a heat dissipation structure on the second surface.

7. The method of forming a semiconductor structure of claim 6, wherein, The heat dissipation structure includes: a heat-dissipating metal layer or thermally conductive silicone grease.

8. The method of forming a semiconductor structure of claim 1, wherein, The semiconductor substrate is made of undoped silicon carbide, the highly doped epitaxial layer is made of doped silicon carbide, and the low-doped epitaxial layer is made of doped silicon carbide.

9. The method of forming a semiconductor structure of claim 9, wherein, The high-doped epitaxial layer has a doping concentration greater than that of the low-doped epitaxial layer, the doping concentration of the high-doped epitaxial layer is 1E18 to 1E21 cm -3 , and the doping concentration of the low-doped epitaxial layer is 1E16 to 3E19 cm -3 .

10. The method of forming a semiconductor structure of claim 1, wherein, The first region includes a core device region and a protection zone surrounding the core device region, and the second region includes a dicing region.

11. A semiconductor structure, characterized by include: A semiconductor substrate, wherein a highly doped epitaxial layer and a low-doped epitaxial layer are sequentially formed on a first surface of the semiconductor substrate, and the semiconductor substrate includes a first region and a second region; The first part of the semiconductor device is located on the low-doped epitaxial layer in the first region, with the low-doped epitaxial layer in the first region serving as the channel; The second portion of the semiconductor device is located in the low-doped epitaxial layer of the second region, and the second portion of the semiconductor device penetrates the low-doped epitaxial layer and is electrically connected to the high-doped epitaxial layer.

12. The semiconductor structure of claim 11, wherein, The second part of the semiconductor device includes: The trench of the highly doped epitaxial layer is exposed through the low-doped epitaxial layer in the second region; A highly doped contact layer located in a low-doped epitaxial layer on the sidewall of the trench; Ohmic contact layers located on the surfaces of the highly doped epitaxial layer at the bottom of the trench and the highly doped contact layer on the sidewall of the trench; A conductive layer located in the trench, filling the trench and electrically connecting the ohmic contact layer.

13. The semiconductor structure of claim 11, wherein, The second part of the semiconductor device includes: The low-doped epitaxial layer penetrating the second region is electrically connected to the high-doped contact layer of the high-doped epitaxial layer; A conductive layer located on the top surface of the highly doped contact layer is electrically connected to the highly doped contact layer.

14. The semiconductor structure of claim 11, wherein, The second part of the semiconductor device includes: The low-doped epitaxial layer penetrating the second region is electrically connected to the high-doped contact layer of the high-doped epitaxial layer; An ohmic contact layer that electrically connects to the highly doped epitaxial layer is formed through the highly doped contact layer. A conductive layer located on the top surface of the ohmic contact layer and the highly doped contact layer, electrically connecting the ohmic contact layer and the highly doped contact layer.

15. The semiconductor structure of claim 11, wherein, The second part of the semiconductor device includes: The low-doped epitaxial layer that penetrates the second region is electrically connected to the conductive layer of the high-doped epitaxial layer.

16. The semiconductor structure of claim 11, wherein, The semiconductor substrate further includes a second surface opposite to the first surface, and the semiconductor structure further includes a heat dissipation structure located on the second surface.

17. The semiconductor structure of claim 16, wherein, The heat dissipation structure includes: a heat-dissipating metal layer or thermally conductive silicone grease.

18. The semiconductor structure of claim 11, wherein, The semiconductor substrate is made of undoped silicon carbide, the highly doped epitaxial layer is made of doped silicon carbide, and the low-doped epitaxial layer is made of doped silicon carbide.

19. The semiconductor structure of claim 19, wherein, The high-doped epitaxial layer has a doping concentration greater than that of the low-doped epitaxial layer, the doping concentration of the high-doped epitaxial layer is 1E18 to 1E21 cm -3 , and the doping concentration of the low-doped epitaxial layer is 1E16 to 3E19 cm -3 .

20. The semiconductor structure of claim 11, wherein, The first region includes a core device region and a protection zone surrounding the core device region, and the second region includes a dicing region.

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