Semiconductor device, manufacturing method, integrated circuit, and electronic device

Abstract

The present application relates to the technical field of semiconductors, and discloses a semiconductor device, a manufacturing method, an integrated circuit, and an electronic device. The semiconductor device comprises a vertical channel, a stack structure, and a first electrode. The first electrode has a first width in a first direction. In a vertical direction from the first electrode toward a substrate, the first width gradually decreases, so that the cross-sectional area of the first electrode on a side close to the vertical channel can be reduced, thereby reducing parasitic capacitance between the first electrode and a gate structure. In addition, the cross-sectional area of the first electrode on a side distant from the vertical channel can be increased, reserving sufficient area on the surface of the side of the first electrode facing away from the vertical channel for maximizing contact area with an interconnect portion, thereby reducing contact resistance between the first electrode and the interconnect portion. On this basis, the first electrode in embodiments of the present application can achieve both reduced contact resistance and reduced parasitic capacitance, thereby improving device performance and reducing power consumption.

Description

A semiconductor device, a fabrication method, an integrated circuit, and an electronic device.

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. 202411456028.6, filed on October 17, 2024, entitled "A Semiconductor Device, Preparation Method, Integrated Circuit and Electronic Equipment", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of semiconductor technology, and in particular to a semiconductor device, a fabrication method, an integrated circuit, and an electronic device. Background Technology

[0004] The pursuit of smaller device size and higher integration density to achieve better performance is the driving force behind the development of integrated circuit technology. The most basic unit in an integrated circuit is the field-effect transistor (FET). Traditional FETs are typically planar structures, with the current path from the drain through the channel to the source running horizontally. However, with the continuous advancement of Moore's Law, the continuous miniaturization of the critical dimension (CD) (such as gate length and contact metal spacing) of traditional planar FET structures has reached its physical limit, leading to a trade-off between power consumption, performance, and cost. To address this, the vertical field-effect transistor (VFET) was developed. By setting a vertical channel, bottom electrode, top electrode, and gate, the VFET can respond to gate control, allowing charge carriers to transport along the vertical channel between the bottom and top electrodes, thus decoupling the contacted gate pitch (CGP) from the gate length. However, in VFETs, a large parasitic capacitance typically exists between the top electrode and the gate, affecting the VFET's performance. Furthermore, during the fabrication process, after forming the VFET, an interconnect layer for signal transmission is also formed, and an interconnect portion is formed between the top electrode of the VFET and the interconnect layer. This interconnect portion allows signal transmission between the interconnect layer and the top electrode. To ensure current flow between the interconnect portion and the top electrode, a relatively large contact area is typically required to achieve low contact resistance. Therefore, how to simultaneously reduce both contact resistance and parasitic capacitance, thereby improving device performance and reducing power consumption, is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] This application provides a semiconductor device, a fabrication method, an integrated circuit, and an electronic device, which can reduce both contact resistance and parasitic capacitance, thereby improving device performance and reducing power consumption.

[0006] In a first aspect, embodiments of this application provide a semiconductor device, comprising a substrate, a vertical channel, a stacked structure, a first electrode, and a recess. Both the vertical channel and the stacked structure are disposed on the substrate. The vertical channel extends in a vertical direction, and the stacked structure is disposed on at least both sides of the vertical channel. The stacked structure includes a gate structure and a first isolation dielectric layer stacked in a vertical direction, with the first isolation dielectric layer disposed on the side of the gate structure facing away from the substrate. Furthermore, the recess is disposed on the side of the first isolation dielectric layer facing away from the substrate, and the orthographic projection of the recess onto the substrate overlaps with the orthographic projection of the vertical channel onto the substrate. The first electrode is disposed in the recess and connected to the vertical channel through the recess, enabling signal transmission to the vertical channel via the first electrode. Additionally, the first electrode has a first width along a first direction, and this first width decreases in the direction along the vertical direction and from the first electrode towards the substrate, forming a structure that is wider at the top and narrower at the bottom. This reduces the cross-sectional area of ​​the first electrode near the vertical channel, thereby reducing the parasitic capacitance between the first electrode and the gate structure. Furthermore, the cross-sectional area of ​​the first electrode on the side away from the vertical trench can be increased, thereby reserving sufficient area on the surface of the first electrode facing away from the vertical trench to increase the contact area with the interconnect portion, thereby reducing the contact resistance between the first electrode and the interconnect portion. Based on this, the first electrode in the embodiments of this application can simultaneously reduce both contact resistance and parasitic capacitance, improving device performance and reducing power consumption.

[0007] Among them, the vertical direction is perpendicular to the layer where the substrate is located, and the first direction is perpendicular to the vertical direction.

[0008] Furthermore, in the semiconductor device provided in this application embodiment, by forming the first electrode of each vertical field-effect transistor in a groove, since the shapes of different grooves are relatively regular, the shapes of the first electrodes formed in the grooves are also relatively regular, thereby reducing the difference in parasitic resistance between the first electrodes of different vertical field-effect transistors and reducing the electrical difference between different vertical field-effect transistors.

[0009] For example, the first electrode is formed using an epitaxial process, which includes, but is not limited to, vapor phase epitaxy (Epi) and solid phase epitaxy (SPE).

[0010] Furthermore, since the first electrode is formed in the groove, the size of the first electrode of different vertical field-effect transistors can be basically the same. Therefore, using the regularly shaped first electrode as a mask is beneficial to the subsequent self-aligned process for forming the gate structure, thereby improving the accuracy of the subsequent self-aligned process.

[0011] In some embodiments, the first width of the surface of the first electrode facing the substrate along the first direction is the smallest of the first widths of the first electrode. Furthermore, the first width of the surface of the first electrode facing away from the substrate along the first direction is the largest of the first widths of the first electrode.

[0012] In some embodiments, the surface of the first electrode facing the substrate is flush with the surface of the first insulating dielectric layer facing away from the substrate, such that the overall structure of the first electrode is disposed on the plane of the surface of the first insulating dielectric layer facing away from the substrate.

[0013] In some embodiments, the first width can vary in a continuously decreasing manner in the direction from the first electrode to the substrate, which can make the first width of the first electrode transition smoothly and improve the structural strength and stability of the first electrode.

[0014] In some embodiments, the first width can be varied in a stepwise manner in the direction from the first electrode to the substrate, which can make the first width of the first electrode transition in a stepwise manner, thereby improving the structural strength and stability of the first electrode.

[0015] In some embodiments, the first width may also vary in a combination of continuous and step-decreasing in the direction from the first electrode to the substrate, so that the first width may have both a continuously decreasing portion and a step-decreasing portion, thereby diversifying the first width.

[0016] In some embodiments, when the first width decreases continuously, the sidewall of the first electrode can be shaped in the vertical direction as one or a combination of a slope, an arcuate shape with the sidewall bulging towards the groove, and an arcuate shape with the sidewall bulging away from the groove. This allows for a simple and easily implemented shape structure of the sidewall of the first electrode in the vertical direction.

[0017] In some embodiments, when the first width decreases in a stepped manner, the sidewall of the first electrode has a stepped shape in the vertical direction. This also simplifies the vertical shape of the sidewall of the first electrode, making it easier to implement.

[0018] In some embodiments, a first dielectric layer is further included on the side of the first insulating dielectric layer facing away from the substrate. The groove includes a first region and a second region, with the first region located between the second region and the first insulating dielectric layer. At least the first region can penetrate the first dielectric layer, allowing the groove to be etched to obtain a specific shape. Furthermore, the first electrode at least fills the first region and is connected to the vertical channel. The sidewalls of the first electrode and the sidewalls of the first dielectric layer in contact with it have complementary shapes. Based on this, a simple fabrication process can be used to form the first electrode with the specific structure of this application, reducing the difficulty of fabrication. In addition, the first dielectric layer can be used to protect the sidewalls of the first electrode, preventing damage to the first electrode from other processes (such as etching processes).

[0019] In some embodiments, a second dielectric layer is further included, at least on both sides of the first dielectric layer, wherein the height of the second dielectric layer in the vertical direction is greater than the height of the first dielectric layer in the vertical direction. Thus, the second dielectric layer can be used to protect the first dielectric layer, improving the stability of the device.

[0020] In some embodiments, the first and second regions of the groove both penetrate the first dielectric layer, so as to obtain a groove of a specific shape by etching the first dielectric layer.

[0021] In some embodiments, the first electrode fills a first region and a second region. Based on this, the first electrode with the specific structure of this application can be formed using a simple fabrication process by etching the first dielectric layer, reducing the difficulty of fabrication. Furthermore, the first dielectric layer can also be used to protect the sidewalls of the first electrode, preventing damage to the first electrode from other processes (such as etching processes).

[0022] In some embodiments, the first region includes a first sub-region and a second sub-region, with the first sub-region located between the second sub-region and the second region. The first sub-region penetrates the first dielectric layer, and the second sub-region and the second region penetrate the second dielectric layer. Based on this, a groove of a specific shape can be formed by the first dielectric layer and the second dielectric layer together. Then, a first electrode is epitaxially formed in the groove. This allows a portion of the sidewall of the first electrode to contact the first dielectric layer, and another portion of the sidewall to contact the second dielectric layer, making the sidewalls of the first electrode and the contacting first and second dielectric layers complementary in shape, thereby giving the epitaxially formed first electrode a specific shape. Based on this, a simple fabrication process can be used to form the first electrode with the specific structure of this application, reducing the difficulty of fabrication. Furthermore, the first dielectric layer and the second dielectric layer can be used together to protect the sidewalls of the first electrode, preventing damage to the first electrode from other processes (such as etching processes).

[0023] In some embodiments, the first electrode fills the first region, such that a portion of the sidewall of the first electrode contacts the first dielectric layer and another portion of the sidewall of the first electrode contacts the second dielectric layer, so that the first dielectric layer and the second dielectric layer are combined with each other, and the shape of the sidewall of the formed first electrode in the vertical direction can also be stepped or other feasible shapes.

[0024] In some embodiments, the semiconductor device further includes an interconnect portion disposed on the side of the first electrode facing away from the substrate and connected to the first electrode, so as to realize signal transmission between the first electrode and the interconnect layer. Furthermore, in order to maximize the contact area between the first electrode and the interconnect portion and minimize its contact resistance, the orthographic projection of the surface of the interconnect portion facing the substrate falls within the orthographic projection of the surface of the first electrode facing away from the substrate.

[0025] In some embodiments, to protect the surface of the first electrode facing away from the substrate, the semiconductor device further includes an etch stop layer disposed on the side of the first electrode facing away from the substrate, with interconnects penetrating the etch stop layer and connecting to the first electrode. Thus, the etch stop layer can be used to prevent damage to the surface of the first electrode facing away from the substrate from other processes (e.g., etching processes).

[0026] In some embodiments, in order to maximize the contact area between the first electrode and the vertical channel, the orthographic projection of the surface of the first electrode facing the substrate onto the substrate covers the orthographic projection of the vertical channel onto the substrate.

[0027] For example, the orthographic projection of the surface of the first electrode facing the substrate onto the substrate coincides with the orthographic projection of the vertical channel onto the substrate, so as to reduce the parasitic capacitance between the first electrode and the gate metal layer while maximizing the contact area between the first electrode and the vertical channel.

[0028] In some embodiments, the first electrode includes a first partial electrode, a second partial electrode, and a third partial electrode. The orthographic projection of the second partial electrode onto the substrate coincides with the orthographic projection of the vertical channel onto the substrate. The first partial electrode and the third partial electrode are symmetrical about the second partial electrode, which can make the orthographic projection of the first electrode onto the substrate symmetrical about the orthographic projection of the vertical channel onto the substrate, thereby improving the reliability of the device.

[0029] Secondly, embodiments of this application also provide a method for fabricating a semiconductor device. This method may include: forming a vertical channel extending in a vertical direction on a substrate; forming a stacked structure disposed at least on both sides of the vertical channel; forming a groove disposed on the side of a first isolation dielectric layer facing away from the substrate; and forming a first electrode disposed in the groove. The orthographic projection of the groove onto the substrate overlaps with the orthographic projection of the vertical channel onto the substrate. The first electrode is connected to the vertical channel through the groove. The stacked structure includes a gate structure and a first isolation dielectric layer stacked in a vertical direction. The first isolation dielectric layer is disposed on the side of the gate structure facing away from the substrate. Furthermore, the first electrode has a first width along a first direction, and the first width decreases in the direction from the first electrode to the substrate. The first direction is perpendicular to the vertical direction, and the vertical direction is perpendicular to the substrate layer. Therefore, the first electrode can be formed with a structure that is wider at the top and narrower at the bottom, thereby reducing the cross-sectional area of ​​the first electrode near the vertical channel and thus reducing the parasitic capacitance between the first electrode and the gate structure. Furthermore, the cross-sectional area of ​​the first electrode on the side furthest from the vertical trench can be increased, thereby reserving sufficient area on the surface of the first electrode facing away from the vertical trench to increase the contact area with the interconnect portion, and thus reduce the contact resistance between the first electrode and the interconnect portion. Based on this, the first electrode in the embodiments of this application can simultaneously reduce both contact resistance and parasitic capacitance, improving device performance and reducing power consumption.

[0030] In some embodiments, a hard mask layer is formed on the side of the vertical channel facing away from the substrate. The hard mask layer includes a hard mask and a pad oxide layer, with the pad oxide layer located between the hard mask and the vertical channel. Furthermore, the process of forming a first electrode disposed in a groove on the side of the first insulating dielectric layer facing away from the substrate may include the following steps:

[0031] Mask sidewalls and sacrificial dielectric layers are formed on both sides of the hard mask layer;

[0032] Etching removes the hard mask, forming the first mask opening;

[0033] The mask sidewalls are etched to form at least a portion of a groove in the mask sidewalls, and the shape of the sidewalls of the retained mask sidewalls facing away from the sacrificial dielectric layer is complementary to the sidewall shape of the first electrode to be formed; wherein the retained mask sidewalls are the first dielectric layer;

[0034] The first electrode is formed by filling the groove using an epitaxial process.

[0035] In some embodiments, a hard mask layer is formed on the side of the vertical channel facing away from the substrate. The hard mask layer includes a hard mask and a pad oxide layer, with the pad oxide layer located between the hard mask and the vertical channel. Furthermore, the process of forming a first electrode disposed in a groove on the side of the first insulating dielectric layer facing away from the substrate may include the following steps:

[0036] Mask sidewalls and sacrificial dielectric layers are formed on both sides of the hard mask layer;

[0037] Etching removes the hard mask layer and mask sidewalls to form a second mask opening;

[0038] A first dielectric layer is formed in the second mask opening, and at least a portion of a groove is formed in the first dielectric layer such that the sidewall of the first dielectric layer opposite to the sacrificial dielectric layer is complementary to the sidewall shape of the first electrode to be formed.

[0039] The first electrode is formed by filling the groove with a heavily doped amorphous semiconductor material layer using an epitaxial process.

[0040] Thirdly, embodiments of this application also provide an integrated circuit (IC), which includes electronic devices and semiconductor devices, with the electronic devices and semiconductor devices connected together. The semiconductor device is a semiconductor device as described in the first aspect or various embodiments thereof, or it may be a semiconductor device fabricated using the second aspect or various embodiments thereof. Since the aforementioned semiconductor devices can improve device performance and reduce power consumption, the integrated circuit including the aforementioned semiconductor devices also exhibits better performance.

[0041] Fourthly, embodiments of this application also provide an electronic device, comprising: a circuit board and an integrated circuit, wherein the integrated circuit is disposed on the circuit board. The integrated circuit is an integrated circuit as described in the third aspect or various embodiments thereof. Since the semiconductor devices in the aforementioned integrated circuit can improve device performance and reduce power consumption, the electronic device including the aforementioned integrated circuit also exhibits better performance. Attached Figure Description

[0042] Figure 1 is a schematic diagram of the structure of an electronic device according to an embodiment of this application;

[0043] Figure 2A is a schematic diagram of a semiconductor device in an embodiment of this application;

[0044] Figure 2B is a schematic diagram of another structure of the semiconductor device in the embodiments of this application;

[0045] Figure 2C is a schematic diagram of another structure of the semiconductor device in the embodiments of this application;

[0046] Figure 2D is a schematic diagram of another structure of the semiconductor device in the embodiments of this application;

[0047] Figures 3A to 3C are top view schematic diagrams of a semiconductor device in an embodiment of this application;

[0048] Figure 4 is a schematic diagram of the structure of a VFET in the prior art;

[0049] Figures 5A to 5P are cross-sectional views of a semiconductor device fabrication process according to an embodiment of this application;

[0050] Figures 6A to 6C are cross-sectional views of another semiconductor device fabrication process in an embodiment of this application;

[0051] Figure 7 is a schematic diagram of another structure of the semiconductor device in the embodiments of this application;

[0052] Figures 8A to 8C are cross-sectional views of another semiconductor device fabrication process in an embodiment of this application;

[0053] Figure 9 is a schematic diagram of another structure of the semiconductor device in the embodiments of this application;

[0054] Figure 10A is a schematic diagram of another structure of the semiconductor device in the embodiments of this application;

[0055] Figure 10B is a schematic diagram of another structure of the semiconductor device in the embodiments of this application.

[0056] Reference numerals: 100-Housing; 200-Circuit board; 210-Integrated circuit; 300-Semiconductor device; 310-Substrate; 400-VFET; 410-Vertical channel; 420-Stacked structure; 421-Second electrode; 422-Second isolation dielectric layer; 423-Gate structure; 424-First isolation dielectric layer; 430-First electrode; 431-Conductive structure; 441-First dielectric layer; 442-Second dielectric layer; 450-Etch barrier layer; 460-Interconnect; 470-Insulating dielectric layer; 510-Hard mask layer; 511-Pad oxide layer; 512-Mask dielectric layer; 520-Dummy gate; 530-Mask sidewall; F0-Vertical direction. Detailed Implementation

[0057] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The specific operational methods in the method embodiments can also be applied to the device embodiments or system embodiments. It should be noted that in the description of this application, "multiple" can be understood as "at least two". Furthermore, it should be understood that in the description of this application, terms such as "first" and "second" are used only for distinguishing purposes and should not be construed as indicating or implying relative importance, nor as indicating or implying order.

[0058] It should be noted that the same reference numerals in the accompanying drawings of this application denote the same or similar structures, and therefore repeated descriptions of them will be omitted. Terms expressing position and direction described in this application are illustrative based on the accompanying drawings, but may be modified as needed, and all modifications are included within the scope of protection of this application. The accompanying drawings of this application are for illustrating relative positional relationships only and do not represent actual scale.

[0059] The semiconductor devices, fabrication methods, integrated circuits, and electronic devices provided in the embodiments of this application are described below with reference to the accompanying drawings.

[0060] Figure 1 is a schematic diagram of an electronic device according to an embodiment of this application. Referring to Figure 1, the electronic device includes: a housing 100, a circuit board 200 disposed within the housing 100, and an integrated circuit 210 fixed on the circuit board 200. The integrated circuit 210 and the circuit board 200 can be connected by bonding or other methods to achieve an electrical connection between the integrated circuit 210 and the circuit board 200, thereby enabling signal transmission between the integrated circuit 210 and the circuit board 200.

[0061] For example, electronic devices include, but are not limited to, terminal devices and communication devices. Terminal devices include, but are not limited to, mobile phones, computers, televisions, set-top boxes, watches, personal computers (PCs), wearable devices, workstations, etc. Communication devices include, but are not limited to, wireless network devices, fixed network devices, servers, smart broadband devices, etc. It is understood that the specific implementation of the electronic device can be determined according to the actual application scenario and is not limited herein.

[0062] For example, circuit board 200 includes, but is not limited to, a printed circuit board (PCB).

[0063] Exemplary, integrated circuit 210 includes, but is not limited to, logic circuits, memory circuits, etc., which are not listed here. Exemplary, integrated circuit 210 may include electronic devices and one or more semiconductor devices, with the electronic device 210 connected to the semiconductor devices. Exemplary, the semiconductor devices may be dies, and integrated circuit 210 may be a structure in which the electronic device and the semiconductor device are packaged. In another embodiment of this application, integrated circuit 210 may not contain electronic devices, that is, integrated circuit 210 may also be a structure in which the semiconductor devices are packaged. Furthermore, when integrated circuit 210 has multiple semiconductor devices, the multiple semiconductor devices may be packaged using 3D, 2.5D, or other packaging methods.

[0064] For example, when the integrated circuit 210 is a logic circuit, the electronic devices include, but are not limited to, passive devices to achieve impedance matching. These passive devices include, but are not limited to, one or a combination of resistors, inductors, and capacitors. For example, the logic circuit can be a processor, such as, but not limited to, a central processing unit (CPU), an artificial intelligence (AI) processor, a digital signal processor, and a neural network processor.

[0065] For example, when integrated circuit 210 is a storage circuit, the electronic devices include, but are not limited to, a controller, and the semiconductor devices include, but are not limited to, a storage array. The controller is electrically connected to the storage array, thereby enabling the controller to access the storage array. For example, the storage integrated circuit can be a memory, such as, but not limited to, random access memory (RAM), read-only memory (ROM), etc. Random access memory includes, but is not limited to, dynamic random access memory (DRAM), static random access memory (SRAM), magnetoresistive random access memory (MRAM), phase change memory (PCM), etc.

[0066] Figure 2A is a schematic diagram of a semiconductor device in an embodiment of this application. Referring to Figure 2A, the semiconductor device 300 in this embodiment may include a substrate 310. Exemplarily, the material of the substrate 310 includes, but is not limited to, silicon (Si), germanium (Ge), silicon-germanium (SiGe), silicon carbide (SiC), III-V compound semiconductor, or II-VI compound semiconductor.

[0067] Semiconductor devices are typically implemented using FETs. However, further reductions in the critical dimension (CD) of horizontally configured FETs, such as gate length and CGP, lead to a significant increase in parasitic capacitance and consequently, power consumption. Therefore, the semiconductor device 300 in this embodiment is formed as a VFET 400, which effectively mitigates the short-channel effect and significantly reduces the planar space occupied by a single transistor device, resulting in substantial performance and area gains.

[0068] For example, referring to FIG2A, the substrate 310 may include a vertical channel 410, a stacked structure 420, and a first electrode 430. The vertical channel 410 extends along a vertical direction F0, and the stacked structure 420 may be disposed at least on both sides of the vertical channel 410. For example, the stacked structure 420 includes a second electrode 421, a second isolation dielectric layer 422, a gate structure 423, and a first isolation dielectric layer 424 stacked along the vertical direction F0, i.e., the second electrode 421, the second isolation dielectric layer 422, the gate structure 423, and the first isolation dielectric layer 424 are sequentially stacked along the vertical direction F0 and disposed at least on both sides of the vertical channel 410. For example, the gate structure 423 may include a gate metal layer 4231 and a gate dielectric layer 4232, with the gate metal layer 4231 disposed at least on both sides of the vertical channel 410 through the gate dielectric layer 4232. Furthermore, a high dielectric constant (k) dielectric material layer can be formed before forming the gate metal layer 4231, thereby making the formed gate structure 423 a high-k metal gate (HKMG). The material of the high-k dielectric material layer includes, but is not limited to, HfO2. The high-k dielectric material layer is not shown in Figure 2A. Furthermore, an insulating dielectric layer 470 can be disposed between the first isolation dielectric layer 424 and the second isolation dielectric layer 422 and the vertical channel 410. Alternatively, the first isolation dielectric layer 424 and the second isolation dielectric layer 422 can also be in direct contact with the vertical channel 410.

[0069] The first isolation dielectric layer 424 has a groove AC on the side facing away from the substrate 310. The orthographic projection of the groove AC onto the substrate 310 overlaps with the orthographic projection of the vertical channel 410 onto the substrate 310, allowing the groove AC to expose part or all of the surface of the vertical channel 410 on the side facing away from the substrate 310. The first electrode 430 is disposed in the groove AC and electrically connected to the vertical channel 410 through the groove AC. Furthermore, the second electrode 421 is also electrically connected to the vertical channel 410, enabling carriers to transport along the vertical channel 410 between the second electrode 421 and the first electrode 430. The second electrode 421 can be the bottom electrode of the VFET 400, and the first electrode 430 can be the top electrode of the VFET 400. In specific implementations, the first electrode 430 can be the drain of the VFET, and the second electrode can be the source of the VFET; alternatively, the second electrode can be the drain of the VFET, and the first electrode 430 can be the source of the VFET. No limitation is made here.

[0070] To increase the contact area between the first electrode 430 and the vertical channel 410, referring to FIG2A, the orthographic projection of the surface Sa_1 of the first electrode 430 facing the substrate 310 onto the substrate 310 can cover the orthographic projection of the vertical channel 410 onto the substrate 310. For example, the orthographic projection of the surface Sa_1 of the first electrode 430 facing the substrate 310 onto the substrate 310 can coincide with the orthographic projection of the vertical channel 410 onto the substrate 310, thereby reducing the parasitic capacitance between the first electrode 430 and the gate metal layer while maximizing the contact area between the first electrode 430 and the vertical channel 410. Alternatively, the orthographic projection of the vertical channel 410 onto the substrate 310 can fall within the orthographic projection of the surface Sa_1 of the first electrode 430 facing the substrate 310 onto the substrate 310, i.e., the area of ​​the surface of the first electrode 430 facing the substrate 310 is larger than the area of ​​the surface of the vertical channel 410 facing away from the substrate 310. Alternatively, the surface Sa_1 of the first electrode 430 facing the substrate 310 can be projected onto the substrate 310 in the orthogonal projection of the vertical channel 410 onto the substrate 310.

[0071] After the VFET is formed, an interconnect layer for transmitting signals is also formed, and an interconnect portion 460 is formed between the first electrode of the VFET and the interconnect layer. The interconnect portion 460 enables signal transmission between the interconnect layer and the first electrode. Based on this, in some embodiments of this application, referring to FIG2A, the semiconductor device 300 may further include an interconnect portion 460 disposed on the side of the first electrode 430 facing away from the substrate 310, and the interconnect portion 460 is connected to the first electrode 430. Thus, the interconnect portion 460 can be used to realize signal transmission between the first electrode 430 and the interconnect layer. Furthermore, in order to maximize the contact area between the first electrode 430 and the interconnect portion 460 and minimize its contact resistance, the orthographic projection of the surface Sf of the interconnect portion 460 facing the substrate 310 onto the substrate 310 falls within the orthographic projection of the surface Sa_2 of the first electrode 430 facing away from the substrate 310 onto the substrate 310. That is, the area of ​​the surface Sa_2 of the first electrode 430 facing away from the substrate 310 is larger than the area of ​​the surface Sf of the interconnect portion 460 facing the substrate 310. By way of example, the orthographic projection of the vertical channel 410 onto the substrate 310 may also fall within the orthographic projection of the surface Sf of the interconnect 460 facing the substrate 310 onto the substrate 310, so that the area of ​​the surface Sf of the interconnect 460 facing the substrate 310 is larger than the area of ​​the surface Sa_2 of the vertical channel 410 facing away from the substrate 310, thereby improving current flow. In other embodiments, the orthographic projection of the vertical channel 410 onto the substrate 310 may also coincide with the orthographic projection of the surface Sf of the interconnect 460 facing the substrate 310 onto the substrate 310.

[0072] As transistor device dimensions continue to shrink (e.g., after the 10nm node), the drive current of a single transistor device remains essentially constant. Improvements in node-to-node performance and reductions in power consumption primarily stem from the reduction of parasitic capacitance. However, in VFETs, a significant parasitic capacitance typically exists between the first electrode 430 and the gate metal layer 4231. This parasitic capacitance can be reduced by decreasing the area of ​​the first electrode 430. However, increasing the contact area between the first electrode 430 and the interconnect 460 is also necessary to achieve a lower contact resistance. Therefore, designing the structure of the first electrode 430 to simultaneously reduce both contact resistance and parasitic capacitance is crucial for improving device performance and reducing power consumption. Therefore, in this embodiment of the application, referring to FIG2A, the first electrode 430 has a first width (e.g., ha) along the first direction F1. In the direction along the vertical direction F0 and from the first electrode 430 to the substrate 310, the first width (e.g., ha) is set to decrease in a decreasing trend. This allows the first electrode 430 to form a structure that is wider at the top and narrower at the bottom. That is, in the direction from the first electrode 430 to the substrate 310 (i.e., the direction opposite to the arrow of F0), the cross-sectional area of ​​the first electrode 430 is set to decrease in a decreasing trend. This reduces the cross-sectional area of ​​the first electrode 430 near the vertical channel 410, thereby reducing the parasitic capacitance between the first electrode 430 and the gate metal layer 4231. Furthermore, the cross-sectional area of ​​the first electrode 430 away from the vertical channel 410 can be increased, thereby reserving sufficient area on the surface of the first electrode 430 facing away from the vertical channel 410 to increase the contact area with the interconnect portion 460, thereby reducing the contact resistance between the first electrode 430 and the interconnect portion 460. Therefore, the first electrode 430 in this embodiment can reduce both contact resistance and parasitic capacitance, thereby improving device performance and reducing power consumption.

[0073] It is understood that, referring to FIG2A, the first width of the surface Sa_1 of the first electrode 430 facing the substrate 310 in the first direction is ha_1, and the first width ha_1 is the smallest among the first widths ha of the first electrode 430. Furthermore, the first width of the surface Sa_2 of the first electrode 430 facing away from the substrate 310 in the first direction is ha_2, and the first width ha_2 is the largest among the first widths ha of the first electrode 430. Therefore, in the direction from the first electrode 430 to the substrate 310, the first width can change from the first width ha_2 to the first width ha_1 based on a decreasing trend. Based on this, when the surface Sa_1 of the first electrode 430 facing the substrate 310 is used as the first cross-section of the first electrode 430, the first cross-section can be the cross-section with the smallest area among the cross-sections of the first electrode 430. And when the surface Sa_2 of the first electrode 430 facing away from the substrate 310 is used as the second cross-section of the first electrode 430, the second cross-section can be the cross-section with the largest area among the cross-sections of the first electrode 430. Therefore, in the direction from the first electrode 430 to the substrate 310, the area of ​​the cross-section of the first electrode 430 can change from the area of ​​the second cross-section to the area of ​​the first cross-section based on a decreasing trend.

[0074] In one embodiment of this application, referring to Figures 3A and 3B, which are schematic top views of a semiconductor device in this embodiment, the stacked structure 420 can be arranged around the vertical channel 410. That is, the second electrode 421, the second isolation dielectric layer 422, the gate structure 423 and the first isolation dielectric layer 424 are stacked sequentially along the vertical direction F0 and surround the vertical channel 410. Furthermore, the gate metal layer 4231 surrounds the vertical channel 410 through the gate dielectric layer 4232, thereby forming a Gate-All-Around (GAA) VFET.

[0075] In another embodiment of this application, referring to FIG3C, FIG3C is a top view schematic diagram of another semiconductor device in this application embodiment. The stacked structure 420 can be disposed on opposite sides of the vertical channel 410 in the first horizontal direction Fs1, that is, the second electrode 421, the second isolation dielectric layer 422, the gate structure 423 and the first isolation dielectric layer 424 are stacked sequentially along the vertical direction F0 and respectively disposed on opposite sides of the vertical channel 410 in the first horizontal direction Fs1, thereby forming a semi-enclosed gate VFET.

[0076] For example, referring to Figures 3A to 3C, the vertical channel 410 can be configured as a fin vertical channel, that is, the orthogonal projection of the vertical channel 410 onto the substrate can extend along the second horizontal direction Fs2, which increases the area of ​​the gate surrounding the vertical channel 410 and can enhance the gate's control over the vertical channel 410.

[0077] In some examples, when the stacked structure 420 is arranged around the vertical channel 410, referring to FIG3A, if the orthogonal projection of the first electrode 430 on the substrate not only covers the orthogonal projection of the vertical channel 410 on the substrate, but also surrounds the orthogonal projection of the vertical channel 410 on the substrate, based on this, the first direction F1 in the embodiments of this application includes a first horizontal direction Fs1 and a second horizontal direction Fs2, and the first width includes the width h11 of the first electrode 430 in the first horizontal direction Fs1 and the width h12 of the first electrode 430 in the second horizontal direction Fs2. Alternatively, the first direction F1 in the embodiments of this application includes the first horizontal direction Fs1, and the first width includes the width h11 of the first electrode 430 in the first horizontal direction Fs1. Alternatively, the first direction F1 in the embodiments of this application includes the second horizontal direction Fs2, and the first width includes the width h12 of the first electrode 430 in the second horizontal direction Fs2.

[0078] In some other examples, when the stacked structure 420 is arranged around the vertical channel 410, referring to FIG3B, if the orthogonal projection of the first electrode 430 on the substrate covers the orthogonal projection of the vertical channel 410 on the substrate, and the orthogonal projection of the first electrode 430 on the substrate also has an overlapping area with the orthogonal projection of the gate 4231 located on both sides of the vertical channel 410 in the first horizontal direction Fs1, based on this, the first direction F1 in the embodiments of this application includes the first horizontal direction Fs1, and the first width includes the width h21 of the first electrode 430 in the first horizontal direction Fs1.

[0079] In some other examples, when the stacked structure 420 is disposed on both sides of the vertical channel 410, referring to FIG3C, if the orthogonal projection of the first electrode 430 on the substrate covers the orthogonal projection of the vertical channel 410 on the substrate, and the orthogonal projection of the first electrode 430 on the substrate also has an overlapping area with the orthogonal projection of the gate 4231 located on both sides of the vertical channel 410 in the first horizontal direction Fs1, based on this, the first direction F1 in the embodiments of this application includes the first horizontal direction Fs1, and the first width includes the width h31 of the first electrode 430 in the first horizontal direction Fs1.

[0080] It is understandable that the vertical direction F0 is perpendicular to the substrate layer, and the first horizontal direction Fs1 and the second horizontal direction Fs2 are parallel to the substrate layer, respectively. Therefore, the first horizontal direction Fs1 and the second horizontal direction Fs2 are perpendicular to the vertical direction F0. Furthermore, the first horizontal direction Fs1 and the second horizontal direction Fs2 are perpendicular to each other.

[0081] The above is merely an example of using a fin-type vertical channel 410 to illustrate the specific structure of the VFET provided in this embodiment of the invention. In specific implementations, the specific structure of the vertical channel 410 can be implemented in various ways. For example, the vertical channel 410 can also be configured as a columnar vertical channel, and the orthographic projection of the columnar vertical channel onto the substrate can be circular, elliptical, square, etc. Therefore, this application does not limit the specific structure of the vertical channel 410, which can be determined according to the needs of the actual application scenario.

[0082] Combined with FIG. 2A and FIG. 4 below, the principle of reducing the parasitic capacitance between the first electrode 430 and the gate metal layer 4231 in the VFET of the embodiment of the present application will be described. Among them, FIG. 4 is a schematic structural diagram of a VFET in the prior art. Referring to FIG. 4, in the VFET in the prior art, in the vertical direction and in the direction pointing from the first electrode 0430 to the substrate (i.e., the direction opposite to the arrow of F0), the first width of the first electrode 0430 is usually the same, so that the cross-sectional area of the first electrode 0430 is usually the same. Assume that the maximum first width of the first electrode 430 in the embodiment of the present application is the same as the first width of the first electrode 0430 in the prior art, so that the maximum cross-sectional area of the first electrode 430 in the embodiment of the present application is the same as the cross-sectional area of the first electrode 0430 in the prior art, and the contact resistance between the first electrode 430 and the interconnecting portion can be reduced. And, the remaining first widths of the first electrode 430 in the embodiment of the present application are all smaller than the first width of the first electrode 0430 in the prior art, so that the areas of the remaining cross-sections of the first electrode 430 are all smaller than the cross-sectional area of the first electrode 0430. Based on this, select the cross-section Sa corresponding to the first width ha shown in FIG. 2A, the cross-section Sb of the first electrode 0430 shown in FIG. 4, the first width ha is smaller than the first width of the first electrode 0430, so that the area of the cross-section Sa is smaller than the area of the cross-section Sb, and make the distance between the cross-section Sa and the gate metal layer 4231 in the vertical direction and the distance between the cross-section Sb and the gate metal layer 04231 in the vertical direction F0 both be d0, then the facing area Sc1 between the cross-section Sa and the gate metal layer 4231 in the vertical direction F0 is smaller than the facing area Sc2 between the cross-section Sb and the gate metal layer 04231 in the vertical direction F0. According to the capacitance determination formula: C = εS / 4πkd, C represents the capacitance value of the capacitor, ε represents the dielectric constant, S represents the facing area between the two electrode plates of the capacitor, k represents the electrostatic constant, d represents the distance between the two electrode plates of the capacitor, the capacitance value Ca of the parasitic capacitance between the cross-section Sa and the gate metal layer 4231 is Ca = εSc1 / 4πkd0, and the capacitance value Cb of the parasitic capacitance between the cross-section Sb and the gate metal layer 04231 is Cb = εSc2 / 4πkd0. In the case where the dielectric constant ε is the same, the electrostatic constant k is the same, and the distance d0 between the two electrode plates is the same, since Sc1 < Sc2, then Ca < Cb. Therefore, the VFET in the embodiment of the present application can also achieve the effect of reducing the parasitic capacitance between the first electrode 430 and the gate metal layer 4231 on the basis of reducing the contact resistance between the first electrode 430 and the interconnecting portion 460.

[0083] Furthermore, in the existing process fabrication, the first electrode 430 is typically epitaxially formed directly on the first isolation dielectric layer after the gate structure is formed. However, due to limitations in the gate structure material, and the trade-offs between factors such as the uniformity of the first electrode 430's size, selective growth degree, and activation rate, the process temperature during epitaxy cannot be too high. This results in an irregular shape of the formed first electrode 430, leading to differences in the size of the first electrode 430 in different VFET devices, and consequently, differences in parasitic resistance between different VFET devices. Therefore, in the semiconductor device provided in this embodiment, referring to FIG2A, the first electrode 430 of each VFET can be formed in a recess AC. Since the shapes of the recess AC of different VFETs are relatively regular, the shape of the first electrode 430 formed in the recess AC is also relatively regular, thereby reducing the difference in parasitic resistance between the first electrodes 430 of different VFETs and reducing the electrical differences between different VFETs. For example, the first electrode 430 can be formed using an epitaxial process, which includes, but is not limited to, vapor phase epitaxy (Epi) and solid phase epitaxy (SPE).

[0084] Furthermore, since the first electrode 430 is formed in the recess AC, the size of the first electrode 430 of different VFETs can be made to be basically the same. Therefore, using the regularly shaped first electrode 430 as a mask is beneficial to the subsequent process of forming the gate structure 423 by self-alignment, thereby improving the accuracy of the subsequent self-alignment process.

[0085] In some embodiments, referring to FIG2A, the surface Sa_1 of the first electrode 430 facing the substrate is flush with the surface Sd_1 of the first insulating dielectric layer 424 facing away from the substrate 310. This allows the entire structure of the first electrode 430 to be disposed on the plane containing the surface Sd_1 of the first insulating dielectric layer 424 facing away from the substrate 310. Exemplarily, referring to FIG2A, if the surface Se of the vertical channel 410 facing away from the substrate 310 can be flush with the surface Sd_1 of the first insulating dielectric layer 424 facing away from the substrate 310, then the surface of the first electrode 430 facing the substrate 310 can directly contact the vertical channel 410 to achieve interconnection.

[0086] In some embodiments, referring to FIG2A, the first width ha can be continuously reduced in the direction from the first electrode 430 to the substrate 310 (i.e., the direction opposite to the arrow of F0), so that the first width ha smoothly transitions from ha_2 to ha_1, improving the structural strength and stability of the first electrode 430. Furthermore, based on this, the area of ​​the cross-section of the first electrode 430 can also be continuously reduced in the direction perpendicular to F0 and from the first electrode 430 to the substrate 310 (i.e., the direction opposite to the arrow of F0), so that the area of ​​the cross-section of the first electrode 430 can smoothly transition from the area of ​​the second cross-section Sa_2 to the area of ​​the first cross-section Sa_1. In some examples, referring to FIG2A, the sidewall of the first electrode 430 can be sloped in the vertical direction F0, so that the cross-section of the first electrode 430 in the vertical direction F0 is an inverted trapezoid, which is simple in structure and easy to implement. In other examples, referring to Figure 2B, the sidewall of the first electrode 430 can also be shaped as an arc protruding towards the sidewall of the groove in the vertical direction F0, thus making the cross-section of the first electrode 430 in the vertical direction F0 approximately an inverted trapezoid, which is simple in structure and easy to implement. In still other examples, referring to Figure 2C, the sidewall of the first electrode 430 can also be shaped as an arc protruding away from the sidewall of the groove in the vertical direction F0, thus making the cross-section of the first electrode 430 in the vertical direction F0 also approximately an inverted trapezoid, which is simple in structure and easy to implement. The above examples illustrate some shapes of the sidewall of the first electrode 430. In still other embodiments, the shape of the sidewall of the first electrode 430 in the vertical direction F0 can also be achieved by any two or all of the following combinations: a ramp shape, an arc protruding towards the sidewall of the groove, and an arc protruding away from the sidewall of the groove. It is understood that in specific implementations, the shape of the sidewall of the first electrode 430 in the vertical direction F0 can also adopt other achievable shapes, which are not limited in this application. Furthermore, the sidewall of the first electrode 430 is the sidewall of the cross-section of the first electrode 430 in the vertical direction F0.

[0087] In other embodiments, referring to FIG2D, the first width ha can also be reduced in a stepped manner in the direction from the first electrode 430 to the substrate 310 (i.e., the direction opposite to the arrow of F0), so that the first width ha transitions from ha_2 to ha_1 in a stepped manner, thereby improving the structural strength and stability of the first electrode 430. Furthermore, based on this, the cross-sectional area of ​​the first electrode 430 can also be reduced in a stepped manner along the vertical direction F0 and in the direction from the first electrode 430 to the substrate 310 (i.e., the direction opposite to the arrow of F0), so that the cross-sectional area of ​​the first electrode 430 can transition in a stepped manner from the area of ​​the second cross-section Sa_2 to the area of ​​the first cross-section Sa_1. In some examples, referring to FIG2D, the sidewall of the first electrode 430 can be stepped in shape in the vertical direction F0, which is simple in structure and easy to implement.

[0088] In some other embodiments, the first width ha can also be implemented using a combination of continuous and step-like reduction along the vertical direction F0, pointing from the first electrode 430 to the substrate 310 (i.e., the direction opposite to the arrow of F0). For example, the structures of one or more of the first electrodes 430 shown in Figures 2A, 2B, and 2C can be combined with the structure of the first electrode 430 shown in Figure 2D, so that the transition of the first width ha of the first electrode 430 from ha_1 to ha_2 can have both continuous and step-like reductions, thus diversifying the first width ha. Based on this, the cross-sectional area of ​​the first electrode 430 can also be implemented using a combination of continuous and step-like reductions. For example, the structure of one or more of the first electrodes 430 shown in Figures 2A, 2B, and 2C can be combined with the structure of the first electrode 430 shown in Figure 2D, so that the area of ​​the cross-section of the first electrode can be continuously reduced or stepped reduced during the transition from the area of ​​the second cross-section Sa_2 to the area of ​​the first cross-section Sa_1, thereby diversifying the area of ​​the cross-section of the first electrode.

[0089] Taking the structure shown in Figure 2A as an example, in some embodiments, a first dielectric layer 441 can be disposed on the side of the first isolation dielectric layer 424 facing away from the substrate 310. The groove AC can include a first region BQ1 and a second region BQ2, with the first region BQ1 located between the second region BQ2 and the first isolation dielectric layer 424. Both the first region BQ1 and the second region BQ2 of the groove AC can penetrate the first dielectric layer 441, or the first region BQ1 can penetrate the first dielectric layer 441, allowing the groove AC of a specific shape to be obtained by etching the first dielectric layer 441. Furthermore, a first electrode 430 can be filled into the first region BQ1 and the second region BQ2 to achieve electrical connection between the first electrode 430 and the vertical channel 410. Thus, after forming a groove AC of a corresponding shape in the first dielectric layer 441, the first electrode 430 filled in the groove AC can be formed. The sidewalls of the first electrode 430 and the sidewalls of the first dielectric layer 441 in contact with it can have complementary shapes, so that the first electrode 430 epitaxially formed in the groove AC of a specific shape also has a specific shape. Based on this, a simple fabrication process can be used to form the first electrode 430 with the specific structure of this application, reducing the difficulty of fabrication. Furthermore, a first dielectric layer 441 can be used to protect the sidewalls of the first electrode 430, preventing damage to the first electrode 430 from other processes (such as etching). In other embodiments, the first electrode 430 can be filled only in the first region BQ1.

[0090] To protect the surface of the first electrode 430 facing away from the substrate 310, referring to Figures 2A to 2D, in this embodiment, the semiconductor device 300 may further include an etch stop layer 450. The etch stop layer 450 is disposed on the side of the first electrode 430 facing away from the substrate 310, and the interconnect portion 460 penetrates the etch stop layer 450 and is connected to the first electrode 430. Thus, the etch stop layer 450 can be used to prevent other processes (such as etching processes) from damaging the surface of the first electrode 430 facing away from the substrate 310.

[0091] It is worth mentioning that, due to limitations in process conditions or other factors, some deviations or errors may exist in the actual process. For example, the "same" described above can refer to the sameness within the allowable error range. Of course, "same" can also be understood as "substantially the same" or "completely the same." Therefore, the "same" relationship described above, as long as it roughly meets the above conditions, falls within the scope of protection of this application. Similarly, the "flush" described above, as long as it roughly meets the above conditions, falls within the scope of protection of this application.

[0092] The following describes in detail a method for fabricating a semiconductor device according to an embodiment of this application, using the structure of the semiconductor device shown in Figure 2A as an example and referring to Figures 5A to 5P. Figures 5A to 5P are cross-sectional views of the semiconductor device fabrication process in an embodiment of this application.

[0093] Step 1: Referring to FIG5A, a substrate 310 is provided, which may be a Si substrate (e.g., a wafer). A pad oxide layer 511 and a mask dielectric layer 512 are sequentially deposited on the substrate 310 using a dielectric material to form a hard mask layer 510. Exemplarily, the material of the pad oxide layer 511 includes, but is not limited to, a dielectric material such as silicon dioxide (SiO2), and the material of the mask dielectric layer includes, but is not limited to, a dielectric material such as silicon nitride (SiN) or silicon carbide nitride (SiCN). Furthermore, by providing the pad oxide layer 511, the stress between the subsequently grown silicon nitride and the substrate 310 can be alleviated, reducing the risk of substrate 310 cracking.

[0094] Step 2: Referring to Figure 5B, an etching process is used to pattern the hard mask layer 510 so that the area of ​​the substrate 310 corresponding to the formation of the vertical channels 410 is covered by the hard mask layer 510, while exposing the other areas of the substrate 310. Then, an etching process is used to etch a plurality of mutually spaced vertical channels 410 on the substrate 310. The etching process in this embodiment can be wet etching or dry etching, and the appropriate etching process can be selected according to the actual object to be etched, which will not be elaborated further below.

[0095] Step 3: Referring to Figure 5C, a second electrode 421 is formed on the substrate 310 using an epitaxial process (e.g., vapor phase epitaxy, solid phase epitaxy) or ion implantation (IMP) process. Exemplarily, the material of the second electrode 421 includes, but is not limited to, heavily doped silicon or heavily doped silicon-germanium. Furthermore, the doped impurities include, but are not limited to, boron, or may be phosphorus, arsenic, indium, or a combination thereof.

[0096] Step 4: Referring to FIG5D, an insulating dielectric layer 470 is formed on the sidewall of each vertical channel 410, and a second insulating dielectric layer 422 is deposited on the second electrode 421 using a dielectric material. Exemplarily, the material of the second insulating dielectric layer 422 includes a low-k (dielectric constant) dielectric material, such as, but not limited to: silicon dioxide (SiO2), silicon oxycarbide (SiOC), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxynitride (SiON), silicon carbonitride (SiOCN), or combinations thereof. Furthermore, the material of the insulating dielectric layer 470 is SiO2. Exemplarily, the second insulating dielectric layer 422 may surround the vertical channel 410 through the insulating dielectric layer 470, or the second insulating dielectric layer 422 may be in direct contact with the vertical channel 410.

[0097] Step 5: Referring to FIG5E, a virtual gate 520 is formed around the channel region of the vertical channel 410. The material of the virtual gate 520 includes, but is not limited to, amorphous silicon material, metal material, etc., so that the subsequent fabrication process of the first electrode 430 can be performed based on the virtual gate 520, and then the fabrication process of the gate structure can be performed, avoiding the fabrication process of the first electrode 430 being limited by the gate structure.

[0098] Step 6: Referring to FIG5F, a first isolation dielectric layer 424 is deposited on the virtual gate 520 using a dielectric material. Exemplarily, the material of the first isolation dielectric layer 424 includes a low-k dielectric material, such as, but not limited to: silicon dioxide (SiO2), silicon oxycarbide (SiOC), silicon nitride (Si3N4), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxynitride (SiON), silicon carbonitride (SiOCN), or combinations thereof. Exemplarily, the materials of the first isolation dielectric layer 424 and the second isolation dielectric layer 422 may be the same or different, and are not limited herein. Exemplarily, the first isolation dielectric layer 424 may surround the vertical channel 410 through an insulating dielectric layer 470, or the first isolation dielectric layer 424 may be in direct contact with the vertical channel 410.

[0099] Step 7: Referring to FIG5G, a mask sidewall 530 is formed on the sidewall of the hard mask layer 510. Exemplarily, a mask sidewall film is conformally grown on the sidewall of each hard mask layer 510, the surface of each hard mask layer 510 facing away from the substrate 310, and the surface of the first isolation dielectric layer 424 between each hard mask layer 510 facing away from the substrate 310. Then, anisotropic etching is performed on the mask sidewall film, retaining the mask sidewall film on the sidewall of the hard mask layer 510 and removing the mask sidewall film in the remaining areas, thereby forming the mask sidewall 530 on the sidewall of the hard mask layer 510, thus enabling a self-aligned formation of the mask sidewall 530. Exemplarily, the material of the mask sidewall 530 includes, but is not limited to, dielectric materials such as silicon nitride (SiN) and silicon carbide nitride (SiCN). Furthermore, the materials of the hard mask 512 and the mask sidewall 530 can be the same or different.

[0100] Step 8: Referring to FIG5H, a sacrificial dielectric layer 540 is deposited on the substrate 310 where the mask sidewalls 530 are formed, using a dielectric material. Exemplarily, a filling dielectric material is deposited on the substrate 310 where the mask sidewalls 530 are formed to form the sacrificial dielectric layer 540, and the sacrificial dielectric layer 540 covers the hard mask 512 and the mask sidewalls 530. Exemplarily, the material of the sacrificial dielectric layer 540 may include, but is not limited to: silicon dioxide (SiO2), silicon oxycarbide (SiOC), silicon nitride (Si3N4), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxynitride (SiON), silicon carbonitride (SiOCN), or combinations thereof. It is worth noting that, in order to achieve etching selectivity, the sacrificial dielectric layer 540, the hard mask 512, and the mask sidewalls 530 are set to different materials, and a material with higher etching selectivity is selected. Subsequently, CMP and other processes are used to planarize the sacrificial dielectric layer 540, smoothing it to expose the hard mask 512 and mask sidewalls 530. Furthermore, due to process factors, the edges of the formed mask sidewalls 530 may have chamfered structures (e.g., rounded edges). Therefore, during the planarization of the sacrificial dielectric layer 540, the hard mask 512, mask sidewalls 530, and sacrificial dielectric layer 540 can be further planarized, removing a portion of the hard mask 512, mask sidewalls 530, and sacrificial dielectric layer 540 on the side facing away from the substrate 310. This allows for more polishing, removing the chamfered structure of the mask sidewalls 530 and resulting in smoother edges (e.g., approximately right angles). Of course, if the edges and corners of the formed mask sidewall 530 are relatively flat, the planarization process can be stopped when the hard mask 512 and the mask sidewall 530 are exposed.

[0101] Step 9: Referring to Figure 5I, an etching process is used to etch the hard mask 512 and the mask sidewalls 530 to form a regularly shaped first mask opening AK1. A portion of the mask sidewalls 530 is removed, leaving more of the sidewalls 530 closer to the substrate 310 and less closer to the substrate 310. This allows the remaining mask sidewalls 530 facing the first mask opening AK1 to form a specific shape, for example, a sloped sidewall. This makes the shape of the remaining mask sidewalls 530 facing the first mask opening AK1 complementary to the sidewall shape of the first electrode 430 to be formed. Based on this, the area of ​​the first mask opening AK1 penetrating the remaining mask sidewalls 530 can be used as a groove AC, allowing the groove AC to completely penetrate the remaining mask sidewalls 530. Furthermore, the etching process also removes the pad oxide layer 511 in the area of ​​the first mask opening AK1, exposing the surface of the vertical channel 410 facing away from the substrate 310. Based on this, the remaining mask sidewalls 530 can be used as the first dielectric layer 441, thus eliminating the need to perform the process of forming the first dielectric layer 441, simplifying the fabrication process and reducing production costs. Furthermore, the first mask opening AK1 can expose the entire area of ​​the surface of the pad oxide layer 511 facing away from the substrate 310. Therefore, the subsequently formed first electrode 430 can contact the entire area of ​​the surface of the vertical channel 410 facing away from the substrate 310. It is understood that the formed first mask opening AK1 can also expose a partial area of ​​the surface of the pad oxide layer 511 facing away from the substrate 310. Therefore, the subsequently formed first electrode 430 can contact a partial area of ​​the surface of the vertical channel 410 facing away from the substrate 310.

[0102] In other embodiments, if the shape of the first electrode 430 shown in FIG2B is desired, the mask sidewall 530 can be etched so that the remaining mask sidewall 530 forms an arc shape that is recessed toward the sidewall of the first mask opening AK1, so that the shape of the sidewall of the subsequently formed first electrode 430 can be an arc shape that is convex toward the sidewall of the groove.

[0103] In some other embodiments, if the shape of the first electrode 430 shown in FIG2C is desired, the mask sidewall 530 can be etched so that the remaining mask sidewall 530 forms an arc shape protruding away from the mask sidewall on the sidewall facing the first mask opening AK1, so that the shape of the sidewall of the subsequently formed first electrode 430 can be an arc shape protruding away from the sidewall of the groove.

[0104] Step 10: Referring to Figure 5J, fill the first electrode 430 in the first mask opening AK1 using an epitaxial process (e.g., vapor phase epitaxy, solid phase epitaxy). This fills the entire area of ​​the groove AC with the first electrode 430, forming a first electrode 430 with a wider top and narrower bottom structure. Exemplarily, the process of filling the first electrode 430 using a solid phase epitaxy process may include, but is not limited to, filling the first mask opening AK1 with a heavily doped amorphous semiconductor material layer using at least one deposition process such as CVD, PECVD, PVD, ALD, PEALD, etc. The semiconductor material of the amorphous semiconductor material layer may have the same or approximately the same lattice constant as the semiconductor material of the vertical channel 410. For example, if the material of the vertical channel 410 is silicon, the material of the heavily doped amorphous semiconductor material layer may be heavily doped amorphous silicon (aSi) or heavily doped amorphous silicon germanium (aSiGe), etc. Furthermore, the doped impurities include, but are not limited to, boron, indium, or phosphorus, arsenic, or combinations thereof. Subsequently, the filled amorphous semiconductor material layer undergoes solid-state epitaxy through low-temperature annealing (e.g., 500–650°C) in a furnace tube. The dopant ions in the amorphous semiconductor material layer are activated using processes such as spike annealing or laser spike annealing (LSA), thereby crystallizing the amorphous semiconductor material layer using solid-state epitaxy. This forms a first electrode 430 with heavily doped and crystalline semiconductor material, which directly contacts the vertical channel 410 exposed by the groove AC, achieving electrical connection between them. Furthermore, since the first mask opening AK1 is filled with a heavily doped amorphous semiconductor material layer, the formed first electrode 430 fills the entire area of ​​the groove AC and contacts the vertical channel 410, achieving electrical connection between them. Based on this, in this embodiment, a first electrode 430 with a wider top and narrower bottom structure can be formed.

[0105] Furthermore, in this embodiment, a deposition process is first used to fill the groove AC with material for forming the first electrode 430. This process has strong filling capability and a regular shape, avoiding the special shape and size variations seen in vapor phase epitaxy. This results in a regular shape and consistent size for the first electrode 430 formed in this embodiment, which helps reduce the size differences between the first electrodes 430 of different VFETs, reduces parasitic resistance differences, and consequently reduces electrical differences between devices. In addition, the temperature of vapor phase epitaxy in existing mass production processes is higher than that of solid phase epitaxy, which can have adverse effects on other films or structures in the VFET (e.g., the gate structure), affecting device reliability. In contrast, this embodiment uses a relatively lower-temperature solid phase epitaxy process and forms the first electrode 430 before fabricating the gate structure, avoiding any impact on the gate structure and improving device reliability. Moreover, compared to vapor phase epitaxy, solid phase epitaxy requires a lower thermal budget, which is beneficial for controlling impurity diffusion in the second electrode and other doped regions (e.g., Wells).

[0106] Furthermore, vapor phase epitaxy is a single-wafer process, resulting in a long processing time for batch fabrication of semiconductor devices. In contrast, solid phase epitaxy in this embodiment allows for multi-wafer processing, such as processing 150 wafers at a time, which increases production capacity and helps reduce costs.

[0107] Furthermore, the first electrode 430 and the etch barrier layer 450 of this rule can help form the subsequent self-aligned gate conductive layer, simplifying the process steps and improving manufacturability.

[0108] Since the lattice constant of the amorphous semiconductor material layer is the same as that of the vertical channel 410, and they are epitaxial, the material of the first electrode 430 can be a single-crystal structure. Furthermore, since current typically flows along the shortest path, the single-crystal structure of the first electrode 430 improves current flow.

[0109] Step 11: Referring to Figure 5K, dry etching is used to etch the first electrode 430 in the direction from the first isolation dielectric layer 424 to the second isolation dielectric layer 422, so that the surface of the first electrode 430 facing away from the substrate 310 is flush with the side of the mask sidewall 530 facing away from the substrate 310. Then, using at least one deposition process such as CVD, PECVD, PVD, ALD, or PEALD, a dielectric material layer is filled into the first mask opening AK1 on the first electrode 430. Subsequently, a process such as CMP is used to planarize the dielectric material layer, exposing the sacrificial dielectric layer 540, thereby forming an etch barrier layer 450 on the first electrode 430, covering the entire area of ​​the surface of the first electrode 430 facing away from the substrate 310. This configuration protects the first electrode 430 from damage by subsequent etching processes. For example, the material of the etch barrier layer 450 includes, but is not limited to, dielectric materials such as silicon nitride (SiN) and silicon carbonitride (SiCN).

[0110] In some embodiments, to enhance the protective effect of the etch barrier layer 450 on the first electrode 430, the orthogonal projection of the etch barrier layer 450 onto the substrate may cover the orthogonal projection of the first electrode 430 onto the substrate. Exemplarily, the orthogonal projection of the first electrode 430 onto the substrate falls within the orthogonal projection of the etch barrier layer 450 onto the substrate; alternatively, the edge of the orthogonal projection of the etch barrier layer 450 onto the substrate may coincide with the edge of the orthogonal projection of the first electrode 430 onto the substrate.

[0111] For example, since the recess AC is formed based on the etch mask sidewall 530, which is formed on the sidewall of the hard mask layer 510, which is used to etch and form the vertical channel 410, the first electrode 430 is formed in the recess AC such that the first electrode 430 is essentially self-aligned based on the hard mask layer 510 (or the vertical channel 410). Therefore, the first electrode 430 of different VFETs can be made to have the same size and regular shape, and the orthogonal projection of the first electrode 430 on the substrate 310 can be symmetrically arranged with respect to the orthogonal projection of the vertical channel 410 on the substrate 310, thereby improving the reliability of the device. Specifically, referring to Figure 5K, the first electrode 430 may include a first partial electrode Db1, a second partial electrode Db2, and a third partial electrode Db3. The orthographic projection of the second partial electrode Db2 onto the substrate 310 coincides with the orthographic projection of the vertical channel 410 onto the substrate 310. The first partial electrode Db1 and the third partial electrode Db3 are symmetrical about the second partial electrode Db2.

[0112] Step 12: Referring to Figure 5L, an etching process is used to etch away the sacrificial dielectric layer 540, exposing the first isolation dielectric layer 424. Then, using an etch stop layer 450 as an etch mask, a self-aligned etching process is used to remove the first isolation dielectric layer 424 exposed by the etch mask, thereby exposing the dummy gate 520 in the area not covered by the etch mask. It is worth noting that the first isolation dielectric layer 424 is formed based on self-alignment of the etch mask; therefore, the formed first isolation dielectric layer 424 is symmetrically arranged about the vertical channel 410, that is, the first isolation dielectric layer 424 is completely symmetrical along the central axis of the VFET, thereby improving device reliability.

[0113] Step 13: Referring to Figure 5M, wet etching is used to remove the dummy gate 520 and the insulating dielectric layer 470 covered by the dummy gate 520, exposing the area of ​​the vertical channel 410 covered by the dummy gate 520.

[0114] Step 14: Referring to Figure 5N, a gate dielectric layer 4232 is formed, followed by filling with metal material to form a gate metal layer 4231, thereby forming a gate structure 423. Afterwards, planarization can be performed using processes such as CMP to expose the etch stop layer 450. Further, a high-k dielectric material layer can be formed before forming the gate metal layer 4231, thereby making the formed gate structure 423 HKMG. For example, the material of the gate dielectric layer 4232 can be SiO2.

[0115] Step 15: Referring to Figure 5O, using the etch stop layer 450 as an etch mask, an etching process is employed to self-align and etch away the gate metal layer 4231, the second isolation dielectric layer 422, and the second electrode 421 in the areas not covered by the etch mask. This self-aligns and cuts off the gate metal layer 4231, the second isolation dielectric layer 422, and the second electrode 421 of different VFETs, thereby realizing the replacement metal gate (RMG) process. Afterwards, the substrate 310 is further etched in the direction from the first isolation dielectric layer 424 to the second isolation dielectric layer 422, forming an isolation trench in the substrate 310 to isolate the different VFETs. Exemplarily, the substrate 310 can also be etched to form the isolation trench during the etching of the gate metal layer 4231, the second isolation dielectric layer 422, and the second electrode 421. Alternatively, since the etching of the gate metal layer 4231, the second isolation dielectric layer 422, and the second electrode 421 may also damage the etching barrier layer 450 and the mask sidewall 530, and considering that the thickness of the etching barrier layer 450 and the mask sidewall 530 may not be sufficient to support the etching isolation trench, a photolithography step can be added after etching the gate metal layer 4231, the second isolation dielectric layer 422, and the second electrode 421 to form photoresist on the etching barrier layer 450, and then the substrate 310 is etched to form the isolation trench, thereby realizing the semi-self-aligned etching isolation trench between the devices.

[0116] It is worth mentioning that the second isolation dielectric layer 422 and the second electrode 421 are formed based on the hard mask layer 510 through self-alignment. Therefore, the formed second isolation dielectric layer 422 and the second electrode 421 are symmetrically arranged about the vertical channel 410, that is, the second isolation dielectric layer 422 and the second electrode 421 are completely symmetrical along the central axis of the VFET, thereby improving the reliability of the device. Thus, each formed VFET is completely symmetrical along its central axis, further improving the reliability of the device. Furthermore, using self-alignment to form the VFET reduces the complexity of the process and eliminates errors in the photolithography process, further enhancing the reliability of the device.

[0117] Step 16: Referring to Figure 5P, an interlayer dielectric layer 501 covering multiple VFETs is deposited using a dielectric material. The interlayer dielectric layer 501 also fills the regions between different VFETs. By filling isolation trenches with the interlayer dielectric layer 501, a trench isolation structure (e.g., a shallow trench isolation (STI) structure) can be formed to isolate different VFETs using the interlayer dielectric layer 501. Exemplarily, the material of the interlayer dielectric layer 501 may include, but is not limited to: silicon dioxide (SiO2), silicon oxycarbonate (SiOC), silicon nitride (Si3N4), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxynitride (SiON), silicon carbonitride (SiOCN), or combinations thereof.

[0118] Afterwards, subsequent metal interconnection processes can be performed to complete the semiconductor device fabrication process. For example, referring to FIG5P, an etching process is used to form through-hole contact holes in the etch stop layer 450 and the interlayer dielectric layer 501 to expose a portion of the first electrode 430 through the contact holes, so that the etch stop layer 450 does not completely cover the first electrode 430. Then, a conductive material (e.g., a metal material) is deposited in the contact holes to form an interconnect portion 460 connected to the first electrode 430. Then, an interconnect wiring layer can be formed on the interconnect portion 460, the interconnect wiring layer having signal wiring, and electrically connecting the signal wiring to the interconnect portion 460 to transmit signals to the first electrode 430 through the signal wiring. Similarly, an interconnect portion 460 connected to the second electrode 421 and its electrically connected signal wiring can also be formed, as well as an interconnect portion 460 connected to the gate conductive layer and its electrically connected signal wiring, to realize the transmission of signals to the second electrode 421 and the gate metal layer 4231.

[0119] This application also provides another semiconductor device fabrication process, which can be obtained by modifying steps 1 to 16 in the above embodiments. The similarities in each step are not repeated here, and the differences in the relevant steps are explained below. Among them, Figures 6A to 6C are cross-sectional views of another semiconductor device fabrication process in this application embodiment.

[0120] Step 9: Referring to Figure 6A, an etching process is used to remove the entire area of ​​the hard mask 512 and the mask sidewalls 530, forming the second mask opening AK2. Then, referring to Figure 6B, a first dielectric layer 441 is deposited on the sidewall of the second mask opening AK2, exposing the pad oxide layer 511. Then, referring to Figure 6C, an etching process is used to etch away a portion of the first dielectric layer 441, leaving a larger portion of the first dielectric layer 441 near the substrate 310 and a smaller portion away from the substrate 310. This ensures that the sidewall of the remaining first dielectric layer 441 facing away from the sacrificial dielectric layer 540 is complementary in shape to the sidewall of the first electrode 430 to be formed. For example, the sidewall of the first dielectric layer 441 facing away from the sacrificial dielectric layer 540 forms a raised arc shape facing away from the first dielectric layer 441. Based on this, the area of ​​the second mask opening AK2 penetrating the remaining first dielectric layer 441 can be used as a groove AC, allowing the groove AC to completely penetrate the remaining first dielectric layer 441. Furthermore, the etching process removes the pad oxide layer 511 in the region of the second mask opening AK2, exposing the surface of the vertical channel 410 facing away from the substrate 310. Based on this, the shape of the first electrode 430 shown in FIG. 2C can be formed, and the formation of the first dielectric layer 441 through other processes can improve the plasticity of the shape of the first electrode 430 formed subsequently. Exemplarily, the material of the first dielectric layer 441 includes, but is not limited to, dielectric materials such as silicon nitride (SiN) and silicon carbonitride (SiCN).

[0121] In other embodiments, if the shape of the first electrode 430 shown in FIG2A is desired, the first dielectric layer 441 can be etched so that the sidewall of the remaining first dielectric layer 441 facing away from the sacrificial dielectric layer 540 is sloping, thereby making the sidewall of the subsequently formed first electrode 430 sloping.

[0122] In other embodiments, if the shape of the first electrode 430 shown in FIG2B is desired, the first dielectric layer 441 can be etched so that the remaining first dielectric layer 441 forms an arc shape that is recessed toward the sidewall of the sacrificial dielectric layer 540, thereby making the sidewall of the subsequently formed first electrode 430 have an arc shape that is convex toward the sidewall of the groove AC.

[0123] Figure 7 is a schematic diagram of another structure of the semiconductor device in this application embodiment. Referring to Figure 7, this embodiment modifies the implementation method in the above embodiments. The similarities are not repeated here. The difference is that the surface Se of the vertical channel 410 on the side facing away from the substrate 310 is lower than the surface Sd_1 of the first isolation dielectric layer 424 on the side facing away from the substrate 310, and the surface Se of the vertical channel 410 on the side facing away from the substrate 310 is higher than the surface Sd_2 of the first isolation dielectric layer 424 on the side facing the substrate 310. As a result, there is a recessed region AX between the surface Se of the vertical channel 410 on the side facing away from the substrate 310 and the surface Sa_1 of the first electrode 430 on the side facing the substrate 310. Based on this, a conductive structure 431 can be filled in the recessed region AX so that the first electrode 430 is electrically connected to the vertical channel 410 through the conductive structure 431, thereby reducing the high-resistance region, increasing the on-state current, and improving the device performance.

[0124] The fabrication process for forming the semiconductor device structure shown in Figure 7 can be obtained by modifying steps 1 to 16 in the above embodiments. The similarities in each step will not be repeated here, and the differences between the relevant steps will be explained below. Among them, Figures 8A to 8C are cross-sectional views of another semiconductor device fabrication process in the embodiments of this application.

[0125] Step 6: Referring to Figure 8A, the first isolation dielectric layer 424 not only surrounds the first spacer region of the vertical channel 410 through the gate dielectric layer 4232, but also surrounds the pad oxide layer 511.

[0126] Step 7: Referring to Figure 8B, the mask sidewall 530 is formed on the sidewall of the hard mask 512.

[0127] Step 9: Referring to Figure 8C, remove the pad oxide layer 511 using an etching process. In some embodiments, if the pad oxide layer 511 has a certain thickness, removing the pad oxide layer 511 can form a deep recessed region AX, thereby forming a conductive structure 431 with a certain thickness in the recessed region AX. Alternatively, the pad oxide layer 511 may be relatively thin, resulting in a shallow or even negligible depth in the recessed region AX formed after removing the pad oxide layer 511, thus making the thickness of the subsequently formed conductive structure 431 relatively small or negligible. However, in order to reduce the high-resistivity region, the vertical channel 410 can be further etched so that the surface Se of the vertical channel 410 facing away from the substrate 310 is lower than the surface Sd_1 of the first isolation dielectric layer 424 facing away from the substrate 310, and the surface Se of the vertical channel 410 facing away from the substrate 310 is higher than the surface Sd_2 of the first isolation dielectric layer 424 facing the substrate 310, thereby forming a recessed region AX with a certain depth, and the conductive structure 431 formed in the recessed region AX has a certain thickness.

[0128] Subsequently, while epitaxially forming the first electrode 430, a conductive structure 431 can also be epitaxially formed in the recessed region AX, thereby making the first electrode 430 and the conductive structure 431 an integral structure of the same material, reducing the difficulty of the process. It is worth mentioning that although the conductive structure 431 and the first electrode 430 can be set as an integral structure, the overall structure of the first electrode 430 does not include the conductive structure 431; that is, the overall structure of the first electrode 430 is located on the plane of the surface of the first insulating dielectric layer 424 facing away from the substrate 310, which faces away from the substrate 310. In other embodiments, the first electrode 430 can also be fabricated after the conductive structure 431 is fabricated, thereby making the first electrode 430 and the conductive structure 431 separate structures of different materials.

[0129] In other embodiments, the vertical channel 410 may not be etched after the pad oxide layer 511 is removed. Since ion doping occurs during the epitaxial formation of the first electrode 430 (e.g., solid-state epitaxy), these doped ions diffuse into the vertical channel 410, implanting ions into a portion of the vertical channel 410 on the side facing away from the substrate 310. This causes the portion to become conductive, forming a conductive structure 431. The remaining area of ​​the vertical channel 410 becomes the body region of the vertical channel 410. Therefore, the surface Se on the side of the vertical channel 410 facing away from the substrate 310 can be the surface of the body region of the vertical channel 410 facing away from the substrate 310.

[0130] Figure 9 is a schematic diagram of another structure of the semiconductor device in an embodiment of this application. Referring to Figure 9, this embodiment modifies the implementation method in the above embodiments. The similarities are not repeated here. The difference is that it also includes a second dielectric layer 442 at least disposed on both sides of the first dielectric layer 441, and the height h2 of the second dielectric layer 442 along the vertical direction F0 is greater than the height h1 of the first dielectric layer 441 along the vertical direction F0, i.e., h2>h1. Therefore, the second dielectric layer 442 can be used to protect the first dielectric layer 441. Since the etching process may occur multiple times during the fabrication process, the etching work will inevitably damage the first dielectric layer 441. If the first dielectric layer 441 is etched through by these etching processes, the first electrode 430 will be exposed and etched. Therefore, by protecting the first dielectric layer 441 with the second dielectric layer 442, the risk of the first dielectric layer 441 being penetrated by multiple etching processes can be reduced, further reducing the risk of the first electrode 430 being etched and damaged, and improving the stability of the device.

[0131] It is understood that in other embodiments of this application, h2 can also be h1, and this is not limited here.

[0132] In some embodiments, referring to FIG9, the second dielectric layer 442 may be disposed on the side of the first isolation dielectric layer 424 facing away from the substrate 310, thereby forming the second dielectric layer 442 on the side of the first isolation dielectric layer 424 facing away from the substrate 310, thereby achieving the effect of protecting the first dielectric layer 441.

[0133] In some embodiments, referring to FIG9, the sum of the height h1 of the first dielectric layer 441 along the vertical direction F0 and the height h3 of the etch stop layer 450 along the vertical direction F0 can be the same as the height h2 of the second dielectric layer 442 along the vertical direction F0, i.e., h1 + h3 = h2. This further protects the etch stop layer 450 from etching, further reducing the risk of etching damage to the first electrode 430 and improving device stability. In other embodiments, h2 can also be... h1+h3.<h1>

[0134] The fabrication process for forming the semiconductor device structure shown in Figure 9 can be obtained by modifying steps 1 to 16 in the above embodiments. The similarities in each step will not be repeated here; the differences between the relevant steps are explained below. For example, in step 13, after etching away the sacrificial dielectric layer 540, a second dielectric layer 442 is deposited. Then, using the second dielectric layer 442 and the etch stop layer 450 as an etch mask, a self-aligned etch is performed to remove the first isolation dielectric layer 424 exposed by the etch mask.

[0135] Figure 10A is a schematic diagram of another structure of the semiconductor device in an embodiment of this application. Referring to Figure 10A, this embodiment modifies the implementation method in the above embodiments. The similarities are not repeated here. The difference is that the first region BQ1 of the groove AC may include a first sub-region BQ1a and a second sub-region BQ1b. The first sub-region BQ1a is located between the second sub-region BQ1b and the second region BQ2. The first sub-region BQ1a penetrates the first dielectric layer 441, and the second sub-region BQ1b and the second region BQ2 penetrate the second dielectric layer 442. Based on this, a groove AC of a specific shape can be formed by the first dielectric layer 441 and the second dielectric layer 442. Then, a first electrode 430 is epitaxially formed in the groove AC. A portion of the sidewall of the first electrode 430 can contact the first dielectric layer 441, and another portion of the sidewall of the first electrode 430 can contact the second dielectric layer 442, so that the sidewall of the first electrode 430 and the sidewall of the first and second dielectric layers in contact with it have complementary shapes, thereby making the epitaxially formed first electrode 430 also have a specific shape. Based on this, a simple fabrication process can be used to form the first electrode 430 with the specific structure of this application, reducing the difficulty of fabrication. In addition, a first dielectric layer 441 and a second dielectric layer 442 can be used together to protect the sidewalls of the first electrode 430, preventing damage to the first electrode 430 from other processes (such as etching processes).

[0136] For example, the materials of the first dielectric layer 441 and the second dielectric layer 442 may be different. For instance, the materials of the first dielectric layer 441 and the second dielectric layer 442 may be materials with greater etching selectivity. Alternatively, the materials of the first dielectric layer 441 and the second dielectric layer 442 may be the same, without limitation.

[0137] In some embodiments, referring to FIG10A, the first electrode 430 may fill the first region BQ1, thereby making a portion of the sidewall of the first electrode 430 contact the first dielectric layer 441 and another portion of the sidewall of the first electrode 430 contact the second dielectric layer 442, so that the first dielectric layer 441 and the second dielectric layer 442 are combined with each other, and the shape of the sidewall of the formed first electrode 430 in the vertical direction may also be stepped or other feasible shapes.

[0138] The fabrication process for forming the structure of the semiconductor device shown in Figure 10A can be obtained by modifying steps 1 to 16 in the above embodiments. The similarities in each step will not be repeated here. The differences between the relevant steps are explained below.

[0139] Step 12: After etching away the sacrificial dielectric layer 540, a second dielectric layer 442 is formed on the first isolation dielectric layer 424. Then, using the etch stop layer 450 and the second dielectric layer 442 as an etch mask, self-aligned etching is used to remove the first isolation dielectric layer 424 exposed by the etch mask, exposing the virtual gate 520 in the area not covered by the etch mask.

[0140] In some embodiments, referring to FIG10A, the second dielectric layer 442 may be retained in the semiconductor device to improve the structural stability of the VFET.

[0141] In other embodiments, referring to FIG10B, the second dielectric layer 442 can also be removed by etching in subsequent process flows, so that the second dielectric layer 442 is not retained in the semiconductor device, and a portion of the sidewall of the first electrode 430 contacts the first dielectric layer 441, and another portion of the sidewall of the first electrode 430 contacts the interlayer dielectric layer 501. Based on this, the interlayer dielectric layer 501 can be regarded as the second dielectric layer 442 in the final semiconductor device.

[0142] The above content is only a specific implementation of this application, but the protection scope of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the protection scope of this application.

Claims

1. A semiconductor device, characterized by, include: Substrate; A vertical channel is disposed on the substrate and extends in a vertical direction, the vertical direction being perpendicular to the layer in which the substrate is located; A stacked structure is disposed on the substrate and at least on both sides of the vertical channel. The stacked structure includes a gate structure and a first isolation dielectric layer stacked along the vertical direction. The first isolation dielectric layer is disposed on the side of the gate structure facing away from the substrate. A groove is disposed on the side of the first isolation dielectric layer facing away from the substrate, and the orthographic projection of the groove on the substrate and the orthographic projection of the vertical channel on the substrate have an overlapping area; A first electrode is disposed in the groove and connected to the vertical channel through the groove. The first electrode has a first width along a first direction, and the first width tends to decrease in the direction from the first electrode to the substrate. The first direction is perpendicular to the vertical direction.

2. The semiconductor device of claim 1, wherein, In the direction from the first electrode to the substrate, the first width decreases continuously or in a stepwise manner, or a combination thereof.

3. The semiconductor device of claim 2, wherein, In the direction from the first electrode to the substrate, the first width decreases in a continuous manner, and the sidewall of the first electrode in the vertical direction is one or a combination of a ramp shape, an arc shape convex towards the sidewall of the groove, and an arc shape convex away from the sidewall of the groove.

4. The semiconductor device of claim 2, wherein, In the direction from the first electrode to the substrate, the first width decreases in a stepped manner, and the sidewall of the first electrode has a stepped shape in the vertical direction.

5. The semiconductor device according to any one of claims 1 to 4, wherein It also includes a first dielectric layer disposed on the side of the first isolation dielectric layer facing away from the substrate, the groove includes a first region and a second region, the first region is located between the second region and the first isolation dielectric layer, and at least the first region penetrates the first dielectric layer; The first electrode at least fills the first region and is connected to the vertical channel, and the sidewalls of the first electrode and the sidewalls of the first dielectric layer in contact with it have complementary shapes.

6. The semiconductor device of claim 5, wherein, It also includes a second dielectric layer disposed on at least both sides of the first dielectric layer, wherein the height of the second dielectric layer along the vertical direction is greater than the height of the first dielectric layer along the vertical direction.

7. The semiconductor device according to claim 5 or 6, wherein Both the first and second regions of the groove penetrate the first dielectric layer.

8. The semiconductor device of claim 7, wherein, The first electrode fills the first region and the second region.

9. The semiconductor device of claim 6, wherein, The first region includes a first sub-region and a second sub-region. The first sub-region is located between the second sub-region and the second region. The first sub-region penetrates the first dielectric layer, and the second sub-region and the second region penetrate the second dielectric layer.

10. The semiconductor device of claim 9, wherein, The first electrode fills the first region.

11. The semiconductor device according to any one of claims 1 to 10, wherein The semiconductor device further includes an interconnect portion disposed on the side of the first electrode facing away from the substrate and connected to the first electrode; The surface of the interconnect facing the substrate is projected onto the substrate in the same way that the surface of the first electrode facing away from the substrate is projected onto the substrate.

12. The semiconductor device of claim 11, wherein, The semiconductor device further includes an etch barrier layer disposed on the side of the first electrode facing away from the substrate, and the interconnect portion penetrates the etch barrier layer and is connected to the first electrode.

13. The semiconductor device of any one of claims 1-12, wherein, The orthographic projection of the surface of the first electrode facing the substrate onto the substrate covers the orthographic projection of the vertical channel onto the substrate.

14. The semiconductor device according to any one of claims 1 to 13, wherein The first electrode includes a first partial electrode, a second partial electrode, and a third partial electrode. The orthographic projection of the second partial electrode onto the substrate coincides with the orthographic projection of the vertical channel onto the substrate. The first partial electrode and the third partial electrode are symmetrical about the second partial electrode.

15. A method of manufacturing a semiconductor device, characterized by, include: A vertical channel extending along the vertical direction is formed on the substrate, a stacked structure is formed at least on both sides of the vertical channel, a groove is formed on the side of the first isolation dielectric layer facing away from the substrate, and a first electrode is formed in the groove. Wherein, the orthographic projection of the groove on the substrate and the orthographic projection of the vertical channel on the substrate have an overlapping area, the first electrode is connected to the vertical channel through the groove, the stacked structure includes a gate structure and a first isolation dielectric layer stacked along the vertical direction, the first isolation dielectric layer is disposed on the side of the gate structure facing away from the substrate, the first electrode has a first width along a first direction, the first width tends to decrease in the direction from the first electrode to the substrate, the first direction is perpendicular to the vertical direction, and the vertical direction is perpendicular to the layer where the substrate is located.

16. The production method according to claim 15, wherein A hard mask layer is formed on the side of the vertical channel facing away from the substrate. The hard mask layer includes a hard mask and a pad oxide layer. The pad oxide layer is located between the hard mask and the vertical channel. The first electrode formed in a groove on the side of the first insulating dielectric layer facing away from the substrate includes: Mask sidewalls and sacrificial dielectric layers are formed on both sides of the hard mask layer; The hard mask is etched away to form a first mask opening; The mask sidewalls are etched to form at least a portion of the groove in the mask sidewalls, and the sidewalls of the retained mask sidewalls facing away from the sacrificial dielectric layer are complementary in shape to the sidewalls of the first electrode to be formed; wherein the retained mask sidewalls are the first dielectric layer; The first electrode is formed by filling the groove using an epitaxial process.

17. The production method according to claim 15, wherein A hard mask layer is formed on the side of the vertical channel facing away from the substrate. The hard mask layer includes a hard mask and a pad oxide layer. The pad oxide layer is located between the hard mask and the vertical channel. The first electrode formed in a groove on the side of the first insulating dielectric layer facing away from the substrate includes: Mask sidewalls and sacrificial dielectric layers are formed on both sides of the hard mask layer; The hard mask layer and the mask sidewalls are etched away to form a second mask opening; A first dielectric layer is formed in the second mask opening, and at least a portion of the groove is formed in the first dielectric layer such that the sidewall of the first dielectric layer facing away from the sacrificial dielectric layer is complementary to the sidewall shape of the first electrode to be formed. The first electrode is formed by filling the groove with a heavily doped amorphous semiconductor material layer using an epitaxial process.

18. An integrated circuit, comprising: include: Electronic devices and semiconductor devices, wherein the electronic devices are connected to the semiconductor devices; The semiconductor device is the semiconductor device as described in any one of claims 1-14, or the semiconductor device is a semiconductor device prepared by the method for preparing a semiconductor device as described in any one of claims 15-17.

19. An electronic device, comprising: include: The circuit board and the integrated circuit as claimed in claim 18, wherein the integrated circuit is disposed on the circuit board.

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