Semiconductor structure and method for forming same

Abstract

The present application provides a semiconductor structure and a method for forming same. The semiconductor structure comprises: a semiconductor substrate, wherein an epitaxial layer is formed on a first surface of the semiconductor substrate, and a plurality of junction implants are formed in the epitaxial layer; a JFET region, located between the plurality of junction implants, wherein the distance between two adjacent junction implants among the plurality of junction implants is defined as a JFET gap; and a plurality of buried implant regions, located in part of the JFET region, wherein the top surfaces of the buried implant regions are lower than the top surface of the JFET region, and the doping type of the buried implant regions is opposite to the doping type of the JFET region. The present application provides a semiconductor structure and a method for forming same. The buried implant regions are formed in the JFET region as an electric field shielding layer, to achieve balance between an electric field and a current without reducing the channel density; in addition, the process is simple, and further scaling down of the size of the JFET region will not be affected.

Description

A semiconductor structure and its formation method Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] Wide bandgap semiconductors, due to their high critical breakdown electric field, can withstand high blocking voltages while providing low on-resistance, making them ideal for fabricating power semiconductor devices. However, improper handling of the electric field inside the device can lead to both premature breakdown due to electric field concentration and reduced gate reliability due to electric field concentration in the gate dielectric.

[0003] Compared to silicon devices, silicon carbide (SiC) devices have a 1-2 order of magnitude higher interface state density. This results in lower channel mobility at the SiC / silicon oxide interface. While square and hexagonal cell techniques are highly effective in increasing channel density per unit area, they also lead to electric field concentration within the SiC device and in the gate dielectric. Furthermore, the current concentration in the diagonal JFET region of square and hexagonal cells in SiC MOSFETs reduces the device's reliability.

[0004] Therefore, optimizing the channel resistance of SiC MOSFETs using cell techniques such as square cells and hexagonal cells necessarily requires optimizing the electric field balance within the device body and the gate dielectric, as well as the current balance in the JFET region of the device. Summary of the Invention

[0005] The purpose of this invention is to optimize the electric field balance within the SiC MOSFET device and in the gate dielectric, as well as the current balance in the JFET region of the device.

[0006] One aspect of this application provides a semiconductor structure comprising: a semiconductor substrate having an epitaxial layer formed on a first surface thereon, wherein a plurality of junction implants are formed in the epitaxial layer; a JFET region located between the plurality of junction implants, wherein the distance between two adjacent junction implants is defined as a JFET gap; and a plurality of buried implant regions located in portions of the JFET region, wherein the top surface of the buried implant regions is lower than the top surface of the JFET region, and the doping type of the buried implant regions is opposite to the doping type of the JFET region.

[0007] In some embodiments of this application, the JFET gap is uniform throughout the semiconductor structure, and the plurality of buried implantation regions are uniformly located in the JFET region.

[0008] In some embodiments of this application, each of the plurality of injection sites is strip-shaped.

[0009] In some embodiments of this application, the JFET gap is non-uniform throughout the semiconductor structure, and the JFET region is divided into a first JFET sub-region and a second JFET sub-region according to the different JFET gaps.

[0010] In some embodiments of this application, the JFET gap of the first JFET sub-region is smaller than the JFET gap of the second JFET sub-region, and the plurality of buried injection regions are located in the second JFET sub-region.

[0011] In some embodiments of this application, each of the plurality of injection sites is rectangular or hexagonal.

[0012] In some embodiments of this application, the semiconductor substrate is made of doped silicon carbide, the epitaxial layer is made of doped silicon carbide, the semiconductor substrate and the epitaxial layer have the same doping type, and the doping concentration of the semiconductor substrate is greater than the doping concentration of the epitaxial layer.

[0013] In some embodiments of this application, the plurality of buried injection zones also extend partially into the knot injection material.

[0014] In some embodiments of this application, the doping concentration of the plurality of buried implantation regions is 9E15 to 6E17 cm⁻¹. -3 .

[0015] Another aspect of this application provides a method for forming a semiconductor structure, comprising: providing a semiconductor substrate, wherein an epitaxial layer is formed on a first surface of the semiconductor substrate, and a plurality of junction implants are formed in the epitaxial layer; forming a JFET region between the plurality of junction implants, wherein the distance between two adjacent junction implants is defined as a JFET gap; forming a plurality of buried implant regions in a portion of the JFET region, wherein the top surface of the buried implant regions is lower than the top surface of the JFET region, and the doping type of the buried implant regions is opposite to the doping type of the JFET region.

[0016] In some embodiments of this application, the JFET gap is uniform throughout the semiconductor structure, and the plurality of buried implantation regions are uniformly located in the JFET region.

[0017] In some embodiments of this application, each of the plurality of injection sites is strip-shaped.

[0018] In some embodiments of this application, the JFET gap is non-uniform throughout the semiconductor structure, and the JFET region is divided into a first JFET sub-region and a second JFET sub-region according to the different JFET gaps.

[0019] In some embodiments of this application, the JFET gap of the first JFET sub-region is smaller than the JFET gap of the second JFET sub-region, and the plurality of buried injection regions are located in the second JFET sub-region.

[0020] In some embodiments of this application, each of the plurality of injection sites is rectangular or hexagonal.

[0021] In some embodiments of this application, the semiconductor substrate is made of doped silicon carbide, the epitaxial layer is made of doped silicon carbide, the semiconductor substrate and the epitaxial layer have the same doping type, and the doping concentration of the semiconductor substrate is greater than the doping concentration of the epitaxial layer.

[0022] In some embodiments of this application, the plurality of buried injection zones also extend partially into the knot injection material.

[0023] In some embodiments of this application, the doping concentration of the plurality of buried implantation regions is 9E15 to 6E17 cm⁻¹. -3 .

[0024] This application provides a semiconductor structure and its formation method, in which a buried implantation region is formed in the JFET region as an electric field shielding layer, achieving a balance between electric field and current without reducing channel density, and the process is simple and does not affect the continued miniaturization of the JFET region size. Attached Figure Description

[0025] The following accompanying drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals denote similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting and exemplary, and the drawings are for illustrative purposes only and are not intended to limit the scope of this application. Other embodiments may similarly fulfill the inventive intent of this application. It should be understood that the drawings are not drawn to scale. Wherein:

[0026] Figure 1 is a schematic diagram of the longitudinal cross-section of the semiconductor structure described in some embodiments of this application;

[0027] Figure 2 is a top view of the semiconductor structure described in the first embodiment of this application;

[0028] Figure 3 is a top view of the semiconductor structure described in the second embodiment of this application;

[0029] Figure 4 is a top view of the semiconductor structure described in the third embodiment of this application;

[0030] Figure 5 is a flowchart of a method for forming a semiconductor structure according to some embodiments of this application. Detailed Implementation

[0031] The following description provides specific application scenarios and requirements for this application, intended to enable those skilled in the art to make and use the content of this application. Various partial modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but rather to the widest scope consistent with the claims.

[0032] The technical solution of the present invention will be described in detail below with reference to the embodiments and accompanying drawings.

[0033] Figure 1 is a schematic longitudinal cross-sectional view of a semiconductor structure according to some embodiments of this application. Figure 1 shows a semiconductor structure unit 10 according to some embodiments of this application.

[0034] Referring to Figure 1, the semiconductor structure unit 10 includes a semiconductor substrate 100, an epitaxial layer 110 is formed on a first surface of the semiconductor substrate 100, and a plurality of junction implants 120 are formed in the epitaxial layer 110. Each junction implant 120 includes a well region 121 and a source well 122. The source well 122 is located within the well region 121 and can be surrounded by the well region 121.

[0035] In some embodiments of this application, the semiconductor substrate 100 is made of doped silicon carbide, the epitaxial layer 110 is made of doped silicon carbide, the semiconductor substrate 100 and the epitaxial layer 110 have the same doping type, and the doping concentration of the semiconductor substrate 100 is greater than the doping concentration of the epitaxial layer 110.

[0036] In some embodiments of this application, the semiconductor substrate 100 is N-type doped, and the doping concentration of the semiconductor substrate 100 is 1E19 to 1E20 cm⁻¹. -3 The epitaxial layer 110 is N-type doped, and the doping concentration of the epitaxial layer 110 is between 5E13 and 1E17 cm⁻¹. -3 .

[0037] In some embodiments of this application, the well region 121 is p-type doped, and the doping concentration of the well region 121 is 1E16 to 3E19 cm⁻¹. -3 The source well 122 is N-type doped, and the doping concentration of the source well 122 is 1E20 to 1E21 cm⁻¹. -3 .

[0038] Referring again to Figure 1, the semiconductor structure unit 10 further includes a JFET (Junction Field-Effect Transistor) region 130 located between the plurality of junction implants 120. The distance between two adjacent junction implants 120 is defined as the JFET gap. The depth of the JFET region 130 may be greater than the depth of the junction implants 120. The JFET region 130 may extend to the bottom of a portion of the junction implants 120.

[0039] In some embodiments of this application, the JFET region 130 is N-type doped, and the doping concentration of the JFET region 130 is 1E16 to 2E17 cm⁻¹. -3 .

[0040] Referring again to Figure 1, the semiconductor structure unit 10 further includes a plurality of buried implantation regions 140 located in a portion of the JFET region 130. The top surface of the buried implantation region 140 is lower than the top surface of the JFET region 130, and the doping type of the buried implantation region 140 is opposite to that of the JFET region 130.

[0041] In some embodiments of this application, the buried implantation region 140 is p-type doped, and the doping concentration of the buried implantation region 140 is 9E15 to 6E17 cm⁻¹. -3 .

[0042] In some embodiments of this application, the plurality of buried injection zones 140 further extend into the knot injection 120.

[0043] Referring again to FIG1, the semiconductor structure unit 10 further includes: a gate dielectric layer 150 located on the surface of the epitaxial layer 110, the gate dielectric layer 150 extending between the source wells 122 of each of the junction implants 120; a gate layer 170 located on the surface of the gate dielectric layer 150; a source metal 160 located on the surface of the epitaxial layer 110, the source metal 160 on a portion of the well region 121 and the source well 122 in each junction implant 120; and a drain metal 180 located on a second surface of the semiconductor substrate 100 opposite to the first surface.

[0044] It should be noted that the semiconductor structural unit 10 is so named because it is the smallest unit of a larger semiconductor structure. The semiconductor structure of this application may include hundreds or thousands of said semiconductor structural units 10 repeated in various geometric configurations. The semiconductor structural unit 10 shown in FIG1 is represented as a two-dimensional cross-section. In practice, the semiconductor structural unit 10 extends into and out of the page in three dimensions as a rectangular cuboid. The semiconductor structural unit 10 may be mirrored or repeated to extend into and out of the page. Furthermore, the semiconductor structural unit 10 may be symmetrically mirrored on its left and right sides and may continue to be repeated in this manner to achieve the desired size.

[0045] Figure 2 is a top view of the semiconductor structure described in the first embodiment of this application. In the first embodiment, Figure 1 can be a longitudinal cross-sectional view along the dashed line AA in Figure 2. The gate dielectric layer, gate layer, and source metal are not shown in Figure 2.

[0046] Referring to FIG2, in a first embodiment of this application, the JFET gap is uniform throughout the semiconductor structure (e.g., each of the plurality of junction implants 120 is strip-shaped), and the plurality of buried implant regions 140 are uniformly located within the JFET region 130. The configuration shown in FIG2 is commonly referred to as a “strip” design because the junction implants 120 are strip-shaped throughout the device.

[0047] In the technical solution of this application, when the JFET gap is uniform throughout the semiconductor structure, a plurality of buried implantation regions 140 are uniformly arranged in the JFET region 130. This can achieve the balance of electric field and current without reducing the channel density, and the process is simple and does not affect the continued miniaturization of the JFET region size.

[0048] The first embodiment of this application illustrates the case where the JFET gap is uniform throughout the semiconductor structure, with each of the plurality of junction implants 120 being strip-shaped. The second and third embodiments will then be used to illustrate the case where the JFET gap is non-uniform throughout the semiconductor structure, with each of the plurality of junction implants 120 being rectangular or hexagonal.

[0049] Figure 3 is a top view of the semiconductor structure described in the second embodiment of this application. In the second embodiment, Figure 1 can be a longitudinal cross-sectional view along the dashed line BB in Figure 3. The gate dielectric layer, gate layer, and source metal are not shown in Figure 3.

[0050] Referring to Figure 3, in the second embodiment of this application, the JFET gap is non-uniform throughout the semiconductor structure. Based on the different JFET gaps, the JFET region 130 is divided into a first JFET sub-region 130a and a second JFET sub-region 130b.

[0051] In a second embodiment of this application, the JFET gap of the first JFET sub-region 130a is smaller than the JFET gap of the second JFET sub-region 130b, and the plurality of buried injection regions 140 are located in the second JFET sub-region 130b. In Figure 3, to clearly show the second JFET sub-region 130b, one of the second JFET sub-regions 130b omits the buried injection region 140.

[0052] In a second embodiment of this application, each of the plurality of junction implants 120 is rectangular. The configuration shown in FIG3 is commonly referred to as a “cell” design because the junction implants 120 are square across the entire device.

[0053] Figure 4 is a top view of the semiconductor structure described in the third embodiment of this application. In the third embodiment, Figure 1 can be a longitudinal cross-sectional view along the dashed line CC in Figure 4. The gate dielectric layer, gate layer, and source metal are not shown in Figure 4.

[0054] Referring to Figure 4, in the third embodiment of this application, the JFET gap is non-uniform throughout the semiconductor structure. Based on the different JFET gaps, the JFET region 130 is divided into a first JFET sub-region 130a and a second JFET sub-region 130b.

[0055] In a third embodiment of this application, the JFET gap of the first JFET sub-region 130a is smaller than the JFET gap of the second JFET sub-region 130b, and the plurality of buried injection regions 140 are located in the second JFET sub-region 130b. In Figure 4, to clearly show the second JFET sub-region 130b, one of the second JFET sub-regions 130b omits the buried injection region 140.

[0056] In a third embodiment of this application, each of the plurality of junction implants 120 is hexagonal. The configuration shown in FIG4 is commonly referred to as a “hexagonal cell” design because the junction implants 120 are hexagonal throughout the device.

[0057] In the technical solution of this application, when the JFET gap is not uniform throughout the semiconductor structure, several buried injection regions 140 are set in the region with a larger JFET gap in the JFET region 130. This can achieve the balance of electric field and current without reducing the channel density, and the process is simple and does not affect the continued miniaturization of the JFET region size.

[0058] Figure 5 is a flowchart of a method for forming a semiconductor structure according to some embodiments of this application.

[0059] Embodiments of this application also provide a method for forming a semiconductor structure, as shown in FIG5, including:

[0060] Step S1: Provide a semiconductor substrate, wherein an epitaxial layer is formed on a first surface of the semiconductor substrate, and a plurality of junction implants are formed in the epitaxial layer;

[0061] Step S2: A JFET region is formed between the plurality of junction implants, and the distance between two adjacent junction implants is defined as the JFET gap;

[0062] Step S3: Form a plurality of buried implantation regions in a portion of the JFET region, wherein the top surface of the buried implantation regions is lower than the top surface of the JFET region, and the doping type of the buried implantation regions is opposite to the doping type of the JFET region.

[0063] Referring to Figure 1, in step S1, a semiconductor substrate 100 is provided. An epitaxial layer 110 is formed on the first surface of the semiconductor substrate 100. A plurality of junction implants 120 are formed in the epitaxial layer 110. Each junction implant 120 includes a well region 121 and a source well 122. The source well 122 is located within the well region 121 and can be surrounded by the well region 121.

[0064] In some embodiments of this application, the semiconductor substrate 100 is made of doped silicon carbide, the epitaxial layer 110 is made of doped silicon carbide, the semiconductor substrate 100 and the epitaxial layer 110 have the same doping type, and the doping concentration of the semiconductor substrate 100 is greater than the doping concentration of the epitaxial layer 110.

[0065] In some embodiments of this application, the semiconductor substrate 100 is N-type doped, and the doping concentration of the semiconductor substrate 100 is 1E19 to 1E20 cm⁻¹. -3 The epitaxial layer 110 is N-type doped, and the doping concentration of the epitaxial layer 110 is between 5E13 and 1E17 cm⁻¹. -3 .

[0066] In some embodiments of this application, the method of forming the epitaxial layer 110 on the first surface of the semiconductor substrate 100 includes an epitaxial growth process.

[0067] In some embodiments of this application, the well region 121 is p-type doped, and the doping concentration of the well region 121 is 1E16 to 3E19 cm⁻¹. -3The source well 122 is N-type doped, and the doping concentration of the source well 122 is 1E20 to 1E21 cm⁻¹. -3 .

[0068] In some embodiments of this application, the method for forming the well region 121 and source well 122 of the junction implant 120 includes an ion implantation process.

[0069] Referring again to Figure 1, in step S2, a JFET region 130 is formed between the plurality of junction implants 120. The distance between two adjacent junction implants 120 is defined as the JFET gap. The depth of the JFET region 130 may be greater than the depth of the junction implants 120. The JFET region 130 may extend to the bottom of a portion of the junction implants 120.

[0070] In some embodiments of this application, the JFET region 130 is N-type doped, and the doping concentration of the JFET region 130 is 1E16 to 2E17 cm⁻¹. -3 .

[0071] In some embodiments of this application, the method of forming the JFET region 130 includes an ion implantation process.

[0072] Referring again to Figure 1, in step S3, a plurality of buried implantation regions 140 are formed in a portion of the JFET region 130. The top surface of the buried implantation region 140 is lower than the top surface of the JFET region 130, and the doping type of the buried implantation region 140 is opposite to that of the JFET region 130.

[0073] In some embodiments of this application, the buried implantation region 140 is p-type doped, and the doping concentration of the buried implantation region 140 is 9E15 to 6E17 cm⁻¹. -3 In some embodiments of this application, the doping concentration of the plurality of buried implantation regions 140 is greater than the doping concentration of the JFET region 130.

[0074] In some embodiments of this application, the plurality of buried injection zones 140 further extend into the knot injection 120.

[0075] In some embodiments of this application, the method of forming the plurality of buried implantation regions 140 includes an ion implantation process.

[0076] Referring again to FIG1, a gate dielectric layer 150 is formed, which is located on the surface of the epitaxial layer 110 and extends between the source wells 122 of each of the junction implants 120; a gate layer 170 is formed, which is located on the surface of the gate dielectric layer 150; a source metal 160 is formed, which is located on the surface of the epitaxial layer 110 and is located on a portion of the well region 121 and the source well 122 in each junction implant 120; and a drain metal 180 is formed, which is located on a second surface of the semiconductor substrate 100 opposite to the first surface.

[0077] Referring to FIG2, in a first embodiment of this application, the JFET gap is uniform throughout the semiconductor structure (e.g., each of the plurality of junction implants 120 is strip-shaped), and the plurality of buried implant regions 140 are uniformly located within the JFET region 130. The configuration shown in FIG2 is commonly referred to as a “strip” design because the junction implants 120 are strip-shaped throughout the device.

[0078] In the technical solution of this application, when the JFET gap is uniform throughout the semiconductor structure, a plurality of buried implantation regions 140 are uniformly arranged in the JFET region 130. This can achieve the balance of electric field and current without reducing the channel density, and the process is simple and does not affect the continued miniaturization of the JFET region size.

[0079] Referring to Figure 3, in the second embodiment of this application, the JFET gap is non-uniform throughout the semiconductor structure. Based on the different JFET gaps, the JFET region 130 is divided into a first JFET sub-region 130a and a second JFET sub-region 130b.

[0080] In a second embodiment of this application, the JFET gap of the first JFET sub-region 130a is smaller than the JFET gap of the second JFET sub-region 130b, and the plurality of buried injection regions 140 are located in the second JFET sub-region 130b. In Figure 3, to clearly show the second JFET sub-region 130b, one of the second JFET sub-regions 130b omits the buried injection region 140.

[0081] In a second embodiment of this application, each of the plurality of junction implants 120 is rectangular. The configuration shown in FIG3 is commonly referred to as a “cell” design because the junction implants 120 are square across the entire device.

[0082] Referring to Figure 4, in the third embodiment of this application, the JFET gap is non-uniform throughout the semiconductor structure. Based on the different JFET gaps, the JFET region 130 is divided into a first JFET sub-region 130a and a second JFET sub-region 130b.

[0083] In a third embodiment of this application, the JFET gap of the first JFET sub-region 130a is smaller than the JFET gap of the second JFET sub-region 130b, and the plurality of buried injection regions 140 are located in the second JFET sub-region 130b. In Figure 4, to clearly show the second JFET sub-region 130b, one of the second JFET sub-regions 130b omits the buried injection region 140.

[0084] In a third embodiment of this application, each of the plurality of junction implants 120 is hexagonal. The configuration shown in FIG4 is commonly referred to as a “hexagonal cell” design because the junction implants 120 are hexagonal throughout the device.

[0085] In the technical solution of this application, when the JFET gap is not uniform throughout the semiconductor structure, several buried injection regions 140 are set in the region with a larger JFET gap in the JFET region 130. This can achieve the balance of electric field and current without reducing the channel density, and the process is simple and does not affect the continued miniaturization of the JFET region size.

[0086] This application provides a semiconductor structure and its formation method, in which a buried implantation region is formed in the JFET region as an electric field shielding layer, achieving a balance between electric field and current without reducing channel density, and the process is simple and does not affect the continued miniaturization of the JFET region size.

[0087] In summary, after reading this application, those skilled in the art will understand that the foregoing content is presented by way of example only and is not restrictive. Although not explicitly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.

[0088] It should be understood that the term "and / or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element.

[0089] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it may be directly on that other element, or there may be intermediate elements present. Conversely, the term "directly" means without intermediate elements. It should also be understood that the terms "comprising," "including," "including," or "comprises," as used in this application, indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0090] It should also be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of this application, a first element in some embodiments may be referred to as a second element in other embodiments. The same reference numerals or the same reference signs denote the same elements throughout the specification.

[0091] Furthermore, this application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, differences from the illustrated shapes are foreseeable due to factors such as manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in shape caused, for example, by manufacturing processes. For instance, etched areas shown as rectangular typically have circular or curved features. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to illustrate the actual shape of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

Claims

1. A semiconductor structure, characterized by, include: A semiconductor substrate, wherein an epitaxial layer is formed on a first surface of the semiconductor substrate, and a plurality of junction implants are formed in the epitaxial layer; The JFET region is located between the plurality of junction implants, and the distance between two adjacent junction implants among the plurality of junction implants is defined as the JFET gap. Several buried implantation regions are located in a portion of the JFET region, the top surface of the buried implantation regions is lower than the top surface of the JFET region, and the doping type of the buried implantation regions is opposite to that of the JFET region.

2. The semiconductor structure of claim 1, wherein, The JFET gap is uniform throughout the semiconductor structure, and the plurality of buried implantation regions are uniformly located within the JFET region.

3. The semiconductor structure of claim 2, wherein, Each of the plurality of injected materials is strip-shaped.

4. The semiconductor structure of claim 1, wherein, The JFET gap is non-uniform throughout the semiconductor structure. Based on the different JFET gaps, the JFET region is divided into a first JFET sub-region and a second JFET sub-region.

5. The semiconductor structure of claim 4, wherein, The JFET gap in the first JFET sub-region is smaller than the JFET gap in the second JFET sub-region, and the plurality of buried injection regions are located in the second JFET sub-region.

6. The semiconductor structure of claim 4, wherein, Each of the plurality of injection sites is rectangular or hexagonal.

7. The semiconductor structure of claim 1, wherein, The semiconductor substrate is made of doped silicon carbide, the epitaxial layer is made of doped silicon carbide, the semiconductor substrate and the epitaxial layer have the same doping type, and the doping concentration of the semiconductor substrate is greater than that of the epitaxial layer.

8. The semiconductor structure of claim 1, wherein, The buried injection zones also extend partially into the injected material.

9. The semiconductor structure of claim 1, wherein, The doping concentration of the several buried implant regions is 9E15 to 6E17 cm -3 .

10. A method of forming a semiconductor structure, comprising: include: A semiconductor substrate is provided, wherein an epitaxial layer is formed on a first surface of the semiconductor substrate, and a plurality of junction implants are formed in the epitaxial layer; A JFET region is formed between the plurality of junction implants, and the distance between two adjacent junction implants is defined as the JFET gap. Several buried implantation regions are formed in a portion of the JFET region, the top surface of the buried implantation regions being lower than the top surface of the JFET region, and the doping type of the buried implantation regions being opposite to the doping type of the JFET region.

11. The method of forming a semiconductor structure of claim 10, wherein, The JFET gap is uniform throughout the semiconductor structure, and the plurality of buried implantation regions are uniformly located within the JFET region.

12. The method of forming a semiconductor structure of claim 11, wherein, Each of the plurality of injected materials is strip-shaped.

13. The method of forming a semiconductor structure of claim 10, wherein, The JFET gap is non-uniform throughout the semiconductor structure. Based on the different JFET gaps, the JFET region is divided into a first JFET sub-region and a second JFET sub-region.

14. The method of forming a semiconductor structure of claim 13, wherein, The JFET gap in the first JFET sub-region is smaller than the JFET gap in the second JFET sub-region, and the plurality of buried injection regions are located in the second JFET sub-region.

15. The method of forming a semiconductor structure of claim 13, wherein, Each of the plurality of injection sites is rectangular or hexagonal.

16. The method of forming a semiconductor structure of claim 10, wherein, The semiconductor substrate is made of doped silicon carbide, the epitaxial layer is made of doped silicon carbide, the semiconductor substrate and the epitaxial layer have the same doping type, and the doping concentration of the semiconductor substrate is greater than that of the epitaxial layer.

17. The method of forming a semiconductor structure of claim 10, wherein, The buried injection zones also extend partially into the injected material.

18. The method of forming a semiconductor structure of claim 10, wherein, The doping concentration of the several buried implant regions is 9E15 to 6E17 cm -3 .

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