Photovoltaic cell, module and system

Abstract

Provided in the present disclosure are a photovoltaic cell, module and system. In the photovoltaic cell, a back side of a silicon wafer is provided with first-polarity doped layers and second-polarity doped layers that are alternately arranged at intervals, the second-polarity doped layers and the first-polarity doped layers being separated by spacing regions. The spacing regions are provided with first isolated doped portions that are not in contact with the first-polarity doped layers or the second-polarity doped layers.

Description

Photovoltaic cells, modules and systems

[0001] Cross-references to related applications

[0002] This disclosure claims priority to Chinese patent application No. 202422539827.1, filed on October 18, 2024, with the China National Intellectual Property Administration, entitled “Back Contact Battery, Battery Module and Photovoltaic System”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of solar cell technology, and more particularly to a back-contact cell, a cell module, and a photovoltaic system. Background Technology

[0004] Currently, in solar cells, back-contact cells are cells in which both the emitter and base are located on the back (non-light-receiving surface) of the cell. The light-receiving surface of this cell is not blocked by any metal electrodes, thereby effectively increasing the short-circuit current of the cell.

[0005] In related technologies, back-contact batteries have P-type and N-type doped layers on the back side, which are isolated by isolation regions (such as trenches) to prevent short-circuit leakage. However, in these technologies, charge carriers tend to recombine in the isolation regions, resulting in low carrier collection rates, and the efficiency of back-contact batteries needs further improvement.

[0006] Public content

[0007] This disclosure provides a back-contact battery, a battery module, and a photovoltaic system.

[0008] This disclosure is implemented as follows: the back contact battery of the embodiments of this disclosure includes:

[0009] A silicon wafer has a front side and a back side. The back side includes a first region and a second region arranged alternately along a first direction, and both the first region and the second region extend along a second direction. There is a gap between adjacent first regions and second regions. The second direction intersects the first direction. A first polar doped layer is stacked on the first region. A second polar doped layer is stacked on the second region, and the polarity of the second polar doped layer is opposite to that of the first polar doped layer. A plurality of first isolated doped portions are independently disposed in the gap and spaced apart from the first polar doped layer and the second polar doped layer. The polarity of the first isolated doped portion is the same as that of the first polar doped layer.

[0010] In some embodiments, in the first direction, the spacing between the first isolated doped portion and the first polar doped layer is greater than or equal to 300 nm.

[0011] In some embodiments, in the first direction, the spacing between the first isolated doped portion and the second polar doped layer is greater than or equal to 300 nm.

[0012] In some embodiments, a plurality of first isolated doped portions are randomly distributed on the spacer region; or

[0013] Several first isolated doped portions are arranged at intervals along the second direction on the spacer region.

[0014] In some embodiments, when a plurality of first isolated doped portions are arranged at intervals along a second direction on a spacer region, the spacing between two adjacent first isolated doped portions in the second direction is 30 μm-380 μm.

[0015] In some embodiments, the ratio of the projected area of ​​all first isolated doped portions within a single spacer region in the thickness direction of the silicon wafer to the projected area of ​​the single spacer region in the thickness direction of the silicon wafer is 0.0001-0.5.

[0016] In some embodiments, the ratio of the projected area of ​​all first isolated doped portions within a single spacer region in the thickness direction of the silicon wafer to the projected area of ​​the single spacer region in the thickness direction of the silicon wafer is 0.001-0.1.

[0017] In some embodiments, the thickness of the first isolated doped portion is 20 nm to 450 nm.

[0018] In some embodiments, a plurality of first arc-shaped recessed regions are formed on the sidewalls adjacent to the first polar doped layer and the spacer region. The plurality of first arc-shaped recessed regions are arranged along the second direction, and two adjacent first arc-shaped recessed regions intersect each other. The first isolated doped portion is disposed near the boundary between two adjacent first arc-shaped recessed regions.

[0019] In some embodiments, within the spacer region, the silicon wafer has a first isolated bump, and a first isolated doped portion is disposed on the first isolated bump and covers at least a portion of the first isolated bump.

[0020] In some embodiments, the first isolated dopant completely covers the first isolated protrusion, and the first isolated dopant portion has a first suspended segment extending beyond the first isolated protrusion and suspended within the spacer region.

[0021] In some embodiments, a second isolated doped portion is provided on the surface of the first suspended segment facing the silicon wafer. The second isolated doped portion has the opposite polarity to the first polar doped layer and the same polarity as the second polar doped layer.

[0022] In some embodiments, the second isolated doped portion is insulated from the first suspended segment.

[0023] In some embodiments, the second isolated doped portion further extends along the side of the first isolated protrusion to the area of ​​the silicon wafer that is blocked by the first suspended segment.

[0024] In some embodiments, the side surface of the first isolated protrusion has a third isolated doped portion, which is spaced apart from the first isolated doped portion.

[0025] In some embodiments, a fourth isolated doped portion is provided in the area of ​​the silicon wafer that is blocked by the first suspended segment. The polarity of the fourth isolated doped portion is the same as that of the second polar doped layer, and the fourth isolated doped portion is spaced apart from the first polar doped layer and the second polar doped layer.

[0026] In some embodiments, the fourth isolated doped portion is spaced apart from the first isolated bump and the first isolated doped portion.

[0027] In some embodiments, in the first direction, the spacing between the fourth isolated doped portion and the first isolated protrusion is 0.1 μm-200 μm.

[0028] In some embodiments, the back contact battery further includes a plurality of fifth isolated doped portions, all of which are disposed within a spacer region, and the fifth isolated doped portions are spaced apart from the first polar doped layer and the second polar doped layer, and the polarity of the fifth isolated doped portions and the second polar doped layer is the same.

[0029] In some embodiments, the fifth isolated doped portion is spaced apart from the first isolated doped portion within the spacer region.

[0030] In some embodiments, the spacing between any fifth isolated doped portion and any first isolated doped portion is greater than or equal to 0.1 μm-200 μm.

[0031] In some embodiments, in the first direction, the spacing between the fifth isolated doped portion and the second polar doped layer is greater than or equal to 300 nm.

[0032] In some embodiments, in the first direction, the spacing between the fifth isolated doped portion and the first polar doped layer is greater than or equal to 300 nm.

[0033] In some embodiments, a plurality of fifth isolated doped portions are randomly distributed on the spacer region; or

[0034] Several fifth isolated doped portions are arranged at intervals along the second direction on the spacer region.

[0035] In some embodiments, when a plurality of fifth isolated doped portions are arranged at intervals along the second direction on the spacer region, the spacing between two adjacent fifth isolated doped portions is 30 μm-380 μm.

[0036] In some embodiments, the ratio of the projected area of ​​all fifth isolated doped portions within a single spacer region in the thickness direction of the silicon wafer to the projected area of ​​the single spacer region in the thickness direction of the silicon wafer is 0.0001-0.5.

[0037] In some embodiments, the ratio of the projected area of ​​all fifth isolated doped portions within a single spacer region in the thickness direction of the silicon wafer to the projected area of ​​the single spacer region in the thickness direction of the silicon wafer is 0.001-0.1.

[0038] In some embodiments, the thickness of the fifth isolated doped portion is 20 nm to 450 nm.

[0039] In some embodiments, a plurality of second arc-shaped recessed regions are formed on the sidewalls adjacent to the spacer region of the second polar doped layer. The plurality of second arc-shaped recessed regions are arranged along the second direction, and two adjacent second arc-shaped recessed regions intersect each other. The fifth isolated doped portion is disposed near the junction of two adjacent second arc-shaped recessed regions.

[0040] In some embodiments, a trench is formed in the spacer region, the trench having a second isolated protrusion, and a fifth isolated doped portion is disposed on the second isolated protrusion and covers at least a portion of the second isolated protrusion.

[0041] In some embodiments, the fifth isolated doped portion covers only a portion of the second isolated protrusion; or the fifth isolated doped portion completely covers the second isolated protrusion, and the fifth isolated doped portion has a second suspended segment extending beyond the second isolated protrusion and suspended within the spacer region.

[0042] In some embodiments, at at least a portion of the first polar doped layer, the first polar doped layer has a third suspended segment extending above the spacer region, the third suspended segment being suspended over a portion of the spacer region, and a first isolated doped portion being disposed in a region of the spacer region not obscured by the third suspended segment.

[0043] In some embodiments, a sixth isolated doped portion is provided on the surface of the third suspended segment facing the silicon wafer, and the polarity of the sixth isolated doped portion is the same as that of the second polar doped layer.

[0044] In some embodiments, a seventh isolated doped portion is provided in the region of the silicon wafer that is blocked by the third suspended segment. The seventh isolated doped portion is spaced apart from the first polar doped layer and the second polar doped layer, and the polarity of the seventh isolated doped portion is the same as that of the second polar doped layer.

[0045] In some embodiments, the seventh isolated doped portion is spaced apart from the first isolated doped portion.

[0046] In some embodiments, the silicon wafer has a silicon wafer extension that extends over and is suspended within the spacer region, and at least a portion of the third suspended segment is stacked on the silicon wafer extension.

[0047] In some embodiments, the silicon wafer extension has an eighth isolated doped portion on the surface away from the third suspended segment, and the polarity of the eighth isolated doped portion is the same as that of the second polar doped layer.

[0048] In some embodiments, the eighth isolated doped portion is spaced apart from the first isolated doped portion.

[0049] This disclosure also provides a battery assembly including a plurality of back contact batteries according to any of the above.

[0050] This disclosure also provides a photovoltaic system, which includes the aforementioned battery module.

[0051] In the back-contact battery, battery module, and photovoltaic system of this disclosure, the back side of the silicon wafer has alternating first and second regions, separated by a spacer. A first polar doped layer is stacked in the first region, and a second polar doped layer is stacked in the second region, separated from the first polar doped layer by the spacer. Within the spacer, a plurality of first isolated doped portions, independent of both the first and second polar doped layers, are provided. These first isolated doped portions do not contact the first or second polar doped layers. Thus, the spacer ensures electrical isolation between the first and second polar doped layers, preventing short circuits. Simultaneously, by providing a plurality of independent first isolated doped portions within the spacer, floating junction passivation can be formed within the spacer, improving the passivation effect and thus increasing the efficiency of the back-contact battery. Furthermore, providing independent first isolated doped portions within the spacer can improve carrier collection efficiency.

[0052] Additional aspects and advantages of this disclosure will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this disclosure. Attached Figure Description

[0053] Figure 1 is a schematic diagram of the modules of the photovoltaic system provided in an embodiment of this disclosure;

[0054] Figure 2 is a schematic diagram of the battery assembly provided in an embodiment of this disclosure;

[0055] Figure 3 is a schematic diagram of the planar structure of the back contact battery provided in an embodiment of this disclosure;

[0056] Figure 4 is a cross-sectional structural diagram of the back contact battery provided in an embodiment of this disclosure;

[0057] Figure 5 is a schematic diagram of another planar structure of the back contact battery provided in an embodiment of this disclosure;

[0058] Figure 6 is another cross-sectional structural schematic diagram of the back contact battery provided in an embodiment of this disclosure;

[0059] Figure 7 is another cross-sectional structural schematic diagram of the back contact battery provided in the embodiment of this disclosure;

[0060] Figure 8 is another cross-sectional structural schematic diagram of the back contact battery provided in the embodiment of this disclosure;

[0061] Figure 9 is another planar structural schematic diagram of the back contact battery provided in an embodiment of this disclosure;

[0062] Figure 10 is another cross-sectional structural schematic diagram of the back contact battery provided in the embodiment of this disclosure;

[0063] Figure 11 is another planar structural schematic diagram of the back contact battery provided in the embodiment of this disclosure;

[0064] Figure 12 is another cross-sectional structural schematic diagram of the back contact battery provided in the embodiment of this disclosure;

[0065] Figure 13 is another cross-sectional structural schematic diagram of the back contact battery provided in the embodiment of this disclosure;

[0066] Figure 14 is another cross-sectional structural schematic diagram of the back contact battery provided in the embodiment of this disclosure;

[0067] Figure 15 is another cross-sectional structural schematic diagram of the back contact battery provided in the embodiment of this disclosure;

[0068] Figure 16 is another cross-sectional structural schematic diagram of the back contact battery provided in the embodiment of this disclosure;

[0069] Figure 17 is another cross-sectional structural schematic diagram of the back contact battery provided in the embodiment of this disclosure.

[0070] Key component symbols: Photovoltaic system 1000, battery module 200, back contact cell 100, silicon wafer 10, front side 11, back side 12, first region 121, second region 122, spacer region 123, first isolated protrusion 1231, trench 1232, second isolated protrusion 1233, first polar doped layer 20, first arc-shaped recessed region 21, second polar doped layer 30, first isolated doped part 40, first suspended section 41, back passivation film layer 50, first electrode 60, second electrode 70, second isolated doped part 80, third isolated doped part 90, fourth isolated doped part 110, fifth isolated doped part 120, second suspended section 1201, third suspended section 22. Detailed Implementation

[0071] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements throughout, or the same or similar reference numerals denote elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this disclosure, and should not be construed as limiting this disclosure. Furthermore, it should be understood that the specific embodiments described herein are merely for explaining this disclosure and are not intended to limit this disclosure.

[0072] In the description of this disclosure, it should be understood that the terms “length”, “width”, “upper”, “lower”, “lateral”, “longitudinal”, etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0073] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this disclosure, "a plurality of" means two or more, unless otherwise explicitly specified.

[0074] In the description of this disclosure, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0075] In this disclosure, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0076] The following disclosure provides numerous different embodiments or examples for implementing various structures of this disclosure. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the scope of this disclosure. Furthermore, at least one of the reference numerals and letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and arrangements discussed. In addition, various specific examples of processes and materials are provided in this disclosure, but those skilled in the art will recognize at least one other application of processes and use cases for other materials.

[0077] Please refer to Figures 1-2. The photovoltaic system 1000 in this embodiment may include the battery module 200 in this embodiment, and the battery module 200 in this embodiment may include a plurality of back contact batteries 100 in this embodiment.

[0078] In this battery assembly 200, multiple back-contact cells 100 can be connected in series to form multiple battery strings. These battery strings can be connected in series to achieve current collection and output, or connected in parallel to achieve current collection and output, or combined in series and parallel to achieve current collection and output. For example, the connection between individual cells in the battery string can be achieved by welding solder strips, or by using busbars. In some embodiments, the battery strings can form a cell array, and then be encapsulated together by a front panel, a front adhesive film, a rear adhesive film, and a back panel to form the battery assembly 200.

[0079] Please refer to Figures 3 and 4. The back contact battery 100 in this embodiment may include a silicon wafer 10, a plurality of first polar doped layers 20, a plurality of second polar doped layers 30, and a plurality of first isolated doped portions 40.

[0080] The silicon wafer 10 has a front side 11 (i.e., a light-receiving surface) and a back side 12 (i.e., a back-lighting surface). The back side 12 of the silicon wafer 10 includes a first region 121 and a second region 122 arranged alternately along a first direction. Both the first region 121 and the second region 122 extend along a second direction. There is a spacer region 123 between adjacent first regions 121 and second regions 122. The second direction intersects the first direction. That is, the first region 121 and the second region 122 are separated by the spacer region 123, which also extends along the second direction.

[0081] Specifically, as shown in Figure 3, the first region 121 and the second region 122 can be alternately arranged along the lateral direction of the silicon wafer 10 and both extend along the longitudinal direction. That is, the first direction can be the lateral direction of the back contact battery 100, and the second direction can be the longitudinal direction of the back contact battery 100, and the two are perpendicular to each other. Of course, in other embodiments, the first direction and the second direction can also be other directions, for example, they can be the diagonal directions of the silicon wafer 10, and there is no specific limitation here.

[0082] In the embodiments of this disclosure, a first polar doped layer 20 is stacked on a first region 121, and a second polar doped layer 30 is stacked on a second region 122. The polarities of the first polar doped layer 20 and the second polar doped layer 30 are opposite, that is, their doping types are opposite. A first polar doped layer 20 is stacked on each first region 121, and a second polar doped layer 30 is stacked on each second region 122. The first polar doped layer 20 and the second polar doped layer 30 are separated by a spacer region 123.

[0083] As shown in Figures 3 and 4, several first isolated doped portions 40 are independently disposed within the spacer region 123 (that is, several first isolated doped portions 40 are disposed at intervals between each other within the spacer region 123), and the first isolated doped portions 40 are spaced apart from the first polar doped layer 20 and the second polar doped layer 30. In other words, several first isolated doped portions 40 can be spaced apart within the spacer region 123, and the first isolated doped portions 40 are not in contact with the first polar doped layer 20 and the second polar doped layer 30; each first isolated doped portion 40 is an isolated doping site.

[0084] It should be noted that, in this document, the term "a film layer stacked on a certain region or a certain film layer" can refer to the film layer being directly stacked on the surface region or film layer, or it can refer to the film layer being stacked with other film layers between it and the surface region or film layer. The term "stacked" merely defines the arrangement of the film layers. For example, in some embodiments, in the back contact battery 100, a tunneling layer (not shown) can be provided between the first polar doped layer 20 and the silicon wafer 10, and a tunneling layer can also be provided between the second polar doped layer 30 and the silicon wafer 10. The tunneling layer includes, but is not limited to, a tunneling oxide layer (e.g., a silicon dioxide tunneling layer), an intrinsic amorphous silicon layer, etc. Furthermore, in some embodiments, a tunneling layer (e.g., a silicon dioxide tunneling layer) can also be provided between the first isolated doped portion 40 and the surface of the spacer region 123.

[0085] Furthermore, in this document, the separation of two structures or films means that they are independent of each other and do not come into contact. For example, the separation of the first isolated doped portion 40 from the first polar doped layer 20 and the second polar doped layer 30 means that the first isolated doped portion 40 does not come into contact with either the first polar doped layer 20 or the second polar doped layer 30. Similar descriptions may be found here.

[0086] In the back-contact battery 100, battery module 200, and photovoltaic system 1000 of this embodiment, the back surface 12 of the silicon wafer 10 has alternating first regions 121 and second regions 122, separated by a spacer region 123. A first polar doped layer 20 is stacked in the first region 121, and a second polar doped layer 30 is stacked in the second region 122, separated from the first polar doped layer 20 by the spacer region 123. Within the spacer region 123, a plurality of first isolated doped portions 40 are provided, independent of both the first polar doped layer 20 and the second polar doped layer 30. None of the first isolated doped portions 40 contact the first polar doped layer 20 or the second polar doped layer 30. Thus, the spacer region 123 ensures electrical isolation between the first polar doped layer 20 and the second polar doped layer 30, preventing short circuits. Furthermore, by providing a plurality of independent first isolated doped portions 40 within the spacer region 123, the first isolated doped portions 40 can form floating junction passivation within the spacer region 123, thereby improving the passivation effect of the spacer region 123, reducing the probability of surface recombination at the spacer region 123, increasing the carrier collection rate (i.e., the probability that photogenerated carriers are collected and participate in current flow), and improving the efficiency of the back contact battery 100. In other words, in the embodiments of this disclosure, by providing the first isolated doped portions 40, a better passivation effect can be achieved while ensuring the isolation effect of the first polar doped layer 20 and the second polar doped layer 30, reducing the probability of surface recombination at the spacer region 123, and improving the efficiency of the back contact battery 100.

[0087] Specifically, in the embodiments of this disclosure, the silicon wafer 10 can be an N-type silicon wafer or a P-type silicon wafer, and there is no specific limitation here. The first polar doped layer 20 and the second polar doped layer 30 have opposite polarities, one of which is a P-type doped layer and the other is an N-type doped layer. When the first polar doped layer 20 is a P-type doped layer and collects holes, the second polar doped layer 30 is an N-type doped layer and collects electrons. When the first polar doped layer 20 is an N-type doped layer and collects electrons, the second polar doped layer 30 is a P-type doped layer and collects holes, and there is no specific limitation here, as long as their polarities are opposite.

[0088] In some embodiments, the first polar doped layer 20 may be a P-type doped layer, the second polar doped layer 30 may be an N-type doped layer, and the first isolated doped portion 40 may be a P-type doped portion. In this case, when the back contact battery 100 is working, the first polar doped layer 20 collects holes, and the second polar doped layer 30 collects electrons. Holes and electrons are prone to surface recombination at the spacer region 123. By providing the P-type first isolated doped portion 40 at the spacer region 123, a floating junction passivation is formed at the first isolated doped portion 40, improving the passivation effect. At the same time, holes will be saturated and filled in the first isolated doped portion 40, and then this region will repel holes, thereby reducing the probability of surface recombination of holes at the spacer region 123. This allows holes to be collected quickly and efficiently by the first polar doped layer 20, improving the hole carrier collection rate and thus improving the conversion efficiency of the back contact battery 100.

[0089] In some embodiments, the first polar doped layer 20 may be an N-type doped layer, the second polar doped layer 30 may be a P-type doped layer, and the first isolated doped portion 40 may be an N-type doped portion. In this case, when the back contact battery 100 is working, the first polar doped layer 20 collects electrons, and the second polar doped layer 30 collects holes. Holes and electrons are prone to surface recombination at the spacer region 123. By providing the N-type first isolated doped portion 40 at the spacer region 123, a floating junction passivation is formed at the first isolated doped portion 40, improving the passivation effect. At the same time, electrons will be saturated and filled in the first isolated doped portion 40, and then this region will repel electrons, reducing the probability of electron recombination at the spacer region 123. That is, it effectively avoids large surface recombination of electrons and holes at the spacer region 123, so that electrons can be collected by the first polar doped layer 20 quickly and efficiently, improving the collection rate of electron carriers, and thus improving the conversion efficiency of the back contact battery 100.

[0090] It is understood that surface recombination is a continuous loss. Without the first isolated doped portion 40 in the spacer region 123, continuous surface recombination will occur in the spacer region 123. In this disclosure, by providing the first isolated doped portion 40, the charge carriers (holes or electrons) at the first isolated doped portion 40 will quickly reach the filling saturation. After saturation, the charge carriers at this position are repelled, and the probability of recombination on the surface is reduced, thereby improving the collection rate of charge carriers and thus improving efficiency.

[0091] Furthermore, as shown in Figure 4, in the back contact battery 100 of this disclosure, a back passivation film layer 50 is also provided on the back side 12. The back passivation film layer 50 covers the first polar doped layer 20, the second polar doped layer 30 and the spacer region 123. That is, the back passivation film layer 50 can cover the entire back side 12.

[0092] A first electrode 60 and a second electrode 70 are provided on the back passivation film layer 50. The first electrode 60 is disposed on the back passivation film layer 50 and located in the first region 121. The first electrode 60 is electrically connected to the first polar doped layer 20. For example, in some embodiments, the first electrode 60 can penetrate the back passivation film layer 50 to make conductive contact with the first polar doped layer 20.

[0093] The second electrode 70 is disposed on the back passivation film layer 50 and located in the second region 122. The second electrode 70 is electrically connected to the second polar doped layer 30. For example, in some embodiments, the second electrode 70 may also penetrate the back passivation film layer 50 to make conductive contact with the second polar doped layer 30. The first isolated doped portion 40 does not have electrodes; that is, the first electrode 60 and the second electrode 70 are physically separated from and do not contact the first isolated doped portion 40 to prevent charge carriers from failing to reach saturation at the first isolated doped portion 40.

[0094] In the embodiments of this disclosure, the specific shape of the first isolated doped portion 40 can be a regular shape or an irregular shape. For example, in some embodiments, the shape of the first isolated doped portion 40 can be one or more of the following: square, conical, pyramidal, frustum, and truncated cone. No specific limitation is made here.

[0095] Referring to Figure 4, in some embodiments, in the first direction, the spacing L1 between the first isolated doped portion 40 and the first polar doped layer 20 is greater than or equal to 300 nm.

[0096] In this way, the poor isolation effect between the first isolated doped portion 40 and the first polar doped layer 20 can be avoided due to the small spacing between them. That is, this setting can improve the isolation effect between the first isolated doped portion 40 and the first polar doped layer 20, thereby achieving a better carrier collection rate and improving the passivation effect of the spacer region 123.

[0097] Specifically, it is not difficult to understand that when the distance L1 between the two is too small (i.e. less than 300nm), the electrical isolation effect between the first isolated doped part 40 and the first polar doped layer 20 is poor. This is equivalent to the first isolated doped part 40 being connected to the first polar doped layer 20, which easily leads to the carriers at the first isolated doped part 40 being directly collected by the first polar doped layer 20, and the corresponding carriers cannot be saturated at the first isolated doped part 40. Thus, the function of repelling holes or electrons at the first isolated doped part 40 cannot be realized, resulting in a significant decrease in the effect of reducing surface recombination.

[0098] In other words, in this disclosure, by setting the spacing L1 between the first isolated doped portion 40 and the first polar doped layer 20 to be greater than or equal to 300 nm, the surface recombination of the spacer region 123 can be significantly reduced, thereby achieving a better carrier collection rate.

[0099] Specifically, in such an embodiment, the spacing L1 between the first isolated doped portion 40 and the first polar doped layer 20 can be any value between 300nm, 400nm, 500nm, 600nm, 700nm, 800nm, 900nm, 1μm, 2μm, 3μm, 4μm, 5μm, 6μm, 7μm, 8μm, 9μm, 10μm, 11μm, 12μm, 13μm, 14μm, 15μm, 16μm, 17μm, 18μm, 19μm, and 20μm.

[0100] As shown in Figure 4, in the embodiments of this disclosure, the width L2 of the spacer region 123 in the first direction can be 50 μm-300 μm. The maximum preferred spacing between the first isolated doped portion 40 and the first polar doped layer 20 is the width L2 of the spacer region 123 in the first direction minus 6 μm, that is, 300 nm ≤ L1 ≤ L2 - 6 μm. Through research, it has been found that L1 is preferably greater than or equal to 3 μm and less than or equal to L2 - 6 μm. Under such conditions, the performance of the back contact battery 100 can be optimized.

[0101] Please continue to refer to Figure 4. In some embodiments, in the first direction, the spacing L3 between the first isolated doped portion 40 and the second polar doped layer 30 may be greater than or equal to 300 nm.

[0102] Thus, by setting the spacing L3 between the first isolated doped portion 40 and the second polar doped layer 30 to be greater than 300 nm, the isolation effect of the first isolated doped portion 40 and the second polar doped layer 30 can be guaranteed, avoiding the direct recombination of some charge carriers at the first isolated doped portion 40 with the charge carriers at the second polar doped layer 30, which would prevent the charge carriers of the first isolated doped portion 40 from reaching saturation, thereby significantly reducing the surface recombination effect.

[0103] Specifically, it is not difficult to understand that when the spacing between the two is too small (i.e., less than 300 nm), it is equivalent to the first isolated doped part 40 being connected to the second polar doped layer 30. This can easily cause the charge carriers (e.g., holes) at the first isolated doped part 40 to recombine directly with the charge carriers (e.g., electrons) at the second polar doped layer 30, and the corresponding charge carriers (e.g., holes) cannot be saturated and filled at the first isolated doped part 40. Thus, the function of repelling holes or electrons at the first isolated doped part 40 cannot be achieved, resulting in a significant reduction in the effect of reducing surface recombination.

[0104] In other words, in this disclosure, by setting the spacing L3 between the first isolated doped portion 40 and the second polar doped layer 30 to be greater than or equal to 300m, the surface recombination of the spacer region 123 can be significantly reduced, thereby achieving a better carrier collection rate.

[0105] Specifically, in such an embodiment, the spacing L3 between the first isolated doped portion 40 and the second polar doped layer 30 can be any value between 300nm, 400nm, 500nm, 600nm, 700nm, 800nm, 900nm, 1μm, 2μm, 3μm, 4μm, 5μm, 6μm, 7μm, 8μm, 9μm, 10μm, 11μm, 12μm, 13μm, 14μm, 15μm, 16μm, 17μm, 18μm, 19μm, and 20μm. Preferably, the maximum spacing between the first isolated doped portion 40 and the second polar doped layer 30 is the width of the spacing region 123 in the first direction minus 6μm, i.e., 300nm ≤ L3 ≤ L2 - 6μm. Research has shown that the optimal L3 size is greater than or equal to 3μm and less than or equal to L2-6μm. Under these conditions, the performance of the back contact battery 100 can be optimized.

[0106] In the embodiments of this disclosure, it is preferable that the distance between the first isolated doped portion 40 and the first polar doped layer 20 is greater than or equal to 3 μm and less than the width of the spacer region 123 minus 6 μm, and the distance between the first isolated doped portion 40 and the second polar doped layer 30 is also greater than or equal to 3 μm and less than the width of the spacer region 123 minus 6 μm. In this way, the surface recombination of the spacer region 123 can be significantly reduced, so that the carrier collection rate reaches the optimal state.

[0107] In some embodiments, a plurality of first isolated doped portions 40 may be randomly distributed on the spacer region 123, or a plurality of first isolated doped portions 40 may be arranged at intervals along the second direction on the spacer region 123, and there is no specific limitation here.

[0108] When a number of first isolated doped portions 40 are randomly distributed on the spacer region 123, the spacing between any two first isolated doped portions 40 (i.e. the length of the line connecting any two first isolated doped portions 40) is 30μm-380μm.

[0109] Referring to Figure 3, in some embodiments, a plurality of first isolated doped portions 40 are arranged at intervals along the second direction on the spacer region 123, and the spacing L4 between two adjacent first isolated doped portions 40 can be 30μm-380μm.

[0110] In this way, the spacing between the first isolated doped portions 40 can be avoided from being too small, which would cause the first isolated doped portions 40 to be too dense.

[0111] Specifically, when a plurality of first isolated doped portions 40 are randomly distributed on the spacer region 123, the spacing between any two first isolated doped portions 40 can be, for example, any value between 30μm, 35μm, 40μm, 45μm, 50μm, 55μm, 60μm, 65μm, 70μm, 75μm, 80μm, 85μm, 90μm, 95μm, 100μm, 120μm, 140μm, 160μm, 180μm, 200μm, 220μm, 240μm, 260μm, 280μm, 300μm, 320μm, 340μm, 360μm, 380μm or 30μm-380μm.

[0112] When a plurality of first isolated doped portions 40 may also be arranged at intervals along the second direction on the spacer region 123, the size of the spacing L4 between two adjacent first isolated doped portions 40 may be, for example, any value between 30μm, 35μm, 40μm, 45μm, 50μm, 55μm, 60μm, 65μm, 70μm, 75μm, 80μm, 85μm, 90μm, 95μm, 100μm, 120μm, 140μm, 160μm, 180μm, 200μm, 220μm, 240μm, 260μm, 280μm, 300μm, 320μm, 340μm, 360μm, 380μm or 30μm-380μm.

[0113] Please refer to Figure 4. In some embodiments, the thickness H1 of the first isolated doped portion 40 may be 20 nm to 450 nm.

[0114] Thus, by setting the thickness of the first isolated doped portion 40 within this range, it is possible to avoid the first isolated doped portion 40 being too thin and thus failing to achieve an efficient floating junction passivation effect, and it is also possible to avoid the first isolated doped portion 40 being too thick and thus increasing costs.

[0115] Specifically, the thickness H1 of the first isolated doped portion 40 can be, for example, any value between 20nm, 22nm, 24nm, 26nm, 28nm, 30nm, 32nm, 34nm, 36nm, 38nm, 40nm, 42nm, 44nm, 46nm, 48nm, 50nm, 100nm, 150nm, 200nm, 250nm, 300nm, 350nm, 400nm, 450nm, or 20nm-450nm.

[0116] In some embodiments, the ratio of the projected area of ​​all first isolated doped portions 40 within a single spacer region 123 in the thickness direction of the silicon wafer 10 to the projected area of ​​the single spacer region 123 in the thickness direction of the silicon wafer 10 is 0.0001-0.5.

[0117] In this way, it can avoid the situation where the area of ​​the first isolated doped part 40 is too small, resulting in the floating junction passivation region being too small and failing to achieve the expected effect. It can also avoid the situation where the area of ​​the first isolated doped part 40 is too large, resulting in excessive saturation of charge carriers in the first isolated doped part 40, which would reduce the number of charge carriers collected by the first polar doped layer 20. At the same time, it can also avoid the situation where the area of ​​the first isolated doped part 40 is too large, resulting in excessive parasitic absorption of light on the back side, which would lead to a significant reduction in the bifaciality.

[0118] In other words, in such an embodiment, setting the area ratio of the two within this reasonable range can improve the carrier collection rate while ensuring the number of carriers collected. Through such an optimized design, the relationship between the carrier collection rate and the number of carriers collected can be balanced, thereby optimizing the conversion efficiency of the back contact battery 100.

[0119] In such an embodiment, the ratio of the areas of the two is preferably 0.001-0.1. Thus, through this optimized design, the relationship between bifaciality and efficiency can be balanced, improving the conversion efficiency of the back contact battery 100 while also achieving a better bifaciality.

[0120] Referring to Figure 5, in some embodiments, a plurality of first arc-shaped recessed regions 21 are formed on the sidewalls adjacent to the first polar doped layer 20 and the spacer region 123. The plurality of first arc-shaped recessed regions 21 are arranged along the second direction, and two adjacent first arc-shaped recessed regions 21 intersect each other. The first isolated doped portion 40 is disposed near the junction of two adjacent first arc-shaped recessed regions 21.

[0121] Thus, the arrangement of the first arc-shaped recessed region 21 helps to reduce the carrier recombination rate of the first polar doped layer 20 near the spacer region 123, thereby improving the carrier collection efficiency. Furthermore, the fabrication process of the first arc-shaped recessed region 21 is simple, causing minimal damage to the first polar doped layer 20, which facilitates the subsequent deposition of the back passivation film layer 50, thereby improving the passivation performance of the back contact cell 100. In addition, placing the first isolated doped portion 40 near the junction of the two first arc-shaped recessed regions 21 can further enhance the field passivation effect.

[0122] Specifically, in this embodiment, the shape of the first arc-shaped recessed area 21 can be a regular arc shape such as a circular arc, or it can be an irregular arc shape with different curvatures at different positions; no specific limitation is made here. The intersection of two adjacent first arc-shaped recessed areas 21 refers to the fact that the sidewalls adjacent to the first polar doped layer 20 and the spacer region 123 are composed of multiple first arc-shaped recessed areas 21. That is, the outline of the sidewalls adjacent to the first polar doped layer 20 and the spacer region 123 is basically a wavy curve.

[0123] In such an embodiment, the distance between the first isolated doped portion 40 and the intersection of two adjacent first arc-shaped recessed regions 21 is greater than or equal to 300 nm.

[0124] Referring to Figure 4, in some embodiments, within the spacer region 123, the silicon wafer 10 has a first isolated bump 1231, and a first isolated doped portion 40 is disposed on the first isolated bump 1231 and covers at least a portion of the first isolated bump 1231. Thus, the provision of the first isolated bump 1231 can enhance the passivation effect of the subsequent back-side passivation film layer 50.

[0125] Specifically, in such an embodiment, in the embodiments of this disclosure, the spacer region 123 and the second region 122 are more recessed into the silicon wafer 10 than the first region 121, and the surface of the first isolated protrusion 1231 is flush with the surface of the first polar doped layer 20 stacked thereon.

[0126] In one possible embodiment, during fabrication, a first polar doped layer 20 can be deposited on the entire back surface 12 of the silicon wafer 10. Then, the first polar doped layer 20 in a portion of the area can be removed by etching (laser etching, wet etching, etc.), thereby forming several first polar doped layers 20 arranged along a first direction, while retaining some independent first isolated doped portions 40. It can be understood that during the removal process, grooves will be formed on the silicon wafer 10, and a first isolated protrusion 1, which protrudes relative to the groove, will be formed below the first isolated doped portion 40. 231. Subsequently, a second polar doped layer 30 can be prepared within the groove, with the second polar doped layer 30 spaced apart from the first polar doped layer 20. Thus, the region corresponding to the first polar doped layer 20 is the first region 121, the region corresponding to the second polar doped layer 30 is the second region 122, and the region between the regions containing the first polar doped layer 20 and the second polar doped layer 30 is the spacer region 123. The silicon wafer 10 has a first isolated protrusion 1231 in the spacer region 123, and the first isolated doped portion 40 is disposed on the first isolated protrusion 1231. Of course, it is understood that in other embodiments, other methods can also be used to prepare the back contact battery 100; no specific method is limited here, as long as it can form the structure corresponding to this disclosure.

[0127] Referring to Figure 6, in some embodiments, the first isolated doped portion 40 completely covers the first isolated protrusion 1231, and the first isolated doped portion 40 has a first suspended segment 41 extending beyond the first isolated protrusion 1231 and suspended within the spacer region 123.

[0128] Thus, the first isolated doped portion 40 has an extended, suspended first suspended segment 41 on the spacer region 123. There are opposing deposition regions between the first suspended segment 41 and the silicon wafer 10. During the subsequent deposition of the back passivation film 50, this deposition region configuration can suppress the full exchange of plasma components between this region and those outside the region, thereby achieving a localized distribution of the mobile hydrogen content in the back passivation film 50 on the back side 12. This results in a lower mobile hydrogen content in the back passivation film 50 within the deposition region and a higher mobile hydrogen content in other regions, achieving optimal passivation and anti-attenuation effects. Simultaneously, it can reduce the direct bombardment of the silicon wafer by the plasma, reducing bombardment damage.

[0129] Specifically, in such an embodiment, the first suspended segment 41 can extend in any direction and be suspended on the interval 123, and there is no restriction on the extension direction of the first suspended segment 41.

[0130] The extension length of the first suspended segment 41 relative to the first isolated protrusion 1231 can be 0.2μm-50μm, for example, any value between 0.2μm, 0.4μm, 0.6μm, 0.8μm, 1μm, 2μm, 3μm, 4μm, 5μm, 6μm, 7μm, 8μm, 9μm, 10μm, 20μm, 30μm, 40μm, 50μm or 0.2μm-50μm.

[0131] Referring to Figure 6, in some embodiments, a second isolated doped portion 80 is provided on the surface of the first suspended segment 41 facing the silicon wafer 10. The second isolated doped portion 80 has the opposite polarity to the first polar doped layer 20 and the same polarity as the second polar doped layer 30. The second isolated doped portion 80 is spaced apart from the first polar doped layer 20 and the second polar doped layer 30 and is not in contact.

[0132] Thus, by providing second isolated doped portions 80 of different polarities on the surface of the first suspended segment 41 facing the silicon wafer 10, the passivation effect on the first suspended segment 41 can be improved, thereby improving the passivation effect of the entire spacer region 123.

[0133] Specifically, in such an embodiment, the second isolated doped portion 80 located on the first suspended segment 41 can be a single, continuous doped portion, or it can be a plurality of mutually independent second isolated doped portions 80 on the first suspended segment 41. In such an embodiment, the second isolated doped portion 80 can be in direct contact with the first suspended segment 41 or can be insulated from the first suspended segment 41.

[0134] Furthermore, referring to FIG6, in some embodiments, the second isolated doped portion 80 also extends along the side of the first isolated protrusion 1231 to the area of ​​the silicon wafer 10 that is blocked by the first suspended segment 41.

[0135] Thus, the setting of the second isolated doped portion 80 can also improve the passivation effect on the side of the first isolated protrusion 1231 and the area blocked by the first suspended segment 41, further improving the passivation effect at the interval region 123.

[0136] Referring to Figure 7, in some embodiments, the side of the first isolated protrusion 1231 may have a third isolated doped portion 90, which is spaced apart from the first isolated doped portion 40 (i.e., the third isolated doped portion 90 does not contact the first isolated doped portion 40), thereby achieving the purpose of improving the passivation effect of the first isolated protrusion 1231.

[0137] Referring to Figure 8, in some embodiments, a fourth isolated doped portion 110 is provided on the area of ​​the silicon wafer 10 that is blocked by the first suspended segment 41. The polarity of the fourth isolated doped portion 110 is the same as that of the second polar doped layer 30. The fourth isolated doped portion 110 is spaced apart from the first polar doped layer 20 and the second polar doped layer 30, that is, the fourth isolated doped portion 110 is not in contact with either the first polar doped layer 20 or the second polar doped layer 30.

[0138] Thus, the fourth isolated doped portion 110 is in contact with the silicon wafer 10 but not with the first polar doped layer 20 or the second polar doped layer 30. In this way, by setting the first isolated doped portion 40 and the fourth isolated doped portion 110 of different polarities, both the first isolated doped portion 40 and the fourth isolated doped portion 110 can form field passivation in the spacer region 123, thereby improving the passivation effect. Furthermore, by setting the first isolated doped portion 40 and the fourth isolated doped portion 110, the collection rate of holes and electrons can be improved.

[0139] Specifically, when the doping type of the first isolated doped portion 40 is P-type doping and the doping type of the fourth isolated doped portion 110 is N-type doping, the first isolated doped portion 40 is saturated with hole carriers, which will generate a repulsive force on subsequent hole carriers, thereby enabling hole carriers to be collected more quickly by the first polar doped layer 20. At the fourth isolated doped portion 110, the electron carriers are saturated with electron carriers, which will generate a repulsive force on subsequent electrons, thereby enabling electrons to be collected more quickly by the second polar doped layer 30. This reduces the probability of recombination between holes and electrons in the spacer region 123, thereby improving the carrier collection rate and further improving the efficiency of the back contact battery 100.

[0140] Similarly, when the first isolated doped portion 40 is N-type doped and the fourth isolated doped portion 110 is P-type doped, the first isolated doped portion 40 is saturated with electron carriers, which will exert a repulsive force on subsequent electron carriers, thereby enabling electron carriers to be collected more quickly by the first polar doped layer 20. At the fourth isolated doped portion 110, the fourth isolated doped portion 110 is saturated with hole carriers, which will exert a repulsive force on subsequent holes, thereby enabling holes to be collected more quickly by the second polar doped layer 30, without causing large recombination between holes and electrons in the spacer region 123, thereby improving the carrier collection rate and further improving the efficiency of the back contact battery 100.

[0141] In other words, by setting the first isolated doped portion 40 and the fourth isolated doped portion 110, the collection rate of holes and electrons at the spacer region 123 can be improved, thereby improving the efficiency of the back contact battery 100.

[0142] Furthermore, in such an embodiment, the fourth isolated doped portion 110 is preferably spaced apart from the first isolated protrusion 1231 and the first isolated doped portion 40, that is, the fourth isolated doped portion 110 is preferably not in contact with the first isolated protrusion 1231. Thus, by configuring the fourth isolated doped portion 110 to not contact either the first isolated protrusion 1231 or the first isolated doped portion 40, the collection rate of holes and electrons can be further improved, thereby further enhancing the efficiency of the back contact battery 100.

[0143] Referring to Figure 8, in some embodiments, the spacing between the fourth isolated doped portion 110 and the first isolated protrusion 1231 in the first direction is 0.1 μm-200 μm.

[0144] Thus, by setting the spacing between the fourth isolated doped portion 110 and the first isolated protrusion 1231 to 0.1μm-200μm, the carrier collection rate can be further optimized and surface recombination can be further reduced.

[0145] Specifically, in such an embodiment, the spacing between the fourth isolated doped portion 110 and the first isolated protrusion 1231 can be, for example, any value between 0.1μm, 0.2μm, 0.4μm, 0.6μm, 0.8μm, 1μm, 2μm, 3μm, 4μm, 5μm, 6μm, 7μm, 8μm, 9μm, 10μm, 20μm, 30μm, 40μm, 50μm, 60μm, 70μm, 80μm, 90μm, 100μm, 120μm, 140μm, 160μm, 180μm, 200μm, or 0.1μm-200μm.

[0146] Please refer to Figures 9 and 10. In some embodiments, the back contact battery 100 may include a plurality of fifth isolated doped portions 120. The plurality of fifth isolated doped portions 120 are all disposed within the spacer region 123 and are spaced apart from the first polar doped layer 20 and the second polar doped layer 30. The polarity of the fifth isolated doped portion 120 and the second polar doped layer 30 is the same.

[0147] Thus, by simultaneously setting several first isolated doped portions 40 and second isolated doped portions 120 of different polarities in the spacer region 123, both the first isolated doped portion 40 and the fifth isolated doped portion 120 can form field passivation in the spacer region 123, thereby improving the passivation effect and increasing the collection rate of holes and electrons.

[0148] Specifically, when the first isolated doped portion 40 is P-type doped and the fifth isolated doped portion 120 is N-type doped, the first isolated doped portion 40 is saturated with hole carriers, which will exert a repulsive force on subsequent hole carriers, thereby enabling hole carriers to be collected more quickly by the first polar doped layer 20. At the fifth isolated doped portion 120, the fifth isolated doped portion 120 is saturated with electron carriers, which will exert a repulsive force on subsequent electrons, thereby enabling electrons to be collected more quickly by the second polar doped layer 30. This reduces the probability of recombination between holes and electrons in the spacer region 123, thereby improving the carrier collection rate and further improving the efficiency of the back contact battery 100.

[0149] Similarly, when the first isolated doped portion 40 is N-type doped and the fifth isolated doped portion 120 is P-type doped, the first isolated doped portion 40 is saturated with electron carriers, which will exert a repulsive force on subsequent electron carriers, thereby enabling electron carriers to be collected more quickly by the first polar doped layer 20. At the fifth isolated doped portion 120, the fifth isolated doped portion 120 is saturated with hole carriers, which will exert a repulsive force on subsequent holes, thereby enabling holes to be collected more quickly by the second polar doped layer 30, without causing large recombination between holes and electrons in the spacer region 123, thereby improving the carrier collection rate and further improving the efficiency of the back contact battery 100.

[0150] In other words, by setting the first isolated doped portion 40 and the fifth isolated doped portion 120, the collection rate of holes and electrons at the spacer region 123 can be improved, thereby improving the efficiency of the back contact battery 100.

[0151] In such an embodiment, the fifth isolated doped portion 120 does not have electrodes, that is, the first electrode 60 and the second electrode 70 are physically separated from and do not contact the fifth isolated doped portion 120.

[0152] In the embodiments of this disclosure, the specific shape of the fifth isolated doped portion 120 can be a regular shape or an irregular shape. For example, in some embodiments, the shape of the first isolated doped portion 40 can be one or more of a cone shape, a pyramid shape, a frustum shape, and a truncated cone shape, and there is no specific limitation here.

[0153] Furthermore, in such an embodiment, the fifth isolated doped portion 120 and the first isolated doped portion 40 are spaced apart within the spacer region 123, that is, the fifth isolated doped portion 120 and the first isolated doped portion 40 are independent of each other and do not contact each other.

[0154] Thus, by setting the fifth isolated doped portion 120 to be independent of and not in contact with the first isolated doped portion 40, the collection rate of holes and electrons can be further improved, thereby further improving the efficiency of the back contact battery 100.

[0155] Furthermore, in some embodiments, the distance between any fifth isolated doped portion 120 and any first isolated doped portion 40 (i.e., the length of the line connecting any first isolated doped portion 40 and any fifth isolated doped portion 120) is greater than or equal to 0.1 μm-200 μm.

[0156] Thus, by setting the spacing between the fifth isolated doped portion 120 and the first isolated protrusion 1231 to 0.1μm-200μm, the carrier collection rate can be further optimized and surface recombination can be further reduced.

[0157] Specifically, the spacing between any fifth isolated doped portion 120 and any first isolated doped portion 40 is any value between 0.1 μm and 200 μm, and can be, for example, one of 0.1 μm, 0.2 μm, 0.4 μm, 0.6 μm, 0.8 μm, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, 20 μm, 30 μm, 40 μm, 50 μm, 60 μm, 70 μm, 80 μm, 90 μm, 100 μm, 120 μm, 140 μm, 160 μm, 180 μm, and 200 μm.

[0158] Referring to Figure 10, in some embodiments, in the first direction, the spacing L5 between the fifth isolated doped portion 120 and the second polar doped layer 30 is greater than or equal to 300 nm.

[0159] In this way, the poor isolation effect between the fifth isolated doped portion 120 and the second polar doped layer 30 can be avoided due to the small spacing between them. That is, this setting can improve the isolation effect between the fifth isolated doped portion 120 and the second polar doped layer 30, thereby achieving a better carrier collection rate and improving the passivation effect of the spacer region 123.

[0160] Specifically, it is not difficult to understand that when the distance between the two is too small (i.e. less than 300 nm), the electrical isolation effect between the fifth isolated doped part 120 and the second polar doped layer 30 is poor. This is equivalent to the fifth isolated doped part 120 being connected to the second polar doped layer 30, which easily leads to the carriers at the fifth isolated doped part 120 being directly collected by the second polar doped layer 30, and the corresponding carriers cannot be saturated and filled at the fifth isolated doped part 120. Thus, the function of repelling holes or electrons at the fifth isolated doped part 120 cannot be realized, resulting in a significant decrease in the effect of reducing surface recombination.

[0161] In other words, in this disclosure, by setting the spacing L5 between the fifth isolated doped portion 120 and the second polar doped layer 30 to be greater than or equal to 300 nm, the surface recombination of the spacer region 123 can be significantly reduced, thereby achieving a better carrier collection rate.

[0162] Specifically, in such an embodiment, the spacing L5 between the fifth isolated doped portion 120 and the second polar doped layer 30 can be, for example, any value among 300nm, 400nm, 500nm, 600nm, 700nm, 800nm, 900nm, 1μm, 2μm, 3μm, 4μm, 5μm, 6μm, 7μm, 8μm, 9μm, 10μm, 11μm, 12μm, 13μm, 14μm, 15μm, 16μm, 17μm, 18μm, 19μm, 20μm, etc.

[0163] The maximum spacing between the fifth isolated doped portion 120 and the first polar doped layer 20 is preferably the width of the spacer region 123 in the first direction minus 6 μm, that is, 300nm≤L5≤L2-6μm.

[0164] Research has shown that the optimal L5 is greater than or equal to 3μm and less than or equal to L2-6μm, under which the performance of the back contact battery 100 can be optimized.

[0165] Please continue to refer to Figure 10. In some embodiments, in the first direction, the spacing L6 between the fifth isolated doped portion 120 and the first polar doped layer 20 is greater than or equal to 300 nm.

[0166] Thus, by setting the spacing between the fifth isolated doped portion 120 and the first polar doped layer 20 to be greater than 300 nm, the isolation effect between the fifth isolated doped portion 120 and the first polar doped layer 20 can be guaranteed, preventing some charge carriers at the fifth isolated doped portion 120 from directly recombinating with the charge carriers at the first polar doped layer 20, which would cause the charge carriers at the fifth isolated doped portion 120 to fail to reach saturation, thereby significantly reducing the effect of reducing surface recombination.

[0167] Specifically, it is not difficult to understand that when the spacing between the two is too small (i.e., less than 300 nm), it is equivalent to the fifth isolated doped part 120 being connected to the first polar doped layer 20. This can easily cause the charge carriers (e.g., holes) at the fifth isolated doped part 120 to recombine directly with the charge carriers (e.g., electrons) at the first polar doped layer 20, and the corresponding charge carriers (e.g., holes) cannot be saturated and filled at the fifth isolated doped part 120. Thus, the function of repelling holes or electrons at the fifth isolated doped part 120 cannot be achieved, resulting in a significant reduction in the effect of reducing surface recombination.

[0168] In other words, in this disclosure, by setting the spacing L6 between the fifth isolated doped portion 120 and the first polar doped layer 20 to be greater than or equal to 300 nm, the surface recombination of the spacer region 123 can be significantly reduced, thereby achieving a better carrier collection rate.

[0169] Specifically, in such an embodiment, the spacing L6 between the fifth isolated doped portion 120 and the first polar doped layer 20 can be any value selected from, for example, 300nm, 400nm, 500nm, 600nm, 700nm, 800nm, 900nm, 1μm, 2μm, 3μm, 4μm, 5μm, 6μm, 7μm, 8μm, 9μm, 10μm, 11μm, 12μm, 13μm, 14μm, 15μm, 16μm, 17μm, 18μm, 19μm, 20μm, etc. Preferably, the maximum spacing between the fifth isolated doped portion 120 and the first polar doped layer 20 is the width of the spacing region 123 in the first direction minus 6μm, i.e., 300nm ≤ L6 ≤ L2 - 6μm. Research has shown that the optimal L6 size is greater than or equal to 3μm and less than or equal to L2-6μm, which allows the back contact battery 100 to achieve optimal performance.

[0170] In the embodiments of this disclosure, it is preferable that the distance L1 between the fifth isolated doped portion 120 and the first polar doped layer 20 is greater than or equal to 3 μm, and the distance L5 between the fifth isolated doped portion 120 and the second polar doped layer 30 is also greater than or equal to 3 μm. In this way, the surface recombination of the spacer region 123 can be significantly reduced, so that the carrier collection rate reaches the optimal state.

[0171] In some embodiments, a plurality of fifth isolated doped portions 120 may be randomly distributed on the spacer region 123, or a plurality of fifth isolated doped portions 120 may be arranged at intervals along the second direction on the spacer region 123, and there is no specific limitation here.

[0172] When several isolated fifth doped portions 120 are randomly distributed on the spacer region 123, the spacing between any two isolated fifth doped portions 120 (i.e. the length of the line connecting any two isolated fifth doped portions 120) is 30μm-380μm.

[0173] Referring to Figure 9, in some embodiments, a plurality of fifth isolated doped portions 120 are arranged at intervals along the second direction on the spacer region 123, and the spacing L7 between two adjacent fifth isolated doped portions 120 can be 30μm-380μm.

[0174] In this way, the spacing between the fifth isolated doped portions 120 can be avoided from being too small, which would cause the fifth isolated doped portions 120 to be too dense.

[0175] Specifically, when a plurality of fifth isolated doped portions 120 are randomly distributed on the spacer region 123, the spacing between any two fifth isolated doped portions 120 can be, for example, any value between 30 μm and 380 μm. For example, the spacing between any two fifth isolated doped portions 120 can be one of the following: 30 μm, 35 μm, 40 μm, 45 μm, 50 μm, 55 μm, 60 μm, 65 μm, 70 μm, 75 μm, 80 μm, 85 μm, 90 μm, 95 μm, 100 μm, 120 μm, 140 μm, 160 μm, 180 μm, 20 μm, 220 μm, 240 μm, 260 μm, 280 μm, 300 μm, 320 μm, 340 μm, 360 μm, or 380 μm.

[0176] When several isolated fifth doped portions 120 are also arranged at intervals along the second direction on the spacer region 123, the size of the spacing L7 between two adjacent isolated fifth doped portions 120 can be any value between 30μm and 380μm, for example, the size of the spacing L7 between two adjacent isolated fifth doped portions 120 can be one of the following: 30μm, 35μm, 40μm, 45μm, 50μm, 55μm, 60μm, 65μm, 70μm, 75μm, 80μm, 85μm, 90μm, 95μm, 100μm, 120μm, 140μm, 160μm, 180μm, 200μm, 220μm, 240μm, 260μm, 280μm, 300μm, 320μm, 340μm, 360μm, 380μm.

[0177] Please refer to Figure 10. In some embodiments, the thickness H2 of the fifth isolated doped portion 120 can be 20 nm to 450 nm.

[0178] Thus, by setting the thickness of the fifth isolated doped portion 120 within this range, it is possible to avoid the fifth isolated doped portion 120 being too thin and thus failing to achieve an efficient floating junction passivation effect, and it is also possible to avoid the fifth isolated doped portion 120 being too thick and thus increasing costs.

[0179] Specifically, the thickness H2 of the fifth isolated doped portion 120 can be any value between 20 nm and 450 nm. For example, the thickness H2 of the fifth isolated doped portion 120 can be one of the following: 20 nm, 22 nm, 24 nm, 26 nm, 28 nm, 30 nm, 32 nm, 34 nm, 36 nm, 38 nm, 40 nm, 42 nm, 44 nm, 46 nm, 48 nm, 50 nm, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, and 450 nm.

[0180] In some embodiments, the ratio of the projected area of ​​all fifth isolated doped portions 120 within a single spacer region 123 in the thickness direction of the silicon wafer 10 to the projected area of ​​the single spacer region 123 in the thickness direction of the silicon wafer 10 is 0.0001-0.5.

[0181] In this way, it is possible to avoid the fifth isolated doped part 120 having too small an area ratio, which would result in the floating junction passivation region having too small an area and thus failing to achieve the expected effect. It is also possible to avoid the fifth isolated doped part 120 having too large an area ratio, which would result in excessive saturation of charge carriers at the fifth isolated doped part 120, leading to a reduction in the number of charge carriers collected by the first polar doped layer 20. At the same time, it is also possible to avoid the fifth isolated doped part 120 having too large an area ratio, which would result in excessive parasitic absorption of light from the back side and a significant reduction in the bifaciality.

[0182] In other words, in such an embodiment, setting the area ratio of the two within this reasonable range can improve the carrier collection rate while ensuring the number of carriers collected. Through such an optimized design, the relationship between the carrier collection rate and the number of carriers collected can be balanced, thereby optimizing the conversion efficiency of the back contact battery 100.

[0183] Specifically, the value of this ratio can be, for example, one of the following: 0.0001, 0.0005, 0.001, 0.0015, 0.002, 0.004, 0.006, 0.008, 0.01, 0.02, 0.03, 0.04, 0.05, 0.06, 0.07, 0.08, 0.09, 0.1, 0.15, 0.2, 0.25, 0.3, 0.35, 0.4, 0.45, or 0.5.

[0184] In such an embodiment, the ratio of the areas of the two is preferably 0.001-0.1. Thus, through this optimized design, the relationship between bifaciality and efficiency can be balanced, improving the conversion efficiency of the back contact battery 100 while also achieving a better bifaciality.

[0185] Referring to Figure 11, in some embodiments, a plurality of second arc-shaped recessed regions 31 are formed on the sidewalls adjacent to the second polar doped layer 30 and the spacer region 123. The plurality of second arc-shaped recessed regions 31 are arranged along the second direction, and two adjacent second arc-shaped recessed regions 31 intersect each other. The fifth isolated doped portion 120 is disposed near the junction of two adjacent second arc-shaped recessed regions 31.

[0186] Thus, the arrangement of the second arc-shaped recessed region 31 helps to reduce the carrier recombination rate of the second polar doped layer 30 near the spacer region 123, thereby improving the carrier collection efficiency. Furthermore, the fabrication process of the second arc-shaped recessed region 31 is simple, causing minimal damage to the first polar doped layer 20, which facilitates the subsequent deposition of the back passivation film layer 50, thereby improving the passivation performance of the back contact cell 100. In addition, placing the fifth isolated doped portion 120 close to the boundary between two adjacent second arc-shaped recessed regions 31 can further enhance the field passivation effect.

[0187] Specifically, in this embodiment, the shape of the second arc-shaped recessed region 31 can be a regular arc shape such as a circular arc, or an irregular arc shape with different curvatures at different positions; no specific limitation is made here. The intersection of two adjacent first arc-shaped recessed regions 31 refers to the fact that the sidewalls adjacent to the second polar doped layer 30 and the spacer region 123 are composed of multiple first arc-shaped recessed regions 31. That is, the outline of the sidewalls adjacent to the second polar doped layer 30 and the spacer region 123 is basically a wavy curve.

[0188] In such an embodiment, the distance between the fifth isolated doped portion 120 and the intersection of two adjacent first arc-shaped recessed regions 31 is greater than or equal to 300 nm.

[0189] Referring to FIG12, in some embodiments, a trench 1232 is formed in the spacer region 123, and a second isolated protrusion 1233 is provided in the trench 1232. A fifth isolated doped portion 120 is disposed on the second isolated protrusion 1233 and covers at least a portion of the second isolated protrusion 1233.

[0190] Thus, by setting the trench 1232 and the second isolated protrusion 1233, the isolation effect between the first polar doped layer 20 and the second polar doped layer 30 can be further improved, and the passivation effect of the subsequent back passivation film layer 50 can be improved.

[0191] Specifically, in such embodiments, in the embodiments of this disclosure, the spacer region 123 and the second region 122 are more recessed into the silicon wafer 10 than the first region 121, and the surface of the first isolated protrusion 1231 can be flush with the surface of the first polar doped layer 20. In one possible embodiment, during the fabrication process, the first polar doped layer 20 can be deposited on the entire back surface 12 of the silicon wafer 10 firstly, and then the first polar doped layer 20 on a portion of the area can be removed by etching (laser etching, wet etching) or other methods, thereby forming a plurality of first polar doped layers 20 arranged along the first direction, retaining a portion of independent first isolated doped portions 40. It can be understood that during the removal process, a groove will be formed on the silicon wafer 10, and a first isolated protrusion 1231 will be formed below the first isolated doped portion 40, which is a protrusion relative to the groove.

[0192] Subsequently, a second polar doped layer 30 can be prepared within the trench, and then the second polar doped layer 30 is locally removed (e.g., by laser etching or wet etching) to form a trench 1232. Within the trench 1232, independent second isolated protrusions 1233 and fifth isolated doped portions 120 are formed. Thus, the region corresponding to the first polar doped layer 20 is the first region 121, the region corresponding to the second polar doped layer 30 is the second region 122, and the region between the regions containing the first polar doped layer 20 and the second polar doped layer 30 is the spacer region 123. The silicon wafer 10 has a first isolated protrusion 1231 and a second isolated protrusion 1233 in the spacer region 123. The first isolated doped portion 40 is disposed on the first isolated protrusion 1231, and the fifth isolated doped portion 120 is disposed on the second isolated protrusion 1233. Of course, it is understood that in other embodiments, other methods can also be used to prepare the back contact battery 100; no specific method is limited here, as long as it can form the structure corresponding to this disclosure.

[0193] In some embodiments, the fifth isolated doped portion 120 covers only a portion of the second isolated protrusion 1233.

[0194] In this way, the cross section of the fifth isolated doped part 120 can be avoided from being exposed at the cross section of the trench 1232, thus reducing recombination in the space charge region.

[0195] Referring to Figure 12, in some embodiments, the fifth isolated doped portion 120 completely covers the second isolated protrusion 1233, and the fifth isolated doped portion 120 has a second suspended segment 1201 extending beyond the second isolated protrusion 1233 and suspended within the spacer region 123. Specifically, the second suspended segment 1201 is suspended above the trench 1232.

[0196] Thus, the fifth isolated doped portion 120 has a second suspended segment 1201 extending and suspended on the spacer region 123. There are opposing deposition regions between the second suspended segment 1201 and the silicon wafer 10. During the subsequent deposition of the back passivation film 50, this deposition region configuration can suppress the full exchange of plasma components between this region and those outside this region, thereby achieving a localized distribution of the mobile hydrogen content in the back passivation film 50 on the back side 12. This results in a lower mobile hydrogen content in the back passivation film 50 within this deposition region and a higher mobile hydrogen content in other regions, achieving optimal passivation and anti-attenuation effects. Simultaneously, it can reduce the direct bombardment of the silicon wafer by the plasma, reducing bombardment damage.

[0197] Specifically, in such an embodiment, the second suspended segment 1201 can extend in any direction and be suspended above the groove 1232; the extension direction of the second suspended segment 1201 is not specifically limited. The extension length of the second suspended segment 1201 relative to the second isolated protrusion 1233 can be any value between 0.2μm and 50μm. For example, the extension length of the second suspended segment 1201 relative to the second isolated protrusion 1233 can be 0.2μm-50μm, such as one of 0.2μm, 0.4μm, 0.6μm, 0.8μm, 1μm, 2μm, 3μm, 4μm, 5μm, 6μm, 7μm, 8μm, 9μm, 10μm, 20μm, 30μm, 40μm, and 50μm.

[0198] Referring to Figure 13, in some embodiments, at least a portion of the first polar doped layer 20 has a third suspended segment 22 extending above the spacer region 123, the third suspended segment 22 is suspended over a portion of the spacer region 123, and the first isolated doped portion 40 is disposed on the area of ​​the spacer region 123 not covered by the third suspended segment 22.

[0199] Thus, by setting the third suspended section 22, a relatively spaced deposition area can be formed between the bottom of the third suspended section 22 and the spacer region 123. During the subsequent deposition of the back passivation film 50, this deposition area setting can suppress the full exchange of plasma components between this area and the plasma outside this area, thereby achieving a localized distribution of the mobile hydrogen content of the back passivation film 50 on the back side 12. This results in a lower mobile hydrogen content in the back passivation film 50 within the deposition area and a higher mobile hydrogen content in the back passivation film 50 in other areas, achieving optimal passivation and anti-attenuation effects. At the same time, it can reduce the direct bombardment of the silicon wafer by the plasma and reduce bombardment damage.

[0200] Referring to Figure 14, in some embodiments, a sixth isolated doped portion 130 is provided on the surface of the third suspended segment 22 facing the silicon wafer 10, and the polarity of the sixth isolated doped portion 130 is the same as that of the second polar doped layer 30.

[0201] Thus, by providing a sixth isolated doped portion 130 of different polarities on the surface of the third suspended segment 22 facing the silicon wafer 10, the passivation effect on the third suspended segment 22 can be improved, thereby improving the passivation effect of the entire spacer region 123.

[0202] Specifically, in such an embodiment, the sixth isolated doped portion 130 located on the third suspended segment 22 can be a single, continuous doped portion, or it can be a plurality of independent sixth isolated doped portions 130 on the third suspended segment 22. In such an embodiment, the sixth isolated doped portion 130 can be in direct contact with the third suspended segment 22 or can be insulated from the third suspended segment 22.

[0203] In some embodiments, the third suspended segment 22 may also extend to the area of ​​the silicon wafer 10 that is blocked by the third suspended segment 22, thereby further enhancing the passivation effect of the spacer region 123.

[0204] Referring to Figure 15, in some embodiments, a seventh isolated doped portion 140 is provided on the area of ​​the silicon wafer 10 that is blocked by the third suspended segment 22. The polarity of the seventh isolated doped portion 140 is the same as that of the second polar doped layer 30. The seventh isolated doped portion 140 is spaced apart from the first polar doped layer 20 and the second polar doped layer 30, that is, the seventh isolated doped portion 140 is not in contact with either the first polar doped layer 20 or the second polar doped layer 30.

[0205] Thus, the seventh isolated doped portion 140 is in contact with the silicon wafer 10 but not with the first polar doped layer 20 or the second polar doped layer 30. In this way, by setting the first isolated doped portion 40 and the seventh isolated doped portion 140 of different polarities, both the first isolated doped portion 40 and the seventh isolated doped portion 140 can form field passivation in the spacer region 123, thereby improving the passivation effect. Furthermore, by setting the first isolated doped portion 40 and the seventh isolated doped portion 140, the collection rate of holes and electrons can be improved.

[0206] Specifically, when the doping type of the first isolated doped portion 40 is P-type doping and the doping type of the seventh isolated doped portion 140 is N-type doping, the first isolated doped portion 40 is saturated with hole carriers, which will generate a repulsive force on subsequent hole carriers, thereby enabling hole carriers to be collected more quickly by the first polar doped layer 20. At the seventh isolated doped portion 140, the electron carriers are saturated with electron carriers, which will generate a repulsive force on subsequent electrons, thereby enabling electrons to be collected more quickly by the second polar doped layer 30. This reduces the probability of recombination between holes and electrons in the spacer region 123, thereby improving the carrier collection rate and further improving the efficiency of the back contact battery 100.

[0207] Similarly, when the first isolated doped portion 40 is N-type doped and the seventh isolated doped portion 140 is P-type doped, the first isolated doped portion 40 is saturated with electron carriers, which will exert a repulsive force on subsequent electron carriers, thereby enabling electron carriers to be collected more quickly by the first polar doped layer 20. At the seventh isolated doped portion 140, the seventh isolated doped portion 140 is saturated with hole carriers, which will exert a repulsive force on subsequent holes, thereby enabling holes to be collected more quickly by the second polar doped layer 30, without causing large recombination between holes and electrons in the spacer region 123, thereby improving the carrier collection rate and further improving the efficiency of the back contact battery 100.

[0208] In other words, by setting the first isolated doped portion 40 and the seventh isolated doped portion 140, the collection rate of holes and electrons at the spacer region 123 can be improved, thereby improving the efficiency of the back contact battery 100.

[0209] Furthermore, in such an embodiment, the seventh isolated doped portion 140 is preferably spaced apart from the first isolated doped portion 40, that is, the seventh isolated doped portion 140 and the first isolated doped portion 40 are preferably not in contact. In this way, by setting the seventh isolated doped portion 140 to not contact either the first isolated doped portion 40, the collection rate of holes and electrons can be further improved, and the efficiency of the back contact battery 100 can be further improved.

[0210] Referring to FIG16, in some embodiments, the silicon wafer 10 has a silicon wafer extension 13 extending onto and suspended within the spacer region 123, and at least a portion of the third suspended segment 22 is stacked on the silicon wafer extension 13.

[0211] Thus, by setting the silicon wafer extension 13, the third suspended segment 22 can be prevented from breaking and falling into the spacer region 123 during the fabrication process, which would cause defects. It can also further suppress the full exchange of plasma components between this region and the plasma components outside this region, so as to achieve the best passivation and anti-attenuation effect. At the same time, it can also further reduce the direct bombardment of the silicon wafer by the plasma and reduce bombardment damage.

[0212] Referring to Figure 17, in some embodiments, the silicon wafer extension 13 has an eighth isolated doped portion 150 on the surface opposite to the third suspended segment 22, and the polarity of the eighth isolated doped portion 150 is the same as that of the second polar doped layer 30.

[0213] Thus, by providing an eighth isolated doped portion 150 on the silicon wafer extension 13, the passivation effect on the silicon wafer extension 13 can be improved, thereby improving the passivation effect of the entire spacer region 123. At the same time, the provision of the eighth isolated doped portion 150 can also form a floating junction passivation, thereby further improving the carrier collection rate.

[0214] In some embodiments, the eighth isolated doped portion 150 may preferably be spaced apart from the first isolated doped portion 40, thereby further optimizing the carrier collection rate of the back contact cell 100.

[0215] In the description of this specification, the reference to terms such as "some embodiments," "illustrative embodiments," "examples," "specific examples," and "some examples" indicates that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, any of the specific features, structures, materials, or characteristics described herein may be combined in any suitable manner in one or more embodiments or examples.

[0216] Furthermore, the above description is merely a preferred embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A back-contact battery, comprising: A silicon wafer having a front side and a back side, the back side including a first region and a second region arranged alternately along a first direction, and both the first region and the second region extending along a second direction, with a gap between adjacent first regions and second regions, and the second direction intersecting the first direction; A first polar doped layer is stacked on the first region; A second polar doped layer is stacked on the second region, the polarity of the second polar doped layer being opposite to that of the first polar doped layer; and A plurality of first isolated doped portions are independently disposed within the spacer region and spaced apart from the first polar doped layer and the second polar doped layer, wherein the polarity of the first isolated doped portion is the same as that of the first polar doped layer.

2. The back contact battery according to claim 1, wherein, In the first direction, the spacing between the first isolated doped portion and the first polar doped layer is greater than or equal to 300 nm.

3. The back contact battery according to claim 1, wherein, In the first direction, the spacing between the first isolated doped portion and the second polar doped layer is greater than or equal to 300 nm.

4. The back contact battery according to claim 1, wherein, A plurality of the first isolated doped portions are randomly distributed on the spacer region; or A plurality of the first isolated doped portions are arranged at intervals along the second direction on the spacer region.

5. The back contact battery according to claim 4, wherein, When a plurality of first isolated doped portions are arranged at intervals along the second direction on the spacer region, the spacing between two adjacent first isolated doped portions in the second direction is 30 μm-380 μm.

6. The back contact battery according to claim 1, wherein, The ratio of the projected area of ​​all the first isolated doped portions within a single spacer region in the thickness direction of the silicon wafer to the projected area of ​​the single spacer region in the thickness direction of the silicon wafer is 0.0001-0.

5.

7. The back contact battery according to claim 6, wherein, The ratio of the projected area of ​​all the first isolated doped portions within a single spacer region in the thickness direction of the silicon wafer to the projected area of ​​the single spacer region in the thickness direction of the silicon wafer is 0.001-0.

1.

8. The back contact battery according to claim 1, wherein, The thickness of the first isolated doped portion is 20nm-450nm.

9. The back contact battery according to claim 1, wherein, The first polar doped layer has a plurality of first arc-shaped recessed regions on the sidewall adjacent to the spacer region. The plurality of first arc-shaped recessed regions are arranged along the second direction. Two adjacent first arc-shaped recessed regions intersect each other. The first isolated doped portion is disposed near the junction of two adjacent first arc-shaped recessed regions.

10. The back contact battery according to claim 1, wherein, Within the spacer region, the silicon wafer has a first isolated bump, the first isolated doped portion being disposed on the first isolated bump and covering at least a portion of the first isolated bump.

11. The back contact battery according to claim 10, wherein, The first isolated dopant completely covers the first isolated protrusion, and the first isolated dopant portion has a first suspended segment extending beyond the first isolated protrusion and suspended within the spacer region.

12. The back contact battery according to claim 11, wherein, The first suspended segment has a second isolated doped portion on its surface facing the silicon wafer. The second isolated doped portion has the opposite polarity to the first polar doped layer and the same polarity as the second polar doped layer.

13. The back contact battery according to claim 12, wherein, The second isolated doped portion is insulated from the first suspended segment.

14. The back contact battery according to claim 12, wherein, The second isolated doped portion also extends along the side of the first isolated protrusion to the area of ​​the silicon wafer that is blocked by the first suspended segment.

15. The back contact battery according to claim 11, wherein, The first isolated protrusion has a third isolated doped portion on its side, and the third isolated doped portion is spaced apart from the first isolated doped portion.

16. The back contact battery according to claim 11, wherein, A fourth isolated doped portion is provided on the area of ​​the silicon wafer that is blocked by the first suspended segment. The polarity of the fourth isolated doped portion is the same as that of the second polar doped layer, and the fourth isolated doped portion is spaced apart from the first polar doped layer and the second polar doped layer.

17. The back contact battery according to claim 16, wherein, The fourth isolated doped portion is spaced apart from the first isolated protrusion and the first isolated doped portion.

18. The back contact battery according to claim 17, wherein, In the first direction, the distance between the fourth isolated doped portion and the first isolated protrusion is 0.1 μm-200 μm.

19. The back contact battery according to claim 1, wherein, The back contact battery also includes a plurality of fifth isolated doped portions, all of which are disposed within the spacer region, and the fifth isolated doped portions are spaced apart from the first polar doped layer and the second polar doped layer, and the polarity of the fifth isolated doped portions is the same as that of the second polar doped layer.

20. The back contact battery according to claim 19, wherein, The fifth isolated doped portion is spaced apart from the first isolated doped portion within the spacer region.

21. The back contact battery according to claim 20, wherein, The spacing between any of the fifth isolated doped portions and any of the first isolated doped portions is greater than or equal to 0.1 μm-200 μm.

22. The back contact battery according to claim 19, wherein, In the first direction, the spacing between the fifth isolated doped portion and the second polar doped layer is greater than or equal to 300 nm.

23. The back contact battery according to claim 19, wherein, In the first direction, the spacing between the fifth isolated doped portion and the first polar doped layer is greater than or equal to 300 nm.

24. The back contact battery according to claim 19, wherein, Several of the fifth isolated doped portions are randomly distributed on the spacer region; or Several of the fifth isolated doped portions are arranged at intervals along the second direction on the spacer region.

25. The back contact battery according to claim 21, wherein, When several of the fifth isolated doped portions are arranged at intervals along the second direction on the spacer region, the spacing between two adjacent fifth isolated doped portions is 30μm-380μm.

26. The back contact battery according to claim 19, wherein, The ratio of the projected area of ​​all the fifth isolated doped portions within a single spacer region in the thickness direction of the silicon wafer to the projected area of ​​the single spacer region in the thickness direction of the silicon wafer is 0.0001-0.

5.

27. The back contact battery according to claim 26, wherein, The ratio of the projected area of ​​all the fifth isolated doped portions within a single spacer region in the thickness direction of the silicon wafer to the projected area of ​​the single spacer region in the thickness direction of the silicon wafer is 0.001-0.

1.

28. The back contact battery according to claim 19, wherein, The thickness of the fifth isolated doped portion is 20nm-450nm.

29. The back contact battery according to claim 19, wherein, The second polar doped layer has a plurality of second arc-shaped recessed regions formed on the sidewall surface adjacent to the spacer region. The plurality of second arc-shaped recessed regions are arranged along the second direction. Two adjacent second arc-shaped recessed regions intersect each other. The fifth isolated doped part is disposed near the junction of two adjacent second arc-shaped recessed regions.

30. The back contact battery according to claim 19, wherein, A trench is formed in the spacer region, and the trench has a second isolated protrusion. The fifth isolated doped portion is disposed on the second isolated protrusion and covers at least a portion of the second isolated protrusion.

31. The back contact battery according to claim 30, wherein, The fifth isolated doped portion only covers a portion of the second isolated protrusion; or The fifth isolated doped portion completely covers the second isolated protrusion, and the fifth isolated doped portion has a second suspended segment extending beyond the second isolated protrusion and suspended within the spacer region.

32. The back contact battery according to claim 1, wherein, At at least a portion of the first polar doped layer, the first polar doped layer has a third suspended segment extending above the spacer region, the third suspended segment being suspended over a portion of the spacer region, and the first isolated doped portion being disposed in a region of the spacer region not obscured by the third suspended segment.

33. The back contact battery according to claim 32, wherein, A sixth isolated doped portion is provided on the surface of the third suspended segment facing the silicon wafer, and the polarity of the sixth isolated doped portion is the same as that of the second polar doped layer.

34. The back contact battery according to claim 32, wherein, A seventh isolated doped portion is provided on the area of ​​the silicon wafer that is blocked by the third suspended segment. The seventh isolated doped portion is spaced apart from the first polar doped layer and the second polar doped layer. The polarity of the seventh isolated doped portion is the same as that of the second polar doped layer.

35. The back contact battery according to claim 34, wherein, The seventh isolated doped portion is spaced apart from the first isolated doped portion.

36. The back contact battery according to claim 32, wherein, The silicon wafer has a silicon wafer extension that extends over and is suspended within the spacer region, and at least a portion of the third suspended segment is stacked on the silicon wafer extension.

37. The back contact battery according to claim 36, wherein, The silicon wafer extension has an eighth isolated doped portion on its surface away from the third suspended segment, and the polarity of the eighth isolated doped portion is the same as that of the second polar doped layer.

38. The back contact battery according to claim 37, wherein, The eighth isolated doped portion is spaced apart from the first isolated doped portion.

39. A battery assembly comprising a back contact battery as described in any one of claims 1-38.

40. A photovoltaic system comprising the battery module of claim 39.

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