Semiconductor device and method for preparing semiconductor device, electronic device, and vehicle

Abstract

Disclosed are a semiconductor device and a method for preparing the semiconductor device, an electronic device, and a vehicle. The semiconductor device comprises a substrate of a first conductive type, metal electrodes, and a first leakage protection layer. The metal electrodes are located on the upper surface of the substrate. The first leakage protection layer is located on the surface of the substrate between the metal electrodes and the side surface of the substrate.

Description

Semiconductor devices and methods for fabricating semiconductor devices, electronic devices and vehicles

[0001] Cross-reference of related applications

[0002] This application claims priority to Chinese Patent Application No. 202411465234.3, filed on October 18, 2024, with the China National Intellectual Property Administration, entitled "Semiconductor Device and Method for Preparing a Semiconductor Device, Electronic Equipment and Vehicle", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device, a method for manufacturing a semiconductor device, electronic equipment, and a vehicle. Background Technology

[0004] In practical applications of semiconductor device packaging, the device's metal electrodes are typically connected to the substrate via conductive adhesives or wire bonding to achieve circuit functionality and protect other components. However, because the metal electrodes are close to the mesa edge of the semiconductor device, and the substrate sides are exposed to air, metal electrode material can easily spill onto the substrate sides during manufacturing and packaging processes, forming conductive paths and leading to leakage current problems. Furthermore, conductive adhesive on the back of the substrate may migrate to the top surface of the device via the substrate sides, also causing similar leakage risks. This leakage problem not only shortens the lifespan of the semiconductor device but can also affect its stability and electrical performance, thus negatively impacting the reliability of the entire electronic system.

[0005] Public content

[0006] This disclosure aims to at least address one of the technical problems existing in the prior art. To this end, one object of this disclosure is to provide a semiconductor device that achieves effective isolation between the metal electrode and the side of the substrate, reducing the potential risk of leakage current and improving the stability and reliability of the device.

[0007] The second objective of this disclosure is to provide a method for fabricating semiconductor devices.

[0008] The third objective of this disclosure is to propose an electronic device.

[0009] The fourth objective of this disclosure is to propose a vehicle.

[0010] To achieve the above objectives, a semiconductor device according to a first aspect of this disclosure includes: a substrate of a first conductivity type; a metal electrode located on an upper surface of the substrate; and a first leakage protection layer located on a substrate surface between the metal electrode and a side surface of the substrate.

[0011] According to embodiments of the semiconductor device disclosed herein, a first leakage protection layer is provided between the metal electrode and the side surface of the substrate. This first leakage protection layer has excellent insulation properties and can form an effective barrier protection, thereby preventing the metal electrode from overflowing to the side surface of the substrate during die bonding or wire bonding. This avoids the formation of a conductive path between the metal electrode and the side surface of the substrate, reducing the potential risk of leakage. Furthermore, the presence of the first leakage protection layer also prevents the upward migration of conductive adhesive on the back of the substrate, further reducing the occurrence of leakage problems. This design ensures the insulation between the metal electrode and the side surface of the substrate, effectively improving the overall stability and reliability of the device.

[0012] In some embodiments, the first leakage protection layer is constructed as at least one step.

[0013] In some embodiments, the first leakage protection layer is constructed as a plurality of steps, the plurality of steps being arranged continuously along the side of the metal electrode to the substrate.

[0014] In some embodiments, the first leakage protection layer includes a first passivation layer located on the substrate surface between the metal electrode and the side of the substrate.

[0015] In some embodiments, the thickness H1 of the first passivation layer satisfies: 0.5um ≤ H1 ≤ 1.5um.

[0016] In some embodiments, the first leakage protection layer further includes a second passivation layer, wherein the second passivation layer is located on the first passivation layer.

[0017] In some embodiments, the thickness H2 of the second passivation layer satisfies: 0.5um ≤ H2 ≤ 1.5um.

[0018] In some embodiments, the first leakage protection layer is sloped from the metal electrode to the side of the substrate, and the first leakage protection layer is at a predetermined angle to the upper surface of the substrate.

[0019] In some embodiments, the thickness H3 of the first leakage protection layer satisfies: 0.5um ≤ H3 ≤ 1.5um.

[0020] In some embodiments, the first leakage protection layer also covers a portion of the upper surface of the substrate.

[0021] In some embodiments, the thickness H4 of the first leakage protection layer located on the upper surface of the substrate satisfies: 1um ≤ H4 ≤ 3um.

[0022] In some embodiments, the semiconductor device further includes at least one doped region of a second conductivity type, the doped region being located within the substrate and close to the upper surface of the substrate.

[0023] In some embodiments, the semiconductor device further includes: a metal dielectric layer located on the upper surface of the substrate corresponding to the doped region; and a metal electrode connected to the metal dielectric layer via a contact hole formed by a first leakage protection layer located on the upper surface of the substrate.

[0024] In some embodiments, the semiconductor device further includes: a second leakage protection layer, one end of which is connected to the first leakage protection layer, and a second end of which extends along the side of the substrate and at least to a position close to the lower surface of the substrate.

[0025] In some embodiments, the second leakage protection layer surrounds the lower surface of the substrate.

[0026] To achieve the above objectives, a method for fabricating a semiconductor device according to a second aspect of this disclosure includes: providing a substrate of a first conductivity type; and fabricating a first leakage protection layer and a metal electrode on the substrate, wherein the metal electrode is located on an upper surface of the substrate, and the first leakage protection layer is located on a substrate surface between the metal electrode and a side surface of the substrate.

[0027] According to the method for fabricating a semiconductor device according to embodiments of this disclosure, a first leakage protection layer is formed between a metal electrode and the side surface of a substrate. This first leakage protection layer has excellent insulation properties and can form an effective barrier to prevent the metal electrode from overflowing to the side surface of the substrate during die bonding or wire bonding. This avoids the formation of a conductive path between the metal electrode and the side surface of the substrate, reducing the potential risk of leakage. Furthermore, the presence of the first leakage protection layer also prevents the upward migration of conductive adhesive on the back of the substrate, further reducing the occurrence of leakage problems. This design ensures insulation between the metal electrode and the side surface of the substrate, effectively improving the overall stability and reliability of the device.

[0028] In some embodiments, forming a first leakage protection layer on the substrate includes: forming at least one step structure on the substrate surface between the metal electrode and the side of the substrate; and forming the first leakage protection layer on the surface of the at least one step structure, wherein the first leakage protection layer is configured as at least one step.

[0029] In some embodiments, forming the first leakage protection layer on the surface of the at least one stepped structure includes: forming a first passivation layer on the surface of the at least one stepped structure; and forming a second passivation layer on the first passivation layer, wherein the first passivation layer and the second passivation layer constitute the first leakage protection layer.

[0030] In some embodiments, forming a first leakage protection layer on the substrate includes: forming a sloped first leakage protection layer on the substrate surface between the metal electrode and the side surface of the substrate, wherein the first leakage protection layer is at a predetermined angle to the upper surface of the substrate.

[0031] In some embodiments, the first leakage protection layer further covers a portion of the upper surface of the substrate, and the method further includes: preparing at least one doped region of a second conductivity type within the substrate and near the upper surface of the substrate; and preparing a metal dielectric layer on the upper surface of the substrate corresponding to the doped region, wherein the metal electrode is connected to the metal dielectric layer through a contact hole formed by the first leakage protection layer located on the upper surface of the substrate.

[0032] In some embodiments, the method further includes: forming a second leakage protection layer on the side of the substrate, one end of the second leakage protection layer being connected to the first leakage protection layer, and a second end of the second leakage protection layer extending along the side of the substrate to a position close to the lower surface of the substrate.

[0033] In some embodiments, the second leakage protection layer surrounds the lower surface of the substrate.

[0034] To achieve the above objectives, an electronic device according to a third aspect of this disclosure includes the semiconductor device described in the above embodiments.

[0035] The electronic device according to the embodiments of this disclosure, by employing the semiconductor device described in the above embodiments, achieves effective isolation between the metal electrode and the side of the substrate, reduces the potential risk of leakage current, and thereby improves the stability and reliability of the device.

[0036] In some embodiments, the electronic device includes a light-emitting diode (LED) light source.

[0037] In some embodiments, the semiconductor device includes a transient suppression diode; and the light-emitting diode light source further includes a light-emitting diode and a substrate, the light-emitting diode being located on the substrate, and the transient suppression diode being flip-chip connected to the substrate to be connected in parallel with the light-emitting diode.

[0038] To achieve the above objectives, the vehicle according to the fourth aspect of this disclosure includes the semiconductor device described in the above embodiments, or includes the electronic device described in the above embodiments.

[0039] According to embodiments of the present disclosure, the vehicle employs the semiconductor device or electronic device described in the above embodiments. Its internal first leakage protection layer possesses excellent insulation properties, forming an effective isolation protection that prevents metal electrodes from overflowing to the side of the substrate during die bonding or wire bonding. This avoids the formation of a conductive path between the metal electrode and the side of the substrate, reducing the potential risk of leakage. Furthermore, the presence of the first leakage protection layer also prevents the upward migration of conductive adhesive on the back of the substrate, further reducing the occurrence of leakage problems. This design ensures insulation between the metal electrode and the side of the substrate, thereby improving the overall performance of the vehicle.

[0040] Additional aspects and advantages of this disclosure will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this disclosure. Attached Figure Description

[0041] The above and / or additional aspects and advantages of this disclosure will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0042] Figure 1 is a structural cross-sectional view of a semiconductor device according to an embodiment of the present disclosure;

[0043] Figure 2 is a structural cross-sectional view of a semiconductor device according to yet another embodiment of the present disclosure;

[0044] Figure 3 is a top view of the structure of a semiconductor device according to an embodiment of the present disclosure;

[0045] Figure 4 is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present disclosure;

[0046] Figure 5 is a block diagram of an electronic device according to an embodiment of the present disclosure;

[0047] Figure 6 is a block diagram of a vehicle according to an embodiment of the present disclosure;

[0048] Figure 7 is a block diagram of a vehicle according to yet another embodiment of the present disclosure.

[0049] Reference numerals: Vehicle 100; Electronic device 110; Semiconductor device 1; Light-emitting diode light source 2; Substrate 10; Metal electrode 20; First leakage protection layer 30; Doped region 40; Metal dielectric layer 50; Second leakage protection layer 60; Contact hole 70; First passivation layer 31; Second passivation layer 32. Detailed Implementation

[0050] The embodiments of this disclosure are described in detail below, and the embodiments described with reference to the accompanying drawings are exemplary.

[0051] A semiconductor device according to an embodiment of the present disclosure is described below with reference to FIG1.

[0052] Figure 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. As shown in Figure 1, the semiconductor device 1 includes a substrate 10 of a first conductivity type, a metal electrode 20, and a first leakage protection layer 30.

[0053] In some embodiments, substrate 10 is the base material of semiconductor device 1, carrying and supporting all subsequent layer structures. The choice of substrate 10 material is crucial to the performance of semiconductor device 1. Substrate 10 materials may include silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs), and other materials.

[0054] Silicon (Si) is one of the most commonly used semiconductor materials. Its relatively low cost makes it suitable for most electronic devices, such as diodes, transistors, and complementary metal-oxide-semiconductor (CMOS) devices. Silicon (Si) possesses good conductivity, mechanical strength, and mature processing technology, thus it is widely used in large-scale integrated circuits, power semiconductor devices, and other fields. Silicon carbide (SiC) has high breakdown field strength, high thermal conductivity, and a wide bandgap, making it suitable for harsh environments such as high temperature, high pressure, and high frequency. The excellent properties of silicon carbide (SiC) make it suitable for manufacturing high-power electronic devices, such as power metal-oxide-semiconductor field-effect transistors (MOSFETs), insulated-gate bipolar transistors (IGBTs), and Schottky diodes. Gallium arsenide (GaAs) has high electron mobility and low parasitic capacitance, making it suitable for high-frequency applications (such as wireless communication, microwave circuits, and optoelectronic devices).

[0055] In some embodiments, the first conductivity type refers to the doping type of the substrate 10, which can be N-type or P-type. The doping type is achieved by introducing specific impurity elements into a pure semiconductor material. Different doping types determine the types of charge carriers and the current conduction mode in the semiconductor device 1. For example, the N-type conductivity type is obtained by doping with pentavalent elements such as phosphorus (P) and arsenic (As), which generates additional free electrons as majority carriers within the material. The P-type conductivity type is obtained by doping with trivalent elements such as boron (B), which generates holes as majority carriers within the material.

[0056] Therefore, the conductivity type of substrate 10 affects the overall electrical performance of the device, providing physical and electrical support for other layers and structures of the device. This conductivity type determines factors such as electric field distribution and carrier conduction mechanism, and thus can affect the device's response speed, turn-on and turn-off characteristics in practical applications.

[0057] In some embodiments, the metal electrode 20 can be a conductive structure for providing electrical connections. It is located on the upper surface of the substrate 10 and is used to enable the input and output of current or signals. The metal electrode 20 can be a conductive layer formed by a deposition process, which is directly connected to external circuits or devices to provide electrical contact.

[0058] In some embodiments, the metal electrode 20 can be made of a metallic material such as gold-tin solder (AuSn). Gold-tin solder (AuSn) has a melting point of approximately 280°C, making it suitable for high-temperature environments. Furthermore, gold-tin solder (AuSn) possesses good electrical conductivity and high mechanical strength, enabling efficient transmission of electrical signals, resulting in greater device stability and suitability for long-term use. Therefore, gold-tin solder (AuSn) is commonly used in electronic devices requiring high reliability and durability.

[0059] In addition to gold-tin solder (AuSn), other metallic materials can be selected to fabricate the metal electrode 20, depending on factors such as application requirements, operating environment, and cost. Examples include aluminum (Al), copper (Cu), and silver (Ag). Aluminum is widely used in most integrated circuits due to its lower cost and mature manufacturing process, but its performance may not be as good as gold-tin solder in high-temperature or high-power applications. Copper has good conductivity and heat dissipation, and is often used in power devices or applications requiring higher current carrying capacity. Copper electrodes are suitable for high-power electronic components, but they are prone to oxidation and require appropriate encapsulation protection. Silver has excellent conductivity and is suitable for high-frequency and radio-frequency applications; however, silver is easily oxidized in air and also requires surface protection to ensure long-term stability.

[0060] In some embodiments, the first leakage protection layer 30 may be an insulating material layer in the semiconductor device 1, located on the surface of the substrate 10 between the metal electrode 20 and the side surface of the substrate 10. The main function of the first leakage protection layer 30 is to form electrical isolation, prevent the material of the metal electrode 20 from overflowing to the side surface of the substrate 10 during die bonding or wire bonding, and avoid unnecessary conductive paths between the metal electrode 20 and the side surface of the substrate 10, thereby effectively preventing leakage.

[0061] In some embodiments, the material of the first leakage protection layer 30 can be selected according to the specific application scenario and device requirements. Common materials may include silicon dioxide (SiO2), silicon nitride (Si3N4), or other dielectric materials with excellent insulation properties. Among them, silicon dioxide (SiO2) has excellent insulation properties and can withstand high temperatures, so it is widely used in integrated circuits and power devices; silicon nitride (Si3N4) has high dielectric strength and mechanical strength, and also has better chemical stability in humid environments. Therefore, it is suitable for semiconductor devices 1 operating in harsh environments, especially in high-voltage, high-humidity, or high-frequency applications. In addition, in some high-performance devices, organic insulating materials such as polyimide can be used as the first leakage protection layer 30. These materials have good flexibility, high temperature resistance, and insulation properties, making them suitable for applications with extremely high electrical performance requirements and complex environments.

[0062] According to the semiconductor device 1 of this disclosure, a first leakage protection layer 30 is provided between the metal electrode 20 and the side surface of the substrate 10. This first leakage protection layer 30 has excellent insulation properties and can form an effective barrier, preventing the metal electrode 20 from overflowing to the side surface of the substrate 10 during die bonding or wire bonding. This avoids the formation of a conductive path between the metal electrode 20 and the side surface of the substrate 10, reducing the potential risk of leakage. Furthermore, the presence of the first leakage protection layer 30 also prevents the conductive adhesive on the back of the substrate 10 from migrating upwards, further reducing the occurrence of leakage problems. This design ensures the insulation between the metal electrode 20 and the side surface of the substrate 10, effectively improving the overall stability and reliability of the device.

[0063] In some embodiments, the first leakage protection layer 30 is constructed as at least one step, meaning that the protection layer is designed not merely as a flat insulating material, but rather as having a stepped structure. This stepped structure indicates the introduction of a hierarchical difference in the first leakage protection layer 30, i.e., different regions of the first leakage protection layer 30 have different heights or thicknesses. This structural design can be formed through the deposition, photolithography, and etching processes of the insulating material. The height of the step can be designed according to the thickness of the metal electrode 20 and the device operating voltage; higher voltage devices may require a thicker insulating layer to provide stronger electrical isolation.

[0064] In some embodiments, designing the first leakage protection layer 30 as a stepped structure can increase the length of the leakage path, thereby effectively improving insulation performance. The stepped structure helps to form a stronger electric field shielding effect, thereby preventing leakage between the metal electrode 20 and the side of the substrate 10, especially when the metal electrode 20 is near the edge, the leakage prevention effect is even better. If it is only a planar insulating layer, it may not provide sufficient protection at the edge of the device, while the stepped structure can further enhance the leakage protection effect in the edge region.

[0065] Furthermore, the stepped structure design not only prevents material overflow from the metal electrode 20, but also provides better buffering and support during electrode manufacturing processes, thereby improving overall reliability. In high-voltage or high-temperature applications, the stepped structure can also help disperse stress and reduce the impact of material deformation on electrical performance.

[0066] In some embodiments, the first leakage protection layer 30 is configured as multiple steps continuously arranged along the side of the metal electrode 20 to the substrate 10. This continuous arrangement of steps means they are geometrically continuous, extending from the metal electrode 20 to the side of the substrate 10. This continuity ensures the consistency of the first leakage protection layer 30 throughout the structure, without interruptions or irregular areas. By further increasing the length of the leakage path, the insulation effect is enhanced and the risk of leakage current is reduced. A key objective of this design is to create a more complex geometric path between the electrode and the substrate 10, making it difficult for leakage current to conduct through this path.

[0067] Furthermore, the design of multiple consecutive steps can help disperse the electric field distribution. Especially in high-voltage devices, the electric field often concentrates in the edge region between the metal electrode 20 and the substrate 10, which can easily lead to breakdown or leakage. By designing multiple steps, the electric field can be dispersed and weakened layer by layer, reducing the risk of excessive concentration of the electric field in the side edge region, thereby improving the breakdown voltage and reliability of the device.

[0068] As shown in Figure 1, the first leakage protection layer 30 includes a first passivation layer 31, which is located on the surface of the substrate 10 between the metal electrode 20 and the sidewall of the substrate 10. The main function of the first passivation layer 31 is to provide electrical isolation, preventing leakage caused by electrode overflow during die bonding or wire bonding of the metal electrode 20, or by the migration of adhesive from the back of the substrate 10 to the upper surface through the sidewalls. In addition to its electrical isolation function, the passivation layer also protects the edge areas of the substrate 10 from external environmental factors such as moisture, oxidation, and chemicals, increasing the reliability and lifespan of the device.

[0069] In some embodiments, the material of the first passivation layer 31 may include silicon dioxide (SiO2), silicon nitride (Si3N4), etc. These materials have good insulation properties and can maintain chemical stability in harsh environments such as high temperature and high humidity. For specific applications, organic materials such as polyimide (PI) or other highly insulating and high-temperature resistant materials may also be selected to form the first passivation layer 31.

[0070] In some embodiments, the thickness H1 of the first passivation layer 31 satisfies: 0.5µm ≤ H1 ≤ 1.5µm. This range is not only closely related to the required electrical isolation effect of the device, but also takes into account factors such as the feasibility of the manufacturing process, cost, and application environment.

[0071] Choosing 0.5µm as the lower limit ensures that the first passivation layer 31 has sufficient thickness to provide effective electrical isolation. If the first passivation layer 31 is too thin, it may not be able to effectively prevent leakage current between the metal electrode 20 and the side of the substrate 10, especially under high voltage conditions. In addition, an excessively thin passivation layer is easily damaged during die bonding or wire bonding, affecting the overall performance of the device.

[0072] The 1.5µm upper limit takes into account the balance between process technology and cost. If the first passivation layer 31 is too thick, although the electrical isolation capability increases, it may also introduce mechanical stress or affect the packaging reliability of the device. In addition, an excessively thick first passivation layer 31 may increase the difficulty of manufacturing processes, such as making it more difficult to control the precision during photolithography and etching, affecting the dimensional consistency and yield of the device.

[0073] Therefore, the appropriate thickness of the first passivation layer 31 can ensure the effectiveness of electrical insulation performance, prevent leakage current and electric field concentration, and at the same time provide necessary support and buffer in terms of mechanical performance, reducing the risks caused by stress concentration. The thickness range (0.5um≤H1≤1.5um) fully considers the requirements of different application scenarios for insulation performance, mechanical strength and thermal stability.

[0074] As shown in Figure 1, the first leakage protection layer 30 also includes a second passivation layer 32, which is another insulating material located above the first passivation layer 31. This insulating material can be the same as or different from the first passivation layer 31, and its main function is also to provide additional electrical isolation, thereby effectively reducing the leakage current between the metal electrode 20 and the side of the substrate 10. Furthermore, the second passivation layer 32 provides additional protection for the first passivation layer 31, especially under harsh environmental conditions (such as high humidity and corrosive gases). It can effectively prevent the external environment from corroding the first passivation layer 31, thereby improving the long-term reliability of the device.

[0075] In some embodiments, the material selection for the second passivation layer 32 can be adjusted according to the specific application requirements. Commonly used materials include silicon dioxide (SiO2), silicon nitride (Si3N4), or other insulating materials. The manufacturing process of the second passivation layer 32 can be achieved through various technologies, including vapor deposition, photolithography, etching, and other processes.

[0076] In some embodiments, the thickness H2 of the second passivation layer 32 satisfies: 0.5µm ≤ H2 ≤ 1.5µm. The thickness of the second passivation layer 32 directly affects its electrical insulation performance. Choosing 0.5µm as the lower limit ensures that it has a certain effectiveness in electrical isolation. If the second passivation layer 32 is too thin, it may not be able to effectively isolate the current between the metal electrode 20 and the substrate 10, especially under high-voltage operating conditions, which may lead to an increase in leakage current. Under high-voltage conditions, a thinner passivation layer may cause the electric field to concentrate in certain areas, thereby increasing the risk of electrical breakdown. Therefore, an appropriate thickness can effectively prevent this from happening.

[0077] Furthermore, the second passivation layer 32 provides additional protection under harsh environmental conditions (such as humidity, chemical corrosion, etc.). If its thickness is insufficient, it may affect its protective function, causing the first passivation layer 31 to be susceptible to erosion from the external environment. An appropriate thickness can also help disperse stress generated during the manufacturing process, reducing the risk of damage due to thermal expansion or mechanical stress.

[0078] Furthermore, the thickness range is determined by the feasibility of photolithography and etching during manufacturing. An excessively thick passivation layer can create difficulties in process control, affecting device dimensional consistency and production yield. A suitable thickness range helps achieve better process control and improves production efficiency. Cost factors are also considered when selecting an appropriate thickness range; a thicker passivation layer increases material and processing costs, while an excessively thin layer may lead to device failure, ultimately resulting in higher repair and replacement costs.

[0079] Therefore, the design of the thickness H2 of the second passivation layer 32 within the range of 0.5um≤H2≤1.5um fully considers factors such as electrical performance, mechanical strength, manufacturing feasibility and cost, ensuring the stability and reliability of the device.

[0080] Figure 2 is a cross-sectional view of the semiconductor device 1 according to another embodiment of the present disclosure. As shown in Figure 2, in addition to designing the first leakage protection layer 30 as multiple steps, the first leakage protection layer 30 can also be arranged in a sloping manner from the metal electrode 20 to the side of the substrate 10, with the first leakage protection layer 30 forming a predetermined angle with the upper surface of the substrate 10. This design increases the isolation space between the metal electrode 20 and the side of the substrate 10, ensuring that an effective physical barrier is formed between the metal electrode 20 and the side of the substrate 10, preventing the material of the metal electrode 20 from overflowing into the substrate 10, thereby preventing leakage risk.

[0081] In some embodiments, the ramp design can be implemented through various manufacturing processes, including physical vapor deposition (PVD), chemical vapor deposition (CVD), photolithography, and etching. By adjusting process parameters, the angle and height of the ramp can be precisely controlled to meet the design requirements of different applications. The ramp design also helps simplify subsequent device fabrication processes, such as improving alignment accuracy with other layers and reducing the requirements for photolithography, thereby improving production yield and manufacturing efficiency.

[0082] In some embodiments, the thickness H3 of the first leakage protection layer 30 satisfies: 0.5µm ≤ H3 ≤ 1.5µm. The thickness range of 0.5µm to 1.5µm takes into account various factors, including electrical insulation capability, mechanical stability, stress management, and manufacturing process reliability. For the thickness range of the first leakage protection layer 30, different manufacturing processes can precisely control its thickness by adjusting parameters such as deposition time, etching time, and process temperature. Through process optimization, the thickness of the first leakage protection layer 30 can be ensured to be within the range of 0.5µm to 1.5µm, while simultaneously meeting the electrical isolation and mechanical requirements of the device design.

[0083] In some embodiments, the first leakage protection layer 30 also covers a portion of the upper surface of the substrate 10, thereby better isolating potential leakage paths between the metal electrode 20 and the substrate 10 and preventing the metal electrode 20 material from diffusing into the substrate 10 under high voltage or high temperature conditions. Specifically, in the semiconductor device 1, there is a potential difference between the metal electrode 20 and the substrate 10. Without an effective isolation layer, current may leak into the substrate 10 through sidewalls or minute defects on the surface of the substrate 10, leading to device performance degradation or failure. By covering a portion of the upper surface of the substrate 10 with the first leakage protection layer 30, this protective layer not only prevents current leakage from the metal electrode 20 to the side of the substrate 10 but also prevents current from flowing directly along the upper surface of the substrate 10, thereby effectively isolating current paths and reducing the risk of leakage.

[0084] Furthermore, the design of covering part of the substrate 10 surface helps enhance the mechanical protection of the device, especially during die bonding or soldering, the first leakage protection layer 30 can prevent mechanical stress from damaging the substrate 10. At the same time, it can also effectively prevent the substrate 10 from being exposed to the external environment, such as moisture, oxygen and corrosive chemicals, thereby improving the durability and lifespan of the device.

[0085] In some embodiments, the thickness H4 of the first leakage protection layer 30 located on the upper surface of the substrate 10 satisfies: 1µm ≤ H4 ≤ 3µm. This thickness range is determined by comprehensively considering various factors such as the requirements of the semiconductor device 1 for leakage protection, electrical insulation, mechanical protection, and process feasibility. Specifically, in the semiconductor device 1, effective electrical isolation is required between the metal electrode 20 and the substrate 10. The setting of H4 ensures that the first leakage protection layer 30 is thick enough to prevent current from leaking through the upper surface of the substrate 10. Especially in power devices, a thicker protection layer can withstand higher operating voltages and effectively reduce the risk of current leakage.

[0086] Furthermore, the first leakage protection layer 30, within its thickness range, not only provides electrical isolation but also effectively enhances the mechanical strength of the upper surface of the substrate 10, particularly during processes such as die bonding and soldering, resisting damage to the device from external forces. Especially in large-size and high-power devices, a thicker protective layer can better resist thermal and mechanical stresses caused by temperature changes. A thicker first leakage protection layer 30 also provides better protection against environmental factors such as moisture, oxygen, and chemicals, extending the device's lifespan. In harsh operating environments, such as high-temperature, high-humidity, or chemically corrosive environments, a thickness of 1µm to 3µm can provide sufficient protection to prevent damage to the substrate 10 from the external environment.

[0087] As shown in Figures 1 and 2, the semiconductor device 1 further includes at least one doped region 40 of a second conductivity type. The conductivity type of the doped region 40 is opposite to that of the substrate 10. For example, if the substrate 10 has a P-type conductivity, the doped region 40 has an N-type conductivity; conversely, if the substrate 10 has an N-type conductivity, the doped region 40 has a P-type conductivity.

[0088] In some embodiments, the doped region 40 is located within the substrate 10 and close to the upper surface of the substrate 10. This arrangement aims to form a PN junction within the device, thereby modulating the electric field distribution and effectively mitigating electric field concentration. Therefore, by introducing doped regions 40 of different conductivity types within the substrate 10, an electric field shielding layer can be formed, thereby reducing the electric field gradient within the device. This is particularly important under high-voltage conditions, helping to prevent localized breakdown caused by electric field concentration.

[0089] In some embodiments, the doped region 40 can be formed by ion implantation or diffusion processes. During manufacturing, the depth and concentration of doping can be precisely controlled to ensure that the region has the desired electrical properties.

[0090] As shown in Figures 1 and 2, the semiconductor device 1 further includes a metal dielectric layer 50. The metal dielectric layer 50 is located on the upper surface of the substrate 10 corresponding to the doped region 40. The function of the metal dielectric layer 50 is to ensure a stable ohmic contact between the metal electrode 20 and the doped region 40 of the second conductivity type. This contact can form a low-impedance electrical connection between the metal electrode 20 and the doped region 40, allowing current to flow smoothly between them. A good ohmic contact is an important condition for ensuring normal operation and high efficiency of the device.

[0091] In some embodiments, the metal dielectric layer 50 may use a variety of metal materials, including but not limited to: titanium (Ti), nickel (Ni), and platinum (Pt). Titanium (Ti) possesses good electrical conductivity, corrosion resistance, and good adhesion. Titanium (Ti) is typically used in the bottom metal dielectric layer 50 as a good interface material with the silicon substrate, maintaining good electrical properties, especially under high-temperature conditions. Nickel (Ni) has excellent electrical conductivity and corrosion resistance, and good compatibility with many metals. Nickel can also form metal silicides (NiSi) with silicon, improving the stability of ohmic contacts. Platinum has excellent electrical conductivity, high-temperature resistance, and corrosion resistance; its chemical stability allows it to maintain good performance under many extreme conditions.

[0092] In some embodiments, the metal electrode 20 is connected to the metal dielectric layer 50 through a contact hole 70, which is formed by a first leakage protection layer 30 located on the upper surface of the substrate 10. The contact hole 70 serves as a channel connecting the metal electrode 20 and the metal dielectric layer 50 and can be formed by etching or other micromachining techniques. This hole allows the metal electrode 20 to effectively contact the metal dielectric layer 50, ensuring reliable electrical connection. The size and shape of the contact hole 70 can be optimized according to specific electrical characteristics.

[0093] As shown in Figures 1-3, the semiconductor device 1 further includes a second leakage protection layer 60. One end of the second leakage protection layer 60 is connected to the first leakage protection layer 30, and the second end of the second leakage protection layer 60 extends along the side of the substrate 10 and at least to a position close to the lower surface of the substrate 10. The main function of the second leakage protection layer 60 is to effectively block the gold-tin solder (AuSn) compound that is squeezed out during the eutectic process, preventing it from leaking into the substrate 10, thereby reducing the risk of leakage.

[0094] In some embodiments, the material of the second leakage protection layer 60 may be a passivation material with a high dielectric constant, such as silicon nitride (Si3N4) or silicon dioxide (SiO2), depending on the manufacturing process and performance requirements. These materials not only have excellent insulation properties but also effectively shield electric fields, improving the overall reliability of the device.

[0095] Furthermore, the thickness of the second leakage protection layer 60 should be designed according to the operating voltage of the device. In high-voltage applications, a thicker protection layer can provide a stronger electric field shielding effect. For low-voltage applications, appropriately reducing the thickness of the protection layer can help reduce manufacturing costs while still maintaining sufficient electric field control.

[0096] In some embodiments, the second leakage protection layer 60 surrounds the lower surface of the substrate 10, forming an all-around isolation barrier, thereby enhancing the overall electrical insulation performance and making the electric field distribution between the substrate 10 and the external environment more uniform, avoiding electrical breakdown caused by local electric field concentration. The surrounding design of the second leakage protection layer 60 can also provide additional physical protection for the substrate 10, preventing external mechanical impact or chemical corrosion.

[0097] Figure 4 is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present disclosure. As shown in Figure 4, the method for fabricating a semiconductor device includes at least steps S1-S2, as follows:

[0098] S1 provides a substrate of the first conductivity type.

[0099] In some embodiments, the substrate can be of P-type or N-type conductivity. The N-type conductivity type is obtained by doping the material with impurities such as pentavalent elements such as phosphorus (P) and arsenic (As), which generates additional free electrons as majority carriers. The P-type conductivity type is obtained by doping the material with impurities such as trivalent elements such as boron (B), which generates holes as majority carriers.

[0100] In some embodiments, the substrate may be fabricated from silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs), and other materials. These materials each possess different electrical and thermal properties to meet the application requirements of specific devices.

[0101] In some embodiments, the substrate should be rigorously cleaned prior to preparation to remove surface impurities and oxide layers. Chemical solvents (such as acetone and isopropanol) and ultrasonic cleaning techniques can be used. To ensure adhesion for subsequent processes, surface roughening or leveling treatments may also be performed to enhance material bonding.

[0102] S2, a first leakage protection layer and a metal electrode are prepared on a substrate, wherein the metal electrode is located on the upper surface of the substrate, and the first leakage protection layer is located on the substrate surface between the metal electrode and the side of the substrate.

[0103] In some embodiments, the primary function of the first leakage protection layer is to form electrical isolation, prevent the metal electrode material from overflowing to the side of the substrate during die bonding or wire bonding, and avoid unnecessary conductive paths between the metal electrode and the side of the substrate, thereby effectively preventing leakage.

[0104] In some embodiments, the first leakage protection layer may be made of an insulating material with a high dielectric constant, such as silicon nitride (Si3N4) or silicon dioxide (SiO2). The selection of materials must take into account their electrical insulation properties, mechanical strength, and environmental stability to ensure their reliability under various operating conditions.

[0105] In some embodiments, the first leakage protection layer can be prepared by methods such as thermal oxidation or chemical vapor deposition (CVD). Thermal oxidation can form a uniform oxide layer on the substrate surface, while CVD can achieve high-quality thin film deposition and is suitable for surfaces with complex shapes.

[0106] In some embodiments, the metal electrodes can be made of metallic materials such as gold-tin solder (AuSn). Gold-tin solder (AuSn) has a melting point of approximately 280°C, making it suitable for high-temperature environments. Furthermore, gold-tin solder (AuSn) possesses excellent electrical conductivity and high mechanical strength, enabling efficient transmission of electrical signals, resulting in more stable devices suitable for long-term use. Therefore, gold-tin solder (AuSn) is commonly used in electronic devices requiring high reliability and durability.

[0107] In some embodiments, the metal electrodes can be fabricated using sputtering deposition or evaporation techniques to uniformly deposit metal material onto a substrate. The desired electrode shape is then formed on the metal thin film using photolithography, and excess metal is removed using development and etching techniques, leaving the desired electrode structure.

[0108] According to the method for fabricating a semiconductor device according to embodiments of this disclosure, a first leakage protection layer is formed between a metal electrode and the side surface of a substrate. This first leakage protection layer has excellent insulation properties and can form an effective barrier to prevent the metal electrode from overflowing to the side surface of the substrate during die bonding or wire bonding. This avoids the formation of a conductive path between the metal electrode and the side surface of the substrate, reducing the potential risk of leakage. Furthermore, the presence of the first leakage protection layer also prevents the upward migration of conductive adhesive on the back of the substrate, further reducing the occurrence of leakage problems. This design ensures insulation between the metal electrode and the side surface of the substrate, effectively improving the overall stability and reliability of the device.

[0109] In some embodiments, fabricating a first leakage protection layer on a substrate includes: fabricating at least one stepped structure on a substrate surface between a metal electrode and a side of the substrate. The first leakage protection layer is formed on the surface of the at least one stepped structure, the first leakage protection layer being configured as at least one step.

[0110] Specifically, constructing the first leakage protection layer as at least one step can increase the length of the leakage path, thereby effectively improving insulation performance. The stepped structure helps to form a stronger electric field shielding effect, thereby preventing leakage between the metal electrode and the side of the substrate, especially when the metal electrode is near the edge, the leakage prevention effect is even better.

[0111] In some embodiments, the stepped structure can be formed through photolithography and etching processes. Specifically, first, a layer of photoresist is coated on the substrate surface. Then, a photolithography machine is used to project the designed pattern onto the photoresist; after exposure, the photoresist undergoes a chemical reaction in specific areas; the exposed substrate is then placed in a developing solution, and the unexposed photoresist is removed, forming the desired pattern; then, the portions of the substrate surface not protected by the photoresist are removed using a wet or dry etching process. This process can form a stepped shape on the substrate; after etching, the residual photoresist is removed, leaving a substrate with a stepped structure.

[0112] In some embodiments, forming a first leakage protection layer on the surface of at least one stepped structure includes: forming a first passivation layer on the surface of at least one stepped structure, forming a second passivation layer on the first passivation layer, wherein the first passivation layer and the second passivation layer constitute the first leakage protection layer.

[0113] In some embodiments, the first passivation layer and the second passivation layer can be fabricated by methods such as thermal oxidation or chemical vapor deposition (CVD). By superimposing the two passivation layers, the first leakage protection layer has good electrical isolation capability, which can effectively prevent the metal electrode from overflowing to the side of the substrate during the die bonding or wire bonding process, thereby reducing the risk of leakage.

[0114] In some embodiments, fabricating a first leakage protection layer on a substrate further includes forming a sloped first leakage protection layer on the substrate surface between the metal electrode and the side of the substrate, wherein the first leakage protection layer is at a predetermined angle to the upper surface of the substrate.

[0115] The ramp design increases the isolation space between the metal electrode and the side of the substrate, ensuring an effective physical barrier between the metal electrode and the side of the substrate, preventing the metal electrode material from overflowing into the substrate and thus creating a risk of leakage.

[0116] In some embodiments, the ramp design can be achieved through various manufacturing processes, including photolithography, etching, thermal oxidation, and chemical vapor deposition (CVD). During etching, the etching time and rate need to be precisely controlled to ensure that the angle and shape of the ramp meet the design requirements.

[0117] In some embodiments, the first leakage protection layer further covers a portion of the upper surface of the substrate, and the method further includes: preparing at least one doped region of a second conductivity type in the substrate and near the upper surface of the substrate; preparing a metal dielectric layer on the upper surface of the substrate in a region corresponding to the doped region, wherein a metal electrode is connected to the metal dielectric layer through a contact hole, the contact hole being constructed by the first leakage protection layer located on the upper surface of the substrate.

[0118] In some embodiments, the second conductivity type can be P-type or N-type. If the first conductivity type is P-type, then the second conductivity type is N-type; conversely, if the first conductivity type is N-type, then the second conductivity type is P-type. The doped region can be formed by ion implantation or diffusion processes, which can effectively control the depth and concentration of doping, thereby ensuring that the region has the desired electrical properties.

[0119] In some embodiments, the material of the metal dielectric layer can be selected from metals with good conductivity and chemical stability, such as titanium (Ti), nickel (Ni), and platinum (Pt). The metal dielectric layer can be formed using techniques such as chemical vapor deposition (CVD) or physical vapor deposition (PVD). These methods ensure uniform deposition of the metal dielectric layer and avoid the problem of poor local conductivity.

[0120] In some embodiments, the contact holes can be formed by processes such as photolithography and etching to ensure a good connection between the metal electrode and the metal dielectric layer, thereby ensuring smooth current flow.

[0121] In some embodiments, the method of fabricating a semiconductor device further includes: fabricating a second leakage protection layer on the side of a substrate, one end of the second leakage protection layer being connected to a first leakage protection layer, and a second end of the second leakage protection layer extending along the side of the substrate to a position close to the lower surface of the substrate.

[0122] In some embodiments, the material of the second leakage protection layer may be selected from materials with good insulation properties, high temperature resistance and chemical corrosion resistance, such as silicon dioxide (SiO2), silicon nitride (Si3N4), etc.

[0123] In some embodiments, the second leakage protection layer can be formed using a process similar to that of the first leakage protection layer, such as chemical vapor deposition (CVD) or physical vapor deposition (PVD). These techniques ensure uniform coverage of the insulating layer on the substrate sides.

[0124] In some embodiments, the second leakage protection layer surrounds the lower surface of the substrate. This means that the entire lower surface of the substrate is covered by the second leakage protection layer, resulting in a more robust leakage protection structure for the entire device. Especially for the edges and back surfaces of semiconductor devices, this fully enclosed leakage protection design effectively prevents leakage caused by concentrated electric fields. Furthermore, during fabrication, the thickness and uniformity of the second leakage protection layer can be optimized by adjusting etching and deposition process parameters.

[0125] Taking the semiconductor device shown in Figure 1 as an example, the fabrication process of the semiconductor device may include the following steps:

[0126] First, a silicon substrate of a first conductivity type is provided. The substrate can be an N-type or a P-type silicon substrate. The N-type silicon substrate is obtained by doping with phosphorus impurities, and the P-type silicon substrate is obtained by doping with boron impurities. The thickness of the substrate is 150 μm.

[0127] Second, photoresist is coated on the substrate surface, and then the desired pattern is created through exposure and development methods, so that subsequent etching can be performed in appropriate areas to form a specific shape.

[0128] Third, using chemical substances, the pattern created in the above photolithography steps is etched on the substrate surface to form at least one step structure on the substrate surface between the metal electrode and the side of the substrate. This structure provides support for the subsequent formation of the first passivation layer, extends the path from the metal electrode to the side of the substrate, and thus forms a barrier between the metal electrode and the side of the substrate to prevent it from overflowing to the side of the substrate and causing leakage.

[0129] Fourth, use a chemical cleaning solution to clean the substrate and remove organic and inorganic impurities from the surface.

[0130] Fifth, a first passivation layer is formed on the side of the substrate by thermal oxidation or chemical vapor deposition. The first passivation layer can be silicon dioxide (SiO2), silicon nitride (Si3N4), or other insulating materials, and its main function is to provide moisture protection and leakage protection. The thickness of the first passivation layer is 0.5um to 1.5um.

[0131] Sixth, photoresist is coated on the surface of the first passivation layer, and then the required pattern is created by exposure and development methods so that contact holes can be formed in the appropriate areas in the future.

[0132] Seventh, under the guidance of the photolithography pattern in the above steps, the surface of the first passivation layer is etched with chemical gases (such as trifluoromethyl (CF3), sulfur hexafluoride (SF6) and oxygen (O2)) to form contact holes.

[0133] Eighth, at high temperature, impurities of a second conductivity type are introduced into the contact holes to form two symmetrically distributed doped regions of the second conductivity type. If the substrate's conductivity type is N-type, the doped regions are formed into P-type doped regions by doping with boron impurities; if the substrate's conductivity type is P-type, the doped regions are formed into N-type doped regions by doping with arsenic or phosphorus impurities. The thickness of the doped regions is 3µm to 6µm.

[0134] Ninth, photoresist is coated on the surface of the oxide layer (first passivation layer) of the doped region of the second conductivity type, and then the desired pattern is created by exposure and development methods so that contact holes can be formed in the appropriate area in the future.

[0135] Tenth, under the guidance of the photolithography pattern in the above steps, the oxide layer (first passivation layer) of the doped region is etched with chemical gases (such as trifluoromethyl (CF3), sulfur hexafluoride (SF6) and oxygen (O2)) to form contact holes again.

[0136] Eleventh, deposit metal within the contact holes to form a metallic dielectric layer. The metallic dielectric layer can be made of materials such as titanium (Ti), nickel (Ni), or platinum (Pt), which possess excellent electrical conductivity, corrosion resistance, and adhesion.

[0137] Twelfth, a second passivation layer is formed on the substrate surface using thermal oxidation or chemical vapor deposition (CVD). The second passivation layer can be silicon dioxide (SiO2), silicon nitride (Si3N4), or other insulating materials, serving as moisture protection and leakage current protection. The thickness of the second passivation layer is set between 0.5µm and 1.5µm to ensure sufficient insulation while also considering process feasibility.

[0138] Thirteenth, photoresist is coated on the surface of the newly generated passivation layer, and then the required pattern is created by exposure and development methods so that contact holes can be formed in the appropriate areas in the future.

[0139] Fourteenth, according to the photolithography pattern, holes are made on the surface of the second passivation layer through an etching process to form contact holes again for subsequent deposition of metal electrodes.

[0140] Fifteenth, metal deposition is performed inside the contact hole and on the surface of the second passivation layer to form a metal electrode; the material of the metal electrode can be gold-tin solder (AuSn), and the thickness of the metal electrode is 2um to 5um; in practical applications, conductive connection with the substrate is achieved through a eutectic process.

[0141] Sixteenth, the entire silicon wafer is cut into individual devices using laser cutting technology. This process ensures that each device can be individually tested and packaged.

[0142] Seventeenth, a second leakage protection layer is formed by depositing silicon dioxide (SiO2) or silicon nitride (Si3N4) material on the side of the substrate through evaporation deposition. In practical applications, this layer effectively blocks the overflow of gold-tin solder (AuSn) compound during the eutectic process, preventing it from overflowing into the substrate and causing leakage.

[0143] Taking the semiconductor device shown in Figure 2 as an example, the fabrication process of the semiconductor device may include the following steps:

[0144] First, a silicon substrate of a first conductivity type is provided. The substrate can be an N-type or a P-type silicon substrate. The N-type silicon substrate is obtained by doping with phosphorus impurities, and the P-type silicon substrate is obtained by doping with boron impurities. The thickness of the substrate is 150 μm.

[0145] Second, photoresist is coated on the substrate surface, and then the desired pattern is created through exposure and development methods, so that subsequent etching can be performed in appropriate areas to form a specific shape.

[0146] Third, using chemical substances, the pattern created in the photolithography steps is etched onto the substrate surface to form a sloped first leakage protection layer on the substrate surface between the metal electrode and the side of the substrate. The first leakage protection layer is at a predetermined angle to the upper surface of the substrate. This increases the isolation space between the metal electrode and the side of the substrate, forming a barrier between the metal electrode and the side of the substrate in practical applications, preventing leakage from overflowing into the substrate.

[0147] Fourth, use a chemical cleaning solution to clean the substrate and remove organic and inorganic impurities from the surface.

[0148] Fifth, a first leakage protection layer is formed on the side of the substrate by thermal oxidation or chemical vapor deposition. The first leakage protection layer can be silicon dioxide (SiO2), silicon nitride (Si3N4), or other insulating materials, and its main function is to provide moisture protection and leakage protection. The thickness of the first leakage protection layer is 0.5um to 1.5um.

[0149] Sixth, photoresist is coated on the surface of the first leakage protection layer, and then the required pattern is created by exposure and development methods so that contact holes can be formed in the appropriate area in the future.

[0150] Seventh, under the guidance of the photolithography pattern in the above steps, the surface of the first leakage protection layer is etched with chemical gases (such as trifluoromethyl (CF3), sulfur hexafluoride (SF6) and oxygen (O2)) to form contact holes.

[0151] Eighth, at high temperature, impurities of a second conductivity type are introduced into the contact holes to form two symmetrically distributed doped regions of the second conductivity type. If the substrate's conductivity type is N-type, the doped regions are formed into P-type doped regions by doping with boron impurities; if the substrate's conductivity type is P-type, the doped regions are formed into N-type doped regions by doping with arsenic or phosphorus impurities. The thickness of the doped regions is 3µm to 6µm.

[0152] Ninth, photoresist is coated on the oxide layer (first leakage protection layer) of the doped region of the second conductivity type, and then the required pattern is made by exposure and development methods so that the contact hole can be formed by opening in the appropriate area.

[0153] Tenth, under the guidance of the photolithography pattern in the above steps, the oxide layer (first leakage protection layer) of the doped region is etched with chemical gases (such as trifluoromethyl (CF3), sulfur hexafluoride (SF6) and oxygen (O2)) to form contact holes again.

[0154] Eleventh, deposit metal within the contact holes to form a metallic dielectric layer. The metallic dielectric layer can be made of materials such as titanium (Ti), nickel (Ni), or platinum (Pt), which possess excellent electrical conductivity, corrosion resistance, and adhesion.

[0155] Twelfth, a first leakage protection layer with a thickness of 0.5um to 1.5um is further generated on the substrate surface by thermal oxidation or chemical vapor deposition (CVD).

[0156] Thirteenth, photoresist is coated on the surface of the first leakage protection layer, and then the required pattern is created by exposure and development methods so that contact holes can be formed in the appropriate area in the future.

[0157] Fourteenth, according to the photolithography pattern, holes are made on the surface of the first leakage protection layer through an etching process to re-form contact holes for subsequent deposition of metal electrodes.

[0158] Fifteenth, metal deposition is performed inside the contact hole and on the surface of the first leakage protection layer to form a metal electrode. The metal electrode material can be gold-tin solder (AuSn), and the thickness of the metal electrode is 2µm to 5µm. In practical applications, conductive connection with the substrate is achieved through a eutectic process.

[0159] Sixteenth, laser cutting technology is used to cut the entire silicon wafer into individual devices. This process ensures that each device can be individually tested and packaged.

[0160] Seventeenth, a second leakage protection layer is formed by depositing silicon dioxide (SiO2) or silicon nitride (Si3N4) material on the side of the substrate through evaporation deposition. In practical applications, this layer effectively blocks the overflow of gold-tin solder (AuSn) compound during the eutectic process, preventing it from overflowing into the substrate and causing leakage.

[0161] In summary, the semiconductor devices of Figures 1 and 2 in this embodiment can be fabricated through multiple photolithography, etching, deposition, and evaporation coating processes.

[0162] The electronic device 110 of this disclosure embodiment will now be described with reference to FIG5.

[0163] Figure 5 is a block diagram of an electronic device 110 according to an embodiment of the present disclosure. As shown in Figure 5, the electronic device 110 includes the semiconductor device 1 described in the above embodiment.

[0164] In some embodiments, electronic device 110 may include, but is not limited to, smart electronic products (such as smartphones, tablets, smartwatches, and laptops), automotive electronic systems, communication equipment (such as base stations, switches, and routers), industrial equipment (such as automation equipment, robots, and controllers), and medical devices (such as CT scanners, ultrasound equipment, and heart rate monitors).

[0165] The electronic device 110 according to the present disclosure, by employing the semiconductor device 1 described in the above embodiments, achieves effective isolation between the metal electrode 20 and the side of the substrate 10, reduces the potential risk of leakage current, and thereby improves the stability and reliability of the device.

[0166] As shown in Figure 5, the electronic device 110 includes a light-emitting diode (LED) light source 2. The LED light source 2, as a highly efficient and long-life light source, is widely used in various electronic devices 110, such as displays, lighting equipment, and communication equipment. The high brightness and low power consumption characteristics of the LED light source 2 make it a common choice in modern electronic devices 110.

[0167] In some embodiments, the semiconductor device 1 includes a transient voltage suppression diode (TVS). A transient voltage suppression diode is a device specifically designed to protect electronic circuits from transient high voltages (such as electrostatic discharge, surge current, or lightning strikes). When a transient overvoltage occurs in a circuit, the TVS diode can quickly turn on and absorb energy, preventing the voltage from rising to a level that could damage the equipment. TVS diodes are characterized by their very fast response speed, making them suitable for applications requiring protection of sensitive components (such as light-emitting diodes).

[0168] In some embodiments, the light-emitting diode light source 2 further includes a light-emitting diode and a substrate. The light-emitting diode is located on the substrate, and a transient suppression diode is flip-chip connected to the substrate in parallel with the light-emitting diode. Specifically, under normal conditions, the transient suppression diode exhibits high impedance and can be considered an open circuit (ideal state), which does not affect the operation of the light-emitting diode. When subjected to a transient high-voltage surge, the transient suppression diode immediately utilizes the avalanche breakdown effect of the PN junction to change its impedance from high impedance to low impedance. The surge generated by the high voltage is shunted by the transient suppression diode, effectively protecting the light-emitting diode.

[0169] In some embodiments, flip-chip bonding of a transient voltage suppressor (VTS) diode to the substrate means that the VTS diode directly contacts the pads on the substrate using flip-chip bonding technology, achieving a more compact and low-inductance connection, further improving the circuit's response speed and electrical performance. Specifically, flip-chip bonding is an advanced packaging technology that shortens the electrical path and reduces package size by inverting the chip and directly bonding it to the substrate. The main advantages of this technology are reduced parasitic inductance and resistance, and improved device response speed and heat dissipation. Using flip-chip bonding for VTS diodes helps improve their response speed in circuits, thereby more effectively protecting the light-emitting diode.

[0170] In some embodiments, the substrate is used to support the light-emitting diode and the transient voltage suppressor diode. The substrate material can be a material with good thermal conductivity, such as ceramic, metal, or composite material. The substrate design should ensure a stable connection between the light-emitting diode and the transient voltage suppressor diode, and provide good heat dissipation and electrical performance.

[0171] The vehicle 100 of this disclosure embodiment will now be described with reference to Figures 6 and 7.

[0172] Figure 6 is a block diagram of a vehicle 100 according to an embodiment of the present disclosure. As shown in Figure 6, the vehicle 100 includes the semiconductor device 1 described in the above embodiment. The semiconductor device 1 may involve electronic control units (ECUs), sensors, and power management modules, etc. These devices are widely used in various subsystems of the vehicle 100, such as the powertrain system, braking system, body control system, and infotainment system. The semiconductor device 1 design can achieve more precise current control, reduced power consumption, and leakage protection functions in the vehicle 100. These technical advantages can make the electronic system of the vehicle 100 more reliable and efficient.

[0173] Figure 7 is a block diagram of a vehicle 100 according to another embodiment of the present disclosure. As shown in Figure 7, the vehicle 100 includes the electronic device 110 described in the above embodiment. The electronic device 110 includes a light-emitting diode (LED) light source 2 and a transient voltage suppressor diode (VTDS). It has a wide range of applications in the vehicle 100, particularly in parts related to the vehicle 100's lighting system, signal system, and display system. For example, the LED light source 2 is widely used in the vehicle 100's headlights, taillights, turn signals, and interior lighting, while the VTDS prevents damage to the LED due to voltage spikes or transient currents. This design not only improves the electrical stability of the vehicle 100 but also extends the lifespan of the LED light source 2.

[0174] According to the vehicle 100 of this disclosure, by employing the semiconductor device 1 or electronic device 110 described in the above embodiments, the first leakage protection layer 30 inside has excellent insulation properties, which can form an effective isolation protection, thereby preventing the metal electrode 20 from overflowing to the side of the substrate 10 during die bonding or wire bonding. This avoids the formation of a conductive path between the metal electrode 20 and the side of the substrate 10, reducing the potential risk of leakage. In addition, the presence of the first leakage protection layer 30 can also prevent the conductive adhesive on the back of the substrate 10 from migrating upwards, further reducing the occurrence of leakage problems. This design ensures the insulation between the metal electrode 20 and the side of the substrate 10, thereby improving the overall performance of the vehicle 100.

[0175] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example.

[0176] Although embodiments of this disclosure have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this disclosure, the scope of which is defined by the claims and their equivalents.

Claims

1. A semiconductor device (1), characterized by include: Substrate (10) of the first conductivity type; A metal electrode (20) is located on the upper surface of the substrate (10); and A first leakage protection layer (30) is located on the surface of the substrate (10) between the metal electrode (20) and the side of the substrate (10).

2. The semiconductor device (1) according to claim 1, characterized in that The first leakage protection layer (30) is constructed as at least one step.

3. The semiconductor device (1) according to claim 2, characterized in that The first leakage protection layer (30) is constructed as a plurality of steps, which are continuously arranged along the side of the metal electrode (20) to the substrate (10).

4. The semiconductor device (1) according to claim 2 or 3, characterized in that The first leakage protection layer (30) includes: A first passivation layer (31) is located on the surface of the substrate (10) between the metal electrode (20) and the side of the substrate (10).

5. The semiconductor device (1) according to claim 4, characterized in that The thickness H1 of the first passivation layer (31) satisfies: 0.5um≤H1≤1.5um.

6. The semiconductor device (1) according to claim 4 or 5, characterized in that The first leakage protection layer (30) also includes: A second passivation layer (32) is located on the first passivation layer (31).

7. The semiconductor device (1) according to claim 6, characterized in that The thickness H2 of the second passivation layer (32) satisfies: 0.5um≤H2≤1.5um.

8. The semiconductor device (1) according to claim 1, characterized in that The first leakage protection layer (30) is sloped from the metal electrode (20) to the side of the substrate (10), and the first leakage protection layer (30) is at a predetermined angle to the upper surface of the substrate (10).

9. The semiconductor device (1) according to claim 8, characterized in that The thickness H3 of the first leakage protection layer (30) satisfies: 0.5um≤H3≤1.5um.

10. The semiconductor device (1) according to any of claims 1 to 9, characterized in that The first leakage protection layer (30) also covers a portion of the upper surface of the substrate (10).

11. The semiconductor device (1) according to claim 10, characterized in that The thickness H4 of the first leakage protection layer (30) located on the upper surface of the substrate (10) satisfies: 1um≤H4≤3um.

12. The semiconductor device (1) according to claim 10 or 11, characterized in that The semiconductor device (1) further includes: At least one doped region (40) of a second conductivity type, the doped region (40) being located within the substrate (10) and close to the upper surface of the substrate (10).

13. The semiconductor device (1) according to claim 12, characterized in that The semiconductor device (1) further includes: A metal dielectric layer (50) is located on the upper surface of the substrate (10) in the region corresponding to the doped region (40); The metal electrode (20) is connected to the metal dielectric layer (50) through a contact hole (70), which is formed by the first leakage protection layer (30) located on the upper surface of the substrate (10).

14. The semiconductor device (1) according to any of claims 1 to 13, characterized in that The semiconductor device (1) further includes: A second leakage protection layer (60) is provided, one end of which is connected to the first leakage protection layer (30), and the second end of the second leakage protection layer (60) extends along the side of the substrate (10) and at least to a position close to the lower surface of the substrate (10).

15. The semiconductor device (1) according to claim 14, characterized in that The second leakage protection layer (60) surrounds the lower surface of the substrate (10).

16. A method of fabricating a semiconductor device, characterized by, include: Provide a substrate of the first conductivity type; and A first leakage protection layer and a metal electrode are fabricated on the substrate, wherein the metal electrode is located on the upper surface of the substrate, and the first leakage protection layer is located on the substrate surface between the metal electrode and the side surface of the substrate.

17. The method of claim 16, wherein, Fabricating a first leakage protection layer on the substrate includes: At least one stepped structure is formed on the substrate surface between the metal electrode and the side of the substrate; and The first leakage protection layer is formed on the surface of the at least one stepped structure, wherein the first leakage protection layer is constructed as at least one step.

18. The method of claim 17, wherein, Forming the first leakage protection layer on the surface of the at least one stepped structure includes: A first passivation layer is formed on the surface of the at least one stepped structure; and A second passivation layer is formed on the first passivation layer, and the first passivation layer and the second passivation layer constitute the first leakage protection layer.

19. The method of claim 16, wherein, Fabricating a first leakage protection layer on the substrate includes: A sloped first leakage protection layer is formed on the substrate surface between the metal electrode and the side of the substrate, and the first leakage protection layer is at a predetermined angle to the upper surface of the substrate.

20. The method of any one of claims 16-19, wherein, The first leakage protection layer also covers a portion of the upper surface of the substrate, and the method further includes: At least one doped region of a second conductivity type is formed within the substrate and near the upper surface of the substrate; and A metal dielectric layer is prepared on the upper surface of the substrate in the region corresponding to the doped region, wherein the metal electrode is connected to the metal dielectric layer through a contact hole, the contact hole being constructed from the first leakage protection layer located on the upper surface of the substrate.

21. The method of any one of claims 16-20, wherein, The method further includes: A second leakage protection layer is formed on the side of the substrate, one end of the second leakage protection layer is connected to the first leakage protection layer, and the second end of the second leakage protection layer extends along the side of the substrate to a position close to the lower surface of the substrate.

22. The method of claim 21, wherein, The second leakage protection layer surrounds the lower surface of the substrate.

23. An electronic device (110), characterized by The electronic device (110) includes the semiconductor device (1) according to any one of claims 1-15.

24. The electronic device (110) according to claim 23, characterized by The electronic device (110) includes a light-emitting diode light source (2).

25. The electronic device (110) according to claim 24, characterized in that, The semiconductor device (1) includes a transient suppression diode; and The light-emitting diode light source (2) also includes a light-emitting diode and a substrate, wherein the light-emitting diode is located on the substrate, and the transient suppression diode is flip-chip connected to the substrate to be connected in parallel with the light-emitting diode.

26. A vehicle (100), characterized in that It includes the semiconductor device (1) according to any one of claims 1-15, or the electronic device (110) according to any one of claims 23-25.

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