Back contact cell, photovoltaic module and method for manufacturing back contact cell

Abstract

The present application relates to the technical field of back contact cells. Disclosed are a back contact cell, a photovoltaic module and a method for manufacturing the back contact cell, which can solve the problems of high defect risk and high current leakage risk between an N-type doped layer and a P-type doped layer. The back contact cell comprises a semiconductor substrate, a first surface of the semiconductor substrate comprising a first region, a second region and a third region located between the first region and the second region; a first doped semiconductor layer is disposed in the first region; a second doped semiconductor layer, which has a conductivity type opposite to that of the first doped semiconductor layer, is disposed in the second region. The resistivity of the surface layer of at least a portion of the surface of the semiconductor substrate located in the third region is greater than 20 ohm·cm. H1+H2+W is greater than or equal to 4 μm and less than or equal to 300 μm, H1 being the height difference between the surface of the third region and the surface of the first region, H2 being the height difference between the surface of the third region and the surface of the second region, and W being the width of the third region.

Description

Manufacturing methods of back contact cells, photovoltaic modules, and back contact cells Technical Field

[0001] This application relates to the field of back contact battery technology, and more particularly to a back contact battery, a photovoltaic module, and a method for manufacturing a back contact battery. Background Technology

[0002] A back-contact solar cell refers to a solar cell where both the emitter and the metal contact are located on the back of the cell, with no metal electrodes obstructing the front. Compared to solar cells with obstructed front surfaces, back-contact solar cells have higher short-circuit current and photoelectric conversion efficiency, and are one of the current technological directions for achieving high-efficiency crystalline silicon solar cells.

[0003] In existing technologies, back-contact batteries have N-type doped layers and P-type doped layers. The defects between the N-type and P-type doped layers are relatively large, resulting in a high risk of leakage. Summary of the Invention

[0004] The purpose of this application is to provide a back contact battery, a photovoltaic module, and a method for manufacturing a back contact battery, so as to reduce the risk of leakage and reduce safety hazards.

[0005] To achieve the above objectives, in a first aspect, this application provides a back contact battery. The back contact battery includes a semiconductor substrate. The semiconductor substrate includes opposing first and second surfaces. The first surface includes a first region, a second region, and a third region located between the first and second regions. A first doped semiconductor layer is disposed in the first region, and a second doped semiconductor layer is disposed in the second region. The first and second doped semiconductor layers have opposite conductivity types. The resistivity of a surface layer on at least a portion of the surface of the semiconductor substrate located in the third region is greater than 20 ohm·cm; and H1+H2+W is greater than or equal to 4 μm and less than or equal to 300 μm; wherein H1 is the height difference between the surface of the third region and the surface of the first region, H2 is the height difference between the surface of the third region and the surface of the second region, and W is the width of the third region.

[0006] Compared with existing technologies, in the back contact battery provided in this application, the resistivity of the surface layer of at least a portion of the semiconductor substrate in the third region is greater than 20 ohm·cm. Combined with the shortest surface distance L (i.e., H1+H2+W) between the first and second regions being greater than or equal to 4 μm and less than or equal to 300 μm, this reduces the leakage risk between the first doped semiconductor layer in the first region and the second doped semiconductor layer in the second region, thereby reducing safety hazards and improving the photoelectric conversion efficiency of the back contact battery. The resistivity of the surface layer in the third region is set within a large range, which can suppress the lateral movement of charge carriers at the surface of the third region and reduce the charge carrier concentration at that surface, thus ensuring the safety of the leakage risk between the first and second doped semiconductor layers. Furthermore, the shortest surface distance L between the first and second regions being greater than or equal to 4 μm and less than or equal to 300 μm can increase the proportion of the first and second regions, thereby increasing the proportion of the first doped semiconductor layer in the first region and the second doped semiconductor layer in the second region, and ultimately improving the photoelectric conversion efficiency of the back contact battery. Furthermore, due to the high resistivity of the surface layer of the semiconductor substrate corresponding to the third region, it is greatly affected by the electric field of the first or second doped semiconductor layer, resulting in a relatively high electric field strength. Photogenerated carriers generated near the surface of the third region can be effectively separated. Therefore, although the high resistivity of the third region surface affects carrier transport, its additional advantage allows for improved battery efficiency, especially when the overall width of the third region is small. Carriers generated in the semiconductor substrate in the third region are primarily transported within the first and second doped semiconductor layers. Based on this, in this application, the shortest surface distance L between the first and second regions is less than or equal to 300 μm to ensure that carriers generated in the semiconductor substrate in the third region can be effectively collected by the first and second doped semiconductor layers, thereby ensuring the conversion efficiency of the back-contact battery. On the other hand, although the surface layer of the third region has high resistivity, setting the surface distance L between the first and second regions too small would pose a significant risk of leakage and unpredictable risks due to process variations. Therefore, the matched shortest surface distance L is greater than or equal to 4 μm.

[0007] In one implementation, H1+H2+W is greater than or equal to 40μm and less than or equal to 300μm. Using the above technical solution, on the one hand, the third region retains a larger process window, improving process tolerance; on the other hand, more light is absorbed through the third region, increasing the back-side power generation and improving the bifaciality.

[0008] In one implementation, along the direction from the first region to the second region, the surfaces of the first region, the second region, and the third region are approximately on the same plane; H1 is approximately 0, H2 is approximately 0, and 4μm ≤ W ≤ 300μm. Having all three regions at the same height reduces corrosion of the silicon substrate and maximizes the utilization of the thickness of the silicon wafer used in the battery. A thicker wafer allows for a longer light propagation path within the battery, resulting in more current and higher battery efficiency. Furthermore, having all three regions at the same height simplifies the battery fabrication process. For example, a full-surface poly layer can be fabricated first, followed by ion implantation to directly form patterned P- and N-regions. Finally, the third region can be etched away, requiring only the third region to be removed. This simplifies the process and increases battery efficiency.

[0009] In one implementation, along the direction from the second face to the first face, the surface of the first region is higher than the surface of the third region.

[0010] When employing the above technical solution, since the surfaces of the first, second, and third regions are all located on the same plane, and the surface of the first region is higher than the surface of the third region, there is a height difference H1 between the surfaces of the first and third regions. In this case, the shortest surface distance L (i.e., H1 + H2 + W) between the first and second regions is greater than the width W of the third region. Therefore, while ensuring that the shortest surface distance L between the first and second regions remains constant, the width W of the third region can be reduced. At this point, while ensuring the isolation of the first and second doped semiconductor layers, the proportion of the first and second regions can be further increased, thereby further increasing the proportion of the first doped semiconductor layer in the first region and the second doped semiconductor layer in the second region, and further improving the photoelectric conversion efficiency of the back contact battery.

[0011] In one implementation, 0μm < H1 ≤ 20μm.

[0012] In one implementation, along the direction from the second face to the first face, the surface of the second region is higher than the surface of the third region.

[0013] With the above technical solution, compared to the surfaces of the first region, the second region, and the third region being located on the same plane, the width W of the third region can be further reduced while keeping the shortest surface distance L between the first and second regions constant. In this case, while ensuring the isolation of the first and second doped semiconductor layers, the proportion of the first and second regions can be further increased, thereby further increasing the proportion of the first doped semiconductor layer in the first region and the second doped semiconductor layer in the second region, and thus further improving the photoelectric conversion efficiency of the back contact battery.

[0014] In one implementation, 0μm < H2 ≤ 20μm.

[0015] In one implementation, the semiconductor substrate located in the first region further includes a first sidewall, which is connected to both the surface of the third region and the surface of the first region. The first sidewall includes a surface that is inclined relative to the first surface; or, the first sidewall is perpendicular to the first surface.

[0016] When using the above technical solution, the inclined edge of the third region has the following advantages: it reduces the sharp corners caused by right-angled sections and the bottom of the third region, which are actually difficult to passivate. Therefore, the slope can effectively avoid the occurrence of such structures, thereby improving the passivation effect of the third region of the battery. In the case of a deeper third region, the inclined slope can greatly reduce the stress problem of silicon wafer caused by the deep third region, thereby maintaining a low breakage rate even in the case of a deep third region. In contrast, in a straight third region without a slope, the stress is concentrated at the junction of the bottom of the third region and the cliff, resulting in a very high breakage rate.

[0017] In one implementation, the semiconductor substrate located in the second region further includes a second sidewall, which is connected to the surface of the third region and the surface of the second region, respectively. The second sidewall includes a surface that is inclined relative to the first surface; or, the second sidewall is perpendicular to the first surface.

[0018] In one implementation, when both the first sidewall and the second sidewall include surfaces that are inclined relative to the first surface, the horizontal distance between the first sidewall and the second sidewall gradually decreases along the direction from the first surface to the second surface.

[0019] Based on the preceding description, this facilitates better film coverage of the first and second sidewalls during the subsequent formation of the film layer on the surface of the third region. This prevents unfilled gaps at the boundaries between the first and third regions, or between the second and third regions, reducing the number of defects on the first side of the back contact cell and improving the formation quality of the film layer at these boundaries. Furthermore, in the case of a deeper third region, the sloping ramp can significantly reduce the stress on the silicon wafer caused by the depth of the third region, thus maintaining a low breakage rate even in a deep third region. In contrast, a straight, unsloping third region results in stress concentration at the interface between the bottom of the third region and the cliff face, leading to a very high breakage rate.

[0020] In one implementation, the back contact battery sequentially includes a first region, a third region, a second region, and a third region, that is, the back contact battery includes alternating first and second regions spaced apart by the third region, the width of the back contact battery is greater than or equal to 500 μm and less than or equal to 2000 μm; the ratio of the width of at least one third region to the width of the back contact battery is less than or equal to 0.2%; the width direction of the back contact battery and the width direction of the third region are both consistent with the direction from the first region to the second region.

[0021] When employing the above technical solution, since the ratio of the width of the third region to the width of the back contact cell is less than or equal to 0.2%, the ratio of the sum of the widths of the first and second regions to the width of the back contact cell is greater than or equal to 99.8%. Therefore, the total proportion of the first and second regions is larger than that of the third region, resulting in a larger total proportion of the first doped semiconductor layer located in the first region and the second doped semiconductor layer located in the second region. This increases the amount of charge carriers collected by the back contact cell, thereby improving its photoelectric conversion efficiency.

[0022] In one implementation, the back contact battery further includes a first electrode and a second electrode. The first electrode is electrically connected to a first doped semiconductor layer, and the second electrode is electrically connected to the second doped semiconductor layer. The first electrode includes a contact portion that directly contacts the first doped semiconductor layer and a main body portion that is away from the first doped semiconductor layer. The second electrode includes a contact portion that directly contacts a second doped semiconductor layer and a main body portion that is away from the second doped semiconductor layer. The distance L1 between the contact portion of the first electrode and the third region is greater than or equal to 80 μm and less than or equal to 500 μm, and the extending direction of the distance L1 is consistent with the direction from the first region to the second region; and / or, the distance L2 between the contact portion of the second electrode and the third region is greater than or equal to 80 μm and less than or equal to 500 μm, and the extending direction of the distance L2 is consistent with the direction from the first region to the second region.

[0023] When the above technical solution is adopted, L1 and L2, within the aforementioned value range, not only ensure the strong connection between the first electrode and the first doped semiconductor layer (or the second electrode and the second doped semiconductor layer), but also improve the bonding force between the electrode and the doped semiconductor layer. Simultaneously, compared to cases with a spacing of less than 80 μm, current transmission efficiency can be improved, thereby increasing the conversion efficiency of the back contact battery.

[0024] In one implementation, the ratio of the width of the first doped semiconductor layer to the spacing L1 is greater than or equal to 2, and the width direction of the first doped semiconductor layer is consistent with the direction from the first region to the second region; and / or, the ratio of the width of the second doped semiconductor layer to the spacing L2 is greater than or equal to 2, and the width direction of the second doped semiconductor layer is consistent with the direction from the first region to the second region.

[0025] In one implementation, the distance between the main body of the first electrode and the third region is L3, L3≤L1, and the direction of extension of the distance L3 is consistent with the direction from the first region to the second region; and / or, the distance between the main body of the second electrode and the third region is L4, L4≤L2, and the direction of extension of the distance L4 is consistent with the direction from the first region to the second region.

[0026] When the distance between the contact portion of the electrode and the third region is greater than the distance between the main body of the electrode and the third region, the actual electrical distance between the first electrode and the second electrode can be further increased, thereby further reducing leakage current. At the same time, it can also achieve uniform collection of charge carriers and avoid heat loss caused by local overheating.

[0027] In one implementation, the ratio of the width W of the third region to the width of the first doped semiconductor layer is less than or equal to 35%; and / or, the ratio of the width W of the third region to the width of the second doped semiconductor layer is less than or equal to 35%.

[0028] By adopting the above technical solution, the proportion of the first region and the second region can be increased while ensuring the isolation of the first doped semiconductor layer and the second doped semiconductor layer, thereby increasing the proportion of the first doped semiconductor layer in the first region and the second doped semiconductor layer in the second region, and thus improving the photoelectric conversion efficiency of the back contact battery.

[0029] In one implementation, the ratio of the area of ​​the semiconductor substrate located in the third region to the area of ​​the first surface is less than or equal to 20%.

[0030] By adopting the above technical solution, the proportion of the first region and the second region can be increased while ensuring the isolation of the first doped semiconductor layer and the second doped semiconductor layer, thereby increasing the proportion of the first doped semiconductor layer in the first region and the second doped semiconductor layer in the second region, and thus improving the photoelectric conversion efficiency of the back contact battery.

[0031] In one implementation, the resistivity of the surface layer on at least a portion of the surface of the semiconductor substrate located in the third region is greater than 80 ohm·cm; and / or, the doping concentration of Group IIIA dopants and the doping concentration of Group VA dopants in the semiconductor substrate located in the third region are both less than 1E14 / cm. -3 .

[0032] When the above technical solution is adopted, the surface layer of the semiconductor substrate located in the third region may be doped with other surface passivation layers or other elements or electrical doping during the formation process, resulting in the formation of leakage paths. By controlling the resistivity of the surface layer of the semiconductor substrate located in the third region to be greater than 80 ohm·cm, the leakage can be kept low. Under such circumstances, low leakage can be maintained.

[0033] In one implementation, the doping concentration of the doped element in the semiconductor substrate located in the third region is A within a depth range of 20 nm; and the doping concentration of the doped element in the semiconductor substrate located in the third region is B within a depth range of 2000 nm.

[0034] When the above technical solution is adopted, the resistivity of the surface of the semiconductor substrate in the third region and the deeper part of the semiconductor substrate in the third region is kept at a high level, and the resistivity variation within the depth range is relatively low. Thus, when the doping concentration inside and outside is consistent, the probability of emitter or field formation on the surface of the third region can be reduced, thereby further reducing leakage current.

[0035] In one implementation, the back contact battery further includes a first interface passivation layer; the first interface passivation layer is disposed between the semiconductor substrate and the first doped semiconductor layer.

[0036] When the above technical solution is adopted, the passivation contact structure composed of the first interface passivation layer and the first doped semiconductor layer has excellent interface passivation effect and can achieve selective collection of charge carriers, at least reducing the charge carrier recombination rate of the first region of the first surface, and further improving the photoelectric conversion efficiency of the back contact cell.

[0037] In one implementation, the back contact battery further includes a second interface passivation layer, which is disposed between the second doped semiconductor layer and the semiconductor substrate.

[0038] When the above technical solution is adopted, the passivation contact structure composed of the second interface passivation layer and the second doped semiconductor layer has excellent interface passivation effect and can achieve selective collection of charge carriers, at least reducing the charge carrier recombination rate in the second region of the first surface, and further improving the photoelectric conversion efficiency of the back contact cell.

[0039] In one implementation, the shortest surface distance between the first region and the second region satisfies: H1+H2+W>(150-ρ) / 6, and / or H1+H2+W<(150-ρ)*5.

[0040] Where ρ represents resistivity, 0.1 ohm·cm ≤ ρ ≤ 100 ohm·cm.

[0041] When the above technical solution is adopted, the resistance of the third region can remain relatively high when the resistivity ρ is large, and it can tolerate a relatively small L. However, if the L is also small when the resistivity ρ is small, the third region is prone to breakdown. Therefore, the negative correlation between L and resistivity ρ can avoid breakdown and other problems. The fact that L and resistivity ρ satisfy the above relationship can prevent the shortest surface distance L between the first and second regions from being too small, thus ensuring the insulation effect. It can also avoid problems such as carrier collection problems and decreased stress resistance of the solar cell that may be caused by the shortest surface distance L between the first and second regions being seriously exceeded by the normal range. For example, an excessively large L may be caused by an excessively large W. In this case, the surface carrier transport distance is too large, which will lead to poor carrier collection and thus low solar cell efficiency. An excessively large L may also be caused by excessively large H1 and / or H2. In this case, the substrate is excessively corroded, which can easily lead to a decrease in the stress resistance of the solar cell and thus cell fragmentation.

[0042] In one implementation, W and H2 satisfy the following relationship: lg(W / H2)∈(0.8,3). When using the above technical solution, since W and H2 are formed in a single etching step, both need to be balanced. H2 must be within a suitable range to ensure it is large enough to cut off the longitudinal conductive path, while also preventing it from being too large to ensure uniform longitudinal etching. Similarly, within a suitable range, W can address the problem of poor in-plane etching uniformity due to excessively small W, or the problem of increased carrier transport difficulty due to excessively large W.

[0043] In one implementation, the inner expansion depth of the semiconductor substrate located in the first region is h11, and the inner expansion depth of the semiconductor substrate located in the second region is h21, wherein H1, H2, h11, and h12 are greater than zero and satisfy one or more of the following relationships: H1 > h11; H2 > h21; H1 > H2; h11 > h21; H1 / h11 ∈ (2,500); H2 / h21 ∈ (3,1000); H1 / h11 < H2 / h21.

[0044] When using the above technical solution, since the doping concentration of the first doped semiconductor layer is usually lower than that of the second doped semiconductor layer, the resistivity of the first doped semiconductor layer is relatively high, resulting in poor current collection performance. Therefore, the inner extension layer of the first doped semiconductor layer needs to be deepened while maintaining a certain concentration, with h11 > h21, to improve the current collection capability of the first region. On the other hand, since the doping concentration of the first doped semiconductor layer is usually lower than that of the second doped semiconductor layer, the doping concentration of the inner extension layer in the substrate corresponding to the second doped semiconductor layer is also higher, exceeding 3E17 atoms / cm. 3 The concentration of H2 is more than 4 times that of the inner expansion layer in the substrate corresponding to the first doped semiconductor layer, which leads to a much higher risk of leakage than the inner expansion layer in the substrate corresponding to the first doped semiconductor layer. Therefore, the proportion of h21 to H2 should be lower than the proportion of h11 to H1, i.e., H1 / h11 < H2 / h21, so as to achieve effective electrical isolation of the third region.

[0045] Furthermore, since the third region also has the same doped semiconductor layer and inner extension layer as the first and second regions during the fabrication process, in order to prevent the first dopant forming the first doped semiconductor layer or the second dopant forming the second doped semiconductor layer from remaining on the surface of the third region, the doped semiconductor layer and inner extension layer need to be removed during the subsequent fabrication of the third region. H1 > h11, and H2 > h21, which can ensure that the corresponding doped semiconductor layer and inner extension layer are completely removed, cutting off the leakage path. H1 / h11∈(2,500) or H2 / h21∈(3,1000) can ensure that there is no similar leakage doping in other normal regions except for specially designed regions such as anti-hot spots.

[0046] Secondly, this application also provides a photovoltaic module. The photovoltaic module includes a cell string and an encapsulation layer. The cell string is formed by connecting multiple back-contact cells as described in the above technical solutions, and the encapsulation layer is used to cover the surface of the cell string.

[0047] The beneficial effects of the second aspect and its various implementations in this application can be found in the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0048] Thirdly, this application also provides a method for manufacturing a back contact battery. The method for manufacturing the back contact battery includes:

[0049] A semiconductor substrate is provided, the semiconductor substrate including a first side and a second side opposite to each other, the first side including a first region, a second region and a third region located between the first region and the second region;

[0050] A first doped semiconductor layer is formed in the first region;

[0051] A second doped semiconductor layer is formed in the second region, wherein the first doped semiconductor layer and the second doped semiconductor layer have opposite conductivity types.

[0052] The resistivity of the surface layer of at least a portion of the surface of the semiconductor substrate located in the third region is greater than 20 ohm·cm;

[0053] Furthermore, H1+H2+W is greater than or equal to 4μm and less than or equal to 300μm; where H1 is the height difference between the surface of the third region and the surface of the first region, H2 is the height difference between the surface of the third region and the surface of the second region, and W is the width of the third region.

[0054] The beneficial effects of the third aspect and its various implementations in this application can be found in the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here. Attached Figure Description

[0055] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments of this application and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0056] Figure 1 is a schematic diagram of the structure of the first type of back contact battery in the embodiments of this application;

[0057] Figure 2 is a schematic diagram of the structure of the second type of back contact battery in the embodiments of this application;

[0058] Figure 3 is a schematic diagram of the structure of the third type of back contact battery in the embodiments of this application;

[0059] Figure 4 is a schematic diagram of the structure of the fourth type of back contact battery in the embodiments of this application;

[0060] Figure 5 is a schematic diagram of the distribution of the first electrode and the second electrode in the back contact battery in the embodiment of this application;

[0061] Figure 6 is a schematic diagram of the structure of the fifth type of back contact battery in the embodiments of this application;

[0062] Figure 7 is an enlarged structural schematic diagram of a portion of the area in Figure 6 in an embodiment of this application;

[0063] Figure 8 is a schematic diagram of the sixth type of back contact battery in the embodiments of this application;

[0064] Figure 9 is a schematic diagram showing the internal expansion depth of the third type of back contact battery in Figure 3.

[0065] Reference numerals: 1-Semiconductor substrate, 10-First region, 11-Second region, 12-Third region, 13-Surface, 14-First sidewall, 15-Second sidewall; 2-First doped semiconductor layer, 3-Second doped semiconductor layer, 4-First interface passivation layer, 5-Second interface passivation layer, 6-First electrode, 60-Contact portion of the first electrode, 61-Main body portion of the first electrode; 7-Second electrode, 70-Contact portion of the second electrode, 71-Main body portion of the second electrode; 8-Surface passivation layer. Detailed Implementation

[0066] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0067] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0068] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified. In the description of this application, it should be understood that the terms "upper," "lower," "front," "rear," "left," and "right," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0069] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0070] Currently, in silicon solar cells, the substrate is typically a silicon wafer doped with either N-type or P-type doped material. P-type and N-type doped layers are formed at different locations on the silicon wafer, and electrodes are then formed on the respective regions of the P-type and N-type doped layers.

[0071] When light enters the substrate, electron-hole pairs are generated. These ionized electron-hole pairs undergo carrier separation, causing electrons to accumulate near the N-pole and holes to accumulate near the P-pole. By connecting an external circuit at the electrodes, current can be output.

[0072] BC cells, also known as back-contact cells, have both positive and negative electrodes located on one side of the cell. This effectively reduces the shading area of ​​the main incident surface and improves the light utilization efficiency of the solar cell. In existing technologies, back-contact cells have both N-type and P-type doped layers. The gap between these two doped layers is significant, leading to a higher risk of leakage.

[0073] To address the aforementioned technical problems, in a first aspect, embodiments of this application provide a back-contact battery. Referring to Figures 1 to 4, the back-contact battery includes a semiconductor substrate 1. The semiconductor substrate 1 includes a first surface and a second surface opposite to each other. The first surface includes a first region 10, a second region 11, and a third region 12 located between the first region 10 and the second region 11. A first doped semiconductor layer 2 is disposed in the first region 10, and a second doped semiconductor layer 3 is disposed in the second region 11. The first doped semiconductor layer 2 and the second doped semiconductor layer 3 have opposite conductivity types.

[0074] The resistivity of the surface layer on at least a portion of the surface of the semiconductor substrate located in the third region is greater than 20 ohm·cm; exemplaryly, the resistivity of the surface layer on at least a portion of the surface of the semiconductor substrate located in the third region may be 20 ohm·cm, 21 ohm·cm, 25 ohm·cm, 30 ohm·cm, 32 ohm·cm, 35 ohm·cm, 40 ohm·cm, 45 ohm·cm, 50 ohm·cm, 55 ohm·cm, 60 ohm·cm, 65 ohm·cm, 70 ohm·cm, 75 ohm·cm, 80 ohm·cm, 85 ohm·cm, 90 ohm·cm, 95 ohm·cm, 100 ohm·cm, 105 ohm·cm, 110 ohm·cm, 115 ohm·cm, 120 ohm·cm, etc. 19 0ohm·cm, 200ohm·cm, 250ohm·cm, 300ohm·cm, 350ohm·cm, 400ohm·cm, 450ohm·cm, 500ohm·cm, 550ohm·cm, 600ohm·cm, 700ohm·cm, 800ohm·cm, 900ohm·cm, 1000ohm·cm, etc. Preferably, the resistivity of the surface layer on at least a portion of the surface of the semiconductor substrate located in the third region is greater than 80 ohm·cm. More preferably, the resistivity of the surface layer on at least a portion of the surface of the semiconductor substrate located in the third region is greater than 200 ohm·cm. The resistivity of the surface layer in this application refers to the bulk resistivity within a certain thickness range of the surface, such as a thickness range of 1 micrometer, 1 millimeter, or 1 centimeter.

[0075] Referring to Figures 1 to 4, the semiconductor substrate 1 located in the third region 12 is situated between the first doped semiconductor layer 2 in the first region 10 and the second doped semiconductor layer 3 located in the second region 11. The shortest surface distance L between the first region 10 and the second region 11 can be considered as the shortest distance from the surface of the first region 10 (through an optional first sidewall) along the surface of the third region 12 (through an optional second sidewall) to the surface of the second region 11, i.e., L = H1 + H2 + W. In this application, the shortest surface distance L between the first region 10 and the second region 11 is greater than or equal to 4 μm and less than or equal to 300 μm. Exemplarily, the shortest surface distance L between the first region 10 and the second region 11 can be 4 μm, 10 μm, 50 μm, 100 μm, 120 μm, 150 μm, 180 μm, 200 μm, 230 μm, 250 μm, 280 μm, or 300 μm, etc. Preferably, the shortest surface distance L between the first region 10 and the second region 11 is greater than or equal to 30 μm and less than or equal to 200 μm. For example, the shortest surface distance L between the first region 10 and the second region 11 can be 30 μm, 40 μm, 50 μm, 100 μm, 120 μm, 150 μm, 180 μm, or 200 μm, etc. Preferably, the shortest surface distance L between the first region 10 and the second region 11 is greater than or equal to 40 μm and less than or equal to 300 μm. For example, the shortest surface distance L between the first region 10 and the second region 11 can be 40 μm, 50 μm, 100 μm, 120 μm, 150 μm, 180 μm, 200 μm, 230 μm, 250 μm, 280 μm, or 300 μm, etc. In this embodiment, the shortest surface distance L between the first region 10 and the second region 11 is 150 μm. Meanwhile, in the back contact battery provided in this application embodiment, the resistivity of the surface layer of at least a portion of the surface of the semiconductor substrate 1 located in the third region 12 is greater than 20 ohm·cm. In this application embodiment, the resistivity of the surface layer of at least a portion of the surface of the semiconductor substrate 1 in the third region 12 is greater than 20 ohm·cm. Combined with the shortest surface distance L between the first region 10 and the second region 11 being greater than or equal to 4 μm and less than or equal to 300 μm, it is possible to reduce the leakage risk between the first doped semiconductor layer 2 on the first region 10 and the second doped semiconductor layer 3 on the second region 11, thereby reducing safety hazards and improving the photoelectric conversion efficiency of the back contact battery.The resistivity of the surface layer in the third region is set within a large range, which can suppress the lateral movement of charge carriers at the surface of the third region and reduce the charge carrier concentration at the surface, thereby reducing the leakage risk between the first doped semiconductor layer and the second doped semiconductor layer. Furthermore, the shortest surface distance L between the first region 10 and the second region 11 is greater than or equal to 4 μm and less than or equal to 300 μm, which can increase the proportion of the first region 10 and the second region 11, thereby increasing the proportion of the first doped semiconductor layer 2 located in the first region 10 and the second doped semiconductor layer 3 located in the second region 11, and thus improving the photoelectric conversion efficiency of the back contact battery. Moreover, because the surface layer in the semiconductor substrate 1 corresponding to the third region 12 has a high resistivity and is greatly affected by the electric field of the first or second doped semiconductor layer, the relative electric field strength is high. Photogenerated charge carriers generated near the surface of the third region can be effectively separated. Therefore, although the high resistivity of the third region surface affects the transport of charge carriers, its additional advantages enable the battery efficiency to be improved, especially when the overall width of the third region is small. In the third region 12, the charge carriers generated by the semiconductor substrate 1 are primarily transported within the first doped semiconductor layer 2 and the second doped semiconductor layer 3. Therefore, in this application, the shortest surface distance L between the first region 10 and the second region 11 is less than or equal to 300 μm to ensure that the charge carriers generated by the semiconductor substrate 1 in the third region 12 can be effectively collected by the first doped semiconductor layer 2 and the second doped semiconductor layer 3, thereby ensuring the conversion efficiency of the back contact battery. On the other hand, although the surface of the third region has a high resistivity, setting the surface distance L between the first region 10 and the second region 11 too small would pose a significant risk of leakage and unpredictable risks due to process fluctuations. Therefore, the matched shortest surface distance L is greater than or equal to 4 μm.

[0076] In practical applications, this application does not specifically limit the structure and material of the semiconductor substrate, as long as it can be applied to the back contact battery provided in this application. For example, the semiconductor substrate can be a P-type doped semiconductor substrate, an N-type doped semiconductor substrate, or a semiconductor substrate of a similar intrinsic conductivity type. The crystal type of the semiconductor substrate can be single crystal or polycrystalline, etc.

[0077] Specifically, the aforementioned semiconductor substrate can be a semiconductor substrate without any structure formed thereon. Alternatively, the semiconductor substrate can also have some structure formed thereon; in this case, the structure formed on the semiconductor substrate can be set according to actual needs, and is not specifically limited here. For example, the semiconductor substrate may include a semiconductor substrate and a passivation antireflection layer disposed on the side of the semiconductor substrate opposite to the first doped semiconductor layer and the second doped semiconductor layer, to passivate the side of the semiconductor substrate opposite to the first doped semiconductor layer and the second doped semiconductor layer, reduce the carrier recombination rate on that side, and facilitate more light to be refracted into the semiconductor substrate through that side, further improving the working efficiency of the back contact battery. The material of the aforementioned semiconductor substrate may include any semiconductor material such as silicon, germanium silicon, germanium, or gallium arsenide. The material of the aforementioned passivation antireflection layer may include silicon oxide, silicon nitride, or aluminum oxide.

[0078] Furthermore, the first surface of the semiconductor substrate corresponds to the back-lighting surface of the back contact battery, and the second surface of the semiconductor substrate corresponds to the light-receiving surface of the back contact battery. The distribution of the first, second, and third regions of the semiconductor substrate on the first surface can be determined based on the distribution of the first and second doped semiconductor layers on the first surface. Specifically, since the first doped semiconductor layer of the back contact battery is disposed on the first region, the distribution range of the first region on the first surface can be determined based on the distribution requirements of the first doped semiconductor layer in the actual application scenario. Since the second doped semiconductor layer of the back contact battery is disposed on the second region of the first surface, the distribution range of the second region on the first surface can be determined based on the distribution requirements of the second doped semiconductor layer on the semiconductor substrate in the actual application scenario.

[0079] Furthermore, the light-receiving surface of the aforementioned semiconductor substrate can be planar, or it can be textured. Since textured surfaces have a light-trapping effect, when the light-receiving surface of the semiconductor substrate is textured, the reflectivity of the light-receiving surface can be reduced, allowing more light to be refracted from the light-receiving surface into the semiconductor substrate and absorbed and utilized, thus improving the photoelectric conversion efficiency of the back-contact cell. When the back-lighting surface is polished, the light incident from the light-receiving surface onto the surface of the solar cell and passing through the solar cell can be better reflected back, allowing the light to be reused by the solar cell, improving the conversion efficiency of the solar cell. In addition, because polished surfaces have better flatness, the coating effect is better when preparing other films on the semiconductor substrate, which helps reduce the generation of interface defects and improves the passivation performance of the cell, thereby improving the photoelectric conversion efficiency of the back-contact cell.

[0080] Furthermore, the first and / or second regions have a polished surface or a similar polished surface structure. The surface of the third region can be a polished surface or a similar polished surface, or it can be a textured surface. When the surface of the third region is a polished surface or a similar polished surface, it is beneficial for the formation of subsequent film layers, thereby facilitating surface passivation and deposition. When the surface of the third region is textured, it is beneficial for further reducing leakage current generation, and the proportion of the third region can be further reduced. For example, the textured surface can be a pyramid textured structure.

[0081] It is understandable that one of the first and second regions corresponds to region P, and the other corresponds to region N.

[0082] As for the morphology of the first and second regions in the first surface mentioned above, it can be determined based on the morphology of the electrode structure of the back contact battery and the actual application scenario. For example, the first and second regions can be distributed in alternating stripe patterns or in alternating interdigitated patterns.

[0083] Regarding the first and second doped semiconductor layers mentioned above, in terms of doping type, the first doped semiconductor layer can be N-type, in which case the second doped semiconductor layer is P-type; alternatively, the first doped semiconductor layer can also be P-type, in which case the second doped semiconductor layer is N-type. This application does not specifically limit the doping type of the first and second doped semiconductor layers, as long as their doping types are opposite. When the doping type is P-type, it is generally doped with Group III elements. When the doping type is N-type, it is generally doped with Group V or Group VI elements.

[0084] In terms of materials, the first doped semiconductor layer and / or the second doped semiconductor layer can be made of any semiconductor material such as silicon, germanium-silicon, or germanium. In terms of the arrangement of matter, the crystal phase of the first doped semiconductor layer and / or the second doped semiconductor layer can be amorphous, microcrystalline, nanocrystalline, single-crystal, or polycrystalline. For example, the first doped semiconductor layer and / or the second doped semiconductor layer can be composed of one or more of polycrystalline silicon, amorphous silicon, and microcrystalline silicon.

[0085] In terms of thickness, as the thickness of the first and / or second doped semiconductor layers increases, their conductivity increases. However, this increases the likelihood of leakage between the first and second doped semiconductor layers, necessitating a wider third region. To balance the conductivity of the first and second doped semiconductor layers, their proportion, and the width of the third region, the thickness of the first and / or second doped semiconductor layers is set to be greater than or equal to 50 nm and less than or equal to 500 nm. The thickness directions of both the first and second doped semiconductor layers are aligned with the direction from the first surface to the second surface. For example, the thickness of the first doped semiconductor layer and / or the thickness of the second doped semiconductor layer can be 50nm, 80nm, 100nm, 120nm, 150nm, 180nm, 200nm, 220nm, 250nm, 280nm, 300nm, 320nm, 350nm, 380nm, 400nm, 420nm, 450nm, 480nm, or 500nm, etc. The thickness of the first doped semiconductor layer and the thickness of the second doped semiconductor layer can be equal or unequal.

[0086] In terms of location, the first doped semiconductor layer can be directly formed on the semiconductor substrate. Alternatively, as shown in Figures 1 to 4, the back contact battery may also include a first interface passivation layer 4. The first interface passivation layer 4 is disposed between the semiconductor substrate 1 and the first doped semiconductor layer 2. The material and thickness of the first interface passivation layer 4 can be determined based on the material of the first doped semiconductor layer 2 and actual requirements; no specific limitations are made here. The first interface passivation layer 4 can be a single-layer or multi-layer structure. The first interface passivation layer 4 can be composed of different materials in different regions. It should be noted that "regionalization" here refers to a detailed division based on the first interface passivation layer 4 as the main body, and does not refer to the first region 10, second region 11, and third region 12 mentioned earlier. The material of the first interface passivation layer 4 can be one or more of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, silicon carbide, and amorphous silicon. For example, when the first doped semiconductor layer 2 is a doped polycrystalline silicon layer, the first interface passivation layer 4 is a tunneling oxide layer. For example, when the first doped semiconductor layer 2 is a doped amorphous silicon layer, the first interface passivation layer 4 can be an intrinsic amorphous silicon layer. The thickness of the first interface passivation layer 4 is greater than or equal to 0.5 nm and less than or equal to 5 nm. For example, the thickness of the first interface passivation layer 4 can be 0.5 nm, 1 nm, 1.5 nm, 2 nm, 2.5 nm, 3 nm, 3.5 nm, 4 nm, 4.5 nm, or 5 nm, etc. The passivation contact structure composed of the first interface passivation layer 4 and the first doped semiconductor layer 2 has excellent interface passivation effect and can achieve selective collection of charge carriers, at least reducing the carrier recombination rate in the first region 10 of the first surface, and further improving the photoelectric conversion efficiency of the back contact cell.

[0087] As for the second doped semiconductor layer, it can be directly formed on the semiconductor substrate. Alternatively, as shown in Figure 1, the back contact battery may also include a second interface passivation layer 5, wherein the second interface passivation layer 5 is disposed between the second doped semiconductor layer 3 and the semiconductor substrate 1. The material and thickness of the second interface passivation layer 5 can be set according to the material of the second doped semiconductor layer 3 and actual needs, and are not specifically limited here. The second interface passivation layer 5 can be a single-layer structure or a multi-layer structure. The second interface passivation layer 5 can be composed of different materials in different regions. It should be noted that the "division of regions" here refers to a detailed division based on the second interface passivation layer 5 as the main body, and does not refer to the first region 10, the second region 11, and the third region 12 mentioned above. The material of the second interface passivation layer 5 can be one or more of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, silicon carbide, and amorphous silicon. For example, when the second doped semiconductor layer 3 is a doped polycrystalline silicon layer, the second interface passivation layer 5 is a tunneling oxide layer. For example, when the second doped semiconductor layer 3 is a doped amorphous silicon layer, the second interface passivation layer 5 can be an intrinsic amorphous silicon layer. The thickness of the second interface passivation layer 5 is greater than or equal to 0.5 nm and less than or equal to 5 nm. For example, the thickness of the second interface passivation layer 5 can be 0.5 nm, 1 nm, 1.5 nm, 2 nm, 2.5 nm, 3 nm, 3.5 nm, 4 nm, 4.5 nm, or 5 nm, etc. The passivation contact structure composed of the second interface passivation layer 5 and the second doped semiconductor layer 3 has excellent interface passivation effect and can achieve selective collection of charge carriers, at least reducing the carrier recombination rate in the second region 11 of the first surface, and further improving the photoelectric conversion efficiency of the back contact cell.

[0088] The following describes some specific application scenarios of this application with several possible embodiments. It should be understood that the following description is for understanding only and is not intended to limit the application.

[0089] The first type: Referring to Figures 1 and 2, along the direction from the first region 10 to the second region 11, the surfaces of the first region 10, the second region 11, and the third region 12 are located on approximately the same plane.

[0090] At this point, the height difference H1 between the surface of the third region and the surface of the first region is approximately 0, the height difference H2 between the surface of the third region and the surface of the second region is approximately 0, and the width of the third region is W, where 4μm ≤ W ≤ 300μm. That is, the shortest surface distance L between the first region 10 and the second region 11 is approximately the width W of the third region, where W can be 4μm, 10μm, 50μm, 100μm, 120μm, 150μm, 180μm, 200μm, 230μm, 250μm, 280μm, or 300μm, etc.

[0091] Based on the preceding description, the resistivity of the surface layer of the semiconductor substrate in the third region is greater than 20 ohm·cm. Since the surface of the third region is located on approximately the same plane as the surfaces of the first and second regions, the risk of leakage between the first doped semiconductor layer 2 and the second doped semiconductor layer 3 is relatively high. Therefore, the resistivity of the surface layer of the third region can preferably be greater than 50 ohm·cm.

[0092] Referring to Figure 1, a first interface passivation layer 4 and a first doped semiconductor layer 2 are formed on the first interface passivation layer in the first region. A second interface passivation layer 5 and a second doped semiconductor layer 3 are formed on the second interface passivation layer in the second region. Referring to Figure 2, the second doped semiconductor layer 3 is located at a certain depth within the surface of the semiconductor substrate in the second region, for example, it can be an aluminum-doped region.

[0093] The second type: Referring to Figures 3, 4 and 9, along the direction from the second surface to the first surface, the surface of the first region 10 is higher than the surface 13 of the third region 12.

[0094] With the above technical solution, since the surfaces of the first region 10, the second region 11, and the third region 12 are located on the same plane, and the surface of the first region 10 is higher than the surface 13 of the third region 12, there is a height difference H1 between the surfaces of the first region 10 and the third region 12. In this case, the shortest surface distance L between the first region 10 and the second region 11 is greater than the width W of the third region. Therefore, while ensuring that the shortest surface distance L between the first region 10 and the second region 11 is constant, the width W of the third region 12 can be reduced. At this point, while ensuring the isolation of the first doped semiconductor layer 2 and the second doped semiconductor layer 3, the proportion of the first region 10 and the second region 11 can be further increased, thereby further increasing the proportion of the first doped semiconductor layer 2 located in the first region 10 and the second doped semiconductor layer 3 located in the second region 11, and further improving the photoelectric conversion efficiency of the back contact battery.

[0095] In this embodiment, 0 μm < H1 ≤ 20 μm. Exemplarily, H1 can be 1 μm, 3 μm, 5 μm, 7 μm, 10 μm, 12 μm, 15 μm, 18 μm, or 20 μm, etc. Preferably, 1 μm ≤ H1 ≤ 7 μm. Exemplarily, H1 can be 1 μm, 1.3 μm, 1.5 μm, 2 μm, 2.3 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.3 μm, 4.5 μm, 5 μm, 5.5 μm, 6 μm, 6.3 μm, 6.5 μm, or 7 μm, etc.

[0096] Referring to Figures 3 and 9, a first interface passivation layer 4 and a first doped semiconductor layer 2 are disposed on the first region, and a second interface passivation layer 5 and a second doped semiconductor layer 3 are disposed on the second region. Along the direction from the second surface to the first surface, the surface of the second region is higher than the surface of the third region, and at this time, the surface of the second region 11 and the surface of the third region also have a height difference H2. In this case, the semiconductor substrate 1 located in the first region 10 also includes a first sidewall 14, and the semiconductor substrate 1 located in the second region 11 also includes a second sidewall 15. The first sidewall 14 is connected to the surface 13 of the third region and the surface of the first region 10, respectively, and the second sidewall 15 is connected to the surface 13 of the third region and the surface of the second region 11, respectively. The shortest surface distance L between the first region 10 and the second region 11 is the sum of the bottom width of the third region, the length of the first sidewall 14, and the length of the second sidewall 15. The length of the first sidewall 14 at this location is the shortest distance from the surface of the first region 10 along the surface of the first sidewall 14 to the surface of the third region. The length of the second sidewall 15 is the shortest distance from the surface of the second region 11 along the surface of the second sidewall 15 to the surface of the third region. As shown in Figures 3 and 9, when both the first sidewall 14 and the second sidewall 15 are vertical sidewalls, the shortest surface distance L between the first region 10 and the second region 11 is H1 + W + H2. Preferably, W is greater than 4 μm and less than or equal to 300 μm.

[0097] In one alternative approach, 0 μm < H2 ≤ 20 μm. Exemplarily, H2 can be 1 μm, 3 μm, 5 μm, 7 μm, 10 μm, 12 μm, 15 μm, 18 μm, or 20 μm, etc. Preferably, 1 μm ≤ H2 ≤ 7 μm. Exemplarily, H2 can be 1 μm, 1.3 μm, 1.5 μm, 2 μm, 2.3 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.3 μm, 4.5 μm, 5 μm, 5.5 μm, 6 μm, 6.3 μm, 6.5 μm, or 7 μm, etc.

[0098] When one or both of the first sidewall 14 and the second sidewall 15 include surfaces inclined relative to the first surface, the shortest surface distance L between the first region 10 and the second region 11 will be slightly less than H1+W+H2, but the difference is not significant, as shown in Figures 6 and 7. In this case, it is beneficial for the film layer to better cover the first sidewall 14 and the second sidewall 15 when forming the film layer on the surface of the third region 12 later, preventing unfilled gaps at the boundaries of the first region 10 and the third region 12 or the second region 11 and the third region 12, reducing the number of defects on the first surface side of the back contact battery, and improving the formation quality of the film layer at the aforementioned boundaries. It should be noted that the width W of the third region is the maximum distance between the first and second sidewalls. Referring to Figure 4, the surfaces of the second and third regions can be located on approximately the same plane. In this case, when the first sidewall 14 is a vertical sidewall, the surface distance L between the first region 10 and the second region 11 is H1+W. Of course, when the first sidewall 14 includes a surface inclined relative to the first surface, the shortest surface distance L between the first region 10 and the second region 11 is slightly less than H1+W. Wherein, 4μm≤W≤250μm, 0μm

[0099] With the above technical solution, compared to the surfaces of the first region 10, the second region 11, and the third region 12 being located on the same plane, the width W of the third region 12 can be further reduced while keeping the shortest surface distance L between the first region 10 and the second region 11 constant. In this case, while ensuring the isolation of the first doped semiconductor layer 2 and the second doped semiconductor layer 3, the proportion of the first region 10 and the second region 11 can be further increased, thereby further increasing the proportion of the first doped semiconductor layer 2 in the first region 10 and the second doped semiconductor layer 3 in the second region 11, and further improving the photoelectric conversion efficiency of the back contact battery.

[0100] ​Furthermore, when the third region has a sidewall structure (i.e., including a first sidewall and / or a second sidewall of a surface inclined relative to the first surface), the surfaces of the first and / or second sidewalls near the first and / or second doped semiconductor layers may have locally highly doped regions due to the doping effect of the first and / or second doped semiconductor layers. In this case, the surface layer of the third region preferably has a resistivity greater than 20 ohm·cm, more preferably greater than 50 ohm·cm, to offset part of the highly doped regions on the sidewall surfaces. Here, highly doped regions should be understood as having an impurity concentration greater than that inside the substrate.

[0101] As one possible implementation, when both the first sidewall and the second sidewall include surfaces that are inclined relative to the first surface, the horizontal distance between the first sidewall and the second sidewall gradually decreases along the direction from the first surface to the second surface.

[0102] Furthermore, the surfaces of the first sidewall and / or the second sidewall can be polished or similarly polished, or even textured. When the surfaces of the first sidewall and / or the second sidewall are polished or similarly polished, it facilitates the formation of the subsequent film layer, thereby promoting surface passivation and deposition. When the surfaces of the first sidewall and / or the second sidewall are textured, it helps to further reduce leakage current. For example, the textured surface can be a pyramidal textured structure.

[0103] In this application, as one possible implementation, the minimum value of the width of the third region preferably conforms to W. min = k / ρ+C; where ρ represents resistivity, k = 400 μm·ohm·cm, 0 μm ≤ C ≤ 40 μm.

[0104] For example, when ρ = 5, W min =80; when ρ=20, W min =20; when ρ=50, W min =8; when ρ=100, W min =4.

[0105] As one possible implementation, the shortest surface distance L between the first and second regions is negatively correlated with ρ and satisfies L > (150 - ρ) / 6; where ρ represents resistivity, 0.1 ohm·cm ≤ ρ ≤ 100 ohm·cm. With the above technical solution, since a large resistivity ρ allows the resistance of the third region to remain relatively high, it can tolerate a relatively small L. Conversely, if the resistivity ρ is low, and L is also small, the third region is prone to breakdown. Therefore, the negative correlation between L and resistivity ρ can avoid breakdown problems. The fact that L and resistivity ρ satisfy the above relationship can prevent the shortest surface distance L between the first and second regions from being too small, thus ensuring the insulation effect.

[0106] As one possible implementation, the shortest surface distance L between the first and second regions is preferably negatively correlated with ρ and satisfies L < (150 - ρ) * 5; where ρ represents resistivity, 0.1 ohm·cm ≤ ρ ≤ 100 ohm·cm. With the above technical solution, since a large resistivity ρ allows the resistance of the third region to remain relatively high, it can tolerate a relatively small L. Conversely, if the resistivity ρ is low, and L is also small, the third region is prone to breakdown. Therefore, the negative correlation between L and resistivity ρ can avoid breakdown problems. The fact that L and resistivity ρ satisfy the above relationship can prevent carrier collection problems and decreased cell stress resistance that may result from the shortest surface distance L between the first and second regions significantly exceeding the normal range. For example, an excessively large L may be caused by an excessively large W, in which case the excessive surface carrier transport distance leads to poor carrier collection, resulting in low solar cell efficiency. An excessively large L may also be caused by excessively large H1 and / or H2, in which case the substrate is excessively corroded, easily leading to reduced cell stress resistance and cell fragmentation.

[0107] Referring to Table 1, which shows the different effects when the resistivity ρ is 30 ohm·cm.

[0108] Table 1

[0109] In Table 1, when the resistivity ρ is 30 ohm·cm, the lower limit is L > (150-30) / 6 = 20 μm, and the upper limit is L < (150-30)*5 = 600 μm.

[0110] Experimental group 3 was the normal experimental group, and the effects of the other experimental groups were compared with those of experimental group 3.

[0111] In Table 1, Experiment 1 shows the case where L is close to the lower limit. This is a normal experimental group, but due to the small L caused by W, the leakage current Irev is slightly higher, but the situation is basically normal. Experiment 6 shows the case where H1 and H2 are too small, causing L to be small, resulting in higher leakage current. Experiment 2 shows the case where L is below the lower limit. This is an experimental group with small L. Due to the small L, the leakage current Irev is relatively large, and the battery efficiency Eta is relatively low. Experiment 3 shows the case where L is in the middle of the range between the upper and lower limits. This is a normal experimental group. Due to the moderate L, the leakage current Irev is slightly lower, but the situation is basically normal. Experiment 4 shows the case where L exceeds the upper limit. This is an experimental group with large L. Due to the large L, the leakage current Irev is normal, but the collection efficiency is low, and the battery efficiency Eta is low. Experiment 5 shows the case where H1 and H2 are too large. This experimental group shows that large H1 and H2 may lead to a large fragmentation rate. The comparison between experimental groups 1 and 6 and experimental group 2 shows that when L is less than 20μm, the leakage current Irev is seriously exceeded, resulting in the battery being unqualified and the battery efficiency Eta is also affected.

[0112] Experimental group 3 is the normal group. It can be seen that under a large L, the leakage current Irev is improved compared to experimental group 1, and is reduced to 0.09A; the reliability is improved to a certain extent.

[0113] In experimental group 4, L = 611 μm, which exceeded the upper limit, resulting in a significant decrease in efficiency to 23.66%, which is already considered an inefficient product; although leakage was normal, the collection efficiency and battery efficiency were low.

[0114] In experimental group 5, the H1 depth was too large. Although the total L was normal, the photoelectric conversion efficiency Eta data was good, and the leakage was also relatively good, the battery fragmentation rate reached 3.3%, seriously affecting the yield and resulting in excessively high product costs. In this application, given a fixed shortest surface distance L between the first and second regions, generally speaking, the larger H1 and H2 are, the smaller W can be. H1 and H2 can affect the fragmentation rate, while W can affect the collection efficiency.

[0115] For example, W > 20 μm. Further, considering the difficulty of achieving process uniformity of W across the entire cell plane and the difficulty of carrier transport, preferably, W > 30 μm; more preferably, W > 35 μm. H2 typically requires consideration of both etching depth and the difficulty of carrier transport; therefore, preferably lg(W / H2) ∈ (0.8, 3), which can balance the lateral and longitudinal etching uniformity of the silicon substrate with the difficulty of carrier transport.

[0116] As one possible implementation, the aforementioned back contact battery sequentially includes a first region, a third region, a second region, and a third region. The width of the back contact battery is greater than or equal to 500 μm and less than or equal to 2000 μm. The ratio of the width of at least one third region to the width of the back contact battery is less than or equal to 0.2%. The width direction of both the back contact battery and the third region is consistent with the direction from the first region to the second region. For example, the width of the back contact battery can be 500 μm, 800 μm, 1000 μm, 1200 μm, 1500 μm, 1800 μm, 1900 μm, or 2000 μm, etc. The ratio of the width of at least one third region to the width of the back contact battery can be 0.2%, 0.18%, 0.15%, 0.1%, or 0.05%, etc.

[0117] When employing the above technical solution, since the ratio of the width of the third region to the width of the back contact cell is less than or equal to 0.2%, the ratio of the sum of the widths of the first and second regions to the width of the back contact cell is greater than or equal to 99.8%. Therefore, the total proportion of the first and second regions is larger than that of the third region, resulting in a larger total proportion of the first doped semiconductor layer located in the first region and the second doped semiconductor layer located in the second region. This increases the amount of charge carriers collected by the back contact cell, thereby improving its photoelectric conversion efficiency.

[0118] As one possible implementation, referring to Figures 1 to 5, the aforementioned back contact battery further includes a first electrode 6 and a second electrode 7, wherein the first electrode 6 is electrically connected to the first doped semiconductor layer 2, and the second electrode 7 is electrically connected to the second doped semiconductor layer 3.

[0119] Referring to Figure 1, the first electrode 6 includes a contact portion 60 in direct contact with the first doped semiconductor layer 2 and a main body portion 61 away from the first doped semiconductor layer 2. The second electrode 7 includes a contact portion 70 in direct contact with the second doped semiconductor layer 3 and a main body portion 71 away from the second doped semiconductor layer 3. The distance L1 between the contact portion 60 of the first electrode and the third region 12 is greater than or equal to 80 μm and less than or equal to 500 μm, and the extending direction of the distance L1 is consistent with the direction from the first region 10 to the second region 11; and / or, the distance L2 between the contact portion 70 of the second electrode and the third region 12 is greater than or equal to 80 μm and less than or equal to 500 μm, and the extending direction of the distance L2 is consistent with the direction from the first region 10 to the second region 11. For example, the distance L1 can be 80 μm, 100 μm, 150 μm, 200 μm, 250 μm, 300 μm, 350 μm, 400 μm, 450 μm, or 500 μm, etc. The spacing L2 can be 80μm, 100μm, 150μm, 200μm, 250μm, 300μm, 350μm, 400μm, 450μm, or 500μm, etc. Preferably, the spacing L1 and spacing L2 are greater than or equal to 150μm and less than or equal to 300μm. For example, the spacing L1 and spacing L2 can be 150μm, 160μm, 180μm, 200μm, 220μm, 250μm, 280μm, or 300μm, etc. The values ​​of the above spacing L1 and L2 can be equal or unequal.

[0120] When the above technical solution is adopted, L1 and L2, within the aforementioned value range, not only ensure the strong connection between the first electrode 6 and the first doped semiconductor layer 2 (or the second electrode 7 and the second doped semiconductor layer 3), but also improve the bonding force between the electrode and the doped semiconductor layer. Simultaneously, compared to cases with a spacing of less than 80 μm, current transmission efficiency can be improved, thereby increasing the conversion efficiency of the back contact battery.

[0121] In one alternative embodiment, referring to FIG1, the ratio of the width W1 of the first doped semiconductor layer 2 to the spacing L1 is greater than or equal to 2, and the width direction of the first doped semiconductor layer 2 is consistent with the direction from the first region 10 to the second region 11; and / or, the ratio of the width W2 of the second doped semiconductor layer 3 to the spacing L2 is greater than or equal to 2, and the width direction of the second doped semiconductor layer 3 is consistent with the direction from the first region 10 to the second region 11. Exemplarily, the ratio can be 2, 2.1, 2.3, 2.5, 2.7, or 3, etc. It should be noted that the ratio of the width of the first doped semiconductor layer 2 to the spacing L1 and the ratio of the width of the second doped semiconductor layer 3 to the spacing L2 can be equal or unequal.

[0122] In one alternative embodiment, referring to Figure 1, the distance between the main body portion 61 of the first electrode and the third region 12 is L3, where L3 ≤ L1; the direction of extension of distance L3 is consistent with the direction from the first region 10 to the second region 11; and / or, the distance between the main body portion 71 of the second electrode and the third region 12 is L4, where L4 ≤ L2; the direction of extension of distance L4 is consistent with the direction from the first region 10 to the second region 11. Under optimized metallization conditions, L3 and / or L4 equal to 0.

[0123] As one possible implementation, the electrode paste forming the first electrode and the electrode paste forming the second electrode may be the same or different. Exemplarily, the electrode paste forming the first electrode and the electrode paste forming the second electrode may include metals (e.g., Ag, Cu, Al, Ni, Au, Zn, Sn, Pb, etc.), metal oxides (e.g., ITO, AZO, IWO, etc.), metal nitrides (e.g., TiN, etc.), metal carbides (e.g., TiC, etc.), or metal sulfides, as well as other conductive connecting materials (e.g., graphene, etc.), or various combinations of the above materials.

[0124] As one possible implementation, the widths of the first electrode and the second electrode can be the same or different. For example, the widths of both the first and second electrodes are greater than or equal to 5 μm and less than or equal to 600 μm. For instance, the widths can be 5 μm, 10 μm, 50 μm, 100 μm, 150 μm, 200 μm, 250 μm, 300 μm, 350 μm, 400 μm, 450 μm, 500 μm, 550 μm, or 600 μm, etc.

[0125] As one possible implementation, referring to Figures 1 to 4, the aforementioned back contact battery further includes a surface passivation layer 8 formed on the first doped semiconductor layer 2, the second doped semiconductor layer 3, and the semiconductor substrate 1 located in the third region 12. The surface passivation layer 8 can be made of one or more of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, silicon carbide, and amorphous silicon. The surface passivation layer 8 can be a single-layer structure or a multi-layer structure.

[0126] Both the first electrode and the second electrode can be in continuous contact. In the actual manufacturing process of the back contact battery, the electrode paste used to form the first electrode and the second electrode is coated on the surface passivation layer and then sintered so that the electrode paste passes through the surface passivation layer and is electrically connected to the corresponding first doped semiconductor layer and second doped semiconductor layer respectively.

[0127] The first and second electrodes described above can also be in partial contact. For example, the first electrode and / or the second electrode may include a fine gate and a main gate, wherein the fine gate contacts the first doped semiconductor layer and the second doped semiconductor layer, while the main gate does not contact either the first doped semiconductor layer or the second doped semiconductor layer. Alternatively, the first electrode and / or the second electrode may consist only of a fine gate, which may contact the first doped semiconductor layer or the second doped semiconductor layer at selective locations.

[0128] As one possible implementation, referring to Figure 1, the ratio of the width W of the third region 12 to the width W1 of the first doped semiconductor layer 2 is less than or equal to 35%, and / or, the ratio of the width W of the third region 12 to the width W2 of the second doped semiconductor layer 3 is less than or equal to 35%. Exemplarily, the ratio of the width W of the third region 12 to the width W1 of the first doped semiconductor layer 2 can be 35%, 33%, 31%, 30%, 29%, 26%, 20%, etc. Preferably, the ratio of the width W of the third region 12 to the width W1 of the first doped semiconductor layer 2 is less than or equal to 30%. Exemplarily, the ratio of the width W of the third region 12 to the width W2 of the second doped semiconductor layer 3 can be 35%, 33%, 31%, 30%, 29%, 26%, 20%, etc. Preferably, the ratio of the width W of the third region 12 to the width W2 of the second doped semiconductor layer 3 is less than or equal to 30%. It should be noted that the above two ratios may or may not be equal.

[0129] As another possible implementation, the ratio of the area of ​​the semiconductor substrate located in the third region to the area of ​​the first surface is less than or equal to 20%. Exemplarily, this ratio can be 20%, 19%, 18%, 17%, 16%, 15%, 14%, 13%, 12%, 11%, or 10%, etc.

[0130] In both of the above cases, the proportion of the first region and the second region can be increased while ensuring the isolation of the first doped semiconductor layer and the second doped semiconductor layer. This increases the proportion of the first doped semiconductor layer in the first region and the second doped semiconductor layer in the second region, thereby improving the photoelectric conversion efficiency of the back contact battery.

[0131] As one possible implementation, the doping concentrations of Group IIIA dopants and Group VA dopants in the semiconductor substrate located in the third region are both less than 1E14 / cm². -3 For example, the doping concentration could be 9.9E13 / cm³. -3 9E13 / cm -3 8E13 / cm -3 7E13 / cm -3 6E13 / cm -3 wait.

[0132] As another possible implementation, the doping concentration of the doped element in the semiconductor substrate located in the third region is A within a depth range of 20 nm; and the doping concentration of the doped element in the semiconductor substrate located in the third region is B within a depth range of 2000 nm. For example, It can be 9.9%, 9%, 8.5%, 8%, etc. As can be seen from the above, within the two depth ranges mentioned above, the doping concentration of the doped elements in the semiconductor substrate located in the third region is the same or close.

[0133] In this application, the inner diffusion depth is defined as a doping concentration > 3E17 atoms / cm 3 The depth of the inner expansion can be measured using existing methods, such as SIMS (secondary ion mass spectrometry). This application does not limit the measurement method.

[0134] In this application, the inward expansion depth of the semiconductor substrate located in the first region is defined as h11, and the inward expansion depth of the semiconductor substrate located in the second region is defined as h21, as shown in Figure 9. The first doped semiconductor layer is usually prepared before the second doped semiconductor layer, therefore H1 > H2.

[0135] Since the doping concentration of the first doped semiconductor layer is typically lower than that of the second doped semiconductor layer (e.g., the doping concentration of the second doped semiconductor layer is >5E19 atoms / cm³, for example, 5E19 atoms / cm³ < the doping concentration of the second doped semiconductor layer < 8E21 atoms / cm³), and the doping concentration of the first doped semiconductor layer is <5E19 atoms / cm³ (e.g., 5E17 atoms / cm³ < the doping concentration of the first doped semiconductor layer < 5E19 atoms / cm³), the resistivity of the first doped semiconductor layer is relatively high, resulting in poor current collection performance. Therefore, the inner extension layer of the first doped semiconductor layer needs to be deepened while maintaining a certain concentration to improve the current collection capability of the first region. Therefore, preferably, h11 > h21. Since the doping concentration of the first doped semiconductor layer is typically lower than that of the second doped semiconductor layer, the doping concentration of the inner extension layer in the substrate corresponding to the second doped semiconductor layer is also higher, exceeding 3E17 atoms / cm³. 3 The concentration of H2 is more than 4 times that of the inner expansion layer in the substrate corresponding to the first doped semiconductor layer, which leads to a much higher risk of leakage than the inner expansion layer in the substrate corresponding to the first doped semiconductor layer. Therefore, the proportion of h21 to H2 should be lower than the proportion of h11 to H1, i.e., H1 / h11 < H2 / h21, so as to achieve effective electrical isolation of the third region.

[0136] Because the third region also has the same doped semiconductor layer and inner extension layer as the first and second regions during fabrication, to prevent the first dopant forming the first doped semiconductor layer or the second dopant forming the second doped semiconductor layer from remaining on the surface of the third region, the doped semiconductor layer and inner extension layer need to be removed during subsequent fabrication of the third region. To ensure that the corresponding doped semiconductor layer and inner extension layer are completely removed and the leakage path is cut off, H1 > h11, and preferably H2 > h21 at the same time.

[0137] As one possible implementation, preferably, H1 and h11 satisfy the following relationship: H1 / h11∈(2,500); preferably, H2 and h21 satisfy the following relationship: H2 / h21∈(3,1000). By adopting the above technical solution, the process window can be guaranteed. Considering that the entire surface can achieve doping in the third region, the conditions H1 / h11∈(2,500) or H2 / h21∈(3,1000) are preferred. This ensures that, except for specially designed areas such as those for preventing hot spots, there is no similar leakage doping in other normal areas.

[0138] As one possible implementation, when the third region includes the first sidewall 14 (as shown in Figures 3-4 and 9), the first doped semiconductor layer located in the first region and the first sidewall 14 of the third region have a lateral spacing, for example, as shown in Figure 8; and / or, when the third region includes the second sidewall 15, the second doped semiconductor layer located in the second region and the second sidewall 15 of the third region have a lateral spacing.

[0139] At this point, not only can the first doped semiconductor layer and the second doped semiconductor layer be further isolated, further reducing the risk of leakage between the first doped semiconductor layer and the second doped semiconductor layer and reducing safety hazards, but parasitic absorption can also be reduced and battery efficiency improved.

[0140] Secondly, embodiments of this application also provide a photovoltaic module. The photovoltaic module includes a cell string and an encapsulation layer. The cell string is formed by connecting multiple back-contact cells as described in the above technical solutions, and the encapsulation layer is used to cover the surface of the cell string.

[0141] The beneficial effects of the second aspect and its various implementations in this application can be found in the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0142] Thirdly, embodiments of this application also provide a method for manufacturing a back contact battery. The method for manufacturing the back contact battery includes:

[0143] First, a semiconductor substrate is provided; the semiconductor substrate includes a first surface and a second surface opposite to each other; the first surface includes a first region, a second region and a third region located between the first region and the second region.

[0144] It should be noted that before actually fabricating the back contact battery, the semiconductor substrate needs to undergo surface treatment, such as damage removal, stain removal, polishing, or texturing, to obtain a semiconductor substrate that meets the requirements. As for the specific processing procedures, existing technologies can be referenced, and no specific limitations are made here.

[0145] Next, a first doped semiconductor layer is formed in the first region.

[0146] For example, a first doped semiconductor material layer can be formed on a first surface of a semiconductor substrate using processes such as chemical vapor deposition. Next, a first mask material layer is formed on the first doped semiconductor material layer. Then, the first mask material layer is patterned (e.g., patterned using a laser) to obtain a first mask layer corresponding to the first region. Next, under the action of the first mask layer, the first doped semiconductor material layer is processed (e.g., patterned using KOH or NaOH) to obtain a first doped semiconductor layer corresponding to the first region. The material of the first mask material layer can be silicon oxide.

[0147] In one example, the specific steps for forming a monolithically disposed first doped semiconductor material layer on the first surface of a semiconductor substrate may be: forming an intrinsic amorphous silicon layer monolithically on the first surface of the semiconductor substrate, and then subjecting the intrinsic amorphous silicon layer to boron diffusion to form a P-type doped polycrystalline silicon layer. The thickness of the aforementioned P-type doped polycrystalline silicon layer is greater than or equal to 50 nm and less than or equal to 500 nm; for example, the thickness of the P-type doped polycrystalline silicon layer can be 50 nm, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, 450 nm, or 500 nm, etc. It should be understood that the aforementioned intrinsic amorphous silicon layer can be replaced with other semiconductor layers, such as microcrystalline silicon, polycrystalline silicon, nanocrystalline silicon, or any combination of two or more.

[0148] In another example, the specific steps for forming the first doped semiconductor layer disposed in the first region may be as follows: an intrinsic semiconductor layer is formed integrally on the first surface of a semiconductor substrate, and then, in a high-temperature, BCl3, and oxygen environment, P-type doping of the intrinsic semiconductor layer is completed in one step to obtain the first doped semiconductor material layer. Simultaneously, a borosilicate glass (BSG) layer is formed on the first doped semiconductor material layer, serving as a first mask material layer. Next, the first mask material layer is patterned to obtain a first mask layer corresponding to the first region. Then, under the action of the first mask layer, the first doped semiconductor material layer is processed to obtain the first doped semiconductor layer corresponding to the first region.

[0149] As one possible implementation, when the back contact battery also includes a first interface passivation layer, after providing the semiconductor substrate and before forming the first doped semiconductor layer disposed in the first region, the manufacturing method of the back contact battery further includes: forming a first interface passivation material layer integrally on the first surface of the semiconductor substrate, and then processing the first interface passivation material layer under the action of a mask layer to form the first interface passivation layer located in the first region. For a description of the material and thickness of the first interface passivation layer, please refer to the description in the first aspect, which will not be repeated here. It should be noted that the method for forming the first interface passivation layer includes one or more of plasma-enhanced chemical vapor deposition, low-pressure chemical vapor deposition, catalytic chemical vapor deposition (Cat-CVD), or atomic layer deposition (ALD).

[0150] Next, a second doped semiconductor layer is formed in the second region; the first doped semiconductor layer and the second doped semiconductor layer have opposite conductivity types.

[0151] For example, a second doped semiconductor material layer can be formed integrally on a first surface of a semiconductor substrate and on a first mask layer using processes such as chemical vapor deposition. Next, a second mask material layer is formed integrally on the integrally formed second doped semiconductor material layer. Then, the second mask material layer is patterned (e.g., patterned using a laser) to obtain a second mask layer corresponding to the second region. Next, under the action of the second mask layer, the second doped semiconductor material layer is processed (e.g., patterned using KOH or NaOH) to obtain a second doped semiconductor layer corresponding to the second region. The second mask material layer can be a silicon oxide layer or a glass phosphate layer. Finally, the first mask layer and the second mask layer are removed.

[0152] As one possible implementation, when the back contact battery also includes a second interface passivation layer, after providing the semiconductor substrate and before forming the second doped semiconductor layer disposed in the second region, the manufacturing method of the back contact battery further includes: forming a second interface passivation material layer integrally on a first surface of the semiconductor substrate and on a first mask layer, and then processing the second interface passivation material layer under the action of the mask layer to form the second interface passivation layer located in the second region. Descriptions of the material and thickness of the second interface passivation layer can be found in the description in the first aspect and will not be repeated here. It should be noted that the method for forming the second interface passivation layer includes one or more of plasma-enhanced chemical vapor deposition, low-pressure chemical vapor deposition, catalytic chemical vapor deposition (Cat-CVD), or atomic layer deposition (ALD).

[0153] Wherein, the resistivity of the surface layer of at least a portion of the surface of the semiconductor substrate located in the third region is greater than 20 ohm·cm; and H1+H2+W is greater than or equal to 4 μm and less than or equal to 300 μm; wherein, H1 is the height difference between the surface of the third region and the surface of the first region, H2 is the height difference between the surface of the third region and the surface of the second region, and W is the width of the third region.

[0154] Next, a surface passivation layer is formed on the first doped semiconductor layer, the second doped semiconductor layer, and the semiconductor substrate located in the third region. The surface passivation layer can be made of one or more of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, silicon carbide, and amorphous silicon. The surface passivation layer can be a single-layer structure or a multi-layer structure. The method for forming the surface passivation layer can be one or more of plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), ambient pressure chemical vapor deposition (APCVD), metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), or physical vapor deposition (PVD). For example, an aluminum oxide layer is prepared using atomic layer deposition, and then one or more silicon nitride layers are prepared on the aluminum oxide layer using plasma-enhanced chemical vapor deposition.

[0155] As one possible implementation, when the back contact battery also includes a passivation layer and / or an anti-reflection layer located on the second surface of the semiconductor substrate, the material of the passivation layer and / or anti-reflection layer can be one or more of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, silicon carbide, and amorphous silicon. The formation process of the passivation layer and / or anti-reflection layer can be found in the formation process of the surface passivation layer, and will not be repeated here.

[0156] Next, electrode paste is printed on the first doped semiconductor layer in the first region and the second doped semiconductor layer in the second region to form a first electrode electrically connected to the first doped semiconductor layer and a second electrode electrically connected to the second doped semiconductor layer. The selection of the electrode paste can be found in the description of the first aspect and will not be repeated here.

[0157] The beneficial effects of the third aspect and its various implementations in the embodiments of this application can be referred to the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0158] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples. The above descriptions are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A back-contact battery, comprising: A semiconductor substrate includes opposing first and second surfaces, the first surface including a first region, a second region, and a third region located between the first region and the second region; A first doped semiconductor layer is disposed in the first region; A second doped semiconductor layer is disposed in the second region, wherein the first doped semiconductor layer and the second doped semiconductor layer have opposite conductivity types; The resistivity of the surface layer of at least a portion of the surface of the semiconductor substrate located in the third region is greater than 20 ohm·cm; Furthermore, H1+H2+W is greater than or equal to 4μm and less than or equal to 300μm, where H1 is the height difference between the surface of the third region and the surface of the first region, H2 is the height difference between the surface of the third region and the surface of the second region, and W is the width of the third region.

2. The back contact battery according to claim 1, wherein, Along the direction from the first region to the second region, the surfaces of the first region, the second region, and the third region are approximately in the same plane, with H1 approximately 0, H2 approximately 0, and 4μm ≤ W ≤ 300μm.

3. The back contact battery according to claim 1, wherein, Along the direction from the second surface to the first surface, the surface of the first region is higher than the surface of the third region.

4. The back contact battery according to claim 3, wherein, 0μm<H1≤20μm.

5. The back contact battery according to claim 3 or 4, wherein, Along the direction from the second surface to the first surface, the surface of the second region is higher than the surface of the third region.

6. The back contact battery according to claim 5, wherein, 0μm<H2≤20μm.

7. The back contact battery according to claim 3, wherein, The semiconductor substrate located in the first region also includes: A first sidewall, which is connected to the surface of the third region and the surface of the first region, respectively; The first sidewall includes a surface that is inclined relative to the first surface; or, the first sidewall is perpendicular to the first surface.

8. The back contact battery according to claim 7, wherein, The semiconductor substrate located in the second region also includes: The second sidewall is connected to the surface of the third region and the surface of the second region, respectively. The second sidewall includes a surface that is inclined relative to the first surface; or, the second sidewall is perpendicular to the first surface.

9. The back contact battery according to claim 8, wherein, When both the first sidewall and the second sidewall include surfaces that are inclined relative to the first surface, the horizontal distance between the first sidewall and the second sidewall gradually decreases along the direction from the first surface to the second surface.

10. The back contact battery according to claim 1, wherein, The width of the back contact battery is greater than or equal to 500 μm and less than or equal to 2000 μm; the ratio of the width of at least one of the third regions to the width of the back contact battery is less than or equal to 0.2%; the width direction of the back contact battery and the width direction of the third region are both consistent with the direction from the first region to the second region.

11. The back contact battery according to claim 1, wherein, The back contact battery further includes a first electrode and a second electrode, wherein the first electrode is electrically connected to the first doped semiconductor layer, and the second electrode is electrically connected to the second doped semiconductor layer; The first electrode includes a contact portion that is in direct contact with the first doped semiconductor layer and a main body portion that is away from the first doped semiconductor layer; The second electrode includes a contact portion that is in direct contact with the second doped semiconductor layer and a main body portion that is away from the second doped semiconductor layer; The distance L1 between the contact portion of the first electrode and the third region is greater than or equal to 80 μm and less than or equal to 500 μm, and the extension direction of the distance L1 is consistent with the direction from the first region to the second region; And / or, the distance L2 between the contact portion of the second electrode and the third region is greater than or equal to 80 μm and less than or equal to 500 μm, and the extension direction of the distance L2 is consistent with the direction from the first region to the second region.

12. The back contact battery according to claim 11, wherein, The ratio of the width of the first doped semiconductor layer to the spacing L1 is greater than or equal to 2, and the width direction of the first doped semiconductor layer is consistent with the direction from the first region to the second region; And / or, the ratio of the width of the second doped semiconductor layer to the spacing L2 is greater than or equal to 2, and the width direction of the second doped semiconductor layer is consistent with the direction from the first region to the second region.

13. The back contact battery according to claim 11, wherein, The distance between the main body of the first electrode and the third region is L3, where L3 ≤ L1, and the direction of the extension of the distance L3 is consistent with the direction from the first region to the second region. And / or, the distance between the main body of the second electrode and the third region is L4, L4≤L2, and the direction of extension of the distance L4 is consistent with the direction from the first region to the second region.

14. The back contact battery according to claim 1, wherein, The ratio of the width W of the third region to the width of the first doped semiconductor layer is less than or equal to 35%. And / or, the ratio of the width W of the third region to the width of the second doped semiconductor layer is less than or equal to 35%.

15. The back contact battery according to claim 1, wherein, The ratio of the area of ​​the semiconductor substrate located in the third region to the area of ​​the first surface is less than or equal to 20%.

16. The back contact battery according to claim 1, wherein, The resistivity of the surface layer of at least a portion of the surface of the semiconductor substrate located in the third region is greater than 80 ohm·cm; And / or, the doping concentration of Group IIIA dopants and the doping concentration of Group VA dopants in the semiconductor substrate located in the third region are both less than 1E14 / cm². -3 .

17. The back contact battery according to claim 1, wherein, Within a depth range of 20 nm, the doping concentration of the doped element in the semiconductor substrate located in the third region is A; within a depth range of 2000 nm, the doping concentration of the doped element in the semiconductor substrate located in the third region is B.

18. The back contact battery according to any one of claims 1 to 17, wherein, The back contact battery further includes a first interface passivation layer, which is disposed between the semiconductor substrate and the first doped semiconductor layer. And / or, the back contact battery further includes a second interface passivation layer disposed between the second doped semiconductor layer and the semiconductor substrate.

19. The back contact battery according to claim 1, wherein, The shortest distance from the first region to the second region along the surface of the third region is the shortest surface distance between the first region and the second region. The shortest surface distance satisfies: H1+H2+W>(150-ρ) / 6, and / or The shortest surface distance satisfies: H1+H2+W<(150-ρ)*5, Where ρ represents resistivity, 0.1 ohm·cm ≤ ρ ≤ 100 ohm·cm.

20. The back contact battery according to claim 1, wherein W and H2 satisfy: lg(W / H2)∈(0.8,3).

21. The back contact battery according to claim 1, wherein, The inward expansion depth of the semiconductor substrate located in the first region is h11, and the inward expansion depth of the semiconductor substrate located in the second region is h21, wherein H1, H2, h11, and h12 are greater than zero and satisfy one or more of the following relationships: H1 > h11; H2 > h21; H1 > H2; h11 > h21; H1 / h11 < H2 / h21.

22. A photovoltaic module, the photovoltaic module comprising: A battery string, wherein the battery string is formed by connecting a plurality of back-contact batteries as described in any one of claims 1 to 21; An encapsulation layer is used to cover the surface of the battery string.

23. A method for manufacturing a back-contact battery, comprising: A semiconductor substrate is provided, the semiconductor substrate including a first surface and a second surface opposite to each other, the first surface including a first region, a second region and a third region located between the first region and the second region; A first doped semiconductor layer is formed in the first region; A second doped semiconductor layer is formed in the second region, wherein the first doped semiconductor layer and the second doped semiconductor layer have opposite conductivity types. The resistivity of the surface layer of at least a portion of the surface of the semiconductor substrate located in the third region is greater than 20 ohm·cm; Furthermore, H1+H2+W is greater than or equal to 4μm and less than or equal to 300μm, where H1 is the height difference between the surface of the third region and the surface of the first region, H2 is the height difference between the surface of the third region and the surface of the second region, and W is the width of the third region.

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