Memory device

Abstract

Provided in the present invention is a memory device, comprising: a substrate; a plurality of memory arrays, provided on the substrate and formed of a stack; and staircase structures provided between the plurality of memory arrays. First dummy pillars (11, 21) that penetrate through a plurality of dielectric layers and conductive layers and do not function as memory cells are provided at edges of the stack; second dummy pillars (12, 22) that are adjacent to the first dummy pillars (11, 21) are provided in the staircase structures; and the second dummy pillars (12, 22) are covered by a filler that fills the interiors of the staircase structures. In the present invention, the introduction of more dummy pillars into the staircase structures can reduce the physical bending and displacement of effective memory arrays caused by stress, while not affecting the size of memory chips, thereby improving the yield and reliability in the vertical direction.

Description

memory devices Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more specifically, to a memory device. Background Technology

[0002] Memory is widely used in integrated circuits to store data. Memory typically includes volatile memory and non-volatile memory. An example of non-volatile memory is NAND flash memory, a low-power, lightweight, and high-performance non-volatile storage product widely used in electronic products. Currently, to further increase storage capacity and reduce the cost per bit, 3D NAND memory with a 3D structure has been proposed. 3D NAND memory forms a multi-layer structure by vertically stacking storage cells.

[0003] Specifically, 3D NAND flash memory features a "staircase" structure, also known as a ladder structure, which is used to connect different memory cells in 3D NAND flash memory. It typically consists of multiple steps, each connected to a word line of a different layer. In 3D NAND flash memory, the "staircase" structure provides a vertical connection method, allowing memory cells on different layers to communicate with each other. This structure allows more memory cells to be accommodated within the same chip area, thus significantly increasing storage capacity.

[0004] 3D NAND flash memory also incorporates memory pillars. A memory pillar is a columnar structure composed of a series of vertically stacked memory cells. These cells are arranged sequentially in a vertical direction using specific manufacturing processes. Each memory cell can independently store data, and data writing, reading, and erasing operations can be achieved by controlling related circuits and voltages. The main function of memory pillars is to significantly increase storage capacity. Compared to traditional planar (2D) NAND flash memory, 3D NAND extends the memory cell layout from a planar arrangement to three-dimensional space, allowing for more memory cells to be accommodated within the same chip area.

[0005] In addition to the aforementioned memory pillars, 3D NAND flash memory also includes dummy pillars. Dummy pillars are auxiliary structures typically formed during the manufacturing process of 3D NAND flash memory. Their primary purpose is to improve the uniformity of the manufacturing of effective memory cells, aiding in the construction of complex 3D memory structures. Dummy pillars are closely adjacent to the memory cells, ensuring the stability and reliability of the memory cells in the vertical direction.

[0006] The quality and structural stability of dummy pillars directly affect the overall stability of 3D NAND flash memory. Defects or deformation in dummy pillars can lead to cell failures, impacting data storage and retrieval. Furthermore, to meet ever-increasing data storage demands, the number of layers in 3D NAND flash memory is constantly increasing. Dummy pillar technology needs to adapt to these higher layer requirements, achieving a denser layout and more precise support positioning within a limited space to improve storage density.

[0007] Specifically, as the number of layers in 3D NAND memory increases, stress becomes increasingly severe. This leads to increased pillar bending at the edges and significant yield drops due to misalignment between upper and lower pillars, insufficient vias, damaged vias, and short circuits between bit lines. While adding more dummy pillars (i.e., further inwards from the stack) can move the pillars away from the edges, suppressing the increase in pillar spacing and thus reducing pillar bending and misalignment, the added dummy pillars occupy excessive effective storage area, resulting in chip size loss. Summary of the Invention

[0008] In view of the above problems, the present invention provides a memory device that can reduce pillar bending without affecting chip size, reduce physical bending and displacement of the effective memory array caused by stress, thereby improving yield and reliability in the vertical direction.

[0009] According to one aspect of the present invention, a memory device is provided, comprising: a substrate; a plurality of memory arrays formed by a stack disposed on the substrate; and a stepped structure disposed between the plurality of memory arrays, the stack comprising a plurality of dielectric layers and conductive layers alternately stacked on top of each other, a first dummy pillar that does not function as a memory cell is disposed at an edge of the stack and penetrates the plurality of dielectric layers and conductive layers, and a second dummy pillar adjacent to the first dummy pillar is disposed in the stepped structure, the second dummy pillar being covered by a filler material filling the stepped structure.

[0010] In some embodiments, each of the memory arrays has a plurality of stack groups arranged in a direction perpendicular to the substrate, each composed of the stack body, and the second dummy pillar is disposed in the stack groups other than the topmost stack group.

[0011] In some embodiments, each of the memory arrays has three stacking groups: a bottom stacking group at the bottom, a middle stacking group above the bottom stacking group, and a top stacking group above the middle stacking group, wherein the second pseudo-pillar is disposed in the bottom stacking group and the middle stacking group.

[0012] In some embodiments, the second dummy pillar disposed in the middle stack group is disposed above the second dummy pillar of the bottom stack group in a manner corresponding to the second dummy pillar disposed in the bottom stack group.

[0013] In some embodiments, the number of the second dummy pillars disposed in the middle stack group is the same as the number of the second dummy pillars disposed in the bottom stack group.

[0014] In some embodiments, the second pseudo-pillar is disposed on opposite sides of the stepped structure.

[0015] In some embodiments, the materials of the first dummy pillar and the second dummy pillar are at least one of polycrystalline silicon, silicon oxide, and silicon nitride.

[0016] In some embodiments, the hardness of the first dummy pillar and the second dummy pillar is greater than the hardness of the filler.

[0017] In some embodiments, the filler material is silicon oxide.

[0018] According to embodiments of the present invention, column bending can be reduced without affecting chip size, thereby reducing physical bending and displacement of the effective memory array caused by stress, and thus improving yield and reliability in the vertical direction. Attached Figure Description

[0019] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings. The drawings are merely exemplary and are not intended to limit the scope of the invention. In the drawings, the same reference numerals denote the same parts in the various figures and embodiments of the present invention, wherein:

[0020] Figure 1 is an example cross-sectional view showing the word line ladder structure of a 3D NAND memory array.

[0021] Figure 2 is a partial cross-sectional view of a memory device according to an embodiment of the present invention.

[0022] Figure 3 is a partial cross-sectional view of a comparative example memory device.

[0023] It should be understood that, for the sake of simplicity and / or clarity, the elements shown in the accompanying drawings are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to others for clarity. Furthermore, to facilitate a better understanding of the concept of the invention, elements known in the art have been omitted from the drawings. The dimensions in the drawings do not represent the precise dimensions and / or scale of the various elements depicted herein. Detailed Implementation

[0024] In the following description, several specific details are set forth. However, the embodiments described herein can be implemented without certain specific details. In particular, well-known structures and techniques are not shown in detail in the specific embodiments to avoid ambiguity in understanding the specification.

[0025] Furthermore, the phrases “in one embodiment,” “in one embodiment,” and / or “in some embodiments” may be used repeatedly throughout this document. These phrases do not typically refer to the same embodiment, but may refer to the same embodiment. Additionally, unless the context otherwise requires, the terms “comprising,” “having,” and “including” are synonyms. The phrases “A or B” and “A / B” mean “(A), (B), or (A and B).”

[0026] It should be understood that ordinal adjectives such as “first,” “second,” “third,” etc., may be used in this document to refer to elements. Unless explicitly stated otherwise, this is only used to distinguish different elements and does not imply that the elements mentioned must be in a given order in time, space, or other respects.

[0027] Furthermore, it should be understood that the terms "up," "down," "left," "right," "front," "back," "top," "bottom," "inner," and "outer" may be used in this text to describe the position of components. This is only for the convenience of explaining the relative positional relationship between components, and the use of these terms does not constitute a limitation on the components.

[0028] When presenting a specific example of a multi-layered structure with two or more layers in a diagram or description, the relative positioning of these layers or the order of the arrangement of the layers as shown reflects the specific implementation of the described or illustrated example, and different relative positioning or order of arrangement of layers is possible.

[0029] Typical flash memory devices may include memory arrays comprising a large number of non-volatile memory cells arranged in rows and columns. In recent years, vertical memory, such as 3D memory, has been developed. 3D flash memory (e.g., 3D NAND memory) devices may include multiple strings of charge storage devices (memory cells) stacked on top of each other. Each group of multiple strings may share multiple access lines called word lines (WLs). Each of the multiple access lines may be coupled (e.g., electrically connected via provided contacts) to a charge storage device (memory cell) corresponding to a respective layer of each string.

[0030] As 3D NAND memory arrays have evolved, they tend to use a greater number of word lines and exhibit greater depth. Therefore, in 3D NAND technology, memory arrays are often created with a stepped word line structure. That is, a 3D NAND memory array typically includes multiple word lines arranged in an interleaved or "stepped" manner, where vertical contact electrodes connect the top interconnect layer to the word lines, with each word line located at a specific distance from the top of the memory array.

[0031] In one embodiment of the present invention, the memory device may include a 3D NAND device. The memory device may refer to the die itself and / or the packaged memory product.

[0032] Figure 1 schematically illustrates an example cross-sectional side view of a word line ladder structure of a 3D NAND memory array. Referring to Figure 1, a stack 100 is depicted in a 3D NAND memory array, formed by alternately stacking multiple conductive layers (e.g., 102a, 102b, 102c, 102d, and 102e) and multiple dielectric layers (e.g., 101a, 101b, 101c, 101d, and 101e) on a support substrate 301. In this document, the conductive layers are typically word line conductors (WL conductors). Although not explicitly shown in the figure, as will be understood by those skilled in the art, multiple memory cells and associated circuit elements, such as silicon-based word lines, floating gates, control gates, non-silicon metal word lines, etc., can be formed in the word line conductors 102a, 102b, 102c, 102d, and 102e. However, it should be understood that although five dielectric layers and five word line conductive layers are shown in Figure 1, this is schematic and only for illustration; in actual memory, there may be more or fewer dielectric layers and word line conductive layers. As shown in Figure 1, the stack 100 may include two or more word line conductive layers (e.g., 102a, 102b, 102c, 102d, and 102e) disposed adjacent to each other. In the stack 100, dielectric layers 101a, 101b, 101c, 101d, and 101e and word line conductive layers 102a, 102b, 102c, 102d, and 102e are stacked alternately. Furthermore, one end of the word line conductive layer (e.g., 102b) and its corresponding dielectric layer 101b extends beyond the corresponding end of the adjacent word line conductive layer (e.g., 102a) and its corresponding dielectric layer 101a disposed above the word line conductive layer 102b and its corresponding dielectric layer 101b, forming a staircase structure.

[0033] Furthermore, in the manufacturing process of 3D NAND memory, as the number of stacked layers increases, challenges arise in manufacturing processes such as high aspect ratio etching and bonding. Therefore, based on the difficulty of the process, the entire memory structure is divided into multiple "decks" (also referred to as "stack groups" in this specification), making the manufacturing process within each "deck" relatively easier to implement and control.

[0034] Specifically, 3D NAND flash memory achieves high-capacity storage by stacking multiple layers of memory cells vertically. These stacked layers are not simply added one on top of the other; instead, they are divided into different "decks" ("stack groups") according to design and process requirements to achieve better results in terms of storage capacity, performance, and optimized manufacturing processes. Each stack group contains a certain number of memory cell layers, which may undergo certain process steps as a whole or possess certain common characteristics and functions during manufacturing. For example, 3D NAND flash memory can be composed of two or more stack groups. Each stack group is composed of the stack shown in Figure 1.

[0035] In one embodiment of the present invention, the memory device 1 is described as having three stacked groups, but the present invention is not limited thereto and may also have two stacked groups.

[0036] Figure 2 is a partial cross-sectional view of a memory device 1 according to an embodiment of the present invention. As shown in Figure 2, the memory device 1 includes: a substrate; a plurality of memory arrays (e.g., memory array A, memory array B, etc. shown in the figure) disposed on the substrate and formed by stacked bodies; and a staircase disposed between the plurality of memory arrays. Furthermore, as shown in Figure 1, the stacked bodies include a plurality of dielectric layers and conductive layers that are alternately stacked on top of each other.

[0037] Each memory array has multiple stacked groups arranged in a direction perpendicular to the substrate (vertical direction), each composed of the stacked bodies shown in FIG1, namely: a bottom stacked group 10 located at the bottom, a middle stacked group 20 located above the bottom stacked group, and a top stacked group 30 located above the middle stacked group. Furthermore, the memory arrays of the present invention are not limited to two, and more than two memory arrays can be used as needed.

[0038] In addition, isolation trenches are formed within the stepped structure. These trenches isolate different memory arrays (memory cells), providing both physical and electrical isolation to prevent interference between adjacent memory arrays. The formation of these isolation trenches typically requires processes such as photolithography and etching. During photolithography, photoresist is coated onto the wafer surface, and then a photolithography machine transfers the designed pattern onto the photoresist. During etching, etching gases or liquids are used to etch away the areas not protected by the photoresist, thus forming the isolation trenches. The width and depth of the isolation trenches usually need to be optimized based on specific process and design requirements. Wider isolation trenches provide better isolation but occupy more chip area; deeper isolation trenches provide better electrical isolation but increase process complexity and cost. Furthermore, to improve the isolation effect, the stepped isolation trenches are filled with a filler (not shown), such as an insulating material like silicon dioxide. The insulating material reduces leakage current and capacitive coupling in the isolation trenches, thereby improving the performance and reliability of the memory cells.

[0039] Each memory array stack includes: memory pillars that function as memory cells and penetrate multiple dielectric and conductive layers; and dummy pillars that do not function as memory cells but improve the uniformity of effective memory cell manufacturing.

[0040] Specifically, a storage column is a columnar structure composed of a series of vertically stacked storage cells. These storage cells are arranged sequentially in a vertical direction using specific manufacturing processes. Each storage cell can independently store data, and data writing, reading, and erasing operations can be achieved by controlling the relevant circuits and voltages. The main function of storage columns is to greatly increase storage capacity. Compared to traditional planar (2D) NAND flash memory, 3D NAND extends the storage cell layout from a planar arrangement to three-dimensional space, allowing more storage cells to be accommodated within the same chip area.

[0041] Pseudopillars are auxiliary structures typically formed during the manufacturing process of 3D NAND flash memory. Their primary function is to improve the uniformity of effective memory cell manufacturing, aiding in the construction of complex 3D memory structures. Pseudopillars are closely adjacent to the memory cells, ensuring the stability and reliability of the memory cells in the vertical direction.

[0042] In a memory device 1 according to an embodiment of the present invention, first dummy pillars 11 and 21, which do not function as memory cells, are provided at the edge of the stack body, penetrating multiple dielectric and conductive layers. These first dummy pillars 11 and 21 are not covered by the filler material in the stepped structure. It should be noted that, although not shown in FIG2, the memory device 1 also includes the aforementioned memory pillars, which are, for example, located on the inner side of the stack body (i.e., opposite to the stepped structure) than the first dummy pillars 11 and 21. The first dummy pillars 11 and 21 include a first dummy pillar 11 provided in the bottom stack group 10 and a first dummy pillar 21 provided in the middle stack group 20.

[0043] Furthermore, in a memory device 1 according to an embodiment of the present invention, second pseudo-pillars 12 and 22 adjacent to the first pseudo-pillars 11 and 21 are provided in a stepped structure. That is, the second pseudo-pillars 12 and 22 are provided in a manner that extends into the stepped structure relative to the first pseudo-pillars 11 and 21. The second pseudo-pillars 12 and 22 include: a second pseudo-pillar 12 disposed in the bottom stack group 10 adjacent to the first pseudo-pillar 11 and disposed in the stepped structure; and a second pseudo-pillar 22 disposed in the middle stack group 20 adjacent to the first pseudo-pillar 21 and disposed in the stepped structure. In addition, unlike the first pseudo-pillars 11 and 21, since the second pseudo-pillars 12 and 22 are disposed in the stepped structure, they are covered by the filler material filled in the stepped structure.

[0044] As the number of layers in a 3D NAND memory device increases, stress becomes increasingly severe. This leads to increased pillar bending at the edges and significant yield drops due to misalignment between upper and lower pillars, insufficient vias, damaged vias, and short circuits between bit lines. While adding more dummy pillars (i.e., further inwards from the stack (opposite to the stepped structure) can move the pillars away from the edges, suppressing the increase in pillar spacing and thus reducing pillar bending and mitigating pillar misalignment, the added dummy pillars occupy excessive effective memory area, resulting in chip size loss.

[0045] According to the above embodiments of the present invention, by making full use of the useless areas in the stepped structure to set up the second pseudo pillars 12 and 22 adjacent to the first pseudo pillars 11 and 21 as described above, and the second pseudo pillars 12 and 22 are covered by the filler in the stepped structure, compared with the case shown in FIG3 where the second pseudo pillars 12 and 22 are not set up, it is possible to reduce pillar bending without affecting the chip size, reduce the physical bending and displacement of the effective memory array caused by stress, thereby improving the yield and reliability in the vertical direction.

[0046] In some embodiments, the second dummy pillar 22 disposed in the middle stack group 20 is positioned directly above the second dummy pillar 12 disposed in the bottom stack group 10, corresponding to the second dummy pillar 12 disposed in the bottom stack group 10. This further reduces pillar bending and improves vertical stability and reliability.

[0047] In some embodiments, the number of second dummy pillars 22 disposed in the middle stack group 20 is the same as the number of second dummy pillars 12 disposed in the bottom stack group 10. Alternatively, the number of second dummy pillars 12 in the bottom stack group 10 may be greater than the number of second dummy pillars 22 in the middle stack group 20, depending on the requirements.

[0048] In some embodiments, the second pseudo-pillars 12 and 22 are disposed on opposite sides of each other in the stepped structure. That is, the second pseudo-pillar 12 is disposed on the memory array A side of the stepped structure, and the second pseudo-pillar 22 is disposed on the memory array B side of the stepped structure opposite to the second pseudo-pillar 12.

[0049] In some embodiments, the material of the first dummy pillars 11 and 21 may be the same as or different from the material of the second dummy pillars 12 and 22, and may be at least one of polycrystalline silicon, silicon oxide and silicon nitride.

[0050] In some implementations, the dummy pillars are made of polycrystalline silicon. Polycrystalline silicon possesses excellent electrical conductivity and semiconductor properties, which can meet some of the electrical and physical requirements of 3D NAND structures. Furthermore, the fabrication process for polycrystalline silicon is relatively mature, making it easy to process and integrate into the manufacturing process of 3D NAND.

[0051] In addition, oxides possess excellent insulating properties, serving as isolation and insulation in 3D NAND flash memory. In some cases, using oxide materials for dummy pillars can help improve the electrical performance and reliability of 3D NAND flash memory, reducing issues such as leakage current. Furthermore, oxide materials are chemically stable and have good compatibility with other materials, making them suitable for use in semiconductor manufacturing processes.

[0052] Silicon nitride (Si3N4) possesses high hardness and strength, providing excellent support for 3D NAND structures when used as dummy pillars. Furthermore, silicon nitride exhibits relatively stable electrical properties, which can improve the performance of 3D NAND to some extent.

[0053] In some embodiments, the hardness of the first dummy pillars 11, 21 and the second dummy pillars 12, 22 is greater than the hardness of the filler in the stepped structure. For example, when the material of the first dummy pillars 11, 21 and the second dummy pillars 12, 22 is polycrystalline silicon, since the hardness of polycrystalline silicon is higher than that of the silicon oxide material layer, and the high-temperature deformation and thermal stress are relatively small, using polycrystalline silicon as the material of the first dummy pillars 11, 21 and the second dummy pillars 12, 22 can further reduce pillar bending, improve stability and reliability in the vertical direction, and also prevent the formation of pitting defects on the filler surface. Furthermore, the forming process is simple and the cost is low.

[0054] In some embodiments, the thickness of the dielectric layer 101 can be 10–50 nm, and the thickness of each dielectric layer 101 can be the same or different from each other. A suitable thickness of the dielectric layer 101 can ensure effective isolation between word line conductors and prevent current breakdown. However, when the dielectric layer is too thick, the resulting final memory structure is too thick, which also increases the difficulty of the etching process. In some embodiments, the thickness of the word line conductive layer 102 can be 20–60 nm, and the thickness of each word line conductive layer 102 can be the same or different from each other. If the thickness of the word line conductive layer 102 is too small, the corresponding height and volume of the memory cell are too small, resulting in insufficient performance of a single memory cell.

[0055] In some embodiments, the material of dielectric layer 101 may include silicon oxide, silicon nitride, high-k materials, or combinations thereof. High-k materials may have a higher dielectric constant than silicon oxide. Silicon oxide (SiO2) may have a dielectric constant of about 3.9, and dielectric layer 101 may include high-k materials having a dielectric constant of about 4 or greater. High-k materials may have a dielectric constant of about 20 or greater. High-k materials may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanium oxide (SrTiO3). In some embodiments, dielectric layer 101 may be formed of a composite layer comprising two or more layers of the aforementioned high-k materials. In some preferred embodiments, the material of dielectric layer 101 may be silicon dioxide.

[0056] In some embodiments, the word line conductive layer 102 may be made of a semiconductor material. The word line conductive layer 102 may include titanium nitride, tungsten, monocrystalline silicon, polycrystalline silicon, or combinations thereof. The word line conductive layer 102 may include an N-type work function material or a P-type work function material. The N-type work function material may have a low work function of approximately 4.5 eV or less, while the P-type work function material may have a high work function of approximately 4.5 eV or greater. In some preferred embodiments, the word line conductive layer 102 may be made of polycrystalline silicon.

[0057] It should be understood that although the above embodiments are described in the context of 3D NAND memory, they can be applied to other 3D memory devices where appropriate.

[0058] Furthermore, it should be understood that although the invention has been described with reference to specific embodiments, those skilled in the art, upon reading the specification, can modify one or more features without departing from the spirit and scope of the invention. Therefore, this specification is not intended to limit the invention. Rather, the scope of the invention is limited only by the appended technical solutions and their equivalents.

Claims

1. A memory device, comprising: include: Substrate; Multiple memory arrays composed of stacked bodies are disposed on the substrate; and A ladder structure is provided between the plurality of memory arrays. The stack comprises multiple dielectric and conductive layers that are stacked alternately on top of each other. A first dummy pillar, which does not function as a storage cell, is provided at the edge of the stack, penetrating the plurality of dielectric and conductive layers. A second pseudo-pillar is provided in the stepped structure, adjacent to the first pseudo-pillar, and the second pseudo-pillar is covered by the filler material in the stepped structure.

2. The memory device according to claim 1, characterized in that: Each of the memory arrays has multiple stacked groups, each composed of the stacked bodies, arranged in a direction perpendicular to the substrate. The second pseudo-pillar is disposed in the stacking groups other than the topmost stacking group.

3. The memory device according to claim 2, characterized in that: Each of the memory arrays has three stacking groups: a bottom stacking group at the bottom, a middle stacking group above the bottom stacking group, and a top stacking group above the middle stacking group. The second pseudo-pillar is disposed in the bottom stack group and the middle stack group.

4. The memory device according to claim 3, characterized in that: The second dummy pillar disposed in the middle stack group is disposed above the second dummy pillar in the bottom stack group in a manner corresponding to the second dummy pillar disposed in the bottom stack group.

5. The memory device according to claim 3, characterized in that: The number of second dummy pillars set in the middle stack group is the same as the number of second dummy pillars set in the bottom stack group.

6. The memory device according to claim 1, characterized in that: The second pseudo-pillar is disposed on opposite sides of the stepped structure.

7. The memory device according to claim 1, characterized in that: The first dummy pillar and the second dummy pillar are made of at least one of polycrystalline silicon, silicon oxide and silicon nitride.

8. The memory device according to claim 1, characterized in that: The hardness of the first pseudo-pillar and the second pseudo-pillar is greater than the hardness of the filler.

9. The memory device according to claim 8, characterized in that: The first and second pseudo pillars are made of polycrystalline silicon, and the filler is made of silicon oxide.

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