Method of manufacturing a photovoltaic device

Abstract

Method of manufacturing a photovoltaic device (10), comprising steps of: a. providing a silicon wafer (1) having a first face, a second face and a plurality of edges; b. forming at least one functional layer (2a, 2b, 3a, 3b) on at least one of said faces and on said edges; c. forming a metal seed grid (6a, 6b) for subsequent deposition of a metallic plating layer (7a, 7b) on at least one of said faces; d. laser cutting said wafer (1) so as to result in edges of a first type and edges of a second type; e. depositing a dielectric layer (5a, 5b) on at least one of said faces and on said edges of said first type and said second type; f. depositing said metallic plating layer (7a, 7b) on said metal seed grid (6a, 6b), wherein said step d is carried out after step b, and said step e is carried out after step.

Description

DescriptionMETHOD OF MANUFACTURING A PHOTOVOLTAIC DEVICETechnical Field

[0001] The present invention relates to the field of photovoltaic devices, i.e. solar cells. More particularly, it relates to a method of manufacturing a photovoltaic device with metallised conductive tracks formed by metal plating.State of the Art

[0002] The standard size of photovoltaic wafers and cells has increased significantly in recent years, growing from the M0 format, with edge dimensions of 156 mm x 156 mm, to the M10 format (182 mm x 182 mm) and even the G12 size (210 mm x 210 mm) or rectangular formats like 210 mm x 182 mm (G12R). To avoid higher resistive losses in modules, cells fabricated on the larger M10, G12 or rectangular G12R wafers are then laser-cut into halves or even smaller segments before being interconnected into modules, see for instance Xu, G. et al., A comparative experimental study on front and back laser cutting technology for mass separation of N-TOPCon crystal silicon solar cells, SOLMAT, 2024. Laser scribing and cleaving (LSC) and thermal laser separation (TLS) are the common techniques.

[0003] In state of the art cell manufacturing processes, screen-printing of silver paste is the standard metallization method for both heterojunction (SHJ) and TOPCon cells. When such processes are applied to the larger wafers mentioned above, the typical processing steps for heterojunction cells are as follows:

[0004] - wet processing steps (including saw damage removal, texturing, cleaning etc.);

[0005] - deposition of a-Si passivating layers, intrinsic and doped;

[0006] - deposition of transparent conductive oxide conductive on both surfaces, with full area deposition;

[0007] - printing of metallisation grid (e.g. silver-paste) with layout adapted for e.g. half-cells;

[0008] - drying and curing of the metallisation grid (typically thermally, at a temperature of around 200°C);

[0009] - laser cutting to separate the individual cells.

[0010] For TOPCon cells with standard metallisation, a simplified process flow, assuming a symmetric structure with poly-Si layers on both sides and bifacial cells, is:

[0011] - wet processing steps (including saw damage removal, texturing, cleaning etc.);

[0012] - deposition of tunnel silicon oxide;

[0013] - deposition of a-Si layers and thermal treatment (>800°C) to form polycrystalline layers and for dopant diffusion into c-Si underneath the tunnel oxide;

[0014] - deposition of dielectric layer (usually SiNx);

[0015] - printing of metallisation grid (e.g. silver-paste) with layout adapted for e.g. cell halves;

[0016] - firing-through of the metallisation grid (at a temperature of around 850°C), possibly using laser enhanced contact optimization (LECO);

[0017] - laser cutting to separate the individual cell segments.

[0018] In the case of electroplated copper metallisation on heterojunction cells according to EP2489076, the steps are as follows:

[0019] - wet processing steps (including saw damage removal, texturing, cleaning etc.);

[0020] - deposition of a-Si passivating layers;

[0021] - deposition of transparent conductive oxide on both surfaces;

[0022] - formation of a seed grid for electrodeposition of copper, e.g. by screen printing of a conductive paste, such as silver-coated copper paste with a silver content below 50%, or even pure copper paste, deposited in narrow, shallow lines;

[0023] - deposition of a dielectric layer as plating mask, the dielectric layer having voids over the seed grid by the nature of the deposition process on the seed grid material;

[0024] - electrodeposition of copper;

[0025] - laser cutting to separate the individual cells.

[0026] During cell processing, when passivating, conducting, or dielectric layers are deposited, the edges of the cells are often covered with the layers being deposited, due to the low directionality of the deposition process. After laser cutting, the laser-cut edges of the resulting cells are no longer covered by these previously deposited layers. This may lead to a loss of passivation and, consequently, a slight decrease in cell efficiency. Additional processes to cover and re-passivate the laser-cut edges may be applied, as described in EP3900052B1 or in Lohmuller, E. et al., TOPCon shingle solar cells: Thermal laser separation and passivated edge technology, PiP, 2023, https: / / doi.Org / 10.1002 / pip.3680

[0027] The obvious solution to avoid having to apply subsequent processes to cover and re-passivate the laser-cut edges is to cut the wafers to the desired size prior to forming the cells thereupon, and hence all deposited layers will be present on all the desired surfaces. However, this means that a larger number of smaller wafers must be handled during the entire process, which is inefficient and goes against the handling advantages of using larger wafers.

[0028] Document US2015 / 075601 discloses a method for manufacturing a photovoltaic device, in which a number of layers are deposited and then all the edges are laser-grooved and then cleaved by being bent and snapped along the groove. Subsequent to this cleavage, an insulating layer is deposited on all edges. This requires four cleavages per segment, increasing the risk of damage, and results in lost substrate in the final segments.

[0029] Document EP4287269 discloses a photovoltaic device with different layer configurations provided on two different edges.

[0030] The aim of the invention is hence to propose a method of manufacturing a photovoltaic device in which the above-mentioned drawbacks of the prior art are at least partially overcome.Disclosure of the invention

[0031] More precisely, the invention relates to a method of manufacturing a photovoltaic device, as defined in claim 1 . This method can be used with any type of PV technology, such as heterojunction (SHJ) cells, TOPCon cells,perovskite-silicon tandem cells(SHJ / PK or TOPCon / PK) , all of which can be monofacial or bifacial, front or rear emitter structures, both-sides-contacted or with interdigitated back contacts (IBC) of any convenient type, and comprises steps of:

[0032] a. providing a silicon wafer having a first face, a second face and a plurality of edges, the wafer being namely a silicon wafer in such a form as to be ready to have various functional layers formed thereon (e.g. having been subject to the usual wet processing steps);

[0033] b. forming at least one functional layer on at least one side of said wafer and on the edges thereof, such as a passivation layer, a tunnelling layer, an intrinsic and / or doped silicon layer, a transparent conductive oxide (TCO) layer, perovskite layer, charge transport layer or similar, which forms part of the usual layer structure of the single-junction cell or of the top cell in a tandem cell and may extend down the edges of the wafer. Indeed, in the case of a tandem cell, the at least one functional layer comprises the bottom cell, possibly having layers contributing to the recombination junction.

[0034] c. forming a metal seed-grid pattern for subsequent deposition of a metallic plating layer on said wafer, e.g. by screen printing of metal paste or sputtering a metal layer with subsequent patterning and etch-back in between the seed-grid. The seed-grid may be dried and optionally also cured, and serves as a seed layer for later metal deposition;

[0035] d. laser cutting said wafer (and the layers thereupon) to form smaller segments, which have edges of a first type (uncut) and edges of a second type (laser cut);

[0036] e. depositing a dielectric layer on said wafer so as to cover at least one face and the edges of the wafer, which is now divided into two or more smaller segments, which results in the dielectric which is deposited over the seedgrid being thinner than that deposited over the remainder of the surface and discontinuous (i.e. with voids), as in EP2489076;

[0037] f. depositing said metallic plating layer on said metal seed grid, e.g. by electroplating or electroless plating of a metal such as copper, nickel, tin or alloys thereof.

[0038] According to the invention, said step d is carried out after step b, and said step e is carried out after step d. It should be noted that, unless otherwise specified, the sequence of the other steps being arranged in any convenient manner that makes technical sense. It should also be noted that the steps mentioned above may be sub-steps of a broader manufacturing step, and as such, other intervening (sub) steps of manufacture (e.g. deposition of other layers) are typically in the application of the method. Also, unless explicitly stated, other intervening layers can be present, and deposition of a layer can hence be directly or indirectly upon the underlying layer and / or wafer.

[0039] As a result of the earlier laser cutting of the larger wafer into smaller segments prior to deposition of the dielectric, the edge of the wafer, which is exposed by laser cutting, is coated by said dielectric layer, protecting and possibly passivating it, without having to resort to an additional process step specifically to address the cut edge, and without loss of substrate due to cleaved-off edges. This results in edges of a first type, which have at least one functional layer between the silicon wafer and the dielectric layer, this at least one functional layer being contiguous over this edge and at least one face of the wafer, and edges of a second type, which have fewer, or zero, functional layers between the dielectric layer and the silicon wafer.

[0040] In one variant, said step d is carried out prior to step c.

[0041] An another variant, step d is carried out after step c, and the steps a-f are preferably carried out in the order a, b, c, d, e, f.

[0042] The invention also relates to a photovoltaic device, typically obtained or obtainable by the method as described above. This photovoltaic device may be of any convenient type of PV technology, such as a heterojunction cell, TOPCon cells, perovskite-heterojunction tandem cells, TOPCon-perovskite tandem cells, all of which can be monofacial or bifacial, double-side- contacted or with interdigitated back contacts, and comprise:

[0043] - a silicon wafer having a first face, a second face, and a plurality of edges of at least a first type (uncut) and at least one edge of a second type (laser cut);

[0044] - at least one functional layer, such as a passivation layer, a tunnelling layer, a doped silicon layer, a transparent conductive oxide, a perovskite (absorber)layer, a charge transporting layer or similar (and forming part of the usual layer structure of the cell or top cell in a tandem), provided upon at least one of said first face and said second face and also upon at least one of said edges. Indeed, in the case of a tandem cell, the at least one functional layer comprises the bottom cell, possibly having layers contributing to the recombination junction;

[0045] - a dielectric layer provided upon at least one of said first face and said second face.

[0046] Said edges of said first type are coated with a dielectric layer separated from a corresponding edge of said silicon wafer by N functional layers which are contiguous with the same functional layer as provided on said face, N being greater than or equal to 1 ;

[0047] And wherein said edge or edges of said second type are coated with said dielectric layer, which is separated from the corresponding edge of said silicon wafer by M functional layers, M having a value between 0 and N-1. These two conditions hold for the whole of the surface of said at least one edge of each of said first and second types, as appropriate. The dielectric layer is hence contiguous over the edges and the face upon which it is deposited. Also, multiple dielectric layers provided on the wafer edges are not excluded.

[0048] This results in the advantages as defined above in the context of the method of the invention.

[0049] Preferably, M is zero, i.e. a dielectric layer is in direct, intimate contact with the laser-cut edge of the wafer.

[0050] The photovoltaic device further comprises a seed-grid upon which said dielectric layer is discontinuous, i.e. has voids exposing the underlying seedgrid material, and a conductive track plated onto said seed-grid as in EP2489076, with the same dielectric layer extending on at least one face and on the edgesBrief description of the drawings

[0051] Further details of the invention will become apparent upon reading the following description, in reference to the appended figures, which illustrate:- Figure 1 : a schematic block diagram of a method according to the invention, in its simplest form;- Figure 2: a schematic block diagram of a variant of the method according to the invention, in its simplest form;- Figure 3: a schematic cross-sectional view of a bifacial heterojunction cell with conductive tracks formed according to EP2489076, laser-cut according to the method of the invention.- Figure 4: a schematic cross-sectional view of a bifacial cell with conductive tracks formed according to EP2489076, conventionally laser-cut.Embodiments of the invention

[0052] Figure 1 illustrates a method according to the invention in its most generic form, which, when applied in the case of a bifacial heterojunction cell with metallised contacts formed as per EP2489076, results in the structure of figure 3. The structural differences for other types of PV technology, whether mono-facial or bifacial, double-side contacted or IBC, single-junction, two- terminal or three-terminal tandems or multijunction are within the understanding of the skilled person. It should be noted that the exact details of the individual functional layers are known in the art for each type of cell, and no particular restrictions apply to their nature. It should be noted that “cell” and “PV device” are interchangeable terms.

[0053] In step 101 , a silicon wafer 1 is provided. Such a wafer has a first face (directed upwards on figure 3), a second face (directed downwards on figure 3), and a number of edges joining the two faces together, as is generally known. Depending on the type of PV device 10 being manufactured, the silicon wafer may be of the intrinsic, p-doped or n-doped type. It should be noted that for simplicity the faces of the wafer 1 have been illustrated as being smooth, but these are usually textured, typically with a pyramid texture, as is generally known.

[0054] In step 103, this wafer 1 is processed as is generally known, in order to at least partially create a PV device 10 of any convenient type, whether singlejunction, tandem, multijunction, single-face or double-face, double-sidecontacted or IBC. Specific examples are discussed in more detail below. This results in the deposition of at least one, typically multiple, functional layers 2a, 3a, 2b, 3b on one or both faces of the wafer, said functional layers 2a, 3a, 2b, 3b being defined as layers which provide a function in the finished cell 10, such as passivation, charge separation, tunnelling, charge transport, absorption (perovskite) or similar. Indeed, in the case of a tandem cell, the functional layers also define a bottom cell. In the illustrated case functional layers 2a (intrinsic a-Si) and 3a (doped a-Si) are deposited on the first face of the wafer 1 and extend also over the edges of the wafer 1. They are hence contiguous over said edge, and the face upon which they are deposited. On the second face, functional layers 2b (intrinsic a-Si) and 3b (doped a-Si) are likewise deposited and also extend over the edges of the wafer 1 . Again, they are hence contiguous over said edge, and the face upon which they are deposited.

[0055] Each side of the wafer 1 is subsequently provided with a corresponding transparent conductive oxide layer 4a, 4b, such as indium tin oxide or other convenient material (typical thickness 20-50 nm) which does not or does not fully extend over the sides of the wafer 1 and the layers 2a, 2b, 3a, 3b situated thereupon, the edges having been masked prior to deposition and / or a directional deposition process having been utilised.

[0056] At the end of step 103, the PV device 10 is at a stage of development to receive a seed-grid 6a, 6b adapted to seed the (electro-)deposition of a metal such as copper, nickel, tin or alloys thereof. This seed-grid 6a, 6b is deposited in step 105, and comprises a pattern defining where the conductive tracks 7a, 7b will be deposited, this pattern being formed of metallic tracks 6a, 6b formed by screen printing of metallic paste (silver, copper, silver-coated copper, or similar), and / or physical vapour deposition / patterning / etch-back or similar, as is suitable for the underlying PV device. Ultimately, the conductive tracks 7a, 7b will be formed thereupon as in EP2489076, as will become apparent below. It should be noted, and will become apparent below, that in some cases step 103 can be split (see in particular figure 2), and / or part of step 105 can be carried out between substeps of step 103 (see the example below of silicon / perovskite tandemcells), and the illustration should not be taken to imply that the illustrated steps are immutable and necessarily carried out completely, one after the other: as is generally the case, unless specifically mentioned, steps can be carried out in any order that makes technical sense, and each step as illustrated may be comprised of a number of sub-steps. Furthermore, the presence of other, non-mentioned sub-steps is not excluded within each step.

[0057] At the termination of step 105, in step 107 the wafer 1 is laser cut into two or more pieces, thereby forming a plurality of sub-wafers I sub-devices (segments), which are not yet completely finalised. The non-laser-cut edge or edges of the sub-devices are of a first type, having at least one functional layer 2a, 3a, 2b, 3b deposited thereupon (see left-side of figure 3), and the laser-cut edges are of a second type, which, immediately after laser-cutting in step 107, have exposed silicon wafer 1 .

[0058] Subsequently, in step 109, each of the two sub-devices is subjected to a deposition of a dielectric layer 5a, 5b such that this layer is discontinuous over the seed-layer 6a, 6b as in EP2489076, and extends over the edges of the wafer 1. Typical thickness of the dielectric layers 5a, 5b is 50-150 nm. This results in that the edges of said first type are provided with a number N of functional layers 2a, 3a, 2b, 3b situated between the first-deposited dielectric layer 5a and the edge of the silicon wafer 1 , where N is greater than or equal to one, and that the edges of said second type are provided with M functional layers between the first-deposited dielectric layer 5a and the lasercut edge of the silicon wafer 1 , where M is less than N. In the illustrated embodiment, M is zero, and the first-deposited dielectric layer 5a is hence in direct, intimate contact with the laser-cut edge of the wafer 1 on edges of said second type. Dielectric layers 5a, 5b may be e.g. PECVD-SiOx, or any other convenient, known material, and typically have a thickness of approximately 100 nm. Optionally, a thermal treatment is carried out after deposition of the dielectric layer.

[0059] Since the example of figure 3 is a bifacial arrangement, two of these dielectric layers 5a, 5b are deposited, each extending over the edges of the wafer 1 , one on top of the other, as illustrated. The first of these to bedeposited, which is the dielectric layer 5a of the first face, is deposited on the exposed silicon of the laser-cut edge of the wafer 1 , in intimate contact therewith, whereas on the un-cut edges, it is deposited on the other layers 2a, 2b, 3a, 3b which are present thereupon. The second dielectric layer 5b to be deposited is likewise deposited on the second face of the wafer 1 , and is on top of the first dielectric layer 5a. Naturally, in the case of a mono-facial arrangement, the layers provided on the second face of the wafer 1 , i.e. those with a “b” suffix in the reference signs, are not present. The dielectric layer 5a, 5b is typically of SiOx, SiNx, SiOxNy or AI2O3. AI2O3 is typically applied in the thickness range 5-20 nm

[0060] Although the laser cutting of step 107 is illustrated in figure 1 as taking place after seed-grid formation in step 105, it can actually be carried out at any convenient point during the processing of step 103, provided that at least one functional layer has been deposited on at least one face of the wafer 1 and on the edges thereof. This variation of the method of the invention is illustrated in figure 2, showing that the PV cell processing step 103 is split between being carried out on the full-size wafer 1 prior to laser cutting in step 107, the remaining operations of step 103 being carried out on the cut segments prior to the seed-grid deposition of step 105.

[0061] Although these methods do not eliminate handling the smaller segments 1 during processing, they minimise it, with a number of processes being carried out on the larger wafer 1 prior to laser-cutting in step 107.

[0062] The difference in the resulting PV device 10 manufactured according to a method of the invention, namely the variant of figure 1 , compared to lasercutting after formation of the conductive tracks 7a, 7b, is clearly visible by comparing figures 3 and 4. In this latter case, the exposed laser-cut edge is clearly visible on the right of figure 4, which either requires being tolerated in the final module, or requires being passivated in a subsequent step. All other process steps have remained the same between the two figures, and hence the difference relates only to the moment at which laser cutting occurs.

[0063] Several nonlimiting applications of the methods of figure 1 to different specific types of PV technologies will now be described below.

[0064] In the case of bifacial heterojunction cells 10, step 101 includes wet processes with saw damage removal, texturing and cleaning, e.g. on n-type wafer, so as to provide a wafer 1 suitable for further processing.

[0065] In step 103, deposition is carried out of amorphous silicon layers 2a, 2b, 3a, 3b, intrinsic and doped, usually by PECVD, e.g. a-Si(i) and a-Si(p) on the rear side and a-Si(i) and a-Si(n) on the front side, followed by deposition of transparent conductive oxide (TCO) 4a, 4b on both sides, typically by PVD as is generally known. At least one of the PECVD-deposited layers 2a, 2b, 3a, 3b, for instance an a-Si(i) passivation layer 2a, 2b, occurs also on the edges of the wafer 1 , contiguous with the deposition on the corresponding face thereof, since PECVD is a relatively non-directional deposition technique. The PVD TCO layer, however, typically does not fully extend over the edges of the wafer 1 , since the edge is masked and / or the deposition is directional. This avoids short-circuits between the front and back of the cell.

[0066] Then, in step 105, formation of a seed-grid 6a, 6b is carried out, usually screen-printing of silver-coated-copper or pure copper paste. This material is at least dried, typically at approximately 150°C, or drying and curing at approximately 200°C is carried out. It should note that the seed-grid 6a, 6b alone does not have sufficient conductivity for good cell performance, hence why the subsequent deposition of step 111 is carried out, in order to provide greater conductivity.

[0067] In step 107, the full-size wafer 1 is laser cut, leaving the silicon of the wafer 1 exposed on the laser-cut edge.

[0068] Subsequently, on the cell segments, in step 109 deposition of a dielectric layer 5a, 5b on the surface and also on the edges of the wafer is carried out, usually PECVD with and optional annealing at 200°C, on both sides of the wafer (or only on a single side in the case of a monofacial PV device). PECVD is a relatively non-directional coating technique, which is why the dielectric layer is also deposited on the edges, contiguous with the deposition on the face, thereby protecting and possibly passivating the laser-cut edge. Itshould be noted that the TCO and the dielectric layer form together the antireflective coating, the thicknesses of both layers being accordingly adjusted. As mentioned above, this dielectric layer 5a, 5b has voids where it is deposited over the corresponding part of the seed-grid 6a, 6b, as described in EP2489076.

[0069] Subsequently, and again on the cell segments, in step 111 , conductive tracks 7a, 7b are formed over the corresponding parts of the seed-grid 6a, 6b by deposition of metal such as typically copper, nickel, tin or alloys thereof, by electroplating or electroless plating, to form highly conductive lines, which may be capped with a subsequently-deposited capping layer 8a, 8b (e.g. electrodeposited or electroless tin or other suitable metal). The conductive tracks 7a, 7b are hence distinct from the underlying seed-grid 6a, 6b.

[0070] The modifications of this method to follow the flow diagram of figure 2 are within the reach of the skilled person. For instance, laser cutting step 107 may be carried out at an intermediate point during step 103, e.g. after deposition of the a-Si(i) layers 2a, 2b or after deposition of the doped a-Si layers 3a, 3b. In the former case, the doped a-Si layers 3a, 3b will be present on the laser cut edge of the finished cell, i.e. on the edge of the second type, whereas all the layers 2a, 2b, 3a, 3b will be present on the uncut edge of the first type.

[0071] In the context of TOPCon cells, the details of the method of figure 1 are as follows (the process flow being simplified for a symmetric cell structure with passivating poly-Si layers on both sides):

[0072] In step 101 , the wafer 1 is wet processed as mentioned above in the context of heterojunction cells.

[0073] Subsequently, step 103 includes deposition of tunnel oxide, e.g. by a wet process, for example in an ozone solution or in a thermal process, and deposition of passivating layers, e.g. poly-Si by PECVD or PVD, e.g. by deposition of amorphous Si layers and subsequent annealing (usually >800°C).

[0074] Subsequently, in step 105, the seed-grid is deposited, usually by screen printing of metal paste and firing or sputtering a metal layer, patterning andetch-back in between the grid pattern. As before, the conductivity of the seed-grid is not sufficient for good cell performance, hence the later plating in step 111.

[0075] Subsequently, in step 107, laser cutting is carried out to form sub-cells.

[0076] Then, in step 109, a dielectric layer is deposited on the surface and also on the edges of the cut wafer, usually sequential deposition, one side after another, by PECVD and optionally annealing, usually at <500°C.

[0077] Then, in step 111 , deposition of metal 7a, 7b such as typically copper, nickel, tin or alloys thereof occurs on the seed-layers by electroplating or electroless plating, to form highly conductive lines, which may be capped with a subsequently-deposited capping layer 8a, 8b (e.g. electrodeposited or electroless tin or other suitable metal). In this case, sequential deposition is typically carried out, one side after another, in a horizontal (single side) line, or alternatively simultaneous deposition on both sides in a vertical plating line can be carried out.

[0078] The resulting cell hence has the tunnel oxide and passivating layers under the dielectric layer on the uncut edges, the first-deposited dielectric layer being in direct contact with the silicon of the wafer on the cut edge. The resulting PV device hence corresponds to that of figure 3 but with the different layers as discussed above.

[0079] In the case of modifying this process such that it corresponds to that of figure 2, step 107 can be carried out part way through step 103, e.g. after deposition of the tunnel oxide layer, with deposition of the passivating layers and formation of the seed-grid hence being carried out on the sub-cells after laser cutting in step 107. In such a case, the tunnel oxide layer is only present on the uncut edges, and the passivating layers are deposited on the laser cut edge or edges.

[0080] In the case of perovskite / silicon tandem cells with a heterojunction bottom cell (see for instance De Bastiani, M. et al., Bifacial perovskite / silicon tandem solar cells, Joule 6, 1431-1445, (2022), https: / / doi.Org / 10.1016 / j.joule.2022.05.014), the following describes anexemplary sequence for a bifacial tandem manufactured according to the method of figure 1 :

[0081] In step 101 , the wafer wet processed with saw damage removal, texturing and cleaning on Si wafer, e.g. n-type doped wafer, the wafer being fully immersed in the solution, such that the process occurs on both sides of the wafer.

[0082] In step 103, firstly deposition occurs of intrinsic amorphous Si passivation layers and doped amorphous Si layer, e.g. on the back a-Si(p) for rear-side emitter and on the front a-Si(n). Then, on the front of the wafer, formation of recombination junction towards the perovskite top cell, e.g. a-Si(n+), together with a TCO is carried out, with additional nanocrystalline layers being a possibility. On the rear of the wafer, TCO deposition is carried out. One or more of these functional layers is also contiguously deposited on the wafer edges, as in the heterojunction case.

[0083] Subsequently, and representing a part of step 105 which is intermeshed with step 103, on the rear, a seed-grid for electrodeposition is formed, usually screen-printing of silver-coated-copper or pure copper paste, which is at least dried at ~150°C, or it may be dried and cured at ~200°C. As before, the seed-grid alone does not have sufficient line conductivity for good cell performance. Optionally, this step can be carried out after formation of the top cell, together with seed-grid formation on the top cell.

[0084] Subsequently, a protection foil is applied to the rear of the wafer, temporarily applied during perovskite top cell processing in step 103, and the perovskite top cell is formed, by depositing a hole transporting layer (HTL), e.g. Me- 4PACz, depositing a perovskite absorber, forming an electron transporting layer (ETL) stack, e.g. LiF, C60, SnOx, and deposition of a TCO layer, e.g. indium-tin-oxide, typically with a thickness 20-50 nm (less than required for an anti-reflective coating, which can be completed by the dielectric layer).

[0085] Subsequently, the remainder of step 105 is carried out, namely formation of a seed-grid for electrodeposition on the front of the top cell with metal paste as described above, typically at a maximum temperature of 150°C due to the thermal sensitivity of perovskites. As mentioned above, the seed-grid on therear of the bottom cell and the seed-grid on the front of the top cell can be printed together at this stage.

[0086] Subsequently, in step 107, the partially-formed tandem cell is laser-cut into a plurality of segments.

[0087] Subsequently, in step 109, one or more dielectric layers is / are deposited on the segments, usually sequentially on both sides and also on the edges, usually PECVD and with optional annealing. It should be noted that also the TCO on the front of the top cell and the dielectric layer may together form the antireflective coating, the thicknesses of both layers being accordingly adjusted.

[0088] Subsequently, formation of the conductive tracks on the seed-grid is carried out as described above.

[0089] Again, this method can be modified to correspond to that of figure 2, by moving the step 107 into step 103, e.g. after deposition of SnOx and / or another layer or layers. In such a case, also the TCO could be deposited at the same stage on both sides of the tandem and followed by seed-grid printing also on both sides.

[0090] In the case of a bifacial TOPCon-perovskite-tandem (such as described in Y. Wu et al., 27.6% Perovskite / c-Si Tandem Solar Cells Using Industrial Fabricated TOPCon Device, Adv. Energy Mater. 2022, DOI: 10.1002 / aenm.202200821), an exemplary sequence according to the method of figure 1 is as follows.

[0091] In step 101 , the wafer is prepared as before, the wafer being e.g. an n-type doped wafer.

[0092] In step 103, first the TOPCon bottom cell is first formed: a tunnel oxide layer is formed on both faces of the wafer, followed by deposition of passivating layers, e.g. on the back poly-Si(p) for rear-side emitter and on the front poly- Si(n) and thermal treatment (usually >800°C). At least one of these functional layers is deposited contiguously on the sides of the wafer.

[0093] Subsequently, on the front side, a recombination junction towards the perovskite top cell, e.g. a TCO layer, is formed, and on the rear side a metal seed-grid for electrodeposition or electroless deposition is deposited formed,e.g. by screen printing of metal paste and firing or by sputtering a metal layer over the full surface, patterning and etching-back in between the grid pattern. Naturally, other processes are possible.

[0094] Subsequently, a dielectric layer (stack) is deposited (on the rear side of the bottom cell), e.g. Al2O3 / SiNx, with optional thermal treatment at a temperature <500°C, the temperature taking into account the thermal stability of layers on the front side and interface passivating layer to sputtered seed-grid at the rear.

[0095] The rear side of the cell is temporarily protected for the duration of top cell processing, e.g. with a protective film.

[0096] Subsequently, and still in step 103 a perovskite top cell is formed, first by depositing optional additional layers forming the recombination junction, deposition of a hole transporting layer (HTL), deposition of the perovskite absorber, and formation of the electron transporting layer (ETL). Subsequently, a TCO is deposited, e.g. indium-tin-oxide.

[0097] Subsequently, in step 105, a seed-grid for electrodeposition is deposited, e.g. by screen printing of metal particle paste and curing, while not exceeding 150°C due to the thermal sensitivity of the perovskite.

[0098] Subsequently, in step 107, the cell is laser-cut into sub-cells / segments.

[0099] Subsequently, in step 109, on the cells segments a dielectric layer is deposited on the front side (of the top cell) and also on the edges of the wafer, usually by PECVD, with optional annealing.

[0100] Subsequently, metal plating is applied to both sides by electroplating or electroless deposition.

[0101] In the alternative case in which a TCO layer would be applied on the rear side of the cell, the sequence for plating on the bottom cell would be as on heterojunction cells. TCO could be deposited on both side at the same stage and followed by seed-grid printing also on both sides.

[0102] In the case of a modification of this method to that of figure 2, step 107 could e.g. be moved to after deposition of SnOx, and / or other layers, the remaining sub-steps of step 103 being carried out after laser cutting, on the sub-cells I segments.

[0103] Although the invention has been described in terms of specific embodiments, variations thereto are possible without departing from the scope of the invention as defined in the appended claims.

Claims

Claims1. Method of manufacturing a photovoltaic device (10), comprising steps of: a. providing a silicon wafer (1 ) having a first face, a second face and a plurality of edges; b. forming at least one functional layer (2a, 2b, 3a, 3b) on at least one of said faces and on said edges; c. forming a metal seed grid pattern (6a, 6b) for subsequent deposition of a metallic plating layer (7a, 7b) on at least one of said faces; d. laser cutting said wafer (1) so as to result in edges of a first type and edges of a second type; e. depositing a dielectric layer (5a, 5b) on at least one of said faces and on said edges of said first type and said second type; f. depositing said metallic plating layer (7a, 7b) on said metal seed grid (6a, 6b), wherein said step d is carried out after step b, and said step e is carried out after step d.

2. Method according to claim 1 , wherein said step d is carried out prior to step c.

3. Method according to claim 1 , wherein said step d is carried out after step c.

4. Method according to claim 3, wherein steps a-f are carried out in the order a, b, c, d, e, f.

5. Method according to any preceding claim, wherein in step d said wafer (1) is cut into two or more segments, and said step e is carried out on all of said segments.

6. Method according to any preceding claim, wherein said at least one functional layer (2a, 2b, 3a, 3b) is one or more of:- a passivation layer;- a tunnelling layer;- a doped silicon layer.- a transparent conductive oxide- an carrier transport layer (stack): organic, inorganic or a mixture thereof- a perovskite absorber;- a bottom cell.

7. Method according to any preceding claim, wherein said photovoltaic cell (10) is one of:- a heterojunction cell;- a TOPCon cell;- a perovskite-silicon tandem cell, such as a heterojunction-perovskite tandem or TOPCon-perovskite tandem cell.

8. Photovoltaic device (10) comprising:- a silicon wafer (1) having a first face, a second face, and a plurality of edges of at least a first type and at least one edge of a second type;- at least one functional layer (2a, 2b, 3a, 3b) provided upon at least one of said first face and said second face and on at least one of said edges;- a dielectric layer (5a, 5b) provided upon at least one of said first face and said second face; wherein said edges of said first type are coated with said dielectric layer (5a, 5b), this latter being separated from said edge of said silicon wafer by N functional layers (2a, 2b, 3a, 3b) which are each contiguous on said edges and said face, N being greater than or equal to 1 , this condition holding for the whole of said edges of said first type; and wherein said at least one edge of said second type is coated with a dielectric layer (5a, 5b) separated from said edge of said silicon wafer (1) by M functional layers, M having a value between 0 and N-1 , this condition holding for the whole of said edges of said second type.

9. Photovoltaic device (10) according to the preceding claim, wherein M=0.

10. Photovoltaic device (10) according to one of claims 8-9, further comprising a seed-grid (6a, 6b) upon which said dielectric layer (5a, 5b) is discontinuous, and a conductive track plated onto said seed-grid.11 . Photovoltaic device according to one of claims 8-10, wherein said functional layer is layer is one or more of:- a passivation layer;- a tunnelling layer;- a doped silicon layer.- a transparent conductive oxide- an carrier transport layer (stack): organic, inorganic or a mixture thereof- a perovskite absorber,- a bottom cell.

12. Photovoltaic device according to one of claims 8-11 , wherein said photovoltaic cell is one of:- a heterojunction cell;- - a TOPCon cell;- a perovskite-silicon tandem cell, such as a heterojunction-perovskite tandem or TOPCon-perovskite tandem cell.

13. Photovoltaic device according to one of claims 8-12, wherein said dielectric layer on said edges is contiguous with said dielectric layer on said face.

14. Photovoltaic device according to one of claims 8-13, obtained or obtainable by the method of one of claims 1 -7.

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