Semiconductor device, and method for manufacturing semiconductor device

Abstract

Provided is a semiconductor device having little electrical characteristic variation between transistors. The present invention has a transistor and first through third insulating layers. The transistor has first through third conductive layers, a semiconductor layer, and a fourth insulating layer. The first insulating layer overlaps the first conductive layer. The second conductive layer is located on the first insulating layer. The second insulating layer is located on the second conductive layer. The third conductive layer is located on the second insulating layer. The third insulating layer contacts each of the upper surface and a side surface of the first conductive layer, a side surface of the first insulating layer, a side surface of the second conductive layer, a side surface of the second insulating layer, and the upper surface and a side surface of the third conductive layer. The third insulating layer has a first opening overlapping each of the first and second conductive layers. The fourth insulating layer contacts each of a side surface of the first insulating layer, a side surface of the second conductive layer, and a side surface of the second insulating layer within the first opening. The semiconductor layer is included in the first opening and contacts each of the upper surface of the first conductive layer, the upper surface of the fourth insulating layer, and the upper surface of the third conductive layer.

Description

Semiconductor device and method for manufacturing a semiconductor device.

[0001] One aspect of the present invention relates to a semiconductor device and a method for manufacturing the same. Another aspect of the present invention relates to a transistor and a method for manufacturing the same. Another aspect of the present invention relates to a display device having a semiconductor device.

[0002] It should be noted that one aspect of the present invention is not limited to the above-mentioned technical field. Examples of technical fields of one aspect of the present invention include semiconductor devices, display devices, light-emitting devices, energy storage devices, memory devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), electronic devices having the same, methods for driving them, or methods for manufacturing them.

[0003] In this specification, a semiconductor device refers to a device that utilizes semiconductor properties, including circuits containing semiconductor elements (transistors, diodes, photodiodes, etc.), devices having such circuits, etc. It also refers to any device that can function by utilizing semiconductor properties. For example, integrated circuits, chips equipped with integrated circuits, and electronic components with chips housed in packages are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, and electronic devices are themselves semiconductor devices, and may each have a semiconductor device.

[0004] Semiconductor devices containing transistors are widely used in electronic devices. For example, in display devices, reducing the area occupied by transistors can reduce the pixel size and improve resolution. Therefore, there is a demand for miniaturized transistors.

[0005] As devices requiring high-definition display capabilities, for example, devices for virtual reality (VR), augmented reality (AR), substitute reality (SR), and mixed reality (MR) are being actively developed.

[0006] As display devices, for example, light-emitting devices having organic EL (Electroluminescence) elements or light-emitting diodes (LEDs) have been developed.

[0007] Patent Document 1 discloses a high-definition display device using an organic EL element (also known as an OLED (Organic LED)).

[0008] International Publication No. 2016 / 038508

[0009] Takashi Koida, "High-Mobility Transparent Conductive Film," National Institute of Advanced Industrial Science and Technology (AIST), AIST Photovoltaic Power Generation Research Results Presentation 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf>

[0010] To further increase the resolution of display devices, further miniaturization of the semiconductor devices they contain is required. However, the more miniaturization is pursued for the transistors in the semiconductor devices, the more difficult it becomes to ensure good electrical characteristics, maintain processing accuracy, and reduce variations in electrical characteristics between transistors.

[0011] One aspect of the present invention aims to provide a semiconductor device having a transistor of a very small size and a method for manufacturing the same. Alternatively, one aspect of the present invention aims to provide a semiconductor device having a transistor with a short channel length and a method for manufacturing the same. Alternatively, one aspect of the present invention aims to provide a semiconductor device having a transistor with a large on-current and a method for manufacturing the same. Alternatively, one aspect of the present invention aims to provide a semiconductor device having a transistor with high field-effect mobility and a method for manufacturing the same. Alternatively, one aspect of the present invention aims to provide a semiconductor device having a transistor with good electrical characteristics and a method for manufacturing the same. Alternatively, one aspect of the present invention aims to provide a semiconductor device with small variations in electrical characteristics between transistors and a method for manufacturing the same.

[0012] Alternatively, one aspect of the present invention aims to provide a semiconductor device that operates at high speed and a method for manufacturing the same. Alternatively, one aspect of the present invention aims to provide a semiconductor device that occupies a small area and a method for manufacturing the same. Alternatively, one aspect of the present invention aims to provide a semiconductor device or display device with low power consumption and a method for manufacturing the same. Alternatively, one aspect of the present invention aims to provide a high-definition display device. Alternatively, one aspect of the present invention aims to provide a method for manufacturing a semiconductor device or display device with high productivity. Alternatively, one aspect of the present invention aims to provide a novel transistor, semiconductor device, display device, or a method for manufacturing the same.

[0013] Furthermore, the description of these problems does not preclude the existence of other problems. One aspect of the present invention does not necessarily have to solve all of these problems. It is possible to extract other problems from the description in the specification, drawings, and claims.

[0014] One aspect of the present invention includes a transistor, a first insulating layer, a second insulating layer, and a third insulating layer, wherein the transistor has a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a semiconductor layer, a fourth insulating layer, and a fifth insulating layer, wherein the first insulating layer is located on the first conductive layer such that it has a region overlapping with the first conductive layer, the second conductive layer is located on the first insulating layer, the second insulating layer is located on the second conductive layer, the third conductive layer is located on the second insulating layer, and the third insulating layer is located on the first conductive layer, the first insulating layer, the second insulating layer, and the third conductive layer, and the upper and side surfaces of the first conductive layer, the side surfaces of the first insulating layer, and the second conductive layer The semiconductor device is configured such that the semiconductor layer is located on the first conductive layer, the fourth insulating layer, and the third conductive layer, and is in contact with the sides of the first insulating layer, the sides of the second insulating layer, and the top and sides of the third conductive layer, with the third insulating layer having a first opening that overlaps with the first conductive layer and the third conductive layer, and the fourth insulating layer is located on the fifth insulating layer, and is in contact with the top surface of the first conductive layer, the top surface of the fourth insulating layer, and the top surface of the third conductive layer, with the semiconductor layer being contained within the first opening, and is in contact with the top surface of the first conductive layer, the top surface of the fourth insulating layer, and the top surface of the third conductive layer, and the fifth insulating layer is located on the semiconductor layer, with the fourth conductive layer having a region that overlaps with the semiconductor layer.

[0015] Furthermore, in the above, the semiconductor layer is preferably an oxide semiconductor layer having indium, the second insulating layer has a sixth insulating layer, a seventh insulating layer on the sixth insulating layer, and an eighth insulating layer on the seventh insulating layer, the first insulating layer, the sixth insulating layer, and the eighth insulating layer each have silicon and nitrogen, the seventh insulating layer has silicon and oxygen, and the third insulating layer is preferably one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, zinc gallium oxide, aluminum nitride, silicon nitride, and silicon nitride oxide.

[0016] Furthermore, in the above, it is preferable that the first insulating layer comprises a ninth insulating layer, a tenth insulating layer on the ninth insulating layer, and an eleventh insulating layer on the tenth insulating layer, wherein the ninth insulating layer and the eleventh insulating layer each contain silicon and nitrogen, and the tenth insulating layer contains silicon and oxygen.

[0017] Furthermore, in the above, it is preferable that the fourth insulating layer is in contact with the upper surface of the ninth insulating layer.

[0018] Furthermore, in the above, it is preferable that a 12th insulating layer is located below the first conductive layer, the upper surface of the 12th insulating layer is in contact with the first conductive layer, and the 12th insulating layer is one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, zinc gallium oxide, aluminum nitride, silicon nitride, and silicon nitride oxide.

[0019] Furthermore, in the above, the first insulating layer, the second conductive layer, the second insulating layer, and the third conductive layer are preferably provided in an island-like manner, and their respective ends coincide or substantially coincide in a plan view.

[0020] Furthermore, in the above, it is preferable that the second conductive layer is divided by a slit reaching the first conductive layer, and that the fourth insulating layer, semiconductor layer, fifth insulating layer, and fourth conductive layer are stacked in this order on a pair of opposing sides with respect to the slit.

[0021] Furthermore, in the above, it is preferable that the first insulating layer, the second conductive layer, the second insulating layer, and the third conductive layer each have a second opening that reaches the first conductive layer, and that within the second opening, there is a region where the fourth insulating layer, the semiconductor layer, the fifth insulating layer, and the fourth conductive layer are laminated in this order with respect to the side surface of the first insulating layer, the side surface of the second conductive layer, and the side surface of the second insulating layer.

[0022] Furthermore, in the above, the first opening and the semiconductor layer each have regions that overlap with the first corners of the first insulating layer, the second conductive layer, the second insulating layer, and the third conductive layer in a plan view, and it is preferable that the first corners are corners whose interior angle in a plan view is greater than 0 degrees and less than 180 degrees.

[0023] Furthermore, in the above, the first opening and the semiconductor layer each have regions that overlap with the second corners of the first insulating layer, the second conductive layer, the second insulating layer, and the third conductive layer in a plan view, and it is preferable that the second corners have an interior angle greater than 180 degrees and less than 360 degrees in a plan view.

[0024] Furthermore, in the above, it is preferable that the fourth insulating layer comprises a thirteenth insulating layer and a fourteenth insulating layer on the thirteenth insulating layer, wherein the thirteenth insulating layer comprises silicon and nitrogen, and the fourteenth insulating layer comprises silicon and oxygen.

[0025] Furthermore, in one aspect of the present invention, a first conductive layer is formed, a first insulating film, a first conductive film, a second insulating film, and a second conductive film are deposited on the first conductive layer in this order, the first insulating film, the first conductive film, the second insulating film, and the second conductive film are processed to have a region overlapping with the first conductive layer to form a first insulating layer, a second conductive layer, a second insulating layer, and a third conductive layer, respectively, a third insulating film is deposited in contact with the upper and side surfaces of the first conductive layer, the side surfaces of the first insulating layer, the side surfaces of the second conductive layer, the side surfaces of the second insulating layer, and the upper and side surfaces of the third conductive layer, a part of the third insulating film is removed to form an opening that overlaps with the first conductive layer and the third conductive layer, and a third insulating layer having an opening is formed from the third insulating film, and the third This is a method for manufacturing a semiconductor device, comprising: forming a fourth insulating film in contact with the upper surface of the insulating layer, the upper surface of the first conductive layer, the side surface of the first insulating layer, the side surface of the second conductive layer, the side surface of the second insulating layer, and the upper and side surfaces of the third conductive layer; removing a portion of the fourth insulating film to form a fourth insulating layer in contact with the side surface of the first insulating layer, the side surface of the second conductive layer, and the side surface of the second insulating layer; forming a metal oxide film in contact with the side and upper surface of the third insulating layer, the upper surface of the first conductive layer, the upper surface of the fourth insulating layer, and the upper surface of the third conductive layer; processing the metal oxide film to form a semiconductor layer so that it is contained within the opening in a plan view; forming a fifth insulating layer on the semiconductor layer; and forming a fourth conductive layer on the fifth insulating layer such that it has a region that overlaps with the semiconductor layer.

[0026] Furthermore, in the above, it is preferable to use anisotropic etching to remove a portion of the fourth insulating film.

[0027] According to one aspect of the present invention, a semiconductor device having a small-sized transistor and a method for manufacturing the same can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device having a transistor with a short channel length and a method for manufacturing the same can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device having a transistor with a large on-current and a method for manufacturing the same can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device having a transistor with high field-effect mobility and a method for manufacturing the same can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device having a transistor with good electrical characteristics and a method for manufacturing the same can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with small variations in electrical characteristics between transistors and a method for manufacturing the same can be provided.

[0028] Alternatively, according to one aspect of the present invention, a high-speed semiconductor device and a method for manufacturing the same can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with a small footprint and a method for manufacturing the same can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device or display device with low power consumption and a method for manufacturing the same can be provided. Alternatively, according to one aspect of the present invention, a high-definition display device can be provided. Alternatively, according to one aspect of the present invention, a method for manufacturing a semiconductor device or display device with high productivity can be provided. Alternatively, according to one aspect of the present invention, a novel transistor, semiconductor device, display device, or a method for manufacturing the same can be provided.

[0029] Furthermore, the description of these effects does not preclude the existence of other effects. One aspect of the present invention does not necessarily have to possess all of these effects. Other effects can be extracted from the description, drawings, and claims.

[0030] Figure 1A is a plan view showing an example of a semiconductor device. Figures 1B and 1C are cross-sectional views showing an example of a semiconductor device. Figures 2A and 2B are perspective views showing an example of a semiconductor device. Figure 3 is a perspective view showing an example of a semiconductor device. Figure 4A is a cross-sectional view showing an example of a semiconductor device. Figure 4B is a plan view showing an example of a semiconductor device. Figures 5A, 5B, 5C, and 5D are cross-sectional views showing an example of a semiconductor device. Figures 6A, 6B, 6C, and 6D are cross-sectional views showing an example of a semiconductor device. Figure 7A is a plan view showing an example of a semiconductor device. Figures 7B and 7C are cross-sectional views showing an example of a semiconductor device. Figure 8A is a plan view showing an example of a semiconductor device. Figures 8B and 8C are cross-sectional views showing an example of a semiconductor device. Figure 9A is a plan view showing an example of a semiconductor device. Figures 9B and 9C are cross-sectional views showing an example of a semiconductor device. Figure 10A is a plan view showing an example of a semiconductor device. Figures 10B and 10C are cross-sectional views showing an example of a semiconductor device. Figure 11A is a plan view showing an example of a semiconductor device. Figures 11B and 11C are cross-sectional views showing an example of a semiconductor device. Figure 12A is a plan view showing an example of a semiconductor device. Figures 12B and 12C are cross-sectional views showing an example of a semiconductor device. Figure 13A is a plan view showing an example of a semiconductor device. Figures 13B and 13C are cross-sectional views showing an example of a semiconductor device. Figure 14A is a plan view showing an example of a semiconductor device. Figures 14B and 14C are cross-sectional views showing an example of a semiconductor device. Figure 15A is a plan view showing an example of a semiconductor device. Figures 15B and 15C are cross-sectional views showing an example of a semiconductor device. Figure 16A is a plan view showing an example of a semiconductor device. Figures 16B and 16C are cross-sectional views showing an example of a semiconductor device. Figure 17A is a plan view showing an example of a semiconductor device. Figures 17B and 17C are cross-sectional views showing an example of a semiconductor device. Figures 18A and 18B illustrate the carrier concentration dependence of hole mobility. Figure 18C is a cross-sectional view illustrating an indium oxide film. Figures 19A, 19B, 19C, 19D, and 19E are cross-sectional views showing an example of a semiconductor device fabrication method. Figures 20A, 20B, 20C, and 20D are cross-sectional views showing an example of a semiconductor device manufacturing method.Figures 21A, 21B, 21C, and 21D are cross-sectional views showing an example of a semiconductor device manufacturing method. Figures 22A, 22B, 22C, and 22D are cross-sectional views showing an example of a semiconductor device manufacturing method. Figures 23A and 23B are perspective views showing an example of a semiconductor device manufacturing method. Figures 24A and 24B are perspective views showing an example of a semiconductor device manufacturing method. Figures 25A and 25B are perspective views showing an example of a semiconductor device manufacturing method. Figures 26A and 26B are perspective views showing an example of a semiconductor device manufacturing method. Figure 27 is a perspective view showing an example of a semiconductor device manufacturing method. Figure 28 is a block diagram of a display device. Figures 29A, 29B, 29C, and 29D are circuit diagrams of a pixel circuit. Figures 30A, 30B, and 30C are circuit diagrams of a pixel circuit. Figure 31 is a perspective view showing an example of a display device. Figures 32A and 32B are cross-sectional views showing an example of a display device. Figure 33 is a cross-sectional view showing an example of a display device. Figures 34A, 34B, and 34C are cross-sectional views showing an example of a display device. Figures 35A and 35B are cross-sectional views showing an example of a display device. Figure 36 is a cross-sectional view showing an example of a display device. Figures 37A, 37B, 37C, and 37D are diagrams showing an example of an electronic device. Figures 38A, 38B, 38C, 38D, 38E, and 38F are diagrams showing an example of an electronic device. Figures 39A, 39B, 39C, 39D, 39E, 39F, and 39G are diagrams showing an example of an electronic device.

[0031] Embodiments will be described in detail with reference to the drawings. However, it will be readily apparent to those skilled in the art that the present invention is not limited to the following description, and that its form and details can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention shall not be construed as being limited to the descriptions of the embodiments shown below.

[0032] In the invention described below, the same reference numerals are used in common across different drawings for identical parts or parts having similar functions, and repeated explanations are omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used, and reference numerals may not be assigned.

[0033] The positions, sizes, and extents of each component shown in the drawings may not represent their actual positions, sizes, and extents for the sake of ease of understanding. Therefore, the disclosed invention is not necessarily limited to the positions, sizes, and extents disclosed in the drawings.

[0034] In this specification, the ordinal numbers "first," "second," etc., are used for convenience only and do not limit the number of components or the order of components (for example, process order or stacking order). Also, the ordinal numbers attached to components in one part of this specification may not be the same as the ordinal numbers attached to those components in other parts of this specification or in the claims.

[0035] It should be noted that the terms "film" and "layer" can be interchanged depending on the context or situation. For example, the term "conductive layer" can be changed to "conductive film." Or, for example, the term "insulating film" can be changed to "insulating layer."

[0036] A transistor is a type of semiconductor device that can perform functions such as amplifying current or voltage, and switching operations that control conduction or non-conductivity. Transistors as used herein include IGFETs (Insulated Gate Field Effect Transistors) and thin-film transistors (TFTs).

[0037] The functions of "source" and "drain" may be reversed when transistors with different polarities are used, or when the direction of current changes during circuit operation. For this reason, in this specification, the terms "source" and "drain" may be used interchangeably. Furthermore, the names of the source and drain of a transistor can be appropriately rephrased as source terminal and drain terminal, or source electrode and drain electrode, etc., depending on the situation.

[0038] The terms "gate" and "back gate" are interchangeable. Therefore, in this specification, the terms "gate" and "back gate" may be used interchangeably. Furthermore, the names of the gate and back gate of a transistor can be appropriately rephrased as gate electrode and back gate electrode, etc., depending on the context.

[0039] In this specification, "connection" includes, for example, "electrical connection." The term "electrical connection" is sometimes used to define the connection relationship of circuit elements as a physical object. Furthermore, "electrical connection" includes both "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the use of circuit elements (e.g., transistors, switches, etc.; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected through one or more circuit elements. A and B refer to objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0040] For example, assuming a circuit including A and B is in operation, if there is a timing during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then it can be defined that "A and B are indirectly connected" as physical objects. Furthermore, even if there is a timing during the circuit's operation when no electrical signals are exchanged or potential interactions occur between A and B, if there is a timing during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then it can be defined that "A and B are indirectly connected."

[0041] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where "A and B are not indirectly connected" is when an insulator is interposed in the path from A to B. Specifically, this includes cases where a capacitive element is connected between A and B, or where a transistor gate insulating film is interposed between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of a transistor are indirectly connected."

[0042] Another example of a situation where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via source and drain in the path from A to B, and a constant potential V is supplied to the nodes between the transistors from a power supply, GND, etc.

[0043] In this specification, unless otherwise specified, on-current refers to the drain current (also written as Id) when the transistor is in the ON state (also called the conducting state). Unless otherwise specified, the ON state refers to the state in an n-channel transistor where the voltage between the gate and source (also written as Vg or Vgs) is equal to or greater than the threshold voltage (also written as Vth), and to the state in a p-channel transistor where it is less than or equal to the threshold voltage.

[0044] In this specification, unless otherwise specified, off-current refers to the source-drain leakage current when the transistor is in the off state (also called the non-conductive state or cutoff state). Unless otherwise specified, the off state refers to the state in an n-channel transistor where the voltage between the gate and source is lower than the threshold voltage, and in a p-channel transistor where it is higher than the threshold voltage.

[0045] In this specification, "parallel" means a state in which two lines are positioned at an angle of -10 degrees or more and 10 degrees or less. Therefore, the case of -5 degrees or more and 5 degrees or less is also included. Furthermore, "approximately parallel" means a state in which two lines are positioned at an angle of -30 degrees or more and 30 degrees or less. Furthermore, "perpendicular" means a state in which two lines are positioned at an angle of 80 degrees or more and 100 degrees or less. Therefore, the case of 85 degrees or more and 95 degrees or less is also included. Furthermore, "approximately perpendicular" means a state in which two lines are positioned at an angle of 60 degrees or more and 120 degrees or less.

[0046] In this specification, the "upper surface" of a layer or film refers to the surface of the layer or film in a direction parallel or approximately parallel to the surface on which the layer or film is formed. The "side surface" of a layer or film refers to the surface of the layer or film in a direction perpendicular or approximately perpendicular to the surface on which the layer or film is formed.

[0047] In this specification, the top surface shape of a component refers to the contour shape of the component in a plan view (also called a top view). A plan view refers to a view from the direction normal to the surface on which the component is formed, or to the surface of the support (e.g., substrate) on which the component is formed.

[0048] In this specification, "matching or roughly matching top shapes" means that at least a portion of the contours overlaps between stacked layers. For example, this includes cases where the upper and lower layers are processed with the same mask pattern, or partially with the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or the upper layer may be located outside the lower layer, and in this case too, it may be said that "matching or roughly matching top shapes." Furthermore, when the top shapes match or roughly match, it may also be said that "the edges match or roughly match," or "the edges are aligned or roughly aligned."

[0049] In this specification, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined with respect to the substrate surface or the surface to be formed. The angle formed between the inclined side surface and the substrate surface or the surface to be formed is sometimes called the taper angle.

[0050] In this specification, devices manufactured using a metal mask or FMM (Fine Metal Mask, high-resolution metal mask) may be referred to as MM (metal mask) structured devices. Furthermore, in this specification, devices manufactured without using a metal mask or FMM may be referred to as MML (metal maskless) structured devices. Since MML structured devices can be manufactured without using a metal mask, they can exceed the upper limit of resolution imposed by the alignment accuracy of the metal mask. Additionally, MML structured devices eliminate the need for metal mask manufacturing equipment and metal mask cleaning processes. Moreover, because MML structured devices can be manufactured at a lower cost, they are suitable for mass production.

[0051] In this specification, a structure in which different light-emitting layers are created using light-emitting elements (also called light-emitting devices) with different emission wavelengths is sometimes referred to as an SBS (Side By Side) structure. Because the SBS structure allows for the optimization of materials and configurations for each light-emitting element, it increases the freedom of material and configuration selection, making it easier to improve brightness and reliability.

[0052] In this specification, holes or electrons may be referred to as "carriers." Specifically, in a light-emitting element, a hole injection layer or electron injection layer may be called a "carrier injection layer," a hole transport layer or electron transport layer may be called a "carrier transport layer," and a hole blocking layer or electron blocking layer may be called a "carrier blocking layer." It should be noted that the above-mentioned carrier injection layer, carrier transport layer, and carrier blocking layer may not always be clearly distinguishable. Furthermore, a single layer may combine the functions of two or three of these layers.

[0053] In this specification, a light-emitting element has an EL layer between a pair of electrodes. The EL layer has at least a light-emitting layer. Examples of layers (also called functional layers) that the EL layer has include a light-emitting layer, a carrier injection layer (hole injection layer and electron injection layer), a carrier transport layer (hole transport layer and electron transport layer), and a carrier blocking layer (hole blocking layer and electron blocking layer). In this specification, a photodetector (also called a photodetector device) has at least an active layer that functions as a photoelectric conversion layer between a pair of electrodes. In this specification, one of the pair of electrodes may be referred to as a pixel electrode and the other as a common electrode.

[0054] In this specification, "step breakage" refers to the phenomenon in which a layer, film, or electrode is divided due to the shape of the surface on which it is formed (e.g., a step).

[0055] In this specification, "island-like" refers to a state in which two or more layers made of the same material and formed in the same process are physically separated.

[0056] In this specification, the sacrificial layer (which may also be called the mask layer) is located at least above the light-emitting layer (more specifically, the layer that is processed into an island shape among the layers constituting the EL layer) and has the function of protecting the light-emitting layer during the manufacturing process.

[0057] (Embodiment 1) In this embodiment, a semiconductor device according to one aspect of the present invention will be described with reference to Figures 1A to 17C.

[0058] One aspect of the present invention is a semiconductor device having a transistor, a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer.

[0059] A transistor according to one aspect of the present invention is provided on a first insulating layer. A transistor according to one aspect of the present invention has a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, an oxide semiconductor layer, a fifth insulating layer, and a sixth insulating layer.

[0060] The first conductive layer functions as either the source electrode or the drain electrode of the transistor. The second conductive layer functions as the other source electrode or drain electrode of the transistor. The third conductive layer functions as the first gate electrode (also called the top gate electrode) of the transistor. The fourth conductive layer functions as the second gate electrode (also called the back gate electrode) of the transistor. The fifth insulating layer functions as the first gate insulating layer (also called the top gate insulating layer) of the transistor. The sixth insulating layer functions as the second gate insulating layer (also called the back gate insulating layer) of the transistor. The region of the oxide semiconductor layer in contact with the first conductive layer functions as either the source region or the drain region of the transistor. The region of the oxide semiconductor layer in contact with the second conductive layer functions as the other source region or drain region of the transistor. In the oxide semiconductor layer, the channel formation region of the transistor is located between the source region and the drain region.

[0061] The second insulating layer is located on the first conductive layer. The second insulating layer has regions that are in contact with the upper surface and side surfaces of the first conductive layer, as well as the upper surface of the first insulating layer.

[0062] The fourth conductive layer is located on the second insulating layer. The fourth conductive layer has a region that is in contact with the upper surface of the second insulating layer.

[0063] The third insulating layer is located on the fourth conductive layer. The third insulating layer has a region that is in contact with the upper surface of the fourth conductive layer.

[0064] The second conductive layer is located on the third insulating layer. The second insulating layer, the fourth conductive layer, the third insulating layer, and the second conductive layer have regions where their respective edges coincide or substantially coincide in a plan view.

[0065] The fourth insulating layer is provided so as to cover the structure composed of the first insulating layer, the first conductive layer, the second insulating layer, the fourth conductive layer, the third insulating layer, and the second conductive layer. The fourth insulating layer has regions that are in contact with the upper surface of the first insulating layer, the upper and side surfaces of the first conductive layer, the side surfaces of the second insulating layer, the side surfaces of the fourth conductive layer, the side surfaces of the third insulating layer, and the upper and side surfaces of the second conductive layer.

[0066] The fourth insulating layer has an opening in the region that overlaps with the channel formation region of the transistor, as well as the source region and the drain region, respectively. The opening is provided such that, in a plan view, it overlaps with the first conductive layer and the second conductive layer, respectively. The structure composed of the first insulating layer, the first conductive layer, the second insulating layer, the fourth conductive layer, the third insulating layer, and the second conductive layer has the region facing the channel formation region of the transistor, as well as the source region and the drain region, respectively, exposed within the opening.

[0067] The sixth insulating layer is provided covering the opening such that it has a region facing the channel formation region of the transistor. Within the opening, the sixth insulating layer has regions in contact with the side surfaces of the second insulating layer, the fourth conductive layer, and the third insulating layer. Outside the opening, the sixth insulating layer has regions in contact with the upper surface of the fourth insulating layer (in this case, the surface of the region of the fourth insulating layer that is in contact with the side surfaces of the second insulating layer, the fourth conductive layer, and the third insulating layer).

[0068] The oxide semiconductor layer is located on the first conductive layer, the sixth insulating layer, and the second conductive layer. The oxide semiconductor layer is provided such that, in a plan view, it has regions that overlap with the first conductive layer and the second conductive layer, respectively. The oxide semiconductor layer is provided such that, in a plan view, it is contained within the opening. Within the opening, the oxide semiconductor layer has regions that are in contact with the upper surface of the first conductive layer, the upper surface of the sixth insulating layer (here, the surface of the region of the sixth insulating layer that is in contact with the side surface of the second insulating layer, the side surface of the fourth conductive layer, and the side surface of the third insulating layer, respectively), and the upper surface of the second conductive layer, respectively.

[0069] The sixth insulating layer preferably contains oxygen. The oxygen contained in the sixth insulating layer is supplied to the oxide semiconductor layer in contact with the sixth insulating layer. This fills the oxygen vacancies (V) in the oxide semiconductor layer (mainly the channel formation region). Ｏ (Oxygen Vacancy) is compensated, and a transistor with good electrical characteristics can be realized.

[0070] The second and third insulating layers preferably each contain oxygen, similar to the sixth insulating layer. This allows the oxygen contained in the second and third insulating layers to be supplied to the oxide semiconductor layer via the sixth insulating layer. Therefore, oxygen vacancies (V) in the oxide semiconductor layer are reduced. Ｏ This allows for further compensation of the above, and further improves the electrical characteristics of the transistor.

[0071] The fourth insulating layer is preferably an insulating layer that can suppress oxygen permeation. The fourth insulating layer has a configuration that covers the entire side surface of the second insulating layer and the entire side surface of the third insulating layer, excluding the opening. Therefore, it is possible to suppress the release of oxygen from the second insulating layer and the third insulating layer to the outside from the side surfaces of the second insulating layer and the third insulating layer other than the region in contact with the sixth insulating layer and the oxide semiconductor layer (i.e., the region overlapping with the opening). As a result, oxygen from the second insulating layer and the third insulating layer can be efficiently supplied to the oxide semiconductor layer (mainly the channel-forming region) via the sixth insulating layer.

[0072] The fifth insulating layer is located on the oxide semiconductor layer. The fifth insulating layer is provided so as to cover the structure composed of the oxide semiconductor layer, the fourth insulating layer, and the sixth insulating layer. The fifth insulating layer has regions that are in contact with the upper surface of the oxide semiconductor layer, the upper surface of the fourth insulating layer, and the upper surface of the sixth insulating layer, respectively. The third conductive layer is located on the fifth insulating layer. The third conductive layer is provided so as to have a region that overlaps with the oxide semiconductor layer. The third conductive layer has a region that faces the side surface of the fourth conductive layer via the fifth insulating layer, the oxide semiconductor layer, and the sixth insulating layer.

[0073] In a cross-sectional view, one surface of the oxide semiconductor layer has a region facing the third conductive layer via a fifth insulating layer, and the other surface of the oxide semiconductor layer has regions facing the second insulating layer, the fourth conductive layer, and the third insulating layer via a sixth insulating layer.

[0074] The first insulating layer preferably contains hydrogen. The hydrogen contained in the first insulating layer diffuses into the oxide semiconductor layer through the first conductive layer. The region of the oxide semiconductor layer in contact with the first conductive layer, that is, either the source region or the drain region, contains hydrogen. As a result, the electrical resistance of either the source region or the drain region is reduced, which allows the on-current of the transistor to be increased.

[0075] A transistor according to one aspect of the present invention is a vertical transistor whose channel length can be controlled by the thickness of a second insulating layer, a fourth insulating layer, and a third insulating layer, which are sandwiched between a first conductive layer and a second conductive layer. In other words, unlike a planar transistor, the channel length of the transistor is not affected by the exposure performance of the exposure apparatus used for fabrication. Therefore, the channel length of the transistor can be made smaller than the minimum dimension that the exposure apparatus can expose (hereinafter also referred to as the minimum dimension). By shortening the channel length, a transistor with a large on-current can be made. Therefore, a semiconductor device that operates at high speed can be made.

[0076] Furthermore, since vertical transistors can have their source electrode, oxide semiconductor layer, and drain electrode stacked on top of each other, the area occupied by the transistor can be reduced compared to planar transistors. Therefore, the area occupied by the semiconductor device having such a transistor can be reduced. For example, by applying such a semiconductor device to a display device, the resolution of the display device can be increased.

[0077] Furthermore, a transistor according to one aspect of the present invention has two gate electrodes flanking an oxide semiconductor layer. Therefore, a gate electric field can be applied to the carriers in the channel formation region from both sides of the oxide semiconductor layer. Consequently, a larger on-current can be achieved than with a transistor having only one gate electrode. A smaller off-current can also be achieved. In addition, the threshold voltage can be shifted to the normally off side. Furthermore, the saturation characteristics of the current flowing when operating in the saturation region can be improved (i.e., the magnitude of the drain current hardly changes with increasing drain voltage).

[0078] <Configuration Example 1> A semiconductor device according to one aspect of the present invention will be described. A plan view (also called a top view) of the semiconductor device 10 is shown in Figure 1A. A cross-sectional view along the dashed line A1-A2 shown in Figure 1A is shown in Figure 1B, and a cross-sectional view along the dashed line B1-B2 is shown in Figure 1C. Note that in Figure 1A, some of the components of the semiconductor device 10 (such as the gate insulating layer) are omitted. In subsequent drawings, as in Figure 1A, some of the components may also be omitted in the plan view of the semiconductor device.

[0079] The semiconductor device 10 includes a transistor 100, an insulating layer 109, an insulating layer 110a, an insulating layer 110b, and an insulating layer 116. The insulating layer 109 is provided on the substrate 102, and the transistor 100 and the like are provided on the insulating layer 109.

[0080] In Figures 1B and 1C, etc., an example is shown in which the insulating layer 110a has a laminated structure consisting of insulating layer 110a1, insulating layer 110a2 on insulating layer 110a1, and insulating layer 110a3 on insulating layer 110a2. An example is shown in which the insulating layer 110b has a laminated structure consisting of insulating layer 110b1, insulating layer 110b2 on insulating layer 110b1, and insulating layer 110b3 on insulating layer 110b2. Insulating materials that contain and release oxygen are used for insulating layers 110a2 and 110b2, respectively. In addition, insulating materials that can suppress oxygen permeation (insulating materials with oxygen barrier properties) are used for insulating layers 110a1, 110a3, 110b1, and 110b3, respectively.

[0081] In this specification, the term "barrier film" refers to a film that possesses barrier properties. Barrier properties refer to one or both of the following functions: a function that makes it difficult for a target substance to diffuse, thereby suppressing the permeation of the substance through the film (also known as low permeability); and a function that captures or fixes the substance (also known as gettering). For example, an insulating layer that possesses barrier properties can be called a barrier insulating layer.

[0082] The transistor 100 includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108, a conductive layer 112a, a conductive layer 112b, a conductive layer 103, and an insulating layer 119. The conductive layer 104 functions as a first gate electrode (top gate electrode), and a portion of the insulating layer 106 functions as a first gate insulating layer (top gate insulating layer). The conductive layer 112a functions as either a source electrode or a drain electrode, and the conductive layer 112b functions as the other of either a source electrode or a drain electrode. The conductive layer 103 functions as a second gate electrode (back gate electrode), and a portion of the insulating layer 119 functions as a second gate insulating layer (back gate insulating layer). Of the semiconductor layer 108, the region between the source electrode and the drain electrode that overlaps with the first gate electrode via the first gate insulating layer functions as a channel forming region. Furthermore, within the semiconductor layer 108, the region between the source electrode and the drain electrode that overlaps with the second gate electrode via the second gate insulating layer also functions as a channel formation region (also called a back channel formation region). In addition, within the semiconductor layer 108, the region in contact with the source electrode functions as the source region, and the region in contact with the drain electrode functions as the drain region.

[0083] Figure 2A is a perspective view of the semiconductor device 10. Figure 2B is a perspective view of the structure obtained by omitting the conductive layer 104 and the insulating layer 106 from the semiconductor device 10 shown in Figure 2A. Figure 3 is a perspective view of the structure shown in Figure 2B, with the semiconductor layer 108, insulating layer 119, and insulating layer 116 shown separately. In Figure 3, the insulating layer 110a and insulating layer 110b are shown as single-layer structures. A hatching pattern is applied to the region of the insulating layer 119 that is in contact with the semiconductor layer 108.

[0084] A conductive layer 112a is provided on the insulating layer 109. An insulating layer 110a is provided on the conductive layer 112a and on the insulating layer 109, such that it has an overlapping region with the conductive layer 112a. A conductive layer 103 is provided on the insulating layer 110a. An insulating layer 110b is provided on the conductive layer 103. A conductive layer 112b is provided on the insulating layer 110b. The conductive layer 112a has a region that is in contact with the insulating layer 109. The insulating layer 110a has a region that is in contact with the upper surface and side surfaces of the conductive layer 112a, and the upper surface of the insulating layer 109. The conductive layer 103 has a region that is in contact with the upper surface of the insulating layer 110a. The insulating layer 110b has a region that is in contact with the upper surface of the conductive layer 103. The conductive layer 112b has a region that is in contact with the upper surface of the insulating layer 110b.

[0085] The insulating layer 110a is in contact with and sandwiched between the conductive layer 112a and the conductive layer 103. The insulating layer 110b is in contact with and sandwiched between the conductive layer 103 and the conductive layer 112b. The conductive layer 112a has a region that overlaps with the conductive layer 112b via the insulating layer 110a, the conductive layer 103, and the insulating layer 110b.

[0086] As shown in Figure 3, etc., a structure in which an insulating layer 110a, a conductive layer 103, an insulating layer 110b, and a conductive layer 112b are stacked in this order is provided in an island-like configuration. The upper surfaces of the insulating layer 110a, the conductive layer 103, the insulating layer 110b, and the conductive layer 112b are identical or approximately identical. That is, in a plan view, the ends of the insulating layer 110a, the conductive layer 103, the insulating layer 110b, and the conductive layer 112b are identical or approximately identical.

[0087] As shown in Figure 3, the insulating layer 116 is provided to cover the structure composed of the substrate 102, insulating layer 109, conductive layer 112a, insulating layer 110a, conductive layer 103, insulating layer 110b, and conductive layer 112b. As shown in Figures 1B and 1C, the insulating layer 116 has regions that are in contact with the upper and side surfaces of the conductive layer 112b, the side surfaces of the insulating layer 110a (insulating layer 110a1, insulating layer 110a2, and insulating layer 110a3), the side surfaces of the conductive layer 103, the side surfaces of the insulating layer 110b (insulating layer 110b1, insulating layer 110b2, and insulating layer 110b3), the upper and side surfaces of the conductive layer 112a, and the upper surface of the insulating layer 109.

[0088] As shown in Figure 3, the insulating layer 116 has an opening 145. The opening 145 is provided such that, in a plan view, it has a region that overlaps with the conductive layer 112a and the conductive layer 112b, respectively. In the structure composed of the conductive layer 112a, insulating layer 110a, conductive layer 103, insulating layer 110b, conductive layer 112b, and insulating layer 116, the upper surface of the conductive layer 112a, the side surface of the insulating layer 110a, the side surface of the conductive layer 103, the side surface of the insulating layer 110b, and the upper surface and side surface of the conductive layer 112b are exposed within the opening 145 of the insulating layer 116.

[0089] The insulating layer 116 is made of an insulating material that has barrier properties against oxygen, similar to the insulating layers 110a1, 110a3, 110b1, and 110b3 mentioned above.

[0090] The insulating layer 119 is provided on the insulating layer 116. As shown in Figures 1B, 1C, 2B, and 3, the insulating layer 119 has regions that are in contact with the upper surface of the conductive layer 112a, the side surface of the insulating layer 110a, the side surface of the conductive layer 103, the side surface of the insulating layer 110b, the side surface of the conductive layer 112b, and the upper surface of the insulating layer 116. As shown in Figure 3, the insulating layer 119 is provided so as to cover the side surface of the island-shaped structure composed of the insulating layer 110a, the conductive layer 103, the insulating layer 110b, and the conductive layer 112b, via the insulating layer 116. The insulating layer 119 is provided so as to have a region that overlaps with the opening 145. The insulating layer 119 is in contact with the side surface of the insulating layer 110a, the side surface of the conductive layer 103, and the side surface of the insulating layer 110b on the inside of the opening 145, and is in contact with the upper surface of the insulating layer 116 on the outside of the opening 145.

[0091] Note that while Figures 1B and 1C show an example where the upper end of the insulating layer 119 in cross-sectional view is curved and rounded, this is not always the case. Depending on the method and conditions for forming the insulating layer 119, the upper end of the insulating layer 119 may have a corner, as shown in Figures 2B and 3.

[0092] The insulating layer 119 is made of an insulating material that contains and can release oxygen, similar to the insulating layers 110a2 and 110b2 described above. Within the opening 145, the upper surface of the insulating layer 119 (the surface opposite to the surface in contact with the side surface of insulating layer 110a, the side surface of insulating layer 110b, etc.) is in contact with the semiconductor layer 108 (the area with the hatching pattern in the insulating layer 119 shown in Figure 3). Therefore, the oxygen contained in the insulating layer 119 can be supplied to the semiconductor layer 108 (mainly the channel formation region). In addition, the oxygen contained in insulating layer 110a and insulating layer 110b can be supplied to the semiconductor layer 108 via the insulating layer 119.

[0093] The semiconductor layer 108 is provided on the conductive layer 112a, the insulating layer 119, and the conductive layer 112b. In a plan view, the semiconductor layer 108 is provided such that it has regions that overlap with the conductive layer 112a and the conductive layer 112b, respectively. The semiconductor layer 108 can also be provided spanning between the region on the conductive layer 112a where the insulating layer 110a, conductive layer 103, insulating layer 110b, and conductive layer 112b are provided, and the region on the conductive layer 112a where the insulating layer 110a, conductive layer 103, insulating layer 110b, and conductive layer 112b are not provided. Furthermore, as shown in Figure 1A, the semiconductor layer 108 is provided so as to be enclosed within the opening 145 in a plan view.

[0094] As shown in Figures 1B, 1C, 2B, and 3, the semiconductor layer 108 has regions that are in contact with the upper surface of the conductive layer 112a, the upper surface of the insulating layer 119, and the upper surface of the conductive layer 112b, respectively. As shown in Figure 1B, the semiconductor layer 108 has a shape that follows the upper surface of the conductive layer 112a, the upper surface of the insulating layer 119, the curved portion of the insulating layer 119, and the upper surface of the conductive layer 112b, respectively. As shown in Figure 3, the semiconductor layer 108 is in contact with the upper surface of the conductive layer 112a, the upper surface of the insulating layer 119, and the upper surface of the conductive layer 112b, respectively, inside the opening in the insulating layer 116 (opening 145 shown in Figure 1A), and is in contact with the upper surface of the insulating layer 116 outside the opening.

[0095] Within the opening 145, the region in contact with the conductive layer 112a of the semiconductor layer 108 functions as either the source region or the drain region of the transistor 100. Within the opening 145, the region in contact with the conductive layer 112b of the semiconductor layer 108 functions as the other source region or drain region of the transistor 100. Within the opening 145, the region in contact with the insulating layer 119 of the semiconductor layer 108 functions as the channel formation region of the transistor 100.

[0096] As shown in Figures 1B, 1C, and 3, the multiple sides of the island-shaped insulating layers 110a and 110b are all covered by the insulating layer 116, except for a portion of the area in contact with the insulating layer 119 (the area overlapping with the opening 145). Therefore, in the insulating layer 110a, the lower surface (the surface on the substrate 102 side) of the insulating layer 110a2 is in contact with the insulating layer 110a1, and the upper surface is in contact with the insulating layer 110a3. The sides of the insulating layer 110a2 are all in contact with the insulating layer 116, except for a portion of the area in contact with the insulating layer 119. Similarly, in the insulating layer 110b, the lower surface (the surface facing the substrate 102) of the insulating layer 110b2 is in contact with the insulating layer 110b1, and the upper surface is in contact with the insulating layer 110b3. The sides of the insulating layer 110b2 are in contact with the insulating layer 116, except for a portion of the area in contact with the insulating layer 119. In other words, the insulating layer 110a2 can be covered with the insulating layers 110a1, 110a3, and 116, each having barrier properties against oxygen, except for the area in contact with the insulating layer 119. Similarly, the insulating layer 110b2 can be covered with the insulating layers 110b1, 110b3, and 116, each having barrier properties against oxygen, except for the area in contact with the insulating layer 119. Therefore, the release of oxygen from the insulating layer 110a2 and the insulating layer 110b2 to the outside can be suppressed, and the oxygen can be efficiently supplied to the semiconductor layer 108 (mainly the channel formation region) via the insulating layer 119.

[0097] The insulating layer 106, which functions as a gate insulating layer for transistor 100, is provided so as to cover the semiconductor layer 108. The insulating layer 106 has regions that are in contact with the upper and side surfaces of semiconductor layer 108, the upper surface of conductive layer 112a, the upper surface of conductive layer 112b, the upper surface of insulating layer 116, and the upper surface of insulating layer 119.

[0098] The conductive layer 104, which functions as the gate electrode of transistor 100, is provided on the insulating layer 106 and has a region in contact with the upper surface of the insulating layer 106. The conductive layer 104 has a region that overlaps with the semiconductor layer 108 via the insulating layer 106. Furthermore, the conductive layer 104 has regions that face the side surface of the insulating layer 110a, the side surface of the conductive layer 103, and the side surface of the insulating layer 110b, respectively, via the insulating layer 106 and the semiconductor layer 108. The conductive layer 104 is provided so as to cover at least the upper surface of the insulating layer 119 in the region that overlaps with the semiconductor layer 108 in a plan view. This allows the region of the semiconductor layer 108 facing the said side surface to function as the channel formation region of transistor 100.

[0099] It is preferable that the conductive layer 104 covers the entire semiconductor layer 108. As shown in Figure 1A, it is preferable that the conductive layer 104 encompasses the semiconductor layer 108 in a plan view. By covering the semiconductor layer 108 with the conductive layer 104, damage to the semiconductor layer 108 when a layer is formed on the transistor 100 can be suppressed. This makes it possible to realize a transistor 100 that exhibits good electrical characteristics and is highly reliable. It is also possible to have a configuration in which the semiconductor layer 108 has regions that are not covered by the conductive layer 104.

[0100] A step is formed between the region on the conductive layer 112a where the insulating layer 110a, conductive layer 103, insulating layer 110b, and conductive layer 112b are provided, and the region on the conductive layer 112a where the insulating layer 110a, conductive layer 103, insulating layer 110b, and conductive layer 112b are not provided. A semiconductor layer 108, insulating layer 106, conductive layer 104, etc., can be provided along this step.

[0101] One of the conductive layer 104 and conductive layer 103 can function as a gate electrode (first gate electrode), and the other can function as a back gate electrode (second gate electrode). It is preferable that the conductive layer 104 and conductive layer 103 are arranged so as to sandwich the channel formation region of the semiconductor layer 108. That is, in a cross-sectional view, it is preferable that one surface of the semiconductor layer 108 faces the conductive layer 104 via the insulating layer 106, and the other surface of the semiconductor layer 108 faces the conductive layer 103 via the insulating layer 119. This allows the gate voltage to be applied to the channel formation region from both sides of the region, thereby strengthening the effect of the gate voltage on the carriers in the region. Therefore, the on-current of the transistor 100 can be increased. The off-current can be decreased. The threshold voltage can be shifted to the normally-off side. The saturation characteristics of the current flowing when operating in the saturation region can be improved.

[0102] For example, by applying transistor 100 to a drive transistor constituting the pixel circuit of a display device using organic EL elements, the luminescence brightness of the light-emitting element can be stabilized. Also, for example, by applying transistor 100 to a selection transistor constituting the pixel circuit of a display device using organic EL elements, the selection speed of the display pixels can be increased. Furthermore, for example, by applying transistor 100 to a transistor constituting the drive circuit of a display device (for example, one or both of the gate line drive circuit and the source line drive circuit), a display device with a high operating speed can be realized.

[0103] By applying a potential that turns on the transistor to the back gate electrode (second gate electrode), the field-effect mobility of the transistor can be increased. Furthermore, by changing the potential of the back gate electrode, the threshold voltage of the transistor can be changed. The potential of the back gate electrode can be the same as that of the gate electrode (first gate electrode). Alternatively, the potential of the back gate electrode can be the ground potential or any arbitrary potential. Also, the potential of the back gate electrode can be the same as that of the source electrode or drain electrode. This allows the potential of the region of the semiconductor layer opposite the back gate electrode to be fixed, thereby suppressing variations in the electrical characteristics of the transistor.

[0104] To apply the same potential to the back gate electrode as to the gate electrode, the back gate electrode and the gate electrode should be connected to create conductivity. To apply the same potential to the back gate electrode as to the source electrode or drain electrode, the back gate electrode should be connected to the source electrode or drain electrode to create conductivity. By configuring the gate electrode or back gate electrode to be connected to the source electrode, for example, the reliability of the transistor can be improved.

[0105] Furthermore, when the potential of the back gate electrode is set to ground potential or any other potential, it is also possible to provide a common wire connecting to the back gate electrodes of multiple transistors and apply a potential to this common wire.

[0106] By configuring a transistor to have a back gate electrode, it may be possible to reduce variations in the electrical characteristics between multiple transistors. For example, it may be possible to reduce variations in the threshold voltage between multiple transistors.

[0107] As described above, in one aspect of the present invention, a semiconductor device 10 can be realized that exhibits good electrical characteristics and is highly reliable as a transistor 100.

[0108] The semiconductor material used in the semiconductor layer 108 is not particularly limited. For example, a semiconductor made of a single element or a compound semiconductor can be used. Examples of semiconductors made of single elements include silicon and germanium. Examples of compound semiconductors include gallium arsenide and silicon germanium. Other examples of compound semiconductors include organic semiconductors, nitride semiconductors, and oxide semiconductors (OS). These semiconductor materials may contain impurities that act as dopants.

[0109] The crystallinity of the semiconductor material used in the semiconductor layer 108 is not particularly limited, and any amorphous semiconductor, single-crystal semiconductor, or semiconductor having crystalline properties other than single crystal (microcrystalline semiconductor, polycrystalline semiconductor, or semiconductor having a crystalline region in part) can be used. Using a single-crystal semiconductor or a semiconductor having crystalline properties is preferable because it can suppress the degradation of transistor characteristics.

[0110] For example, silicon can be used for the semiconductor layer 108. Examples of silicon include single-crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. An example of polycrystalline silicon is low-temperature polysilicon (LTPS). Transistors using amorphous silicon for the channel formation region can be formed on a large glass substrate and can be manufactured at low cost. Transistors using polycrystalline silicon for the channel formation region have high field-effect mobility and can operate at high speed. Furthermore, transistors using microcrystalline silicon for the channel formation region have higher field-effect mobility than transistors using amorphous silicon and can operate at high speed.

[0111] The semiconductor layer 108 preferably has a metal oxide (also called an oxide semiconductor) that exhibits semiconductor properties. Transistors using oxide semiconductors (hereinafter referred to as OS transistors) have extremely high field-effect mobility compared to transistors using amorphous silicon. Furthermore, OS transistors have a remarkably low off-current and can retain the charge stored in a capacitor connected in series with the transistor for a long period of time. In addition, by applying OS transistors, the power consumption of the semiconductor device can be reduced. When an oxide semiconductor is used for the semiconductor layer, the semiconductor layer can be called an oxide semiconductor layer or a metal oxide layer.

[0112] Each of the insulating layers 110a and 110b can be an inorganic insulating layer, an organic insulating layer, or both. Examples of materials that can be used for the organic insulating layer include acrylic resin and polyimide resin. Preferably, each of the insulating layers 110a and 110b has one or more inorganic insulating layers. Examples of materials that can be used for the inorganic insulating layer include oxides, nitrides, oxidized nitrides, and nitride oxides. Examples of oxides include silicon oxide, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, cerium oxide, zinc gallium oxide, and hafnium aluminate. Examples of nitrides include silicon nitride and aluminum nitride. Examples of oxidized nitrides include silicon oxidized nitride, aluminum oxidized nitride, gallium oxidized nitride, yttrium oxidized nitride, and hafnium oxidized nitride. Examples of nitride oxides include silicon nitride and aluminum nitride.

[0113] In this specification, the term "oxidogenic nitride" refers to a material whose composition contains more oxygen than nitrogen. The term "nitride oxide" refers to a material whose composition contains more nitrogen than oxygen.

[0114] The insulating layer 119 has a region that is in contact with the semiconductor layer 108. When a metal oxide is used for the semiconductor layer 108, it is preferable that at least a portion of the region of the insulating layer 119 that is in contact with the semiconductor layer 108 contains oxygen in order to improve the interfacial characteristics between the semiconductor layer 108 and the insulating layer 119. Specifically, it is preferable that the portion of the insulating layer 119 that is in contact with the channel-forming region of the semiconductor layer 108 contains oxygen. One or more oxides and oxiditrides can be suitably used in the portion of the insulating layer 119 that is in contact with the channel-forming region of the semiconductor layer 108.

[0115] When a metal oxide is used for the semiconductor layer 108, it is preferable that at least a portion of the region of the insulating layer 119 that is in contact with the semiconductor layer 108 releases oxygen when heat is applied. This supplies oxygen from the insulating layer 119 to the semiconductor layer 108, reducing oxygen deficiencies (V) in the semiconductor layer 108. Ｏ ), and defects in which hydrogen enters the oxygen vacancy (hereinafter referred to as V Ｏ This can reduce the amount of H (which is denoted as H).

[0116] Furthermore, when a metal oxide is used for the semiconductor layer 108, it is preferable that at least the insulating layer 110a2 of the insulating layer 110a (insulating layer 110a1, insulating layer 110a2, and insulating layer 110a3) contains oxygen and releases oxygen when heat is applied. Similarly, it is preferable that at least the insulating layer 110b2 of the insulating layer 110b1, insulating layer 110b2, and insulating layer 110b3 contains oxygen and releases oxygen when heat is applied. As a result, oxygen is supplied to the semiconductor layer 108 from the insulating layer 110a2 and insulating layer 110b2 via the insulating layer 119, and oxygen deficiencies (V) in the semiconductor layer 108 are reduced. Ｏ ) and V Ｏ H can be further reduced.

[0117] In transistor 100, the source electrode and drain electrode are positioned at different heights relative to the surface of the substrate 102, and the drain current flows perpendicular to, or approximately perpendicular to, the surface of the substrate 102. In transistor 100, it can also be said that the drain current flows in the vertical direction, or approximately vertical direction. Therefore, a transistor according to one aspect of the present invention can be called a vertical channel transistor, a vertical transistor, or a VFET (Vertical Field Effect Transistor).

[0118] The channel length of the transistor 100 can be controlled by the thickness of the insulating layer 110a, the conductive layer 103, and the insulating layer 110b, which are provided between the conductive layer 112a and the conductive layer 112b. Therefore, transistors with a channel length shorter than the minimum exposure dimension of the exposure apparatus used to manufacture the transistors can be manufactured with high precision. Furthermore, variations in the electrical characteristics between multiple transistors 100 can be reduced. As a result, the operation of the semiconductor device 10 becomes more stable and its reliability can be increased. In addition, when the variations in the electrical characteristics of the transistors 100 are reduced, the degree of freedom in circuit design increases, and the operating voltage of the semiconductor device 10 can be lowered. As a result, the power consumption of the semiconductor device 10 can be reduced.

[0119] In one embodiment of the present invention, the source electrode, semiconductor layer, and drain electrode can be arranged in a stacked manner. Therefore, compared to a so-called planar transistor in which the source electrode, semiconductor layer, and drain electrode are arranged on a plane, the occupied area can be significantly reduced.

[0120] The conductive layers 112a, 112b, 104, and 103 can each function as wiring, and the transistor 100 can be placed in the region where these wirings overlap. In other words, in a circuit having the transistor 100 and wiring, the area occupied by the transistor 100 and wiring can be reduced. Therefore, a semiconductor device 10 with a small occupied area can be realized.

[0121] For example, when a semiconductor device according to one aspect of the present invention is applied to the pixel circuit of a display device, the occupied area of ​​the pixel circuit can be reduced, resulting in a high-definition display device. Also, for example, when a semiconductor device according to one aspect of the present invention is applied to the drive circuit of a display device (for example, one or both of a gate line drive circuit and a source line drive circuit), the occupied area of ​​the drive circuit can be reduced, resulting in a narrow-bezel display device.

[0122] The insulating layer 109 is provided between the transistor 100, the insulating layer 110a, and the substrate 102. The insulating layer 109 has regions that are in contact with each of the conductive layer 112a, the insulating layer 110a, and the insulating layer 116. The insulating layer 109 can be made from the materials listed for insulating layer 110a and insulating layer 110b.

[0123] The insulating layer 109 preferably has barrier properties. It is preferable to use a material for the insulating layer 109 that does not easily allow impurities (e.g., water and hydrogen) contained in the substrate 102 to diffuse. This makes it possible to suppress the diffusion of impurities from the substrate 102 to the transistor 100.

[0124] The insulating layer 109, which functions as a barrier film, can be made from, for example, one or more oxides having aluminum and / or hafnium, an oxide having magnesium, an oxide having gallium, an aluminum nitride, an aluminum nitride, an aluminum nitride, and an oxide silicon nitride. Specifically, the insulating layer 109 can preferably be made from, for example, one or more aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, zinc gallium oxide, aluminum nitride, silicon nitride, and silicon nitride oxide.

[0125] The insulating layer 109 contains impurities (e.g., water and hydrogen) that lower the electrical resistance of the semiconductor layer 108, and it is preferable to use a material that releases these impurities. The impurities released from the insulating layer 109 diffuse into the region of the conductive layer 112a that is in contact with the insulating layer 109. Furthermore, the impurities diffused into the conductive layer 112a diffuse into the region of the semiconductor layer 108 that is in contact with the conductive layer 112a, so that region contains impurities, and the electrical resistance of that region can be lowered. In other words, the electrical resistance of either the source region or the drain region can be lowered. Therefore, a transistor 100 with a large on-current can be made, and a semiconductor device 10 that operates at high speed can be made.

[0126] When a metal oxide is used for the semiconductor layer 108, it is more preferable that the impurities released by the insulating layer 109 include hydrogen. The hydrogen contained in the insulating layer 109 diffuses into the semiconductor layer 108 via the conductive layer 112a, causing the region of the semiconductor layer 108 in contact with the conductive layer 112a to contain hydrogen, thereby increasing the carrier concentration in that region. In other words, the electrical resistance of either the source region or the drain region can be lowered. The insulating layer 109 preferably contains, for example, silicon and hydrogen. Typically, silicon nitride containing hydrogen can be suitably used for the insulating layer 109.

[0127] It is more preferable to use a material for the insulating layer 109 that releases impurities that lower the electrical resistance of the conductive layer 112a. This makes it possible to lower the electrical resistance of the conductive layer 112a.

[0128] For example, a conductive metal oxide (also called an oxide conductor) can be used for the conductive layer 112a. Examples of oxide conductors (OC) include indium oxide (also called indium oxide), zinc oxide, In-Sn oxide (ITO), In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Sn-Si oxide (also called silicon-containing ITO or ITSO), zinc oxide with added gallium, and In-Ga-Zn oxide. In particular, oxide conductors containing indium have high conductivity and can therefore be suitably used for the conductive layer 112a.

[0129] When a metal oxide is used for the conductive layer 112a, it is more preferable that the impurities released from the insulating layer 109 contain hydrogen. The impurities released from the insulating layer 109 diffuse through the conductive layer 112a, causing the conductive layer 112a to contain impurities. As a result, the carrier concentration of the conductive layer 112a increases, and the electrical resistance can be reduced. Also, since the conductive layer 112a can function as a wiring, a semiconductor device 10 with low wiring resistance can be realized. Note that the impurities that lower the electrical resistance of the conductive layer 112a can be the same as the impurities that lower the electrical resistance of the semiconductor layer 108. Or, these impurities can have different configurations from each other. It is more preferable that the conductive layer 112a allows impurities to permeate easily. It is more preferable that the conductive layer 112a is less likely to adsorb impurities.

[0130] The thickness of the insulating layer 109 is preferably 5 nm or more and 100 nm or less, more preferably 10 nm or more and 100 nm or less, still more preferably 20 nm or more and 100 nm or less, and even more preferably 20 nm or more and 50 nm or less. For example, as shown in FIG. 4A, the thickness T109 of the insulating layer 109 can be the shortest distance between the formed surface of the insulating layer 109 (here, the upper surface of the substrate 102) and the upper surface of the insulating layer 109 in a cross-sectional view.

[0131] When the thickness T109 is large and the amount of impurities released from the insulating layer 109 becomes too large, the amount of impurities diffusing into the semiconductor layer 108 increases, and the amount of oxygen vacancies (V Ｏ ) and V Ｏ H may become larger than the amount of oxygen vacancies (V Ｏ ) and V Ｏ H that can be repaired by the oxygen supplied from each of the insulating layer 110a and the insulating layer 110b. On the other hand, when the thickness T109 is small, the amount of impurities diffusing into the conductive layer 112a and the semiconductor layer 108 decreases, and there is a risk that the electrical resistance of the conductive layer 112a and the electrical resistance of either the source region or the drain region will increase. By setting the thickness T109 within the above range, the oxygen vacancies (V Ｏ ) and V ＯThis can suppress the increase in H and lower these electrical resistances. Note that the thickness T109 is not limited to the range described above.

[0132] Furthermore, it is also possible to omit the insulating layer 109.

[0133] It is preferable that the insulating layer 110a and insulating layer 110b each have a laminated structure. In Figure 1B, etc., an example is shown in which insulating layer 110a has insulating layer 110a1, insulating layer 110a2 on insulating layer 110a1, and insulating layer 110a3 on insulating layer 110a2, and insulating layer 110b has insulating layer 110b1, insulating layer 110b2 on insulating layer 110b1, and insulating layer 110b3 on insulating layer 110b2. The insulating layers 110a1, 110a2, 110a3, 110b1, 110b2, and 110b3 can be made from the materials listed for insulating layer 110a and insulating layer 110b, respectively.

[0134] In transistor 100, the region of semiconductor layer 108 in contact with insulating layer 119 functions as a channel-forming region. As mentioned above, the insulating layer 119 preferably contains oxygen, and it is preferable to use one or more of the oxides and oxiditrides mentioned above for insulating layer 110a and insulating layer 110b. Typically, silicon oxide and silicon oxiditride, or both, can be suitably used for the insulating layer 119.

[0135] It is more preferable to use a material that releases oxygen when heat is applied for the insulating layer 119. The heat applied during the manufacturing process of the semiconductor device 10 causes the insulating layer 119 to release oxygen, thereby supplying oxygen to the semiconductor layer 108. By supplying oxygen from the insulating layer 119 to the semiconductor layer 108, particularly to the channel formation region of the semiconductor layer 108, oxygen deficiencies (V) in that region can be reduced. Ｏ ) is repaired, and oxygen deficiency (V Ｏ This can reduce the V in the region. Ｏ H can be reduced. Therefore, a transistor 100 that exhibits good electrical characteristics and is highly reliable can be realized.

[0136] Furthermore, it is preferable to use the same material as the insulating layer 119 for each of the insulating layer 110a2 and insulating layer 110b2. This allows oxygen released from each of the insulating layer 110a2 and insulating layer 110b2 to be supplied to the channel formation region of the semiconductor layer 108 via the insulating layer 119, thereby reducing oxygen deficiencies (V) in that region. Ｏ ) and V Ｏ H can be further reduced. Therefore, the electrical characteristics and reliability of transistor 100 can be further improved.

[0137] For example, oxygen can be supplied to the insulating layer 110a2 and the insulating layer 110b2 by performing a heat treatment in an oxygen-containing atmosphere or a plasma treatment in an oxygen-containing atmosphere. Alternatively, oxygen can be supplied to the upper surfaces of the insulating layer 110a2 and the insulating layer 110b2 by forming a film in an oxygen-containing atmosphere using a sputtering method. The film can then be removed. The method for supplying oxygen to the insulating layer 110a2 and the insulating layer 110b2 will be specifically described in Embodiment 3.

[0138] For the deposition of the insulating layer 110a2 and the insulating layer 110b2, it is preferable to use sputtering or plasma chemical vapor deposition (PECVD: Plasma Enhanced Chemical Vapor Deposition, also known as plasma CVD). In particular, by using sputtering and deposition in a manner that does not use hydrogen-containing gases (e.g., hydrogen gas and ammonia gas) as the deposition gas, it is possible to obtain a film with an extremely low hydrogen content. Therefore, the supply of hydrogen to the channel formation region is suppressed, and the electrical characteristics of the transistor 100 can be stabilized.

[0139] Insulating layer 110a1 is provided between insulating layer 110a2 and conductive layer 112a and insulating layer 109. Insulating layer 110a3 is provided between insulating layer 110a2 and conductive layer 103. Insulating layer 110b1 is provided between insulating layer 110b2 and conductive layer 103. Insulating layer 110b3 is provided between insulating layer 110b2 and conductive layer 112b. It is preferable that insulating layers 110a1, 110a3, 110b1, and 110b3 each release small amounts of impurities (e.g., hydrogen and water). Furthermore, it is preferable that insulating layers 110a1, 110a3, 110b1, and 110b3 each have low permeability to substances. The insulating layers 110a1, 110a3, 110b1, and 110b3 can also be said to function as barrier films. Specifically, it is preferable that the insulating layers 110a1, 110a3, 110b1, and 110b3 are each resistant to the permeability of impurities. This suppresses the diffusion of impurities contained in each of the insulating layers 110a1, 110a3, 110b1, and 110b3 into the channel formation region. Therefore, a transistor 100 that exhibits good electrical characteristics and is highly reliable can be realized.

[0140] As described above, it is preferable to use materials that are impermeable to oxygen for each of the insulating layers 110a1, 110a3, 110b1, and 110b3. This suppresses the diffusion of oxygen contained in insulating layer 110a2 to the conductive layer 112a side via insulating layer 110a1. It also suppresses the diffusion of oxygen contained in insulating layer 110a2 to the conductive layer 103 side via insulating layer 110a3. Similarly, it suppresses the diffusion of oxygen contained in insulating layer 110b2 to the conductive layer 103 side via insulating layer 110b1. It also suppresses the diffusion of oxygen contained in insulating layer 110b2 to the conductive layer 112b side via insulating layer 110b3. This increases the amount of oxygen supplied from insulating layer 110a2 and insulating layer 110b2 to the channel formation region of semiconductor layer 108, thereby reducing oxygen deficiencies (V) in the channel formation region. Ｏ ) and VＯ H can be reduced. This makes it possible to realize a transistor 100 that exhibits good electrical characteristics and is highly reliable. Furthermore, oxidation of the conductive layer 112a by oxygen contained in the insulating layer 110a2 and an increase in the electrical resistance of the conductive layer 112a can be suppressed. Similarly, oxidation of the conductive layer 103 by oxygen contained in the insulating layer 110a2 and an increase in the electrical resistance of the conductive layer 103 can be suppressed. Likewise, oxidation of the conductive layer 103 by oxygen contained in the insulating layer 110b2 and an increase in the electrical resistance of the conductive layer 103 can be suppressed. Furthermore, oxidation of the conductive layer 112b by oxygen contained in the insulating layer 110b2 and an increase in the electrical resistance of the conductive layer 112b can be suppressed. Therefore, a transistor 100 with a large on-current can be realized.

[0141] The insulating layers 110a1, 110a3, 110b1, and 110b3 can each be made from the materials listed above for the barrier film. For example, the insulating layers 110a1, 110a3, 110b1, and 110b3 can each preferably be made from one or more of the following materials: aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, zinc gallium oxide, aluminum nitride, silicon nitride, and silicon nitride oxide. The same material can be used for each of the insulating layers 110a1, 110a3, 110b1, and 110b3. Alternatively, different materials can be used for each of the insulating layers 110a1, 110a3, 110b1, and 110b3.

[0142] In this specification, "different materials" means materials in which some or all of the constituent elements are different, or materials in which the constituent elements are the same but the composition is different.

[0143] The insulating layers 110a1, 110a2, 110a3, 110b1, 110b2, and 110b3 can also be arranged in a laminated structure. For example, insulating layer 110a3 and insulating layer 110b3 can each be arranged in a laminated structure of an aluminum oxide film and a silicon nitride film on the aluminum oxide film.

[0144] The thicknesses of insulating layer 110a3 and insulating layer 110b3 are preferably 3 nm to 500 nm, more preferably 5 nm to 400 nm, more preferably 10 nm to 300 nm, more preferably 20 nm to 300 nm, more preferably 50 nm to 300 nm, more preferably 100 nm to 300 nm, and more preferably 100 nm to 200 nm. For example, the thickness of insulating layer 110a3 can be the shortest distance between the surface of insulating layer 110a3 being formed (here, the upper surface of insulating layer 110a2) and the upper surface of insulating layer 110a3 in a cross-sectional view. Similarly, the thickness of insulating layer 110b3 can be the shortest distance between the surface of insulating layer 110b3 being formed (here, the upper surface of insulating layer 110b2) and the upper surface of insulating layer 110b3 in a cross-sectional view.

[0145] The thickness of the insulating layer 110a3 and the insulating layer 110b3 is preferably such that they function as a barrier film against oxygen. The thickness of the insulating layer 110a3 and the insulating layer 110b3 can be thinner than the thickness of the insulating layer 110a1 and the insulating layer 110b1, respectively. If the thickness of the insulating layer 110a3 and the insulating layer 110b3 is thick, the amount of impurities released from the insulating layer 110a3 and the insulating layer 110b3 will increase, and the amount of impurities diffusing into the channel-forming region may increase. On the other hand, if the thickness of the insulating layer 110a3 is thin, the oxygen contained in the insulating layer 110a2 may diffuse to the conductive layer 103 side through the insulating layer 110a3, and the amount of oxygen supplied to the channel-forming region may decrease. Similarly, if the thickness of the insulating layer 110b3 is thin, the oxygen contained in the insulating layer 110b2 may diffuse to the conductive layer 112b side through the insulating layer 110b3, and the amount of oxygen supplied to the channel-forming region may decrease. By setting the thickness of the insulating layer 110a3 and the insulating layer 110b3 to the aforementioned range, the amount of oxygen supplied to the channel formation region can be increased, and the oxygen deficiency (V) in the channel formation region can be reduced. Ｏ ) and V Ｏ H can be reduced. Furthermore, oxidation of the conductive layer 103 by oxygen contained in the insulating layer 110a2 can be suppressed, which would increase the electrical resistance of the conductive layer 103. Similarly, oxidation of the conductive layer 112b by oxygen contained in the insulating layer 110b2 can be suppressed, which would increase the electrical resistance of the conductive layer 112b. Note that the thicknesses of the insulating layer 110a3 and the insulating layer 110b3 are not limited to the ranges described above.

[0146] The thickness of the insulating layer 110a1 and the insulating layer 110b1 is preferably 3 nm to 500 nm, more preferably 5 nm to 400 nm, more preferably 10 nm to 300 nm, more preferably 20 nm to 300 nm, more preferably 50 nm to 300 nm, more preferably 100 nm to 300 nm, more preferably 100 nm to 250 nm, and more preferably 150 nm to 250 nm. For example, the thickness of the insulating layer 110a1 can be the shortest distance between the surface on which the insulating layer 110a1 is formed (here, the upper surface of the conductive layer 112a) and the upper surface of the insulating layer 110a1 in a cross-sectional view. The thickness of the insulating layer 110b1 can be the shortest distance between the surface on which the insulating layer 110b1 is formed (here, the upper surface of the conductive layer 103) and the upper surface of the insulating layer 110b1 in a cross-sectional view.

[0147] If the thickness of insulating layer 110a1 is thin, oxygen contained in insulating layer 110a2 may diffuse to the conductive layer 112a side via insulating layer 110a1, reducing the amount of oxygen supplied to the channel formation region. Similarly, if the thickness of insulating layer 110b1 is thin, oxygen contained in insulating layer 110b2 may diffuse to the conductive layer 103 side via insulating layer 110b1, reducing the amount of oxygen supplied to the channel formation region. On the other hand, if the thicknesses of insulating layer 110a1 and insulating layer 110b1 are thick, the amount of impurities released from insulating layer 110a1 and insulating layer 110b1 increases, and the amount of impurities diffusing to the channel formation region increases. By setting the thicknesses of insulating layer 110a1 and insulating layer 110b1 within the aforementioned ranges, the amount of oxygen supplied to the channel formation region can be increased, reducing oxygen deficiency (V) in the channel formation region. Ｏ ) and V Ｏ H can be reduced. Furthermore, oxidation of the conductive layer 112a by oxygen contained in the insulating layer 110a2 can be suppressed, preventing an increase in the electrical resistance of the conductive layer 112a. Similarly, oxidation of the conductive layer 103 by oxygen contained in the insulating layer 110b2 can be suppressed, preventing an increase in the electrical resistance of the conductive layer 103. Note that the thicknesses of the insulating layer 110a1 and the insulating layer 110b1 are not limited to the ranges described above.

[0148] Furthermore, impurities released from one or more of the insulating layers 110a1, 110a3, 110b1, and 110b3 may diffuse into the channel-forming region via the insulating layer 119. However, oxygen is supplied to the channel-forming region from the insulating layer 119, or from the insulating layers 110a2 and 110b2 respectively via the insulating layer 119, thus preventing oxygen deficiency (V) in the channel-forming region. Ｏ ) and V Ｏ H can be reduced. This suppresses the shift of the threshold voltage to the normally-on side, making it possible to realize a transistor 100 that achieves both a small cutoff current (drain current when the gate voltage is 0V) and a large on current. Therefore, it is possible to realize a semiconductor device 10 that achieves both low power consumption and high performance.

[0149] However, if the amount of impurities released from insulating layers 110a1, 110a3, 110b1, and 110b3 becomes too large, the amount of impurities contained in the semiconductor layer 108 will increase. As a result, oxygen vacancies (V) will be formed in the semiconductor layer 108. Ｏ ) and V Ｏ The amount of H is such that the oxygen deficiency (V) is repaired by the oxygen supplied from the insulating layer 110a2 and the insulating layer 110b2, respectively. Ｏ ) and V Ｏ There is a risk that the amount of H may exceed the amount of H. Even when materials that release impurities are used for insulating layers 110a1, 110a3, 110b1, and 110b3, it is more preferable that the amount of released impurities be small.

[0150] The insulating layer 110a1 has regions that are in contact with the upper surface of the insulating layer 109 and the upper and side surfaces of the conductive layer 112a. This suppresses the diffusion of impurities contained in the insulating layer 109 and the conductive layer 112a into the channel-forming region of the semiconductor layer 108 via the insulating layer 110a2 and the insulating layer 119.

[0151] It is preferable that the insulating layer 109 has a region with a higher hydrogen content than the insulating layer 110a1. It is preferable that the film density of the insulating layer 110a1 is higher than the film density of the insulating layer 109.

[0152] Furthermore, for analyzing the hydrogen content of the insulating layer 109, etc., secondary ion mass spectrometry (SIMS) can be used, for example.

[0153] Furthermore, impurities released from the insulating layer 109 may diffuse into the channel formation region via the conductive layer 112a. However, oxygen is supplied to at least the region of the semiconductor layer 108 in contact with the insulating layer 119 from the insulating layer 119, or from the insulating layers 110a2 and 110b2 via the insulating layer 119, thus preventing oxygen deficiency (V) in the channel formation region. Ｏ ) and V Ｏ H can be reduced. This suppresses the shift of the threshold voltage to the normally-on side, making it possible to realize a transistor 100 that achieves both a small cutoff current and a large on current. Therefore, a semiconductor device 10 that achieves both low power consumption and high performance can be realized.

[0154] The amount of hydrogen released can be adjusted by differentiating the film formation conditions for the insulating layer 109 and the insulating layer 110a1. Specifically, one or more of the following can be made different for the insulating layer 109 and the insulating layer 110a1: the film formation power (film formation power density), film formation pressure, film formation gas type, film formation gas flow rate ratio, film formation temperature, and the distance between the substrate and the electrode. For example, by making the film formation power density of the insulating layer 109 lower than that of the insulating layer 110a1, the hydrogen content in the insulating layer 109 can be increased compared to the hydrogen content in the insulating layer 110a1. This increases the amount of hydrogen released from the insulating layer 109 due to the heat applied to it.

[0155] The film-forming gas used to form the insulating layer 109 preferably has a higher hydrogen content than the film-forming gas used to form the insulating layer 110a1. Specifically, when forming a silicon nitride film or a silicon nitride oxide film on the insulating layer 109 and the insulating layer 110a1 using the PECVD method, the ratio of the flow rate of ammonia gas to the total film-forming gas used to form the insulating layer 109 (hereinafter also referred to as the ammonia flow rate ratio) is preferably higher than the ammonia flow rate ratio of the film-forming gas used to form the insulating layer 110a1. By forming the insulating layer 109 under conditions of a high ammonia flow rate ratio, the hydrogen content in the insulating layer 109 can be increased. In addition, the amount of hydrogen released from the insulating layer 109 due to the heat applied to it can be increased.

[0156] It is more preferable that the film density of the insulating layer 110a1 is higher than that of the insulating layer 109. This suppresses the diffusion of hydrogen contained in the insulating layer 109 into the channel formation region of the semiconductor layer 108 via the insulating layer 110a1 and the insulating layer 119. For example, Rutherford backscattering (RBS) or X-ray reflectivity (XRR) can be used to evaluate the film density. Differences in film density can sometimes be evaluated using a transmission electron microscope (TEM) image of the cross-section. In TEM observation, a high film density results in a darker (more intense) transmission electron (TE) image, while a low film density results in a lighter (brighter) transmission electron (TE) image. Therefore, in the transmission electron (TE) image, the insulating layer 110a1 may appear darker (more intense) compared to the insulating layer 109. Even when the same material is applied to the insulating layer 109 and the insulating layer 110a1, the film densities are different, so in some cases, the boundary between them can be observed as a difference in contrast in the cross-sectional TEM image.

[0157] Here, the insulating layer 110a is shown as a three-layer laminated structure, but the present invention is not limited to this. Preferably, the insulating layer 110a has at least an insulating layer 110a2. It is also possible to have a configuration that does not have one or both of the insulating layers 110a1 and 110a3. Furthermore, it is also possible to have a configuration in which the insulating layer 110a has a four-layer laminated structure. The same applies to the insulating layer 110b; by replacing insulating layers 110a1, 110a2, and 110a3 with insulating layers 110b1, 110b2, and 110b3, respectively, the above description relating to the insulating layer 110a can also be applied to the insulating layer 110b.

[0158] [Semiconductor Layer 108] The metal oxides that can be used in the semiconductor layer 108 will be described in detail. Examples of metal oxides include indium oxide (also called indium oxide, IO). Examples of metal oxides include gallium oxide and zinc oxide. The metal oxide preferably contains at least indium. It is also preferable that the metal oxide contains either or both indium and zinc. Furthermore, it is preferable that the metal oxide has one or more elements selected from indium, element M, and zinc. Element M is a metal element or metalloid with a high bond energy with oxygen, for example, a metal element or metalloid with a higher bond energy with oxygen than indium. Specific examples of element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M present in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from gallium, aluminum, tin, and yttrium, and even more preferably one or more of gallium, aluminum, and tin. These elements are more preferable because they have high bonding energy with oxygen and similar ionic radii to indium or zinc. Furthermore, tin is more preferable because its tetravalent state enhances carrier mobility. In this specification, metallic elements and metalloid elements are sometimes collectively referred to as "metallic elements," and the term "metallic elements" as used here may include metalloid elements.

[0159] For example, indium oxide can be used for the semiconductor layer 108. Alternatively, for example, indium zinc oxide (In-Zn oxide, also known as IZO®), indium tin oxide (In-Sn oxide, also known as ITO), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium tungsten oxide (In-W oxide, also known as IWO), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also known as IGTO), gallium zinc oxide (Ga-Zn oxide, also known as GZO), and aluminum zinc oxide (Al-Zn oxide) can be used for the semiconductor layer 108. Indium aluminum zinc oxide (also written as AZO), indium aluminum zinc oxide (In-Al-Zn oxide, also written as IAZO), indium tin zinc oxide (In-Sn-Zn oxide, also written as ITZO®), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also written as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also written as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also written as IGAZO, IGZAO, or IAGZO), etc. can be used. Alternatively, silicon-containing indium tin oxide (also written as ITSO), gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), etc. can be used.

[0160] Furthermore, the metal oxide can be composed of one or more metal elements with high periodic numbers in the periodic table, either in place of indium or in addition to indium. The greater the overlap of the metal element orbitals, the greater the carrier conduction in the metal oxide tends to be. Therefore, by including metal elements with high periodic numbers, the field-effect mobility of the transistor can be increased. Examples of metal elements with high periodic numbers include those belonging to the 5th period and those belonging to the 6th period. Specifically, examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0161] Metal oxides may contain one or more nonmetallic elements. The presence of nonmetallic elements in metal oxides can increase carrier concentration or reduce the band gap, potentially improving the field-effect mobility of transistors. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0162] By increasing the ratio of indium atoms to the sum of all metal element atoms in the metal oxide, the field-effect mobility of the transistor can be increased. Furthermore, a transistor with a high on-current can be realized.

[0163] In this specification, the ratio of the number of indium atoms to the sum of the total number of atoms of all contained metal elements may be referred to as the indium content. The same applies to other metal elements. If element M contains multiple elements, the sum of the ratios of the number of atoms of element M to the sum of the total number of atoms of all contained metal elements may be referred to as the element M content.

[0164] By increasing the zinc content in a metal oxide, a highly crystalline metal oxide is obtained, which suppresses the diffusion of impurities within the metal oxide. Therefore, fluctuations in the electrical characteristics of the transistor are suppressed, and reliability can be improved.

[0165] By increasing the content of element M in the metal oxide, a metal oxide with a large band gap can be obtained. Furthermore, oxygen vacancies (V) can be added to the metal oxide. Ｏ The formation of oxygen deficiency (V) is suppressed, Ｏ This suppresses carrier generation caused by (), preventing the transistor's threshold voltage from shifting to the normally-on side. As a result, the cutoff current can be reduced, allowing for a normally-off transistor. It also allows for a transistor with a small off-current. Furthermore, fluctuations in the transistor's electrical characteristics are suppressed, improving reliability.

[0166] The composition of the metal oxide applied to the semiconductor layer 108 affects the electrical characteristics and reliability of the transistor. Therefore, by varying the composition of the metal oxide according to the required electrical characteristics and reliability of the transistor, it is possible to create a semiconductor device that achieves both excellent electrical characteristics and high reliability.

[0167] When the metal oxide is an In-M-Zn oxide, it is preferable that the atomic ratio of In in the In-M-Zn oxide is equal to or greater than the atomic ratio of element M. Examples of such atomic ratios of metal elements in an In-M-Zn oxide include In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=2:1:3, In:M:Zn=3:1:1, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:3, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, In: Compositions such as M:Zn=5:1:9, In:M:Zn=6:1:6, In:M:Zn=10:1:1, In:M:Zn=10:1:3, In:M:Zn=10:1:4, In:M:Zn=10:1:6, In:M:Zn=10:1:7, In:M:Zn=10:1:8, In:M:Zn=5:2:5, In:M:Zn=10:1:10, In:M:Zn=20:1:10, In:M:Zn=40:1:10, and compositions near these. Note that compositions near these include a range of ±30% of the desired atomic ratio. Increasing the atomic ratio of indium in the metal oxide can increase the on-current or field-effect mobility of the transistor.

[0168] The atomic ratio of In in an In-M-Zn oxide can be less than the atomic ratio of element M. Examples of such atomic ratios of metal elements in an In-M-Zn oxide include In:M:Zn = 1:3:2, In:M:Zn = 1:3:3, In:M:Zn = 1:3:4, In:M:Zn = 1:3:6, and compositions close to these. By increasing the proportion of M atoms in the metal oxide, oxygen deficiency (V) can be reduced. Ｏ This can suppress the generation of ()

[0169] Furthermore, if element M comprises multiple elements, the sum of their atomic ratios can be used as the atomic ratio of element M.

[0170] By using a material with a high indium content in the semiconductor layer 108, the on-current or field-effect mobility of the transistor can be increased. Furthermore, the presence of element M allows for oxygen deficiency (V ＯThe generation of ) can be suppressed. The content of element M (the ratio of the number of atoms of element M to the sum of the number of atoms of all contained metal elements) is preferably 0.1% to 25%, more preferably 0.1% to 20%, more preferably 0.1% to 10%, more preferably 0.1% to 8%, more preferably 0.1% to 6%, and more preferably 0.1% to 4%. This makes it possible to make a transistor with good electrical properties. For example, it is preferable to use metal oxides of In:M:Zn = 40:1:10 and nearby elements. Element M is preferably one or more of the above elements, and more preferably one or more selected from aluminum, gallium, tin, and yttrium. Specifically, metal oxides of In:Sn:Zn = 40:1:10 and nearby elements can be suitably used. Alternatively, metal oxides of In:Al:Zn = 40:1:10 and nearby elements can be suitably used.

[0171] A metal oxide that does not contain element M can be applied to the semiconductor layer 108. When the metal oxide is an In-Zn oxide, examples of atomic ratios of the metal elements include In:Zn=1:1, In:Zn=2:1, In:Zn=1:2, In:Zn=3:1, In:Zn=3:2, In:Zn=2:3, In:Zn=4:1, In:Zn=4:3, In:Zn=5:1, In:Zn=5:2, In:Zn=5:3, In:Zn=5:4, In:Zn=5:6, In:Zn=5:7, In:Zn=5:8, In:Zn=5:9, In:Zn=7:1, In:Zn=10:1, In:Zn=10:3, In:Zn=10:7, and compositions near these. Furthermore, it is more preferable that the atomic ratio of In is greater than or equal to the atomic ratio of Zn. By increasing the atomic ratio of indium in a metal oxide, the on-current or field-effect mobility of a transistor can be increased.

[0172] For analyzing the composition of the semiconductor layer 108, for example, energy-dispersive X-ray spectroscopy (EDX), X-ray photoelectron spectroscopy (XPS), or Electron Spectrometry for Chemical Analysis (ESCA), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled high-frequency plasma atomic emission spectroscopy (ICP-AES) can be used. Spectrometry can be used. Alternatively, a combination of these methods can be used for analysis. It is preferable to separate the peaks of the spectrum obtained by the analysis and then identify and quantify the elements. Note that for elements with low content, the actual content may differ from the content obtained by the analysis due to the effect of analytical accuracy. For example, if the content of element M is low, the content of element M obtained by the analysis may be lower than the actual content, it may be difficult to quantify the content of element M, or the content of element M may be below the detection limit.

[0173] For depositing metal oxide films, sputtering or atomic layer deposition (ALD) can be suitably used. However, when depositing metal oxide films by sputtering, the composition of the deposited metal oxide film may differ from the composition of the sputtering target. In particular, the zinc content in the deposited metal oxide film may decrease to about 50% compared to the sputtering target.

[0174] It is preferable to use a crystalline metal oxide for the semiconductor layer 108. Examples of crystalline metal oxide structures include CAAC (C-Axis Aligned Crystal) structure, polycrystalline structure, microcrystalline structure, and nanocrystalline (nc: nano-crystalline) structure. By using a crystalline metal oxide, the defect level density in the semiconductor layer 108 can be reduced, and a highly reliable semiconductor device can be realized.

[0175] It is preferable to use CAAC-OS or nc-OS for the semiconductor layer 108.

[0176] CAAC-OS has multiple layered crystals. The c-axis of the crystals is oriented in the direction normal to the surface to be formed. It is preferable that the semiconductor layer 108 has layered crystals that are parallel or approximately parallel to the surface to be formed. For example, it is preferable that the semiconductor layer 108 has layered crystals that are parallel or approximately parallel to the upper surface of the conductive layer 112b in the region in contact with the upper surface of the conductive layer 112b, and layered crystals that are parallel or approximately parallel to the upper surface of the insulating layer 119 in the region in contact with the upper surface of the insulating layer 119. In particular, it is preferable that the semiconductor layer 108 has layered crystals that are parallel or approximately parallel to the upper surface, which is the surface to be formed, in the region in contact with the upper surface of the insulating layer 119. With this configuration, the layered crystals of the semiconductor layer 108 are formed parallel or approximately parallel to the channel length direction of the transistor 100, so that a transistor with a large on-current can be made.

[0177] By using a highly crystalline metal oxide in the channel formation region, the defect level density in the channel formation region can be reduced. On the other hand, by using a less crystalline metal oxide, it is possible to realize a transistor that can carry a large current.

[0178] The higher the substrate temperature during metal oxide film deposition, the more crystalline the metal oxide film can be formed. The substrate temperature during deposition can be adjusted, for example, by the temperature of the stage on which the substrate is placed during deposition. Furthermore, the higher the oxygen flow rate ratio of the deposition gas used for film formation, or the higher the oxygen partial pressure in the processing chamber, the more crystalline the metal oxide film can be formed.

[0179] The crystallinity of the semiconductor layer 108 can be analyzed, for example, by X-ray diffraction (XRD), TEM, or electron diffraction (ED). Alternatively, a combination of these methods can be used for the analysis.

[0180] When a metal oxide is used for the semiconductor layer 108, the V of the channel formation region Ｏ It is preferable to reduce H as much as possible and make it high-purity intrinsic or substantially high-purity intrinsic. In this way, V Ｏ To obtain a metal oxide with sufficiently reduced H content, impurities such as water and hydrogen must be removed from the metal oxide (sometimes referred to as dehydration and dehydrogenation treatment), and oxygen must be supplied to the metal oxide to eliminate oxygen deficiency (V). Ｏ It is important to repair ). Ｏ By using metal oxides with sufficiently reduced defects such as H in the channel formation region of a transistor, stable electrical characteristics can be provided. Furthermore, by supplying oxygen to the metal oxide, oxygen deficiencies (V) can be reduced. Ｏ The process of repairing this is sometimes referred to as oxygenation treatment.

[0181] When a metal oxide is used for the semiconductor layer 108, the carrier concentration in the channel formation region is 1 × 10⁻⁶ １８ cm −３ The following is preferable: 1 × 10 １７ cm −３ It is more preferable that it be less than 1 × 10 １６ cm −３ It is even more preferable that it be less than 1 × 10 １３ cm −３ It is even more preferable that it be less than 1 × 10 １２ cm −３ It is even more preferable that it be less than 1. There is no limit to the lower limit of the carrier concentration in the channel-forming region, but for example, 1 × 10⁻⁶ −９ cm −３ It can be done this way.

[0182] OS transistors exhibit small fluctuations in electrical properties due to radiation exposure, meaning they have high resistance to radiation, making them suitable for use in environments where radiation may be incident. OS transistors can also be said to have high reliability against radiation. For example, OS transistors can be suitably used in the pixel circuits of X-ray flat panel detectors. Furthermore, OS transistors can be suitably used in semiconductor devices used in outer space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, protons, and neutrons).

[0183] The semiconductor layer 108 may also have a layered material that functions as a semiconductor. A layered material is a general term for a group of materials that have a layered crystalline structure. A layered crystalline structure is a structure in which layers formed by covalent or ionic bonds are stacked via weaker bonds than covalent or ionic bonds, such as van der Waals bonds. Layered materials have high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be realized.

[0184] Examples of the above-mentioned layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogens (elements belonging to Group 16). Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specifically, a transition metal chalcogenide applicable as a channel formation region in transistors is molybdenum sulfide (typically MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum tellurium (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ ) are some examples.

[0185] The semiconductor layer 108 can have a laminated structure having two or more metal oxide layers. The two or more metal oxide layers of the semiconductor layer 108 can have the same or substantially the same composition. By having a laminated structure of metal oxide layers with the same composition, for example, it can be formed using the same sputtering target, thus reducing manufacturing costs. When the two or more metal oxide layers of the semiconductor layer 108 have the same or substantially the same composition, it may not be possible to clearly identify the boundaries (interfaces) of these metal oxide layers.

[0186] The channel length and channel width of transistor 100 will be explained using Figures 4A and 4B. Figure 4B is a plan view of semiconductor device 10. Figure 4A is an enlarged cross-sectional view of transistor 100 along the dashed line A1-A2 in the plan view shown in Figure 4B.

[0187] In Figure 4A, the channel length L100 of transistor 100 is indicated by a dashed double arrow. In Figure 4A, the distance along the upper surface and curved portion of the insulating layer 119 between the upper surface of conductive layer 112a and the upper surface of conductive layer 112b is shown as the channel length L100 of transistor 100.

[0188] In addition, the channel length L100 of transistor 100 may be the sum of the thickness of the insulating layer 110a, the thickness of the conductive layer 103, and the thickness of the insulating layer 110b in the region sandwiched between the upper surface of the conductive layer 112a and the lower surface of the conductive layer 112b (in Figure 4A, the thickness T110 is indicated by a dashed double arrow). Alternatively, the channel length L100 of transistor 100 may be the sum of the thickness T110 and the thickness of the conductive layer 112b. Alternatively, the channel length L100 of transistor 100 may be the height of the insulating layer 119 (the distance between the upper and lower ends of the insulating layer 119 in a direction perpendicular to the substrate surface).

[0189] Here, the channel length L100 is determined by the thickness T110, the thickness of the conductive layer 112b, the angle θ110 between the surface of the insulating layer 119 to be formed (here, the side surface of the insulating layer 110a, the side surface of the conductive layer 103, the side surface of the insulating layer 110b, and the side surface of the conductive layer 112b) and the surface of the insulating layer 110a to be formed (here, the top surface of the conductive layer 112a), etc. Therefore, the channel length L100 can be set to a value smaller than the minimum exposure dimension of the exposure apparatus, making it possible to realize transistors of a very small size. Specifically, it is possible to realize transistors with extremely short channel lengths that were difficult to achieve with conventional exposure apparatuses for mass production of flat panel displays (for example, with a minimum dimension of about 2 μm or 1.5 μm). Furthermore, it is possible to realize transistors with channel lengths of less than 10 nm without using extremely expensive exposure apparatuses used in state-of-the-art LSI technology.

[0190] The channel length L100 can be, for example, 5 nm or more and less than 3 μm, 7 nm or more and 2.5 μm or less, 10 nm or more and 2 μm or less, 10 nm or more and 1.5 μm or less, 10 nm or more and 1.2 μm or less, 10 nm or more and 1 μm or less, 10 nm or more and 500 nm or less, 10 nm or more and 300 nm or less, 10 nm or more and 20 nm or less, 10 nm or more and 100 nm or less, 10 nm or more and 50 nm or less, 10 nm or more and 30 nm or less, or 10 nm or more and 20 nm or less. For example, the channel length L100 can also be 100 nm or more and 1 μm or less.

[0191] By shortening the channel length L100, the on-current of the transistor 100 can be increased. Using the transistor 100, a circuit capable of high-speed operation can be fabricated. Furthermore, the circuit's occupied area can be reduced. Therefore, a compact semiconductor device can be made. For example, when a semiconductor device according to one aspect of the present invention is applied to a large display device or a high-definition display device, even when the number of wires increases, the signal delay in each wire can be reduced, and display unevenness can be suppressed. In addition, since the circuit's occupied area can be reduced, the bezel of the display device can be narrowed.

[0192] The channel length L100 can be controlled by adjusting the thickness T110, angle θ110, etc.

[0193] The thickness of the insulating layer 110a2 and the insulating layer 110b2 can be, for example, 5 nm or more and less than 3 μm, 7 nm or more and 2.5 μm or less, 10 nm or more and 2 μm or less, 10 nm or more and 1.5 μm or less, 10 nm or more and 1.2 μm or less, 10 nm or more and 1 μm or less, 10 nm or more and 500 nm or less, 10 nm or more and 300 nm or less, 10 nm or more and 20 nm or less, 10 nm or more and 100 nm or less, 10 nm or more and 50 nm or less, 10 nm or more and 30 nm or less, or 10 nm or more and 20 nm or less.

[0194] The surfaces to which the insulating layer 119 is formed (here, the side surfaces of the insulating layer 110a, the conductive layer 103, the insulating layer 110b, and the conductive layer 112b) are preferably tapered. The angle θ110 is preferably less than 90 degrees. By reducing the angle θ110, the coverage of the insulating layer 119 and the like can be improved. Also, the smaller the angle θ110, the longer the channel length L100 can be made, and the larger the angle θ110, the shorter the channel length L100 can be made.

[0195] Although Figure 1B and other figures show the angle θ110 as less than 90 degrees, the present invention is not limited to this. The angle θ110 can also be 90 degrees or approximately 90 degrees. This allows for a shorter channel length L100 of the transistor 100 and a smaller footprint of the semiconductor device 10.

[0196] The angle θ110 can be, for example, 30 degrees or more and 90 degrees or less, 35 degrees or more and 85 degrees or less, 40 degrees or more and 80 degrees or less, 45 degrees or more and 75 degrees or less, 50 degrees or more and 70 degrees or less, 55 degrees or more and 70 degrees or less, 60 degrees or more and 70 degrees or less, or 65 degrees or more and 70 degrees or less.

[0197] In Figure 1B, etc., the side surfaces of the insulating layer 110a, the conductive layer 103, the insulating layer 110b, and the conductive layer 112b are aligned in a cross-sectional view, and each side surface has a straight shape. However, the present invention is not limited to this. In a cross-sectional view, the side surface may have a curved shape. Alternatively, in a cross-sectional view, the side surface may include both a region having a straight shape and a region having a curved shape.

[0198] It is preferable that the upper surface shapes of the insulating layer 110a, conductive layer 103, insulating layer 110b, and conductive layer 112b are identical or substantially identical. Figure 1A, etc., shows a configuration in which the upper surface shapes of the insulating layer 110a, conductive layer 103, insulating layer 110b, and conductive layer 112b are identical or substantially identical. In this case, the insulating layer 110a, conductive layer 103, insulating layer 110b, and conductive layer 112b can each be formed using the same mask layer. For example, an insulating film that will become the insulating layer 110a, a conductive film that will become the conductive layer 103 on the insulating film, an insulating film that will become the insulating layer 110b on the conductive film, and a conductive film that will become the conductive layer 112b on the insulating film are formed, and a mask layer (for example, a resist mask) is formed on the conductive film. Then, by processing the conductive film and the insulating film using the mask layer as a mask, insulating layer 110a, conductive layer 103, insulating layer 110b, and conductive layer 112b, respectively, can be formed, each having an identical or substantially identical top surface shape. By processing the insulating film that becomes insulating layer 110a, the conductive film that becomes conductive layer 103, the insulating film that becomes insulating layer 110b, and the conductive film that becomes conductive layer 112b in the same process, manufacturing costs can be reduced. In Figure 1A, etc., the top surface shapes of conductive layer 112b, insulating layer 110b, conductive layer 103, and insulating layer 110a are shown as rectangles, but the top surface shapes of conductive layer 112b, insulating layer 110b, conductive layer 103, and insulating layer 110a are not particularly limited.

[0199] As shown in Figure 1B, it is preferable that there are no steps between the sides of the conductive layer 112b, the insulating layer 110b, the conductive layer 103, and the insulating layer 110a, and that they are flat (i.e., the four sides coincide or roughly coincide). This improves the coverage of the layers provided along these four sides (for example, the insulating layer 109). However, it is also possible to have a configuration in which the sides of the conductive layer 112b, the insulating layer 110b, the conductive layer 103, and the insulating layer 110a are discontinuous. Furthermore, it is also possible to have a configuration in which the upper surface shapes of the insulating layer 110a, the conductive layer 103, the insulating layer 110b, and the conductive layer 112b each coincide or roughly coincide.

[0200] The channel width of transistor 100 is the length of the region where the channel formation area in the semiconductor layer 108 and the conductive layer 104 overlap in a plan view. In Figure 4B, the channel width W100 of transistor 100 is shown by the double-headed arrow in the dashed line.

[0201] When forming the semiconductor layer 108 and the conductive layer 104 using lithography, the channel width W100 is greater than or equal to the limiting resolution of the exposure apparatus. The channel width W100 can be, for example, 20 nm or more and less than 500 μm, 50 nm or more and 200 μm or less, 100 nm or more and 100 μm or less, 200 nm or more and 50 μm or less, 500 nm or more and 20 μm or less, 1 μm or more and 10 μm or less, or 1 μm or more and 5 μm or less.

[0202] Figure 5A is an enlarged view of the region 161 shown in Figure 1B. Figure 5A shows a configuration in which the height of the upper end of the insulating layer 119 is equal to or approximately equal to the height of the upper surface of the conductive layer 112b (the configuration shown in Figure 1B, etc.). In this configuration, no step is formed between the upper end of the insulating layer 119 and the side surface of the conductive layer 112b. Therefore, compared to a configuration with such a step, the coverage of the semiconductor layer 108, which is provided in contact with the upper surface and curved portion of the insulating layer 119 and the upper surface of the conductive layer 112b, can be improved.

[0203] In transistor 100, the height of the upper end of the insulating layer 119 is not limited to a configuration that matches or approximately matches the height of the upper surface of the conductive layer 112b, as shown in Figure 1B, etc. The configurations shown in Figures 5B to 5D are examples of configurations in which the height of the upper end of the insulating layer 119 differs from that in Figure 5A.

[0204] Figure 5B shows a configuration in which the height of the upper end of the insulating layer 119 is lower than the height of the upper surface of the conductive layer 112b, and higher than the height of the upper surface of the insulating layer 110b3 located below the conductive layer 112b. In the configuration shown in Figure 5B, the side surface of the conductive layer 112b has a region in contact with the semiconductor layer 108. Because the semiconductor layer 108 is in contact with the side surface of the conductive layer 112b, the contact area between the semiconductor layer 108 and the conductive layer 112b becomes larger than in the configuration shown in Figure 5A, and the contact resistance between the semiconductor layer 108 and the conductive layer 112b may be reduced.

[0205] Figure 5C shows a configuration in which the height of the upper end of the insulating layer 119 is lower than the height of the upper surface of the insulating layer 110b3. In the configuration shown in Figure 5C, the side surface of the conductive layer 112b has a region in contact with the semiconductor layer 108, and the side surface of the insulating layer 110b3 has a region in contact with the semiconductor layer 108. In this configuration, since the semiconductor layer 108 is in contact with the entire side surface of the conductive layer 112b, the contact resistance between the semiconductor layer 108 and the conductive layer 112b may be reduced compared to the configuration shown in Figure 5B.

[0206] Figure 5D shows a configuration in which the height of the upper end of the insulating layer 119 is lower than the height of the upper surface of the insulating layer 110b2. In the configuration shown in Figure 5D, the side surface of the conductive layer 112b has a region in contact with the semiconductor layer 108, the side surface of the insulating layer 110b3 has a region in contact with the semiconductor layer 108, and the side surface of the insulating layer 110b2 has a region in contact with the semiconductor layer 108. In this configuration, it is possible to obtain effects similar to those obtained in the configuration shown in Figure 5C described above.

[0207] During etching for the formation of the insulating layer 119, the height of the insulating layer 119 (the distance between the upper and lower ends of the insulating layer 119 in a direction perpendicular to the substrate surface) can sometimes be reduced by increasing the etching time. When the etching time is increased, the height of the upper end of the insulating layer 119 may become lower than the height of the upper surface of the conductive layer 112b. Preferably, the height of the upper end of the insulating layer 119 is at least higher than the height of the upper surface of the conductive layer 103. That is, it is preferable that the insulating layer 119 faces the entire side surface of the conductive layer 103. As described above, the insulating layer 119 is an insulating layer that functions as the second gate insulating layer (back gate insulating layer) of the transistor 100. Therefore, by having a region of the insulating layer 119 that faces the entire side surface of the conductive layer 103, the entire region of the semiconductor layer 108 that faces the conductive layer 103 via the insulating layer 119 can be made to function as a channel formation region (back channel formation region).

[0208] Figure 6A is an enlarged view of the region 163 shown in Figure 1B. Figure 6A shows a configuration (as shown in Figure 1B, etc.) in which a single-layer insulating layer 119 is provided in contact with the upper surface of the conductive layer 112a, the side surface of the insulating layer 110a1, the side surface of the insulating layer 110a2, the side surface of the insulating layer 110a3, the side surface of the conductive layer 103, the side surface of the insulating layer 110b1, the side surface of the insulating layer 110b2, the side surface of the insulating layer 110b3, and the side surface of the conductive layer 112b. In this configuration, as described above, the oxygen contained in the insulating layer 119 can be supplied to the semiconductor layer 108 (mainly the channel formation region) in contact with the insulating layer 119. In addition, the oxygen contained in the insulating layer 110a2 and the insulating layer 110b2 can be supplied to the semiconductor layer 108 via the insulating layer 119 in contact with the insulating layer 110a2 and the insulating layer 110b2, respectively.

[0209] In transistor 100, the configuration of the insulating layer 119, which functions as a second gate insulating layer, and the conductive layer 103, which functions as a second gate electrode (back gate electrode), is not limited to the configuration shown in Figure 1B, etc. The configurations shown in Figures 6B to 6D are examples in which the configuration of the insulating layer 119, conductive layer 103, etc. differs from that of Figure 6A.

[0210] Figure 6B shows a configuration in which the surface of the conductive layer 103 is covered with an insulating layer 118, and there are no insulating layers 110a3 and 110b1. In the configuration shown in Figure 6B, the insulating layer 119 and the conductive layer 103 face each other via the insulating layer 118. Also, the insulating layer 110a2 and the conductive layer 103 are laminated with the insulating layer 118 in between. Furthermore, the conductive layer 103 and the insulating layer 110b2 are laminated with the insulating layer 118 in between.

[0211] The insulating layer 118 has, for example, an oxide of the element present in the conductive layer 103. If the conductive layer 103 is a metal, for example, the insulating layer 118 is an oxide of that metal. If the conductive layer 103 is silicon, for example, the insulating layer 118 is silicon oxide. As the insulating layer 118, for example, a metal oxide such as aluminum oxide or tantalum oxide can be used, and the use of aluminum oxide is particularly preferred.

[0212] Furthermore, the insulating layer 118 can function as a gate insulating layer (second gate insulating layer) of the transistor 100. In the configuration shown in Figure 6B, for example, the laminated structure of the insulating layer 119 sandwiched between the semiconductor layer 108 and the conductive layer 103 and the insulating layer 118 functions as a gate insulating layer (second gate insulating layer) of the transistor 100.

[0213] The insulating layer 118 can be formed self-aligned by using a conductive material that is easily oxidized for the conductive layer 103. For example, when aluminum is used for the conductive layer 103, the insulating layer 118 (in this case, aluminum oxide) can be formed on the surface of the conductive layer 103 by oxidizing the surface of the conductive layer 103 with oxygen supplied from the insulating layers 110a2, 110b2, and 119 that are in contact with the conductive layer 103.

[0214] In the configuration shown in Figure 6B, the formation of insulating layers 110a3 and 110b1 is unnecessary, thus reducing the number of steps involved in the manufacturing of the semiconductor device compared to the configuration shown in Figure 6A.

[0215] Figure 6C shows a configuration in which the side edge of the insulating layer 110a1 protrudes outward from the side edge of the upper layers (insulating layer 110a2, insulating layer 110a3, conductive layer 103, insulating layer 110b1, insulating layer 110b2, insulating layer 110b3, and conductive layer 112b) of the insulating layer 110a1, and the upper surface of the protruding side edge of the insulating layer 110a1 is in contact with the lower edge of the insulating layer 119. In the configuration shown in Figure 6C, unlike the configuration shown in Figure 6A, the lower edge of the insulating layer 119 is not in contact with the upper surface of the conductive layer 112a. Therefore, it is possible to suppress the oxidation of the conductive layer 112a by the oxygen contained in the insulating layer 119, which would increase the electrical resistance of the conductive layer 112a. For this reason, the configuration shown in Figure 6C allows for a wider range of material selection that can be used for the conductive layer 112a than the configuration shown in Figure 6A.

[0216] Figure 6D shows a configuration in which the insulating layer 119 has a laminated structure consisting of insulating layer 119_1 and insulating layer 119_2 on insulating layer 119_1. In the configuration shown in Figure 6D, insulating layer 119_1 is provided in contact with the upper surface of conductive layer 112a, the side surface of insulating layer 110a1, the side surface of insulating layer 110a2, the side surface of insulating layer 110a3, the side surface of conductive layer 103, the side surface of insulating layer 110b1, the side surface of insulating layer 110b2, the side surface of insulating layer 110b3, and the side surface of conductive layer 112b. The insulating layer 119_2 is provided so as to face, via the insulating layer 119_1, the upper surface of the conductive layer 112a, the side surface of the insulating layer 110a1, the side surface of the insulating layer 110a2, the side surface of the insulating layer 110a3, the side surface of the conductive layer 103, the side surface of the insulating layer 110b1, the side surface of the insulating layer 110b2, the side surface of the insulating layer 110b3, and the side surface of the conductive layer 112b.

[0217] It is preferable to use a material that is impermeable to oxygen for the insulating layer 119_1. For example, the insulating layer 119_1 can be made from materials that can be used for insulating layers 110a1, 110a3, 110b1, and 110b3, respectively.

[0218] It is preferable to use a material that contains oxygen and releases oxygen upon heating for the insulating layer 119_2. For example, the insulating layer 119_2 can be made from a material that can be used for insulating layer 110a2 and insulating layer 110b2, respectively.

[0219] In the configuration shown in Figure 6D, of the insulating layers 119 (insulating layer 119_1 and insulating layer 119_2) that function as the second gate insulating layer of the transistor 100, insulating layer 119_2 has the function of supplying oxygen to the semiconductor layer 108, and insulating layer 119_1 has the function of suppressing the diffusion of oxygen from insulating layer 119_2 to the conductive layer 112a, conductive layer 112b, and conductive layer 103, respectively. Therefore, even if materials that release oxygen are not used for insulating layer 110a and insulating layer 110b, oxygen can be supplied to the semiconductor layer 108 by oxygen release from insulating layer 119_2. Furthermore, by providing an insulating layer 119_1 below the insulating layer 119_2, oxygen released from the insulating layer 119_2 diffuses into the conductive layer 112a, conductive layer 112b, and conductive layer 103, thereby suppressing oxidation of the conductive layer 112a, conductive layer 112b, and conductive layer 103 and preventing an increase in electrical resistance.

[0220] On the other hand, when conductive materials that are resistant to oxidation, conductive materials that maintain low electrical resistance even when oxidized, or oxide conductors are used for conductive layer 112a, conductive layer 112b, and conductive layer 103, it is preferable to apply the configuration shown in Figure 6A. This reduces the number of steps involved in manufacturing the semiconductor device compared to the configuration shown in Figure 6D. Furthermore, in the configuration shown in Figure 6A, in addition to the oxygen released by the insulating layer 119, the oxygen released by the insulating layer 110a and insulating layer 110b can also be supplied to the semiconductor layer 108. Therefore, the configuration shown in Figure 6A can supply more oxygen to the semiconductor layer 108 than the configuration shown in Figure 6D.

[0221] [Conductive layer 112a, conductive layer 112b, conductive layer 104, conductive layer 103] Conductive layers 112a, 112b, 104, and 103 can each be a single layer or a laminated structure of two or more layers. Examples of materials that can be used for conductive layers 112a, 112b, 104, and 103 include one or more of chromium, copper, aluminum, gold, silver, zinc, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, molybdenum, and niobium, as well as alloys composed of one or more of the aforementioned metals. Conductive layers 112a, 112b, 104, and 103 can each preferably be conductive materials with low electrical resistivity that contain one or more of copper, silver, gold, and aluminum. Copper or aluminum are particularly preferred because they are easy to mass-produce.

[0222] Oxide conductors can be used for conductive layers 112a, 112b, 104, and 103, respectively. For details on oxide conductors, please refer to the above description.

[0223] Oxygen vacancies (V) in metal oxides with semiconductor properties Ｏ When hydrogen is added to the oxygen vacancy, a donor level is formed near the conduction band. As a result, the metal oxide becomes highly conductive and turns into a conductor. A metal oxide that has turned into a conductor can be called an oxide conductor.

[0224] The conductive layers 112a, 112b, 104, and 103 can each have a laminated structure consisting of a conductive film containing the aforementioned oxide conductor (metal oxide) and a conductive film containing a metal or alloy. By using a conductive film containing a metal or alloy, the wiring resistance can be reduced.

[0225] Conductive layers 112a, 112b, 104, and 103 can each be coated with a Cu-X alloy film (where X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti). By using a Cu-X alloy film, processing can be performed by wet etching, thus reducing manufacturing costs.

[0226] Furthermore, the conductive layers 112a, 112b, 104, and 103 can be made of the same material. Alternatively, at least one of them can be made of a different material.

[0227] The conductive layer 112a and the conductive layer 112b each have a region that is in contact with the semiconductor layer 108. When an oxide semiconductor is used for the semiconductor layer 108, if an easily oxidized metal (e.g., aluminum) is used for the conductive layer 112a or the conductive layer 112b, an insulating oxide (e.g., aluminum oxide) may be formed between the conductive layer 112a or the conductive layer 112b and the semiconductor layer 108, which may hinder conductivity. Therefore, it is preferable to use a conductive material that is not easily oxidized, a conductive material that maintains low electrical resistance even when oxidized, or an oxide conductor for the conductive layer 112a and the conductive layer 112b.

[0228] For conductive layers 112a and 112b, it is preferable to use materials such as titanium, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel, respectively. These are preferred because they are conductive materials that are resistant to oxidation, or materials that maintain low electrical resistance even when oxidized. Furthermore, if conductive layer 112a or conductive layer 112b has a laminated structure, it is preferable to use a conductive material that is resistant to oxidation in at least the layer in contact with the semiconductor layer 108.

[0229] The aforementioned oxide conductors can be used for conductive layer 112a and conductive layer 112b, respectively. Specifically, oxide conductors such as indium oxide, zinc oxide, ITO, In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, silicon-containing In-Sn oxide, and gallium-doped zinc oxide can be used. In particular, oxide conductors containing indium have high conductivity and are therefore suitable for use in conductive layer 112a and conductive layer 112b.

[0230] Nitride conductors can also be used for conductive layers 112a and 112b, respectively. Examples of nitride conductors include tantalum nitride and titanium nitride.

[0231] [Insulating layer 106] The insulating layer 106 preferably has one or more inorganic insulating layers. The insulating layer 106 can be made from materials that can be used for insulating layer 110a and insulating layer 110b, respectively.

[0232] The insulating layer 106 has regions that are in contact with the semiconductor layer 108, the insulating layer 116, and the conductive layer 104. When a metal oxide is used for the semiconductor layer 108, it is preferable that at least the film constituting the insulating layer 106 that is in contact with the semiconductor layer 108 uses one of the aforementioned oxides and oxiditrides. When the insulating layer 106 has a single-layer structure, silicon oxide, silicon oxiditride, or aluminum oxide can be suitably used for the insulating layer 106.

[0233] In the case of miniature transistors, if the thickness of the gate insulating layer is reduced, the leakage current may increase. By using a material with a high dielectric constant (also called a high-k material) for the gate insulating layer, it is possible to reduce the voltage during transistor operation while maintaining the physical film thickness. Examples of high-k materials that can be used for the insulating layer 106 include gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, oxidized nitrides having aluminum and hafnium, oxides having silicon and hafnium, oxidized nitrides having silicon and hafnium, and nitrides having silicon and hafnium.

[0234] Although the insulating layer 106 is shown as a single layer in Figure 1B, etc., the present invention is not limited to this. The insulating layer 106 can also be a laminated structure of two or more layers.

[0235] When the insulating layer 106 has a laminated structure, it is preferable to use an oxide or oxidized nitride for the insulating layer on the semiconductor layer 108 side. For example, one or more of silicon oxide, silicon oxidized nitride, or aluminum oxide can be suitably used. Alternatively, nitrides or nitride oxides can be used. For example, aluminum nitride can be suitably used.

[0236] Preferably, one or more of the layers constituting the insulating layer 106 function as a barrier film. By providing a barrier film, it is possible to suppress the diffusion of metal components contained in the conductive layer 104 and impurities (e.g., water and hydrogen) contained in the layers formed on the transistor 100 into the semiconductor layer 108 via the insulating layer 106. Furthermore, it is possible to suppress the diffusion of oxygen contained in the insulating layer 110a and insulating layer 110b into the conductive layer 104 side via the insulating layer 106. As a result, the amount of oxygen supplied from the insulating layer 110a and insulating layer 110b to the channel formation region of the semiconductor layer 108 increases, reducing oxygen deficiencies (V) in the channel formation region. Ｏ ) and V Ｏ H can be reduced. Therefore, a transistor exhibiting good electrical characteristics and high reliability can be realized. In addition, oxidation of the conductive layer 104 by oxygen contained in the insulating layer 110a and insulating layer 110b, respectively, and the resulting increase in the electrical resistance of the conductive layer 104 can be suppressed. As a result, a transistor exhibiting good electrical characteristics and high reliability can be realized. The aforementioned materials can be used as the barrier film. For example, silicon nitride, aluminum oxide, and one or more of the aluminum nitride can be suitably used in one or more of the layers constituting the insulating layer 106.

[0237] [Insulating layer 119] The insulating layer 119 preferably has one or more inorganic insulating layers. The insulating layer 119 can be made from materials that can be used for insulating layer 110a and insulating layer 110b, respectively.

[0238] The insulating layer 119 has a region that is in contact with the semiconductor layer 108. It is preferable to use an insulating layer containing oxygen on at least the side of the insulating layer 119 that is in contact with the semiconductor layer 108. It is also preferable to use an insulating layer that releases oxygen when heated. This allows, for example, when a metal oxide is used for the semiconductor layer 108, the oxygen contained in the insulating layer 119 to be supplied to the metal oxide. This reduces oxygen deficiencies (V) in the metal oxide. Ｏ Since the damage can be repaired, the electrical characteristics and reliability of transistor 100 can be improved.

[0239] Furthermore, the insulating layer 119 has regions that are in contact with both the insulating layer 110a and the insulating layer 110b. Therefore, it is preferable that the insulating layer 119 is an insulating layer that allows oxygen to diffuse easily. This allows oxygen present in both the insulating layer 110a and the insulating layer 110b to be supplied to the semiconductor layer 108 via the insulating layer 119. Therefore, for example, when a metal oxide is used for the semiconductor layer 108, both the oxygen present in the insulating layer 119 and the oxygen present in both the insulating layer 110a and the insulating layer 110b can be supplied to the metal oxide. This reduces oxygen deficiencies (V) in the metal oxide. Ｏ Since the ) can be further repaired, the electrical characteristics and reliability of transistor 100 can be further improved.

[0240] For example, one or more insulating oxides, oxidized nitrides, nitride oxides, and nitrides can be used for the insulating layer 119. For example, one or more silicon oxide, silicon oxidized nitride, silicon oxide nitride, silicon nitride, aluminum oxide, aluminum oxide nitride, aluminum oxide nitride, aluminum nitride, hafnium oxide, hafnium oxide nitride, gallium oxide, gallium oxide nitride, yttrium oxide, yttrium oxide nitride, and Ga-Zn oxide can be used for the insulating layer 119. For example, it is preferable to use one or more silicon oxide and silicon oxidized nitride for the insulating layer 119.

[0241] Although the insulating layer 119 is shown as a single layer in Figure 1B, etc., the present invention is not limited to this. The insulating layer 119 can also be a laminated structure of two or more layers. For example, the insulating layer 119 can be a laminated structure of oxide and nitride.

[0242] It is preferable that the insulating layer 119 releases little impurities (e.g., water and hydrogen) from itself. By reducing the release of impurities from the insulating layer 119, the diffusion of such impurities into the semiconductor layer 108 is suppressed, enabling the realization of a transistor 100 that exhibits good electrical characteristics and is highly reliable.

[0243] [Insulating layer 116] It is preferable to use an insulating material that can suppress oxygen permeation (an insulating material having barrier properties against oxygen) for the insulating layer 116. The insulating layer 116 can be made from the same materials that can be used for the insulating layers 110a1, 110a3, 110b1, and 110b3 described above.

[0244] For the insulating layer 116, one or more of the following can be suitably used: aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, zinc gallium oxide, aluminum nitride, silicon nitride, and silicon nitride oxide.

[0245] The insulating layer 116 can also be a laminated structure. For example, the insulating layer 116 can be a laminated structure of an aluminum oxide film and a silicon nitride film on the aluminum oxide film.

[0246] The thickness of the insulating layer 116 is preferably about the same as the thickness of the insulating layer 110a1, insulating layer 110a3, insulating layer 110b1, or insulating layer 110b3. For example, the thickness of the insulating layer 116 is preferably 3 nm to 500 nm, more preferably 5 nm to 400 nm, more preferably 10 nm to 300 nm, more preferably 20 nm to 300 nm, more preferably 50 nm to 300 nm, more preferably 100 nm to 300 nm, and more preferably 100 nm to 200 nm.

[0247] The thickness of the insulating layer 116 is preferably such that it functions as a barrier film against oxygen. If the insulating layer 116 is too thick, the amount of impurities (e.g., water and hydrogen) released from the insulating layer 116 increases, and the amount of impurities that diffuse into the channel formation region of the semiconductor layer 108 via the insulating layer 106 may increase. On the other hand, if the insulating layer 116 is too thin, its function as a barrier film against oxygen may be reduced. By setting the thickness of the insulating layer 116 within the aforementioned range, an insulating layer with sufficient barrier properties against oxygen can be obtained without increasing the amount of impurities that diffuse into the channel formation region of the semiconductor layer 108. Note that the thickness of the insulating layer 116 is not limited to the aforementioned range.

[0248] [Substrate 102] There are no major restrictions on the material of the substrate 102, but it must have at least enough heat resistance to withstand subsequent heat treatment. For example, single-crystal semiconductor substrates made of silicon or silicon carbide, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SOI (Silicon On Insulator) substrates, glass substrates, quartz substrates, sapphire substrates, ceramic substrates, or resin substrates can be used as the substrate 102. In addition, a substrate on which semiconductor elements are provided can be used as the substrate 102. A substrate with an insulating film formed on its surface can be used as the substrate 102. The shape of the substrate 102 is not particularly limited and can be circular or rectangular, for example.

[0249] A flexible substrate can be used as the substrate 102, and transistors 100, etc., can be formed directly on the flexible substrate. Alternatively, a release layer can be provided between the substrate 102 and the transistors 100, etc. By providing a release layer, after partially or completely completing the semiconductor device on it, it can be separated from the substrate 102 and transferred to another substrate. In this case, the transistors 100, etc., can also be transferred to a substrate with low heat resistance or a flexible substrate.

[0250] In this specification, flexibility refers to the property of an object being flexible and able to bend. It is the property of an object being able to deform in response to an external force applied to it, and does not concern itself with elasticity or the ability to restore to its original shape.

[0251] For example, flexible electronic devices can deform in response to external forces. Flexible electronic devices can be used fixed in a deformed state, repeatedly deformed and used, or used in an undeformed state. Similarly, flexible display devices (also called flexible display devices, flexible display devices, flexible displays, etc.) can deform in response to external forces. Flexible display devices can be used fixed in a deformed state, repeatedly deformed and used, or used in an undeformed state. Furthermore, flexible substrates (also called flexible substrates, flexible substrates, etc.) can deform in response to external forces. Flexible substrates can be used fixed in a deformed state, repeatedly deformed and used, or used in an undeformed state. Note that "deforms in response to external forces" above means that it can be deformed by an average adult's hand without requiring excessive force. Note that flexibility can be quantified as the deformation of an object in response to an external force using testing machines capable of stress-strain measurement (tensile testing machines, compression testing machines, etc.).

[0252] Furthermore, in this specification, when an object is described as having flexibility, it means that at least a part of the object is flexible. In other words, a flexible object may also have parts that do not have flexibility (also called rigid parts).

[0253] Furthermore, in this specification, a highly flexible object is defined as the object that deforms more when two objects are deformed with the same external force. Also, when a first part and a second part of an object are deformed with the same external force, the part that deforms more is considered to be the highly flexible part.

[0254] The following describes a semiconductor device configuration example that differs in some aspects from the previously described configuration example. Note that in the following, explanations of parts that overlap with the previously described configuration example may be omitted. Also, in the drawings shown below, parts having the same function as the previously described configuration example may use the same hatching pattern and may not be labeled with reference numerals.

[0255] <Configuration Example 2> A plan view of a semiconductor device 10A, which is one embodiment of the present invention, is shown in Figure 7A. A cross-sectional view along the dashed line A1-A2 shown in Figure 7A is shown in Figure 7B, and a cross-sectional view along the dashed line B1-B2 is shown in Figure 7C.

[0256] The semiconductor device 10A includes a transistor 100A, an insulating layer 109, an insulating layer 110a, an insulating layer 110b, and an insulating layer 116. The semiconductor device 10A differs from the semiconductor device 10 shown in Figure 1B, etc., in that the areas of the insulating layers 110a and 110b in a plan view are larger than the areas of the conductive layer 103 and 112b, and the insulating layer 116 has a region in contact with the upper surface of the insulating layer 110b. In Figure 7A, the opening corresponding to the opening 145 (see Figure 1A) in the semiconductor device 10 is shown as opening 146.

[0257] In the semiconductor device 10A, the upper surface shape of the conductive layer 112b does not match the upper surface shapes of the insulating layer 110a and the insulating layer 110b. The insulating layer 110a and the insulating layer 110b each have a region that protrudes more than the conductive layer 112b. In a plan view, it is preferable that the insulating layer 110a and the insulating layer 110b encompass the conductive layer 112b. As shown in Figure 7C, the insulating layer 110b has a region on its upper surface where the conductive layer 112b is provided and a region where the conductive layer 112b is not provided. In the region where the conductive layer 112b is not provided, the insulating layer 116 is in contact with the upper surface of the insulating layer 110b.

[0258] For example, an insulating film that will become the insulating layer 110a and a conductive film that will become the conductive layer 103 are deposited in this order, and a first mask layer (for example, a resist mask) is formed on the conductive film. Then, by processing the conductive film using the first mask layer as a mask, a conductive layer (the conductive layer that will become the conductive layer 103) extending in the X direction is formed. Subsequently, an insulating film that will become the insulating layer 110b and a conductive film that will become the conductive layer 112b are deposited in this order on the conductive layer and on the insulating film that will become the insulating layer 110a, and the aforementioned first mask layer is formed again on the conductive film. Then, by processing the conductive film using the first mask layer as a mask, a conductive layer (the conductive layer that will become the conductive layer 112b) extending in the X direction is formed. Next, a second mask layer (for example, a resist mask) is formed on the conductive layer, and the insulating film that will become the insulating layer 110a, the conductive layer that will become the conductive layer 103, the insulating film that will become the insulating layer 110b, and the conductive layer that will become the conductive layer 112b are processed using the second mask layer as a mask, thereby forming the insulating layer 110a, the conductive layer 103, the insulating layer 110b, and the conductive layer 112b, respectively, whose sides are aligned or roughly aligned.

[0259] By forming insulating layers 110a and 110b, and conductive layers that become conductive layer 103 and conductive layer 112b, using different mask layers, the degree of freedom in the layout of insulating layers 110a and 110b can be increased. For example, by increasing the area on which insulating layers 110a and 110b are provided, the amount of oxygen supplied from insulating layers 110a and 110b to the semiconductor layer 108 can be increased. This reduces oxygen deficiencies (V) in the channel formation region. Ｏ ) and V Ｏ H can be reduced.

[0260] Furthermore, while Figure 7A and other figures show a configuration in which one transistor (here, transistor 100A) is provided on a side surface where the respective edges of insulating layer 110a and insulating layer 110b coincide or substantially coincide, the present invention is not limited to this. Multiple transistors can also be provided on the above side surface. For example, multiple transistors can be provided by providing multiple semiconductor layers on the above side surface.

[0261] Regarding semiconductor device 10A, for details other than those described above, please refer to the information provided for semiconductor device 10.

[0262] <Configuration Example 3> Figure 8A shows a plan view of a semiconductor device 10B, which is one embodiment of the present invention. Figure 8B shows a cross-sectional view along the dashed line A1-A2 shown in Figure 8A, and Figure 8C shows a cross-sectional view along the dashed line B1-B2.

[0263] The semiconductor device 10B includes a transistor 100B, an insulating layer 109, an insulating layer 110a, an insulating layer 110b, and an insulating layer 116. The semiconductor device 10B mainly differs from the semiconductor device 10 shown in Figure 1B, etc., in that the insulating layers 110a and 110b are separated by grooves (also called slits). In Figure 8A, the opening corresponding to the opening 145 in the semiconductor device 10 (see Figure 1A) is shown as opening 147.

[0264] The insulating layer 110a, the conductive layer 103, and the insulating layer 110b have slits 137 that reach the conductive layer 112a and the insulating layer 109. As shown in Figure 8B, the insulating layer 110a, the conductive layer 103, and the insulating layer 110b have a pair of sides (side A1 and side A2) facing each other across the slits 137. Both sides include a portion located on the conductive layer 112a and a portion located on the insulating layer 109. An insulating layer 119 is provided in contact with each of these two sides.

[0265] A conductive layer 103 and a conductive layer 103S are provided on the insulating layer 110a, and a conductive layer 112b and a conductive layer 112bS are provided on the insulating layer 110b. The conductive layer 103S is the portion of the conductive layer 103 that remains after being separated when the slit 137 is formed. The conductive layer 103 is provided on the insulating layer 110a on the A2 side, and the conductive layer 103S is provided on the insulating layer 110a on the A1 side. Note that a configuration without the conductive layer 103S is also possible. The conductive layer 112bS is the portion of the conductive layer 112b that remains after being separated when the slit 137 is formed. The conductive layer 112b is provided on the insulating layer 110b on the A2 side, and the conductive layer 112bS is provided on the insulating layer 110b on the A1 side. Note that a configuration without the conductive layer 112bS is also possible.

[0266] The semiconductor layer 108 has regions that are in contact with the upper surface and curved portion of the insulating layer 119, the upper surface of the conductive layer 112b, the upper surface of the conductive layer 112bS, and the upper surface of the conductive layer 112a. The semiconductor layer 108 has a shape that conforms to the shape of the upper surface and curved portion of the insulating layer 119, the upper surface of the conductive layer 112b and the upper surface of the conductive layer 112bS, and the upper surface of the conductive layer 112a. The semiconductor layer 108 is provided spanning the region on the conductive layer 112a where the insulating layers 110a and 110b are provided and the region on the conductive layer 112a where the insulating layers 110a and 110b are not provided. Furthermore, the semiconductor layer 108 is provided not only on the A2 side surface of the insulating layer 110a and 110b, but also on the A1 side surface of the insulating layer 110a and 110b.

[0267] An insulating layer 106 is provided on the semiconductor layer 108, and a conductive layer 104 is provided on the insulating layer 106. The conductive layer 104 has a region that faces the A2 side surface of the insulating layers 110a and 110b via the insulating layer 106 and the semiconductor layer 108. The conductive layer 104 also has a region that faces the A1 side surface of the insulating layers 110a and 110b via the insulating layer 106 and the semiconductor layer 108. The conductive layer 103S is not connected to the conductive layer 103 and is not connected to either the source electrode or the gate electrode (first gate electrode). The conductive layer 112bS is not connected to the conductive layer 112b and is not connected to either the source electrode or the drain electrode. Therefore, the region of the semiconductor layer 108 that is in contact with the A1 side surface of the insulating layers 110a and 110b does not function as a channel formation region of the transistor 100B. The region of the semiconductor layer 108 that is in contact with the A2 side surface of the insulating layer 110a and the insulating layer 110b functions as the channel formation region of the transistor 100B.

[0268] It is preferable that the conductive layer 104 covers not only the channel formation region but also the entire semiconductor layer 108. This helps to suppress damage to the semiconductor layer 108 when the layer is formed on the transistor 100B. However, it is also possible to have a configuration in which the semiconductor layer 108 has regions that are not covered by the conductive layer 104.

[0269] Figure 8A and others show a configuration in which the insulating layer 110a, the conductive layer 103, and the insulating layer 110b are divided into two by a slit 137 extending in one direction. The shape of the upper surface of the slit 137 is not particularly limited.

[0270] Figure 8A and others show a configuration in which one transistor (here, transistor 100B) is provided on a side surface where the respective ends of insulating layer 110a and insulating layer 110b coincide or approximately coincide. However, the present invention is not limited to this. Multiple transistors can also be provided on the above side surface. For example, multiple transistors can be provided by providing multiple semiconductor layers on the A2 side of the insulating layer 110a and insulating layer 110b of the semiconductor layer 108.

[0271] Regarding semiconductor device 10B, for details other than those described above, please refer to the information provided for semiconductor device 10.

[0272] <Configuration Example 4> Figure 9A shows a plan view of a semiconductor device 10C, which is one embodiment of the present invention. Figure 9B shows a cross-sectional view along the dashed line A1-A2 shown in Figure 9A, and Figure 9C shows a cross-sectional view along the dashed line B1-B2.

[0273] The semiconductor device 10C includes a transistor 100C, an insulating layer 109, an insulating layer 110a, an insulating layer 110b, and an insulating layer 116. The semiconductor device 10C mainly differs from the semiconductor device 10 shown in Figure 1B, etc., in that the insulating layer 110a, the conductive layer 103, the insulating layer 110b, and the conductive layer 112b have openings. In Figure 9A, the opening corresponding to the opening 145 in the semiconductor device 10 (see Figure 1A) is shown as opening 148.

[0274] The insulating layer 110a, conductive layer 103, insulating layer 110b, and conductive layer 112b each have an opening 141 that reaches the conductive layer 112a. The opening 141 includes the opening in the insulating layer 110a, the opening in the conductive layer 103, the opening in the insulating layer 110b, and the opening in the conductive layer 112b. It can also be said that the upper surface of the conductive layer 112a, the side surface of the insulating layer 110a, the side surface of the conductive layer 103, the side surface of the insulating layer 110b, and the side surface of the conductive layer 112b are exposed at the opening 141. An insulating layer 119 is provided in contact with the side walls of the opening 141 (the side surface of the insulating layer 110a, the side surface of the conductive layer 103, the side surface of the insulating layer 110b, and the side surface of the conductive layer 112b).

[0275] In a plan view, the semiconductor layer 108 is provided such that it has a region that overlaps with the opening 141.

[0276] A semiconductor layer 108 is provided on an insulating layer 119, an insulating layer 106 is provided on the semiconductor layer 108, and a conductive layer 104 is provided on the insulating layer 106. The insulating layer 119, the semiconductor layer 108, the insulating layer 106, and the conductive layer 104 each have a region located within the opening 141.

[0277] Figure 9A and others show that the top surface shape of the opening 141 is a quadrilateral with rounded corners, but the present invention is not limited to this. The top surface shape of the opening 141 is not limited and can be, for example, a circle, an ellipse, a triangle, a quadrilateral (including rectangles, rhombuses, and squares), a pentagon, or a polygon with rounded corners. The polygon can be either a concave polygon (a polygon in which at least one interior angle exceeds 180 degrees) or a convex polygon (a polygon in which all interior angles are 180 degrees or less). By making the top surface shape of the opening 141 circular, the processing accuracy when forming the opening 141 can be improved, and a fine-sized opening 141 can be formed. In this specification, the term "circular" is not limited to a perfect circle.

[0278] The opening 141 is provided only in the semiconductor layer 108 and its vicinity, while the insulating layer 110a and insulating layer 110b are provided in the remaining areas. Therefore, the area of ​​the region where the insulating layers 110a and 110b are provided can be increased, and the unevenness caused by the difference between the region where the insulating layers 110a and 110b are provided and the region where they are not can be reduced. As a result, the coverage of the layers provided on the transistor 100C and on the insulating layers 110a and 110b can be improved, and defects such as step breaks or porosity in the layers can be suppressed.

[0279] Furthermore, in semiconductor device 10C, the semiconductor layer 108, insulating layer 106, and conductive layer 104 are stacked in this order against the two sides (side A1 and side A2) of the insulating layer 110a and insulating layer 110b within the opening 141. Therefore, the transistor 100C in semiconductor device 10C can output twice the on-current compared to the transistor 100 in semiconductor device 10, the transistor 100A in semiconductor device 10A, etc.

[0280] Regarding semiconductor device 10C, for details other than those described above, please refer to the information provided for semiconductor device 10.

[0281] <Configuration Example 5> Figure 10A shows a plan view of a semiconductor device 10D, which is one embodiment of the present invention. Figure 10B shows a cross-sectional view along the dashed line A1-A2 shown in Figure 10A, and Figure 10C shows a cross-sectional view along the dashed line B1-B2.

[0282] The semiconductor device 10D includes a transistor 100D, an insulating layer 109, an insulating layer 110a, an insulating layer 110b, and an insulating layer 116. The semiconductor device 10D differs from the semiconductor device 10 shown in Figure 1B, etc., mainly in the shape of the semiconductor layer 108 in a plan view.

[0283] As shown in Figures 10A to 10C, in the semiconductor device 10D, a portion of the semiconductor layer 108 is located outside the opening 145. Specifically, in the semiconductor device 10D, the width of the semiconductor layer 108 in the X direction is larger than in the semiconductor device 10, and the A1 and A2 ends of the semiconductor layer 108 are located outside the opening 145. In the semiconductor device 10D, it is not necessary to form the semiconductor layer 108 so that it is enclosed within the opening 145 in a plan view, as is the case with the semiconductor device 10. Therefore, in the semiconductor device 10D, the processing accuracy of the semiconductor layer 108 is not required to the same extent as in the semiconductor device 10, and it can be said that it is easier to manufacture.

[0284] On the other hand, in semiconductor device 10D, a portion of the semiconductor layer 108 has a region located outside the opening 145, which creates a step. However, in semiconductor device 10, no such step is formed. Therefore, semiconductor device 10 can provide better coverage of the film (insulating layer 106, etc.) deposited on the semiconductor layer 108, insulating layer 116, etc., than semiconductor device 10D.

[0285] Furthermore, it is preferable that both ends of the semiconductor layer 108 in the Y direction be formed to be located inside the opening 145. For example, if the semiconductor layer 108 has a region located outside the opening 145 in the Y direction, leakage current may occur between the source and drain of the transistor 100D through that region. Therefore, even if the X-direction ends (one or both sides) of the semiconductor layer 108 are located outside the opening 145, it is preferable that the Y-direction ends (both sides) of the semiconductor layer 108 be formed to be located inside the opening 145.

[0286] Furthermore, the semiconductor layer 108 is formed from the original oxygen vacancies (V) in the metal oxide. Ｏ ) and V ＯWhen using a material with extremely low H content or a state close to high-purity intrinsic, it is not always necessary to position the Y-direction end of the semiconductor layer 108 inside the opening 145. In other words, depending on the material used for the semiconductor layer 108, it may be possible to provide the semiconductor layer 108 with a region located not only outside the X-direction but also outside the Y-direction of the opening 145.

[0287] Regarding semiconductor device 10D, for details other than those described above, please refer to the information provided for semiconductor device 10.

[0288] <Configuration Example 6> A plan view of a semiconductor device 10E, which is one embodiment of the present invention, is shown in Figure 11A. A cross-sectional view along the dashed line A1-A2 shown in Figure 11A is shown in Figure 11B, and a cross-sectional view along the dashed line B1-B2 is shown in Figure 11C.

[0289] The semiconductor device 10E includes a transistor 100E, an insulating layer 109, an insulating layer 110a1, an insulating layer 110b, and an insulating layer 116. The semiconductor device 10E differs from the semiconductor device 10 shown in Figure 1B, etc., mainly in the formation position of the conductive layer 103.

[0290] As shown in Figures 11A and 11B, the semiconductor device 10E has a configuration in which the conductive layer 103, which functions as the second gate electrode (back gate electrode) of the transistor 100E, is provided below the transistor 100 (on the substrate 102 side) of the semiconductor device 10. Furthermore, in the semiconductor device 10, the insulating layer 110a provided between the conductive layer 112a and the conductive layer 103 has a three-layer stacked structure consisting of insulating layer 110a1, insulating layer 110a2, and insulating layer 110a3, whereas in the semiconductor device 10E, it has a single-layer structure consisting only of insulating layer 110a1.

[0291] Because semiconductor device 10E does not have insulating layers 110a2 and 110a3, the number of manufacturing steps for semiconductor device 10 can be reduced compared to semiconductor device 10. On the other hand, semiconductor device 10 has insulating layers 110a2 and 110a3, which allows it to have more layers capable of supplying oxygen to the semiconductor layer 108 than semiconductor device 10. Therefore, semiconductor device 10 can supply more oxygen to the semiconductor layer 108 than semiconductor device 10E.

[0292] Regarding semiconductor device 10E, for details other than those described above, please refer to the content described for semiconductor device 10.

[0293] <Configuration Example 7> A plan view of a semiconductor device 10F, which is one embodiment of the present invention, is shown in Figure 12A. A cross-sectional view along the dashed line A1-A2 shown in Figure 12A is shown in Figure 12B, and a cross-sectional view along the dashed line B1-B2 is shown in Figure 12C.

[0294] The semiconductor device 10F includes a transistor 100F, an insulating layer 109, an insulating layer 110a, an insulating layer 110b, and an insulating layer 116. The semiconductor device 10F differs from the semiconductor device 10 shown in Figure 1B, etc., mainly in the shape of the insulating layer 110a, conductive layer 103, insulating layer 110b, and conductive layer 112b in a plan view.

[0295] As shown in Figures 12A to 12C, the semiconductor device 10F has a configuration in which, compared to the semiconductor device 10, the width in the Y direction of the island-shaped insulating layer 110a, conductive layer 103, insulating layer 110b, and conductive layer 112b is smaller, and in a plan view, the opening 145 and the semiconductor layer 108 are arranged to overlap with one corner of the insulating layer 110a, conductive layer 103, insulating layer 110b, and conductive layer 112b (a corner with an interior angle greater than 0 degrees and less than 180 degrees in a plan view). The above corner can also be rounded.

[0296] Because the semiconductor device 10F has the above-described configuration, the semiconductor layer 108 has a region that faces two sides (i.e., the side shown in Figure 12B and the side on the B2 side shown in Figure 12C) corresponding to the corners of the insulating layer 110a, the conductive layer 103, and the insulating layer 110b, via the insulating layer 119. For this reason, in the semiconductor device 10F, the region of the semiconductor layer 108 facing the two sides can function as the channel formation region of the transistor 100F.

[0297] In transistor 100F, in a plan view, the lengths of the two sides that overlap with the semiconductor layer 108 correspond to the channel width of the transistor. Therefore, the widths in the Y direction of the conductive layers 112a and 112b, which function as the source and drain electrodes of transistor 100F, can be made shorter than those of transistor 100 (Figure 12A shows a configuration where the width in the Y direction of conductive layer 112a is the same as in Figure 1A, and the width in the Y direction of conductive layer 112b is shorter than that of transistor 100). Consequently, the area occupied in a plan view of a transistor with the same channel width can be reduced compared to transistor 100.

[0298] In semiconductor device 10F, the opening 145 and semiconductor layer 108 overlap with only one corner of the insulating layer 110a, conductive layer 103, insulating layer 110b, and conductive layer 112b in a plan view, but this is not limited to this configuration. In one embodiment of the present invention, the opening 145 and semiconductor layer 108 can also overlap with the adjacent corner on the Y-direction side of the aforementioned corner in a plan view. For example, the semiconductor layer 108 can be configured to be in contact with the side shown in Figure 12B, the side shown in Figure 12C on the B2 side, and the side shown in Figure 12C on the B1 side in a cross-sectional view. This makes it possible to increase the channel width of the transistor (i.e., increase the on-current of the transistor) without changing the size of each electrode constituting the transistor (source electrode, drain electrode, and gate electrode) in a plan view.

[0299] Regarding semiconductor device 10F, for details other than those mentioned above, please refer to the content described for semiconductor device 10.

[0300] <Configuration Example 8> A plan view of a semiconductor device 10G, which is one embodiment of the present invention, is shown in Figure 13A. A cross-sectional view along the dashed line A1-A2 shown in Figure 13A is shown in Figure 13B, and a cross-sectional view along the dashed line B1-B2 is shown in Figure 13C.

[0301] The semiconductor device 10G includes a transistor 100G, an insulating layer 109, an insulating layer 110a, an insulating layer 110b, and an insulating layer 116. The semiconductor device 10G differs from the semiconductor device 10 shown in Figure 1B, etc., mainly in the shape of the insulating layer 110a, conductive layer 103, insulating layer 110b, and conductive layer 112b in a plan view.

[0302] As shown in Figures 13A to 13C, the semiconductor device 10G has an island-like arrangement of insulating layer 110a, conductive layer 103, insulating layer 110b, and conductive layer 112b, each having a concave polygonal shape. In a plan view, the opening 145 and the semiconductor layer 108 are arranged to overlap with one corner of the insulating layer 110a, conductive layer 103, insulating layer 110b, and conductive layer 112b (a corner with an interior angle greater than 180 degrees and less than 360 degrees in a plan view). The corner can also be rounded.

[0303] Because the semiconductor device 10G has the above-described configuration, the semiconductor layer 108 has a region that faces two sides (i.e., the side shown in Figure 13B and the side closest to B1 shown in Figure 13C) corresponding to the corners of the insulating layer 110a, the conductive layer 103, and the insulating layer 110b, via the insulating layer 119. For this reason, in the semiconductor device 10G, the region of the semiconductor layer 108 facing these two sides can function as a channel formation region for the transistor 100G.

[0304] In transistor 100G, in a plan view, the lengths of the two sides that overlap with the semiconductor layer 108 correspond to the channel width of the transistor. Therefore, the widths in the Y direction of the conductive layers 112a and 112b, which function as the source electrode and drain electrode of transistor 100G, can be made shorter than those of transistor 100 (Figure 13A shows a configuration in which the widths in the Y direction of both conductive layers 112a and 112b are the same as those in Figure 1A). Consequently, the area occupied in a plan view of a transistor with the same channel width can be reduced compared to transistor 100.

[0305] In semiconductor device 10G, the opening 145 and semiconductor layer 108 overlap with only one corner of the insulating layer 110a, conductive layer 103, insulating layer 110b, and conductive layer 112b in a plan view, but this is not limited to this configuration. In one embodiment of the present invention, similar to semiconductor device 10F described above, the opening 145 and semiconductor layer 108 can also overlap with the corner adjacent to the aforementioned corner in a plan view.

[0306] Regarding semiconductor device 10G, for details other than those described above, please refer to the information provided for semiconductor device 10.

[0307] <Configuration Example 9> Figure 14A shows a plan view of a semiconductor device 10H, which is one embodiment of the present invention. Figure 14B shows a cross-sectional view along the dashed line A1-A2 shown in Figure 14A, and Figure 14C shows a cross-sectional view along the dashed line B1-B2.

[0308] The semiconductor device 10H includes transistor 100H1, transistor 100H2, insulating layer 109, insulating layer 110a, insulating layer 110b, and insulating layer 116. The semiconductor device 10H differs from the semiconductor device 10B shown in Figure 8B, etc., in that it has two transistors.

[0309] As shown in Figures 14A and 14C, in semiconductor device 10H, the A1-side end of the conductive layer 103 and the A1-side end of the conductive layer 112b extend further than semiconductor device 10B, and are provided to have a region that overlaps with the slit 137 in a plan view. As a result, in semiconductor device 10H, the regions where the two opposing sides of the insulating layer 110a, conductive layer 103, and insulating layer 110b, and the semiconductor layer 108 face each other via the insulating layer 119, as shown in Figure 14B, can function as channel formation regions for transistors. Of these, the transistor in which the region of the semiconductor layer 108 facing the A2-side side of the insulating layer 110a, conductive layer 103, and insulating layer 110b is used as the channel formation region is shown as transistor 100H1, and the transistor in which the region of the semiconductor layer 108 facing the A1-side side of the insulating layer 110a, conductive layer 103, and insulating layer 110b is used as the channel formation region is shown as transistor 100H2.

[0310] Transistors 100H1 and 100H2 are transistors that share various components, such as source electrodes, drain electrodes, semiconductor layers, gate insulating layers, and gate electrodes, respectively. That is, in semiconductor device 10H, conductive layer 112a functions as either the source electrode or the drain electrode of transistors 100H1 and 100H2. Conductive layer 112b functions as the other source electrode or drain electrode of transistors 100H1 and 100H2. Semiconductor layer 108 functions as a semiconductor layer having channel-forming regions for transistors 100H1 and 100H2, respectively. Insulating layer 106 functions as the first gate insulating layer of transistors 100H1 and 100H2, respectively. Conductive layer 104 functions as the first gate electrode of transistors 100H1 and 100H2, respectively. Conductive layer 103 functions as the second gate electrode of transistors 100H1 and 100H2, respectively. Furthermore, the insulating layer 119, which functions as the second gate insulating layer for transistors 100H1 and 100H2, is provided separately for each transistor.

[0311] In other words, the semiconductor device 10H, similar to the semiconductor device 10B, has a configuration in which the insulating layer 119, semiconductor layer 108, insulating layer 106, and conductive layer 104 are stacked in this order against the two sides (side A1 and side A2) of the insulating layer 110a, conductive layer 103, and insulating layer 110b within the slit 137. However, in semiconductor device 10B, only the region of the semiconductor layer 108 facing the A2 side of the insulating layer 110a, conductive layer 103, and insulating layer 110b functions as a channel formation region for the transistor (transistor 100B), whereas in semiconductor device 10H, both the region of the semiconductor layer 108 facing the A1 side of the insulating layer 110a, conductive layer 103, and insulating layer 110b, and the region of the semiconductor layer 108 facing the A2 side of the insulating layer 110a, conductive layer 103, and insulating layer 110b, function as channel formation regions for the transistors (transistor 100H2 and transistor 100H1, respectively). Therefore, in semiconductor device 10H, the on-current of the transistors in the semiconductor device can be doubled compared to semiconductor device 10B.

[0312] Regarding semiconductor device 10H, for details other than those described above, please refer to the descriptions provided for semiconductor device 10 and semiconductor device 10B, respectively.

[0313] <Configuration Example 10> A plan view of a semiconductor device 10I, which is one embodiment of the present invention, is shown in Figure 15A. A cross-sectional view along the dashed-dotted line A1-A2 shown in Figure 15A is shown in Figure 15B, and a cross-sectional view along the dashed-dotted line B1-B2 is shown in Figure 15C.

[0314] The semiconductor device 10I includes a transistor 100I, an insulating layer 109, an insulating layer 110a1, an insulating layer 110c, an insulating layer 103b3, and an insulating layer 116. The semiconductor device 10I differs from the semiconductor device 10 shown in Figure 1B, etc., mainly in that it does not have a conductive layer 103, and in the configuration of the insulating layers 110a and 110b.

[0315] As shown in Figures 15B and 15C, in the semiconductor device 10I, the transistor 100I does not have a second gate electrode, and the insulating layer sandwiched between the conductive layer 112a and the conductive layer 112b has a three-layer stacked structure consisting of an insulating layer 110a1, an insulating layer 110c on the insulating layer 110a1, and an insulating layer 110b3 on the insulating layer 110c.

[0316] The insulating layer 110c in the semiconductor device 10I can use the same materials that can be used for the insulating layer 110a2 and insulating layer 110b2 in the semiconductor device 10. That is, the insulating layer 110c can be made of a material that contains oxygen and can release oxygen. As a result, the region sandwiched between the insulating layer 110a1 and the insulating layer 110b3 can be made only of the insulating layer 110c, so that more oxygen can be supplied to the semiconductor layer 108 than in the semiconductor device 10. In addition, in the semiconductor device 10I, the number of manufacturing steps for the semiconductor device can be reduced compared to the semiconductor device 10 because it does not require the formation of the insulating layer 110a3, the conductive layer 103, the insulating layer 110b1, etc. On the other hand, by having a second gate electrode (conductive layer 103) as in the semiconductor device 10I, it is possible to achieve effects such as increasing the on-current of the transistor, decreasing the off-current, shifting the threshold voltage to the normally off side, and improving the saturation characteristics of the current that flows when operating in the saturation region.

[0317] Regarding semiconductor device 10I, for details other than those described above, please refer to the content described for semiconductor device 10.

[0318] <Configuration Example 11> Figure 16A shows a plan view of a semiconductor device 10J, which is one embodiment of the present invention. Figure 16B shows a cross-sectional view along the dashed line A1-A2 shown in Figure 16A, and Figure 16C shows a cross-sectional view along the dashed line B1-B2.

[0319] The semiconductor device 10J includes a transistor 100J, an insulating layer 109, an insulating layer 110d, and an insulating layer 116. The semiconductor device 10J differs from the semiconductor device 10I shown in Figure 15B, etc., mainly in the configuration of the insulating layer sandwiched between the conductive layer 112a and the conductive layer 112b.

[0320] As shown in Figures 16B and 16C, the semiconductor device 10J has only a single-layer insulating layer 110d between the conductive layer 112a and the conductive layer 112b.

[0321] The insulating layer 110d in the semiconductor device 10J can be made of the same material that can be used for the insulating layers 110a1, 110a3, 110b1, and 110b3 in the semiconductor device 10. In other words, a material that does not easily permeate oxygen can be used. As a result, in the semiconductor device 10J, oxygen is not supplied from the insulating layer sandwiched between the conductive layers 112a and 112b to the semiconductor layer 108. However, since an insulating layer 119 that contains and can release oxygen is provided in contact with the semiconductor layer 108, oxygen can be supplied from the insulating layer 119 to the semiconductor layer 108.

[0322] Furthermore, while semiconductor device 10I has three insulating layers (insulating layer 110a1, insulating layer 110c, and insulating layer 110b3) between conductive layer 112a and conductive layer 112b, semiconductor device 10J only requires one insulating layer (insulating layer 110d) between conductive layer 112a and conductive layer 112b. Therefore, semiconductor device 10J can reduce the number of manufacturing steps compared to semiconductor device 10I.

[0323] Regarding semiconductor device 10J, for details other than those described above, please refer to the descriptions of semiconductor device 10 and semiconductor device 10I, respectively.

[0324] <Configuration Example 12> Figure 17A shows a plan view of a semiconductor device 10K, which is one embodiment of the present invention. Figure 17B shows a cross-sectional view along the dashed line A1-A2 shown in Figure 17A, and Figure 17C shows a cross-sectional view along the dashed line B1-B2.

[0325] The semiconductor device 10K includes a transistor 100K, an insulating layer 109, an insulating layer 110a, an insulating layer 110b, and an insulating layer 116. The semiconductor device 10K differs from the semiconductor device 10 mainly in the configuration of the insulating layer 119 and the insulating layer 116 in some cross-sectional directions.

[0326] As shown in Figure 17B, the semiconductor device 10K has the same configuration as the semiconductor device 10 shown in Figure 1B in the direction of the dashed-dotted line A1-A2 in the cross-sectional view in the direction of the dashed-dotted line A1-A2. However, as shown in Figure 17C, the semiconductor device 10K has a different configuration from the semiconductor device 10 shown in Figure 1C in the direction of the dashed-dotted line B1-B2 in the cross-sectional view in the direction of the dashed-dotted line B1-B2. Specifically, in the cross-section in the direction of the dashed-dotted line B1-B2, the semiconductor device 10 has a configuration in which an insulating layer 116 is provided in contact with the side surfaces of the island-shaped insulating layer 110a, conductive layer 103, insulating layer 110b, and conductive layer 112b, and an insulating layer 119 is provided in contact with the upper surface of the insulating layer 116. In contrast, the semiconductor device 10K has a configuration in which an insulating layer 119 is provided in contact with the sides of each of the island-shaped insulating layer 110a, conductive layer 103, insulating layer 110b, and conductive layer 112b, and an insulating layer 116 is provided in contact with the upper surface of the insulating layer 119.

[0327] As explained in the <Example of Manufacturing Method>, by reversing the formation order of the insulating layer 116 and the insulating layer 119 in the manufacturing process of the semiconductor device 10, the same configuration as the semiconductor device 10K can be formed. The semiconductor device 10K can also achieve the same effects as the semiconductor device 10.

[0328] Regarding semiconductor device 10K, for details other than those mentioned above, please refer to the information provided for semiconductor device 10.

[0329] This embodiment can be combined with other embodiments as appropriate. Furthermore, if multiple configuration examples are shown within a single embodiment in this specification, these configuration examples can be combined as appropriate.

[0330] (Embodiment 2) This embodiment describes an indium oxide film that can be used in the semiconductor layer of a transistor in a semiconductor device according to one aspect of the present invention.

[0331] In this specification, indium oxide having at least a crystalline portion or crystalline region in the film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystal IO or crystalline IO include single-crystal indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0332] Indium oxide is a semiconductor material with completely different physical properties from oxide semiconductors such as In-Ga-Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0333] The carrier concentration dependence of the hole (Hall) mobility of indium oxide, silicon, and IGZO is described. Figure 18A shows silicon (Si) and indium oxide (InO Ｘ Figure 18B is a schematic diagram of the carrier concentration dependence of hole mobility for IGZO.

[0334] First, as indicated by the arrows in Figure 18B, IGZO tends to show higher hole mobility as the carrier concentration increases. On the other hand, as indicated by the arrows in Figure 18A, indium oxide tends to show higher hole mobility as the carrier concentration decreases (see Non-Patent Literature 1). This trend is similar to that of silicon, where the lower the concentration of dopants (impurities) in the material, the less impurity scattering occurs and the higher the hole mobility. In other words, the higher the purity and intrinsic nature of indium oxide, the higher its hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to silicon. Note that the properties of indium oxide shown in Figure 18A are assumed to be those of a single crystal. Therefore, when indium oxide is not a single crystal (for example, polycrystalline), the properties may differ from those shown in Figure 18A.

[0335] In Figure 18A, the low carrier concentration range R1 exhibits extremely high hole mobility, making it a suitable carrier concentration range for, for example, the channel formation region of a transistor. For example, in the case of indium oxide, the range R1 has a carrier concentration of 1 × 10⁻⁶. １５ cm −３ This range includes, for example, 1 × 10１４ cm −３ The above is 1 x 10 １８ cm −３ The range is as follows: By sufficiently reducing the carrier concentration, the hole mobility value can be increased to 270 cm⁻¹. ２ It can be expected to be raised to the level of / (V・s).

[0336] Furthermore, in indium oxide, the region where the carrier concentration is within the range R1 may contain elements that lower the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Other elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0337] On the other hand, the range R2 with high carrier concentration has low electrical resistance and can be said to be a suitable range of carrier concentration for applications such as the source and drain regions of a transistor, or for resistors or transparent conductive films. The range R2 is when the carrier concentration value is 1 × 10⁻⁶. ２０ cm −３ This range includes, for example, 1 × 10 １９ cm −３ The above is 1 x 10 ２２ cm −３ The range is as follows: By making the carrier concentration sufficiently high, the resistivity can be increased to 1 × 10⁻⁶. −４ It is expected that the level can be reduced to below Ω·cm.

[0338] Furthermore, in the indium oxide, the region where the carrier concentration is in the range R2 may contain elements that increase the carrier concentration. For example, it is preferable to include elements common to the source and drain electrodes of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use elements in which the oxide is conductive or semiconducting.

[0339] In this way, indium oxide uses regions with low carrier concentrations for the transistor's channel formation region and regions with high carrier concentrations for the transistor's source and drain regions. In other words, indium oxide can be said to be an oxide in which valence electron control is possible. In contrast, with IGZO, strain can form in the source and drain regions due to stress on the electrodes in contact with IGZO, sometimes resulting in the formation of an n-type region. On the other hand, unlike IGZO, indium oxide allows for valence electron control, so it does not require the formation of strain in the film as in IGZO. Less strain in the film is expected to improve reliability. For example, by creating regions with carrier concentrations in the range R1 and range R2 shown in Figure 18A within the indium oxide film, a so-called n-i-n junction (a junction of an n-type region, an i-type region, and an n-type region) can be created. Valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technological concept that would not normally be conceived.

[0340] By applying the above technical concept, the indium oxide transistor described herein has two or more, preferably three or more, more preferably four or more, and most preferably five of the following features (1) to (5): (1) High on-current (in other words, high mobility). (2) Low off-current. (3) Normally off is possible. (4) High reliability. (5) High cutoff frequency (fT). For example, the indium oxide transistor described herein has high mobility, low off-current, and is normally off. This transistor is different from a transistor that is high mobility and normally on.

[0341] Next, we will describe the indium oxide film applied to transistors. The indium oxide film is preferably crystalline (i.e., it has crystal grains). Examples of films with crystal grains include single-crystal films, polycrystalline films, or amorphous films containing crystal grains (also called microcrystalline films). In particular, polycrystalline films are preferred for indium oxide films, and single-crystal films are more preferred. Single-crystal films do not have crystal grain boundaries. Impurities that inhibit carrier flow (typically insulating impurities, insulating oxides, etc.) tend to segregate at crystal grain boundaries. By using a single-crystal film, carrier scattering at crystal grain boundaries can be suppressed, enabling the realization of transistors exhibiting high field-effect mobility. Furthermore, it provides excellent effects such as suppressing variations in transistor characteristics caused by these crystal grain boundaries.

[0342] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using polycrystalline films, it is preferable to use films with the largest possible grain size and few grain boundaries. In a transistor to which a polycrystalline indium oxide film is applied, if there are no grain boundaries in the channel formation region, or if no grain boundaries are observed, the channel formation region is located within the single-crystal region contained in the polycrystalline film, and therefore it can be considered a transistor to which single-crystal indium oxide is applied.

[0343] The crystallinity of indium oxide can be analyzed, for example, by XRD, TEM, or ED. Alternatively, a combination of these methods may be used for analysis.

[0344] Furthermore, in this specification, a semiconductor layer in which no grain boundaries are observed in the channel-forming region, a semiconductor layer in which the channel-forming region is contained within a single crystal grain, or a semiconductor layer in which the direction of the crystal axes is the same in at least two regions within the channel-forming region can be called a single crystal film. In addition, a semiconductor layer in which, within a single crystal grain in the channel-forming region, the direction of other crystal axes changes continuously with respect to a certain crystal axis or crystal orientation as the axis of rotation can be called a single crystal film.

[0345] Note that the channel formation region refers to a region in the semiconductor layer that overlaps (or faces) the gate electrode through the gate insulating layer and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, crystal grains, grain boundaries, crystal axes, crystal orientations, etc. in the channel formation region can be confirmed by cross-sectional observation including the semiconductor layer, the source electrode, and the drain electrode.

[0346] The indium oxide film in the channel formation region preferably has a lower impurity concentration. Impurities in the indium oxide film in the channel formation region can be a scattering source of carriers and thus can be a factor in the decrease in field-effect mobility. In addition, these impurities can also be a factor in inhibiting the crystal growth of the indium oxide film. Examples of impurities for the indium oxide film include boron, silicon, etc. The indium oxide film preferably has a concentration of these impurities of 0.1% or less, more preferably 0.01% (100 ppm) or less, respectively. Note that carbon, hydrogen, etc. are elements that may be contained in the film-forming gas or precursor during film formation and may remain in the indium oxide film more than the above impurities.

[0347] Note that the indium oxide film in the channel formation region may contain an element that can become a trivalent cation the same as indium within the range where its crystal retains a cubic crystal structure (bixbyite type). For example, Group 13 elements of the periodic table such as gallium and aluminum, and Group 3 elements of the periodic table, etc. can be mentioned. Since these elements mainly exist as trivalent cations in the oxide, the carrier concentration of indium oxide can be kept low.

[0348] By using such an indium oxide film in a transistor, the field-effect mobility of the transistor can be made 50 cm ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, even more preferably 200 cm ２ / (V·s) or more, even more preferably 250 cm ２ / (V·s) or more.

[0349] One of the characteristics of the indium oxide film is that it has higher oxygen permeability (diffusivity) compared to the IGZO film. As shown in Fig. 18C, the oxygen (O) diffusing into the indium oxide film (denoted as InO Ｘ ) permeates through the indium oxide film and is released as oxygen molecules (O ２ ). Also, by reacting with hydrogen contained in the film, it may be released as water molecules (H ２ O). Further, when there is oxygen deficiency (V Ｏ ) in the film, the diffusing oxygen atoms fill the oxygen deficiency. Since oxygen diffuses easily in the indium oxide film, it can be said that it is easier to fill oxygen deficiency compared to the IGZO film.

[0350] Thus, since the indium oxide film is likely to reduce oxygen deficiency in the film compared to the IGZO film, by applying such an indium oxide film to a transistor, a transistor showing extremely high reliability can be realized.

[0351] Also, as shown in Fig. 18C, the indium oxide film diffuses hydrogen. The hydrogen diffusing into the indium oxide film from the outside permeates through the indium oxide film and is released as hydrogen molecules (H ２ ). Or, by reacting with oxygen contained in the film, it is released as water molecules.

[0352] A transistor using an indium oxide film is an accumulation-type transistor with electrons as majority carriers. Assuming that the relaxation time of carriers is a constant value, the smaller the effective mass of electrons (carriers), the higher the electron mobility. That is, by using indium oxide with a small effective mass of electrons in a transistor, the on-current or the field-effect mobility of the transistor can be increased.

[0353] In Table 1, single-crystal indium oxide (here, In ２ O ３The effective masses of indium oxide and single-crystal silicon (Si) are shown below. As shown in Table 1, indium oxide is characterized by a small effective electron mass and a large effective hole mass. Furthermore, the effective electron mass of indium oxide is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in transistors, transistors with high field-effect mobility and high frequency characteristics (also called f-characteristics) can be realized. In addition, because the effective hole mass is large, transistors with extremely low off-currents can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width is 1 fA (1 × 10⁻¹⁶) in an environment of 125°C. −１５ A) Less than or equal to, or 1aA (1 × 10 −１８ A) Less than or equal to 1aA (1 × 10) in a room temperature (25°C) environment. −１８ A) Less than or equal to, or 1zA (1 × 10 −２１ A) The following is possible. Furthermore, as shown in Table 1, indium oxide has a smaller effective electron mass and a larger effective hole mass than silicon, so it may be possible to realize a transistor with higher field-effect mobility and lower off-current than a transistor using silicon in the semiconductor layer (hereinafter referred to as a Si transistor).

[0354]

[0355] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. It is preferable to use a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with the indium oxide for the seed layer. This can improve the crystallinity of the indium oxide film. A substrate (for example, a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0356] One method for evaluating the degree of lattice mismatch is to use the following lattice mismatch value. The lattice mismatch Δa [%] of the crystals in the formed film (in this case, the indium oxide film) relative to the crystals in the seed layer is given by Δa = ((L １ -L ２ ) / L２ It is calculated as ) × 100. Here L １ L is the length of the unit cell vector of the crystals in the formed film, or the lattice constant. ２ This is the length of the unit cell vector of the crystal in the seed layer, or the lattice constant.

[0357] The lattice mismatch Δa between the seed layer and the indium oxide film is preferably small in absolute value, and most preferably zero. For example, Δa can be -5% or more and 5% or less, preferably -4% or more and 4% or less, more preferably -3% or more and 3% or less, and even more preferably -2% or more and 2% or less.

[0358] Here, the indium oxide crystal has a cubic structure (bixbite type). For example, yttria-stabilized zirconia (YSZ) crystals can have a cubic structure (fluorite type). The lattice mismatch of the indium oxide crystal with respect to the cubic YSZ crystal is in the range of -2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on a YSZ substrate.

[0359] Furthermore, the crystal structure of the seed layer and the crystal structure of the indium oxide film do not necessarily have to be the same in terms of crystal system or crystal orientation. For example, a film with a hexagonal or trigonal crystal structure can be used beneath an indium oxide film with a cubic crystal structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to crystal orientation necessary for epitaxial growth can be met. Examples of hexagonal or trigonal crystals include wurtzite-type structures and YbFe. ２ O ４ Type structure, Yb ２ Fe ３ O ７ These include type structures and their modified forms. YbFe ２ O ４ Type structure or Yb ２ Fe ３ O ７ An example of a crystal having a type structure is IGZO.

[0360] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0361] (Embodiment 3) In this embodiment, a method for manufacturing a semiconductor device according to one aspect of the present invention will be described with reference to Figures 19A to 27. Note that the description of the materials and formation methods of each element may be omitted if it is the same as that described in Embodiment 1.

[0362] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be deposited using sputtering, chemical vapor deposition (CVD), vacuum deposition, pulsed laser deposition (PLD), atomic layer deposition (ALD), and other methods. CVD methods include plasma chemical vapor deposition (PECVD or plasma CVD) and thermal CVD. One type of thermal CVD is metal-organic chemical vapor deposition (MOCVD).

[0363] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed by wet deposition methods such as spin coating, dip coating, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife coating, slit coating, roll coating, curtain coating, or knife coating.

[0364] When processing thin films that constitute semiconductor devices, lithography or similar methods can be used. Alternatively, thin films can be processed by nanoimprint lithography, sandblasting, lift-off methods, etc. Furthermore, island-shaped thin films can be directly formed by film deposition methods using shielding masks such as metal masks.

[0365] There are two main methods of lithography. One method involves forming a resist mask on the thin film to be processed, then processing the thin film by etching or other means, and finally removing the resist mask. The other method involves forming a photosensitive thin film, then exposing and developing it to process the thin film into the desired shape.

[0366] In lithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Additionally, ultraviolet light, KrF laser light, ArF laser light, etc. can also be used. Moreover, exposure can be performed by immersion lithography technology. Also, extreme ultraviolet (EUV) light or X-rays can be used as the light for exposure. Instead of the light used for exposure, an electron beam can also be used. Using extreme ultraviolet light, X-rays, or an electron beam is preferable because extremely fine processing becomes possible. Note that when performing exposure by scanning a beam such as an electron beam, a photomask is not required.

[0367] For etching of the thin film, one or more of a dry etching method, a wet etching method, and a sandblasting method can be used.

[0368] <Example of Fabrication Method> Here, an example of the fabrication method of the semiconductor device 10 shown in FIGS. 1A to 2A will be described using FIGS. 19A to 27. FIGS. 19A to 22D show cross-sectional views between the dashed-dotted line A1 - A2 shown in FIG. 1A. FIGS. 23A to 27 show perspective views corresponding to FIG. 2A in each fabrication step.

[0369] First, an insulating layer 109 is formed on the substrate 102. For forming the insulating layer 109, a sputtering method or a PECVD method can be preferably used.

[0370] Subsequently, a conductive film that becomes the conductive layer 112a is formed on the insulating layer 109, and the conductive layer 112a is formed by processing the conductive film (FIG. 19A). For forming the conductive film, a sputtering method can be preferably used.

[0371] Subsequently, an insulating film 110a1f that becomes the insulating layer 110a1 and an insulating film 110a2f that becomes the insulating layer 110a2 are formed in this order on the conductive layer 112a (FIG. 19B).

[0372] For the formation of each of the insulating films 110a1f and 110a2f, a sputtering method or a PECVD method can be preferably used. After forming the insulating film 110a1f, it is preferable to form the insulating film 110a2f without exposing the surface of the insulating film 110a1f to the atmosphere. Thereby, it is possible to suppress the adhesion of impurities derived from the atmosphere to the surface of the insulating film 110a1f. Examples of such impurities include water and organic substances. For example, after forming the insulating film 110a1f, it is preferable to continuously form the insulating film 110a2f using the same apparatus.

[0373] The substrate temperature during the formation of the insulating film 110a1f and the insulating film 110a2f is preferably 180°C or higher and 450°C or lower, more preferably 200°C or higher and 450°C or lower, still more preferably 250°C or higher and 450°C or lower, still more preferably 300°C or higher and 450°C or lower, still more preferably 300°C or higher and 400°C or lower, and still more preferably 350°C or higher and 400°C or lower. By setting the substrate temperature during the formation of each of the insulating films 110a1f and 110a2f within the above-mentioned range, the amount of impurities (e.g., water and hydrogen) released from itself can be reduced, and the diffusion of impurities into the semiconductor layer 108 can be suppressed. Therefore, a transistor that exhibits good electrical characteristics and has high reliability can be realized.

[0374] Note that since the insulating films 110a1f and 110a2f are formed prior to the semiconductor layer 108, there is no need to worry about the desorption of oxygen from the semiconductor layer 108 due to the heat applied during the formation of the insulating films 110a1f and 110a2f.

[0375] After forming the insulating films 110a1f and 110a2f, a heat treatment can be performed. By performing the heat treatment, impurities (e.g., water and hydrogen) can be desorbed from the film of the insulating film 110a1f, as well as from the film and the surface of the insulating film 110a2f.

[0376] After the insulating film 110a2f is formed, oxygen can be supplied to the insulating film 110a2f. As a method of supplying oxygen, for example, ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment can be used. As a plasma treatment, a device that turns oxygen gas into plasma using high-frequency power can be suitably used. Examples of devices that turn gas into plasma using high-frequency power include a PECVD device, a plasma etching device, and a plasma ashing device. Plasma treatment is preferably performed in an atmosphere containing oxygen. For example, oxygen, nitrous oxide (N) ２ O), Nitrogen dioxide (NO) ２ It is preferable to perform the plasma treatment in an atmosphere containing one or more of the following: ), carbon monoxide, and carbon dioxide. The amount of oxygen supplied can be adjusted, for example, by the power and processing time in the plasma treatment. In Figure 19C, the supply of oxygen (oxygen 180) to the insulating film 110a2f is schematically shown by arrows.

[0377] After forming the insulating film 110a2f, nitrogen can be supplied to the insulating film 110a2f. For the method of supplying nitrogen, refer to the description of the oxygen supply method described above. Plasma treatment in a nitrogen-containing atmosphere is suitably used as the nitrogen supply method. For example, nitrogen, nitrous oxide (N) ２ O), and nitrogen dioxide (NO) ２ It is preferable to perform the plasma treatment in an atmosphere containing one or more of the following. The amount of nitrogen supplied can be adjusted, for example, by the power and treatment time in the plasma treatment.

[0378] In the insulating layer (here, the insulating film 110a2f or the later insulating layer 110a2), nitrogen oxides are produced by the reaction of nitrogen and oxygen. As nitrogen oxides, for example, N ２ O, NO, and NO ２ For example, in the insulating layer, nitrogen oxides form energy levels, which are located within the band gap of the metal oxide. ２ The transition level at which the charge of 0 transitions between the -1 state lies within the band gap of indium oxide. Therefore, nitrogen oxides (e.g., NO) ２When a negative charge (also called a negative fixed charge) diffuses to or near the interface between the insulating layer and the semiconductor layer having a metal oxide, that level traps electrons. As a result, a negative charge (also called a negative fixed charge) is formed at or near the interface between the insulating layer and the semiconductor layer, which can shift the threshold voltage of the transistor in the positive direction. This makes it possible to realize a normally-off transistor (in the case of an n-channel transistor) and a semiconductor device with low power consumption.

[0379] Increasing the amount of nitrogen oxides can shift the threshold voltage more towards the positive side. However, if the amount of nitrogen oxides is too high, the fluctuation in the threshold voltage when a positive potential (positive bias) is applied to the transistor gate will become large, which may reduce reliability. Therefore, it is preferable to use an amount of nitrogen oxides that does not affect reliability.

[0380] The amount of nitrogen oxides can be evaluated, for example, by the emission amount in thermal desorption spectroscopy (TDS) or by the electron spin amount in electron spin resonance (ESR). In TDS, NO (mass-to-charge ratio (also called m / z) = 30), N ２ O (m / z = 44), and NO ２ The amount of NO (m / z = 46) can be evaluated. ２ In some cases, it is difficult to quantify the amount of NO and N released. ２ By evaluating the amount of O released, NO ２ The amount of NO can be evaluated. In ESR, NO ２ The ESR signal derived from NO can be used. Since N atoms have 7 electrons and O atoms have 8 electrons, NO ２ Molecules have an open-shell structure for electrons. Therefore, neutral NO ２ Because molecules have lone electrons, they can be measured using ESR. １４ Since N has a nuclear spin of 1, １４The peak of the ESR signal involving N splits into three. In this case, the split width of the ESR signal is the hyperfine coupling constant.

[0381] The order of supplying oxygen and supplying nitrogen is not particularly limited. Oxygen can be supplied after supplying nitrogen. Nitrogen can be supplied after supplying oxygen. Alternatively, oxygen and nitrogen can be supplied in the same process. For example, oxygen and nitrogen can be supplied by performing plasma treatment in an atmosphere containing nitrogen and oxygen. For example, nitrous oxide (N) ２ Plasma treatment using O) is preferable because it allows for efficient generation of nitrogen oxides.

[0382] Furthermore, after the insulating film 110a2f is formed, the plasma treatment can be performed without exposing the surface of the insulating film 110a2f to the atmosphere. For example, when a PECVD apparatus is used to form the insulating film 110a2f, it is preferable to perform the plasma treatment in the PECVD apparatus. This can increase productivity. Specifically, after forming the insulating film 110a2f in the PECVD apparatus, the plasma treatment can be performed continuously. ２ It can perform plasma processing.

[0383] Next, it is preferable to deposit a film 130a on the insulating film 110a2f (Figure 19D). Sputtering can be suitably used to deposit the film 130a. It is preferable to carry out the sputtering in an oxygen-containing atmosphere. By depositing the film 130a in an oxygen-containing atmosphere, oxygen can be supplied to the insulating film 110a2f.

[0384] The conductivity of the film 130a is not required. At least one of an insulating film, a semiconductor film, and a conductive film can be used as the film 130a. For example, aluminum oxide, hafnium oxide, hafnium aluminate, indium oxide, indium tin oxide (ITO), or silicon-containing indium tin oxide (ITSO) can be used as the film 130a.

[0385] It is preferable to use an oxide material containing one or more of the same elements as the semiconductor layer 108 as the film 130a. In particular, it is preferable to use an oxide semiconductor applicable to the semiconductor layer 108.

[0386] When forming the film 130a, the higher the oxygen flow rate ratio of the film-forming gas introduced into the processing chamber of the film-forming apparatus, or the higher the oxygen partial pressure in the processing chamber, the greater the amount of oxygen supplied to the insulating film 110a2f. The oxygen flow rate ratio or oxygen partial pressure is preferably, for example, 50% or more and 100% or less, more preferably 60% or more and 100% or less, more preferably 70% or more and 100% or less, more preferably 80% or more and 100% or less, and more preferably 90% or more and 100% or less. In particular, it is preferable to set the oxygen flow rate ratio to 100% and the oxygen partial pressure as close to 100% as possible.

[0387] In this way, by depositing the film 130a by sputtering in an oxygen-containing atmosphere, oxygen can be supplied to the insulating film 110a2f during the deposition of the film 130a, while preventing oxygen from being released from the insulating film 110a2f. As a result, a large amount of oxygen can be trapped in the insulating film 110a2f. Then, a large amount of oxygen can be supplied to the semiconductor layer 108 by subsequent heat treatment. As a result, oxygen vacancies (V) in the semiconductor layer 108 can be reduced. Ｏ ) and V Ｏ This allows for a reduction in H, enabling the realization of a transistor that exhibits good electrical characteristics and high reliability.

[0388] After forming the film 130a, a heat treatment can be performed. By performing a heat treatment after forming the film 130a, oxygen can be effectively supplied from the film 130a to the insulating film 110a2f.

[0389] The heat treatment temperature is preferably 150°C or higher and below the strain point of the substrate, more preferably 200°C to 450°C, more preferably 250°C to 450°C, more preferably 300°C to 450°C, more preferably 300°C to 400°C, and more preferably 350°C to 400°C. The heat treatment can be carried out in an atmosphere containing one or more noble gases, nitrogen, or oxygen. Dry air (CDA: Clean Dry Air) can be used as the nitrogen-containing atmosphere or the oxygen-containing atmosphere. It is preferable that the content of hydrogen, water, etc. in the atmosphere be kept to a minimum. It is preferable to use a high-purity gas with a dew point of -60°C or lower, preferably -100°C or lower, as the atmosphere. By using an atmosphere with a minimum content of hydrogen, water, etc., it is possible to prevent hydrogen, water, etc. from being incorporated into the insulating film 110a1f and insulating film 110a2f as much as possible. For heat treatment, ovens, rapid thermal annealing (RTA) devices, etc., can be used. Using an RTA device can shorten the heat treatment time.

[0390] After forming the film 130a, or after the aforementioned heat treatment, oxygen can also be supplied to the insulating film 110a2f via the film 130a. For example, ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment can be used as methods for supplying oxygen. A detailed explanation of plasma treatment is omitted here, as it can be found in the previous description.

[0391] Next, the film 130a is removed. There are no particular limitations on the method for removing the film 130a, but a wet etching method can be suitably used. By using a wet etching method, etching of the insulating film 110a2f during the removal of the film 130a can be suppressed. This prevents the thickness of the insulating film 110a2f from becoming thinner, and the thickness of the insulating layer 110a2 can be made uniform.

[0392] The process of supplying oxygen to the insulating film 110a2f is not limited to the methods described above. For example, oxygen radicals, oxygen atoms, oxygen atom ions, or oxygen molecular ions can be supplied to the insulating film 110a2f by ion doping, ion implantation, or plasma treatment. Alternatively, a film that suppresses oxygen desorption can be formed on the insulating film 110a2f, and then oxygen can be supplied to the insulating film 110a2f through this film. It is preferable to remove the film after supplying oxygen. As the film that suppresses oxygen desorption mentioned above, a conductive film or semiconductor film having one or more of indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, and tungsten can be used.

[0393] Next, an insulating film 110a3f, which will become the insulating layer 110a3, is deposited on the insulating film 110a2f. For details on depositing the insulating film 110a3f, refer to the description of depositing the insulating films 110a1f and 110a2f.

[0394] When an oxide or oxidized nitride is used for the insulating layer 110a3, oxygen can be supplied to the insulating film 110a2f by depositing the insulating film 110a3f in an oxygen-containing atmosphere. Sputtering is suitably used for depositing the insulating film 110a3f. For example, an aluminum oxide film can be deposited as the insulating film 110a3f using an aluminum target in an oxygen-containing atmosphere by sputtering. When depositing the insulating film 110a3f, the higher the oxygen flow rate ratio of the deposition gas introduced into the processing chamber of the deposition apparatus, or the higher the oxygen partial pressure in the processing chamber, the greater the amount of oxygen supplied to the insulating film 110a2f. The oxygen flow rate ratio or oxygen partial pressure is preferably, for example, 50% or more and 100% or less, more preferably 60% or more and 100% or less, more preferably 70% or more and 100% or less, more preferably 80% or more and 100% or less, and more preferably 90% or more and 100% or less. In particular, it is preferable to set the oxygen flow rate ratio to 100% and to bring the oxygen partial pressure as close to 100% as possible.

[0395] By depositing the insulating film 110a3f in an oxygen-containing atmosphere, oxygen can be supplied to the insulating film 110a2f during the deposition of the insulating film 110a3f, while preventing oxygen from detaching from the insulating film 110a2f. As a result, a large amount of oxygen can be trapped in the insulating film 110a2f. Then, a large amount of oxygen can be supplied to the semiconductor layer 108 by subsequent heat treatment. As a result, oxygen vacancies (V) in the semiconductor layer 108 can be reduced. Ｏ ) and V Ｏ This allows for a reduction in H, enabling the realization of a transistor that exhibits good electrical characteristics and high reliability.

[0396] The insulating film 110a3f can also be subjected to heat treatment after deposition. By performing heat treatment after deposition of the insulating film 110a3f, oxygen can be effectively supplied from the insulating film 110a3f to the insulating film 110a2f.

[0397] Next, a conductive film 103f, which will become the conductive layer 103, is formed on the insulating film 110a3f. For forming the conductive film 103f, for example, sputtering, thermal CVD (including MOCVD), or ALD can be suitably used.

[0398] Next, an insulating film 110b1f, which will become the insulating layer 110b1, and an insulating film 110b2f, which will become the insulating layer 110b2, are deposited on the conductive film 103f in this order (Figure 19E). For details on the deposition of insulating films 110b1f and 110b2f, refer to the description of the deposition of insulating films 110a1f and 110a2f.

[0399] Next, after forming the insulating film 110b1f and insulating film 110b2f, a heat treatment can be performed. By performing the heat treatment, impurities (e.g., water and hydrogen) can be removed from the film of insulating film 110b1f and from the film and surface of insulating film 110b2f.

[0400] After the insulating film 110b2f is formed, oxygen can be supplied to the insulating film 110b2f (Figure 20A). For information on how to supply oxygen to the insulating film 110b2f, please refer to the description of how to supply oxygen to the insulating film 110a2f.

[0401] After forming the insulating film 110b2f, nitrogen can be supplied to the insulating film 110b2f. Regarding the supply of nitrogen to the insulating film 110b2f, reference can be made to the description regarding the supply of nitrogen to the insulating film 110a2f.

[0402] Subsequently, it is preferable to form the film 130b on the insulating film 110b2f (FIG. 20B). Regarding the formation of the film 130b, reference can be made to the description regarding the formation of the film 130a. By forming the film 130b, oxygen can be supplied to the insulating film 110b2f.

[0403] After forming the film 130b, a heat treatment can be performed. Regarding the heat treatment, reference can be made to the description regarding the heat treatment performed after forming the film 130a. By performing the heat treatment after forming the film 130b, oxygen can be effectively supplied from the film 130b to the insulating film 110b2f.

[0404] Subsequently, the film 130b is removed. Regarding the removal of the film 130b, reference can be made to the description regarding the removal of the film 130a.

[0405] Note that the process of supplying oxygen to the insulating film 110b2f is not limited to the above-described method, and the processes applicable to the insulating film 110a2f can also be applied to the insulating film 110b2f.

[0406] Subsequently, an insulating film 110b3f that becomes the insulating layer 110b3 is formed on the insulating film 110b2f. Regarding the formation of the insulating film 110b3f, reference can be made to the description regarding the formation of the insulating film 110a1f and the insulating film 110a2f.

[0407] After forming the insulating film 110b3f, a heat treatment can also be performed. By performing the heat treatment after forming the insulating film 110b3f, oxygen can be effectively supplied from the insulating film 110b3f to the insulating film 110b2f.

[0408] Subsequently, a conductive film 112bf that becomes the conductive layer 112b is formed on the insulating film 110b3f (FIG. 20C). For the formation of the conductive film 112bf, a sputtering method can be preferably used.

[0409] Next, the conductive film 112bf, insulating film 110b3f, insulating film 110b2f, insulating film 110b1f, conductive film 103f, insulating film 110a3f, insulating film 110a2f, and insulating film 110a1f are processed into island shapes to form conductive layer 112b, insulating layer 110b3, insulating layer 110b2, insulating layer 110b1, conductive layer 103, insulating layer 110a3, insulating layer 110a2, and insulating layer 110a1, respectively (Figures 20D and 23A). This forms insulating layer 110a having insulating layers 110a1, 110a2, and 110a3, and insulating layer 110b having insulating layers 110b1, 110b2, and 110b3. The insulating layer 110a, the conductive layer 103, the insulating layer 110b, and the conductive layer 112b are formed to have a region that overlaps with the conductive layer 112a. For example, a wet etching method can be suitably used to form the conductive layer 112b and the conductive layer 103. For example, a dry etching method can be suitably used to form the insulating layer 110a and the insulating layer 110b.

[0410] The conductive layer 112b, insulating layer 110b, conductive layer 103, and insulating layer 110a can be formed, for example, using the same resist mask. After forming the insulating film that will become the insulating layer 110a (insulating film 110a1f, insulating film 110a2f, and insulating film 110a3f), the conductive film 103f, the insulating film that will become the insulating layer 110b (insulating film 110b1f, insulating film 110b2f, and insulating film 110b3f), and the conductive film 112bf, a resist mask is formed on the conductive film 112bf, and the conductive film 112bf is used as a mask to process the conductive film 112bf, the insulating film that will become the insulating layer 110b, the conductive film 103f, and the insulating film that will become the insulating layer 110a, respectively, thereby forming the conductive layer 112b, insulating layer 110b, conductive layer 103, and insulating layer 110a. Productivity can be increased by using the same resist mask for forming the conductive layer 112b, insulating layer 110b, conductive layer 103, and insulating layer 110a. Furthermore, the top surface shapes of the conductive layer 112b, insulating layer 110b, conductive layer 103, and insulating layer 110a can be made identical or approximately identical. Alternatively, different resist masks can be used for forming the conductive layer 112b, the insulating layer 110b, the conductive layer 103, and the insulating layer 110a. In this case, for example, the aforementioned semiconductor device 10A can be manufactured.

[0411] Next, an insulating film 116f, which will become an insulating layer 116, is formed to cover the insulating layer 109, conductive layer 112a, insulating layer 110a, conductive layer 103, insulating layer 110b, and conductive layer 112b (Figures 21A and 23B). The insulating film 116f is provided in contact with the upper surface of the insulating layer 109, the upper and side surfaces of the conductive layer 112a, the side surfaces of the insulating layer 110a, the side surfaces of the conductive layer 103, the side surfaces of the insulating layer 110b, and the upper and side surfaces of the conductive layer 112b.

[0412] For the deposition of the insulating film 116f, refer to the descriptions relating to the deposition of insulating films 110a1f, 110a3f, 110b1f, and 110b3f, respectively.

[0413] Next, a portion of the insulating film 116f is removed to form an opening (opening 145 shown in Figure 1A). This opening is formed such that, in a plan view, it has regions that overlap with the conductive layer 112a and the conductive layer 112b. As a result, the insulating layer 116 is formed from the insulating film 116f (Figures 21B and 24A). In the region overlapping with the opening, the upper surface of the conductive layer 112a, the side surface of the insulating layer 110a, the side surface of the conductive layer 103, the side surface of the insulating layer 110b, and the upper and side surfaces of the conductive layer 112b are exposed, respectively.

[0414] Next, an insulating film 119f is formed to cover the insulating layer 116, conductive layer 112a, insulating layer 110a, conductive layer 103, insulating layer 110b, and conductive layer 112b, forming an insulating layer 119 (Figures 21C and 24B). The insulating film 119f is provided in contact with the upper surface of the insulating layer 116, the upper surface of the conductive layer 112a, the side surface of the insulating layer 110a, the side surface of the conductive layer 103, the side surface of the insulating layer 110b, and the upper and side surfaces of the conductive layer 112b. For forming the insulating film 119f, for example, the PECVD method, the sputtering method, or the ALD method can be suitably used. By using the ALD method, the insulating film 119f can be formed with good coverage on the side surface of the insulating layer 110a, the side surface of the conductive layer 103, and the side surface of the insulating layer 110b.

[0415] Next, the insulating layer 119 is formed by removing a portion of the insulating film 119f by etching (Figures 21D and 25A). Specifically, a portion of the insulating film 119f (the region in contact with the upper surface of the insulating layer 116, the region in contact with the upper surface of the conductive layer 112a, and the region in contact with the upper surface of the conductive layer 112b) is removed by etching. Then, the insulating layer 119 can be formed by leaving only the regions of the insulating film 119f that are facing the sides of the insulating layer 110a, the side of the conductive layer 103, and the side of the insulating layer 110b, respectively. Inside the opening 145, the insulating layer 119 has regions in contact with the sides of the insulating layer 110a, the side of the conductive layer 103, the side of the insulating layer 110b, and the side of the conductive layer 112b, respectively, and outside the opening 145, it has a region in contact with the upper surface of the insulating layer 116. Note that, as shown in Figure 21D, the upper end of the insulating layer 119 may become curved as a result of this etching.

[0416] For etching the insulating film 119f, for example, anisotropic etching can be used. More specifically, for example, the insulating layer 119 can be formed by performing highly anisotropic etching in dry etching.

[0417] By changing the anisotropic etching conditions, the height of the upper end of the insulating layer 119 can be adjusted, as shown in Figures 5A to 5D.

[0418] In this example of the manufacturing method, an example is shown in which the insulating layer 119 is formed after the insulating layer 116 is formed. However, this is not the only option, and the insulating layer 116 can also be formed after the insulating layer 119 is formed.

[0419] For example, after forming the conductive layer 112b, insulating layer 110b3, insulating layer 110b2, insulating layer 110b1, conductive layer 103, insulating layer 110a3, insulating layer 110a2, and insulating layer 110a1 shown in Figure 20D, the insulating layer 119 is formed by performing the steps shown in Figures 21C and 21D. Subsequently, the insulating layer 116 can be formed by performing the steps shown in Figures 21A and 21B.

[0420] When forming the insulating layer 119 and insulating layer 116 using the method described above, in the cross-section in the direction of the dashed-dotted line B1-B2 in the plan view of the semiconductor device 10 shown in Figure 1A, the insulating layer 119 is provided in contact with the side surface of the insulating layer 110a, the side surface of the conductive layer 103, the side surface of the insulating layer 110b, and the side surface of the conductive layer 112b, and the insulating layer 116 is provided in contact with the upper surface of the insulating layer 119 (the cross-section in the direction of the dashed-dotted line A1-A2 is the same configuration as in Figure 21D). For example, the same configuration as the semiconductor device 10K shown in Figures 17A to 17C can be formed.

[0421] Next, a metal oxide film 108f, which will become the semiconductor layer 108, is formed to cover the insulating layer 116, the conductive layer 112a, the insulating layer 119, and the conductive layer 112b (Figures 22A and 25B). The metal oxide film 108f is provided in contact with the side and top surfaces of the insulating layer 116, the top surface of the conductive layer 112a, the top surface and curved portion of the insulating layer 119, and the top surface of the conductive layer 112b.

[0422] The metal oxide film 108f is preferably deposited by sputtering using a metal oxide target. Alternatively, the metal oxide film 108f is preferably deposited by the ALD method. By using the ALD method, the metal oxide film 108f can be deposited with good coverage on the upper surface of the insulating layer 119, which is provided in contact with the side surface of the insulating layer 110a, the side surface of the conductive layer 103, and the side surface of the insulating layer 110b. Furthermore, since the deposition rate of the ALD method is easy to control, thin films can be deposited with good yield. Therefore, the ALD method is particularly suitable when the thickness of the metal oxide film 108f is thin. In addition, the CVD method can be used to deposit the metal oxide film 108f instead of the sputtering method and the ALD method.

[0423] It is preferable that the metal oxide film 108f be a dense film with as few defects as possible. Furthermore, it is preferable that the metal oxide film 108f has a high purity, with as few hydrogen-containing impurities as possible. In particular, it is preferable to use a crystalline metal oxide film as the metal oxide film 108f.

[0424] It is preferable to use oxygen gas when forming the metal oxide film 108f. By using oxygen gas, oxygen can be suitably supplied to the insulating layer 119. For example, when an oxide or oxidoxide nitride is used for the insulating layer 119, oxygen can be suitably supplied to the insulating layer 119.

[0425] By supplying oxygen to the insulating layer 119, oxygen is supplied to the semiconductor layer 108 in a later process, and oxygen vacancies (V) in the semiconductor layer 108 are eliminated. Ｏ ) and V Ｏ H can be reduced.

[0426] When forming the metal oxide film 108f, a mixture of oxygen gas and an inert gas (e.g., helium gas, argon gas, xenon gas, etc.) can be used. The higher the oxygen flow rate ratio or oxygen partial pressure of the deposition gas used to form the metal oxide film, the higher the crystallinity of the metal oxide film can be, enabling the realization of a highly reliable transistor. Conversely, the lower the oxygen flow rate ratio or oxygen partial pressure, the lower the crystallinity and the higher the electrical conductivity of the metal oxide film, enabling the realization of a transistor with a large on-current.

[0427] Here, if the oxygen flow rate ratio or oxygen partial pressure is high, the metal oxide film may form a polycrystalline structure. In the case of a polycrystalline metal oxide film, the grain boundaries become recombination centers, trapping carriers and potentially reducing the on-current of the transistor. Therefore, it is preferable to adjust the oxygen flow rate ratio or oxygen partial pressure so that the metal oxide film 108f does not form a polycrystalline structure. Since the likelihood of forming a polycrystalline structure differs depending on the composition of the metal oxide film, it is preferable to adjust the oxygen flow rate ratio or oxygen partial pressure according to the composition of the metal oxide film 108f. However, the present invention is not limited to this, and a polycrystalline metal oxide can also be used. When the grain boundaries of a polycrystalline metal oxide film do not affect the transistor characteristics, a transistor using a polycrystalline metal oxide can be realized with higher reliability than a transistor using a metal oxide with low crystallinity.

[0428] The higher the substrate temperature during metal oxide film deposition, the higher the crystallinity and density of the resulting metal oxide film. This allows for the creation of highly reliable transistors. Conversely, the lower the substrate temperature, the lower the crystallinity and the higher the electrical conductivity of the resulting metal oxide film. This allows for the creation of transistors with high on-current.

[0429] The substrate temperature during the deposition of the metal oxide film 108f is preferably between room temperature and 250°C, more preferably between room temperature and 200°C, and even more preferably between room temperature and 140°C. For example, setting the substrate temperature to between room temperature and 140°C is preferable because it increases productivity. Furthermore, crystallinity can be reduced by depositing the metal oxide film at room temperature or without heating the substrate.

[0430] Furthermore, if the substrate temperature is high, the metal oxide film may develop a polycrystalline structure. It is preferable to vary the substrate temperature depending on the composition of the material used for the metal oxide film 108f.

[0431] When using the ALD method, it is preferable to use a film deposition method such as the thermal ALD method or the PEALD (Plasma Enhanced ALD) method. The thermal ALD method is preferred because it exhibits extremely high coverage. The PEALD method is preferred because, in addition to exhibiting high coverage, it allows for low-temperature film deposition.

[0432] Metal oxide films can be formed, for example, by the ALD method using a precursor containing the constituent metal elements and an oxidizing agent.

[0433] For example, when forming an In-Ga-Zn oxide film, three precursors can be used: an indium-containing precursor, a gallium-containing precursor, and a zinc-containing precursor. Alternatively, two precursors can be used: an indium-containing precursor and precursors containing both gallium and zinc.

[0434] Examples of indium precursors include triethylindium, trimethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionic acid)indium, cyclopentadienylindium, indium(III) chloride, (3-(dimethylamino)propyl)dimethylindium, and [1,1,1-trimethyl-N-(trimethylsilyl)amide]-indium.

[0435] Examples of gallium-containing precursors include trimethylgallium, triethylgallium, gallium trichloride, tris(dimethylamide)gallium(III), gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionic acid)gallium, dimethylchlorogallium, and diethylchlorogallium.

[0436] Examples of tin-containing precursors include tin(IV) chloride and tetrakis(dimethylamide)tin.

[0437] Examples of zinc-containing precursors include dimethylzinc, diethylzinc, bis(2,2,6,6-tetramethyl-3,5-heptanedionic acid) zinc, and zinc chloride.

[0438] Examples of oxidizing agents include ozone, oxygen, and water.

[0439] Methods for controlling the composition of the resulting film include adjusting one or more of the type of raw material gas, the flow rate ratio of the raw material gases, the duration for which the raw material gases are flowed, and the order in which the raw material gases are flowed. By adjusting these factors, the composition of the metal oxide film 108f can be controlled. Furthermore, by adjusting these factors, it is also possible to deposit a metal oxide film 108f with a continuously changing composition.

[0440] Before forming the metal oxide film 108f, it is preferable to perform at least one of the following: a treatment to desorb water, hydrogen, organic matter, etc. adsorbed on the surface of the insulating layer 119, and a treatment to supply oxygen into the insulating layer 119. For example, a heat treatment can be performed in a reduced-pressure atmosphere at a temperature of 70°C to 200°C. Alternatively, a plasma treatment can be performed in an oxygen-containing atmosphere. Alternatively, nitrous oxide (N) can be used. ２ Oxygen can be supplied to the insulating layer 119 by plasma treatment in an atmosphere containing an oxidizing gas such as 0). Plasma treatment containing nitrous oxide gas can suitably remove organic matter from the surface of the insulating layer 119 while supplying oxygen. After such treatment, it is preferable to continuously form the metal oxide film 108f without exposing the surface of the insulating layer 119 to the atmosphere.

[0441] Furthermore, when the semiconductor layer 108 is a stacked structure, it is preferable to deposit the metal oxide film to be deposited first, and then continuously deposit the next metal oxide film without exposing its surface to the atmosphere.

[0442] When the semiconductor layer 108 has a stacked structure, all layers constituting the semiconductor layer 108 can be deposited using the same method (for example, sputtering or ALD). Alternatively, different deposition methods can be used for each layer. For example, the first metal oxide layer can be deposited by sputtering, and the second metal oxide layer on the first metal oxide layer can be deposited by ALD.

[0443] Next, the metal oxide film 108f is processed into island shapes to form a semiconductor layer 108 (Figures 22B and 26A). The semiconductor layer 108 is formed to have regions that overlap with the conductive layer 112a and the conductive layer 112b, respectively. The semiconductor layer 108 has regions that are in contact with the upper surface of the conductive layer 112a, the upper surface of the insulating layer 119, and the upper surface of the conductive layer 112b, respectively. In a plan view, the semiconductor layer 108 is formed to be contained within the aforementioned opening (opening 145 shown in Figure 1A).

[0444] A wet etching method can be suitably used to form the semiconductor layer 108. In this case, parts of the conductive layer 112a, insulating layer 119, and conductive layer 112b in areas that do not overlap with the semiconductor layer 108 may be etched, resulting in a thinner film thickness.

[0445] It is preferable to perform a heat treatment after the metal oxide film 108f has been formed, or after the metal oxide film 108f has been processed into a semiconductor layer 108. The heat treatment can remove hydrogen and water contained in the metal oxide film 108f or the semiconductor layer 108, or adsorbed on the surface. In addition, the heat treatment may improve the film quality of the metal oxide film 108f or the semiconductor layer 108 (for example, by reducing defects or improving crystallinity).

[0446] Oxygen can also be supplied from the insulating layer 119 to the metal oxide film 108f or semiconductor layer 108 by heat treatment. Alternatively, oxygen can be supplied from the insulating layer 110a and the insulating layer 110b to the metal oxide film 108f or semiconductor layer 108 via the insulating layer 119. In this case, it is more preferable to perform the heat treatment before processing the semiconductor layer 108. A detailed explanation of the heat treatment can be found in the above description, so it is omitted here.

[0447] Note that this heat treatment can be omitted if it is not necessary. Alternatively, the heat treatment at this stage can be omitted and combined with a heat treatment performed in a later step. Furthermore, a heat treatment in a later step (for example, a film formation process) may also serve as this heat treatment.

[0448] Next, an insulating layer 106 is formed, covering the semiconductor layer 108, insulating layer 119, insulating layer 116, conductive layer 112a, and conductive layer 112b (Figures 22C and 26B). The insulating layer 106 is provided in contact with the upper and side surfaces of the semiconductor layer 108, the upper surface of the insulating layer 119, the upper surface of the insulating layer 116, the upper surface of the conductive layer 112a, and the upper surface of the conductive layer 112b. For forming the insulating layer 106, for example, the PECVD method, the sputtering method, or the ALD method can be suitably used.

[0449] When an oxide semiconductor is used for the semiconductor layer 108, it is preferable that the insulating layer 106 functions as a barrier film that suppresses the diffusion of oxygen. Because the insulating layer 106 has the function of suppressing oxygen diffusion, the diffusion of oxygen from the insulating layer 106 to the conductive layer 104 is suppressed, thereby suppressing the oxidation of the conductive layer 104. As a result, a transistor exhibiting good electrical characteristics and high reliability can be realized.

[0450] By increasing the temperature during film formation of the insulating layer 106, which functions as a gate insulating layer (first gate insulating layer), an insulating layer with fewer defects can be formed. However, if the temperature during film formation of the insulating layer 106 is high, oxygen will be detached from the semiconductor layer 108, resulting in oxygen vacancies (V) in the semiconductor layer 108. Ｏ ) and V Ｏ In some cases, the H content may increase. The substrate temperature during the deposition of the insulating layer 106 is preferably 180°C to 450°C, more preferably 200°C to 450°C, more preferably 250°C to 450°C, more preferably 300°C to 450°C, and more preferably 300°C to 400°C. By setting the substrate temperature during the deposition of the insulating layer 106 within the above range, defects in the insulating layer 106 can be reduced, and the detachment of oxygen from the semiconductor layer 108 can be suppressed. Therefore, a transistor exhibiting good electrical characteristics and high reliability can be realized.

[0451] Before forming the insulating layer 106, the surface of the semiconductor layer 108 can be subjected to plasma treatment. This plasma treatment can reduce impurities such as water adsorbed on the surface of the semiconductor layer 108. As a result, impurities at the interface between the semiconductor layer 108 and the insulating layer 106 can be reduced, enabling the realization of a highly reliable transistor. This is particularly suitable when the surface of the semiconductor layer 108 is exposed to the atmosphere between the formation of the semiconductor layer 108 and the deposition of the insulating layer 106. The plasma treatment can be performed in an atmosphere such as oxygen, ozone, nitrogen, nitrous oxide, or argon. Furthermore, it is preferable that the plasma treatment and the deposition of the insulating layer 106 are performed continuously without exposure to the atmosphere.

[0452] Next, impurity elements (elements other than the main components constituting the semiconductor layer 108; for example, elements with a concentration of less than 0.1 atomic% in the semiconductor layer 108) can be supplied to the semiconductor layer 108 via the insulating layer 106. It is preferable to use impurity elements that can reduce the resistance of the source and drain regions of the transistor.

[0453] Examples of such impurity elements include one or more of the following: boron, aluminum, indium, carbon, silicon, germanium, tin, phosphorus, arsenic, antimony, magnesium, calcium, titanium, copper, zinc, tungsten, molybdenum, tantalum, hafnium, cerium, and noble gases (helium, neon, argon, krypton, xenon, etc.).

[0454] Furthermore, the impurity elements are not limited to the elements listed above, and may include one or more elements from among the first transition elements (3d transition elements, 3d transition metals), second transition elements (4d transition elements, 4d transition metals), third transition elements (5d transition elements, 5d transition metals), alkaline earth metal elements, and rare earth elements.

[0455] Furthermore, the impurity element can be either the element mentioned above or hydrogen.

[0456] The concentration of the impurity element in the source and drain regions is, for example, 1 × 10⁻⁶ １９ atoms / cm ３ The above 1 x 10 ２３ atoms / cm ３ The following is preferably 5 × 10 １９ atoms / cm ３ The above 5 x 10 ２２ atoms / cm ３ More specifically, 1 x 10 ２０ atoms / cm ３ The above 1 x 10 ２２ atoms / cm ３ It is preferable that the following region be included. If multiple impurity elements are included, it is preferable that the concentration of each impurity element be within the above range.

[0457] By supplying the aforementioned impurity elements to the source and drain regions, these impurity elements remove oxygen from these regions, creating oxygen deficiencies (V) in these regions. Ｏ This creates an oxygen vacancy. Then, when this oxygen vacancy combines with hydrogen in the film, a carrier is generated, which allows the source and drain regions to have lower resistance. As a result, the source and drain regions of the transistor can have lower resistance than the channel formation region. Therefore, the contact resistance between the source region and the source electrode, and the contact resistance between the drain region and the drain electrode of the transistor can be reduced, and the on-current of the transistor can be increased. Furthermore, by increasing the on-current of the transistor, the operating voltage of the transistor can be reduced, which can reduce the power consumption of the semiconductor device.

[0458] Furthermore, the aforementioned impurity elements may also be supplied to the channel formation region in the semiconductor layer 108. Alternatively, due to the effects of heat during the manufacturing process, some of the impurity elements contained in the source region and drain region may diffuse into the channel formation region.

[0459] The concentration of impurity elements contained in the semiconductor layer 108 can be analyzed by analytical methods such as SIMS or XPS. When using XPS analysis, the concentration distribution in the depth direction can be determined by combining ion sputtering from the surface or back side with XPS analysis.

[0460] Ion doping or ion implantation can be suitably used to supply the impurity elements.

[0461] Furthermore, there are no limitations on the method of supplying the impurity elements; for example, plasma treatment or treatment utilizing thermal diffusion by heating can also be used. In the case of plasma treatment, the impurity elements can be supplied by generating plasma in a gas atmosphere containing the impurity elements to be supplied and performing plasma treatment. As the apparatus for generating the plasma, dry etching apparatus, ashing apparatus, plasma CVD apparatus, high-density plasma CVD apparatus, etc., can be used.

[0462] Furthermore, it is preferable to perform the impurity element supply process while heating the substrate 102. This allows for the repair of damage to the semiconductor layer 108 that occurs when the impurity element is supplied. In other words, the supply of impurity elements to the semiconductor layer 108 and the repair of damage caused by such supply can be performed in parallel. In addition, damage to the insulating layer 106 that occurs when the impurity element is supplied can also be repaired.

[0463] The substrate temperature during the supply process of the impurity element is preferably 150°C or higher and below the strain point of the substrate, more preferably 200°C or higher and 500°C or lower, more preferably 200°C or higher and 450°C or lower, more preferably 250°C or higher and 400°C or lower, more preferably 250°C or higher and 350°C or lower, or more preferably 300°C or higher and 350°C or lower.

[0464] After supplying the impurity element, a heat treatment can also be performed. By performing this heat treatment, damage sustained by the semiconductor layer 108 and the insulating layer 106 during the impurity element supply process can be repaired.

[0465] The temperature of the heat treatment after supplying the impurity element is preferably 150°C or higher but below the strain point of the substrate, more preferably 200°C or higher but 500°C or lower, more preferably 200°C or higher but 450°C or lower, more preferably 250°C or higher but 400°C or lower, more preferably 250°C or higher but 350°C or lower, or more preferably 300°C or higher but 400°C or lower, and more preferably 300°C or higher but 350°C or lower.

[0466] Furthermore, if the source and drain regions of the semiconductor layer 108 have sufficiently low resistance, the supply of the impurity element to the semiconductor layer 108 may be omitted. This reduces the number of steps involved in the manufacturing of the semiconductor device.

[0467] Next, a conductive film 104f, which will become the conductive layer 104, is formed on the insulating layer 106 (Figures 22D and 27). For forming the conductive film 104f, for example, sputtering, thermal CVD (including MOCVD), or ALD can be suitably used.

[0468] Next, the conductive film 104f is processed to form a conductive layer 104 (Figures 1B and 2A). The conductive layer 104 is formed to have a region that overlaps with the semiconductor layer 108 in a plan view. For example, a wet etching method can be suitably used to form the conductive layer 104.

[0469] By following the above steps, a semiconductor device 10 according to one aspect of the present invention can be manufactured.

[0470] This embodiment can be combined with other embodiments as appropriate.

[0471] (Embodiment 4) This embodiment describes circuits, layouts, etc., applicable to a display device according to one aspect of the present invention.

[0472] Figure 28 is a block diagram illustrating the display device 200. The display device 200 includes a display unit 435, a first drive circuit unit 431, and a second drive circuit unit 432.

[0473] The display unit 435 has a plurality of pixels 230 arranged in a matrix of m rows (where m is an integer of 1 or more) and n columns (where n is an integer of 1 or more).

[0474] The display unit 435 corresponds, for example, to the display unit 162 in Figure 31, and the pixels 230 correspond, for example, to sub-pixels 11R, 11G, 11B, and 201 in Figure 31.

[0475] In Figure 28, the pixel 230 in the 1st row and nth column is shown as pixel 230[1,n], the pixel 230 in the mth row and 1st column is shown as pixel 230[m,1], and the pixel 230 in the mth row and nth column is shown as pixel 230[m,n]. In addition, any pixel 230 included in the display unit 435 may be shown as pixel 230[r,s]. r is an integer between 1 and m, and s is an integer between 1 and n.

[0476] The circuit included in the first drive circuit section 431 functions, for example, as a scan line drive circuit (also called a gate driver). The circuit included in the second drive circuit section 432 functions, for example, as a signal line drive circuit (also called a source driver). It is also possible to provide some circuit at a position facing the first drive circuit section 431 across the display section 435. Similarly, it is possible to provide some circuit at a position facing the second drive circuit section 432 across the display section 435. The circuits included in the first drive circuit section 431 and the second drive circuit section 432 are collectively referred to as the peripheral drive circuit 433.

[0477] The peripheral drive circuit 433 can utilize various circuits such as a shift register circuit, a level shifter circuit, an inverter circuit, a latch circuit, an analog switch circuit, a multiplexer circuit, a demultiplexer circuit, and a logic circuit. A transistor 100 according to one aspect of the present invention can be used in the peripheral drive circuit 433. Furthermore, the transistors in the peripheral drive circuit and the transistors included in the pixel 230 can be formed in the same process.

[0478] Furthermore, the display device 200 has m wires 436, each arranged substantially parallel to the other and whose potential is controlled by a circuit included in the first drive circuit section 431, and n wires 437, each arranged substantially parallel to the other and whose potential is controlled by a circuit included in the second drive circuit section 432.

[0479] Note that Figure 28 shows an example where wiring 436 and wiring 437 are connected to pixel 230. However, wiring 436 and wiring 437 are just examples, and the wiring connected to pixel 230 is not limited to wiring 436 and wiring 437.

[0480] <Example of Pixel Circuit Configuration> Figures 29A to 30C show an example of the configuration of a pixel 230. The pixel 230 has a pixel circuit 51 (pixel circuit 51A, pixel circuit 51B, pixel circuit 51C, pixel circuit 51D, pixel circuit 51E, pixel circuit 51F, or pixel circuit 51G) and a light-emitting element 61.

[0481] The light-emitting element described in this embodiment refers to a self-emissive display element such as an organic EL element. The light-emitting element connected to the pixel circuit can be a self-emissive light-emitting element such as an LED, microLED, QLED (Quantum-dot LED), or semiconductor laser.

[0482] The pixel circuit 51A shown in Figure 29A is a 2Tr1C type pixel circuit having transistors 52A and 52B, and a capacitor 53. Of the transistors in the pixel circuit 51A, transistor 52B has a back gate (second gate).

[0483] One of the sources or drains of transistor 52A is connected to wiring SL, and the gate of transistor 52A is connected to wiring GL. The other of the sources or drains of transistor 52A is connected to the gate (first gate) of transistor 52B and one terminal of capacitor 53. One of the sources or drains of transistor 52B is connected to wiring ANO. The other of the sources or drains of transistor 52B is connected to the other terminal of capacitor 53 and the anode of light-emitting element 61. The cathode of light-emitting element 61 is connected to wiring VCOM. The back gate of transistor 52B is connected to the other of the sources or drains of transistor 52B, the other terminal of capacitor 53, and the anode of light-emitting element 61. By connecting the back gate of transistor 52B to the other of the sources or drains of transistor 52B, the operation of transistor 52B can be made more stable. The region to which the source or drain of transistor 52A, the gate of transistor 52B, and one terminal of capacitor 53 are connected functions as node ND.

[0484] Wiring GL corresponds to wiring 436, and wiring SL corresponds to wiring 437. Wiring VCOM is a wire that provides a potential for supplying current to the light-emitting element 61. Transistor 52A has the function of controlling the conduction state (a state in which current can flow) or non-conduction state between wiring SL and the gate of transistor 52B based on the potential of wiring GL. For example, VDD is supplied to wiring ANO, and VSS is supplied to wiring VCOM. Transistor 52A can also be called a selection transistor because it functions as a switch for controlling the selection and deselection of the pixel 230.

[0485] By turning transistor 52A ON, an image signal is supplied from wiring SL to node ND. Subsequently, by turning transistor 52A OFF, the image signal is held at node ND. To ensure reliable retention of the image signal supplied to node ND, it is preferable to use a transistor with low off-current for transistor 52A. For example, it is preferable to use an OS transistor as transistor 52A.

[0486] Transistor 52B has the function of controlling the amount of current flowing to the light-emitting element 61. Transistor 52B can also be called a driving transistor. Capacitor 53 has the function of maintaining the gate potential of transistor 52B. The intensity of the light emitted by the light-emitting element 61 is controlled according to the image signal supplied to the gate (node ​​ND) of transistor 52B.

[0487] For example, in the pixel circuit 51A, the transistor 52B having a back gate can be the transistor 100, transistors 100A to 100G, transistor 100H1, or transistor 100H2 shown in Embodiment 1. Alternatively, the transistor 52A without a back gate can be the transistor 100I or transistor 100J shown in Embodiment 1.

[0488] The pixel circuit 51B shown in Figure 29B is a 3Tr1C type pixel circuit having transistors 52A, 52B, 52C, and a capacitor 53. The pixel circuit 51B shown in Figure 29B has a configuration in which transistor 52C is added to the pixel circuit 51A shown in Figure 29A, and the wiring connected to the gate of transistor 52A and the wiring connected to the gate of transistor 52C are each independently configured.

[0489] The back gate of transistor 52B is connected to the other source or drain of transistor 52B, one source or drain of transistor 52C, the other terminal of capacitor 53, and the anode of light-emitting element 61. As described above in the pixel circuit 51A shown in Figure 29A, connecting the back gate of transistor 52B to the other source or drain of transistor 52B makes the operation of transistor 52B more stable.

[0490] Furthermore, the gate of transistor 52A is connected to wiring GL1, and the gate of transistor 52C is connected to wiring GL2. By providing separate wiring for the gates of transistor 52A and transistor 52C, different potentials can be applied to the gates of the two transistors, allowing them to operate independently.

[0491] One of the sources or drains of transistor 52C is connected to the other of the sources or drains of transistor 52B. The other of the sources or drains of transistor 52C is connected to wiring V0. For example, wiring V0 is supplied with a reference potential.

[0492] Transistor 52C has the function of controlling the conduction or non-conduction state between the source or drain of transistor 52B and the wiring V0 based on the potential of the wiring GL2. When an n-channel transistor is used for transistor 52B, the reference potential of the wiring V0 provided via transistor 52C can suppress variations in the gate-source voltage of transistor 52B.

[0493] Furthermore, the wiring V0 can be used to obtain current values ​​that can be used to set pixel parameters. More specifically, the wiring V0 can function as a monitor line for outputting the current flowing through transistor 52B or the current flowing through light-emitting element 61 to the outside. The current output to wiring V0 can be converted into a voltage by a source follower circuit or the like and output to the outside. Alternatively, it can be converted into a digital signal by an A-D converter or the like and output to the outside.

[0494] For example, in the pixel circuit 51B, the transistor 52B having a back gate can be the transistor 100, transistors 100A to 100G, transistor 100H1, or transistor 100H2 shown in Embodiment 1. Also, the transistors 52A and 52C without a back gate can be the transistor 100I or transistor 100J shown in Embodiment 1.

[0495] The pixel circuit 51C shown in Figure 29C has a configuration in which both transistors 52A and 52B of the pixel circuit 51A shown in Figure 29A have back gates, and the back gate of each transistor is connected to the gate of the other transistor. Similarly, the pixel circuit 51D shown in Figure 29D has a configuration in which all transistors 52A, 52B, and 52C of the pixel circuit 51B shown in Figure 29B have back gates, and the back gate of each transistor is connected to the gate of the other transistor. By having all transistors in each of the pixel circuits 51C and 51D have the above configuration, the current that each transistor can supply can be increased. Here, transistors with connected gates and back gates are used for all transistors, but this is not the only option. Transistors in which the gate and back gate are connected to different wiring can also be used. Furthermore, transistors in which either the gate or back gate is connected to the source can also be used. This makes the operation of the transistors more stable.

[0496] For example, transistors 100, 100A to 100G, 100H1, or 100H2, as shown in Embodiment 1, can be applied to all transistors in each of the pixel circuits 51C and 51D.

[0497] The pixel circuit 51E shown in Figure 30A has a configuration in which the back gate of transistor 52B is connected to the other side of the source or drain, and an additional transistor 52D is added, compared to the pixel circuit 51D shown in Figure 29D. The pixel circuit 51E shown in Figure 30A is a 4Tr1C type pixel circuit having transistors 52A, 52B, 52C, 52D, and capacitor 53.

[0498] One of the sources or drains of transistor 52D is connected to node ND, and the other source or drain is connected to wiring V0. Transistor 52D also has a back gate, which is connected to the gate of transistor 52D.

[0499] Wirings GL1, GL2, and GL3 are connected to the pixel circuit 51E. Wiring GL1 is connected to the gate of transistor 52A, wiring GL2 is connected to the gate of transistor 52C, and wiring GL3 is connected to the gate of transistor 52D. In this embodiment, wirings GL1, GL2, and GL3 are sometimes collectively referred to as wiring GL. Therefore, there may be more than one wiring GL.

[0500] By simultaneously making transistors 52C and 52D conduct, the source and gate of transistor 52B become at the same potential, making transistor 52B non-conducting. This allows the current flowing to the light-emitting element 61 to be forcibly interrupted. Such a pixel circuit is suitable when using a display method that alternates between display periods and off periods.

[0501] The pixel circuit 51F shown in Figure 30B is an example of the pixel circuit 51E shown in Figure 30A with the addition of a capacitor 53A. The capacitor 53A functions as a retaining capacitor. The pixel circuit 51E shown in Figure 30A is a 4Tr1C type pixel circuit. The pixel circuit 51F shown in Figure 30B is a 4Tr2C type pixel circuit.

[0502] The pixel circuit 51G shown in Figure 30C is a 6Tr1C type pixel circuit having transistors 52A, 52B, 52C, 52D, 52E, 52F, and a capacitor 53. Transistors 52A to 52F each have a back gate. Of these, transistors 52A, 52C, 52D, 52E, and 52F have their respective back gates connected to their respective gates, while transistor 52B has a configuration in which its back gate is connected to the other side of either the source or the drain.

[0503] One source or drain of transistor 52A is connected to wiring SL, and the gate of transistor 52A is connected to wiring GL2. One source or drain of transistor 52D is connected to wiring ANO, and the gate of transistor 52D is connected to wiring GL1. The other source or drain of transistor 52D is connected to one source or drain of transistor 52B. The other source or drain of transistor 52B is connected to the other source or drain of transistor 52A, and to one source or drain of transistor 52F. The gate of transistor 52F is connected to wiring GL3.

[0504] One source or drain of transistor 52E is connected to the other source or drain of transistor 52D, and one source or drain of transistor 52B. The other source or drain of transistor 52E is connected to the gate of transistor 52B and one terminal of capacitor 53. The other terminal of capacitor 53 is connected to the other source or drain of transistor 52F, the anode of light-emitting element 61, and one source or drain of transistor 52C. The gates of transistor 52E and transistor 52C are connected to wiring GL4. The other source or drain of transistor 52C is connected to wiring V0. The region to which the other source or drain of transistor 52E, the gate of transistor 52B, and one terminal of capacitor 53 are connected functions as node ND.

[0505] For example, transistors 100, 100A to 100G, 100H1, or 100H2, as shown in Embodiment 1, can be applied to all transistors in each of the pixel circuits 51E, 51F, and 51G.

[0506] By using a transistor 100 or the like according to one aspect of the present invention in the pixel circuit of a display device, the occupied area of ​​the pixel circuit can be reduced. Therefore, the resolution of the display device can be increased. For example, a display device can be realized with a resolution of 1,000 ppi or more and 10,000 ppi or less, preferably 2,000 ppi or more and 9,000 ppi or less, more preferably 3,000 ppi or more and 8,000 ppi or less, even more preferably 4,000 ppi or more and 8,000 ppi or less, even more preferably 5,000 ppi or more and 8,000 ppi or less, and even more preferably 6,000 ppi or more and 8,000 ppi or less.

[0507] Furthermore, by reducing the area occupied by the pixel circuit, the number of pixels in the display device can be increased (higher resolution). For example, it becomes possible to realize display devices with extremely high resolutions such as HD (1280 x 720 pixels), FHD (1920 x 1080 pixels), WQHD (2560 x 1440 pixels), WQXGA (2560 x 1600 pixels), 4K2K (3840 x 2160 pixels), or 8K4K (7680 x 4320 pixels).

[0508] Therefore, by using a transistor 100 or the like according to one aspect of the present invention in the pixel circuit of a display device, the display quality of the display device can be improved. Furthermore, in a bottom-emission type display device using an EL element, the aperture ratio of the pixels can be increased. Pixels with a high aperture ratio can emit light with the same brightness as pixels with a low aperture ratio, but with a lower current density. Therefore, the reliability of the display device can be improved.

[0509] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments.

[0510] (Embodiment 5) In this embodiment, a display device according to one aspect of the present invention will be described with reference to Figures 31 to 36.

[0511] The display device of this embodiment can be a high-resolution display device or a large-screen display device. Therefore, the display device of this embodiment can be used in electronic devices with relatively large screens, such as television equipment, desktop or notebook computers, computer monitors, digital signage, and large game machines such as pachinko machines, as well as in the display units of digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, personal information terminals, and audio playback devices.

[0512] The display device of this embodiment can be a high-definition display device. Therefore, the display device of this embodiment can be used, for example, as a display unit for information terminals (wearable devices) such as wristwatches and bracelets, as well as as a display unit for wearable devices that can be worn on the head, such as VR devices such as head-mounted displays (HMDs) and AR devices such as glasses.

[0513] A semiconductor device according to one aspect of the present invention can be used as a display device or a module having said display device. Examples of modules having said display devices include a module to which a connector such as a Flexible Printed Circuit (FPC) or TCP (Tape Carrier Package) is attached, and a module on which an Integrated Circuit (IC) is mounted using the COG (Chip On Glass) method or COF (Chip On Film) method.

[0514] The display device of this embodiment can also function as a touch panel. For example, various detection elements (also called sensor elements) capable of detecting the proximity or contact of an object to be detected, such as a finger, can be applied to the display device.

[0515] Examples of sensor types include capacitive, resistive, surface acoustic wave, infrared, optical, and pressure-sensitive sensors.

[0516] Examples of capacitance methods include surface capacitance and projected capacitance. Furthermore, projected capacitance methods include self-capacitance and mutual capacitance. Mutual capacitance is preferable because it enables simultaneous multi-point detection.

[0517] Examples of touch panels include out-cell, on-cell, and in-cell types. An in-cell touch panel refers to a configuration in which electrodes constituting the sensing element are provided on one or both of the substrate supporting the display element and the opposing substrate.

[0518] <Display device 50A> Figure 31 shows a perspective view of the display device 50A.

[0519] The display device 50A has a configuration in which substrate 152 and substrate 151 are bonded together. In Figure 31, substrate 152 is shown with a dashed line.

[0520] The display device 50A includes a display unit 162, a connection unit 140, a circuit unit 164, a conductive layer 165, etc. Figure 31 shows an example in which the IC 173 and FPC 172 are mounted on the display device 50A. Therefore, the configuration shown in Figure 31 can also be described as a display module having the display device 50A, an IC, and an FPC.

[0521] The connection portion 140 is provided on the outside of the display unit 162. The connection portion 140 can be provided along one or more sides of the display unit 162. There may be one or more connection portions 140. Figure 31 shows an example in which the connection portion 140 is provided so as to surround all four sides of the display unit 162. The common electrode of the display element and the conductive layer are connected at the connection portion 140, and a potential can be supplied to the common electrode.

[0522] The circuit section 164 may include, for example, a scan line drive circuit. Alternatively, the circuit section 164 may include both a scan line drive circuit and a signal line drive circuit.

[0523] The conductive layer 165 has the function of supplying signals and power to the display unit 162 and the circuit unit 164. These signals and power are input to the conductive layer 165 from an external source via the FPC 172, or from the IC 173.

[0524] Figure 31 shows an example in which IC 173 is provided on the substrate 151 using the COG method or COF method, etc. For example, IC 173 can be an IC having one or both of a scan line drive circuit and a signal line drive circuit. Note that the display device 50A and the display module can also be configured without an IC. Furthermore, the IC can be mounted on the FPC using the COF method, etc.

[0525] A semiconductor device according to one aspect of the present invention can be applied, for example, to one or both of the display unit 162 and the circuit unit 164 of a display device 50A. Oxide semiconductors (OS) can preferably be used in the channel formation region of the transistors in the display device. By using OS transistors, a display device with low power consumption can be made. Furthermore, the semiconductor device according to one aspect of the present invention can be used in both the display unit 162 and the circuit unit 164, that is, all of the transistors in the display device can be OS transistors. By making all of the transistors in the display device OS transistors in this way, the manufacturing cost can be kept low.

[0526] For example, when a semiconductor device according to one aspect of the present invention is applied to the pixel circuit of a display device, the occupied area of ​​the pixel circuit can be reduced, resulting in a high-definition display device. Also, for example, when a semiconductor device according to one aspect of the present invention is applied to the drive circuit of a display device (for example, one or both of a gate line drive circuit and a source line drive circuit), the occupied area of ​​the drive circuit can be reduced, resulting in a narrow-bezel display device. Furthermore, because the semiconductor device according to one aspect of the present invention has good electrical characteristics, its use in a display device can improve the reliability of the display device.

[0527] The display unit 162 is the area in the display device 50A that displays images, and has a plurality of pixels 201 arranged periodically. Figure 31 shows an enlarged view of one pixel 201.

[0528] There are no particular limitations on the pixel arrangement in the display device of this embodiment, and various arrangements can be applied. Examples of pixel arrangements include stripe arrangements, S-stripe arrangements, matrix arrangements, delta arrangements, Bayer arrangements, and pentile arrangements.

[0529] The pixel 201 shown in Figure 31 has a sub-pixel 11R that emits red light, a sub-pixel 11G that emits green light, and a sub-pixel 11B that emits blue light. The number of sub-pixels that a single pixel has is not particularly limited.

[0530] Each sub-pixel 11R, sub-pixel 11G, and sub-pixel 11B includes a display element and a circuit that controls the driving of the display element.

[0531] Various elements can be used as display elements, such as liquid crystal elements and light-emitting elements. In addition, display elements using shutter-type or optical interference-type MEMS (Micro Electro Mechanical Systems), microcapsule-type, electrophoretic-type, electrowetting-type, or electronic powder fluid (registered trademark)-type methods can also be used. Furthermore, QLEDs using a light source and color conversion technology with quantum dot materials can also be used.

[0532] Examples of display devices using liquid crystal elements include transmissive liquid crystal display devices, reflective liquid crystal display devices, and semi-transmissive liquid crystal display devices.

[0533] Modes that can be used in display devices using liquid crystal elements include, for example, Vertical Alignment (VA) mode, FFS (Fringe Field Switching) mode, IPS (In-Plane-Switching) mode, TN (Twisted Nematic) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optically Compensated Birefringence) mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (AntiFerroelectric Liquid Crystal) mode, and ECB (Electrically Examples of VA modes include Controlled Birefringence mode and guest host mode. Examples of VA modes include MVA (Multi-Domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment) mode, and ASV (Advanced Super View) mode.

[0534] Examples of liquid crystal materials that can be used in liquid crystal elements include thermotropic liquid crystals, low molecular weight liquid crystals, polymer liquid crystals, polymer dispersed liquid crystals (PDLC), polymer network liquid crystals (PNLC), ferroelectric liquid crystals, and antiferroelectric liquid crystals. Depending on the conditions, these liquid crystal materials exhibit cholesteric phases, smectic phases, cubic phases, chiral nematic phases, isotropic phases, blue phases, etc. Furthermore, either positive-type or negative-type liquid crystals can be used as the liquid crystal material, and can be selected according to the applied mode or design.

[0535] Examples of light-emitting elements include self-emissive light-emitting elements such as LEDs, OLEDs, and semiconductor lasers. Examples of LEDs that can be used include mini-LEDs and micro-LEDs.

[0536] Examples of light-emitting materials for light-emitting devices include fluorescent materials, phosphorescent materials, thermally activated delayed fluorescence (TADF) materials, and inorganic compounds (such as quantum dot materials).

[0537] The light-emitting element can emit light in the following colors: infrared, red, green, blue, cyan, magenta, yellow, or white. Furthermore, the color purity can be improved by adding a microcavity structure to the light-emitting element.

[0538] Of the pair of electrodes in a light-emitting element, one electrode functions as the anode and the other electrode functions as the cathode.

[0539] Furthermore, a display device according to one aspect of the present invention may be any of the following: a top-emission type that emits light in the direction opposite to the substrate on which the light-emitting element is formed; a bottom-emission type that emits light toward the substrate on which the light-emitting element is formed; or a dual-emission type that emits light on both sides.

[0540] Figure 32A shows an example of a cross-section obtained by cutting a portion of the display device 50A, including the FPC 172, a portion of the circuit section 164, a portion of the display section 162, a portion of the connection section 140, and a portion of the end section.

[0541] The display device 50A shown in Figure 32A has transistors 205D, 205R, 205G, 205B, light-emitting elements 130R, 130G, and 130B between substrates 151 and 152. Light-emitting element 130R is a display element of a sub-pixel 11R that emits red light, light-emitting element 130G is a display element of a sub-pixel 11G that emits green light, and light-emitting element 130B is a display element of a sub-pixel 11B that emits blue light.

[0542] The display device 50A employs an SBS structure. Because the SBS structure allows for the optimization of materials and configurations for each light-emitting element, it increases the freedom of material and configuration selection, making it easier to improve brightness and reliability.

[0543] The display device 50A is a top-emission type. In the top-emission type, transistors and the like can be arranged overlapping with the light-emitting region of the light-emitting element, which allows for a higher aperture ratio of pixels compared to the bottom-emission type.

[0544] Transistors 205D, 205R, 205G, and 205B are all formed on the substrate 151. These transistors can be manufactured using the same process. Note that transistors with different structures can also be used for each of transistors 205D, 205R, 205G, and 205B.

[0545] In this embodiment, an example is shown in which OS transistors are used for transistors 205D, 205R, 205G, and 205B. Transistors according to one aspect of the present invention can be used for transistors 205D, 205R, 205G, and 205B. In other words, the display device 50A has transistors according to one aspect of the present invention in both the display unit 162 and the circuit unit 164. By using transistors according to one aspect of the present invention in the display unit 162, the pixel size can be reduced, and high resolution can be achieved. Furthermore, by using transistors according to one aspect of the present invention in the circuit unit 164, the occupied area of ​​the circuit unit 164 can be reduced, and a narrow bezel can be achieved. For details on transistors according to one aspect of the present invention, refer to the description of the previous embodiment.

[0546] Specifically, transistors 205D, 205R, 205G, and 205B each have a conductive layer 104 functioning as a first gate, an insulating layer 106 functioning as a first gate insulating layer, conductive layers 112a and 112b functioning as source and drain, a semiconductor layer 108 having a metal oxide, a conductive layer 103 functioning as a second gate, and an insulating layer 119 functioning as a second gate insulating layer. Here, the same hatching pattern is applied to multiple layers obtained by processing the same conductive film.

[0547] Note that the transistors 205D, 205R, 205G, and 205B shown are examples in which the transistor 100E (Figures 11A to 11C) described in the previous embodiment is applied. In the display device 50A, insulating layer 110a1, conductive layer 103, and insulating layer 110b (insulating layer 110b1, insulating layer 110b2, and insulating layer 110b3) are located between conductive layer 112a and conductive layer 112b. Insulating layer 106 is located between conductive layer 104 and semiconductor layer 108. Insulating layer 119 is located between conductive layer 103 and semiconductor layer 108.

[0548] Furthermore, the transistors in the display device of this embodiment are not limited to those of one aspect of the present invention. For example, the transistors of one aspect of the present invention may be combined with transistors of other structures.

[0549] The display device of this embodiment may have, for example, one or more of the following: planar transistors, staggered transistors, or inverse staggered transistors. The transistors in the display device of this embodiment may be either top-gate or bottom-gate types.

[0550] The display device of this embodiment may also have Si transistors.

[0551] To increase the luminescence brightness of a light-emitting element included in a pixel circuit, it is necessary to increase the amount of current flowing through the light-emitting element. To achieve this, it is necessary to increase the source-drain voltage of the drive transistor included in the pixel circuit. Compared to Si transistors, OS transi...

Claims

It comprises a transistor, a first insulating layer, a second insulating layer, and a third insulating layer. The transistor has a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a semiconductor layer, a fourth insulating layer, and a fifth insulating layer. The first insulating layer is located on the first conductive layer such that it has a region that overlaps with the first conductive layer. The second conductive layer is located on the first insulating layer, The second insulating layer is located on the second conductive layer, The third conductive layer is located on the second insulating layer, The third insulating layer is located on the first conductive layer, the first insulating layer, the second conductive layer, the second insulating layer, and the third conductive layer, and is in contact with the upper and side surfaces of the first conductive layer, the side surfaces of the first insulating layer, the side surfaces of the second conductive layer, the side surfaces of the second insulating layer, and the upper and side surfaces of the third conductive layer. The third insulating layer has a first opening that overlaps with the first conductive layer and the third conductive layer, The fourth insulating layer is in contact with the side surface of the first insulating layer, the side surface of the second conductive layer, and the side surface of the second insulating layer within the first opening. The semiconductor layer is located on the first conductive layer, the fourth insulating layer, and the third conductive layer so as to be contained within the first opening, and is in contact with the upper surface of the first conductive layer, the upper surface of the fourth insulating layer, and the upper surface of the third conductive layer, The fifth insulating layer is located on the semiconductor layer, The fourth conductive layer is located on the fifth insulating layer such that it has a region that overlaps with the semiconductor layer. Semiconductor equipment. 　 In claim 1, The semiconductor layer is an oxide semiconductor layer containing indium. The second insulating layer comprises a sixth insulating layer, a seventh insulating layer on the sixth insulating layer, and an eighth insulating layer on the seventh insulating layer. The first insulating layer, the sixth insulating layer, and the eighth insulating layer each contain silicon and nitrogen, The seventh insulating layer comprises silicon and oxygen, The third insulating layer is one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, zinc gallium oxide, aluminum nitride, silicon nitride, and silicon nitride oxide. Semiconductor equipment. 　 In claim 2, The first insulating layer comprises a ninth insulating layer, a tenth insulating layer on the ninth insulating layer, and an eleventh insulating layer on the tenth insulating layer. The ninth insulating layer and the eleventh insulating layer each contain silicon and nitrogen, The tenth insulating layer comprises silicon and oxygen. Semiconductor equipment. 　 In claim 3, The fourth insulating layer is in contact with the upper surface of the ninth insulating layer. Semiconductor equipment. 　 In claim 1 or claim 2, A twelfth insulating layer is located beneath the first conductive layer. The upper surface of the 12th insulating layer is in contact with the first conductive layer. The 12th insulating layer is one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, gallium zinc oxide, aluminum nitride, silicon nitride, and silicon nitride oxide. Semiconductor equipment. 　 In claim 1 or claim 2, The first insulating layer, the second conductive layer, the second insulating layer, and the third conductive layer are provided in an island-like manner. The first insulating layer, the second conductive layer, the second insulating layer, and the third conductive layer have their respective edges coincide or approximately coincide in a plan view. Semiconductor equipment. 　 In claim 1 or claim 2, The second conductive layer is divided by a slit that reaches the first conductive layer. The material has a region on a pair of opposing sides across the slit in which the fourth insulating layer, the semiconductor layer, the fifth insulating layer, and the fourth conductive layer are stacked in this order. Semiconductor equipment. 　 In claim 1 or claim 2, The first insulating layer, the second conductive layer, the second insulating layer, and the third conductive layer each have a second opening that reaches the first conductive layer. Within the second opening, the fourth insulating layer, the semiconductor layer, the fifth insulating layer, and the fourth conductive layer are stacked in this order against the side surface of the first insulating layer, the side surface of the second conductive layer, and the side surface of the second insulating layer, in a region. Semiconductor equipment. 　 In claim 1 or claim 2, The first opening and the semiconductor layer each have regions that overlap with the first corners of the first insulating layer, the second conductive layer, the second insulating layer, and the third conductive layer in a plan view, The first corner is a corner whose interior angle in a plan view is greater than 0 degrees and less than 180 degrees. Semiconductor equipment. 　 In claim 1 or claim 2, The first opening and the semiconductor layer each have, in a plan view, regions that overlap with the first insulating layer, the second conductive layer, the second insulating layer, and the second corner of the third conductive layer. The second corner is a corner whose interior angle in a plan view is greater than 180 degrees and less than 360 degrees. Semiconductor equipment. 　 In claim 1 or claim 2, The fourth insulating layer comprises a thirteenth insulating layer and a fourteenth insulating layer on the thirteenth insulating layer. The 13th insulating layer comprises silicon and nitrogen, The 14th insulating layer comprises silicon and oxygen. Semiconductor equipment. 　 A first conductive layer is formed, A first insulating film, a first conductive film, a second insulating film, and a second conductive film are deposited on the first conductive layer in this order. The first insulating film, the first conductive film, the second insulating film, and the second conductive film are processed to have a region that overlaps with the first conductive layer, thereby forming a first insulating layer, a second conductive layer, a second insulating layer, and a third conductive layer, respectively. A third insulating film is formed in contact with the upper and side surfaces of the first conductive layer, the side surfaces of the first insulating layer, the side surfaces of the second conductive layer, the side surfaces of the second insulating layer, and the upper and side surfaces of the third conductive layer. A portion of the third insulating film is removed to form an opening that overlaps with the first conductive layer and the third conductive layer, respectively, and a third insulating layer having the opening is formed from the third insulating film. A fourth insulating film is formed in contact with the upper surface of the third insulating layer, the upper surface of the first conductive layer, the side surface of the first insulating layer, the side surface of the second conductive layer, the side surface of the second insulating layer, and the upper surface and side surface of the third conductive layer. A portion of the fourth insulating film is removed to form a fourth insulating layer that is in contact with the side surface of the first insulating layer, the side surface of the second conductive layer, and the side surface of the second insulating layer. A metal oxide film is formed in contact with the side and top surfaces of the third insulating layer, the top surface of the first conductive layer, the top surface of the fourth insulating layer, and the top surface of the third conductive layer, The metal oxide film is processed to form a semiconductor layer so as to be contained within the opening in a plan view. A fifth insulating layer is formed on the semiconductor layer. A fourth conductive layer is formed on the fifth insulating layer such that it has a region that overlaps with the semiconductor layer. Method for manufacturing semiconductor devices. 　 In claim 12, Anisotropic etching is used to remove a portion of the fourth insulating film. Method for manufacturing semiconductor devices.

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