Semiconductor device and display device

Abstract

Provided is a semiconductor device comprising a transistor having a large ON-state current. The semiconductor device comprises a first transistor, a metal oxide layer, and a first insulating layer. The first transistor has a first semiconductor layer, a second insulating layer, and a first conductive layer. The first semiconductor layer has a first region overlapping the first conductive layer with the second insulating layer interposed therebetween, and a second region and a third region sandwiching the first region. The metal oxide layer is located on the first insulating layer. The second region has a region in contact with the upper surface and a side surface of the metal oxide layer. Each of the first region and the third region has a region in contact with the upper surface of the first insulating layer. The first semiconductor layer has a first metal oxide. The metal oxide layer has a second metal oxide. The first metal oxide and the second metal oxide each include indium. The indium content in the first metal oxide is higher than the indium content in the second metal oxide.

Description

Semiconductor device and display device

[0001] One aspect of the present invention relates to a display device and a method for manufacturing the same. Another aspect of the present invention relates to a transistor and a method for manufacturing the same. Another aspect of the present invention relates to a display device having a transistor.

[0002] It should be noted that one aspect of the present invention is not limited to the above-mentioned technical field. Examples of technical fields of one aspect of the present invention include semiconductor devices, display devices, light-emitting devices, energy storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), methods for driving them, or methods for manufacturing them.

[0003] In this specification, a semiconductor device refers to a device that utilizes semiconductor properties, including circuits containing semiconductor elements (transistors, diodes, photodiodes, etc.), devices having such circuits, etc. It also refers to any device that can function by utilizing semiconductor properties. For example, integrated circuits, chips equipped with integrated circuits, and electronic components with chips housed in packages are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, and electronic devices are themselves semiconductor devices, and may each have a semiconductor device.

[0004] In recent years, there has been a growing demand for high-definition display devices. Devices requiring high-definition display capabilities include those for virtual reality (VR), augmented reality (AR), substitute reality (SR), and mixed reality (MR), all of which are being actively developed.

[0005] Examples of display devices include display devices having liquid crystal elements and display devices having light-emitting elements (also called light-emitting devices). Examples of light-emitting elements include organic EL (Electroluminescence) elements and light-emitting diodes (LEDs). Patent document 1 discloses a high-definition display device using organic EL elements.

[0006] Technology related to transistors using semiconductor thin films is attracting attention. These transistors are widely applied in electronic devices such as integrated circuits (ICs) and display devices. While silicon-based semiconductor materials are widely known as semiconductor materials applicable to transistors, oxide semiconductors are also attracting attention as other materials.

[0007] Examples of oxide semiconductors applicable to transistors include indium oxide and indium gallium zinc oxide. Non-patent documents 1 and 2 disclose thin-film transistors using indium oxide.

[0008] International Publication No. 2016 / 038508

[0009] Dhananjay & Chu, C. W. Realization of In▲2▼O▲3▼ thin film transistors through reactive evaporation process. Appl. Phys. Lett. 91, 1-4 (2007). Y. Magari et al. Takashi Koida, “High-mobility hydrogenerated polycrystalline In2O3 (In2O3:H) thin-film transistors”, Nature Communications, 13, 1078 (2022) Takashi Koida, “High-mobility transparent conductive film”, National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Generation Research Results Presentation Meeting 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf>

[0010] One aspect of the present invention aims to provide a semiconductor device or display device having a transistor with high field-effect mobility. Alternatively, it aims to provide a semiconductor device or display device having a transistor with high on-current. Alternatively, it aims to provide a semiconductor device or display device having a transistor of a very small size. Alternatively, it aims to provide a semiconductor device or display device having a transistor with a short channel length. Alternatively, it aims to provide a semiconductor device or display device having a transistor with good electrical characteristics. Alternatively, it aims to provide a semiconductor device or display device that operates at high speed. Alternatively, it aims to provide a semiconductor device with a small footprint. Alternatively, it aims to provide a semiconductor device or display device with low wiring resistance. Alternatively, it aims to provide a semiconductor device or display device with low power consumption. Alternatively, it aims to provide a highly reliable transistor, semiconductor device, or display device. Alternatively, it aims to provide a display device with high display quality. Alternatively, it aims to provide a high-definition display device. Alternatively, it aims to provide a method for manufacturing the aforementioned transistor, semiconductor device, or display device. Alternatively, it aims to provide a method for manufacturing a highly productive transistor, semiconductor device, or display device. Alternatively, one of the objectives is to provide novel transistors, semiconductor devices, display devices, or methods for manufacturing these.

[0011] Furthermore, the description of these problems does not preclude the existence of other problems. One aspect of the present invention does not necessarily have to solve all of these problems. It is possible to extract other problems from the description in the specification, drawings, and claims.

[0012] One aspect of the present invention is a semiconductor device having a first transistor, a metal oxide layer, and a first insulating layer. The first transistor has a first semiconductor layer, a second insulating layer, and a first conductive layer. The first semiconductor layer has a first region that overlaps with the first conductive layer via the second insulating layer, and a second region and a third region that sandwich the first region. The metal oxide layer is located on the first insulating layer. The second region has regions that are in contact with the upper surface and side surface of the metal oxide layer. The first region and the third region each have regions that are in contact with the upper surface of the first insulating layer. The first semiconductor layer has a first metal oxide. The metal oxide layer has a second metal oxide. The first metal oxide and the second metal oxide each contain indium. The indium content in the first metal oxide is higher than the indium content in the second metal oxide.

[0013] In the semiconductor device described above, the first metal oxide is preferably indium oxide. The second region preferably has first crystal grains. The crystal orientation of the first crystal grains with respect to the upper surface of the first insulating layer is preferably <111>. The second metal oxide preferably contains gallium and tin, or both, and zinc. The metal oxide layer preferably has second crystal grains. The c-axis of the second crystal grain is preferably perpendicular or approximately perpendicular to the upper surface of the first insulating layer.

[0014] In the aforementioned semiconductor device, the crystal structure of the second crystal grain is preferably hexagonal or trigonal.

[0015] In the aforementioned semiconductor device, it is preferable to have a second transistor. The second transistor preferably has a second semiconductor layer, a second insulating layer, and a second conductive layer. The second semiconductor layer preferably has a fourth region that overlaps with the second conductive layer via the second insulating layer, and a fifth region and a sixth region that sandwich the fourth region. The second semiconductor layer preferably has a region that is in contact with the upper surface of the first insulating layer. The second semiconductor layer preferably has a second metal oxide.

[0016] In the aforementioned semiconductor device, it is preferable that the thickness of the second semiconductor layer is greater than the thickness of the first semiconductor layer.

[0017] In the aforementioned semiconductor device, it is preferable that the thickness of the region in the metal oxide layer that is in contact with the first semiconductor layer is greater than the thickness of the second semiconductor layer.

[0018] In the aforementioned semiconductor device, it is preferable that the second, third, fifth, and sixth regions each contain a first element. The first element is preferably one or more of hydrogen, boron, and phosphorus. The concentrations of the first element in the second and third regions are preferably higher than the concentration of the first element in the first region. The concentrations of the first element in the fifth and sixth regions are preferably higher than the concentration of the first element in the fourth region.

[0019] In the semiconductor device described above, the metal oxide layer preferably has a seventh region that overlaps with the first semiconductor layer and an eighth region that does not overlap with the first semiconductor layer. The eighth region preferably contains the first element. The concentration of the first element in the eighth region is preferably higher than the concentration of the first element in the seventh region.

[0020] One aspect of the present invention is a display device having a display element and a pixel circuit. The pixel circuit has a first transistor, a second transistor, a metal oxide layer, and a first insulating layer. The first transistor has a first semiconductor layer, a second insulating layer, and a first conductive layer. The first semiconductor layer has a first region that overlaps with the first conductive layer via the second insulating layer, and a second region and a third region that sandwich the first region. The second transistor has a second semiconductor layer, a second insulating layer, and a second conductive layer. The second semiconductor layer has a region that overlaps with the second conductive layer via the second insulating layer. The metal oxide layer and the second semiconductor layer are each located on the first insulating layer. The second region has regions that are in contact with the top surface and side surface of the metal oxide layer. The first region and the third region each have regions that are in contact with the top surface of the first insulating layer. The first semiconductor layer contains a first metal oxide. The metal oxide layer and the second semiconductor layer each contain a second metal oxide. The first metal oxide and the second metal oxide each contain indium. The indium content in the first metal oxide is higher than the indium content in the second metal oxide.

[0021] In the aforementioned display device, the first metal oxide is preferably indium oxide. The second region preferably has first crystal grains. The crystal orientation of the first crystal grains with respect to the upper surface of the first insulating layer is preferably <111>. The second metal oxide preferably contains gallium and tin, or both, and zinc. The metal oxide layer preferably has second crystal grains. The c-axis of the second crystal grain is preferably perpendicular or approximately perpendicular to the upper surface of the first insulating layer.

[0022] In the aforementioned display device, the crystal structure of the second crystal grain is preferably hexagonal or trigonal.

[0023] In the aforementioned display device, it is preferable that the thickness of the second semiconductor layer is greater than the thickness of the first semiconductor layer.

[0024] In the aforementioned display device, it is preferable that the thickness of the region in the metal oxide layer that is in contact with the first semiconductor layer is greater than the thickness of the second semiconductor layer.

[0025] One aspect of the present invention can provide a semiconductor device or display device having a transistor with high field-effect mobility. Alternatively, it can provide a semiconductor device or display device having a transistor with high on-current. Alternatively, it can provide a semiconductor device or display device having a transistor of a very small size. Alternatively, it can provide a semiconductor device or display device having a transistor with a short channel length. Alternatively, it can provide a semiconductor device or display device having a transistor with good electrical characteristics. Alternatively, it can provide a semiconductor device or display device that operates at high speed. Alternatively, it can provide a semiconductor device with a small footprint. Alternatively, it can provide a semiconductor device or display device with low wiring resistance. Alternatively, it can provide a semiconductor device or display device with low power consumption. Alternatively, it can provide a highly reliable transistor, semiconductor device, or display device. Alternatively, it can provide a display device with high display quality. Alternatively, it can provide a high-definition display device. Alternatively, it can provide a method for manufacturing the aforementioned transistor, semiconductor device, or display device. Alternatively, it can provide a highly productive method for manufacturing a transistor, semiconductor device, or display device. Alternatively, it can provide a novel transistor, semiconductor device, display device, or method for manufacturing them.

[0026] Furthermore, the description of these effects does not preclude the existence of other effects. One aspect of the present invention does not necessarily have to possess all of these effects. Other effects can be extracted from the description, drawings, and claims.

[0027] Figure 1A is a top view showing an example of a semiconductor device. Figures 1B and 1C are cross-sectional views showing an example of a semiconductor device. Figures 2A, 2B, and 2C are cross-sectional views showing an example of a semiconductor device. Figures 3A, 3B, 3C, 3D, and 3E are diagrams illustrating the crystal structure of a metal oxide. Figure 4A is a top view showing an example of a semiconductor device. Figure 4B is a cross-sectional view showing an example of a semiconductor device. Figures 5A, 5B, and 5C are cross-sectional views showing an example of a semiconductor device. Figures 6A, 6B, and 6C are cross-sectional views showing an example of a semiconductor device. Figures 7A and 7B are cross-sectional views showing an example of a semiconductor device. Figures 8A, 8B, 8C, and 8D are cross-sectional views showing an example of a semiconductor device. Figure 9A is a top view showing an example of a semiconductor device. Figures 9B and 9C are cross-sectional views showing an example of a semiconductor device. Figure 10A is a top view showing an example of a semiconductor device. Figure 10B is a cross-sectional view showing an example of a semiconductor device. Figure 11 is a top view showing an example of a semiconductor device. Figures 12A, 12B, 12C, 12D, 12E, and 12F are cross-sectional views showing an example of a semiconductor device fabrication method. Figures 13A, 13B, 13C, 13D, and 13E are cross-sectional views showing an example of a semiconductor device fabrication method. Figures 14A, 14B, 14C, 14D, and 14E are cross-sectional views showing an example of a semiconductor device fabrication method. Figures 15A and 15B are diagrams illustrating the carrier concentration dependence of Hall mobility. Figure 15C is a cross-sectional view illustrating an indium oxide film. Figure 16A is a perspective view showing an example of a display device. Figure 16B is a block diagram showing an example of a display device. Figures 17A, 17B, 17C, 17D, and 17E are circuit diagrams of pixel circuits. Figures 18A and 18B are circuit diagrams of pixel circuits. Figures 19A and 19B are cross-sectional views showing an example of a display device. Figure 20 is a cross-sectional view showing an example of a display device. Figures 21A, 21B, and 21C are cross-sectional views showing an example of a display device. Figures 22A and 22B are cross-sectional views showing an example of a display device. Figure 23 is a cross-sectional view showing an example of a display device. Figures 24A, 24B, 24C, and 24D are diagrams showing an example of an electronic device. Figures 25A, 25B, 25C, 25D, 25E, and 25F are diagrams showing an example of an electronic device.Figures 26A, 26B, 26C, 26D, 26E, 26F, and 26G show examples of electronic devices.

[0028] Embodiments will be described in detail with reference to the drawings. However, it will be readily apparent to those skilled in the art that the present invention is not limited to the following description, and that its form and details can be modified in various ways without departing from the spirit and scope of the present invention. Accordingly, the present invention shall not be construed as being limited to the descriptions of the embodiments shown below.

[0029] In the configuration of the invention described below, the same reference numerals are used in common across different drawings for parts that are identical or have similar functions, and repeated explanations are omitted. In addition, when referring to similar functions, the hatching patterns are the same, and reference numerals may not be assigned.

[0030] The position, size, and scope of each component shown in the drawings may not represent the actual position, size, and scope for the sake of ease of understanding. Therefore, the disclosed invention is not necessarily limited to the position, size, and scope disclosed in the drawings.

[0031] In this specification, ordinal numbers such as "first," "second," etc., are used to avoid confusion of components and do not limit the number of components or the order of components (e.g., process order or stacking order). Furthermore, even if a term does not have an ordinal number in this specification, an ordinal number may be added in the claims to avoid confusion of components. Even if a term has an ordinal number in this specification, a different ordinal number may be added in the claims. Even if a term has an ordinal number in this specification, an ordinal number may be omitted in the claims.

[0032] In this specification and drawings, when the same reference numeral is used for multiple elements, and especially when it is necessary to distinguish them, the reference numeral may be accompanied by an identifying numeral such as "_1", "[n]", or "[m,n]". Furthermore, when describing a common matter for multiple elements with identifying numerals, or when it is not necessary to distinguish them, the identifying numeral may be omitted.

[0033] The words "film" and "layer" can be interchanged depending on the context or situation. For example, the term "conductive layer" can be changed to "conductive film." Or, for example, the term "insulating film" can be changed to "insulating layer."

[0034] A transistor is a type of semiconductor device that can perform functions such as amplifying current or voltage, and switching operations that control conduction or non-conductivity. Transistors as used herein include IGFETs (Insulated Gate Field Effect Transistors) and thin-film transistors (TFTs).

[0035] The functions of "source" and "drain" may be reversed when transistors with different polarities are used, or when the direction of current changes during circuit operation. For this reason, in this specification, the terms "source" and "drain" may be used interchangeably. Furthermore, the names of the source and drain of a transistor can be appropriately rephrased as source terminal and drain terminal, or source electrode and drain electrode, depending on the situation.

[0036] The terms "gate" and "back gate" are interchangeable. Therefore, in this specification, the terms "gate" and "back gate" may be used interchangeably. Furthermore, the names of the gate and back gate of a transistor can be appropriately rephrased as gate electrode and back gate electrode, etc., depending on the context.

[0037] In this specification, "connection" includes, for example, "electrical connection." The term "electrical connection" is sometimes used to define the connection relationship of circuit elements as a physical object. Furthermore, "electrical connection" includes both "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the use of circuit elements (e.g., transistors, switches, etc.; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected through one or more circuit elements. A and B refer to objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0038] For example, assuming a circuit including A and B is in operation, if there is a timing during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then it can be defined that "A and B are indirectly connected" as physical objects. Furthermore, even if there is a timing during the circuit's operation when no electrical signals are exchanged or potential interactions occur between A and B, if there is a timing during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then it can be defined that "A and B are indirectly connected."

[0039] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where "A and B are not indirectly connected" is when an insulator is interposed in the path from A to B. Specifically, this includes cases where a capacitive element is connected between A and B, or where a transistor gate insulating film is interposed between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of a transistor are indirectly connected."

[0040] Another example of a situation where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via source and drain in the path from A to B, and a constant potential V is supplied to the nodes between the transistors from a power supply, GND, etc.

[0041] In this specification, unless otherwise specified, on-current refers to the drain current (also called the conduction state) when the transistor is in the on state. Unless otherwise specified, the on state refers to the state in an n-channel transistor where the voltage between the gate and source (gate voltage, also called Vg or Vgs) is equal to or greater than the threshold voltage (also called Vth), and in a p-channel transistor where it is less than or equal to the threshold voltage.

[0042] In this specification, unless otherwise specified, off-current refers to the source-drain leakage current when the transistor is in the off state (also called the non-conductive state or cutoff state). Unless otherwise specified, the off state refers to the state in an n-channel transistor where the voltage between the gate and source is lower than the threshold voltage, and in a p-channel transistor where it is higher than the threshold voltage.

[0043] In this specification, "parallel" means a state in which two lines are positioned at an angle of -10 degrees or more and 10 degrees or less. Therefore, the case of -5 degrees or more and 5 degrees or less is also included. Furthermore, "approximately parallel" means a state in which two lines are positioned at an angle of -30 degrees or more and 30 degrees or less. Furthermore, "perpendicular" means a state in which two lines are positioned at an angle of 80 degrees or more and 100 degrees or less. Therefore, the case of 85 degrees or more and 95 degrees or less is also included. Furthermore, "approximately perpendicular" means a state in which two lines are positioned at an angle of 60 degrees or more and 120 degrees or less.

[0044] In this specification, the top surface shape of a component refers to the contour shape of the component when viewed from above (also called a plan view). Furthermore, a top view refers to viewing from the direction normal to the surface on which the component is formed, or to the surface of the support (e.g., substrate) on which the component is formed.

[0045] In this specification, "matching or roughly matching top shapes" means that at least a portion of the contours overlap between stacked layers. For example, this includes cases where the upper and lower layers are processed with the same mask pattern, or partially with the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or the upper layer may be located outside the lower layer; in this case, it may also be said that the "matching or roughly matching top shapes" apply. Furthermore, when the top shapes match or roughly match, it can also be said that the "edges match or roughly match," or "the edges are aligned or roughly aligned."

[0046] In this specification, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined with respect to the substrate surface or the surface to be formed. The angle formed between the inclined side surface and the substrate surface or the surface to be formed may be called the taper angle.

[0047] In this specification, "step breakage" refers to the phenomenon in which a layer, film, or electrode is divided due to the shape of the surface on which it is formed (e.g., a step).

[0048] In this specification, "island-like" refers to a state in which two or more layers made of the same material and formed in the same process are physically separated. For example, an island-like metal oxide layer refers to a state in which the metal oxide layer and adjacent metal oxide layers are physically separated.

[0049] In this specification, devices fabricated using a metal mask or FMM (Fine Metal Mask, high-resolution metal mask) may be referred to as MM (metal mask) structured devices. Furthermore, in this specification, devices fabricated without using a metal mask or FMM may be referred to as MML (metal maskless) structured devices.

[0050] In this specification, holes or electrons may be referred to as "carriers." For example, in a light-emitting element, a hole injection layer or electron injection layer may be called a "carrier injection layer," a hole transport layer or electron transport layer may be called a "carrier transport layer," and a hole blocking layer or electron blocking layer may be called a "carrier blocking layer." Note that the above-mentioned carrier injection layer, carrier transport layer, and carrier blocking layer may not always be clearly distinguishable. Furthermore, a single layer may combine the functions of two or three of the carrier injection layer, carrier transport layer, and carrier blocking layer.

[0051] In this specification, a light-emitting element has an EL layer between a pair of electrodes (a first electrode and a second electrode). The light-emitting element includes a first electrode, an EL layer on the first electrode, and a second electrode on the EL layer. The EL layer has at least a light-emitting layer. Here, examples of layers (also called functional layers) that the EL layer has include a light-emitting layer, a carrier injection layer (hole injection layer and electron injection layer), a carrier transport layer (hole transport layer and electron transport layer), and a carrier block layer (hole block layer and electron block layer). In this specification, a photodetector (also called a photodetector device) has at least an active layer that functions as a photoelectric conversion layer between a pair of electrodes. In this specification, one of the first electrode and the second electrode may be referred to as a pixel electrode, and the other as a common electrode.

[0052] In this specification, flexibility refers to the property of an object being flexible and able to bend. It is the property of an object being able to deform in response to an external force applied to it, regardless of whether it is elastic or able to return to its original shape.

[0053] For example, flexible electronic devices, flexible display devices (also called flexible displays, etc.), flexible batteries (also called flexible batteries, etc.), and flexible substrates (also called flexible substrates, etc.) can each be deformed in response to external forces. Flexible electronic devices, flexible display devices, flexible batteries, and flexible substrates can each be used fixed in a deformed state, used after repeated deformation, or used in an undeformed state. The phrase "deforms in response to external forces" above means that it can be deformed by the average adult's hand without requiring excessive force. Flexibleness can be evaluated using testing machines capable of stress-strain measurement (tensile testing machines, compression testing machines, etc.). In stress-strain measurement, the flexibility of an object can be quantified by applying an external force to the object and measuring the strain of the object caused by the resulting stress.

[0054] In this specification, when an object is described as having flexibility, it means that at least a part of the object is flexible. In other words, a flexible object may have parts that are not flexible.

[0055] In this specification, when two objects are deformed by the same external force, the object that deforms more is said to be the object with higher flexibility. Also, when a first part and a second part of an object are deformed by the same external force, the part that deforms more is said to be the part with higher flexibility.

[0056] (Embodiment 1) This embodiment describes a display device and a semiconductor device according to one aspect of the present invention. The semiconductor device according to one aspect of the present invention can be suitably used, for example, in one or both of the pixel circuit and the drive circuit of a display device.

[0057] One aspect of the present invention is a semiconductor device having a first transistor, a metal oxide layer, and a first insulating layer.

[0058] The first transistor includes a first semiconductor layer, a second insulating layer, and a first conductive layer. In the first transistor, the second insulating layer functions as a gate insulating layer, and the first conductive layer functions as a gate electrode. The first semiconductor layer includes a first region that overlaps with the first conductive layer via the second insulating layer, and a second region and a third region that sandwich the first region. In the first transistor, the first region functions as a channel forming region, and the second and third regions function as a source region and a drain region.

[0059] The metal oxide layer is located on the first insulating layer. The second region has areas in contact with the top and side surfaces of the metal oxide layer. The first region and the third region each have areas in contact with the top surface of the first insulating layer.

[0060] The first semiconductor layer has a first metal oxide. The metal oxide layer has a second metal oxide. Preferably, the first metal oxide and the second metal oxide each contain indium. Furthermore, it is preferable that the indium content in the first metal oxide is higher than the indium content in the second metal oxide.

[0061] By using a metal oxide with a high indium content in the first semiconductor layer, the field-effect mobility of the first transistor can be increased. Furthermore, the on-current of the first transistor can be increased. The first metal oxide is particularly preferably indium oxide. The second region preferably has first crystal grains. The crystal orientation of the first crystal grains relative to the upper surface of the first insulating layer is preferably <111>.

[0062] The metal oxide layer functions as a seed crystal in the formation of the first semiconductor layer, thereby enhancing the crystallinity of the first semiconductor layer. In this specification, the layer that functions as a seed crystal may be referred to as the seed crystal layer. The crystallinity of the seed crystal layer is preferably high. The seed crystal layer preferably has a second crystal grain. When cubic indium oxide is used for the first semiconductor layer, the crystal structure of the seed crystal layer is preferably hexagonal or trigonal, for example. The second metal oxide preferably contains gallium and tin, or both, and zinc. The c-axis of the second crystal grain is preferably perpendicular or approximately perpendicular to the upper surface of the first insulating layer. The first crystal grain has a crystal structure that reflects the crystal structure of the second crystal grain.

[0063] A metal oxide layer, which will become the first semiconductor layer, is formed in contact with a seed crystal layer. At the stage when the metal oxide layer that will become the first semiconductor layer is formed, it is preferable that the crystallinity of the metal oxide layer is low. By performing a heat treatment after the formation of the metal oxide layer that will become the first semiconductor layer, the metal oxide layer crystallizes and the first semiconductor layer can be formed. This makes it possible to increase the grain size of the crystal grains contained in the first semiconductor layer. Furthermore, the field-effect mobility of the first transistor can be further increased.

[0064] Preferably, the semiconductor device further includes a second transistor. The second transistor includes a second semiconductor layer, a second insulating layer, and a second conductive layer. In the second transistor, the second insulating layer functions as a gate insulating layer, and the second conductive layer functions as a gate electrode.

[0065] The second semiconductor layer has a region in contact with the upper surface of the first insulating layer. Preferably, the second semiconductor layer has a second metal oxide. In other words, the second semiconductor layer can be made of the same material as the seed crystal layer. The second semiconductor layer and the seed crystal layer can be formed by processing the same metal oxide film.

[0066] The indium content in the second metal oxide is preferably lower than the indium content in the first metal oxide. By using a metal oxide with a low indium content in the second semiconductor layer, the field-effect mobility of the second transistor can be reduced. This reduces the on-current of the second transistor and improves saturation.

[0067] In this specification, the term "high saturation" may be used to describe a transistor where the change in current in the saturation region of the Id-Vd characteristic is small.

[0068] A first transistor with high field-effect mobility and large on-current, and a second transistor with high saturation, can be formed on the same substrate by sharing some of the manufacturing processes. For example, by applying the first transistor to a transistor requiring a large on-current and the second transistor to a transistor requiring high saturation, a high-performance semiconductor device can be created.

[0069] In the following sections, more specific examples will be explained using Figures 1A to 14E.

[0070] <Configuration Example 1> Figure 1A shows a top view (also called a plan view) of a semiconductor device 10, which is one embodiment of the present invention. Figure 1B shows a cross-sectional view of the cross-section along the dashed-dotted line A1-A2 shown in Figure 1A, and Figure 1C shows cross-sectional views of the cross-sections along the dashed-dotted lines B1-B2 and B3-B4. Note that in Figure 1A, some of the components of the semiconductor device 10 (such as the gate insulating layer) are omitted. In the top view of the semiconductor device, as in Figure 1A, some of the components are omitted in the following drawings as well.

[0071] The semiconductor device 10 includes a transistor 100, a transistor 200, and a metal oxide layer 70. The semiconductor device 10 is provided on an insulating surface. An enlarged view of the transistor 100 shown in Figure 1A is shown in Figure 2A, and an enlarged view of the transistor 200 is shown in Figure 2B.

[0072] The transistor 100 includes a semiconductor layer 108, an insulating layer 106 on the semiconductor layer 108, and a conductive layer 104 on the insulating layer 106. The conductive layer 104 has a region that overlaps with the semiconductor layer 108 via the insulating layer 106. In the transistor 100, the conductive layer 104 functions as a gate electrode, and the insulating layer 106 functions as a gate insulating layer.

[0073] In the semiconductor layer 108, the region that overlaps with the conductive layer 104 via the insulating layer 106 functions as the channel formation region of the transistor 100. The semiconductor layer 108 also has a pair of regions (region 108P and region 108Q) that sandwich the channel formation region. Regions 108P and 108Q are regions that do not overlap with the conductive layer 104. In the transistor 100, region 108P functions as one of the source region and drain region, and region 108Q functions as the other of the source region and drain region.

[0074] The transistor 200 includes a semiconductor layer 208, an insulating layer 106 on the semiconductor layer 208, and a conductive layer 204 on the insulating layer 106. The conductive layer 204 has a region that overlaps with the semiconductor layer 208 via the insulating layer 106. In the transistor 200, the conductive layer 204 functions as a gate electrode, and the insulating layer 106 functions as a gate insulating layer.

[0075] In the semiconductor layer 208, the region that overlaps with the conductive layer 204 via the insulating layer 106 functions as the channel formation region of the transistor 200. The semiconductor layer 208 also has a pair of regions (region 208P and region 208Q) that sandwich the channel formation region. Regions 208P and 208Q are regions that do not overlap with the conductive layer 204. In the transistor 200, region 208P functions as one of the source region and drain region, and region 208Q functions as the other of the source region and drain region.

[0076] An insulating layer 105 is provided on the substrate 102, and a metal oxide layer 70 and a semiconductor layer 208 are provided on the insulating layer 105. A semiconductor layer 108 is provided on the insulating layer 105 and the metal oxide layer 70. An insulating layer 106 is provided on the semiconductor layer 108 and the semiconductor layer 208, and a conductive layer 104 and a conductive layer 204 are provided on the insulating layer 106.

[0077] The semiconductor material used for semiconductor layer 108 and semiconductor layer 208 is not particularly limited. For example, a semiconductor made of a single element or a compound semiconductor can be used. Examples of semiconductors made of single elements include silicon and germanium. Examples of compound semiconductors include gallium arsenide and silicon germanium. Other examples of compound semiconductors include organic semiconductors, nitride semiconductors, and oxide semiconductors (OS). These semiconductor materials may contain impurities as dopants.

[0078] The crystallinity of the semiconductor material is not particularly limited, and any amorphous semiconductor, single-crystal semiconductor, or semiconductor having crystalline properties other than single crystal (microcrystalline semiconductor, polycrystalline semiconductor, or semiconductor having a crystalline region in part) can be used. Using a single-crystal semiconductor or a semiconductor having crystalline properties is preferable because it can suppress the degradation of transistor characteristics.

[0079] For example, silicon can be used for one or both of the semiconductor layer 108 and the semiconductor layer 208. Examples of silicon include single-crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. An example of polycrystalline silicon is low-temperature polysilicon (LTPS). Transistors using amorphous silicon for the channel formation region can be fabricated at low cost on a large glass substrate. Transistors using polycrystalline silicon for the channel formation region have high field-effect mobility and can operate at high speeds. Transistors using microcrystalline silicon for the channel formation region have higher field-effect mobility than transistors using amorphous silicon and can operate at high speeds. Note that transistors using silicon for the channel formation region are sometimes referred to as Si transistors, and transistors using LTPS for the channel formation region are sometimes referred to as LTPS transistors.

[0080] It is preferable to use a metal oxide (also called an oxide semiconductor) exhibiting semiconductor properties in one or both of the semiconductor layer 108 and the semiconductor layer 208. Transistors using oxide semiconductors (hereinafter also referred to as OS transistors) have extremely high field-effect mobility compared to transistors using amorphous silicon. Furthermore, OS transistors have a remarkably low off-current and can retain the charge stored in a capacitor connected in series with the transistor for a long period of time. In addition, by applying OS transistors, the power consumption of semiconductor devices can be reduced. When a metal oxide is used in the semiconductor layer, the semiconductor layer can be called a metal oxide layer or a metal oxide film.

[0081] It is particularly preferable to use metal oxides for both semiconductor layer 108 and semiconductor layer 208. Furthermore, all transistors in the semiconductor device can be OS transistors. This allows for a semiconductor device with low power consumption.

[0082] The same material can be used for semiconductor layer 108 and semiconductor layer 208. This allows semiconductor layer 108 and semiconductor layer 208 to be formed in the same process, thus enabling the use of the same equipment for forming semiconductor layer 108 and semiconductor layer 208. Therefore, the manufacturing cost of semiconductor devices can be reduced.

[0083] Alternatively, different materials can be used for semiconductor layer 108 and semiconductor layer 208. This broadens the range of materials that can be used for semiconductor layer 108 and semiconductor layer 208. Semiconductor layer 108 and semiconductor layer 208 can be formed using different processes.

[0084] In this specification, "different materials" means materials in which some or all of the constituent elements are different, or materials in which the constituent elements are the same but the composition is different.

[0085] The electrical characteristics and reliability of a transistor differ depending on the material used in the semiconductor layer. It is preferable to use different materials for semiconductor layer 108 and semiconductor layer 208, depending on the required electrical characteristics and reliability of transistors 100 and 200. This makes it possible to create a semiconductor device that achieves both high performance and high reliability.

[0086] A metal oxide can be used for one of the semiconductor layers 108 and 208, and silicon can be used for the other. For example, indium oxide can be used for one of the semiconductor layers 108 and 208, and LTPS can be used for the other. This makes it possible to create a semiconductor device that has both a low off-current and high field-effect mobility OS transistor and a high field-effect mobility LTPS transistor, achieving both high performance and low power consumption.

[0087] The electrical characteristics and reliability of a transistor differ depending on the composition of the metal oxide applied to the semiconductor layer. When metal oxides are used in both semiconductor layer 108 and semiconductor layer 208, it is preferable to use different metal oxide compositions for semiconductor layer 108 and semiconductor layer 208, depending on the electrical characteristics and reliability required for transistors 100 and 200. This makes it possible to create a semiconductor device that achieves both high performance and high reliability.

[0088] The metal oxide preferably contains at least indium. For example, indium oxide can be suitably used as the metal oxide. Alternatively, for example, gallium oxide or zinc oxide can be used as the metal oxide. Alternatively, the metal oxide preferably contains one or both of indium and zinc. Alternatively, the metal oxide preferably has one or more elements selected from indium, element M, and zinc. Element M is a metallic or metalloid element with a high bond energy with oxygen, for example, a metallic or metalloid element with a higher bond energy with oxygen than indium. Specific examples of element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M present in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from gallium, aluminum, tin, and yttrium, and even more preferably one or more of gallium, aluminum, and tin. These elements are more preferred because they have high bonding energy with oxygen and their ionic radii are similar to those of indium or zinc. Furthermore, tin is more preferred because its tetravalent state can increase carrier mobility. In this specification, metallic elements and metalloid elements are sometimes collectively referred to as "metallic elements," and the "metallic elements" described in this specification may include metalloid elements.

[0089] Examples of metal oxides include indium zinc oxide (In-Zn oxide, also known as IZO®), indium tin oxide (In-Sn oxide, also known as ITO), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium tungsten oxide (In-W oxide, also known as IWO), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also known as IGTO), gallium zinc oxide (Ga-Zn oxide, also known as GZO), and aluminum zinc oxide (Al-Zn oxide). Other suitable materials include indium aluminum zinc oxide (In-Al-Zn oxide, also known as IAZO), indium tin zinc oxide (In-Sn-Zn oxide, also known as ITZO®), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also known as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also known as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also known as IGAZO, IGZAO, or IAGZO). Alternatively, silicon-containing indium tin oxide (In-Sn-Si oxide, also known as ITSO), gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), etc., can be used.

[0090] Furthermore, the metal oxide can be composed of one or more metal elements with high periodic numbers in the periodic table, either in place of indium or in addition to indium. The greater the overlap of the metal element orbitals, the greater the carrier conduction in the metal oxide tends to be. Therefore, by including metal elements with high periodic numbers, the field-effect mobility of the transistor can be increased. Examples of metal elements with high periodic numbers include those belonging to the 5th period and those belonging to the 6th period. Specifically, these metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0091] Metal oxides may contain one or more nonmetallic elements. The presence of nonmetallic elements in metal oxides can increase carrier concentration or reduce the band gap, potentially improving the field-effect mobility of transistors. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0092] By increasing the ratio of indium atoms to the sum of all metal element atoms in the metal oxide, the field-effect mobility of the transistor can be increased. Furthermore, this allows for a transistor with a high on-current, resulting in a transistor that operates at high speed.

[0093] In this specification, the ratio of the number of indium atoms to the sum of the total number of atoms of all contained metal elements may be referred to as the indium content. The same applies to other metal elements. If element M contains multiple elements, the sum of the ratios of the number of atoms of element M to the sum of the total number of atoms of all contained metal elements may be referred to as the element M content.

[0094] By increasing the zinc content in a metal oxide, a highly crystalline metal oxide is obtained, which suppresses the diffusion of impurities within the metal oxide. Therefore, fluctuations in the electrical characteristics of the transistor are suppressed, and its reliability can be improved.

[0095] By increasing the content of element M in the metal oxide, a metal oxide with a large band gap can be produced. This allows for the formation of oxygen vacancies (V) in the metal oxide. Ｏ The formation of oxygen deficiency (V) is suppressed. Ｏ Carrier generation caused by ) is suppressed. Therefore, the shift in the transistor's threshold voltage is suppressed, and the drain current (hereinafter also referred to as the cutoff current) that flows when the gate voltage (Vg) is 0V can be reduced, making it possible to create a normally-off transistor. In addition, it is possible to create a transistor with a small off current. Furthermore, fluctuations in the transistor's electrical characteristics are suppressed, and reliability can be improved.

[0096] By using a metal oxide with a large band gap in the semiconductor layer, oxygen vacancies (V) can be created in the semiconductor layer by light. Ｏ The formation of ) is suppressed, and the threshold voltage of the transistor is prevented from shifting. Therefore, a transistor with high reliability against light can be made. A metal oxide having element M can be suitably used in the semiconductor layer of a transistor provided in a region where light can be incident (for example, the display part of a display device).

[0097] It is preferable that the composition of the metal oxide used in semiconductor layer 108 is different from the composition of the metal oxide used in semiconductor layer 208.

[0098] The indium content in semiconductor layer 108 is preferably higher than the indium content in semiconductor layer 208. By using a metal oxide with a high indium content in semiconductor layer 108, a transistor 100 with a large on-current can be made. Furthermore, transistor 100 can be suitably used in transistors where high-speed operation is required.

[0099] The semiconductor layer 108 preferably contains indium and oxygen. For example, indium oxide can be suitably used for the semiconductor layer 108.

[0100] Transistors using metal oxides with a high indium content in the semiconductor layer have high field-effect mobility, allowing for a large on-current even with a small channel width. Therefore, the area occupied by the transistor can be reduced, and thus the area occupied by the semiconductor device 10 can be reduced.

[0101] The indium content in semiconductor layer 208 is preferably lower than the indium content in semiconductor layer 108. This allows the field-effect mobility of transistor 200 to be lower compared to transistor 100. This reduces the on-current, thereby increasing the saturation of transistor 200. Transistor 200 can be suitably used in transistors where high saturation is required. Furthermore, since a small on-current can be achieved even with a short channel length, transistor 200 can be suitably used in transistors where a small current is required. In addition, the occupied area of ​​transistor 200 can be reduced, thereby reducing the occupied area of ​​semiconductor device 10.

[0102] The semiconductor layer 208 preferably contains indium, one or both of element M and zinc, and oxygen.

[0103] The semiconductor layer 208 preferably contains indium, element M, and oxygen. The content of element M in the semiconductor layer 208 is preferably higher than the content of element M in the semiconductor layer 108. This ensures that the semiconductor layer 208 has oxygen vacancies (V Ｏ The formation of oxygen deficiency (V) is suppressed. Ｏ Carrier generation caused by ) is suppressed. Therefore, a highly reliable transistor 200 can be made, and a highly reliable semiconductor device can be made. For example, the semiconductor layer 208 preferably contains indium, gallium, and oxygen. Typically, indium gallium oxide (In-Ga oxide) can be suitably used for the semiconductor layer 208.

[0104] The semiconductor layer 208 preferably contains indium, zinc, and oxygen. The zinc content in the semiconductor layer 208 is preferably higher than the zinc content in the semiconductor layer 108. This allows for higher crystallinity of the semiconductor layer 208. Therefore, a highly reliable transistor 200 and a highly reliable semiconductor device can be produced. Typically, indium zinc oxide (In-Zn oxide) can be suitably used for the semiconductor layer 208.

[0105] The semiconductor layer 208 preferably contains indium, element M, zinc, and oxygen. For example, the semiconductor layer 208 preferably contains indium, tin, zinc, and oxygen. Alternatively, the semiconductor layer 208 preferably contains indium, gallium, zinc, and oxygen. Typically, indium tin zinc oxide (In-Sn-Zn oxide) or indium gallium zinc oxide (In-Ga-Zn oxide) can be suitably used for the semiconductor layer 208.

[0106] It is preferable that the indium content in the semiconductor layer 208 is also high. It is preferable that the indium content in the semiconductor layer 208 is higher than the content of element M (e.g., gallium and tin) in the semiconductor layer 208. Furthermore, it is preferable that the indium content in the semiconductor layer 208 is higher than the zinc content in the semiconductor layer 208. This makes it possible to create a transistor 200 that achieves both a large on-current and high reliability. Therefore, it is possible to create a semiconductor device that achieves both high performance and high reliability. In addition, by using a metal oxide with a high indium content, the occupied area of ​​the transistor 200 can be reduced, and thus the occupied area of ​​the semiconductor device 10 can be reduced.

[0107] It is preferable that semiconductor layer 108 and semiconductor layer 208 each have crystalline properties. Examples of crystalline metal oxide structures include single crystal, polycrystalline, CAAC (c-axis aligned crystal) structure, microcrystalline structure, and nanocrystalline (nc: nano-crystal) structure. By using a crystalline metal oxide, the defect level density in the semiconductor layer can be reduced, and a highly reliable semiconductor device can be realized.

[0108] When a metal oxide contains indium and zinc, it may have a CAAC structure. The CAAC structure has fewer grain boundaries in the a-b plane than a polycrystalline structure.

[0109] It is preferable that the semiconductor layer 108 and semiconductor layer 208 have high crystallinity. For example, it is preferable that semiconductor layer 108 is polycrystalline or monocrystalline. It is preferable to use a polycrystalline indium oxide film as semiconductor layer 108, and more preferable to use a monocrystalline indium oxide film.

[0110] The crystallinity of semiconductor layer 108 and semiconductor layer 208 can be analyzed, for example, by X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED). Alternatively, a combination of these methods can be used for analysis.

[0111] Single-crystal films are particularly preferred because they do not have grain boundaries, thus suppressing carrier scattering at grain boundaries and enabling transistors with high field-effect mobility. Compared to microcrystalline and amorphous films, polycrystalline films can reduce carrier scattering and enable transistors with high field-effect mobility. When a polycrystalline film is used for semiconductor layer 108, it is preferable that the grain size of the crystal grains contained in semiconductor layer 108 is large. By using a polycrystalline film with large grain size, the number of crystal grain boundaries located in the channel formation region can be reduced, and the length of the crystal grain boundaries located in the channel formation region can be shortened, thus enabling transistors with high field-effect mobility. Furthermore, it is preferable that there are few crystal grain boundaries in the channel formation region that intersect with the direction of drain current flow (also known as the channel length direction). Note that even with a polycrystalline film, if there are no crystal grain boundaries located in the channel formation region, the same effects as a single-crystal film can be achieved.

[0112] When a polycrystalline indium oxide film is used as the semiconductor layer, the grain size of the crystal grains contained in the semiconductor layer is preferably 0.1 μm or larger, more preferably 0.2 μm or larger, more preferably 0.3 μm or larger, more preferably 0.4 μm or larger, more preferably 0.5 μm or larger, more preferably 0.6 μm or larger, and more preferably 0.7 μm or larger. Since a larger grain size is preferable, there is no particular upper limit on the grain size. Note that the grain size of the crystal grains is not limited to the above range.

[0113] The grain size of crystal grains contained in a semiconductor layer can be analyzed, for example, by transmission electron microscopy (TEM), scanning transmission electron microscopy (STEM), or electron backscatter diffraction (EBSD). Alternatively, a combination of these methods can be used for analysis. EBSD is sometimes referred to as EBSP (Electron Backscatter Pattern). For example, the average grain size of multiple crystal grains can be used as the grain size. Alternatively, the grain size of a crystal grain can be defined as, for example, the diameter of a circle with the same area as the crystal grain. This diameter is sometimes called the equivalent diameter of a circle.

[0114] In this specification, a grain boundary refers to, for example, the boundary between adjacent grains with different crystal orientations. Therefore, in this specification, boundaries between adjacent grains with the same crystal orientation are not included in grain boundaries. For example, even if a boundary is observed between two grains in a TEM image, if the crystal orientations of those two grains are the same or approximately the same, the boundary may not be called a grain boundary. Also, in EBSD, if the difference in crystal orientation between adjacent measurement points is small (for example, if the difference in crystal orientation is less than 5 degrees), these measurement points can be considered to belong to the same grain.

[0115] In this specification, space groups are denoted using the international notation (or Hermann-Mauguin notation) Short notation. In addition, space group numbers from the International Tables for Crystallography Volume A (hereinafter also referred to as ITA) may be included. Furthermore, Miller indices are used to indicate crystal planes and crystal directions. In crystallography, space groups, crystal planes, and crystal directions are indicated by a bar above the number, but in this specification, due to formatting constraints, a minus sign (-) may be placed before the number instead of a bar above it. In addition, individual orientations indicating directions within a crystal are indicated by [ ], collective orientations indicating all equivalent directions are indicated by < >, individual planes indicating crystal planes are indicated by ( ), and collective planes with equivalent symmetry are indicated by {}. Note that even with the same space group number, the notation for the space group may differ depending on how the crystal axis is defined.

[0116] For example, in the cubic system, ２ O ３ The crystal structure belongs to space group Ia-3 (space group number 206).

[0117] In this specification, the cubic crystal structure is sometimes referred to as cubic crystal or cubic structure. The same applies to other crystal systems (hexagonal, trigonal, tetragonal, orthorhombic, monoclinic, and triclinic).

[0118] The grain size of the crystal grains can also be confirmed, for example, using an optical microscope or a scanning electron microscope (SEM). Furthermore, by creating irregularities on the surface of the semiconductor layer 108 using etchants with different etching rates depending on the crystal plane or crystallinity, the crystal grains can be more easily observed with an optical microscope or a scanning electron microscope (SEM). When an indium oxide film is used as the semiconductor layer 108, the crystal grains of indium oxide can be more easily observed by using an etchant containing an acid. For example, one or more of phosphoric acid, oxalic acid, nitric acid, and hydrochloric acid can be used as the acid. However, if the etching rate is too fast, a part of the semiconductor layer 108 may disappear, making it difficult to observe the crystal grains. Therefore, it is preferable to adjust the etching rate by controlling the concentration, temperature, and processing time of the etchant so that the semiconductor layer 108 does not disappear but its thickness is reduced (also called half-etching). By performing half-etching, it becomes possible to easily observe the crystal grains.

[0119] Furthermore, if the semiconductor layer is thin, it may not be possible to evaluate its crystallinity and grain size.

[0120] The metal oxide layer 70 is provided between the insulating layer 105 and the semiconductor layer 108. The metal oxide layer 70 has regions that are in contact with the lower surface of the semiconductor layer 108 and the upper surface of the insulating layer 105. The semiconductor layer 108 has regions that are in contact with the upper and side surfaces of the metal oxide layer 70 and the upper surface of the insulating layer 105.

[0121] The metal oxide layer 70 preferably has crystallinity. The metal oxide layer 70 preferably has crystal grains. In the formation of the semiconductor layer 108, the metal oxide layer 70 functions as a seed crystal that enhances the crystallinity of the semiconductor layer 108. It is preferable that the metal oxide layer 70 has high crystallinity. High crystallinity of the seed crystal layer is preferable because it can promote the crystallization of the semiconductor layer 108.

[0122] When using cubic indium oxide for the semiconductor layer 108, the crystal structure of the seed crystal layer (in this case, the metal oxide layer 70) is preferably, for example, cubic, hexagonal, or trigonal. By having crystals in the metal oxide layer 70 whose crystal orientation with respect to the surface or the surface to be formed is <001>, a semiconductor layer 108 having crystals with a crystal orientation of <111> can be formed. When the crystal orientation of the crystals in the metal oxide layer 70 with respect to the surface or the surface to be formed is <001>, the c-axis of the crystal is perpendicular or approximately perpendicular to the surface or the surface to be formed. Note that hexagonal or trigonal crystals can sometimes be rephrased as layered crystals, so the above structure can be understood as a structure in which a semiconductor layer 108 having cubic crystals is formed on a metal oxide layer 70 having layered crystals. In other words, it can be considered as a layered structure fabricated using heteroepitaxial growth technology, or a technology similar to heteroepitaxial growth. The crystal structure of the seed crystal layer is not particularly limited.

[0123] In this specification, the crystal orientation of a crystal refers to its orientation relative to the surface of the substrate. Therefore, for example, a crystal with a crystal orientation of <100> can be said to be a crystal in which the (100) plane is parallel to the surface of the substrate. However, it is not limited to the above, and the crystal orientation of a crystal can also be said to be its orientation relative to the surface of the insulating layer 105, or the surface on which the insulating layer 105 is formed.

[0124] The metal oxide layer 70 can be, for example, zinc oxide, In-Ga oxide, gallium zinc oxide (Ga-Zn oxide), aluminum zinc oxide (Al-Zn oxide), In-Al-Zn oxide, In-Ga-Zn oxide, or In-Sn-Zn oxide.

[0125] When a metal oxide having a CAAC structure is used for the metal oxide layer 70, the c-axis of the crystal (also called the seed crystal) in the metal oxide layer 70 is perpendicular or approximately perpendicular to the surface or the surface on which it is formed. In other words, by using a metal oxide that easily has a CAAC structure for the metal oxide layer 70, the controllability of the crystal orientation of the seed crystal can be improved.

[0126] Metal oxides containing indium and zinc tend to have a CAAC structure. The metal oxide layer 70 can preferably use In-Ga-Zn oxide. In this case, the metal oxide layer 70 contains indium, gallium, zinc, and oxygen. Typically, the metal oxide layer 70 can use metal oxides with compositions of In:Ga:Zn = 1:1:1 [atomic ratio], In:Ga:Zn = 4:2:3 [atomic ratio], In:Ga:Zn = 1:3:2 [atomic ratio], In:Ga:Zn = 1:3:4 [atomic ratio], In:Ga:Zn = 1:3:6 [atomic ratio], or near these compositions. Alternatively, the metal oxide layer 70 can preferably use In-Sn-Zn oxide. In this case, the metal oxide layer 70 contains indium, tin, zinc, and oxygen. Typically, the metal oxide layer 70 can be made of a metal oxide with a composition of In:Sn:Zn = 40:1:10 [atomic ratio], In:Sn:Zn = 20:1:10 [atomic ratio], or a composition close to these. Metal oxides with these compositions are suitable for use as the metal oxide layer 70 because they readily form a layered structure. In this specification, "composition close to" includes a range of ±30% of the desired atomic ratio.

[0127] Here, the crystal structures of metal oxides are shown in Figures 3A to 3E. Figure 3A is a view of the crystal structure of In-Ga-Zn oxide with a composition of In:Ga:Zn = 1:1:1 [atomic ratio], viewed from a direction perpendicular to the c-axis. Figure 3B is a view of the plane indicated by the dashed line in Figure 3A, viewed from the c-axis direction. Figure 3C is a view of the plane indicated by the dashed line in Figure 3A, viewed from the c-axis direction. Figure 3D is a view of the plane indicated by the double-dotted line in Figure 3A, viewed from the c-axis direction. In Figures 3A, 3C, and 3D, Mx represents a Ga atom or a Zn atom. Note that in Figure 3A, the plane indicated by the dashed line, the plane indicated by the dashed line, and the plane indicated by the double-dotted line are sometimes collectively called the c-plane. Figure 3E is a view of the crystal structure of indium oxide, viewed from a direction perpendicular to the (111) plane.

[0128] The intermetallic atomic distance on the c-plane (the arrow shown in each of FIGS. 3B to 3D) is said to be 0.330 nm. Also, the In-In distance on the (111) plane (the arrow shown in FIG. 3E) is said to be 0.334 nm and 0.385 nm. That is, it can be seen that the arrangement of metal atoms is similar between the c-plane of the CAAC structure and the (111) plane of indium oxide. Therefore, as the metal oxide layer 70, a metal oxide that is likely to have a CAAC structure can be preferably used.

[0129] When a metal oxide having a CAAC structure is used for the metal oxide layer 70, a semiconductor layer 108 having a crystal with a crystal orientation of <111> can be formed. A cross-sectional view of the metal oxide layer 70, the semiconductor layer 108, and the vicinity thereof is shown in FIG. 2C. In FIG. 2C, the <111> orientation of the crystal included in the semiconductor layer 108 is indicated by a solid-line arrow. As shown in FIG. 2C, the <111> orientation of the crystal included in the semiconductor layer 108 is likely to be perpendicular or substantially perpendicular to the surface to be formed of the metal oxide layer 70 (here, the upper surface of the insulating layer 105) at any position above the metal oxide layer 70, near the side surface of the metal oxide layer 70, and at a position away from the metal oxide layer 70.

[0130] When the layer that becomes the semiconductor layer 108 crystallizes, first, the region in contact with the seed crystal layer of the layer (here, the metal oxide layer 70) crystallizes, and then crystal growth proceeds toward the region not in contact with the seed crystal layer. In FIG. 2C, the direction in which crystal growth proceeds is indicated by a white arrow.

[0131] It is preferable to use a material having a crystal structure with a small difference in lattice constant (also referred to as lattice mismatch) from the crystal structure of the material constituting the semiconductor layer 108 for the seed crystal layer. Thereby, when a layer that becomes the semiconductor layer 108 is formed on the seed crystal layer, epitaxial growth is likely to occur in the layer, and crystallization becomes easier.

[0132] As one method for evaluating the degree of lattice mismatch, there is a method using the value of lattice mismatch shown below. The lattice mismatch degree Δa [%] of the crystal of the film to be formed with respect to the crystal of the forming film is Δa = ((L １ −L ２ ) / L ２ ) × 100. Here, L１ L is the length of the unit cell vector of the crystals in the formed film, or the lattice constant. ２ This is the length of the unit cell vector of the crystal in the formed film, or the lattice constant.

[0133] The lattice mismatch Δa between the seed crystal layer and the semiconductor layer 108 is preferably small in absolute value, and most preferably zero. For example, the lattice mismatch Δa can be -5% or more and 5% or less, preferably -4% or more and 4% or less, more preferably -3% or more and 3% or less, and even more preferably -2% or more and 2% or less. Note that the lattice mismatch Δa is not limited to the above range.

[0134] A cubic metal oxide can also be used for the metal oxide layer 70. By having the metal oxide layer 70 have the same crystal structure as the semiconductor layer 108, the metal oxide layer 70 can be used as a seed crystal for epitaxial growth in the formation of the semiconductor layer 108, thereby improving the crystallinity of the semiconductor layer 108.

[0135] Furthermore, when the metal oxide layer 70 has a laminated structure, it is preferable to use a material that functions as a seed crystal in at least the layer in contact with the semiconductor layer 108.

[0136] The conductivity of the metal oxide layer 70 is not particularly limited and can be, for example, an insulating layer, a semiconductor layer, or a conductive layer. Furthermore, the metal oxide layer 70 can have different electrical resistances. For example, the electrical resistance of the region of the metal oxide layer 70 in contact with the semiconductor layer 108 can be different from the electrical resistance of the region not in contact with the semiconductor layer 108.

[0137] As mentioned above, the semiconductor layer 208 can be made of a metal oxide. Furthermore, the metal oxide layer 70 can be formed using the same material and process as the semiconductor layer 208. By forming the metal oxide layer 70 and the semiconductor layer 208 using the same process, the process can be simplified and manufacturing costs can be kept low. However, even when the same material as the semiconductor layer 208 is used for the metal oxide layer 70, the conductivity of the metal oxide layer 70 may differ from that of the semiconductor layer 208.

[0138] For example, a first metal oxide film is formed on an insulating layer 105, and the first metal oxide film is processed to form island-shaped metal oxide layers 70 and a semiconductor layer 208. A second metal oxide film is formed on the insulating layer 105 and the metal oxide layer 70, and the second metal oxide film is processed to form island-shaped first metal oxide layers that will become the semiconductor layer 108. Then, by performing a heat treatment, the first metal oxide layer can be crystallized to form the semiconductor layer 108.

[0139] During the heat treatment, crystal nuclei originating from the seed crystal layer, the metal oxide layer 70, are generated in the first metal oxide layer. Further growth of these crystal nuclei causes the first metal oxide layer to crystallize. This increases the grain size of the crystal grains contained in the semiconductor layer 108 and reduces the number of grain boundaries. Therefore, a transistor with high field-effect mobility can be achieved. Furthermore, a transistor with high on-current can be achieved.

[0140] By performing a heat treatment after forming the first metal oxide layer in contact with the metal oxide layer 70, the formation of crystal nuclei not originating from the seed crystal layer (hereinafter also referred to as native nuclei) is suppressed, and the number of crystal grains in the semiconductor layer 108 that originate from native nuclei can be reduced. This reduces the number of crystal grain boundaries contained in the semiconductor layer 108. It is also possible to have a configuration in which the semiconductor layer 108 contains crystal grains that originate from native nuclei.

[0141] Furthermore, when forming a second metal oxide film on the metal oxide layer 70, crystal nuclei originating from the metal oxide layer 70 may be generated. In such cases, the growth of these crystal nuclei through heat treatment can increase the grain size of the crystal grains contained in the semiconductor layer 108, thereby reducing the number of grain boundaries.

[0142] It is preferable that the area of ​​the region where the metal oxide layer 70 and the semiconductor layer 108 are in contact is large. Increasing the area of ​​the region where they are in contact can promote crystal growth in the first metal oxide layer, which is preferable.

[0143] Here, if the number of crystal grains contained in the second metal oxide film increases at the stage of deposition, the grain size of the crystal grains after heat treatment may become smaller. Therefore, it is preferable that the number of crystal grains contained in the second metal oxide film is small at the stage of deposition. It is preferable that the crystallinity of the second metal oxide film is low, and it is particularly preferable that it be amorphous. It is preferable to use conditions that result in low crystallinity of the second metal oxide film when deposition. By performing heat treatment after deposition of a second metal oxide film with low crystallinity to induce crystallization, the grain size of the crystal grains can be increased.

[0144] Figure 1B and others show a configuration in which a semiconductor layer 108 is formed on a metal oxide layer 70. In other words, the second metal oxide film can be formed after the first metal oxide film has been formed. As mentioned above, it is preferable that the metal oxide layer 70 has high crystallinity, and therefore it is also preferable that the first metal oxide film has high crystallinity. For example, the substrate temperature during the formation of the first metal oxide film can be increased. On the other hand, it is preferable that the crystallinity of the second metal oxide film is low at the stage when it has been formed, and therefore the substrate temperature during the formation of the second metal oxide film can be decreased. Here, when the first metal oxide film is formed after the second metal oxide film has been formed, if the substrate temperature during the formation of the first metal oxide film is high, the number of crystal grains that form in the second metal oxide film at the stage of forming the first metal oxide film may increase. Therefore, it is preferable to form the second metal oxide film after the first metal oxide film has been formed. However, the present invention is not limited to this embodiment, and a configuration in which a metal oxide layer 70 is formed on the semiconductor layer 108 is also possible. In this case as well, the metal oxide layer 70 can function as a seed crystal layer, and the crystal grains contained in the semiconductor layer 108 can be enlarged.

[0145] In Figure 1A, the top surface shape of the metal oxide layer 70 is shown as a rectangle. The top surface shape of the metal oxide layer 70 is not particularly limited and can be a triangle, a quadrilateral (including rectangles and squares), a pentagon or other polygon, a polygon with rounded corners, an ellipse, or a circle.

[0146] Figure 1B and others show a configuration in which the semiconductor layer 108 covers a portion of the metal oxide layer 70. A portion of the upper surface and a portion of the side surface of the metal oxide layer 70 are in contact with the semiconductor layer 108, while the other upper surface and other side surfaces are in contact with the insulating layer 106. However, the present invention is not limited to this embodiment, and the semiconductor layer 108 can be provided so as to cover the entire metal oxide layer 70.

[0147] It is preferable that the seed crystal layer be positioned so as to overlap with one or both of region 108P and region 108Q. In other words, it is preferable that the seed crystal layer has a region in contact with one or both of region 108P and region 108Q. However, if the seed crystal layer (in this case, the metal oxide layer 70) has a region in contact with the channel formation region, the field-effect mobility of the transistor 100 may decrease. Therefore, it is preferable that the seed crystal layer does not have a region in contact with the channel formation region of the semiconductor layer 108. In other words, it is preferable that the seed crystal layer does not have a region that overlaps with the channel formation region of the semiconductor layer 108. However, the present invention is not limited to this, and the seed crystal layer may also have a region in contact with the channel formation region.

[0148] Figure 1B and others show a configuration in which the metal oxide layer 70 has a region that overlaps with region 108P, but does not overlap with either the channel formation region or region 108Q of the semiconductor layer 108. Region 108P has a region that is in contact with the upper surface and side surface of the metal oxide layer 70. On the other hand, the channel formation region and region 108Q of the semiconductor layer 108 are in contact with the upper surface of the insulating layer 105, but not with the upper surface or side surface of the metal oxide layer 70. In the configuration shown in Figure 1B and others, crystal growth proceeds from the region of the first metal oxide layer that is in contact with the metal oxide layer 70 (in this case, region 108P) toward the channel formation region.

[0149] In the semiconductor layer 108, it is preferable that the crystal grains are large and that the number of crystal grain boundaries is small. In particular, it is preferable that the number of crystal grain boundaries located in the channel formation region is small. By shortening the distance between the seed crystal layer and the channel formation region, the number of crystal grain boundaries located in the channel formation region can be reduced. Therefore, it is preferable to provide the seed crystal layer in a position that overlaps with one or both of region 108P and region 108Q.

[0150] The semiconductor layer 108 can be configured to have multiple regions in contact with the seed crystal layer. Examples of configurations different from those shown in Figures 1A and 1B are shown in Figures 4A and 4B. Figure 4A is a top view of a semiconductor device 10 according to one embodiment of the present invention. Figure 4B is a cross-sectional view of the cross-section along the dashed-dotted line A1-A2 shown in Figure 4A. Cross-sectional views of the cross-sections along the dashed-dotted lines B1-B2 and B3-B4 can be found in Figure 1C.

[0151] The semiconductor device 10 shown in Figures 4A and 4B includes a transistor 100, a transistor 200, a metal oxide layer 70, and a metal oxide layer 70A. The metal oxide layer 70 has a region in contact with region 108P, and the metal oxide layer 70A has a region in contact with region 108Q.

[0152] The metal oxide layer 70 and the metal oxide layer 70A each function as seed crystal layers. The metal oxide layer 70A can be made from the materials listed for the metal oxide layer 70. For details regarding the metal oxide layer 70A, please refer to the description for the metal oxide layer 70.

[0153] For example, the metal oxide layer 70A can be made from the same material as the metal oxide layer 70. Both the metal oxide layer 70A and the metal oxide layer 70 can be formed by processing the same metal oxide film. By forming the metal oxide layer 70A and the metal oxide layer 70 in the same process, the process can be simplified and manufacturing costs can be kept low. Furthermore, the semiconductor layer 208, the metal oxide layer 70A, and the metal oxide layer 70 can all be formed by processing the same metal oxide film.

[0154] Alternatively, the metal oxide layer 70A can be made of a different material than the metal oxide layer 70. This broadens the range of materials that can be used for the metal oxide layer 70A and the metal oxide layer 70. The metal oxide layer 70 and the metal oxide layer 70A can be formed in different processes.

[0155] When the first metal oxide layer, which will become the semiconductor layer 108, is subjected to heat treatment, crystal nuclei originating from the metal oxide layer 70 are formed in the region of the first metal oxide layer that is in contact with the metal oxide layer 70, and crystal nuclei originating from the metal oxide layer 70A are formed in the region of the first metal oxide layer that is in contact with the metal oxide layer 70A. Then, crystal growth progresses from the region of the first metal oxide layer that is in contact with the metal oxide layer 70 toward the channel formation region, and crystal growth also progresses from the region that is in contact with the metal oxide layer 70A toward the channel formation region. This suppresses the inclusion of crystal grains originating from natural nuclei in the semiconductor layer 108, or reduces the number of crystal grains originating from natural nuclei. Therefore, the number of crystal grain boundaries contained in the semiconductor layer 108 can be reduced.

[0156] In a configuration where one of region 108P and region 108Q is in contact with the seed crystal layer, if a difference occurs in the electrical characteristics of the transistor when the source and drain are swapped, the configurations shown in Figures 4A and 4B can be suitably used. By configuring both region 108P and region 108Q to be in contact with the seed crystal layer, the electrical characteristics can be made equivalent when the source and drain are swapped. Therefore, transistor 100 can be suitably used in circuit configurations where the source and drain are swapped.

[0157] Figures 4A and 4B show a configuration in which the semiconductor layer 108 has two regions in contact with the seed crystal layer, but the present invention is not limited to this. The semiconductor layer 108 can have one or three or more regions in contact with the seed crystal layer.

[0158] Here, the on-current of the transistor can be increased by increasing the thickness of the channel formation region of the semiconductor layer. However, if the thickness of the semiconductor layer is too thick, oxygen vacancies (V) in the semiconductor layer will occur. Ｏ ), and defects in which hydrogen enters the oxygen vacancy (hereinafter referred to as V ＯThe amount of (also written as H) increases. This can cause the transistor to exhibit normally-on characteristics. It can also lead to a decrease in reliability. In Figures 2A and 2B, the thickness T108 in the channel formation region of semiconductor layer 108 and the thickness T208 in the channel formation region of semiconductor layer 208 are shown by solid arrows, respectively. The thickness T108 can be the shortest distance between the surface of semiconductor layer 108 to be formed (in this case, the upper surface of the insulating layer 105) and the upper surface of semiconductor layer 108 in a cross-sectional view. The same applies to the thickness T208.

[0159] In Figure 2A, the thickness T70 of the region in contact with the semiconductor layer 108 in the metal oxide layer 70 is indicated by a solid arrow. The thickness T70 can be the shortest distance between the surface of the metal oxide layer 70 being formed (in this case, the upper surface of the insulating layer 105) and the upper surface of the metal oxide layer 70 in a cross-sectional view. As mentioned above, the metal oxide layer 70 and the semiconductor layer 208 can be formed by processing the same metal oxide film. Therefore, the thickness T70 can be the same as or approximately the same as the thickness T208. Note that the thickness T70 can also be configured to be different from the thickness T208.

[0160] When using a metal oxide with a high indium content in a semiconductor layer, if the thickness of the semiconductor layer is large, oxygen vacancies (V) in the semiconductor layer will increase. Ｏ ) and V ＯIf the amount of H increases, the transistor may exhibit normally-on characteristics. In such cases, it is preferable to reduce the thickness of the semiconductor layer. When a metal oxide with a high indium content is used for semiconductor layer 108 and semiconductor layer 208, the thickness T108 and thickness T208 are preferably 1 nm to 50 nm, more preferably 1 nm to 40 nm, more preferably 1 nm to 30 nm, more preferably 1 nm to 20 nm, and more preferably 1 nm to 10 nm. By setting the thickness T108 and thickness T208 within the above ranges, transistors 100 and 200 can be obtained that have good electrical characteristics and high reliability. Note that the thickness T108 and thickness T208 are not limited to the above ranges. Although Figures 2A and 2B show a configuration in which thickness T108 and thickness T208 are equal, the present invention is not limited to this.

[0161] Figure 5A shows configurations with different thicknesses T108 and T208. Figure 5B shows an enlarged view of transistor 100 shown in Figure 5A, and Figure 5C shows an enlarged view of transistor 200.

[0162] When a metal oxide with a low indium content is used in the semiconductor layer, the thickness of the semiconductor layer can be increased. By increasing the thickness of the semiconductor layer, the on-current of the transistor can be increased. For example, when a metal oxide with a lower indium content than semiconductor layer 108 is used in semiconductor layer 208, it is preferable that thickness T208 is thicker than thickness T108. This makes it possible to obtain transistors 100 and 200 with good electrical characteristics. The thickness T208 is preferably 1 nm to 50 nm, more preferably 5 nm to 50 nm, more preferably 10 nm to 50 nm, more preferably 10 nm to 40 nm, and more preferably 20 nm to 40 nm. By setting the thickness T208 within the above range, it is possible to obtain transistor 200 with good electrical characteristics and high reliability. Note that the thickness T208 is not limited to the above range. Also, the thickness T108 can be the same as or thicker than thickness T208.

[0163] By increasing the thickness T208, the thickness T70 can be increased. It is preferable that the thickness T70 is greater than the thickness T108. Increasing the thickness T70 may increase the crystallinity of the metal oxide layer 70. Increased crystallinity of the metal oxide layer 70 promotes the crystallization of the semiconductor layer 108, which is preferable. It is also possible to have a configuration where the thickness T70 is the same as or thinner than the thickness T108.

[0164] Figure 6A shows configurations with different thicknesses T70 and T208. Figure 6B shows an enlarged view of transistor 100 shown in Figure 6A, and Figure 6C shows an enlarged view of transistor 200.

[0165] As described above, a first metal oxide film is deposited, and the first metal oxide film is processed to form island-shaped metal oxide layers 70 and semiconductor layers 208. A second metal oxide film is deposited on the metal oxide layer 70, and the second metal oxide film is processed to form island-shaped first metal oxide layers that become semiconductor layers 108. When forming the first metal oxide layers, a portion of the region of the metal oxide layer 70 that does not overlap with the first metal oxide layer, and a portion of the region of the semiconductor layer 208 that does not overlap with the first metal oxide layer are removed, and the thickness of these regions may be reduced. As a result, the thickness of the region of the metal oxide layer 70 that does not contact the semiconductor layer 108 is reduced compared to the thickness T70 of the region of the metal oxide layer 70 that contacts the semiconductor layer 108. The thickness T70 is the same as or approximately the same as the thickness when the first metal oxide film was deposited. On the other hand, the thickness T208 of the semiconductor layer 208 is reduced compared to the thickness when the first metal oxide film was deposited. Therefore, the thickness T70 becomes thinner than the thickness T208. It is preferable to make the thickness of the first metal oxide film thicker than the desired thickness T208 when forming the film.

[0166] An insulating layer 195 is provided on the conductive layer 104, the conductive layer 204, and the insulating layer 106. The insulating layer 106 and the insulating layer 195 have openings 147a reaching region 108P, 147b reaching region 108Q, 247a reaching region 208P, and 247b reaching region 208Q.

[0167] A conductive layer 112a is provided so as to cover the opening 147a. The conductive layer 112a is in contact with region 108P at the opening 147a and is connected to region 108P. A conductive layer 112b is provided so as to cover the opening 147b. The conductive layer 112b is in contact with region 108Q at the opening 147b and is connected to region 108Q. The conductive layer 112a functions as one of the source electrode and drain electrode of the transistor 100, and the conductive layer 112b functions as the other of the source electrode and drain electrode.

[0168] A conductive layer 212a is provided so as to cover the opening 247a. The conductive layer 212a is in contact with region 208P at the opening 247a and is connected to region 208P. A conductive layer 212b is provided so as to cover the opening 247b. The conductive layer 212b is in contact with region 208Q at the opening 247b and is connected to region 208Q. The conductive layer 212a functions as one of the source electrode and drain electrode of the transistor 200, and the conductive layer 212b functions as the other of the source electrode and drain electrode.

[0169] Transistors 100 and 200 are so-called top-gate transistors, each having a gate electrode above the semiconductor layer. Furthermore, by supplying impurities to the semiconductor layer 108 using the conductive layer 104, which functions as the gate electrode, as a mask, regions 108P and 108Q, which function as the source and drain regions, can be formed in a self-aligned manner. Similarly, regions 208P and 208Q can be formed in a self-aligned manner using the conductive layer 204 as a mask. Transistors 100 and 200 can each be described as TGSA (Top Gate Self-Aligned) type transistors.

[0170] TGSA-type transistors allow for a larger physical distance between the source and drain electrodes and the gate electrode, thereby reducing parasitic capacitance between them.

[0171] Furthermore, the structure of the transistors applicable to the semiconductor device according to one aspect of the present invention is not particularly limited. Also, the structure of transistor 100 and the structure of transistor 200 can be different.

[0172] Regions 108P, 108Q, 208P, and 208Q each contain impurities. By supplying impurities to the semiconductor layer 108, the electrical resistance of regions 108P and 108Q can be lowered. The concentration of impurities in regions 108P and 108Q is higher than the concentration of impurities in the channel-forming region of the semiconductor layer 108. The elements contained in the impurities (hereinafter also referred to as the first element) can be one or more of hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, magnesium, silicon, and noble gases. Representative examples of noble gases include helium, neon, argon, krypton, and xenon. It is particularly preferable to use one or more of hydrogen, boron, phosphorus, aluminum, magnesium, and silicon as the first element. The same applies to semiconductor layer 208, region 208P, and region 208Q.

[0173] In the following explanation, we will use regions 108P and 108Q as examples, and may omit explanations of regions 208P and 208Q. For information on regions 208P and 208Q, please refer to the descriptions related to regions 108P and 108Q.

[0174] Ion implantation is suitably used for supplying impurities. Ion implantation allows for highly precise control of the concentration profile in the depth direction by controlling the ion acceleration energy and dose amount. Furthermore, by using an ion implantation method that ionizes the source gas and supplies the ions after mass separation, it is possible to supply ions of a specific mass, thereby increasing the purity of the supplied impurities. Alternatively, productivity can be increased by using an ion implantation method that supplies ions without mass separation. Unless otherwise specified in this specification, the presence or absence of mass separation is not limited. Note that the method of supplying ions after mass separation is sometimes called ion implantation, and the method of supplying ions without mass separation is sometimes called ion doping.

[0175] When an element that readily bonds with oxygen is used as the first element, the first element removes oxygen from the semiconductor layer 108 and exists in a state bonded with oxygen. In addition, oxygen vacancies (V) exist in the semiconductor layer 108. Ｏ ) occurs. If an element that becomes stable when bonded with oxygen is used as the first element, the first element in the semiconductor layer 108 exists stably in an oxidized state, so it is less likely to desorb due to heat applied during the semiconductor device manufacturing process, and the electrical resistance of regions 108P and 108Q can be kept low. For this reason, it is preferable to use an element as the first element in which its oxide can exist as a solid at least at the temperature during the manufacturing process. Boron and phosphorus, or both, can be suitably used as the first element.

[0176] When boron is used as the first element, the boron contained in regions 108P and 108Q can exist in a state bonded with oxygen. This is evident in XPS analysis, B ２ O ３ This can be confirmed by observing spectral peaks caused by bonding. Furthermore, in XPS analysis, spectral peaks caused by the element boron in its elemental state may not be observed, or their intensity may be extremely low, almost at background levels.

[0177] Hydrogen, through its supply, can fill oxygen deficiencies (V Ｏ ) occurs, along with oxygen deficiency (V Ｏ By entering V Ｏ Because H is generated, the electrical resistance of regions 108P and 108Q can be efficiently reduced. Therefore, hydrogen can be suitably used as the first element.

[0178] In supplying impurities, it is preferable to adjust the supply conditions so that the concentration of impurities is highest on the surface of the semiconductor layer 108, or in a region close to the surface.

[0179] The raw material used to supply impurities can, for example, be a gas containing the first element. When supplying boron, typically B ２ H ６ Gas, or BF ３One or more gases can be used. Also, when supplying phosphorus, typically pH ３ Gases can be used. Alternatively, gases obtained by diluting these source gases with noble gases can also be used.

[0180] For example, CH4 is used as a raw material for supplying impurities. ４ , N ２ NH ３ , AlH ３ AlCl ３ SiH ４ Si ２ H ６ F ２ HF, H ２ , (C ５ H ５ ) ２ Mg and noble gases can be used. The raw materials are not limited to gases; solids or liquids can also be heated and vaporized for use.

[0181] The supply of impurities can be controlled by setting conditions such as acceleration voltage and dose amount, taking into consideration the composition, density, and thickness of the insulating layer 106 and the semiconductor layer 108. When supplying impurities to the semiconductor layer 108 via the insulating layer 106 using the conductive layer 104 as a mask, impurities may be supplied to areas of the insulating layer 106 that do not overlap with the conductive layer 104, resulting in those areas containing impurities. Similarly, impurities may be supplied to areas of the insulating layer 105 that do not overlap with the conductive layer 104, resulting in those areas containing impurities.

[0182] The method of supplying impurities is not limited to this; for example, plasma treatment or treatment utilizing thermal diffusion by heating can also be used. In the case of plasma treatment, impurities can be supplied by generating plasma in a gas atmosphere containing the impurities to be supplied and performing plasma treatment. As the apparatus for generating the plasma, dry etching apparatus, ashing apparatus, plasma CVD apparatus, high-density plasma CVD apparatus, etc., can be used.

[0183] For example, by using a plasma CVD apparatus and performing plasma processing in an atmosphere containing a gas with hydrogen elements, hydrogen can be supplied as an impurity to regions of the semiconductor layer 108 that do not overlap with the conductive layer 104. Furthermore, by using a plasma CVD apparatus for supplying impurities and forming the insulating layer 105, the supply of impurities and the formation of the insulating layer 105 can be performed continuously within the apparatus, thereby increasing productivity.

[0184] The first element present in regions 108P and 108Q can have the same configuration as the first element present in regions 208P and 208Q. This allows for the common use of equipment for supplying the first element, thereby reducing the manufacturing cost of semiconductor devices. Alternatively, the first element present in regions 108P and 108Q can have different configurations than the first element present in regions 208P and 208Q. Depending on the materials used for semiconductor layer 108 and semiconductor layer 208, the range of choices for the first element supplied to semiconductor layer 108 and the first element supplied to semiconductor layer 208 can be broadened.

[0185] When supplying impurities to semiconductor layer 108 and semiconductor layer 208, impurities may also be supplied to metal oxide layer 70. Metal oxide layer 70 contains a first element. Furthermore, the concentration of the first element can vary within the metal oxide layer 70. For example, the first element can be supplied to the region of the metal oxide layer 70 in contact with semiconductor layer 108 via the insulating layer 106 and semiconductor layer 108. On the other hand, the first element can be supplied to the region of the metal oxide layer 70 that does not contact semiconductor layer 108 via the insulating layer 106. As a result, the concentration of the first element in the region of the metal oxide layer 70 not in contact with semiconductor layer 108 may be higher than the concentration of the first element in the region in contact with semiconductor layer 108. Also, the electrical resistance of the region of the metal oxide layer 70 not in contact with semiconductor layer 108 may be lower than the electrical resistance of the region in contact with semiconductor layer 108.

[0186] A transistor 100 with high field-effect mobility and large on-current, and a transistor 200 with high saturation, can be formed on the same substrate by sharing some of the manufacturing processes. For example, by applying transistor 100 to the transistor requiring a large on-current and transistor 200 to the transistor requiring high saturation, a high-performance semiconductor device can be created.

[0187] One embodiment of the present invention is suitable for use, for example, in one or both of the pixel circuit and the drive circuit of a display device.

[0188] When a light-emitting element is used as a display element, the pixel circuit can be configured to include a drive transistor for controlling the current flowing through the light-emitting element and a selection transistor that functions as a switch for controlling the selection and deselection of the pixel. Transistor 100 can be suitably used as the selection transistor where high-speed operation is required, and transistor 200 can be suitably used as the drive transistor where high saturation is required. Furthermore, by using transistor 100 in the drive circuit, a high-speed drive circuit can be made. This makes it possible to create a display device with high display quality.

[0189] Because the semiconductor device according to one aspect of the present invention occupies a small area, using it in a pixel circuit can reduce the area occupied by the pixel circuit, enabling a high-resolution display device. Furthermore, using it in a drive circuit can reduce the area occupied by the drive circuit, enabling a narrow-bezel display device.

[0190] The materials that can be used for each component will be described below. In the following, semiconductor layer 108, conductive layer 104, conductive layer 112a, and conductive layer 112b may be used as examples. For semiconductor layer 208, conductive layer 204, conductive layer 212a, and conductive layer 212b, refer to the descriptions for semiconductor layer 108, conductive layer 104, conductive layer 112a, and conductive layer 112b.

[0191] [Semiconductor layer 108, semiconductor layer 208, metal oxide layer 70] The metal oxides that can be used in semiconductor layer 108, semiconductor layer 208, and metal oxide layer 70 will be described in detail. As mentioned above, it is preferable that the metal oxide contains at least indium.

[0192] When the metal oxide is an In-M-Zn oxide, it is preferable that the atomic ratio of In in the In-M-Zn oxide is equal to or greater than the atomic ratio of element M. Examples of such atomic ratios of metal elements in an In-M-Zn oxide include In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 2:1:3, In:M:Zn = 3:1:1, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:3, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, and In:M Compositions such as Zn=5:1:9, In:M:Zn=6:1:6, In:M:Zn=10:1:1, In:M:Zn=10:1:3, In:M:Zn=10:1:4, In:M:Zn=10:1:6, In:M:Zn=10:1:7, In:M:Zn=10:1:8, In:M:Zn=5:2:5, In:M:Zn=10:1:10, In:M:Zn=20:1:10, In:M:Zn=40:1:10, and compositions near these. Note that compositions near these include a range of ±30% of the desired atomic ratio. Increasing the atomic ratio of indium in the metal oxide can increase the on-current or field-effect mobility of the transistor.

[0193] The atomic ratio of In in an In-M-Zn oxide can be less than the atomic ratio of element M. Examples of such atomic ratios of metal elements in an In-M-Zn oxide include In:M:Zn = 1:3:2, In:M:Zn = 1:3:3, In:M:Zn = 1:3:4, In:M:Zn = 1:3:6, and compositions close to these. By increasing the proportion of M atoms in the metal oxide, oxygen deficiency (V) can be reduced. Ｏ This can suppress the generation of ()

[0194] Furthermore, if element M comprises multiple elements, the sum of their atomic ratios can be used as the atomic ratio of element M.

[0195] By using a material with a high indium content in the semiconductor layer, the on-current or field-effect mobility of the transistor can be increased. Furthermore, the presence of element M allows for oxygen deficiency (V Ｏ The generation of ) can be suppressed. The content of element M (the ratio of the number of atoms of element M to the sum of the number of atoms of all contained metal elements) is preferably 0.1% to 25%, more preferably 0.1% to 20%, more preferably 0.1% to 10%, more preferably 0.1% to 8%, more preferably 0.1% to 6%, and more preferably 0.1% to 4%. This makes it possible to make a transistor with good electrical properties. For example, it is preferable to use a metal oxide in which In:M:Zn = 40:1:10 or a nearby ratio. Element M is preferably one or more of the above elements, and more preferably one or more selected from aluminum, gallium, tin, and yttrium. Specifically, a metal oxide in which In:Sn:Zn = 40:1:10 or a nearby ratio can be suitably used. Alternatively, a metal oxide in which In:Al:Zn = 40:1:10 or a nearby ratio can be suitably used.

[0196] A metal oxide that does not contain element M can be applied to the semiconductor layer 108, the semiconductor layer 208, and the metal oxide layer 70. When the metal oxide is an In-Zn oxide, examples of atomic ratios of the metal elements include In:Zn=1:1, In:Zn=2:1, In:Zn=1:2, In:Zn=3:1, In:Zn=3:2, In:Zn=2:3, In:Zn=4:1, In:Zn=4:3, In:Zn=5:1, In:Zn=5:2, In:Zn=5:3, In:Zn=5:4, In:Zn=5:6, In:Zn=5:7, In:Zn=5:8, In:Zn=5:9, In:Zn=7:1, In:Zn=10:1, In:Zn=10:3, In:Zn=10:7, and compositions near these values. Furthermore, it is more preferable that the atomic ratio of In is greater than or equal to that of Zn. Increasing the atomic ratio of indium in the metal oxide can increase the on-current or field-effect mobility of the transistor.

[0197] For the analysis of the composition of semiconductor layer 108, semiconductor layer 208, and metal oxide layer 70, for example, energy-dispersive X-ray spectroscopy (EDX), X-ray photoelectron spectroscopy (XPS), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled high-frequency plasma atomic emission spectroscopy (ICP-AES) can be used. Alternatively, a combination of these methods can be used for the analysis. XPS is sometimes referred to as ESCA (Electron Spectrometry for Chemical Analysis). It is preferable to separate the peaks of the spectrum obtained by the analysis and then identify and quantify the elements. However, for elements with low content, the actual content may differ from the content obtained by the analysis due to the effect of analytical accuracy. For example, if the content of element M is low, the content of element M obtained by the analysis may be lower than the actual content, it may be difficult to quantify the content of element M, or element M may be below the detection limit.

[0198] For depositing metal oxide films, sputtering or atomic layer deposition (ALD) can be suitably used. However, when depositing metal oxide films by sputtering, the composition of the deposited metal oxide film may differ from the composition of the sputtering target. In particular, the zinc content in the deposited metal oxide film may decrease to about 50% of the content in the sputtering target.

[0199] When a metal oxide is used in the semiconductor layer, the V of the channel formation region Ｏ It is preferable to reduce H as much as possible and make it high-purity intrinsic or substantially high-purity intrinsic. In this way, V ＯTo obtain a metal oxide with sufficiently reduced H content, impurities such as water and hydrogen must be removed from the metal oxide (sometimes referred to as dehydration and dehydrogenation treatment), and oxygen must be supplied to the metal oxide to eliminate oxygen deficiency (V). Ｏ It is important to repair ). Ｏ By using a metal oxide with sufficiently reduced impurities such as H in the channel formation region, a transistor with stable electrical characteristics can be made. Furthermore, by supplying oxygen to the metal oxide, oxygen deficiencies (V) can be reduced. Ｏ The process of repairing this is sometimes referred to as oxygenation treatment.

[0200] OS transistors exhibit minimal fluctuations in electrical properties due to radiation exposure, meaning they have high resistance to radiation, making them suitable for use in environments where radiation may be incident. OS transistors can also be said to have high reliability against radiation. For example, OS transistors can be suitably used in the pixel circuits of X-ray flat panel detectors. Furthermore, OS transistors can be suitably used in semiconductor devices used in outer space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, proton beams, and neutron beams).

[0201] The semiconductor layer may have a layered material that functions as a semiconductor. A layered material is a general term for a group of materials that have a layered crystalline structure. Layered materials have high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0202] Examples of the above-mentioned layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogens (elements belonging to Group 16). Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specifically, a transition metal chalcogenide applicable as a channel formation region in transistors is molybdenum sulfide (typically MoS ２ ), molybdenum selenide (typically MoSe ２), molybdenum tellurium (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２ ), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ ) are some examples.

[0203] [Insulating layer 106, insulating layer 105] It is preferable that insulating layer 106 and insulating layer 105 each have one or more inorganic insulating layers. Examples of materials that can be used for the inorganic insulating layer include oxides, nitrides, oxidized nitrides, and nitride oxides. Examples of oxides include silicon oxide, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, cerium oxide, zinc gallium oxide, and hafnium aluminate. Examples of nitrides include silicon nitride and aluminum nitride. Examples of oxidized nitrides include silicon oxidized nitride, aluminum oxidized nitride, gallium oxidized nitride, yttrium oxidized nitride, and hafnium oxidized nitride. Examples of nitride oxides include silicon nitride and aluminum nitride.

[0204] In this specification, the term "oxidogenic nitride" refers to a material whose composition contains more oxygen than nitrogen. The term "nitride oxide" refers to a material whose composition contains more nitrogen than oxygen.

[0205] The insulating layer 106 has a region that is in contact with the semiconductor layer 108. When a metal oxide is used for the semiconductor layer 108, it is preferable that at least a portion of the region of the insulating layer 106 that is in contact with the semiconductor layer 108 contains oxygen in order to improve the interfacial characteristics between the semiconductor layer 108 and the insulating layer 106. Specifically, it is preferable that the region of the insulating layer 106 that is in contact with the channel-forming region of the semiconductor layer 108 contains oxygen. One or more oxides and oxiditrides can be suitably used in the region of the insulating layer 106 that is in contact with the channel-forming region of the semiconductor layer 108. The same applies to the insulating layer 105. For example, it is preferable that the insulating layer 106 and the insulating layer 105 each contain silicon and oxygen, respectively. Silicon oxide or silicon oxiditride can be suitably used for the insulating layer 106 and the insulating layer 105, respectively.

[0206] In the case of miniature transistors, if the thickness of the gate insulating layer is reduced, the leakage current may increase. By using a material with a high dielectric constant (also called a high-k material) for the gate insulating layer, it is possible to reduce the voltage during transistor operation while maintaining the physical film thickness. Examples of high-k materials that can be used for the insulating layer 106 include gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, oxiditrides having aluminum and hafnium, oxides having silicon and hafnium, oxiditrides having silicon and hafnium, and nitrides having silicon and hafnium.

[0207] In Figure 1B and other figures, the insulating layer 106 and insulating layer 105 are shown as single-layer structures, but the present invention is not limited to this. One or both of the insulating layer 106 and insulating layer 105 can be made into a laminated structure of two or more layers. When the insulating layer 106 is made into a laminated structure, it is preferable that the insulating layer on the semiconductor layer 108 side has an oxide or oxidizride. Similarly, when the insulating layer 105 is made into a laminated structure, it is preferable that the insulating layer on the semiconductor layer 108 side has an oxide or oxidizride. For example, silicon oxide, silicon oxidizride, or aluminum oxide can be suitably used as the insulating layer on the semiconductor layer 108 side.

[0208] It is preferable to use a material that is difficult for substances to permeate in one or more of the layers constituting the insulating layer 106. This layer can also be said to function as a barrier film. By providing a layer that functions as a barrier film, it is possible to suppress the diffusion of metal components contained in the conductive layer 104 and impurities (e.g., water and hydrogen) contained in the layer formed on the transistor 100 into the semiconductor layer 108 via the insulating layer 106. Furthermore, it is possible to suppress the diffusion of oxygen contained in the semiconductor layer 108 into the conductive layer 104 side via the insulating layer 106. As a result, oxygen deficiencies (V) in the semiconductor layer 108 are suppressed. Ｏ This can suppress the formation of ( ). Furthermore, it can suppress oxidation of the conductive layer 104 by oxygen contained in the semiconductor layer 108, which would increase the electrical resistance of the conductive layer 104. As a result, a transistor with good electrical characteristics and high reliability can be obtained. Similarly, it is preferable to provide a layer that functions as a barrier film on one or more of the layers constituting the insulating layer 105.

[0209] In this specification, the term "barrier film" refers to a film that possesses barrier properties. Barrier properties refer to one or both of the following functions: a function that makes it difficult for a target substance to diffuse, thereby suppressing the permeation of the substance through the film (also known as low permeability); and a function that captures or fixes the substance (also known as gettering). For example, an insulating layer that possesses barrier properties can be called a barrier insulating layer.

[0210] The barrier film can be made from, for example, one or more oxides having aluminum and / or hafnium, an oxide having magnesium, an oxide having gallium, a nitride having silicon, and a silicon nitride oxide. Typically, the barrier film can be made from one or more aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, zinc gallium oxide, silicon nitride, and silicon nitride oxide. The barrier film of the insulating layer 106 can be made from one or more oxides and oxidized nitrides, for example, aluminum oxide can be used suitably. The barrier film of the insulating layer 105 can be made from one or more nitrides and nitride oxides, for example, silicon nitride can be used suitably.

[0211] The insulating layer 106 can be, for example, a laminated structure of a silicon oxidizide film and a silicon nitride film on the silicon oxidizide film. Alternatively, the insulating layer 106 can be a laminated structure of a silicon oxidizide film and an aluminum oxide film on the silicon oxidizide film. Alternatively, the insulating layer 106 can be a laminated structure of an aluminum oxide film and a silicon oxidizide film on the aluminum oxide film. Alternatively, the insulating layer 106 can be a laminated structure of an aluminum oxide film and a silicon nitride film on the aluminum oxide film. Here, an example is shown in which the insulating layer 106 has a two-layer laminated structure, but the present invention is not limited to this. The insulating layer 106 can also have a laminated structure of three or more layers.

[0212] The insulating layer 105 can, for example, be a laminated structure of a silicon nitride film and a silicon oxynitride film on the silicon nitride film. Here, an example is shown in which the insulating layer 105 has a two-layer laminated structure, but the present invention is not limited to this. The insulating layer 105 can also have a laminated structure of three or more layers.

[0213] [Conductive layer 112a, conductive layer 112b, conductive layer 212a, conductive layer 212b, conductive layer 104, conductive layer 204] Conductive layers 112a, 112b, 212a, 212b, 104, and 204 can each be a single layer or a laminated structure of two or more layers. Materials that can be used for these conductive layers include, for example, one or more of chromium, copper, aluminum, gold, silver, zinc, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, molybdenum, and niobium, as well as alloys composed of one or more of the aforementioned metals. Conductive materials with low electrical resistivity, each containing one or more of copper, silver, gold, and aluminum, can be suitably used for these conductive layers. Copper or aluminum are particularly preferred due to their excellent mass productivity.

[0214] Conductive layers 112a, 112b, 212a, 212b, 104, and 204 can each be made of a conductive metal oxide (also called an oxide conductor (OC)). Examples of oxide conductors include indium oxide, zinc oxide, ITO, In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, ITSO, zinc oxide with added gallium, and In-Ga-Zn oxide. Oxide conductors containing indium are particularly preferred due to their high conductivity.

[0215] When oxygen vacancies are formed in a metal oxide with semiconductor properties, and hydrogen is added to these vacancies, donor levels are formed near the conduction band. As a result, the metal oxide becomes highly conductive and turns into a conductor. A metal oxide that has become conductive can be called an oxide conductor.

[0216] The conductive layers 112a, 112b, 212a, 212b, 104, and 204 can each be a laminated structure of a conductive film containing the aforementioned oxide conductor (metal oxide) and a conductive film containing a metal or alloy. By using a conductive film containing a metal or alloy, the wiring resistance can be reduced.

[0217] Conductive layers 112a, 112b, 212a, 212b, 104, and 204 can each be made of nitride conductors. Examples of nitride conductors include tantalum nitride and titanium nitride.

[0218] Conductive layers 112a, 112b, 212a, 212b, 104, and 204 can each be made of a Cu-X alloy film (where X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti). Using a Cu-X alloy film allows for processing by wet etching, thus reducing manufacturing costs.

[0219] Note that conductive layers 112a, 112b, 212a, 212b, 104, and 204 can be made of the same material. Alternatively, at least one of them can be made of a different material.

[0220] [Insulating layer 195, insulating layer 218] As shown in Figure 7A, an insulating layer 218 can be provided on the insulating layer 195. Figure 7A is a cross-sectional view of the section along the dashed line A1-A2 shown in Figure 1A. The insulating layer 218 functions as a protective layer for transistors 100 and 200.

[0221] The insulating layer 195 and the insulating layer 218 can each be a single-layer structure or a laminated structure. Preferably, the insulating layer 195 and the insulating layer 218 each have one or more inorganic insulating layers. The inorganic insulating layer can be made from the materials listed for insulating layer 106 and insulating layer 105.

[0222] It is preferable to provide a layer that functions as a barrier film on one or both of the insulating layer 195 and the insulating layer 218. This suppresses the diffusion of impurities (e.g., water and hydrogen) into the transistor from the outside, and suppresses a shift in the threshold voltage. Therefore, a highly reliable semiconductor device can be made. Furthermore, if impurities can diffuse into the semiconductor layer 108 via the conductive layer 112a and conductive layer 112b, and into the semiconductor layer 208 via the conductive layer 212a and conductive layer 212b, it is preferable to provide a layer that functions as a barrier film on the insulating layer 218. Refer to the above description for details on the barrier film. The insulating layer 195 and the insulating layer 218 can preferably be one or more of, for example, silicon nitride, silicon oxide nitride, and aluminum oxide. When an aluminum oxide film is used as the barrier film, it is preferable because it has extremely high barrier properties even when thin.

[0223] Figure 7B shows an example of a configuration in which the insulating layer 218 has a laminated structure. Figure 7B shows an example in which the insulating layer 218 has a laminated structure of insulating layer 218a and insulating layer 218b on insulating layer 218a. It is preferable to provide a layer that functions as a barrier film on one or both of the insulating layer 218a and insulating layer 218b. This enhances the effect of suppressing the diffusion of impurities into the transistor from the outside. For example, aluminum oxide can be suitably used for insulating layer 218a, silicon nitride for insulating layer 218b, and silicon nitride oxide for insulating layer 195. Furthermore, the aluminum oxide film can be formed using the sputtering method, and the silicon nitride film and silicon nitride oxide film can be formed using the PECVD method, respectively. Here, the sputtering method has lower coverage than the PECVD method. Therefore, by forming a laminated structure of insulating layer 218a formed using the sputtering method and insulating layer 218b formed using the PECVD method, the barrier properties of the insulating layer 218 can be further enhanced. Similarly, the insulating layer 195 can also be made into a laminated structure.

[0224] [Substrate 102] There are no major restrictions on the material of the substrate 102, but it must have at least enough heat resistance to withstand subsequent heat treatment. For example, single-crystal semiconductor substrates made of silicon or silicon carbide, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SOI substrates, glass substrates, quartz substrates, sapphire substrates, ceramic substrates, or resin substrates can be used as the substrate 102. In addition, a substrate on which a semiconductor element is provided can be used as the substrate 102. A substrate with an insulating film formed on its surface can be used as the substrate 102. The shape of the substrate 102 is not particularly limited and can be circular or rectangular, for example.

[0225] A flexible substrate can be used as the substrate 102, and transistors 100, etc., can be formed directly on the flexible substrate. Alternatively, a release layer can be provided between the substrate 102 and the transistors 100, etc. By providing a release layer, after partially or completely completing the semiconductor device on it, it can be separated from the substrate 102 and transferred to another substrate. In this case, the transistors 100, etc., can also be transferred to a substrate with low heat resistance or a flexible substrate.

[0226] The following describes a configuration example that differs in some aspects from the aforementioned Configuration Example 1. Note that in the following, explanations of parts that overlap with Configuration Example 1 may be omitted. Furthermore, in the drawings shown below, parts having the same function as those in Configuration Example 1 may use the same hatching pattern and may not be labeled.

[0227] <Configuration Example 2> Figures 8A and 8B show cross-sectional views of a semiconductor device 10A, which is one embodiment of the present invention. A top view of the semiconductor device 10A can be found in Figure 1A. Figure 8A is a cross-sectional view of the section along the dashed-dotted line A1-A2 shown in Figure 1A, and Figure 8B is a cross-sectional view of the section along the dashed-dotted lines B1-B2 and B3-B4.

[0228] The semiconductor device 10A includes a transistor 100A, a transistor 200A, and a metal oxide layer 70. Transistor 100A differs from transistor 100 shown in Figure 1B, etc., in that the edge of the insulating layer 106 coincides with or approximately coincides with the edge of the conductive layer 104. Transistor 200A differs from transistor 200 in that it has an insulating layer 206 instead of the insulating layer 106. The edge of the insulating layer 206 coincides with or approximately coincides with the edge of the conductive layer 204. Furthermore, the insulating layer 106 and the insulating layer 206 can be formed by processing the same film.

[0229] The edges of the insulating layer 106 are located on the semiconductor layer 108. Furthermore, the insulating layer 106 does not overlap with either region 108P or region 108Q. It can also be said that the top surface shape of the insulating layer 106 matches, or roughly matches, the conductive layer 104. Similarly, the edges of the insulating layer 206 are located on the semiconductor layer 208. Furthermore, the insulating layer 206 does not overlap with either region 208P or region 208Q. It can also be said that the top surface shape of the insulating layer 206 matches, or roughly matches, the conductive layer 204. The insulating layers 106 and 206 can be formed, for example, by processing using a resist mask for processing the conductive layers 104 and 204.

[0230] The insulating layer 195 has regions in contact with the upper and side surfaces of the semiconductor layer 108, the upper and side surfaces of the semiconductor layer 208, the side surfaces of the insulating layer 106, the side surfaces of the insulating layer 206, the upper and side surfaces of the conductive layer 104, and the upper and side surfaces of the conductive layer 204. The insulating layer 195 has an opening 147a reaching region 108P, an opening 147b reaching region 108Q, an opening 247a reaching region 208P, and an opening 247b reaching region 208Q.

[0231] Figures 8C and 8D show configuration examples different from those shown in Figures 8A and 8B. Figures 8C and 8D are cross-sectional views of a semiconductor device 10B according to one aspect of the present invention. A top view of the semiconductor device 10B can be found in Figure 1A. Figure 8C is a cross-sectional view of the section along the dashed-dotted line A1-A2 shown in Figure 1A, and Figure 8D is a cross-sectional view of the section along the dashed-dotted lines B1-B2 and B3-B4.

[0232] The semiconductor device 10B includes a transistor 100B, a transistor 200B, and a metal oxide layer 70. Transistor 100B differs from transistor 100A shown in Figure 8A, etc., in that the insulating layer 106 has a region that protrudes beyond the conductive layer 104. Transistor 200B also differs from transistor 100A in that the insulating layer 206 has a region that protrudes beyond the conductive layer 204.

[0233] The edges of the insulating layer 106 are located on the semiconductor layer 108, and the edges of the conductive layer 104 are located on the insulating layer 106. It can also be said that the edges of the insulating layer 106 are located outside the edges of the conductive layer 104. The insulating layer 106 has a region on the semiconductor layer 108 that overlaps with the conductive layer 104 and a region that does not overlap with the conductive layer 104. The edges of the insulating layer 206 are located on the semiconductor layer 208, and the edges of the conductive layer 204 are located on the insulating layer 206. It can also be said that the edges of the insulating layer 206 are located outside the edges of the conductive layer 204. The insulating layer 206 has a region on the semiconductor layer 208 that overlaps with the conductive layer 204 and a region that does not overlap with the conductive layer 204.

[0234] The semiconductor layer 108 has a channel formation region, a pair of regions (region 108R and region 108S) flanking the channel formation region, and a pair of regions (region 108P and region 108Q) located outside of these. Regions 108R and 108S are regions of the semiconductor layer 108 that overlap with the insulating layer 106 and do not overlap with the conductive layer 104. Region 108R is located between the channel formation region and region 108P, and region 108S is located between the channel formation region and region 108Q.

[0235] The semiconductor layer 208 has a channel formation region, a pair of regions (region 208R and region 208S) flanking the channel formation region, and a pair of regions (region 208P and region 208Q) located outside of these regions. Regions 208R and 208S are regions of the semiconductor layer 208 that overlap with the insulating layer 206 and do not overlap with the conductive layer 204. Region 208R is located between the channel formation region and region 208P, and region 208S is located between the channel formation region and region 208Q.

[0236] Regions 108R, 108S, 208R, and 208S function as buffer regions to mitigate the drain electric field. Since regions 108R and 108S do not overlap with the conductive layer 104, channels are hardly formed in these regions even when a gate voltage is applied to the conductive layer 104. It is preferable that the carrier concentration in regions 108R and 108S is higher than that in the channel formation region. This allows regions 108R and 108S to function as LDD (Lightly Doped Drain) regions.

[0237] Regions 108R and 108S can also be described as regions with similar or lower electrical resistance, similar or higher carrier concentration, similar or higher oxygen defect density, and similar or higher impurity concentration compared to the channel-forming region.

[0238] Regions 108R and 108S can also be described as regions with similar or higher electrical resistance, similar or lower carrier concentration, similar or lower oxygen defect density, and similar or lower impurity concentration compared to regions 108P and 108Q.

[0239] For regions 208R and 208S, refer to the descriptions relating to regions 108R and 108S.

[0240] The insulating layer 195 has regions in contact with the upper and side surfaces of the semiconductor layer 108, the upper and side surfaces of the semiconductor layer 208, the upper and side surfaces of the insulating layer 106, the upper and side surfaces of the insulating layer 206, the upper and side surfaces of the conductive layer 104, and the upper and side surfaces of the conductive layer 204. The insulating layer 195 has an opening 147a reaching region 108P, an opening 147b reaching region 108Q, an opening 247a reaching region 208P, and an opening 247b reaching region 208Q.

[0241] <Configuration Example 3> Figure 9A shows a top view of a semiconductor device 10C, which is one embodiment of the present invention. Figure 9B shows a cross-sectional view of the cross-section along the dashed-dotted line A1-A2 shown in Figure 9A, and Figure 9C shows cross-sectional views of the cross-section along the dashed-dotted lines B1-B2 and B3-B4.

[0242] The semiconductor device 10C includes a transistor 100C, a transistor 200C, and a metal oxide layer 70. Transistor 100C differs from transistor 100 shown in Figure 1B, etc., in that it has a conductive layer 103. Transistor 200C differs from transistor 200 in that it has a conductive layer 203.

[0243] Conductive layer 103 and conductive layer 203 are provided between substrate 102 and insulating layer 105, respectively. Conductive layer 103 has a region that overlaps with conductive layer 104 via insulating layer 105, semiconductor layer 108, and insulating layer 106. In transistor 100C, conductive layer 103 functions as a back gate electrode, and insulating layer 105 functions as a back gate insulating layer. Conductive layer 203 has a region that overlaps with conductive layer 204 via insulating layer 105, semiconductor layer 208, and insulating layer 106. In transistor 200C, conductive layer 203 functions as a back gate electrode, and insulating layer 105 functions as a back gate insulating layer.

[0244] By providing a back gate electrode, the potential on the back gate electrode side (also called the back channel side) of the semiconductor layer 108 is fixed, which can improve the saturation in the Id-Vd characteristics. Furthermore, by fixing the potential on the back channel side of the semiconductor layer 108, the threshold voltage shift can be suppressed. Therefore, a transistor with a small cutoff current can be made, resulting in a semiconductor device with low power consumption.

[0245] The conductive layer 103 preferably has a region that protrudes from the edge of the conductive layer 104. This enhances the effect of making it difficult for electric fields generated outside the transistor to act on the channel formation region (also known as the electric field shielding effect).

[0246] The conductive layer 103 can be configured to be connected to either the conductive layer 112a or the conductive layer 112b. For example, by providing openings in the insulating layer 195, insulating layer 106, and insulating layer 105 that reach the conductive layer 103, and providing the conductive layer 112a so as to cover these openings, the conductive layer 103 and the conductive layer 112a can be in contact. By connecting the conductive layer 112a and the conductive layer 103, the source electrode and the drain electrode and the back gate electrode can be brought to the same potential. For example, when the conductive layer 112a functions as the source electrode, a shift in the threshold voltage of the transistor 100C can be suppressed. Furthermore, the reliability of the transistor 100C can be improved.

[0247] The conductive layer 103 can be configured to be connected to the conductive layer 104. For example, by providing openings in the insulating layer 106 and the insulating layer 105 that reach the conductive layer 103, and providing the conductive layer 104 so as to cover the openings, the conductive layer 103 and the conductive layer 104 can be in contact. By connecting the gate electrode and the back gate electrode, the back gate electrode and the gate electrode can be brought to the same potential, and the on-current of the transistor 100C can be increased.

[0248] The conductive layer 103 can be made from the materials listed for conductive layer 104, conductive layer 112a, and conductive layer 112b. Since the conductive layer 103 is formed before the semiconductor layer 108, it is preferable to use a material that can withstand the heat treatment involved in the formation of the semiconductor layer 108. It is preferable to use a high melting point material (for example, tungsten and molybdenum) that provides both heat resistance and conductivity for the conductive layer 103. For example, tungsten can be suitably used for the conductive layer 103.

[0249] For details regarding the conductive layer 203, refer to the description relating to the conductive layer 103.

[0250] Furthermore, transistors with a back gate electrode and transistors without a back gate electrode can be combined. For example, transistor 200C with a back gate electrode (see Figures 9A to 9C) can be combined with transistor 100 without a back gate electrode (see Figures 1A to 1C).

[0251] <Configuration Example 4> Figure 10A shows a top view of a semiconductor device 10D, which is one embodiment of the present invention. Figure 10B shows a cross-sectional view of the cross-section along the dashed-dotted line A1-A2 shown in Figure 10A. For cross-sectional views of the cross-sections along the dashed-dotted lines B1-B2 and B3-B4, please refer to Figure 1C.

[0252] The semiconductor device 10D includes transistor 100 and transistor 200. The semiconductor device 10D differs from the semiconductor device 10 shown in Figure 1B, etc., in that it does not have a metal oxide layer 70.

[0253] For example, a first metal oxide film is formed on an insulating layer 105, and the first metal oxide film is processed to form island-shaped semiconductor layers 208. A second metal oxide film is formed on the insulating layer 105 and the semiconductor layer 208. The second metal oxide film is crystallized by heat treatment. Then, the second metal oxide film can be processed to form the semiconductor layer 108.

[0254] During the heat treatment, the semiconductor layer 208 functions as a seed crystal layer. In the region of the second metal oxide film that is in contact with the semiconductor layer 208, crystal nuclei originating from the semiconductor layer 208 are generated in the second metal oxide film, and as these crystal nuclei grow, the second metal oxide film crystallizes. This increases the grain size of the crystal grains contained in the semiconductor layer 108 and reduces the number of grain boundaries. Therefore, a transistor with high field-effect mobility can be achieved. Furthermore, a transistor with high on-current can be achieved. Because the semiconductor layer 208 functions as a seed crystal layer, there is no need to provide seed crystal layers other than the semiconductor layer 208, thus reducing the occupied area of ​​the semiconductor device.

[0255] Figure 10A shows a configuration in which the semiconductor layer 208 is provided on the region 108Q side of the semiconductor layer 108. In this configuration, crystal growth proceeds from the region of the second metal oxide film that is in contact with the semiconductor layer 208 toward the region that becomes the semiconductor layer 108. In other words, crystal growth proceeds from the region 108Q of the semiconductor layer 108 toward the channel formation region.

[0256] Here, a configuration is shown in which crystal growth progresses from region 108Q toward the channel formation region, but the present invention is not limited to this. By providing the semiconductor layer 208 on the region 108P side of the semiconductor layer 108, a configuration can be made in which crystal growth progresses from region 108P toward the channel formation region of the semiconductor layer 108. Furthermore, by providing seed crystal layers on both the region 108P side and the region 108Q side of the semiconductor layer 108, crystal growth can be promoted from region 108P toward the channel formation region of the semiconductor layer 108, as well as from region 108Q toward the channel formation region.

[0257] Although the present invention has shown a configuration in which the seed crystal layer functions as a semiconductor layer of the transistor 200, the present invention is not limited to this configuration. It is also possible to have a configuration in which the seed crystal layer is not used as a component of the transistor.

[0258] Figure 10A shows a configuration in which the seed crystal layer is provided in a direction that extends along the channel length of the semiconductor layer 108, but the present invention is not limited to this. The seed crystal layer can be provided in a direction that extends along the channel width of the semiconductor layer 108.

[0259] Figure 11 shows an example of a configuration different from that shown in Figure 10A. Figure 11 is a top view of a semiconductor device 10E, which is one embodiment of the present invention. For a cross-sectional view of the cross-section along the dashed line A1-A2 shown in Figure 11, refer to Figure 10B.

[0260] The semiconductor device 10E includes transistor 100 and transistor 200. The semiconductor device 10E differs from the semiconductor device 10D shown in Figure 10A in that the semiconductor layer 208 is provided in a direction in which the channel width direction of the semiconductor layer 108 extends.

[0261] In the configuration shown in Figure 11, crystal growth progresses from the region of the second metal oxide film in contact with the semiconductor layer 208 toward the region that becomes the semiconductor layer 108. In other words, crystal growth progresses in the channel width direction of the semiconductor layer 108. This can reduce the number of grain boundaries that intersect the channel length direction of the semiconductor layer 108. As a result, a transistor with high field-effect mobility can be obtained.

[0262] <Example of Manufacturing Method 1> A method for manufacturing a semiconductor device according to one aspect of the present invention will be described. Note that explanations of the materials and formation methods of each element may be omitted if they have already been described.

[0263] Thin films (insulating films, semiconductor films, and conductive films, etc.) that constitute semiconductor devices can be deposited using sputtering, chemical vapor deposition (CVD), vacuum deposition, pulsed laser deposition (PLD), atomic layer deposition (ALD), and other methods. CVD methods include plasma enhanced chemical vapor deposition (PECVD) and thermal CVD. One type of thermal CVD method is metal-organic CVD (MOCVD).

[0264] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed by wet deposition methods such as spin coating, dip coating, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, or knife coating.

[0265] When processing thin films that constitute semiconductor devices, lithography or similar methods can be used. Alternatively, thin films can be processed by nanoimprint lithography, sandblasting, lift-off methods, etc. Furthermore, island-shaped thin films can be directly formed by deposition methods using shielding masks such as metal masks.

[0266] There are two main methods of lithography. One method involves forming a resist mask on the thin film to be processed, then processing the thin film by etching or other means, and finally removing the resist mask. The other method involves forming a photosensitive thin film, then exposing and developing it to process the thin film into the desired shape.

[0267] In lithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture thereof. Other options include ultraviolet light, KrF laser light, or ArF laser light. Exposure can also be performed using immersion lithography. Furthermore, extreme ultraviolet (EUV) light or X-rays can be used as the light source for exposure. An electron beam can also be used instead of the light source. Using extreme ultraviolet light, X-rays, or an electron beam is preferable because it allows for extremely fine processing. Note that a photomask is not required when exposure is performed by scanning a beam such as an electron beam.

[0268] For etching thin films, one or more of the following methods can be used: dry etching, wet etching, and sandblasting.

[0269] Here, an example of a method for manufacturing the semiconductor device 10 shown in Figures 1A to 1C will be explained using Figures 12A to 13E. Figures 12A to 13E show cross-sectional views between the dashed lines A1 and A2 shown in Figure 1A.

[0270] First, an insulating layer 105 is formed on the substrate 102. The insulating layer 105 can preferably be formed using sputtering or PECVD.

[0271] Next, a semiconductor layer 208 and a metal oxide film 208f, which will become the metal oxide layer 70, are formed on the insulating layer 105 (Figure 12A).

[0272] The metal oxide film 208f is preferably deposited by sputtering using a metal oxide target. Alternatively, the metal oxide film 208f is preferably deposited by the ALD method. The ALD method allows for easy control of the deposition rate, enabling the deposition of thin films with good yield. Therefore, the ALD method is particularly suitable when the metal oxide film 208f is thin. Furthermore, the CVD method can be used to deposit the metal oxide film 208f.

[0273] It is preferable that the metal oxide film 208f be a dense film with as few defects as possible. Furthermore, it is preferable that the metal oxide film 208f is a high-purity film with as few hydrogen element impurities as possible. In particular, it is preferable to use a crystalline metal oxide film as the metal oxide film 208f.

[0274] It is preferable to use oxygen gas when forming the metal oxide film 208f. By using oxygen gas, oxygen can be suitably supplied to the insulating layer 105. For example, when an oxide or oxidized nitride is used for the insulating layer 105, oxygen can be suitably supplied to the insulating layer 105.

[0275] By supplying oxygen to the insulating layer 105, oxygen is supplied to the semiconductor layer 108 and semiconductor layer 208 in subsequent processes, eliminating oxygen deficiencies and V in the semiconductor layer 108 and semiconductor layer 208. Ｏ H can be reduced.

[0276] When forming the metal oxide film 208f, a mixture of oxygen gas and an inert gas (e.g., helium gas, argon gas, xenon gas, etc.) can be used. The higher the ratio of oxygen gas flow rate to the total deposition gas (hereinafter also referred to as the oxygen flow rate ratio) or the oxygen partial pressure, the higher the crystallinity of the metal oxide film can be, resulting in a more reliable transistor. Conversely, a lower oxygen flow rate ratio or oxygen partial pressure results in a metal oxide film with lower crystallinity and higher electrical conductivity, allowing for a transistor with a larger on-current.

[0277] The higher the substrate temperature during metal oxide film deposition, the higher the crystallinity and density of the resulting metal oxide film. This allows for the creation of highly reliable transistors. Conversely, the lower the substrate temperature, the lower the crystallinity and the higher the electrical conductivity of the resulting metal oxide film. This allows for the creation of transistors with high on-current.

[0278] The substrate temperature during the deposition of the metal oxide film 208f is preferably between room temperature (e.g., 25°C) and 250°C, more preferably between room temperature and 200°C, and even more preferably between room temperature and 140°C. For example, setting the substrate temperature to between room temperature and 140°C is preferable because it increases productivity. Furthermore, crystallinity can be reduced by depositing the metal oxide film at room temperature or without heating the substrate.

[0279] By increasing the crystallinity of the metal oxide film 208f, the crystallinity of the metal oxide layer 70 can be increased. This increased crystallinity of the metal oxide layer 70 is preferable because it promotes the crystallization of the semiconductor layer 108 during subsequent formation.

[0280] When using the ALD method, it is preferable to use a film deposition method such as the thermal ALD method or the PEALD (Plasma Enhanced ALD) method. The thermal ALD method is preferred because it exhibits extremely high coverage. The PEALD method is preferred because, in addition to exhibiting high coverage, it allows for low-temperature film deposition.

[0281] Metal oxide films can be formed, for example, by the ALD method using a precursor containing the constituent metal elements and an oxidizing agent.

[0282] For example, when forming an In-Ga-Zn oxide film, three precursors can be used: one containing indium, one containing gallium, and one containing zinc. Alternatively, two precursors can be used: one containing indium, and two containing gallium and zinc.

[0283] Examples of indium precursors include triethylindium, trimethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionic acid)indium, cyclopentadienylindium, indium(III) chloride, [3-(dimethylamino)propyl]dimethylindium, and [1,1,1-trimethyl-N-(trimethylsilyl)amide]-indium.

[0284] Examples of gallium-containing precursors include trimethylgallium, triethylgallium, gallium trichloride, tris(dimethylamide)gallium(III), gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionic acid)gallium, dimethylchlorogallium, and diethylchlorogallium.

[0285] Examples of aluminum-containing precursors include aluminum chloride and trimethylaluminum.

[0286] Examples of tin-containing precursors include tin(IV) chloride and tetrakis(dimethylamide)tin.

[0287] Examples of zinc-containing precursors include dimethylzinc, diethylzinc, bis(2,2,6,6-tetramethyl-3,5-heptanedionic acid) zinc, and zinc chloride.

[0288] Examples of oxidizing agents include ozone, oxygen, and water.

[0289] Methods for controlling the composition of the resulting film include adjusting one or more of the type of raw material gas, the flow rate ratio of the raw material gases, the duration for which the raw material gases are flowed, and the order in which the raw material gases are flowed. By adjusting these factors, the composition of the metal oxide film 208f can be controlled. Furthermore, by adjusting these factors, it is also possible to deposit a metal oxide film 208f with a continuously changing composition.

[0290] Before forming the metal oxide film 208f, it is preferable to perform at least one of the following: a treatment to desorb water, hydrogen, and organic matter adsorbed on the surface of the insulating layer 105, and a treatment to supply oxygen into the insulating layer 105. For example, a heat treatment can be performed in a reduced-pressure atmosphere at a temperature of 70°C to 200°C. Alternatively, a plasma treatment can be performed in an oxygen-containing atmosphere. Alternatively, nitrous oxide (N) can be used. ２Plasma treatment in an atmosphere containing an oxidizing gas such as 0) can supply oxygen to the insulating layer 105. Plasma treatment in an atmosphere containing nitrous oxide gas can suitably remove organic matter from the surface of the insulating layer 105 while supplying oxygen. After such treatment, it is preferable to continuously deposit a metal oxide film 208f without exposing the surface of the insulating layer 105 to the atmosphere.

[0291] Furthermore, when the semiconductor layer 208 is in a stacked structure, it is preferable to deposit the metal oxide film to be deposited first, and then continuously deposit the next metal oxide film without exposing its surface to the atmosphere.

[0292] When the semiconductor layer 208 is a stacked structure, all layers constituting the semiconductor layer 208 can be deposited using the same method (for example, sputtering or ALD). Alternatively, different deposition methods can be used for each layer. For example, a stacked structure can be formed with a metal oxide layer deposited by sputtering and a metal oxide layer deposited by ALD.

[0293] Next, the metal oxide film 208f is processed into island shapes to form the semiconductor layer 208 and the metal oxide layer 70 (Figure 12B).

[0294] The semiconductor layer 208 and the metal oxide layer 70 can be suitably formed using a wet etching method. In this case, a portion of the insulating layer 105 in areas that do not overlap with either the semiconductor layer 208 or the metal oxide layer 70 may be etched, resulting in a reduction in its thickness.

[0295] It is preferable to perform a heat treatment after the metal oxide film 208f has been formed, or after the metal oxide film 208f has been processed into a semiconductor layer 208 and a metal oxide layer 70. The heat treatment can remove impurities (e.g., hydrogen and water) contained in the metal oxide film 208f, or in the semiconductor layer 208 and metal oxide layer 70, or adsorbed on the surface.

[0296] Heat treatment may improve the film quality of the metal oxide film 208f, or the semiconductor layer 208 and the metal oxide layer 70 (for example, reducing defects or increasing crystallinity). The increased crystallinity of the metal oxide layer 70 is preferable because it promotes the crystallization of the semiconductor layer 108 during its subsequent formation.

[0297] By heat treatment, oxygen can also be supplied from the insulating layer 105 to the metal oxide film 208f, or to the semiconductor layer 208 and the metal oxide layer 70.

[0298] Note that this heat treatment may be omitted if it is not necessary. Alternatively, the heat treatment at this stage can be omitted and combined with a heat treatment performed in a later step. Furthermore, a heat treatment in a later step (e.g., a film formation process) may also serve as this heat treatment.

[0299] Next, a metal oxide film 108f, which will become the semiconductor layer 108, is formed on the insulating layer 105, the semiconductor layer 208, and the metal oxide layer 70 (Figure 12C).

[0300] The metal oxide film 108f can be formed using the method described for forming the metal oxide film 208f.

[0301] When forming the metal oxide film 108f, it is preferable to use conditions that result in low crystallinity of the metal oxide film 108f. By performing a heat treatment after forming the metal oxide film 108f with low crystallinity to induce crystallization, the grain size can be increased. However, if the number of grains contained in the metal oxide film 108f is large at the stage of film formation, the grain size of the grains after heat treatment may become small. Therefore, it is preferable that the number of grains contained in the metal oxide film 108f is small at the stage of film formation, and that the crystallinity of the metal oxide film 108f is low. Furthermore, by using conditions that result in low crystallinity of the metal oxide film 108f, it is also possible to suppress the formation of spontaneous nuclei in the metal oxide film 108f at the stage of film formation. This reduces the number of grains caused by spontaneous nuclei. Therefore, the grain size of the grains after heat treatment can be increased.

[0302] When forming the metal oxide film 108f, it is preferable to use a gas containing hydrogen (for example, hydrogen or water). This reduces the number of crystal grains generated during the formation of the metal oxide film 108f, resulting in a metal oxide film 108f with low crystallinity. When forming the metal oxide film 108f, a mixture of hydrogen gas and an inert gas can be used. For example, the ratio of the hydrogen gas flow rate to the total deposition gas when forming the metal oxide film 108f (hereinafter also referred to as the hydrogen flow rate ratio) is preferably higher than 0% and 30% or less, more preferably higher than 0% and 20% or less, more preferably higher than 0% and 15% or less, and more preferably higher than 0% and 10% or less. However, the hydrogen flow rate ratio in the formation of the metal oxide film 108f is not limited to the above range.

[0303] By using oxygen gas when forming the metal oxide film 108f, the occurrence of oxygen vacancies in the metal oxide film 108f can be suppressed. Furthermore, oxygen can be supplied to the insulating layer 105 during the formation of the metal oxide film 108f. This allows oxygen to be supplied to the semiconductor layer 108 in subsequent processes, thereby suppressing oxygen vacancies and V2 in the semiconductor layer 108. Ｏ H can be reduced. When forming the metal oxide film 108f, oxygen gas and an inert gas can be used in mixture form. On the other hand, if the oxygen flow rate ratio when forming the metal oxide film 108f is high, there is a risk that the number of crystal grains contained in the metal oxide film 108f will increase at the stage when the metal oxide film 108f is formed. The oxygen flow rate ratio when forming the metal oxide film 108f is preferably higher than 0% and 10% or less, more preferably higher than 0% and 5% or less, and even more preferably higher than 0% and 3% or less. By setting the oxygen flow rate ratio within the above range, oxygen vacancies and V in the semiconductor layer 108 can be reduced. Ｏ This method can reduce H and lower the crystallinity of the metal oxide film 108f. Note that the oxygen flow rate ratio during the deposition of the metal oxide film 108f is not limited to the aforementioned range.

[0304] A mixture of hydrogen gas, oxygen gas, and an inert gas can be used as the film-forming gas for the metal oxide film 108f. Typically, oxygen gas, hydrogen gas, and argon gas can be suitably used as the film-forming gas for the metal oxide film 108f. The oxygen flow rate ratio and hydrogen flow rate ratio are preferably within the aforementioned ranges. This makes it possible to lower the crystallinity of the metal oxide film 108f and increase the grain size of the crystal grains after heat treatment. Furthermore, oxygen vacancies and V in the semiconductor layer 108 can be reduced. Ｏ H can be reduced. Note that the oxygen flow rate ratio and hydrogen flow rate ratio in the deposition of the metal oxide film 108f are not limited to the ranges mentioned above.

[0305] It is preferable to use a low substrate temperature when depositing the metal oxide film 108f. This allows for a lower crystallinity of the metal oxide film 108f. The substrate temperature during the deposition of the metal oxide film 108f is preferably between room temperature and 150°C, more preferably between room temperature and 100°C, more preferably between room temperature and 80°C, and more preferably between room temperature and 50°C. In particular, it is preferable to deposit the metal oxide film 108f at room temperature or without heating the substrate. However, the substrate temperature during the deposition of the metal oxide film 108f is not limited to the above range.

[0306] Here, it is preferable that the metal oxide film 108f has low crystallinity, and that the metal oxide film 208f has high crystallinity. Therefore, the substrate temperature when depositing the metal oxide film 208f can be higher than the substrate temperature when depositing the metal oxide film 108f. The oxygen flow rate ratio when depositing the metal oxide film 208f can be higher than the oxygen flow rate ratio when depositing the metal oxide film 108f. Also, as mentioned above, the metal oxide film 108f can be deposited using hydrogen gas. On the other hand, the metal oxide film 208f can be deposited without using hydrogen gas. In other words, it can be said that the hydrogen flow rate ratio when depositing the metal oxide film 108f can be higher than the hydrogen flow rate ratio when depositing the metal oxide film 208f. Note that the present invention is not limited to this, and the substrate temperature when depositing the metal oxide film 208f can be lower than or the same as the substrate temperature when depositing the metal oxide film 108f. The oxygen flow rate ratio when depositing the metal oxide film 208f can be lower than or the same as the oxygen flow rate ratio when depositing the metal oxide film 108f. The hydrogen flow rate ratio when depositing the metal oxide film 108f can be lower than or the same as the hydrogen flow rate ratio when depositing the metal oxide film 208f.

[0307] When using the ALD method, it is preferable to use a film deposition method such as the thermal ALD method or the PEALD method.

[0308] The metal oxide film 108f can be formed, for example, by the ALD method using a precursor containing the constituent metal elements and an oxidizing agent. For details on the oxidizing agent, please refer to the previous description.

[0309] For example, when forming an indium oxide film, an indium-containing precursor can be used. Information on indium-containing precursors can be found in the previous description.

[0310] Before forming the metal oxide film 108f, it is preferable to perform at least one of the following: a treatment to desorb water, hydrogen, and organic matter adsorbed on the surface of the insulating layer 105, and a treatment to supply oxygen into the insulating layer 105. Details of these treatments can be found in the above description.

[0311] Next, the metal oxide film 108f is processed into an island shape to form the metal oxide layer 108F (Figure 12D). When indium oxide is used for the semiconductor layer 108, the metal oxide film 108f and the metal oxide layer 108F can be referred to as the indium oxide layer or indium oxide film.

[0312] The metal oxide layer 108F can be suitably formed using a wet etching method. In this process, a portion of the metal oxide layer 108F with low crystallinity is removed by etching, while the semiconductor layer 208 and metal oxide layer 70 with high crystallinity remain. In some cases, a portion of the area of ​​the metal oxide layer 70 that does not overlap with the metal oxide layer 108F may be etched, resulting in a reduction in the thickness of that area (see Figures 6A and 6B). Similarly, the thickness of the semiconductor layer 208 may be reduced. In such cases, it is preferable to increase the thickness of the metal oxide film 208f to achieve the desired semiconductor layer 208. Furthermore, a portion of the area of ​​the insulating layer 105 that does not overlap with the metal oxide layer 108F may be etched, resulting in a reduction in the thickness of that area. In the etching of the metal oxide film 108f, using a material with a high selectivity ratio for the insulating layer 105 can suppress the reduction in the thickness of the insulating layer 105.

[0313] Next, a heat treatment is performed. The heat treatment causes the metal oxide layer 108F to crystallize, forming the semiconductor layer 108 (Figure 12E). The heat treatment causes crystal growth of the crystal grains that originated from the seed crystal layer. This makes it possible to increase the particle size of the crystal grains contained in the semiconductor layer 108 and reduce the number of crystal grain boundaries.

[0314] The heat treatment temperature is preferably 100°C to 650°C, more preferably 100°C to 550°C, more preferably 100°C to 450°C, more preferably 100°C to 350°C, more preferably 100°C to 300°C, more preferably 100°C to 250°C, and more preferably 150°C to 250°C. The heat treatment can be carried out in an atmosphere containing one or more noble gases, nitrogen, or oxygen. Dry air (CDA: Clean Dry Air) can be used as the nitrogen-containing atmosphere or the oxygen-containing atmosphere. It is preferable that the content of hydrogen, water, etc. in the atmosphere be kept as low as possible. It is preferable to use a high-purity gas with a dew point of -60°C or lower, preferably -100°C or lower, as the atmosphere. By using an atmosphere with minimal hydrogen and water content, it is possible to prevent hydrogen and water from being incorporated into the semiconductor layer 108, semiconductor layer 208, metal oxide layer 70, and insulating layer 105 as much as possible. Furthermore, by performing heat treatment in an oxygen-containing atmosphere, it may be possible to enhance effects such as reducing defects in semiconductor layer 108 and semiconductor layer 208, and increasing the grain size of the crystal grains in semiconductor layer 108. For example, the heat treatment can be performed using an oven or a rapid thermal annealing (RTA) device. Using an RTA device can shorten the heat treatment time.

[0315] If the heat treatment temperature is too high, spontaneous nuclei are more likely to form, and crystal growth of these spontaneous nuclei will also proceed more easily. On the other hand, if the heat treatment temperature is too low, the rate of crystal growth of crystal grains originating from the seed crystal layer will slow down, which may reduce the productivity of semiconductor devices. By setting the heat treatment temperature within the aforementioned range, it is possible to suppress the formation of spontaneous nuclei and the crystal growth of these spontaneous nuclei, while accelerating the rate of crystal grain growth. Note that the heat treatment temperature is not limited to the aforementioned range.

[0316] In this way, a metal oxide film 108f with low crystallinity is formed, and the metal oxide film 108f is processed into island-shaped metal oxide layers 108F. Then, by crystallizing the metal oxide layers 108F through heat treatment, a semiconductor layer 108 can be obtained. Since the metal oxide film 108f can be processed into island shapes at a low crystallinity stage, processing becomes easier, and the productivity of semiconductor devices can be increased. However, the present invention is not limited to this embodiment, and a semiconductor layer 108 can be formed by forming a metal oxide film 108f with low crystallinity, crystallizing the metal oxide film 108f through heat treatment, and then processing it into island shapes.

[0317] By heat treatment, oxygen can also be supplied from the insulating layer 105 to the semiconductor layer 108 and the semiconductor layer 208.

[0318] Note that heat treatment is not performed at this stage, and can be combined with heat treatment performed in a later step. Furthermore, a heat treatment in a later step (for example, a film formation process) may also serve as this heat treatment.

[0319] Next, an insulating film 106f is formed to cover the semiconductor layer 108, semiconductor layer 208, metal oxide layer 70, and insulating layer 105, forming the insulating layer 106 (Figure 12F). The insulating film 106f can be formed using, for example, the PECVD method, sputtering method, or ALD method.

[0320] When oxide semiconductors are used for semiconductor layer 108 and semiconductor layer 208, it is preferable that the insulating layer 106 functions as a barrier film that suppresses the diffusion of oxygen. By having the function of the insulating layer 106 that suppresses the diffusion of oxygen, the desorption of oxygen from semiconductor layer 108 and semiconductor layer 208 is suppressed, and oxygen deficiencies (V) are prevented in semiconductor layer 108 and semiconductor layer 208. Ｏ This suppresses the increase of ). Furthermore, the diffusion of oxygen from semiconductor layer 108 and semiconductor layer 208 to conductive layer 104 and conductive layer 204 via insulating layer 106 is suppressed, thereby suppressing oxidation of conductive layer 104 and conductive layer 204. As a result, a transistor with good electrical characteristics and high reliability can be made.

[0321] By increasing the temperature during the deposition of the insulating film 106f, a gate insulating layer with fewer defects can be obtained. However, if the temperature during the formation of the insulating film 106f is high, oxygen will be desorbed from the semiconductor layer 108, resulting in oxygen deficiencies and V in the semiconductor layer 108 and the semiconductor layer 208. Ｏ In some cases, the amount of H may increase. The substrate temperature when forming the insulating layer 106 is preferably 180°C to 450°C, more preferably 200°C to 450°C, more preferably 250°C to 450°C, more preferably 300°C to 450°C, and more preferably 300°C to 400°C. By setting the substrate temperature when forming the insulating film 106f within the above range, defects in the insulating layer 106 can be reduced, and the detachment of oxygen from the semiconductor layer 108 and semiconductor layer 208 can be suppressed. Therefore, a transistor with good electrical characteristics and high reliability can be obtained.

[0322] Before depositing the insulating film 106f, the surfaces of the semiconductor layer 108 and semiconductor layer 208 can be subjected to plasma treatment. This plasma treatment can reduce impurities such as water adsorbed on the surfaces of the semiconductor layer 108 and semiconductor layer 208. This reduces impurities at the interface between the semiconductor layer 108 and semiconductor layer 208 and the insulating layer 106, enabling the realization of a highly reliable transistor. This is particularly suitable when the surfaces of the semiconductor layer 108 and semiconductor layer 208 are exposed to the atmosphere between the formation of the semiconductor layer 108 and semiconductor layer 208 and the deposition of the insulating film 106f. The plasma treatment can be performed in an atmosphere such as oxygen, ozone, nitrogen, nitrous oxide, or argon. Furthermore, it is preferable that the plasma treatment and the deposition of the insulating film 106f are performed continuously without exposure to the atmosphere.

[0323] After the insulating film 106f is formed, oxygen can be supplied to the insulating film 106f. As a method of supplying oxygen, for example, ion implantation or plasma treatment can be used. As the plasma treatment, a device that turns a gas into plasma using high-frequency power can be suitably used. Examples of devices that turn a gas into plasma using high-frequency power include a PECVD device, a plasma etching device, and a plasma ashing device. Plasma treatment is preferably carried out in an atmosphere containing oxygen. For example, oxygen, nitrous oxide (N) ２ O), Nitrogen dioxide (NO) ２ It is preferable to perform the plasma treatment in an atmosphere containing one or more of the following: carbon monoxide and carbon dioxide. The amount of oxygen supplied can be adjusted, for example, by the power and treatment time in the plasma treatment.

[0324] It is preferable to deposit a film 139 on the insulating film 106f (Figure 13A). Sputtering is preferably used to deposit the film 139. By depositing the film 139 in an oxygen-containing atmosphere, oxygen can be supplied to the insulating film 106f.

[0325] The conductivity of the film 139 is not a requirement. At least one of an insulating film, a semiconductor film, and a conductive film can be used as the film 139. For example, the film 139 can be aluminum oxide, hafnium oxide, hafnium aluminate, indium oxide, ITO, or ITSO.

[0326] The film 139 preferably uses an oxide material containing one or more of the same elements as the semiconductor layer 108 or semiconductor layer 208. In particular, it is preferable to use an oxide semiconductor material applicable to the semiconductor layer 108 or semiconductor layer 208.

[0327] When forming the film 139, the higher the oxygen flow rate ratio of the film-forming gas introduced into the processing chamber of the film-forming apparatus, or the higher the oxygen partial pressure in the processing chamber, the greater the amount of oxygen supplied to the insulating film 106f. The oxygen flow rate ratio is preferably 50% to 100%, more preferably 60% to 100%, more preferably 70% to 100%, more preferably 80% to 100%, and more preferably 90% to 100%. In particular, an oxygen flow rate ratio of 100% is preferred. Note that the oxygen flow rate ratio can be interpreted as the ratio of the oxygen partial pressure to the pressure in the processing chamber.

[0328] Thus, by forming the film 139 by sputtering in an oxygen-containing atmosphere, oxygen can be supplied to the insulating film 106f during the formation of the film 139, while preventing oxygen from being released from the insulating film 106f. As a result, a large amount of oxygen can be trapped in the insulating film 106f. Then, a large amount of oxygen can be supplied to the semiconductor layer 108 and semiconductor layer 208 by subsequent heat treatment. As a result, oxygen vacancies and V2 in the semiconductor layer 108 and semiconductor layer 208 can be reduced. Ｏ This allows for a reduction in H, resulting in a transistor that exhibits good electrical characteristics and is highly reliable.

[0329] It is preferable to perform a heat treatment after forming the film 139. By performing a heat treatment after forming the film 139, oxygen can be effectively supplied from the insulating film 106f to the semiconductor layer 108 and the semiconductor layer 208.

[0330] The heat treatment temperature is preferably 150°C or higher and below the strain point of the substrate, more preferably 200°C to 450°C, more preferably 250°C to 450°C, more preferably 300°C to 450°C, more preferably 300°C to 400°C, and more preferably 350°C to 400°C. The heat treatment can be carried out in an atmosphere containing one or more noble gases, nitrogen, or oxygen. Dry air (CDA) can be used as the nitrogen-containing atmosphere or the oxygen-containing atmosphere. It is preferable that the content of hydrogen, water, etc. in the atmosphere be kept to a minimum. It is preferable to use a high-purity gas with a dew point of -60°C or lower, preferably -100°C or lower, as the atmosphere. By using an atmosphere with a minimum content of hydrogen, water, etc., it is possible to prevent hydrogen, water, etc. from being incorporated into the insulating film 106f as much as possible. The heat treatment can be carried out using an oven, RTA device, etc.

[0331] After the film 139 is formed, or after the aforementioned heat treatment, oxygen can be supplied to the insulating film 106f via the film 139. For example, ion implantation or plasma treatment can be used as methods for supplying oxygen. A detailed explanation of plasma treatment is omitted here, as it can be found in the previous description.

[0332] Next, the film 139 is removed. Removing the film 139 exposes the insulating film 106f. There are no particular limitations on the method for removing the film 139, but a wet etching method can be preferably used. By using a wet etching method, etching of the insulating film 106f during the removal of the film 139 can be suppressed. This prevents the thickness of the insulating film 106f from becoming thinner, and the thickness of the insulating layer 106 can be made uniform.

[0333] The process of supplying oxygen to the insulating film 106f is not limited to the methods described above. For example, oxygen radicals, oxygen atoms, oxygen atom ions, or oxygen molecular ions can be supplied to the insulating film 106f by ion implantation or plasma treatment. Alternatively, a film that suppresses oxygen desorption can be formed on the insulating film 106f, and then oxygen can be supplied to the insulating film 106f through this film. It is preferable to remove the film after supplying oxygen. As the film that suppresses oxygen desorption mentioned above, a conductive film or semiconductor film having one or more of indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, and tungsten can be used.

[0334] Next, a conductive film is formed on the insulating film 106f, and resist masks 192a and 192b are formed on the conductive film. The resist mask 192a is provided at the position where the conductive layer 104 is formed, and the resist mask 192b is provided at the position where the conductive layer 204 is formed. Then, the conductive film is processed using the resist masks 192a and 192b as masks to form the conductive layer 104 and the conductive layer 204 (Figure 13B). The conductive film can be formed by, for example, sputtering, thermal CVD (including MOCVD), or ALD.

[0335] Next, using the resist mask 192a and conductive layer 104, and the resist mask 192b and conductive layer 204 as masks, impurities 190 are supplied (also called added or injected) to the semiconductor layer 108 and semiconductor layer 208. As a result, regions 108P and 108Q are formed in the region of semiconductor layer 108 that does not overlap with the conductive layer 104, and regions 208P and 208Q are formed in the region of semiconductor layer 208 that does not overlap with the conductive layer 204 (Figure 13C). At this time, it is preferable to determine the conditions for supplying impurities by considering the materials and thicknesses of the resist mask 192a and conductive layer 104, and the resist mask 192b and conductive layer 204, so as to minimize the supply of impurities 190 to the region of semiconductor layer 108 that overlaps with the conductive layer 104, and the region of semiconductor layer 208 that overlaps with the conductive layer 204. This makes it possible to form channel-forming regions with sufficiently reduced impurity concentrations in the region of the semiconductor layer 108 that overlaps with the conductive layer 104, and in the region of the semiconductor layer 208 that overlaps with the conductive layer 204.

[0336] Figure 13C schematically shows, with arrows, how impurities 190 are supplied to semiconductor layers 108 and 208. Although Figure 13C shows a configuration in which impurities 190 are supplied to semiconductor layer 108 via an insulating film 106f, the present invention is not limited to this. For example, in semiconductor device 10A shown in Figure 8A and semiconductor device 10B shown in Figure 8C, impurities are supplied to regions 108P and 108Q, and regions 208P and 208Q without going through the insulating layer 106. Also, in semiconductor device 10B, impurities are supplied to regions 108R, 108S, 208R and 208S via the insulating layer 106.

[0337] Next, resist masks 192a and 192b are removed.

[0338] In Figure 13C, a configuration is shown in which impurities 190 are supplied using the resist mask 192a and conductive layer 104, and the resist mask 192b and conductive layer 204 as masks. However, the present invention is not limited to this configuration. It is also possible to supply impurities 190 using the conductive layer 104 and conductive layer 204 as masks after removing the resist masks 192a and 192b.

[0339] Next, an insulating film 195f is formed to cover the conductive layer 104, conductive layer 204, insulating layer 106, semiconductor layer 108, and semiconductor layer 208, forming the insulating layer 195 (Figure 13D). The insulating film 195f can preferably be formed using the PECVD method.

[0340] If the deposition temperature of the insulating film 195f is too high, impurities contained in regions 108P and 108Q may diffuse into the peripheral region of the semiconductor layer 108, including the channel formation region. Furthermore, the electrical resistance of regions 108P and 108Q may increase. The same applies to regions 208P and 208Q. Therefore, it is preferable to determine the deposition temperature of the insulating film 195f considering the diffusion of impurities.

[0341] The deposition temperature for the insulating film 195f is preferably, for example, 150°C to 400°C, more preferably 180°C to 360°C, and more preferably 200°C to 250°C. By depositing the insulating film 195f at a low temperature, a transistor with good electrical characteristics can be obtained even with a short channel length.

[0342] After the formation of the insulating film 195f, a heat treatment can be performed. This heat treatment may lower the electrical resistance of regions 108P, 108Q, 208P, and 208Q. A detailed explanation of the heat treatment is omitted as it can be found in the previous description. Note that if the heat treatment temperature is too high (for example, above 500°C), impurities may diffuse into the channel formation region, potentially leading to a decrease in the electrical characteristics and reliability of the transistor.

[0343] Note that this heat treatment is not required. Furthermore, the heat treatment at this stage can be omitted and combined with a heat treatment performed in a later step. Also, if there is a heat treatment in a later step (e.g., a film formation process), this heat treatment may be combined with that step.

[0344] Next, portions of the insulating film 195f and insulating film 106f are removed to form openings 147a, 147b, 247a, and 247b (Figure 13E). This forms the insulating layer 195 and the insulating layer 106. For example, a dry etching method can be preferably used to form openings 147a, 147b, 247a, and 247b.

[0345] Next, conductive layers 112a, 112b, 212a, and 212b are formed to cover openings 147a, 147b, 247a, and 247b (Figure 1B).

[0346] By following the above steps, a semiconductor device 10 according to one aspect of the present invention can be manufactured.

[0347] <Example of Manufacturing Method 2> Here, an example of a manufacturing method for the semiconductor device 10D shown in Figures 10A and 10B will be explained using Figures 14A to 14E. Figures 14A to 14E show a cross-sectional view between the dashed line A1 and A2 shown in Figure 10A. Note that explanations of parts that overlap with the aforementioned Example of Manufacturing Method 1 may be omitted.

[0348] First, a metal oxide film 208f is formed, similar to the method in example 1 (Figure 12A).

[0349] Next, the metal oxide film 208f is processed into an island shape to form the semiconductor layer 208 (Figure 14A).

[0350] Next, a metal oxide film 108f is formed on the insulating layer 105 and the semiconductor layer 208 (Figure 14B).

[0351] Next, a heat treatment is performed. Due to the heat treatment, the metal oxide film 108f crystallizes, and the metal oxide film 108G is formed (Figure 14C).

[0352] Next, the metal oxide film 108G is processed into an island shape to form a semiconductor layer 108 (Figure 14D).

[0353] Next, an insulating film 106f is formed to cover the semiconductor layer 108, the semiconductor layer 208, and the insulating layer 105 (Figure 14E). For the process after the formation of the insulating film 106f, please refer to the description in Figures 12B to 13E.

[0354] By following the above steps, a semiconductor device 10D according to one aspect of the present invention can be manufactured.

[0355] This embodiment can be combined with other embodiments as appropriate.

[0356] (Embodiment 2) This embodiment describes an indium oxide film that can be used in the semiconductor layer of a transistor in a display device according to one aspect of the present invention.

[0357] In this specification, indium oxide having at least a crystalline portion or crystalline region in the film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystal IO or crystalline IO include single-crystal indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0358] Indium oxide is a semiconductor material with completely different physical properties from oxide semiconductors such as In-Ga-Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0359] The carrier concentration dependence of the hole (Hall) mobility of indium oxide, silicon, and IGZO is described. Figure 15A shows silicon (Si) and indium oxide (InO Ｘ Figure 15B is a schematic diagram of the carrier concentration dependence of hole mobility with respect to IGZO.

[0360] First, as indicated by the arrows in Figure 15B, IGZO tends to show higher hole mobility as the carrier concentration increases. On the other hand, as indicated by the arrows in Figure 15A, indium oxide tends to show higher hole mobility as the carrier concentration decreases (see Non-Patent Literature 3). This trend is similar to that of silicon, where the lower the concentration of dopants (impurities) in the material, the less impurity scattering occurs and the higher the hole mobility. In other words, the higher the purity and intrinsic nature of indium oxide, the higher its hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to silicon. Note that the properties of indium oxide shown in Figure 15A are assumed to be for a single crystal. Therefore, when indium oxide is not a single crystal (for example, polycrystalline), the properties may differ from those shown in Figure 15A.

[0361] In Figure 15A, the low carrier concentration range R1 exhibits extremely high hole mobility, making it a suitable carrier concentration range for, for example, the channel formation region of a transistor. For example, in the case of indium oxide, the range R1 has a carrier concentration of 1 × 10⁻⁶. １５ cm −３ This range includes, for example, 1 × 10 １４ cm −３ The above is 1 x 10 １８ cm −３ The range is as follows: By sufficiently reducing the carrier concentration, the hole mobility value can be increased to 270 cm⁻¹. ２ It can be expected to be raised to the level of / (V・s).

[0362] In indium oxide, the region where the carrier concentration is in the range R1 may contain elements that lower the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Other elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0363] On the other hand, the range R2 with high carrier concentration has low electrical resistance and can be said to be a suitable range of carrier concentration for applications such as the source and drain regions of a transistor, or for resistors or transparent conductive films. The range R2 is when the carrier concentration value is 1 × 10⁻⁶. ２０ cm −３ This range includes, for example, 1 × 10 １９ cm −３ The above is 1 x 10 ２２ cm −３ The range is as follows: By making the carrier concentration sufficiently high, the resistivity can be increased to 1 × 10⁻⁶. −４ It is expected that the level can be reduced to below Ω·cm.

[0364] In indium oxide, the region where the carrier concentration is in the range R2 may contain elements that increase the carrier concentration. For example, it is preferable to include elements common to the source and drain electrodes of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use elements whose oxides are conductive or semiconducting. As for the supply of elements that increase the carrier concentration, methods such as forming a film containing the element and diffusing it, ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment can be used.

[0365] In this way, indium oxide uses regions with low carrier concentrations for the transistor's channel formation region and regions with high carrier concentrations for the transistor's source and drain regions. In other words, indium oxide can be said to be an oxide in which valence electron control is possible. In IGZO, however, strain can form in the source and drain regions due to stress on the electrodes in contact with the IGZO, and n-type regions may be formed. On the other hand, unlike IGZO, indium oxide allows for valence electron control, so it does not require the formation of strain in the film as in IGZO. Less strain in the film is expected to improve reliability. For example, by creating regions with carrier concentrations in the range R1 and range R2 shown in Figure 15A within the indium oxide film, a so-called n-i-n junction (a junction of an n-type region, an i-type region, and an n-type region) can be created. Valence electron control in silicon transistors is generally known. On the other hand, valence electron control in indium oxide transistors is a novel technological concept that would not normally be conceived.

[0366] By applying the above technical concept, the indium oxide transistor described herein has two or more, preferably three or more, more preferably four or more, and most preferably five of the following features (1) to (5): (1) High on-current (in other words, high mobility). (2) Low off-current. (3) Normally off is possible. (4) High reliability. (5) High cutoff frequency (fT). For example, the indium oxide transistor described herein has high mobility, low off-current, and is normally off. This transistor is different from a transistor that is high mobility and normally on.

[0367] In addition, the i-type nature of a semiconductor means that the Fermi level (Ef) and the intrinsic Fermi level (Ei) are the same (Ef = Ei). As shown in Figure 15B, in IGZO, the lower the carrier concentration, the lower the hole mobility. Therefore, when Ef = Ei is reached, there are no carriers left (in other words, the material has properties similar to an insulator), and it may cease to function as a transistor. On the other hand, in indium oxide, as shown in Figure 15A, the lower the carrier concentration, the higher the hole mobility, and when Ef = Ei is reached, the hole mobility is maximized. That is, transistors containing indium oxide can achieve high field-effect mobility by setting Ef = Ei. Furthermore, because transistors containing indium oxide have a low carrier concentration, they tend to be normally off. Therefore, transistors containing indium oxide can be normally off and achieve high field-effect mobility.

[0368] Normally off refers to the state in which no current flows through a transistor when no potential is applied to the gate or when the gate-source voltage is 0V. Normally off can be evaluated using the transistor's threshold voltage (Vth) or shift value (Vsh). Unless otherwise specified, Vth will be calculated using the constant current method. More specifically, Vth is the value of drain current (Id) × channel length (L) ÷ channel width (W) in the transistor's Id-Vg characteristic, where Vth is 1nA (1 × 10⁻¹⁰). −９ Let Vsh be the gate voltage (Vg) when A) is true. Also, Vsh is the tangent to the maximum slope when the drain current (Id) in the Id-Vg characteristic of the transistor is expressed logarithmically, and Id = 1pA (1 × 10⁻¹⁰). −１２ Vg is the gate voltage (Vg) at the intersection with line A), or the Vg at the intersection of the line extrapolated from the two points where the slope of Id is maximized when Id is expressed logarithmically in the transistor's Id-Vg characteristic, and the line where Id = 1 pA. For example, if either or both of Vth and Vsh are zero or positive values, it can be considered a normally-off transistor.

[0369] In transistors containing indium oxide, the film configuration in contact with the indium oxide film is crucial for making the semiconductor i-type, i.e., achieving Ef = Ei. For example, in transistors containing indium oxide, a film configuration can be obtained in which a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in contact with the indium oxide film. This film configuration allows for a semiconductor device that is both Ef = Ei and highly reliable.

[0370] Furthermore, in the above film configuration, oxygen-containing films such as silicon oxide-nitride films, silicon oxide nitride films, aluminum oxide films, and gallium oxide films can be used instead of the silicon oxide film. Also, in the above film configuration, silicon oxide nitride films, silicon oxide nitride films, etc. can be used instead of the silicon nitride film. In addition, the hafnium oxide film located on the indium oxide side of the silicon nitride film functions as a hydrogen gettering site.

[0371] The above film configuration can also be understood as a layered structure consisting of a film that can supply oxygen to the indium oxide film (e.g., a silicon oxide film), a film that can getter hydrogen (e.g., a hafnium oxide film), and a film that suppresses the intrusion of oxygen and hydrogen (e.g., a silicon nitride film), from the indium oxide film side. With this configuration, oxygen deficiencies in the indium oxide film are compensated for by oxygen in the silicon oxide film. In addition, hydrogen in the indium oxide film is captured by the hafnium oxide film through heat treatment or other means. Furthermore, by providing a silicon nitride film, the film configuration becomes one in which oxygen and hydrogen are less likely to enter from the outside. In other words, by adopting the above film configuration, the indium oxide film can be made closer to type i. Therefore, transistors having the above-described indium oxide film have high field-effect mobility and high reliability.

[0372] Next, we will describe indium oxide films applied to transistors. Indium oxide films are preferably crystalline (i.e., they have crystal grains). Examples of films with crystal grains include single-crystal films, polycrystalline films, or amorphous films containing crystal grains (also called microcrystalline films). In particular, polycrystalline films are preferred for indium oxide films, and single-crystal films are more preferred. Single-crystal films do not have crystal grain boundaries. Impurities that inhibit carrier flow (typically insulating impurities, insulating oxides, etc.) tend to segregate at crystal grain boundaries. By using single-crystal films, carrier scattering at crystal grain boundaries can be suppressed, enabling the realization of transistors exhibiting high field-effect mobility. Furthermore, it has the excellent effect of suppressing variations in transistor characteristics caused by these crystal grain boundaries.

[0373] Polycrystalline films are preferred over microcrystalline or amorphous films because they can reduce carrier scattering and exhibit high field-effect mobility. When using polycrystalline films, it is preferable to use films with the largest possible grain size and few grain boundaries. In a transistor to which a polycrystalline indium oxide film is applied, if there are no grain boundaries in the channel formation region, or if no grain boundaries are observed, the channel formation region is located within the single-crystal region contained in the polycrystalline film, and therefore it can be considered a transistor to which single-crystal indium oxide is applied.

[0374] In this specification, a semiconductor layer in which no grain boundaries are observed in the channel-forming region, a semiconductor layer in which the channel-forming region is contained within a single crystal grain, or a semiconductor layer in which the direction of the crystal axes is the same in at least two regions within the channel-forming region can be called a single crystal film. Furthermore, a semiconductor layer in which, within a single crystal grain in the channel-forming region, the direction of other crystal axes changes continuously with respect to a certain crystal axis or crystal orientation as the axis of rotation can also be called a single crystal film.

[0375] The channel formation region refers to the region of the semiconductor layer that overlaps with (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, grain boundaries, crystal axes, and crystal orientation in the channel formation region can be confirmed by cross-sectional observation in the channel length direction of the semiconductor layer (for example, cross-sectional observation including the semiconductor layer, source electrode, and drain electrode).

[0376] The indium oxide film in the channel-forming region is preferable to have a low impurity concentration. Impurities in the indium oxide film in the channel-forming region can act as a scattering source for carriers, and thus can cause a decrease in field-effect mobility. Furthermore, these impurities can also inhibit crystal growth in the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The concentration of these impurities in the indium oxide film is preferably 0.1% or less, and more preferably 0.01% (100 ppm) or less. Note that elements such as carbon and hydrogen may be present in the deposition gas or precursor during film formation, and may remain in the indium oxide film in higher concentrations than the impurities mentioned above.

[0377] Furthermore, the indium oxide film in the channel-forming region may contain elements that can become trivalent cations like indium, as long as their crystals maintain a cubic crystal structure (Bixbite type). Examples include Group 13 elements of the periodic table such as gallium and aluminum, and Group 3 elements of the periodic table. Since these elements mainly exist as trivalent cations in the oxide, the carrier concentration of indium oxide can be kept low.

[0378] By using such an indium oxide film in a transistor, the field-effect mobility of the transistor can be increased to 50 cm². ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm２ It can be set to be... or more per (V·s).

[0379] As one of the characteristics of the indium oxide film, it can be cited that the oxygen permeability (diffusivity) is higher compared to the IGZO film. As shown in FIG. 15C, the oxygen (O) diffusing into the indium oxide film (denoted as InO Ｘ ) penetrates through the indium oxide film and is released as oxygen molecules (O ２ ). Also, by reacting with hydrogen contained in the film, it may be released as water molecules (H ２ O). Further, when there are oxygen vacancies (V Ｏ ) in the film, the diffusing oxygen atoms fill the oxygen vacancies. Since oxygen diffuses easily in the indium oxide film, it can be said that it is easier to fill oxygen vacancies compared to the IGZO film.

[0380] Thus, since the indium oxide film is likely to reduce oxygen vacancies in the film compared to the IGZO film, by applying such an indium oxide film to a transistor, a transistor showing extremely high reliability can be realized.

[0381] As shown in FIG. 15C, the indium oxide film diffuses hydrogen. The hydrogen diffusing into the indium oxide film from the outside penetrates through the indium oxide film and is released as hydrogen molecules (H ２ ). Or, by reacting with oxygen contained in the film, it is released as water molecules.

[0382] A transistor using an indium oxide film is an accumulation-type transistor with electrons as majority carriers. Assuming that the relaxation time of carriers is a constant value, the smaller the effective mass of electrons (carriers), the higher the electron mobility. That is, by using indium oxide with a small effective mass of electrons in a transistor, the on-current or the field-effect mobility of the transistor can be increased.

[0383] In Table 1, single-crystal indium oxide (here, In ２ O ３)( ) and single-crystalline silicon (Si) show their respective effective masses. As shown in Table 1, indium oxide has the characteristics that the effective mass of electrons is small and the effective mass of holes is large. Also, the effective mass of electrons in indium oxide hardly depends on the crystal orientation. Therefore, by using crystalline indium oxide in a transistor, a transistor with high field-effect mobility and a transistor with high frequency characteristics (also called f characteristics) can be realized. Furthermore, since the effective mass of holes is large, a transistor with an extremely small off-current can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm channel width can be 1 fA (1 × 10 −１５ A) or less, or 1 aA (1 × 10 −１８ A) or less in an environment of 125°C, and 1 aA (1 × 10 −１８ A) or less, or 1 zA (1 × 10 −２１ A) or less at room temperature (25°C). Also, as shown in Table 1, since indium oxide has a smaller effective mass of electrons and a larger effective mass of holes than silicon, there is a possibility of realizing a transistor with higher field-effect mobility and lower off-current than a Si transistor.

[0384]

[0385] This embodiment can be implemented in appropriate combination with at least some of the other embodiments described in this specification.

[0386] (Embodiment 3) In this embodiment, a display device according to an aspect of the present invention will be described using FIGS. 16A to 23.

[0387] The display device of this embodiment can be a high-resolution display device or a large-screen display device. Therefore, the display device of this embodiment can be used in electronic devices with relatively large screens, such as television equipment, desktop or notebook computers, computer monitors, digital signage, and large game machines such as pachinko machines, as well as in the display units of digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, personal information terminals, and audio playback devices.

[0388] The display device of this embodiment can be a high-definition display device. Therefore, the display device of this embodiment can be used, for example, as a display unit for information terminals (wearable devices) such as wristwatches and bracelets, as well as as a display unit for wearable devices that can be worn on the head, such as VR devices such as head-mounted displays (HMDs) and AR devices such as glasses.

[0389] A semiconductor device according to one aspect of the present invention can be used as a display device or a module having said display device. Examples of modules having said display devices include a module to which a connector such as a flexible printed circuit board (FPC) or TCP (Tape Carrier Package) is attached, and a module on which an integrated circuit (IC) is mounted using the COG (Chip On Glass) method or COF (Chip On Film) method.

[0390] The display device of this embodiment may also function as a touch panel. For example, the display device can be fitted with various detection elements (also called sensor elements) that can detect the proximity or contact of an object to be detected, such as a finger.

[0391] Examples of sensor types include capacitive, resistive, surface acoustic wave, infrared, optical, and pressure-sensitive sensors.

[0392] As capacitance methods, for example, there are surface capacitance methods and projected capacitance methods. Further, as projected capacitance methods, for example, there are self-capacitance methods and mutual-capacitance methods. Using the mutual-capacitance method is preferable because simultaneous multi-point detection becomes possible.

[0393] As touch panels, for example, there are out-cell types, on-cell types, and in-cell types. Note that an in-cell type touch panel refers to a configuration in which electrodes constituting a detection element are provided on one or both of a substrate supporting a display element and a counter substrate.

[0394] <Example Configuration 1 of Display Device> Fig. 16A shows a perspective view of a display device 50A.

[0395] The display device 50A has a configuration in which a substrate 152 and a substrate 151 are bonded together. In Fig. 16A, the substrate 152 is shown by a dashed line.

[0396] The display device 50A has a display unit 162, a connection unit 140, a circuit unit 164, a conductive layer 165, etc. Fig. 16A shows an example in which an IC 173 and an FPC 172 are mounted on the display device 50A. Therefore, the configuration shown in Fig. 16A can also be referred to as a display module having the display device 50A, an IC, and an FPC.

[0397] The connection unit 140 is provided outside the display unit 162. The connection unit 140 can be provided along one side or a plurality of sides of the display unit 162. The connection unit 140 can be single or plural. Fig. 16A shows an example in which the connection unit 140 is provided so as to surround the four sides of the display unit 162. In the connection unit 140, a common electrode of the display element and the conductive layer are connected, and a potential can be supplied to the common electrode.

[0398] The circuit unit 164 has, for example, a scanning line driving circuit (also referred to as a gate driver). Further, the circuit unit 164 may have both a scanning line driving circuit and a signal line driving circuit (also referred to as a source driver).

[0399] The conductive layer 165 has a function of supplying signals and power to the display unit 162 and the circuit unit 164. The signals and power are input to the conductive layer 165 from the outside via the FPC 172 or input to the conductive layer 165 from the IC 173.

[0400] In FIG. 16A, an example in which the IC 173 is provided on the substrate 151 by the COG method is shown. For the IC 173, for example, an IC having one or both of a scanning line drive circuit and a signal line drive circuit can be applied. Note that the display device 50A and the display module may be configured not to include an IC. Further, the IC may be mounted on the FPC by the COF method or the like.

[0401] The semiconductor device according to one aspect of the present invention can be applied to, for example, one or both of the display unit 162 and the circuit unit 164 of the display device 50A. An oxide semiconductor (OS) can be preferably used for the channel formation region of the transistor included in the display device. By using an OS transistor, a display device with low power consumption can be obtained. Further, the semiconductor device according to one aspect of the present invention can be used for both the display unit 162 and the circuit unit 164, that is, all the transistors included in the display device can be OS transistors. By making all the transistors included in the display device OS transistors in this way, an effect such as suppressing the manufacturing cost can be achieved.

[0402] For example, when the semiconductor device according to one aspect of the present invention is applied to the pixel circuit of the display device, the occupied area of the pixel circuit can be reduced, and a high-definition display device can be obtained. Further, for example, when the semiconductor device according to one aspect of the present invention is applied to a drive circuit (for example, one or both of a gate line drive circuit and a source line drive circuit) of the display device, the occupied area of the drive circuit can be reduced, and a narrow-border display device can be obtained. Further, since the semiconductor device according to one aspect of the present invention has good electrical characteristics, the reliability of the display device can be improved by using it for the display device.

[0403] The display unit 162 is an area for displaying an image in the display device 50A, and has a plurality of pixels 201 arranged periodically. FIG. 16A shows an enlarged view of one pixel 201.

[0404] There are no particular limitations on the pixel arrangement in the display device of this embodiment, and various methods can be applied. Examples of pixel arrangements include stripe arrangements, S-stripe arrangements, matrix arrangements, delta arrangements, Bayer arrangements, and pentile arrangements.

[0405] The pixel 201 shown in Figure 16A has a sub-pixel 11R that emits red light, a sub-pixel 11G that emits green light, and a sub-pixel 11B that emits blue light. The number of sub-pixels that a single pixel has is not particularly limited.

[0406] Each sub-pixel 11R, 11G, and 11B includes a display element and a circuit that controls the driving of the display element.

[0407] Various elements can be used as display elements, such as liquid crystal elements and light-emitting elements. In addition, display elements using shutter-type or optical interference-type MEMS (Micro Electro Mechanical Systems), microcapsule-type, electrophoretic-type, electrowetting-type, or electronic powder fluid (registered trademark)-type may also be used. Furthermore, a QLED (Quantum-dot LED) using a light source and color conversion technology using quantum dot materials may also be used.

[0408] Examples of quantum dot materials used in the color conversion layer include Group 14 elements, Group 15 elements, Group 16 elements, compounds consisting of multiple Group 14 elements, compounds of elements belonging to Groups 4 to 14 and Group 16 elements, compounds of Group 2 elements and Group 16 elements, compounds of Group 13 elements and Group 15 elements, compounds of Group 13 elements and Group 17 elements, compounds of Group 14 elements and Group 15 elements, compounds of Group 11 elements and Group 17 elements, iron oxides, titanium oxides, chalcogenide spinels, and various semiconductor clusters.

[0409] Specifically, cadmium selenide, cadmium sulfide, cadmium telluride, zinc selenide, zinc oxide, zinc sulfide, zinc telluride, mercury sulfide, mercury selenide, mercury telluride, indium arsenide, indium phosphide, gallium arsenide, gallium phosphide, indium nitride, gallium nitride, indium antimonide, gallium antimonide, aluminum phosphide, aluminum arsenide, aluminum antimonide, lead selenide, lead telluride, lead sulfide, indium selenide, telluride Indium sulfide, indium sulfide, gallium selenide, arsenic sulfide, arsenic selenide, arsenic telluride, antimony sulfide, antimony selenide, antimony telluride, bismuth sulfide, bismuth selenide, bismuth telluride, silicon, silicon carbide, germanium, tin, selenium, tellurium, boron, carbon, phosphorus, boron nitride, boron phosphide, boron arsenide, aluminum nitride, aluminum sulfide, barium sulfide, barium selenide, barium telluride, calcium sulfide, gallium selenide Calcium, calcium telluride, beryllium sulfide, beryllium selenide, beryllium telluride, magnesium sulfide, magnesium selenide, germanium sulfide, germanium selenide, germanium telluride, tin sulfide, tin selenide, tin telluride, lead oxide, copper fluoride, copper chloride, copper bromide, copper iodide, copper oxide, copper selenide, nickel oxide, cobalt oxide, cobalt sulfide, iron oxide, iron sulfide, manganese oxide, molybdenum sulfide, vanadium oxide, tungsten oxide, tungsten oxide Examples include carbon dioxide, titanium dioxide, zirconium dioxide, silicon nitride, germanium nitride, aluminum oxide, barium titanate, compounds of selenium, zinc, and cadmium, compounds of indium, arsenic, and phosphorus, compounds of cadmium, selenium, and sulfur, compounds of cadmium, selenium, and tellurium, compounds of indium, gallium, and arsenic, compounds of indium, gallium, and selenium, compounds of indium, selenium, and sulfur, compounds of copper, indium, and sulfur, and combinations thereof. In addition, so-called alloy-type quantum dots, whose composition is expressed in any ratio, may also be used.

[0410] Examples of quantum dot structures include core-type, core-shell-type, and core-multishell-type structures. Furthermore, because quantum dots have a high proportion of surface atoms, they are highly reactive and prone to aggregation. To prevent aggregation and improve solubility in solvents, it is preferable that a protective agent is attached to the surface of the quantum dots, or that protective groups are provided. This also reduces reactivity and improves electrical stability.

[0411] As the size of a quantum dot decreases, its band gap increases, so its size is adjusted appropriately to obtain light of a desired wavelength. As the size decreases, the emission of quantum dots shifts towards the blue side, that is, towards higher energy, so by changing the size of the quantum dots, the emission wavelength can be adjusted across the ultraviolet, visible, and infrared spectral wavelength ranges. The size (diameter) of a quantum dot is, for example, 0.5 nm to 20 nm, preferably 1 nm to 10 nm. Furthermore, the narrower the size distribution of quantum dots, the narrower the emission spectrum becomes, and the better the color purity of the emission can be obtained. The shape of the quantum dots is not particularly limited and may be spherical, rod-shaped, disc-shaped, or other shapes. A quantum rod, which is a rod-shaped quantum dot, has the function of exhibiting directional light.

[0412] Examples of display devices using liquid crystal elements include transmissive liquid crystal display devices, reflective liquid crystal display devices, and semi-transmissive liquid crystal display devices.

[0413] Modes that can be used in display devices using liquid crystal elements include, for example, Vertical Alignment (VA) mode, FFS (Fringe Field Switching) mode, IPS (In-Plane-Switching) mode, TN (Twisted Nematic) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optically Compensated Birefringence) mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (AntiFerroelectric Liquid Crystal) mode, and ECB (Electrically Examples of VA modes include Controlled Birefringence mode and Guest Host mode. Examples of VA modes include MVA (Multi-Domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment) mode, and ASV (Advanced Super View) mode.

[0414] Examples of liquid crystal materials that can be used in liquid crystal elements include thermotropic liquid crystals, low molecular weight liquid crystals, polymer liquid crystals, polymer dispersed liquid crystals (PDLC), polymer network liquid crystals (PNLC), ferroelectric liquid crystals, and antiferroelectric liquid crystals. Depending on the conditions, these liquid crystal materials exhibit cholesteric phases, smectic phases, cubic phases, chiral nematic phases, isotropic phases, blue phases, etc. Furthermore, either positive-type or negative-type liquid crystals may be used as the liquid crystal material, and can be selected according to the applied mode or design.

[0415] Examples of light-emitting elements include self-emissive light-emitting elements such as LEDs (Light Emitting Diodes), OLEDs (Organic LEDs), and semiconductor lasers. For example, mini-LEDs and micro-LEDs can be used as LEDs.

[0416] The light-emitting element can emit light in the following colors: infrared, red, green, blue, cyan, magenta, yellow, or white. Furthermore, the color purity can be improved by adding a microcavity structure to the light-emitting element.

[0417] Of the pair of electrodes in a light-emitting element, one electrode functions as the anode and the other electrode functions as the cathode.

[0418] Furthermore, a display device according to one aspect of the present invention may be any of the following: a top-emission type that emits light in the direction opposite to the substrate on which the light-emitting element is formed; a bottom-emission type that emits light toward the substrate on which the light-emitting element is formed; or a dual-emission type that emits light on both sides.

[0419] Figure 16B is a block diagram illustrating the display device 50A. The display device 50A has a display unit 162 and a circuit unit 164. The display unit 162 has a plurality of periodically arranged pixels 230 (pixels 230[1,1] to pixels 230[m,n], where m and n are each independent integers of 2 or more). The circuit unit 164 has a first drive circuit unit 231 and a second drive circuit unit 232.

[0420] The circuit included in the first drive circuit section 231 functions, for example, as a scan line drive circuit (also called a gate line drive circuit, gate driver, scan driver, or low driver). The circuit included in the second drive circuit section 232 functions, for example, as a signal line drive circuit (also called a source line drive circuit, source driver, data driver, or column driver). Note that some circuit may be provided at a position facing the first drive circuit section 231 across the display section 162. Similarly, some circuit may be provided at a position facing the second drive circuit section 232 across the display section 162.

[0421] The circuit section 164 can utilize various circuits, including shift register circuits, level shifter circuits, inverter circuits, latch circuits, analog switch circuits, demultiplexer circuits, and logic circuits. The circuit section 164 can also utilize transistors and capacitive elements. The transistors in the circuit section 164 can be formed using the same process as the transistors in the pixel 230.

[0422] The display device 50A includes wiring 236, each arranged in parallel or approximately parallel, and whose potential is controlled by a circuit included in the first drive circuit unit 231; and wiring 238, each arranged in parallel or approximately parallel, and whose potential is controlled by a circuit included in the second drive circuit unit 232. Figure 16B shows an example in which wiring 236 and wiring 238 are connected to a pixel 230. However, wiring 236 and wiring 238 are just examples, and the wiring connected to the pixel 230 is not limited to wiring 236 and wiring 238.

[0423] In Figure 16B, the direction in which wiring 236 extends is sometimes referred to as the row direction, and the direction in which wiring 238 extends is sometimes referred to as the column direction. While the horizontal direction in the drawing is generally considered the row direction and the vertical direction the column direction, this is not the only way to represent the row and column directions; they can be interchanged.

[0424] <Example of Pixel Configuration> An example of the configuration of pixel 230 is shown in Figure 17A. Pixel 230 has a pixel circuit 51 and a light-emitting device 61.

[0425] The pixel circuit 51 includes transistors 52A and 52B, and a capacitive element 53. The pixel circuit 51 is a 2Tr1C type pixel circuit having two transistors and one capacitive element. The pixel circuit that can be applied to the display device according to one embodiment of the present invention is not particularly limited.

[0426] The anode of the light-emitting device 61 is connected to one of the source and drain electrodes of transistor 52B and one electrode of the capacitive element 53. The other source and drain of transistor 52B is connected to wiring ANO. The gate of transistor 52B is connected to one of the source and drain electrodes of transistor 52A and the other electrode of the capacitive element 53. The other source and drain of transistor 52A is connected to wiring SL. The gate of transistor 52A is connected to wiring GL. The cathode of the light-emitting device 61 is connected to wiring VCOM.

[0427] Wiring GL corresponds to wiring 236, and wiring SL corresponds to wiring 238. Wiring VCOM is wiring that provides a potential for supplying current to the light-emitting device 61. Transistor 52A has the function of controlling the conduction or non-conduction state between wiring SL and the gate of transistor 52B based on the potential of wiring GL. For example, VDD is supplied to wiring ANO, and VSS is supplied to wiring VCOM. In this specification, etc., potential VDD refers to a power supply potential that is higher than potential VSS. Potential VSS refers to a power supply potential that is lower than potential VDD. Also, the ground potential can be used as VDD or VSS. For example, if VDD is the ground potential, VSS is a potential lower than the ground potential, and if VSS is the ground potential, VDD is a potential higher than the ground potential.

[0428] Transistor 52A functions as a selection transistor to control the selected state of the pixel 230. Transistor 52B functions as a drive transistor to control the amount of current flowing to the light-emitting device 61. Capacitive element 53 has the function of maintaining the gate potential of transistor 52B. The intensity of the light emitted by the light-emitting device 61 is controlled according to the image signal supplied to the gate of transistor 52B.

[0429] A semiconductor device according to an aspect of the present invention can be used for the pixel circuit 51. One or both of the transistors 52A and 52B can preferably use one or more of the aforementioned transistors 100 to 100C and transistors 200 to 200C. For example, for the transistor 52A that requires high-speed operation, any one of the aforementioned transistors 100 to 100C can be preferably used. On the other hand, it is preferable that the transistor 52B has high current controllability. Any one of the transistors 200 to 200C that has high saturation and high current controllability can be preferably used for the transistor 52B. Thereby, a display device with high display quality can be obtained. Also, any one of the transistors 100 to 100C with a large on-current can be preferably used for the transistor 52B. Thereby, the current flowing through the light-emitting device 61 becomes large, and a display device with high brightness can be obtained. [[ID=X]]

[0430] By using a plurality of transistors and capacitor elements in the pixel circuit, a high-performance display device can be obtained. By applying a semiconductor device according to an aspect of the present invention, even if the number of transistors and capacitor elements increases, the occupied area can be reduced, and a high-performance and high-definition display device can be obtained. For example, a display device with a fineness of 300 ppi or more, 500 ppi or more, 1000 ppi or more, 2000 ppi or more, or 3000 ppi or more can be realized.

[0431] Since the semiconductor device according to an aspect of the present invention can reduce the occupied area, the aperture ratio of the pixel in a display device with a bottom emission structure can be increased. For example, a display device with an aperture ratio of 50% or more, 55% or more, or 60% or more can be realized.

[0432] In this specification and the like, the aperture ratio refers to the ratio of the area of the region where light is emitted to the area of the pixel.

[0433] A configuration example different from the pixel 230 shown in FIG. 17A is shown in FIG. 17B. The pixel 230 has a pixel circuit 51A and a light-emitting device 61.

[0434] The pixel circuit 51A differs from the pixel circuit 51 shown in Figure 17A in that the anode of the light-emitting device 61 is connected to the wiring ANO.

[0435] One electrode of the source and drain of transistor 52B, and one electrode of the capacitive element 53, are connected to the wiring VCOM. The cathode of the light-emitting device 61 is connected to the other electrode of the source and drain of transistor 52B.

[0436] In the pixel circuit 51A, the source potential of transistor 52B, which functions as a drive transistor, is equal to the potential of the wiring VCOM. Therefore, fluctuations in the voltage (Vgs) between the gate and source of transistor 52B can be suppressed. Consequently, variations in brightness can be reduced.

[0437] Figure 17C shows an example of a different configuration of the pixel 230 from the one shown in Figure 17A. The pixel 230 has a pixel circuit 51B and a light-emitting device 61.

[0438] Pixel circuit 51B differs from pixel circuit 51 shown in Figure 17A mainly in that it has a transistor 52C. Pixel circuit 51B has transistors 52A, 52B, 52C, and a capacitive element 53. Pixel circuit 51B is a 3Tr1C type pixel circuit having three transistors and one capacitive element.

[0439] One of the source and drain of transistor 52C is connected to one of the source and drain of transistor 52B. The other of the source and drain of transistor 52C is connected to wiring V0. For example, a reference potential is supplied to wiring V0. The gate of transistor 52C is connected to wiring GL.

[0440] Transistor 52C has the function of controlling the conduction or non-conduction state between one of the source and drain electrodes of transistor 52B and the wiring V0 based on the potential of the wiring GL. The reference potential of the wiring V0 provided via transistor 52C can suppress variations in the gate-source potential of transistor 52B.

[0441] The wiring V0 can be used to obtain current values ​​that can be used to set pixel parameters. Specifically, wiring V0 can function as a monitor line to output the current flowing through transistor 52B or the current flowing through light-emitting device 61 to the outside. The current output to wiring V0 can be converted into a voltage by a source follower circuit and output to the outside. Alternatively, it can be converted into a digital signal by an AD converter and output to the outside.

[0442] Back gates can be provided for some or all of the transistors included in the pixel circuit 51. The pixel circuit 51C shown in Figure 17D shows a configuration in which the transistor 52B of the pixel circuit 51 shown in Figure 17A has a back gate, and this back gate is connected to either the source or the drain of the transistor 52B. The pixel circuit 51D shown in Figure 17E shows a configuration in which the transistor 52B of the pixel circuit 51B shown in Figure 17C has a back gate, and this back gate is connected to either the source or the drain of the transistor 52B. This can improve reliability. It is also possible to configure the back gate of transistor 52B to be connected to the gate of transistor 52B. This can increase the on-current of transistor 52B.

[0443] Figure 18A shows an example of a different configuration from the aforementioned pixel 230. The pixel 230 has a pixel circuit 51E and a light-emitting device 61.

[0444] The pixel circuit 51E has transistors M21, M22, M23, and a capacitive element C21. The pixel circuit 51E is a 3Tr1C type pixel circuit having three transistors and one capacitive element. One of the source and drain of transistor M21 is connected to wiring SL. One of the source and drain of transistor M22 is connected to wiring ANO. One of the source and drain of transistor M23 is connected to wiring V0. The other of the source and drain of transistor M21 is connected to the gate of transistor M22 and one electrode of capacitive element C21. The other of the source and drain of transistor M22 is connected to the other of the source and drain of transistor M23, the other electrode of capacitive element C21, and the anode of light-emitting device 61. The cathode of light-emitting device 61 is connected to wiring VCOM.

[0445] The gate of transistor M21 is connected to wiring GL11. The gate of transistor M23 is connected to wiring GL12. By making the wiring to which the gate of transistor M21 is connected different from the wiring to which the gate of transistor M23 is connected, different potentials can be applied to the gates of transistor M21 and transistor M23, allowing these transistors to operate independently.

[0446] Transistor M21 functions as a selector transistor, transistor M22 functions as a drive transistor, and capacitive element C21 has the function of maintaining the gate potential of transistor M22. The intensity of the light emitted by the light-emitting device 61 is controlled according to the image signal supplied to the gate of transistor M22. For transistor M23, refer to the description relating to transistor 52C.

[0447] Figure 18B shows an example of a different configuration from the aforementioned pixel 230. The pixel 230 has a pixel circuit 51F and a light-emitting device 61.

[0448] The pixel circuit 51F has transistors M11, M12, M13, M14, M15, M16, capacitive element C11, and capacitive element C12. The pixel circuit 51F is a 6Tr2C type pixel circuit having six transistors and two capacitive elements.

[0449] The anode of the light-emitting device 61 is connected to one of the source and drain of transistor M15. The cathode of the light-emitting device 61 is connected to the wiring VCOM. The other source and drain of transistor M15 is connected to one of the source and drain of transistor M12, one of the source and drain of transistor M13, one of the source and drain of transistor M16, one electrode of capacitive element C11, and one electrode of capacitive element C12. The gate of transistor M12 is connected to one of the source and drain of transistor M11, the other source and drain of transistor M13, and the other electrode of capacitive element C11. The back gate of transistor M12 is connected to one of the source and drain of transistor M14, and the other electrode of capacitive element C12.

[0450] The source and the other drain of transistor M11 are connected to wiring SL. The source and the other drain of transistor M12 are connected to wiring ANO. The source and the other drain of transistor M14 are connected to wiring V0. The source and the other drain of transistor M16 are connected to wiring V1. For example, a constant potential is supplied to wiring V1. The gates of transistor M11 and transistor M16 are connected to wiring GL1. The gates of transistor M13 and transistor M14 are connected to wiring GL2. The gate of transistor M15 is connected to wiring GL3.

[0451] Transistor M11 functions as a selector transistor that controls the conduction or non-conduction state between the gate of transistor M12 and the wiring SL. Transistor M12 functions as a drive transistor that controls the current flowing to the light-emitting device 61. Transistor M14 has the function of changing the potential supplied from the wiring V0 to a potential corresponding to the threshold voltage of transistor M12 and supplying that potential to the back gate of transistor M12. By supplying a constant potential to the back gate of transistor M12, the threshold voltage can be controlled. Capacitor element C11 has the function of holding the gate potential (potential difference between the gate and source) of transistor M12. Capacitor element C12 has the function of holding the back gate potential (potential difference between the back gate and source) of transistor M12. Pixel circuit 51F has a so-called internal threshold voltage correction function that corrects the threshold voltage of transistor M12 using the back gate. Specifically, capacitor element C12 is made to hold a back gate potential such that the threshold voltage of transistor M12 becomes 0V. This makes it possible to correct the threshold voltage of transistor M12 to be constant at or near 0V, regardless of variations in the transistor's threshold voltage and degradation over time.

[0452] Figure 19A shows an example of a cross-section obtained by cutting a portion of the display device 50A, including the FPC 172, a portion of the circuit section 164, a portion of the display section 162, a portion of the connection section 140, and a portion of the end section.

[0453] The display device 50A shown in Figure 19A has transistors 205D, 205R, 207R (not shown), 205G, 207G, 205B, 207B, light-emitting elements 130R, 130G, 130B, etc. between substrates 151 and 152. Light-emitting element 130R is a display element of a sub-pixel 11R that emits red light, light-emitting element 130G is a display element of a sub-pixel 11G that emits green light, and light-emitting element 130B is a display element of a sub-pixel 11B that emits blue light.

[0454] The display device 50A employs an SBS structure. Because the SBS structure allows for the optimization of materials and configurations for each light-emitting element, it increases the freedom of material and configuration selection, making it easier to improve brightness and reliability.

[0455] The display device 50A is a top-emission type. In the top-emission type, transistors and the like can be placed overlapping with the light-emitting region of the light-emitting element, which allows for a higher aperture ratio of pixels compared to the bottom-emission type.

[0456] Transistors 205D, 205R, 207R (not shown), 205G, 207G, 205B, and 207B can be transistors according to one embodiment of the present invention. In other words, the display device 50A has transistors according to one embodiment of the present invention in both the display unit 162 and the circuit unit 164. By using transistors according to one embodiment of the present invention in the display unit 162, the pixel size can be reduced, resulting in a high-definition display device. Furthermore, by using transistors according to one embodiment of the present invention in the circuit unit 164, the occupied area of ​​the circuit unit 164 can be reduced, resulting in a narrow-bezel display device. For details on the transistors according to one embodiment of the present invention, refer to the description of the above embodiments.

[0457] An insulating layer 105 is provided on the substrate 151, and transistors 205D, 205R, 207R (not shown), 205G, 207G, 205B, and 207B are provided on the insulating layer 105. These transistors can be formed by sharing some of the manufacturing processes. Figure 19 shows an example configuration in which transistors 205D, 205R, 205G, and 205B use transistors 100 as shown in Figure 1B, etc., and transistors 207G and 207B use transistors 200.

[0458] Transistors 205D, 205R, 205G, and 205B each have a conductive layer 104 that functions as a gate, an insulating layer 106 that functions as a gate insulating layer, conductive layers 112a and 112b that function as source and drain, and a semiconductor layer 108. The metal oxide layer 70 is provided between the insulating layer 105 and the semiconductor layer 108. The semiconductor layer 108 has regions that are in contact with the top and side surfaces of the metal oxide layer 70. Transistors 207G and 207B each have a conductive layer 204 that functions as a gate, an insulating layer 106 that functions as a gate insulating layer, conductive layers 212a and 212b that function as source and drain, and a semiconductor layer 208. Here, the same hatching pattern is applied to multiple layers obtained by processing the same conductive film.

[0459] The transistors in the display device of this embodiment are not limited to those of one aspect of the present invention. For example, the transistors of one aspect of the present invention may be combined with transistors of other structures.

[0460] The display device of this embodiment may have, for example, one or more of planar transistors, staggered transistors, or inverse staggered transistors. The transistors in the display device of this embodiment may be top-gate or bottom-gate types. Alternatively, gates may be provided above and below the semiconductor layer in which the channel is formed.

[0461] The display device of this embodiment may have a Si transistor.

[0462] To increase the luminescence brightness of a light-emitting element included in a pixel circuit, it is necessary to increase the amount of current flowing through the light-emitting element. To achieve this, it is necessary to increase the source-drain voltage of the drive transistor included in the pixel circuit. Compared to Si transistors, OS transistors have a higher breakdown voltage between the source and drain, so a higher voltage can be applied to the source-drain of an OS transistor. Therefore, by using an OS transistor as the drive transistor in the pixel circuit, the amount of current flowing through the light-emitting element can be increased, thereby increasing the luminescence brightness of the light-emitting element.

[0463] When a transistor operates in the saturation region, an OS transistor exhibits a smaller change in source-drain current in response to a change in gate-source voltage than a Si transistor. Therefore, by using an OS transistor as the driving transistor in a pixel circuit, the current flowing between the source and drain can be precisely controlled by the change in gate-source voltage, thereby allowing control of the current flowing to the light-emitting element. This allows for an increase in the number of grayscale levels in the pixel circuit.

[0464] In terms of the saturation of the current flowing when a transistor operates in the saturation region, OS transistors can supply a more stable current (saturation current) than Si transistors, even when the source-drain voltage gradually increases. Therefore, by using an OS transistor as a driving transistor, a stable current can be supplied to a light-emitting element even if there are variations in the current-voltage characteristics of the light-emitting element. In other words, when operating in the saturation region, OS transistors can stabilize the luminescence brightness of a light-emitting element because the change in source-drain current is small even when the source-drain voltage is changed.

[0465] The transistors in the circuit unit 164 and the transistors in the display unit 162 may have the same structure or different structures. The structures of the multiple transistors in the circuit unit 164 may all be the same or there may be two or more different structures. Similarly, the structures of the multiple transistors in the display unit 162 may all be the same or there may be two or more different structures.

[0466] All of the transistors in the display unit 162 may be OS transistors, all of the transistors in the display unit 162 may be Si transistors, or some of the transistors in the display unit 162 may be OS transistors and the rest may be Si transistors. LTPS transistors have high field-effect mobility and can operate at high speeds.

[0467] For example, by using both an LTPS transistor and an OS transistor in the display unit 162, a display device with low power consumption and high driving capability can be realized. Furthermore, a configuration combining an LTPS transistor and an OS transistor is sometimes referred to as LTPO. A more preferable example is a configuration in which an OS transistor is used for transistors that function as switches to control conduction and non-conduction between wires, and an LTPS transistor is used for transistors that control current.

[0468] For example, one of the transistors in the display unit 162 functions as a transistor for controlling the current flowing to the light-emitting element, and can also be called a drive transistor. One of the source and drain of the drive transistor is connected to the pixel electrode of the light-emitting element. It is preferable to use an LTPS transistor for the drive transistor. This makes it possible to increase the current flowing to the light-emitting element in the pixel circuit.

[0469] On the other hand, the other transistor in the display unit 162 functions as a switch for controlling the selection and deselection of pixels, and can also be called a selection transistor. The gate of the selection transistor is connected to the gate line, and one of the source and drain is connected to the source line (signal line). It is preferable to use an OS transistor for the selection transistor. This makes it possible to maintain the gradation of pixels even when the frame frequency is significantly low (for example, 1 fps or less), and thus power consumption can be reduced by stopping the driver when displaying a still image.

[0470] An insulating layer 218 is provided so as to cover transistors 205D, 205R, 207R (not shown), 205G, 207G, 205B, and 207B, and an insulating layer 235 is provided on the insulating layer 218.

[0471] The insulating layer 235 preferably functions as a planarization layer, and an organic insulating layer is preferred. Materials that can be used for the organic insulating layer include acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimidoamide resin, siloxane resin, benzocyclobutene resin, phenol resin, and precursors of these resins. Furthermore, the insulating layer 235 can be a laminated structure of an organic insulating layer and an inorganic insulating layer. The outermost layer of the insulating layer 235 preferably functions as an etching protection layer. This suppresses the formation of recesses in the insulating layer 235 during processing of pixel electrodes 111R, 111G, 111B, etc. An inorganic insulating layer can be suitably used as the etching protection layer. Alternatively, recesses may be provided in the insulating layer 235 during processing of pixel electrodes 111R, 111G, and 111B, etc. Note that pixel electrodes 111R, 111G, and 111B are sometimes collectively referred to as pixel electrode 111.

[0472] Light-emitting elements 130R, 130G, and 130B are provided on the insulating layer 235.

[0473] The light-emitting element 130R has a pixel electrode 111R on an insulating layer 235, an EL layer 113R on the pixel electrode 111R, and a common electrode 115 on the EL layer 113R. The light-emitting element 130R shown in Figure 19A emits red light (R). The EL layer 113R has a light-emitting layer that emits red light.

[0474] The light-emitting element 130G has a pixel electrode 111G on an insulating layer 235, an EL layer 113G on the pixel electrode 111G, and a common electrode 115 on the EL layer 113G. The light-emitting element 130G shown in Figure 19A emits green light (G). The EL layer 113G has a light-emitting layer that emits green light.

[0475] The light-emitting element 130B has a pixel electrode 111B on an insulating layer 235, an EL layer 113B on the pixel electrode 111B, and a common electrode 115 on the EL layer 113B. The light-emitting element 130B shown in Figure 19A emits blue light (B). The EL layer 113B has a light-emitting layer that emits blue light.

[0476] In Figure 19A, the EL layers 113R, 113G, and 113B are all shown to be the same thickness, but this is not the only option. The thicknesses of the EL layers 113R, 113G, and 113B may be different. For example, it is preferable to set the thickness of the EL layers 113R, 113G, and 113B so that the optical path length is such that the light emitted by each layer is intensified. This makes it possible to realize a microcavity structure and improve the color purity of the light emitted from each light-emitting element.

[0477] The pixel electrode 111R is in contact with and connected to the conductive layer 112b of the transistor 205R at openings provided in the insulating layer 106, insulating layer 195, insulating layer 218, and insulating layer 235. Similarly, the pixel electrode 111G is connected to the conductive layer 112b of the transistor 205G, and the pixel electrode 111B is connected to the conductive layer 112b of the transistor 205B.

[0478] Each end of the pixel electrodes 111R, 111G, and 111B is covered by an insulating layer 237. The insulating layer 237 functions as a partition. The insulating layer 237 can be provided in a single-layer or multi-layer structure using one or both inorganic insulating materials and / or organic insulating materials. For example, the insulating layer 237 can be made of materials that can be used for the insulating layer 218 and materials that can be used for the insulating layer 235. The insulating layer 237 electrically insulates the pixel electrodes from the common electrodes. In addition, the insulating layer 237 electrically insulates adjacent light-emitting elements from each other.

[0479] The insulating layer 237 is provided at least on the display unit 162. The insulating layer 237 may be provided not only on the display unit 162, but also on the connection unit 140 and the circuit unit 164. Furthermore, the insulating layer 237 may extend to the end of the display device 50A.

[0480] The common electrode 115 is a continuous film provided in common to the light-emitting elements 130R, 130G, and 130B. The common electrode 115, which is shared by multiple light-emitting elements, is connected to a conductive layer 123 provided at the connection portion 140. It is preferable to use a conductive layer for the conductive layer 123 that is made of the same material and formed using the same process as the pixel electrodes 111R, 111G, and 111B.

[0481] In a display device according to one aspect of the present invention, among the pixel electrodes and common electrodes, the electrode that extracts light is preferably made of a conductive film that transmits visible light. Furthermore, it is preferable that the electrode that does not extract light is made of a conductive film that reflects visible light.

[0482] A conductive film that transmits visible light may also be used on the electrode that does not extract light. In this case, it is preferable to place the electrode between the reflective layer and the EL layer. In other words, the light emitted from the EL layer may be reflected by the reflective layer and extracted from the display device.

[0483] As the material for forming the pair of electrodes of the light-emitting element, metals, alloys, electrically conductive compounds, and mixtures thereof can be used as appropriate. Specifically, such materials include metals such as aluminum, magnesium, titanium, chromium, manganese, iron, cobalt, nickel, copper, gallium, zinc, indium, tin, molybdenum, tantalum, tungsten, palladium, gold, platinum, silver, yttrium, and neodymium, and alloys containing these in appropriate combinations. Other examples of such materials include ITO, ITSO, indium zinc oxide (In-Zn oxide), and In-W-Zn oxide. Furthermore, examples of such materials include aluminum-containing alloys such as aluminum, nickel, and lanthanum alloys (Al-Ni-La), as well as silver-containing alloys such as silver-magnesium alloys and silver-palladium-copper alloys (Ag-Pd-Cu, also written as APC). Other materials include elements belonging to Group 1 or Group 2 of the periodic table not exemplified above (e.g., lithium, cesium, calcium, strontium), rare earth metals such as europium and ytterbium, alloys containing these in appropriate combinations, graphene, and the like.

[0484] It is preferable that the light-emitting element has a microcavity structure. Therefore, it is preferable that one of the pair of electrodes in the light-emitting element is a semitransmitting / semi-reflective electrode that transmits and reflects visible light, and the other is a reflective electrode that reflects visible light. By having a microcavity structure in the light-emitting element, the light emitted from the light-emitting layer can be resonated between the two electrodes, thereby strengthening the light emitted from the light-emitting element.

[0485] The light transmittance of the transparent electrode shall be 40% or more. For example, it is preferable to use an electrode with a transmittance of 40% or more for visible light (light with a wavelength of 400 nm or more and less than 750 nm) for the transparent electrode of the light-emitting element. The visible light reflectance of the semi-transparent and semi-reflective electrodes shall be 10% or more and 95% or less, preferably 30% or more and 80% or less. The visible light reflectance of the reflective electrode shall be 40% or more and 100% or less, preferably 70% or more and 100% or less. Furthermore, the electrical resistivity of these electrodes shall be 1 × 10⁻⁶−２ A value of Ωcm or less is preferable.

[0486] The EL layers 113R, 113G, and 113B are each provided in an island-like manner. In Figure 19A, the edges of adjacent EL layers 113R and 113G overlap, the edges of adjacent EL layers 113G and 113B overlap, and the edges of adjacent EL layers 113R and 113B overlap. When forming island-like EL layers using a fine metal mask, the edges of adjacent EL layers may overlap as shown in Figure 19A, but this is not the only case. In other words, adjacent EL layers may not overlap and may be separated from each other. Furthermore, in a display device, there may be both regions where adjacent EL layers overlap and regions where adjacent EL layers do not overlap and are separated.

[0487] Each of the EL layers 113R, 113G, and 113B has at least one light-emitting layer. The light-emitting layer has one or more types of light-emitting materials. As the light-emitting material, a material that exhibits a light-emitting color such as blue, purple, blue-violet, green, yellow-green, yellow, orange, or red can be used as appropriate. In addition, a material that emits near-infrared light can also be used as the light-emitting material.

[0488] Examples of luminescent materials include fluorescent materials, phosphorescent materials, thermally activated delayed fluorescence (TADF) materials, and inorganic compounds (such as quantum dot materials).

[0489] Examples of quantum dot materials include colloidal quantum dots, alloy quantum dots, core-shell quantum dots, and core quantum dots. Furthermore, quantum dot materials containing elemental groups of Group 2 and Group 16, Group 13 and Group 15, Group 13 and Group 17, Group 11 and Group 17, or Group 14 and Group 15 can be used. Alternatively, quantum dot materials containing elements such as cadmium (Cd), selenium (Se), zinc (Zn), sulfur (S), phosphorus (P), indium (In), tellurium (Te), lead (Pb), gallium (Ga), arsenic (As), and aluminum (Al) can be used.

[0490] The light-emitting layer may contain one or more types of organic compounds (host material, assist material, etc.) in addition to the light-emitting substance (guest material). One or more of the organic compounds may be substances with high hole transport properties (hole transport material) and / or substances with high electron transport properties (electron transport material). Alternatively, one or more of the organic compounds may be bipolar substances (substances with high electron and hole transport properties) or TADF materials.

[0491] The light-emitting layer preferably comprises, for example, a phosphorescent material and a combination of a hole-transporting material and an electron-transporting material that readily forms an excitation complex. This configuration allows for efficient emission using ExTET (Exciplex-Triplet Energy Transfer), which is energy transfer from the excitation complex to the light-emitting substance (phosphorescent material). By selecting a combination that forms an excitation complex that exhibits emission overlapping with the wavelength of the lowest-energy absorption band of the light-emitting substance, energy transfer becomes smoother, and light emission can be obtained efficiently. This configuration enables high efficiency, low-voltage operation, and a long lifespan for the light-emitting element.

[0492] The EL layer may have, in addition to the light-emitting layer, one or more of the following: a layer containing a material with high hole injection properties (hole injection layer), a layer containing a hole transport material (hole transport layer), a layer containing a material with high electron blocking properties (electron blocking layer), a layer containing a material with high electron injection properties (electron injection layer), a layer containing an electron transport material (electron transport layer), and a layer containing a material with high hole blocking properties (hole blocking layer). Furthermore, the EL layer may contain either or both a bipolar material and a TADF material.

[0493] The light-emitting element can be made of either low-molecular-weight compounds or high-molecular-weight compounds, and may also contain inorganic compounds. The layers constituting the light-emitting element can be formed by methods such as vapor deposition (including vacuum deposition), transfer, printing, inkjet, and coating.

[0494] The light-emitting element may be a single structure (a structure having only one light-emitting unit) or a tandem structure (a structure having multiple light-emitting units). Each light-emitting unit has at least one light-emitting layer. The tandem structure is a configuration in which multiple light-emitting units are connected in series via a charge generation layer. The charge generation layer has the function of injecting electrons into one of the two light-emitting units and holes into the other when a voltage is applied between a pair of electrodes. By using a tandem structure, a light-emitting element capable of high-brightness emission can be made. Furthermore, compared to a single structure, the tandem structure can reduce the current required to obtain the same brightness, thus improving reliability. The tandem structure can also be called a stack structure.

[0495] In Figure 19A, when a tandem light-emitting element is used, it is preferable that the EL layer 113R has a structure having multiple light-emitting units that emit red light, the EL layer 113G has a structure having multiple light-emitting units that emit green light, and the EL layer 113B has a structure having multiple light-emitting units that emit blue light.

[0496] A protective layer 131 is provided on the light-emitting elements 130R, 130G, and 130B. The protective layer 131 and the substrate 152 are bonded together via an adhesive layer 142. A light-shielding layer 117 is provided on the substrate 152. For sealing the light-emitting elements, for example, a solid sealing structure or a hollow sealing structure can be applied. In Figure 19A, the space between the substrate 152 and the substrate 151 is filled with the adhesive layer 142, and a solid sealing structure is applied. Alternatively, the space may be filled with an inert gas (such as nitrogen or argon), and a hollow sealing structure may be applied. In this case, the adhesive layer 142 may be provided in a frame shape so as not to overlap with the light-emitting elements. Furthermore, the space may be filled with a resin different from the adhesive layer 142 provided in a frame shape.

[0497] The protective layer 131 is provided at least on the display section 162, and preferably so as to cover the entire display section 162. It is preferable that the protective layer 131 covers not only the display section 162, but also the connection section 140 and the circuit section 164. Furthermore, it is preferable that the protective layer 131 extends to the end of the display device 50A. On the other hand, in the connection section 197, there is an area where the protective layer 131 is not provided in order to connect the FPC 172 and the conductive layer 166.

[0498] By providing a protective layer 131 on the light-emitting elements 130R, 130G, and 130B, the reliability of the light-emitting elements can be improved.

[0499] The protective layer 131 can be a single layer or a laminated structure of two or more layers. Furthermore, the conductivity of the protective layer 131 is not required. At least one of an insulating film, a semiconductor film, and a conductive film can be used as the protective layer 131.

[0500] The presence of an inorganic film in the protective layer 131 prevents oxidation of the common electrode 115 and suppresses the intrusion of impurities (such as moisture and oxygen) into the light-emitting element, thereby suppressing degradation of the light-emitting element and improving the reliability of the display device.

[0501] The protective layer 131 preferably has one or more inorganic insulating layers. The protective layer 131 can be made from the materials listed for insulating layer 106 and insulating layer 105. In particular, the protective layer 131 preferably uses nitrides or nitride oxides, and more preferably uses nitrides.

[0502] The protective layer 131 may also be an inorganic film containing ITO, In-Zn oxide, Ga-Zn oxide, Al-Zn oxide, or IGZO. The inorganic film is preferably highly resistive, and more specifically, it is preferably more resistive than the common electrode 115. The inorganic film may further contain nitrogen.

[0503] When the light emitted from a light-emitting element is extracted via a protective layer 131, it is preferable that the protective layer 131 has high transmittance (also referred to as light transmission) to visible light. For example, ITO, IGZO, and aluminum oxide are preferred because they are inorganic materials with high transmittance to visible light.

[0504] As the protective layer 131, for example, a laminated structure of an aluminum oxide film and a silicon nitride film on the aluminum oxide film, or a laminated structure of an aluminum oxide film and an IGZO film on the aluminum oxide film can be used. By using such a laminated structure, it is possible to suppress the penetration of impurities (water, oxygen, etc.) into the EL layer.

[0505] Furthermore, the protective layer 131 may have an organic film. For example, the protective layer 131 may have both an organic film and an inorganic film. Examples of organic films that can be used for the protective layer 131 include an organic insulating layer that can be used for the insulating layer 235.

[0506] A connection portion 197 is provided in the region of substrate 151 where substrate 152 does not overlap. At the connection portion 197, the conductive layer 165 is connected to the FPC 172 via the conductive layer 166 and the connection layer 242. Figure 19A shows an example where the conductive layer 165 is a conductive layer obtained by processing the same conductive film as the conductive layer 112b. The conductive layer 166 is an example where it is a conductive layer obtained by processing the same conductive film as the pixel electrodes 111R, 111G, and 111B. The connection portion between conductive layer 165 and conductive layer 166 can be configured in the same way as the connection portion between the pixel electrode 111 and conductive layer 112b. Specifically, Figure 19A shows an example where an opening is provided in the upper layer of conductive layer 165, and the conductive layer 166 is in contact with the upper surface of conductive layer 165 at this opening. The conductive layer 166 is exposed on the upper surface of the connection portion 197. This allows the connection part 197 and the FPC 172 to be connected via the connection layer 242.

[0507] The display device 50A is of the top-emission type. The light emitted by the light-emitting element is emitted towards the substrate 152. It is preferable to use a material with high transmittance to visible light for the substrate 152. The pixel electrodes 111R, 111G, and 111B contain a material that reflects visible light, and the counter electrode (common electrode 115) contains a material that transmits visible light.

[0508] It is preferable to provide a light-shielding layer 117 on the surface of the substrate 152 that faces the substrate 151. The light-shielding layer 117 can be provided between adjacent light-emitting elements, in connection portions 140, and in circuit portions 164, etc.

[0509] A colored layer, such as a color filter, may be provided on the surface of the substrate 152 facing the substrate 151, or on the protective layer 131. By placing a color filter on top of the light-emitting element, the color purity of the light emitted from the pixel can be increased.

[0510] A colored layer is a colored layer that selectively transmits light in a specific wavelength range and absorbs light in other wavelength ranges. For example, a red (R) color filter that transmits light in the red wavelength range, a green (G) color filter that transmits light in the green wavelength range, and a blue (B) color filter that transmits light in the blue wavelength range can be used. One or more of the following can be used for each colored layer: metal materials, resin materials, pigments, and dyes. The colored layers are formed at the desired positions using methods such as printing, inkjet printing, and photolithography etching.

[0511] Various optical components can be placed on the outside of the substrate 152 (the side opposite to the substrate 151). Examples of optical components include polarizing plates, phase difference plates, light diffusion layers (such as diffusion films), anti-reflective layers, and light-gathering films. In addition, surface protection layers such as an antistatic film to suppress the adhesion of dust, a water-repellent film to make it difficult for dirt to adhere, a hard coat film to suppress the occurrence of scratches during use, and a shock-absorbing layer may be placed on the outside of the substrate 152. For example, a glass layer or a silica layer (SiO ｘProviding a protective layer (where x is a real number greater than 0) is preferable as it can suppress surface contamination and scratching. Alternatively, DLC (diamond-like carbon), aluminum oxide, polyester-based materials, or polycarbonate-based materials may be used as the surface protective layer. It is preferable to use a material with high transmittance to visible light for the surface protective layer. Furthermore, it is preferable to use a material with high hardness for the surface protective layer.

[0512] The substrates 151 and 152 can be made of glass, quartz, ceramics, sapphire, resin, metal, alloy, semiconductor, etc., respectively. The substrate on the side that extracts light from the light-emitting element should be made of a material that transmits the light. If flexible materials are used for substrates 151 and 152, the flexibility of the display device can be increased, and a flexible display can be realized. In addition, a polarizing plate may be used as at least one of substrates 151 and 152.

[0513] As substrates 151 and 152, various materials can be used, such as polyester resins like polyethylene terephthalate (PET) and polyethylene naphthalate (PEN), polyacrylonitrile resin, acrylic resin, polyimide resin, polymethyl methacrylate resin, polycarbonate (PC) resin, polyethersulfone (PES) resin, polyamide resin (nylon, aramid, etc.), polysiloxane resin, cycloolefin resin, polystyrene resin, polyamide-imide resin, polyurethane resin, polyvinyl chloride resin, polyvinylidene chloride resin, polypropylene resin, polytetrafluoroethylene (PTFE) resin, ABS resin, cellulose nanofiber, etc. At least one of substrates 151 and 152 may be made of glass of a thickness sufficient to provide flexibility.

[0514] Furthermore, when a circular polarizing plate is superimposed on a display device, it is preferable to use a substrate with high optical isotropy for the substrate of the display device. A substrate with high optical isotropy has low birefringence (or a small amount of birefringence). Examples of films with high optical isotropy include triacetylcellulose (TAC, also called cellulose triacetate) film, cycloolefin polymer (COP) film, cycloolefin copolymer (COC) film, and acrylic film.

[0515] Various types of curing adhesives can be used as the adhesive layer 142, including UV-curing adhesives, reaction-curing adhesives, thermosetting adhesives, and anaerobic adhesives. Examples of these adhesives include epoxy resins, acrylic resins, silicone resins, phenolic resins, polyimide resins, imide resins, PVC (polyvinyl chloride) resins, PVB (polyvinyl butyral) resins, and EVA (ethylene vinyl acetate) resins. Materials with low moisture permeability, such as epoxy resins, are particularly preferred. Two-component mixed resins may also be used. Adhesive sheets may also be used.

[0516] As the connecting layer 242, an anisotropic conductive film (ACF), anisotropic conductive paste (ACP), etc., can be used.

[0517] <Example of Display Device Configuration 2> Figure 19B shows an example of a cross-section of the display unit 162 of the display device 50B. The display device 50B differs from the display device 50A in that each sub-pixel of each color uses a light-emitting element having a common EL layer 113 and a coloring layer (such as a color filter). The configuration shown in Figure 19B can be combined with the configuration of the region including the FPC 172, the circuit unit 164, the laminated structure from the substrate 151 to the insulating layer 235 of the display unit 162, the connection unit 140, and the end portion shown in Figure 19A. Note that in the following description of the display device, parts that are the same as those described in the previously described display device may be omitted.

[0518] The display device 50B shown in Figure 19B includes light-emitting elements 130R, 130G, 130B, a colored layer 132R that transmits red light, a colored layer 132G that transmits green light, and a colored layer 132B that transmits blue light, etc.

[0519] The light-emitting element 130R includes a pixel electrode 111R, an EL layer 113 on the pixel electrode 111R, and a common electrode 115 on the EL layer 113. The light emitted from the light-emitting element 130R is extracted as red light to the outside of the display device 50B via the colored layer 132R.

[0520] The light-emitting element 130G includes a pixel electrode 111G, an EL layer 113 on the pixel electrode 111G, and a common electrode 115 on the EL layer 113. The light emitted from the light-emitting element 130G is extracted as green light to the outside of the display device 50B via the colored layer 132G.

[0521] The light-emitting element 130B includes a pixel electrode 111B, an EL layer 113 on the pixel electrode 111B, and a common electrode 115 on the EL layer 113. The light emitted from the light-emitting element 130B is extracted as blue light to the outside of the display device 50B via the colored layer 132B.

[0522] The light-emitting elements 130R, 130G, and 130B each share an EL layer 113 and a common electrode 115. Providing a common EL layer 113 for each sub-pixel of each color reduces the number of manufacturing steps compared to providing a different EL layer for each sub-pixel of each color.

[0523] For example, the light-emitting elements 130R, 130G, and 130B shown in Figure 19B emit white light. The white light emitted by the light-emitting elements 130R, 130G, and 130B passes through the colored layers 132R, 132G, and 132B, thereby obtaining light of a desired color.

[0524] A light-emitting element that emits white light preferably includes two or more light-emitting layers. When obtaining white light emission using two light-emitting layers, the light-emitting layers can be selected such that their emission colors are complementary. For example, by making the emission color of the first light-emitting layer and the emission color of the second light-emitting layer complementary, a configuration can be obtained in which the entire light-emitting element emits white light. Furthermore, when obtaining white light emission using three or more light-emitting layers, the emission colors of the three or more light-emitting layers combine to create a configuration in which the entire light-emitting element emits white light.

[0525] The EL layer 113 preferably has, for example, an emissive layer having a light-emitting material that emits blue light, and an emissive layer having a light-emitting material that emits visible light with a longer wavelength than blue. The EL layer 113 preferably has, for example, an emissive layer that emits yellow light and an emissive layer that emits blue light. Alternatively, the EL layer 113 preferably has, for example, an emissive layer that emits red light, an emissive layer that emits green light, and an emissive layer that emits blue light.

[0526] For light-emitting elements that emit white light, a tandem structure is preferable. Specifically, a two-stage tandem structure having a light-emitting unit that emits yellow light and a light-emitting unit that emits blue light, a two-stage tandem structure having a light-emitting unit that emits red and green light and a light-emitting unit that emits blue light, a three-stage tandem structure having a light-emitting unit that emits blue light, a light-emitting unit that emits yellow, yellow-green, or green light, and a light-emitting unit that emits blue light in that order, or a three-stage tandem structure having a light-emitting unit that emits blue light, a light-emitting unit that emits yellow, yellow-green, or green light, a light-emitting unit that emits red light, and a light-emitting unit that emits blue light in that order. For example, the number of layers and color order of the light-emitting unit can be, from the anode side, a two-layer structure of B and Y, a two-layer structure of B and light-emitting unit X, a three-layer structure of B, Y, B, or a three-layer structure of B, X, B. The number of layers and color order of the light-emitting layers in light-emitting unit X can be, from the anode side, a two-layer structure of R and Y, a two-layer structure of R and G, a two-layer structure of G and R, a three-layer structure of G, R, G, or a three-layer structure of R, G, R. In addition, other layers may be provided between the two light-emitting layers.

[0527] Furthermore, by applying a microcavity structure, a light-emitting element that normally emits white light may also emit light at specific wavelengths, such as red, green, or blue, with enhanced illumination.

[0528] Alternatively, for example, the light-emitting elements 130R, 130G, and 130B shown in Figure 19B emit blue light. In this case, the EL layer 113 has one or more light-emitting layers that emit blue light. In the sub-pixel 11B that emits blue light, the blue light emitted by the light-emitting element 130B can be extracted. In addition, in the sub-pixel 11R that emits red light and the sub-pixel 11G that emits green light, by providing a color conversion layer between the light-emitting element 130R or light-emitting element 130G and the substrate 152, the blue light emitted by the light-emitting element 130R or light-emitting element 130G can be converted into longer wavelength light, and red or green light can be extracted. The color conversion layer can be described in the above description. Specifically, the various quantum dot materials described above can be used for the color conversion layer. Furthermore, it is preferable to provide a coloring layer 132R between the color conversion layer and the substrate 152 on the light-emitting element 130R, and a coloring layer 132G between the color conversion layer and the substrate 152 on the light-emitting element 130G. Some of the light emitted by a light-emitting element may pass through without being converted by the color conversion layer. By extracting the light that has passed through the color conversion layer via a colored layer, the color of light other than the desired color can be absorbed by the colored layer, thereby increasing the color purity of the light exhibited by the subpixel.

[0529] <Example of Display Device Configuration 3> The display device 50C shown in Figure 20 differs from the display device 50B mainly in that it is a bottom-emission type display device.

[0530] The light emitted by the light-emitting element is emitted towards the substrate 151. It is preferable to use a material with high transmittance to visible light for the substrate 151. On the other hand, the light transmittance of the material used for the substrate 152 is not a requirement.

[0531] It is preferable to form a light-shielding layer 117 between the substrate 151 and the transistors. The display device 50C shown in Figure 20 is an example in which a light-shielding layer 117 is provided on the substrate 151, an insulating layer 153 is provided on the light-shielding layer 117, and transistors 205D, 205R, 207R (not shown), 205G, 207G, 205B (not shown), and 207B are provided on the insulating layer 153. In addition, a colored layer 132R, a colored layer 132G, and a colored layer 132B (not shown) are provided on the insulating layer 218, and an insulating layer 235 is provided on the colored layer 132R, a colored layer 132G, and a colored layer 132B (not shown).

[0532] The light-emitting element 130R, which overlaps with the colored layer 132R, has a pixel electrode 111R, an EL layer 113, and a common electrode 115.

[0533] The light-emitting element 130G, which overlaps with the colored layer 132G, has a pixel electrode 111G, an EL layer 113, and a common electrode 115.

[0534] Although not shown in Figure 20, the light-emitting element 130B, which overlaps with the colored layer 132B, has a pixel electrode 111B, an EL layer 113, and a common electrode 115.

[0535] The pixel electrodes 111R, 111G, and 111B are made of materials with high transmittance to visible light. It is preferable to use a material that reflects visible light for the common electrode 115. In a bottom-emission type display device, a metal with low electrical resistivity can be used for the common electrode 115, thereby suppressing voltage drops caused by the electrical resistance of the common electrode 115 and achieving high display quality.

[0536] A transistor according to one aspect of the present invention can reduce the occupied area, thereby enabling an increase in the aperture ratio of pixels or a reduction in the size of pixels in a display device with a bottom emission structure.

[0537] <Example of Display Device Configuration 4> The display device 50D shown in Figure 21A differs from the display device 50A mainly in that it has a light-receiving element 130S.

[0538] The display device 50D has a light-emitting element and a light-receiving element in each pixel. In the display device 50D, it is preferable to use an organic EL element as the light-emitting element and an organic photodiode as the light-receiving element. The organic EL element and the organic photodiode can be formed on the same substrate. Therefore, an organic photodiode can be incorporated into a display device using an organic EL element.

[0539] In a display device 50D having light-emitting and light-receiving elements in its pixels, the pixels have a light-receiving function, allowing for the detection of contact or proximity of an object while displaying an image. Therefore, the display unit 162 has, in addition to an image display function, one or both of an imaging function and a sensing function. For example, the display device 50D can not only display an image using all of its subpixels, but some subpixels can also emit light as a light source, some other subpixels can perform light detection, and the remaining subpixels can display an image.

[0540] Therefore, it is not necessary to provide a light receiving unit and a light source separately from the display device 50D, and the number of components in the electronic device can be reduced. For example, there is no need to separately provide a biometric authentication device or a capacitive touch panel for scrolling, etc., which are installed in the electronic device. Therefore, by using the display device 50D, it is possible to provide an electronic device with reduced manufacturing costs.

[0541] When a light-receiving element is used as an image sensor, the display device 50D can capture an image using the light-receiving element. For example, the image sensor can be used to capture images for personal authentication, such as fingerprints, palm prints, irises, pulse patterns (including vein patterns and arterial patterns), or faces.

[0542] The light-receiving element can be used in touch sensors (also called direct touch sensors) or non-contact sensors (also called hover sensors, hover touch sensors, or touchless sensors). Touch sensors can detect an object (such as a finger, hand, or pen) by making direct contact between the display device and the object. Non-contact sensors, on the other hand, can detect an object even if the object does not come into contact with the display device.

[0543] The light-receiving element 130S has a pixel electrode 111S on an insulating layer 235, a functional layer 113S on the pixel electrode 111S, and a common electrode 115 on the functional layer 113S. Light Lin is incident on the functional layer 113S from outside the display device 50D.

[0544] The pixel electrode 111S is in contact with and connected to the conductive layer 112b of the transistor 205S at openings provided in the insulating layer 106, insulating layer 195, insulating layer 218, and insulating layer 235.

[0545] The ends of the pixel electrodes 111S are covered by an insulating layer 237.

[0546] The common electrode 115 is a continuous film provided in common to the light-receiving element 130S, the light-emitting element 130R (not shown), the light-emitting element 130G, and the light-emitting element 130B. The common electrode 115, which is shared by the light-emitting element and the light-receiving element, is connected to the conductive layer 123 provided at the connection portion 140.

[0547] The functional layer 113S has at least an active layer (also called a photoelectric conversion layer). The active layer contains a semiconductor. Examples of the semiconductor include inorganic semiconductors such as silicon and organic semiconductors containing organic compounds. In this embodiment, an example is shown in which an organic semiconductor is used as the semiconductor of the active layer. Using an organic semiconductor is preferable because the light-emitting layer and the active layer can be formed by the same method (for example, vacuum deposition), and the manufacturing equipment can be shared.

[0548] The functional layer 113S may further include layers other than the active layer, such as a material with high hole transport properties, a material with high electron transport properties, or a bipolar material. Furthermore, it may also further include layers containing a material with high hole injection properties, a hole blocking material, a material with high electron injection properties, or an electron blocking material. For example, the functional layer 113S can be made from materials that can be used in the above-described light-emitting devices.

[0549] The photodetector can use either low-molecular-weight compounds or high-molecular-weight compounds, and may also contain inorganic compounds. The layers constituting the photodetector can be formed by methods such as vapor deposition (including vacuum deposition), transfer, printing, inkjet, and coating.

[0550] In addition to the aforementioned light-receiving element, a touch sensor can be provided separately. The touch sensor is preferably positioned on the display surface side of the light-receiving element and light-emitting element. For example, a capacitive touch sensor can be used as the touch sensor. For instance, by capturing a fingerprint using the light-receiving element, a high-resolution image can be captured, enabling highly accurate fingerprint authentication. Furthermore, using a capacitive touch sensor for touch sensing allows for high-speed operation. Therefore, a highly convenient display device can be created.

[0551] The display device 50D shown in Figures 21B and 21C has a layer 353 with a light-receiving element, a circuit layer 355, and a layer 357 with an light-emitting element between the substrate 151 and the substrate 152.

[0552] Layer 353 has, for example, a light-receiving element 130S. Layer 357 has, for example, light-emitting elements 130R, 130G, and 130B.

[0553] The circuit layer 355 includes a circuit for driving a light-receiving element and a circuit for driving a light-emitting element. The circuit layer 355 includes, for example, transistors 205R, 205G, and 205B. In addition, the circuit layer 355 may be provided with one or more of the following: switches, capacitors, resistors, wiring, and terminals.

[0554] Figure 21B shows an example of using the light-receiving element 130S as a touch sensor. As shown in Figure 21B, the light emitted by the light-emitting element in layer 357 is reflected by the finger 352 that is in contact with the display device 50D, and the light-receiving element in layer 353 detects this reflected light. This makes it possible to detect that the finger 352 has come into contact with the display device 50D.

[0555] Figure 21C shows an example of using the light-receiving element 130S as a non-contact sensor. As shown in Figure 21C, the light emitted by the light-emitting element in layer 357 is reflected by a finger 352 that is close to (i.e., not in contact with) the display device 50D, and the light-receiving element in layer 353 detects the reflected light.

[0556] <Example of Display Device Configuration 5> The display device 50E shown in Figure 22A is an example of a display device to which an MML (metal maskless) structure is applied. In other words, the display device 50E has a light-emitting element manufactured without using a fine metal mask.

[0557] In a display device using an MML structure, the island-shaped light-emitting layers in the light-emitting elements are formed by depositing a light-emitting layer onto one surface and then processing it using lithography. Therefore, it is possible to realize high-definition display devices or display devices with high aperture ratios, which have been difficult to achieve until now. Furthermore, since the light-emitting layers can be made separately for each color, it is possible to realize a display device that is extremely vivid, has high contrast, and displays high quality. For example, if the display device is composed of three types of light-emitting elements, such as a blue light-emitting element, a green light-emitting element, and a red light-emitting element, three types of island-shaped light-emitting layers can be formed by repeating the deposition of the light-emitting layer and processing by lithography three times.

[0558] Because MML (Multilayer Molded) devices can be manufactured without using a metal mask, they can exceed the resolution limits imposed by the precision required for metal mask alignment. Furthermore, when manufacturing devices without a metal mask, the equipment and cleaning processes associated with metal mask manufacturing are eliminated. Additionally, since the lithography process can utilize equipment common to or similar to that used for transistor manufacturing, there is no need to introduce special equipment for manufacturing MML devices. Thus, MML structures allow for lower manufacturing costs, making them suitable for mass production of devices.

[0559] In a display device to which an MML structure is applied, there is no need to artificially increase the resolution by applying a special pixel arrangement such as a pentile arrangement. Therefore, a display device with high resolution (for example, 500 ppi or more, 1000 ppi or more, 2000 ppi or more, 3000 ppi or more, or 5000 ppi or more) can be realized using a so-called stripe arrangement in which the R, G, and B subpixels are each arranged in one direction.

[0560] By providing a sacrificial layer on the light-emitting layer, damage to the light-emitting layer during the manufacturing process of the display device can be reduced, thereby improving the reliability of the light-emitting element.

[0561] By employing a film deposition process using an area mask and a processing process using a resist mask, light-emitting elements can be fabricated using a relatively simple process.

[0562] Note that the laminated structure from substrate 151 to insulating layer 235, and the laminated structure from protective layer 131 to substrate 152 are the same as those of the display device 50A, so their explanation is omitted.

[0563] In Figure 22A, light-emitting elements 130R, 130G, and 130B are provided on the insulating layer 235.

[0564] The light-emitting element 130R includes a conductive layer 124R on an insulating layer 235, a conductive layer 126R on the conductive layer 124R, a layer 133R on the conductive layer 126R, a common layer 114 on the layer 133R, and a common electrode 115 on the common layer 114. The light-emitting element 130R shown in Figure 22A emits red light (R). Layer 133R has a light-emitting layer that emits red light. In the light-emitting element 130R, layer 133R and the common layer 114 can be collectively called the EL layer. In addition, one or both of the conductive layer 124R and the conductive layer 126R can be called the pixel electrode.

[0565] The light-emitting element 130G includes a conductive layer 124G on an insulating layer 235, a conductive layer 126G on the conductive layer 124G, a layer 133G on the conductive layer 126G, a common layer 114 on the layer 133G, and a common electrode 115 on the common layer 114. The light-emitting element 130G shown in Figure 22A emits green light (G). Layer 133G has a light-emitting layer that emits green light. In the light-emitting element 130G, layer 133G and the common layer 114 can be collectively called the EL layer. In addition, one or both of the conductive layer 124G and the conductive layer 126G can be called the pixel electrode.

[0566] The light-emitting element 130B includes a conductive layer 124B on an insulating layer 235, a conductive layer 126B on the conductive layer 124B, a layer 133B on the conductive layer 126B, a common layer 114 on the layer 133B, and a common electrode 115 on the common layer 114. The light-emitting element 130B shown in Figure 22A emits blue light (B). Layer 133B has a light-emitting layer that emits blue light. In the light-emitting element 130B, layer 133B and the common layer 114 can be collectively called the EL layer. In addition, one or both of the conductive layer 124B and the conductive layer 126B can be called the pixel electrode.

[0567] In this specification, among the EL layers of a light-emitting element, layers provided in an island-like manner for each light-emitting element are referred to as layer 133B, layer 133G, or layer 133R, and a layer shared by multiple light-emitting elements is referred to as the common layer 114. In this specification, the common layer 114 may be omitted, and layers 133R, 133G, and 133B may be referred to as island-like EL layers, island-shaped EL layers, etc. Furthermore, light-emitting elements manufactured without using a metal mask do not need to have a common layer, and all layers constituting the EL layer may be formed in an island-like manner.

[0568] Layers 133R, 133G, and 133B are separated from each other. By providing the EL layer in an island-like configuration for each light-emitting element, leakage current between adjacent light-emitting elements can be suppressed. This prevents unintended light emission caused by crosstalk, enabling the realization of a display device with extremely high contrast.

[0569] Note that in Figure 22A, layers 133R, 133G, and 133B are all shown to be the same thickness, but this is not the only option. The thicknesses of layers 133R, 133G, and 133B may be different.

[0570] The conductive layer 124R is in contact with and connected to the conductive layer 112b of transistor 205R at openings provided in the insulating layer 106, insulating layer 195, insulating layer 218, and insulating layer 235. Similarly, the conductive layer 124G is connected to the conductive layer 112b of transistor 205G, and the conductive layer 124B is connected to the conductive layer 112b of transistor 205B.

[0571] The conductive layers 124R, 124G, and 124B are formed to cover the openings provided in the insulating layer 235. Layer 128 is embedded in the recesses of the conductive layers 124R, 124G, and 124B, respectively.

[0572] Layer 128 has the function of flattening the recesses of the conductive layers 124R, 124G, and 124B. Conductive layers 126R, 126G, and 126B are provided on conductive layers 124R, 124G, and 124B and on layer 128, and are connected to conductive layers 124R, 124G, and 124B. Therefore, the regions that overlap with the recesses of conductive layers 124R, 124G, and 124B can also be used as light-emitting regions, and the aperture ratio of the pixels can be increased. It is preferable to use conductive layers that function as reflective electrodes for conductive layers 124R and 126R.

[0573] Layer 128 may be an insulating layer or a conductive layer. Various inorganic insulating materials, organic insulating materials, and conductive materials can be used for layer 128 as appropriate. In particular, it is preferable that layer 128 be formed using an insulating material, and especially preferable that it be formed using an organic insulating material. For example, an organic insulating material that can be used for the insulating layer 237 described above can be applied to layer 128.

[0574] Figure 22A shows an example where the upper surface of layer 128 has a flat portion, but the shape of layer 128 is not particularly limited. The upper surface of layer 128 can have at least one of a convex curved surface, a concave curved surface, and a flat surface.

[0575] The height of the top surface of layer 128 and the height of the top surface of conductive layer 124R may be the same, approximately the same, or different from each other. For example, the height of the top surface of layer 128 may be lower or higher than the height of the top surface of conductive layer 124R.

[0576] The end of the conductive layer 126R may be aligned with the end of the conductive layer 124R, or it may cover the side surface of the end of the conductive layer 124R. Preferably, the ends of the conductive layer 124R and the conductive layer 126R have a tapered shape. Specifically, it is preferable that the ends of the conductive layer 124R and the conductive layer 126R have a tapered shape with a taper angle greater than 0 degrees and less than 90 degrees. When the end of the pixel electrode has a tapered shape, the layer 133R provided along the side surface of the pixel electrode has an inclined portion. By making the side surface of the pixel electrode tapered, the coverage of the EL layer provided along the side surface of the pixel electrode can be improved.

[0577] Detailed explanations of conductive layers 124G, 126G, and conductive layers 124B, 126B are omitted because they are the same as conductive layers 124R, 126R.

[0578] The top and sides of the conductive layer 126R are covered by layer 133R. Similarly, the top and sides of the conductive layer 126G are covered by layer 133G, and the top and sides of the conductive layer 126B are covered by layer 133B. Therefore, the entire region where the conductive layers 126R, 126G, and 126B are provided can be used as the light-emitting region of the light-emitting elements 130R, 130G, and 130B, thereby increasing the aperture ratio of the pixels.

[0579] The upper surfaces and sides of layers 133R, 133G, and 133B are covered by insulating layers 125 and 127. A common layer 114 is provided on layers 133R, 133G, 133B, and insulating layers 125 and 127, and a common electrode 115 is provided on the common layer 114. The common layer 114 and the common electrode 115 are each a continuous film provided in common to multiple light-emitting elements.

[0580] In Figure 22A, the insulating layer 237 shown in Figure 19A, etc., is not provided between the conductive layer 126R and layer 133R. Similarly, the insulating layer 237 is not provided between the conductive layer 126G and layer 133G, and between the conductive layer 126B and layer 133B. In other words, the display device 50E does not have an insulating layer (also called a partition, bank, spacer, etc.) that is in contact with the pixel electrodes and covers the upper edge of the pixel electrodes. Therefore, the spacing between adjacent light-emitting elements can be made extremely narrow. Consequently, a high-definition or high-resolution display device can be made. In addition, a mask for forming the insulating layer is not required, and the manufacturing cost of the display device can be reduced.

[0581] As described above, layers 133R, 133G, and 133B each have an emissive layer. Preferably, layers 133R, 133G, and 133B each have one or both of a carrier transport layer (electron transport layer or hole transport layer) and a carrier block layer (hole block layer or electron block layer) on the emissive layer. When the surfaces of layers 133R, 133G, and 133B are exposed to the atmosphere during the manufacturing process of the display device, providing one or both of the carrier transport layer and the carrier block layer on the emissive layer prevents the emissive layer from being exposed to the atmosphere because it does not have the emissive layer exposed to the outermost surface. This reduces the damage the emissive layer receives and improves the reliability of the light-emitting element.

[0582] The common layer 114 may have, for example, an electron injection layer or a hole injection layer. Alternatively, the common layer 114 may have an electron transport layer and an electron injection layer stacked together, or a hole transport layer and a hole injection layer stacked together. The common layer 114 is shared by the light-emitting elements 130R, 130G, and 130B.

[0583] Each side of layer 133R, layer 133G, and layer 133B is covered by the insulating layer 125. The insulating layer 127 covers each side of layer 133R, layer 133G, and layer 133B via the insulating layer 125.

[0584] The sides (and even a portion of the top surface) of layers 133R, 133G, and 133B are covered by at least one of the insulating layers 125 and 127. This prevents the common layer 114 (or common electrode 115) from coming into contact with the pixel electrode and the sides of layers 133R, 133G, and 133B, thereby suppressing short circuits in the light-emitting element. This improves the reliability of the light-emitting element.

[0585] Preferably, the insulating layer 125 has regions that are in contact with the respective sides of layers 133R, 133G, and 133B. By configuring the insulating layer 125 to be in contact with layers 133R, 133G, and 133B, peeling of the layers 133R, 133G, and 133B can be prevented, and the reliability of the light-emitting element can be improved.

[0586] The insulating layer 127 is provided on the insulating layer 125 so as to fill any recesses in the insulating layer 125. Preferably, the insulating layer 127 covers at least a portion of the side surface of the insulating layer 125.

[0587] By providing insulating layers 125 and 127, the gaps between adjacent island-shaped layers can be filled, thereby reducing the large height differences and irregularities on the formed surface of layers (e.g., carrier injection layers and common electrodes) on the island-shaped layers, making it flatter. Consequently, the coverage of the carrier injection layers and common electrodes can be improved.

[0588] The common layer 114 and the common electrode 115 are provided on layers 133R, 133G, 133B, insulating layer 125, and insulating layer 127. Before the insulating layer 125 and insulating layer 127 are provided, a step difference occurs due to the region where the pixel electrode and island-shaped EL layer are provided and the region where the pixel electrode and island-shaped EL layer are not provided (the region between light-emitting elements). In one embodiment of the present invention, the presence of the insulating layer 125 and insulating layer 127 can flatten this step difference and improve the coverage of the common layer 114 and the common electrode 115. Therefore, connection failures due to step breaks can be suppressed. In addition, it is possible to suppress the localized thinning of the thickness of the common electrode 115 due to the step difference and the resulting increase in electrical resistance.

[0589] The upper surface of the insulating layer 127 is preferably flat. The upper surface of the insulating layer 127 may include at least one of a flat surface, a convex surface, and a concave surface. For example, the upper surface of the insulating layer 127 is preferably a convex surface with a large radius of curvature.

[0590] The insulating layer 125 can be a single-layer structure or a laminated structure of two or more layers. Preferably, the insulating layer 125 has one or more inorganic insulating layers. The insulating layer 125 can be made from the materials listed for insulating layer 106 and insulating layer 105. In particular, aluminum oxide is preferred because it has a high selectivity ratio with the EL layer during etching and has the function of protecting the EL layer during the formation of the insulating layer 127. In particular, by applying an inorganic insulating layer such as an aluminum oxide film, hafnium oxide film, or silicon oxide film formed by the ALD method to the insulating layer 125, an insulating layer 125 can be formed with fewer pinholes and excellent function in protecting the EL layer. The insulating layer 125 may also be a laminated structure of a film formed by the ALD method and a film formed by the sputtering method. For example, the insulating layer 125 may be a laminated s...

Claims

It comprises a first transistor, a metal oxide layer, and a first insulating layer. The first transistor has a first semiconductor layer, a second insulating layer, and a first conductive layer. The first semiconductor layer has a first region that overlaps with the first conductive layer via the second insulating layer, and a second region and a third region that sandwich the first region. The metal oxide layer is located on the first insulating layer, The second region has regions that are in contact with the upper surface and side surface of the metal oxide layer, The first region and the third region each have a region that is in contact with the upper surface of the first insulating layer. The first semiconductor layer has a first metal oxide, The metal oxide layer has a second metal oxide, The first metal oxide and the second metal oxide each contain indium, A semiconductor device wherein the indium content in the first metal oxide is higher than the indium content in the second metal oxide. 　 In claim 1, The first metal oxide is indium oxide, The second region has a first crystal grain, The crystal orientation of the first crystal grain with respect to the upper surface of the first insulating layer is <111>, The second metal oxide comprises gallium and tin, or both, and zinc. The metal oxide layer has a second crystal grain, A semiconductor device wherein the c-axis of the second crystal grain is perpendicular or approximately perpendicular to the upper surface of the first insulating layer. 　 In claim 2, A semiconductor device wherein the crystal structure of the second crystal grain is hexagonal or trigonal. 　 In any one of claims 1 to 3, It has a second transistor, The second transistor comprises a second semiconductor layer, a second insulating layer, and a second conductive layer. The second semiconductor layer has a fourth region that overlaps with the second conductive layer via the second insulating layer, and a fifth region and a sixth region that sandwich the fourth region. The second semiconductor layer has a region that is in contact with the upper surface of the first insulating layer. The semiconductor device comprises the second semiconductor layer and the second metal oxide. 　 In claim 4, A semiconductor device wherein the thickness of the second semiconductor layer is greater than the thickness of the first semiconductor layer. 　 In claim 5, A semiconductor device wherein the thickness of the region in the metal oxide layer that is in contact with the first semiconductor layer is greater than the thickness of the second semiconductor layer. 　 In claim 4, The second region, the third region, the fifth region, and the sixth region each contain the first element, The first element is one or more of hydrogen, boron, and phosphorus. The concentrations of the first element in the second region and the third region are each higher than the concentration of the first element in the first region. A semiconductor device wherein the concentration of the first element in the fifth region and the sixth region is higher than the concentration of the first element in the fourth region. 　 In claim 7, The metal oxide layer has a seventh region that overlaps with the first semiconductor layer and an eighth region that does not overlap with the first semiconductor layer. The eighth region has the first element, A semiconductor device wherein the concentration of the first element in the eighth region is higher than the concentration of the first element in the seventh region. It has a display element and a pixel circuit, The pixel circuit comprises a first transistor, a second transistor, a metal oxide layer, and a first insulating layer. The first transistor has a first semiconductor layer, a second insulating layer, and a first conductive layer. The first semiconductor layer has a first region that overlaps with the first conductive layer via the second insulating layer, and a second region and a third region that sandwich the first region. The second transistor comprises a second semiconductor layer, a second insulating layer, and a second conductive layer. The second semiconductor layer has a region that overlaps with the second conductive layer via the second insulating layer. The metal oxide layer and the second semiconductor layer are each located on the first insulating layer. The second region has regions that are in contact with the upper surface and side surface of the metal oxide layer, The first region and the third region each have a region that is in contact with the upper surface of the first insulating layer. The first semiconductor layer has a first metal oxide, The metal oxide layer and the second semiconductor layer each have a second metal oxide, The first metal oxide and the second metal oxide each contain indium, A display device wherein the indium content in the first metal oxide is higher than the indium content in the second metal oxide. 　 In claim 9, The first metal oxide is indium oxide, The second region has a first crystal grain, The crystal orientation of the first crystal grain with respect to the upper surface of the first insulating layer is <111>, The second metal oxide comprises gallium and tin, or both, and zinc. The metal oxide layer has a second crystal grain, A display device in which the c-axis of the second crystal grain is perpendicular or approximately perpendicular to the upper surface of the first insulating layer. 　 In claim 10, A display device wherein the crystal structure of the second crystal grain is hexagonal or trigonal. 　 In any one of claims 9 to 11, A display device wherein the thickness of the second semiconductor layer is greater than the thickness of the first semiconductor layer. 　 In claim 12, A display device wherein the thickness of the region in the metal oxide layer that is in contact with the first semiconductor layer is greater than the thickness of the second semiconductor layer.

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