Semiconductor device and method for manufacturing semiconductor device

Abstract

Provided is a highly reliable semiconductor device. The semiconductor device includes a transistor that uses indium oxide as a semiconductor layer, and an insulating layer. The insulating layer has a region in contact with an upper surface of the semiconductor layer. The insulating layer has first to third openings each having a region overlapping the semiconductor layer. The inside of the first opening is provided with a gate insulating layer and a gate electrode. A source electrode is provided inside the second opening, and a drain electrode is provided inside the third opening. The concentration of an impurity element in a region of the semiconductor layer in contact with the source electrode is higher than each of the concentration of the impurity element in the source electrode and the concentration of the impurity element in a channel formation region. The same also applies to the drain electrode. The impurity element is supplied after formation of the second and third openings so that the impurity element reaches the semiconductor layer.

Description

Semiconductor device and method for manufacturing a semiconductor device.

[0001] One aspect of the present invention relates to a semiconductor device, a memory device, and an electronic device. Another aspect of the present invention relates to a method for manufacturing a semiconductor device.

[0002] It should be noted that one aspect of the present invention is not limited to the above-mentioned technical field. Examples of technical fields of one aspect of the present invention include semiconductor devices, display devices, light-emitting devices, energy storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), methods for driving them, or methods for manufacturing them.

[0003] In this specification, a semiconductor device refers to a device that utilizes semiconductor properties, including circuits containing semiconductor elements (transistors, diodes, photodiodes, etc.), and devices having such circuits. It also refers to any device that can function by utilizing semiconductor properties. For example, integrated circuits, chips equipped with integrated circuits, and electronic components with chips housed in packages are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, and electronic devices are themselves semiconductor devices, and may each have semiconductor devices.

[0004] A technology for constructing transistors using semiconductor thin films formed on substrates with insulating surfaces is attracting attention. These transistors are widely applied in electronic devices such as integrated circuits (ICs) and display devices. While silicon-based semiconductor materials are widely known as semiconductor materials applicable to transistors, oxide semiconductors are also gaining attention as other materials.

[0005] Furthermore, transistors using oxide semiconductors are known to have extremely low leakage current in the off state. For example, Patent Document 1 discloses a low-power CPU (Central Processing Unit) that utilizes the low leakage current characteristic of transistors using oxide semiconductors. Also, for example, Patent Document 2 discloses a memory device that can retain stored data for a long period of time by utilizing the low leakage current characteristic of transistors using oxide semiconductors.

[0006] Furthermore, examples of oxide semiconductors applicable to the active layer of a transistor include indium oxide and indium gallium zinc oxide. Non-patent document 1 discloses the use of indium oxide in thin-film transistors. Non-patent document 2 discloses a thin-film transistor using hydride polycrystalline indium oxide formed by low-temperature solid-phase crystallization as the active layer.

[0007] Japanese Patent Publication No. 2012-257187 Japanese Patent Publication No. 2011-151383

[0008] Dhananjay and C. W. Chu, Realization of In▲2▼O▲3▼ thin film transistors through reactive evaporation process. Appl. Phys. Lett. 91, 132111 (2007). Y. Magari et al. Takashi Koida, “High-mobility hydrogenerated polycrystalline In2O3 (In2O3:H) thin-film transistors”, Nature Communications, 13, 1078 (2022) Takashi Koida, “High-mobility transparent conductive film”, National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Generation Research Results Presentation Meeting 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf>

[0009] One aspect of the present invention aims to provide a highly reliable semiconductor device or memory device. One aspect of the present invention aims to provide a semiconductor device or memory device having a transistor with good electrical characteristics. One aspect of the present invention aims to provide a semiconductor device or memory device with low manufacturing costs. One aspect of the present invention aims to provide a semiconductor device or memory device having a transistor with a large on-current. One aspect of the present invention aims to provide a semiconductor device or memory device with a high operating speed. One aspect of the present invention aims to provide a transistor, semiconductor device, or memory device that can be miniaturized or highly integrated. One aspect of the present invention aims to provide a semiconductor device or memory device with low power consumption. One aspect of the present invention aims to provide a novel transistor, semiconductor device, or memory device.

[0010] One aspect of the present invention aims to provide a method for manufacturing a highly reliable semiconductor device or memory device. One aspect of the present invention aims to provide a method for manufacturing a semiconductor device or memory device having a transistor with good electrical characteristics. One aspect of the present invention aims to provide a method for manufacturing a semiconductor device or memory device with a high yield. One aspect of the present invention aims to provide a method for manufacturing a semiconductor device or memory device with high productivity. One aspect of the present invention aims to provide a method for manufacturing a semiconductor device or memory device having a transistor with a large on-current. One aspect of the present invention aims to provide a method for manufacturing a semiconductor device or memory device with a fast operating speed. One aspect of the present invention aims to provide a method for manufacturing a transistor, semiconductor device, or memory device that can be miniaturized or highly integrated. One aspect of the present invention aims to provide a method for manufacturing a semiconductor device or memory device with low power consumption. One aspect of the present invention aims to provide a novel method for manufacturing a transistor, semiconductor device, or memory device.

[0011] Furthermore, the description of these problems does not preclude the existence of other problems. One aspect of the present invention does not necessarily have to solve all of these problems. It is possible to extract other problems from the description in the specification, drawings, and claims.

[0012] One aspect of the present invention comprises a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a first insulating layer, and a second insulating layer, wherein the first insulating layer has a region in contact with the upper surface of the semiconductor layer, and the first insulating layer has a first opening, a second opening, and a third opening, each having a region overlapping with the semiconductor layer, the first opening has a region located between the second opening and the third opening, the second insulating layer is provided inside the first opening so as to have a region in contact with the semiconductor layer, the first conductive layer is provided on the second insulating layer so as to have a region located inside the first opening, the second conductive layer is provided inside the second opening so as to have a region in contact with the upper surface of the semiconductor layer, and the third conductive layer The semiconductor device is provided inside the third opening such that the electrode layer has a region in contact with the upper surface of the semiconductor layer, and the semiconductor layer has a first region in contact with the second conductive layer, a second region in contact with the third conductive layer, and a third region overlapping with the first conductive layer, wherein the concentration of the first element in the first region is higher than the concentration of the first element in the second conductive layer and the concentration of the first element in the third region, and the concentration of the first element in the second region is higher than the concentration of the first element in the third conductive layer and the concentration of the first element in the third region, and the semiconductor layer has indium oxide, and the first element is one or more of boron, phosphorus, aluminum, magnesium, and silicon.

[0013] Alternatively, in the above embodiment, the first element may be boron.

[0014] Alternatively, in the above embodiment, the first region and the second region each have a concentration of the first element of 1 × 10⁻⁶ １９ cm −３ It may have a region that is greater than or equal to the above.

[0015] Alternatively, in the above embodiment, the third region has a concentration of the first element of 1 × 10⁻⁶ １８ cm−３ It may have the following areas:

[0016] Alternatively, in the above embodiment, the concentration of the first element between the first region and the third region may be less than the concentration of the first element in the first region and higher than the concentration of the first element in the third region.

[0017] Alternatively, one aspect of the present invention is a method for manufacturing a semiconductor device, comprising: a first step of forming a semiconductor layer and a first insulating layer having a region in contact with the upper surface of the semiconductor layer; a second step of processing the first insulating layer to form a first opening in the first insulating layer that reaches the semiconductor layer; a third step of forming a second insulating layer and a first conductive layer on the second insulating layer such that a region is located inside the first opening; a fourth step of processing the first insulating layer to form a second opening and a third opening in the first insulating layer that reach the semiconductor layer and are opposite to each other with the first opening in between; a fifth step of supplying a first element to a first region overlapping with the second opening of the semiconductor layer and a second region overlapping with the third opening; and a sixth step of forming a second conductive layer in contact with the first region and a third conductive layer in contact with the second region.

[0018] Alternatively, in the above embodiment, the first element may be one or more of boron, phosphorus, aluminum, magnesium, and silicon.

[0019] Alternatively, in the above embodiment, the supply of the first element may be carried out using ion implantation or ion doping.

[0020] Alternatively, in the above embodiment, the semiconductor layer may be formed in the first step to have indium oxide.

[0021] According to one aspect of the present invention, a highly reliable semiconductor device or memory device can be provided. According to one aspect of the present invention, a semiconductor device or memory device having a transistor with good electrical characteristics can be provided. According to one aspect of the present invention, a semiconductor device or memory device with low manufacturing costs can be provided. According to one aspect of the present invention, a semiconductor device or memory device having a transistor with a large on-current can be provided. According to one aspect of the present invention, a semiconductor device or memory device with a fast operating speed can be provided. According to one aspect of the present invention, a transistor, semiconductor device, or memory device that can be miniaturized or highly integrated can be provided. According to one aspect of the present invention, a semiconductor device or memory device with low power consumption can be provided. According to one aspect of the present invention, a novel transistor, semiconductor device, or memory device can be provided.

[0022] According to one aspect of the present invention, a method for manufacturing a highly reliable semiconductor device or memory device can be provided. According to one aspect of the present invention, a method for manufacturing a semiconductor device or memory device having a transistor with good electrical characteristics can be provided. According to one aspect of the present invention, a method for manufacturing a semiconductor device or memory device with a high yield can be provided. According to one aspect of the present invention, a method for manufacturing a semiconductor device or memory device with high productivity can be provided. According to one aspect of the present invention, a method for manufacturing a semiconductor device or memory device having a transistor with a large on-current can be provided. According to one aspect of the present invention, a method for manufacturing a semiconductor device or memory device with a fast operating speed can be provided. According to one aspect of the present invention, a method for manufacturing a transistor, semiconductor device, or memory device that can be miniaturized or highly integrated can be provided. According to one aspect of the present invention, a method for manufacturing a semiconductor device or memory device with low power consumption can be provided. According to one aspect of the present invention, a method for manufacturing a novel transistor, semiconductor device, or memory device can be provided.

[0023] Furthermore, the description of these effects does not preclude the existence of other effects. One aspect of the present invention does not necessarily have to possess all of these effects. Other effects can be extracted from the description, drawings, and claims.

[0024] Figures 1A and 1B are plan views showing an example of the configuration of a semiconductor device. Figures 2A and 2B are cross-sectional views showing an example of the configuration of a semiconductor device. Figures 3A and 3B are cross-sectional views showing an example of the configuration of a semiconductor device. Figure 4A is a plan view showing an example of the configuration of a semiconductor device. Figure 4B is a cross-sectional view showing an example of the configuration of a semiconductor device. Figure 5 is a plan view showing an example of the configuration of a semiconductor device. Figures 6A, 6B, and 6C are cross-sectional views showing an example of the configuration of a semiconductor device. Figures 7A, 7B, and 7C are cross-sectional views showing an example of the configuration of a semiconductor device. Figures 8A and 8B are cross-sectional views showing an example of the configuration of a semiconductor device. Figure 9 is a cross-sectional view showing an example of the configuration of a semiconductor device. Figures 10A, 10B, and 10C are cross-sectional views showing an example of the configuration of a semiconductor device. Figure 11A is a plan view showing an example of the configuration of a semiconductor device. Figure 11B is a cross-sectional view showing an example of the configuration of a semiconductor device. Figures 12A and 12B are cross-sectional views showing an example of the configuration of a semiconductor device. Figures 13A, 13B, 13C, 13D, and 13E are cross-sectional views showing an example of a method for manufacturing a semiconductor device. Figures 14A, 14B, and 14C are cross-sectional views showing an example of a semiconductor device fabrication method. Figures 15A, 15B, and 15C are cross-sectional views showing an example of a semiconductor device fabrication method. Figures 16A and 16B are cross-sectional views showing an example of a semiconductor device fabrication method. Figures 17A and 17B are diagrams illustrating the carrier concentration dependence of Hall mobility. Figure 17C is a cross-sectional view illustrating an indium oxide film. Figure 18 is a block diagram illustrating an example configuration of a semiconductor device. Figures 19A, 19B, 19C, 19D, 19E, 19F, and 19G are diagrams illustrating an example circuit configuration of a memory cell. Figure 20 is a cross-sectional view showing an example of a semiconductor device. Figures 21A and 21B are perspective views illustrating an example configuration of a semiconductor device. Figure 22 is a cross-sectional view showing an example of a semiconductor device. Figure 23 is a block diagram illustrating a CPU. Figures 24A and 24B are perspective views of a semiconductor device. Figures 25A and 25B are perspective views of a semiconductor device. Figure 26 is a conceptual diagram illustrating the hierarchy of memory devices. Figures 27A and 27B show examples of electronic components. Figures 28A, 28B, and 28C show examples of large-scale computers. Figure 28D shows an example of space equipment.Figure 28E shows an example of a storage system applicable to a data center.

[0025] Embodiments will be described in detail with reference to the drawings. However, it will be readily apparent to those skilled in the art that the present invention is not limited to the following description, and that its form and details can be modified in various ways without departing from the spirit and scope of the present invention. Accordingly, the present invention shall not be construed as being limited to the descriptions of the embodiments shown below.

[0026] In the invention described below, the same reference numerals are used in common across different drawings for identical parts or parts having similar functions, and repeated explanations are omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used, and reference numerals may not be assigned.

[0027] Furthermore, the position, size, and scope of each component shown in the drawings may not represent the actual position, size, and scope for the sake of ease of understanding. Therefore, the disclosed invention is not necessarily limited to the position, size, and scope disclosed in the drawings.

[0028] In this specification, ordinal numbers such as "first," "second," etc., are used to avoid confusion of constituent elements and do not indicate any order or rank, such as process order, layering order, or arrangement order. Furthermore, even if a term in this specification does not have an ordinal number, an ordinal number may be added in the claims to avoid confusion of constituent elements. Also, even if a term in this specification has an ordinal number, a different ordinal number may be added in the claims. Furthermore, even if a term in this specification has an ordinal number, the ordinal number may be omitted in the claims.

[0029] Furthermore, a transistor is a type of semiconductor device that can perform functions such as amplifying current or voltage, and switching operations that control conduction or non-conductivity. Transistors in this specification include IGFETs (Insulated Gate Field Effect Transistors) and thin-film transistors (TFTs).

[0030] In this specification, transistors using an oxide semiconductor or metal oxide in the semiconductor layer, and transistors having an oxide semiconductor or metal oxide in the channel formation region, may be referred to as OS (Oxide Semiconductor) transistors. Furthermore, transistors having silicon in the channel formation region may be referred to as Si transistors.

[0031] Furthermore, in this specification, a transistor is defined as an element having at least three terminals, including a gate, a drain, and a source. It also has a channel-forming region (also called a channel-forming region) between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), through which current can flow between the source and the drain. In this specification, the channel-forming region refers to the region through which current primarily flows.

[0032] Furthermore, the functions of "source" and "drain" may be reversed when transistors of different polarities are used, or when the direction of current changes during circuit operation. For this reason, in this specification, the terms "source" and "drain" may be used interchangeably.

[0033] In semiconductors, impurities refer to elements other than the main components that make up the semiconductor. For example, elements with a concentration of less than 0.1 atomic percent can be considered impurities. The presence of impurities can cause, for example, an increase in the defect level density of the semiconductor or a decrease in crystallinity. When the semiconductor is an oxide semiconductor, impurities that alter the properties of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor. Specifically, these include, for example, hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Water can also function as an impurity. Furthermore, for example, the inclusion of impurities can cause oxygen vacancies (V) in the oxide semiconductor. Ｏ (Also known as) may form.

[0034] In addition, in this specification and the like, an oxynitride refers to a material having a higher oxygen content than nitrogen in its composition. A nitride oxide refers to a material having a higher nitrogen content than oxygen in its composition. For example, when silicon oxynitride is described, it refers to a material having a higher oxygen content than nitrogen in its composition, and when silicon nitride oxide is described, it indicates a material having a higher nitrogen content than oxygen in its composition.

[0035] For the analysis of the content of elements such as hydrogen, oxygen, carbon, or nitrogen contained in the film, for example, secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry) or X-ray photoelectron spectroscopy (XPS: X-ray Photoelectron Spectroscopy or ESCA: Electron Spectroscopy for Chemical Analysis) can be used. When the content rate of the target element is high (for example, 0.5 atomic% or more, or 1 atomic% or more), XPS is suitable. On the other hand, when the content rate of the target element is low (for example, 0.5 atomic% or less, or 1 atomic% or less), SIMS is suitable. When comparing the content of elements, it is more preferable to perform a combined analysis using both SIMS and XPS analysis methods.

[0036] In addition, in this specification and the like, the content rate indicates the ratio of the components contained in the film. For example, when the oxide semiconductor layer contains metal element X, metal element Y, and metal element Z, and the number of atoms of metal element X, metal element Y, and metal element Z contained in the oxide semiconductor layer are A Ｘ , A Ｙ , A Ｚ respectively, the content rate of metal element X can be expressed as A Ｘ / (A Ｘ + A Ｙ + A Ｚ ). Also, when the ratio of the number of atoms (atomic ratio) of metal element X, metal element Y, and metal element Z in the oxide semiconductor layer is B Ｘ : B Ｙ : B Ｚ respectively, the content rate of metal element X is B Ｘ / (B Ｘ + B Ｙ + BＺ This can be shown by:

[0037] It should be noted that the terms "film" and "layer" can be interchanged depending on the context or situation. For example, the term "conductive layer" can be changed to "conductive film." Or, for example, the term "insulating film" can be changed to "insulating layer."

[0038] In this specification, space groups are expressed using international notation (or Hermann-Mauguin notation) in short notation. Crystal planes and crystal orientations are expressed using Miller indices. In crystallography, space groups, crystal planes, and crystal orientations are expressed by superscripting numbers, but in this specification, due to formatting constraints, a minus sign (-) may be placed before the number instead of a superscript. Individual orientations within a crystal are represented by [ ], collective orientations representing all equivalent orientations are represented by < >, individual crystal planes are represented by ( ), and collective planes with equivalent symmetry are represented by {}.

[0039] Furthermore, in this specification, "parallel" means a state in which two lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, the case of -5 degrees or more and 5 degrees or less is also included. Furthermore, "approximately parallel" means a state in which two lines are arranged at an angle of -20 degrees or more and 20 degrees or less. Furthermore, "perpendicular" means a state in which two lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, the case of 85 degrees or more and 95 degrees or less is also included. Furthermore, "approximately perpendicular" means a state in which two lines are arranged at an angle of 70 degrees or more and 110 degrees or less.

[0040] Furthermore, in this specification, openings also include, for example, grooves, slits, and the like.

[0041] In this specification, "connection" includes, for example, "electrical connection." The term "electrical connection" is sometimes used to describe the connection relationship between circuit elements as a physical object. Furthermore, "electrical connection" includes both "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the use of circuit elements (e.g., transistors, switches, etc.; however, wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected through one or more circuit elements.

[0042] For example, assuming a circuit including A and B is in operation, if there is a timing during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then it can be defined that "A and B are indirectly connected" as physical objects. Furthermore, even if there is a timing during the circuit's operation when no electrical signals are exchanged or potential interactions occur between A and B, if there is a timing during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then it can be defined that "A and B are indirectly connected."

[0043] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where "A and B are not indirectly connected" is when an insulator is interposed in the path from A to B. Specifically, this includes cases where a capacitive element is connected between A and B, or where the gate insulating layer of a transistor is interposed between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of a transistor are indirectly connected."

[0044] Another example of a situation where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via source and drain in the path from A to B, and a constant potential V is supplied from a power supply, GND, etc., to the nodes between the transistors.

[0045] In this specification, unless otherwise specified, off-current refers to the source-drain leakage current when the transistor is in the off state (also called the non-conducting state or cutoff state). Unless otherwise specified, the off state refers to the state in an n-channel transistor where the voltage Vgs between the gate and source is lower than the threshold voltage Vth (in a p-channel transistor, it is higher than Vth).

[0046] In this specification, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined with respect to the substrate surface or the surface to be formed. For example, it is preferable to have a region in which the angle (also called the taper angle) between the inclined side surface and the substrate surface or the surface to be formed is greater than 0 degrees and less than 90 degrees. The side surface of the structure, the substrate surface, and the surface to be formed do not necessarily have to be perfectly flat, and may be substantially planar with a small curvature, or substantially planar with fine irregularities.

[0047] In this specification, when it is stated that A is located on B, at least a portion of A is located on B. Therefore, for example, this can be rephrased as A has a region located on B. Similarly, when it is stated that A is adjacent to B, or A overlaps with B, at least a portion of A is adjacent to B, or overlaps with B. Therefore, for example, this can be rephrased as A has a region adjacent to B, or A has a region overlapping with B. Similarly, when it is stated in this specification, when it is stated that A covers B, at least a portion of A covers B. Therefore, for example, this can be rephrased as A has a region covering B.

[0048] In this specification, "island-like" refers to a state in which two or more layers made of the same material and formed in the same process are physically separated.

[0049] (Embodiment 1) This embodiment describes a semiconductor device according to one aspect of the present invention.

[0050] One aspect of the present invention relates to a transistor having a metal oxide semiconductor layer, and a semiconductor device having the transistor. When a metal oxide (also called an oxide semiconductor) that functions as a semiconductor is used as the semiconductor layer, the higher the ratio of the number of indium atoms to the sum of the number of atoms of all metal elements contained in the metal oxide, the higher the field-effect mobility of the transistor can be. Therefore, by using indium oxide as the metal oxide in the semiconductor layer, the transistor can obtain a large on-current and high frequency characteristics. Consequently, a semiconductor device with a high operating speed can be realized.

[0051] In one embodiment of the present invention, an insulating layer is provided such that it has a region in contact with the upper surface of the semiconductor layer. The insulating layer can be provided so as to cover the upper and side surfaces of the semiconductor layer.

[0052] The insulating layer has a first opening, a second opening, and a third opening. Each of the first to third openings has a region that overlaps with the semiconductor layer. The first opening has a region located between the second and third openings.

[0053] Inside the first opening, a gate insulating layer and a gate electrode of the transistor are provided. The gate insulating layer has a region in contact with the semiconductor layer. The gate electrode is provided on the gate insulating layer.

[0054] The source electrode of the transistor is provided inside the second opening. The drain electrode of the transistor is provided inside the third opening. The source electrode and the drain electrode have a region that is in contact with the upper surface of the semiconductor layer.

[0055] The regions of the semiconductor layer in contact with the source electrode and the regions in contact with the drain electrode contain impurity elements. These regions containing impurity elements are designated as the source region and the drain region, respectively. The concentration of impurity elements in the source region is higher than that of the source electrode of the transistor and the channel formation region. Similarly, the concentration of impurity elements in the drain region is higher than that of the drain electrode of the transistor and the channel formation region. The impurity elements can be, for example, one or more of boron, phosphorus, aluminum, magnesium, and silicon.

[0056] In a method for manufacturing a semiconductor device according to one aspect of the present invention, first, an insulating layer is formed having a region in contact with the upper surface of a semiconductor layer, and then a first opening reaching the semiconductor layer is formed in the insulating layer. Subsequently, a gate insulating layer and a gate electrode of a transistor are formed having a region located inside the first opening. After that, a second opening and a third opening are formed in the insulating layer, reaching the semiconductor layer and facing each other with the first opening in between.

[0057] Then, after forming the second and third openings, impurity elements are supplied to the semiconductor layer. This forms a source region in the area overlapping with the second opening of the semiconductor layer and a drain region in the area overlapping with the third opening. The impurity elements can be supplied to the semiconductor layer using, for example, ion implantation or ion doping.

[0058] Subsequently, a source electrode is formed inside the second opening, and a drain electrode is formed inside the third opening. Through this process, a semiconductor device according to one embodiment of the present invention can be fabricated.

[0059] As described above, in one aspect of the present invention, impurity elements are supplied to the semiconductor layer after the gate insulating layer, gate electrode, second opening, and third opening are formed. This makes it possible to increase the distance between the source region and the channel formation region, and the distance between the drain region and the channel formation region, compared to, for example, the case where the gate insulating layer and gate electrode are formed after the formation of the semiconductor layer without forming the insulating layer described above, and impurity elements are supplied by self-alignment using the gate electrode as a mask. This suppresses the incorporation of impurity elements into the channel formation region of the transistor. Therefore, for example, the formation of oxygen vacancies in the channel formation region of the transistor can be suppressed. Consequently, the effective channel length of the transistor is shortened, and it is possible to prevent it from becoming, for example, a normally-on transistor. As a result, in one aspect of the present invention, a transistor exhibiting good electrical characteristics and high reliability can be realized. Therefore, a highly reliable semiconductor device can be realized.

[0060] <Example of Semiconductor Device Configuration 1> Below, an example of the configuration of a semiconductor device according to one aspect of the present invention will be described.

[0061] Figure 1A is a plan view showing an example of the configuration of a semiconductor device according to one embodiment of the present invention. Figure 1B is a plan view in which some elements are omitted from Figure 1A. Note that some elements are omitted in Figure 1A for clarity. Some elements may also be omitted in subsequent plan views.

[0062] Figure 2A is a cross-sectional view between the dashed lines A1 and A2 shown in Figures 1A and 1B, and is also a cross-sectional view of transistor 200 in the channel length direction. Figure 2B is an enlarged view of region R shown in Figure 2A.

[0063] Figure 3A is a cross-sectional view between the dashed lines A3 and A4 shown in Figures 1A and 1B, and is also a cross-sectional view of transistor 200 in the channel width direction. Figure 3B is a cross-sectional view between the dashed lines A5 and A6 shown in Figures 1A and 1B.

[0064] The semiconductor device shown in Figures 1A to 3B includes an insulating layer 212 on a substrate (not shown), an insulating layer 214 on the insulating layer 212, a transistor 200, an insulating layer 216, an insulating layer 241a, and an insulating layer 241b on the insulating layer 214, an insulating layer 275 on the insulating layer 216, an insulating layer 280 on the insulating layer 275, an insulating layer 282 on the transistor 200 and on the insulating layer 280, an insulating layer 283 on the insulating layer 282, and an insulating layer 285 on the insulating layer 283. The insulating layers 212, 214, 216, 280, 282, 283, and 285 function as interlayer insulating layers. Here, the insulating layer 212 and the insulating layer 214 can be considered together as one insulating layer. Also, the insulating layer 221 and the insulating layer 222 can be considered together as one insulating layer. Furthermore, insulating layer 275 and insulating layer 280 can be considered together as a single insulating layer. In addition, insulating layer 282, insulating layer 283, and insulating layer 285 can be considered together as a single insulating layer.

[0065] [Transistor] The transistor 200 includes a conductive layer 205, an insulating layer 221 on the conductive layer 205, an insulating layer 222 on the insulating layer 221, an insulating layer 224 on the insulating layer 222, a semiconductor layer 230 on the insulating layer 224, an insulating layer 250, a conductive layer 245a, and a conductive layer 245b on the semiconductor layer 230, and a conductive layer 260 on the insulating layer 250. Here, Figures 1A to 3B show an example in which the insulating layer 224 and the semiconductor layer 230 are processed in an island shape.

[0066] The semiconductor layer 230 has an oxide semiconductor. Here, a transistor having an oxide semiconductor is called an OS transistor. In this specification, a semiconductor layer having an oxide semiconductor can be referred to as an oxide semiconductor layer. Also, since the semiconductor layer 230 has a metal oxide, the semiconductor layer 230 can be referred to as a metal oxide layer. In a semiconductor device according to one aspect of the present invention, for example, indium oxide can be used as the semiconductor layer 230.

[0067] When the semiconductor layer 230 is a metal oxide layer, the higher the ratio of indium atoms to the sum of the total number of atoms of all metal elements contained in the metal oxide layer, the higher the field-effect mobility of the transistor can be. Therefore, by using indium oxide as the semiconductor layer 230, the transistor 200 can obtain a large on-current and high frequency characteristics. Consequently, a semiconductor device with a high operating speed can be realized.

[0068] Furthermore, indium oxide films have higher oxygen and hydrogen permeability (diffusivity) compared to other metal oxide films. Therefore, indium oxide films are more effective at filling oxygen deficiencies compared to other metal oxide films. Also, hydrogen diffusing into the indium oxide film from the outside permeates the film, and hydrogen molecules (H) are released. ２ ) or water molecule (H ２ It is easily released as O). Therefore, by using indium oxide as the semiconductor layer 230, the electrical characteristics of the transistor 200 can be improved and its reliability can be increased. Thus, a highly reliable semiconductor device can be realized.

[0069] The semiconductor layer 230 preferably has crystalline properties. For example, the semiconductor layer 230 preferably has crystal grains. The particle size of the crystal grains in the semiconductor layer 230 is preferably, for example, 10 nm to 1 μm, 10 nm to 0.5 μm, or 10 nm to 100 nm. Alternatively, it is preferably, for example, 50 nm to 1 μm, 50 nm to 0.5 μm, or 50 nm to 100 nm. The crystalline properties of the semiconductor layer 230 suppress impurity diffusion within the semiconductor layer 230. Therefore, fluctuations in the electrical characteristics of the transistor 200 can be suppressed. Thus, a highly reliable semiconductor device can be realized. Specifically, the semiconductor layer 230 preferably has a polycrystalline structure, and more preferably a single-crystal structure.

[0070] By increasing the indium content in the crystal grains of the semiconductor layer 230, the crystal structure of the crystal grains becomes cubic, specifically a bixbite structure. For the semiconductor layer 230 to have crystal grains with a cubic crystal structure, the indium content in the crystal grains should be 70% or more and 100% or less, preferably 80% or more and 100% or less, more preferably 90% or more and 100% or less, and even more preferably 95% or more and 100% or less.

[0071] The conductive layer 260 functions as the first gate electrode of the transistor 200 (also called the upper gate electrode or top gate electrode). The insulating layer 250 functions as the first gate insulating layer of the transistor 200. At least a portion of the region of the semiconductor layer 230 that overlaps with the conductive layer 260 functions as the channel formation region 230i of the transistor 200.

[0072] The conductive layer 205 functions as the second gate electrode of the transistor 200 (also called the lower gate electrode or bottom gate electrode). The insulating layers 224, 222, and 221 each function as second gate insulating layers of the transistor 200. The conductive layer 245a functions as one of the source electrode and drain electrode of the transistor 200. The conductive layer 245b functions as the other of the source electrode and drain electrode of the transistor 200.

[0073] The insulating layer 275 has a region that is in contact with the upper surface of the semiconductor layer 230. The insulating layer 275 can be provided so as to cover the semiconductor layer 230. As mentioned above, the insulating layer 280 is provided on the insulating layer 275.

[0074] It is preferable to use an insulating material that releases oxygen when heat is applied to the insulating layer 280. During the semiconductor device manufacturing process, the heat applied causes the insulating layer 280 to release oxygen, which can then be supplied to the semiconductor layer 230 via the insulating layer 250. By supplying oxygen to the semiconductor layer 230, particularly to the channel formation region 230i, oxygen vacancies or defects where hydrogen has entered the oxygen vacancy (hereinafter referred to as V) can be formed. ＯThis reduces the H (also known as H). Therefore, the transistor 200 can be made into a transistor that exhibits good electrical characteristics and is highly reliable.

[0075] Since the insulating layer 280 functions as an interlayer insulating layer, it is preferable to use a material with a low dielectric constant. By using a material with a low dielectric constant for the interlayer insulating layer, parasitic capacitance between wirings can be reduced. Furthermore, it is preferable to reduce the concentration of impurities such as water and hydrogen in the insulating layer 280. This suppresses the incorporation of impurities such as hydrogen or water into the channel formation region 230i. For example, silicon oxide or silicon oxynitride can be used as the insulating layer 280.

[0076] The insulating layer 275 and the insulating layer 280 have an opening 289. Inside the opening 289, an insulating layer 250 and a conductive layer 260 are provided. The insulating layer 250 has a region in contact with the semiconductor layer 230. Specifically, the insulating layer 250 has a region in contact with the channel forming region 230i. In addition to the region in contact with the semiconductor layer 230 described above, the insulating layer 250 may also have a region in contact with the side surface of the opening 289 of the insulating layer 275, a region in contact with the side surface of the opening 289 of the insulating layer 280, a region in contact with the side surface of the insulating layer 224, and a region in contact with the upper surface of the insulating layer 222.

[0077] The insulating layer 250 preferably has the function of supplying oxygen to the semiconductor layer 230. The insulating layer 250 preferably has a region containing oxygen that is desorbed by heating (hereinafter sometimes referred to as excess oxygen). By the insulating layer having a region containing excess oxygen coming into contact with the semiconductor layer 230, oxygen can be supplied to the semiconductor layer 230. The oxygen supplied to the semiconductor layer 230 repairs oxygen vacancies and can reduce the amount of oxygen vacancies in the semiconductor layer 230. Examples of insulating materials that readily form regions containing excess oxygen include silicon oxide, silicon oxynitride, and silicon oxide with vacancies. Examples of insulating layers that readily form regions containing excess oxygen include silicon oxide films, silicon oxynitride films, and silicon oxide films with vacancies.

[0078] Furthermore, it is preferable that the insulating layer 250 has the function of capturing or fixing oxygen (also known as gettering). As mentioned above, the indium oxide film is a film with high oxygen permeability (diffusivity). Therefore, if the insulating layer 250 has the function of capturing or fixing oxygen, excess oxygen in the semiconductor layer 230 can diffuse into the insulating layer 250, and the oxygen can be captured or fixed therein.

[0079] When an excess amount of oxygen is supplied to the semiconductor layer 230, electron traps caused by the excess oxygen are formed in the insulating layer 250. This makes the OS transistor more susceptible to positive drift degradation in +GBT (Gate Bias-Temperature) stress tests. In other words, the amount of positive drift degradation in +GBT stress tests increases. This may reduce the reliability of the transistor 200.

[0080] As described above, if the insulating layer 250 has the function of capturing or fixing oxygen (also called gettering), it is possible to suppress positive drift degradation in the +GBT stress test caused by excess oxygen. Therefore, the electrical characteristics of the transistor 200 can be improved and its reliability can be increased. Thus, a highly reliable semiconductor device can be realized. Examples of insulating materials having the function of capturing or fixing oxygen include aluminum oxide, hafnium oxide, hafnium zirconium oxide, and oxides containing hafnium and silicon (hafnium silicate). Examples of insulating layers having the function of capturing or fixing oxygen include aluminum oxide film, hafnium oxide film, hafnium zirconium oxide film, and hafnium silicate film.

[0081] Furthermore, aluminum oxide films, hafnium oxide films, hafnium zirconium oxide films, and hafnium silicate films have the function of capturing or fixing hydrogen. As mentioned above, indium oxide films are films to which hydrogen easily moves. Therefore, because the insulating layer 250 has the function of capturing or fixing hydrogen, hydrogen in the semiconductor layer 230 can diffuse into the insulating layer 250 and be captured or fixed. Consequently, the hydrogen concentration in the semiconductor layer 230 (especially the hydrogen concentration in the channel formation region) can be reduced.

[0082] The conductive layer 260 is provided on the insulating layer 250 such that it has a region located inside the opening 289. In the examples shown in Figures 1A to 3A, the conductive layer 260 is provided so as to fill the opening 289. Figures 2A and 3A also show examples where the upper surface of the insulating layer 280, the upper end of the insulating layer 250, and the upper surface of the conductive layer 260 coincide or substantially coincide.

[0083] As shown in Figures 1A and 3A, it is preferable that the conductive layer 260 extends in the channel width direction of the transistor 200. With this configuration, when multiple transistors 200 are provided in the semiconductor device, the conductive layer 260 functions as wiring.

[0084] It is preferable to use a highly conductive material such as tungsten for the conductive layer 260. Furthermore, it is preferable to use a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing oxygen diffusion for the conductive layer 260. Examples of such conductive materials include conductive materials containing nitrogen (e.g., titanium nitride or tantalum nitride) and conductive materials containing oxygen (e.g., ruthenium oxide). This makes it possible to suppress a decrease in the conductivity of the conductive layer 260.

[0085] Furthermore, it is preferable to use a conductive material for the conductive layer 260 that contains the metal element contained in the semiconductor layer 230 and oxygen. For example, if the semiconductor layer 230 contains indium, one or more of the following can be used as the conductive layer 260: indium tin oxide (In-Sn oxide, also called ITO), indium zinc oxide (In-Zn oxide, also called IZO®), indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, and indium tin oxide containing silicon (also called ITSO). Alternatively, indium gallium zinc oxide containing nitrogen may be used. By using such materials, it may be possible to capture hydrogen contained in the semiconductor layer 230. Or, it may be possible to capture hydrogen that is mixed in from the outer insulating layer, etc.

[0086] The insulating layer 282 is located on the insulating layer 280, the insulating layer 250, and the conductive layer 260. As mentioned above, the insulating layer 283 is located on the insulating layer 282, and the insulating layer 285 is located on the insulating layer 283.

[0087] The insulating layers 275, 280, 282, 283, and 285 have openings 243a and 243b. The openings 243a and 243b have regions that overlap with the semiconductor layer 230 and are arranged to face each other with an opening 289 in between. In other words, the opening 289 has a region located between the openings 243a and 243b.

[0088] An insulating layer 241a and a conductive layer 245a are provided inside the opening 243a. An insulating layer 241b and a conductive layer 245b are provided inside the opening 243b. Here, Figure 1B omits the insulating layer 241a, insulating layer 241b, conductive layer 245a, and conductive layer 245b shown in Figure 1A.

[0089] Figures 1A and 1B show examples where the openings 243a and 243b have circular shapes in plan view. In this specification, "circular" is not limited to a perfect circle. Furthermore, the shapes of the openings 243a and 243b in plan view do not have to be circular; for example, they can be approximately circular shapes such as ellipses, polygonal shapes such as quadrilaterals, or polygonal shapes such as quadrilaterals with rounded corners.

[0090] In Figure 2A, the height of the opening 243a is defined as height H. ＣＨ This is indicated. Also, in Figures 1A, 1B, and 2A, the width of the opening 243a is shown as width W. ＣＨ This indicates the width W. ＣＨ If the shape of the opening 243a in plan view is circular, it can be, for example, the diameter as shown in Figures 1A and 1B. If the side wall of the opening 243a has a tapered shape and the width of the top surface and the width of the bottom surface are different, for example, the width of the bottom surface can be the width W. ＣＨ It can be done this way.

[0091] Here, height H ＣＨ width W ＣＨ The value obtained by dividing by is the aspect ratio of the opening 243a. That is, the aspect ratio of the opening 243a is H ＣＨ / W ＣＨ It can be shown as follows. Similarly, the height, width, and aspect ratio of the opening 243b can also be shown as follows, with respect to height H ＣＨ , width W ＣＨ , and H ＣＨ / W ＣＨ This can be shown as follows.

[0092] The insulating layer 241a may have a region in contact with the upper surface of the semiconductor layer 230, a region in contact with the side surface of the opening 243a of the insulating layer 275, a region in contact with the side surface of the opening 243a of the insulating layer 280, a region in contact with the side surface of the opening 243a of the insulating layer 282, a region in contact with the side surface of the opening 243a of the insulating layer 283, and a region in contact with the side surface of the opening 243a of the insulating layer 285. Similarly, the insulating layer 241b may have a region in contact with the upper surface of the semiconductor layer 230, a region in contact with the side surface of the opening 243b of the insulating layer 275, a region in contact with the side surface of the opening 243b of the insulating layer 280, a region in contact with the side surface of the opening 243b of the insulating layer 282, a region in contact with the side surface of the opening 243b of the insulating layer 283, and a region in contact with the side surface of the opening 243b of the insulating layer 285. The insulating layer 241a can be provided so as to cover the side wall of the opening 243a. The insulating layer 241b can be provided so as to cover the side wall of the opening 243b.

[0093] In this specification, the side wall of an opening refers to the side surface of the layer in which the opening is formed, on the interior side of the opening.

[0094] The conductive layer 245a is located inside the insulating layer 241a (on the opposite side of the side wall of the opening 243a). The conductive layer 245b is located inside the insulating layer 241b (on the opposite side of the side wall of the opening 243b). In other words, the insulating layer 241a is located between the side wall of the opening 243a and the conductive layer 245a. Similarly, the insulating layer 241b is located between the side wall of the opening 243b and the conductive layer 245b.

[0095] The conductive layers 245a and 245b have regions that are in contact with the upper surface of the semiconductor layer 230. This allows the conductive layer 245a to function as one of the source and drain electrodes of the transistor 200. The conductive layer 245b can also function as the other of the source and drain electrodes of the transistor 200.

[0096] In the example shown in Figure 2A, the conductive layer 245a is provided to fill the opening 243a. Also, in the examples shown in Figures 2A and 3B, the conductive layer 245b is provided to fill the opening 243b. For example, Figure 2A shows an example where the upper surface of the insulating layer 285, the upper end of the insulating layer 241a, the upper end of the insulating layer 241b, the upper surface of the conductive layer 245a, and the upper surface of the conductive layer 245b coincide or substantially coincide.

[0097] For example, silicon nitride can be used as the insulating layer 241a and insulating layer 241b. This prevents impurities such as water and hydrogen contained in the insulating layer 280 from mixing into the semiconductor layer 230 through the conductive layer 245a or conductive layer 245b. It also prevents oxygen contained in the insulating layer 280 from being absorbed by the conductive layer 245a and conductive layer 245b. Note that the insulating layers 241a and 241b do not need to be provided. In this case, the number of manufacturing steps for the semiconductor device can be reduced, and the productivity of the semiconductor device can be increased.

[0098] Furthermore, the insulating layer 241a and the insulating layer 241b may be in a laminated structure. In this case, it is preferable that the first insulating layer in contact with the side wall of the opening 243a or the side wall of the opening 243b and the second insulating layer inside it use a combination of an oxygen barrier insulating layer and a hydrogen barrier insulating layer.

[0099] The conductive layers 245a and 245b can be made from conductive materials described in the [Conductive Layer] section below. Preferably, the conductive layers 245a and 245b are made from conductive materials primarily composed of tungsten, copper, or aluminum. The conductive layers 245a and 245b may also be arranged in a laminated structure.

[0100] The semiconductor layer 230 has a low-resistance region 230na in the region overlapping with the opening 243a. The semiconductor layer 230 also has a low-resistance region 230nb in the region overlapping with the opening 243b. Here, the conductive layer 245a has a region in contact with the low-resistance region 230na. The conductive layer 245b also has a region in contact with the low-resistance region 230nb. The low-resistance region 230na functions as one of the source region and drain region of the transistor 200. The low-resistance region 230nb functions as the other of the source region and drain region of the transistor 200. The insulating layer 241a may also have a region in contact with the low-resistance region 230na. Similarly, the insulating layer 241b may also have a region in contact with the low-resistance region 230nb.

[0101] The electrical resistivity of the low-resistivity region 230na and the low-resistivity region 230nb is at least lower than the electrical resistivity of the channel-forming region 230i. A lower electrical resistivity is preferable for the low-resistivity region 230na and the low-resistivity region 230nb. For example, the electrical resistivity of the low-resistivity region 230na and the low-resistivity region 230nb is 1 × 10⁻¹⁶. −５ Ω・m or more 1×10 −３ It can be less than or equal to Ω·m.

[0102] The low-resistance region 230na and the low-resistance region 230mb contain impurity elements. Examples of impurity elements include typical nonmetallic elements other than hydrogen, typical metallic elements, and transition elements (transition metals). For example, elements such as boron, phosphorus, magnesium, aluminum, and silicon can be listed as impurity elements. The low-resistance region 230na and the low-resistance region 230mb may contain one or more of these elements as impurity elements.

[0103] In this specification, the impurity elements contained in the low-resistance region 230na and the low-resistance region 230mb may be referred to as the first element.

[0104] The concentration of impurity elements in the low-resistance region 230na is higher than the concentration of said impurity elements in the conductive layer 245a and in the channel-forming region 230i. Similarly, the concentration of impurity elements in the low-resistance region 230nb is higher than the concentration of said impurity elements in the conductive layer 245b and in the channel-forming region 230i. In the low-resistance region 230na and the low-resistance region 230nb, the concentration of said impurity elements is, for example, 1 × 10⁻¹⁵. １８ cm −３ The above 1 x 10 ２２ cm −３ The following is preferably 5 × 10 １８ cm −３ The above 5 x 10 ２１ cm −３ More specifically, 1 x 10 １９ cm −３ The above 1 x 10 ２１ cm −３ It is preferable that the following region be included. If multiple impurity elements are included, it is preferable that the concentration of each impurity element be within the above range.

[0105] By supplying the aforementioned impurity elements to the low-resistance region 230na and the low-resistance region 230nb, the impurity elements remove oxygen from these regions, creating oxygen deficiencies (V) in these regions. ＯA vacancy is created. Then, when this oxygen vacancy combines with hydrogen in the film, a carrier is generated, which makes it possible to reduce the resistance of the low-resistance region 230na and the low-resistance region 230nb. As a result, the low-resistance region 230na and the low-resistance region 230nb of the transistor 200 can be made to have lower resistance than the channel-forming region 230i. Therefore, the contact resistance between the low-resistance region 230na of the transistor 200 and the conductive layer 245a, and the contact resistance between the low-resistance region 230nb and the conductive layer 245b can be reduced, and the on-current of the transistor 200 can be increased. In particular, even if the main component of the semiconductor layer 230 (indium in the case of indium oxide) is different from the main components of the conductive layer 245a and the conductive layer 245b, by forming the low-resistance region 230na and the low-resistance region 230nb in the semiconductor layer 230, the above-mentioned contact resistance can be reduced, and the on-current of the transistor 200 can be increased. Furthermore, by increasing the on-current of transistor 200, transistor 200 can achieve high frequency characteristics. Therefore, a semiconductor device with high operating speed can be realized.

[0106] Here, if low-resistance regions 230na and 230nb are not formed in the semiconductor layer 230, it is preferable that the main components of the source electrode and drain electrode of the transistor be the same as the main components of the semiconductor layer 230. For example, if low-resistance regions 230na and 230nb are not formed in the semiconductor layer 230, and indium oxide is used as the semiconductor layer 230, ITO is used as the source electrode and drain electrode of the transistor. For example, an ITO film is provided between the semiconductor layer 230 and the conductive layer 245a, insulating layer 241a, and insulating layer 275 as one of the source electrode and drain electrode. Alternatively, an ITO film is provided between the semiconductor layer 230 and the conductive layer 245b, insulating layer 241b, and insulating layer 275 as the other of the source electrode and drain electrode.

[0107] If the main components of the source electrode and drain electrode are common to the main components of the semiconductor layer, the work functions of the source electrode and drain electrode can be made to approximately match those of the lower end of the conduction band of the semiconductor layer. This reduces the energy barrier between the source electrode and drain electrode and the semiconductor layer. Therefore, the contact resistance between the source electrode and the semiconductor layer, and the contact resistance between the drain electrode and the semiconductor layer can be reduced without forming a low-resistance region in the semiconductor layer.

[0108] However, if the main components of the source electrode and drain electrode are the same as the main components of the semiconductor layer, the etching selectivity ratio between the source electrode and drain electrode and the semiconductor layer will be lower than when the main components are different. Therefore, when forming the source electrode and drain electrode between the semiconductor layer 230 and the insulating layer 275, etc., the semiconductor layer 230 may be divided or deep recesses may be formed in the semiconductor layer 230 when processing the conductive film that will become the source electrode and drain electrode. Specifically, when removing the region that overlaps with the opening 289 of the conductive film using etching, the semiconductor layer 230 may be divided or deep recesses may be formed in the semiconductor layer 230.

[0109] In one embodiment of the present invention, a semiconductor device is formed after the formation of the openings 243a and 243b, by forming a low-resistance region 230na and a low-resistance region 230nb. This allows the conductive layer 245a to function as one of the source and drain electrodes of the transistor 200 without forming the aforementioned source and drain electrodes between the semiconductor layer 230 and the insulating layer 275, etc. Furthermore, the conductive layer 245b can function as the other of the source and drain electrodes of the transistor 200. As a result, the separation of the semiconductor layer 230 and the formation of deep recesses in the semiconductor layer 230 can be prevented, and a semiconductor device can be manufactured in a way that yields a high percentage of the product. Therefore, a semiconductor device with low manufacturing costs can be realized. In addition, the number of manufacturing steps for the semiconductor device can be reduced, and the productivity of the semiconductor device can be increased.

[0110] Furthermore, the aforementioned impurity elements may also be supplied to the channel formation region 230i in the semiconductor layer 230. Alternatively, due to the effects of heat during the manufacturing process, some of the impurity elements contained in the low-resistance region 230na and low-resistance region 230nb may diffuse into the channel formation region 230i. The concentration of impurity elements in the channel formation region 230i is preferably one-tenth or less of the concentration of impurity elements in the low-resistance region 230na and low-resistance region 230nb, and more preferably one-hundredth or less. The concentration of the impurity elements in the channel formation region 230i is, for example, 1 × 10⁻⁶ １８ cm −３ The following is preferably 1 x 10 １７ cm −３ More specifically, 1 x 10 １６ cm −３ More specifically, 1 x 10 １５ cm −３ More specifically, 1 x 10 １４ cm −３ More specifically, 1 x 10 １３ cm −３ More specifically, 1 x 10 １２ cm −３ More specifically, 1 x 10 １１ cm −３ More preferably 1 × 10 １０ cm −３ The following is possible. Furthermore, there are no particular limitations on the lower limit of the impurity concentration in the channel-forming region 230i, but for example, 1 × 10 −９ cm −３ It can be done this way.

[0111] For example, the concentration of impurity elements in the semiconductor layer 230 can be analyzed by analytical methods such as SIMS and XPS. When using XPS analysis, the concentration distribution in the depth direction can be determined by combining ion sputtering from the surface or back side with XPS analysis.

[0112] The low-resistance regions 230na and 230nb can be formed by supplying impurity elements to the semiconductor layer 230 after the formation of the openings 243a and 243b, and before the formation of the conductive layers 245a and 245b. The impurity elements can be supplied to the semiconductor layer, for example, by ion implantation or ion doping. Here, the supply of impurity elements to the semiconductor layer 230 is performed after the formation of the insulating layer 285. Therefore, the insulating layer 285 may have regions where the concentration of the impurity elements is higher than, for example, the channel-forming region 230i.

[0113] In transistor 200, the distance La between the low-resistance region 230na and the channel formation region 230i, and the distance Lb between the low-resistance region 230nb and the channel formation region 230i can be increased. Specifically, for example, the distances La and Lb can be increased compared to the case where, after the formation of the semiconductor layer, the gate insulating layer and the gate electrode are formed without forming an interlayer insulating layer, and impurity elements are supplied by self-alignment using the gate electrode as a mask. This suppresses the mixing of impurity elements contained in the low-resistance region 230na or the low-resistance region 230nb into the channel formation region 230i. Therefore, for example, the formation of oxygen vacancies in the channel formation region of the transistor can be suppressed. Consequently, the effective channel length of the transistor is shortened, and it is possible to prevent it from becoming a normally-on transistor, for example. As a result, the electrical characteristics of transistor 200 can be improved and its reliability can be increased. Therefore, a highly reliable semiconductor device can be realized.

[0114] The region R shown in Figure 2B includes the semiconductor layer 230, insulating layer 275, insulating layer 280, insulating layer 250, conductive layer 260, insulating layer 241a, and conductive layer 245a. Furthermore, within the semiconductor layer 230, region R includes the channel-forming region 230i and the low-resistance region 230na, as shown in Figure 2A. In Figure 2B, white circles represent oxygen (O), and dashed arrows indicate the direction of oxygen diffusion. Specifically, the oxygen shown by the dotted line is assumed to diffuse in the direction of the arrow. Black circles represent impurity elements, such as boron (B).

[0115] For example, boron is an element that readily combines with oxygen. Therefore, it is possible to combine oxygen contained in the channel-forming region 230i with impurity elements such as boron. Figure 2B shows an example in which some of the oxygen contained in the channel-forming region 230i diffuses into the low-resistance region 230na and combines with impurity elements such as boron. In Figure 2B, oxides of impurity elements are shown as pairs of white and black circles. For example, if the impurity element is boron, the oxide of the impurity element is B ２ O ３ This can be done. Note that in Figure 2B, for clarity, oxygen contained in the semiconductor layer 230 other than in the channel formation region 230i and the low-resistance region 230na has been omitted.

[0116] As mentioned above, if the semiconductor layer 230 contains excess oxygen, the reliability of the transistor 200 may decrease. In the transistor 200, for example, the excess oxygen contained in the channel formation region 230i can be deactivated by combining it with impurity elements. In this case, the electrical characteristics of the transistor 200 can be improved and its reliability can be increased. Therefore, a highly reliable semiconductor device can be realized.

[0117] As mentioned above, indium oxide films have higher oxygen permeability (diffusivity) compared to other metal oxide films. Therefore, by using indium oxide as the semiconductor layer 230, excess oxygen contained in the semiconductor layer 230 can easily diffuse into the low-resistance region 230na or the low-resistance region 230nb. As a result, for example, excess oxygen contained in the channel-forming region 230i can be easily deactivated by combining with impurity elements. Consequently, the reliability of semiconductor devices can be effectively improved.

[0118] The longer the distances La and Lb, the easier it becomes to suppress the incorporation of impurity elements contained in the low-resistance region 230na or low-resistance region 230nb into the channel-forming region 230i. This makes it easier to suppress the generation of oxygen vacancies in the channel-forming region 230i. On the other hand, if the distances La and Lb become too long, the on-current of the transistor 200 decreases.

[0119] Furthermore, the shorter the distances La and Lb, the easier it is for oxygen contained in the channel-forming region 230i to diffuse into the low-resistance region 230na or low-resistance region 230mb. Therefore, for example, excess oxygen contained in the channel-forming region 230i can be easily deactivated by combining with impurity elements. On the other hand, if the distances La and Lb are too short, too much oxygen may diffuse from the channel-forming region 230i into the low-resistance region 230na or low-resistance region 230mb. This may result in the creation of oxygen vacancies in the channel-forming region 230i.

[0120] Based on the above, it is preferable to design the distances La and Lb accordingly. Specifically, it is preferable that the distances La and Lb be as short as possible, within a range where no oxygen vacancies are generated in the channel formation region 230i.

[0121] Figure 2B shows an example in which the semiconductor layer 230 has a region 230nc between the low-resistance region 230na and the channel-forming region 230i. Region 230nc is a region where the concentration of impurity elements is less than the concentration of impurity elements in the low-resistance region 230na and higher than the concentration of impurity elements in the channel-forming region 230i. Region 230nc may include a region of the semiconductor layer 230 that is in contact with the insulating layer 275.

[0122] Region 230nc can function as an LDD (Lightly Doped Drain) region. This suppresses hot carrier degradation of transistor 200. Therefore, the electrical characteristics of transistor 200 can be improved and its reliability can be increased. Thus, a highly reliable semiconductor device can be realized. In addition, an LDD region may be formed not only between the low-resistance region 230na and the channel formation region 230i, but also between the low-resistance region 230nb and the channel formation region 230i. Transistor 200 is a transistor that can easily form an LDD region compared to, for example, a transistor in which the gate electrode described above is used as a mask and impurity elements are supplied by self-alignment.

[0123] As mentioned above, the insulating layer 280 can be made of an insulating material that releases oxygen when heat is applied. In this case, the insulating layer 280 contains oxygen, as shown in Figure 2B. The oxygen contained in the insulating layer 280 is supplied to the semiconductor layer 230 through the insulating layer 250, as indicated by the dashed arrow. By supplying oxygen from the insulating layer 280 to the semiconductor layer 230, particularly to the channel formation region 230i, oxygen deficiencies or V Ｏ H can be reduced. Therefore, the transistor 200 can be made into a transistor that exhibits good electrical characteristics and is highly reliable.

[0124] In addition, metal oxides other than indium oxide may be used for the semiconductor layer 230. Examples of metal oxides that can be used for the semiconductor layer 230 include tin oxide, zinc oxide, ITO, In-Zn oxide, indium titanium oxide (In-Ti oxide), indium tungsten oxide (In-W oxide, also called IWO), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide, indium gallium tin oxide, gallium zinc oxide (Ga-Zn oxide, also called GZO), aluminum zinc oxide (Al-Zn oxide, also called AZO), indium aluminum zinc oxide (In-Al-Zn oxide, also called IAZO), indium tin zinc oxide (In-Sn-Zn oxide, also called ITZO®), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also called IGZO), indium gallium tin zinc oxide, indium gallium aluminum zinc oxide, etc. Alternatively, ITSO, gallium tin oxide, aluminum tin oxide (Al-Sn oxide), etc., can be used. When using these, it is preferable that the film has at least crystalline properties, and more preferably that it has a single-crystal structure.

[0125] The conductive layer 205 is provided so as to be embedded in an opening formed in the insulating layer 216. The conductive layer 205 is provided so as to overlap with the semiconductor layer 230 and the conductive layer 260. As shown in Figures 1A, 1B, 2A, and 3A, it is preferable that the conductive layer 205 extends in the channel width direction of the transistor 200. With this configuration, when multiple transistors 200 are provided in the semiconductor device, the conductive layer 205 functions as wiring.

[0126] By independently changing the potential applied to the conductive layer 205, without linking it to the potential applied to the conductive layer 260, the threshold voltage (Vth) of the transistor 200 can be controlled. In particular, by applying a negative potential to the conductive layer 205, it is possible to increase the Vth of the transistor 200 and reduce the off-current. Therefore, applying a negative potential to the conductive layer 205 reduces the drain current when the potential applied to the conductive layer 260 is 0V compared to not applying a negative potential.

[0127] The conductive layer 205 can be made from a conductive material described in the [Conductive Layer] section below. Preferably, the conductive layer 205 is made from a conductive material mainly composed of tungsten, copper, or aluminum.

[0128] It is preferable to use an insulating material that releases oxygen when heat is applied for the insulating layer 224. For example, silicon oxide or silicon oxynitride is preferable for the insulating layer 224. When heat is applied during the semiconductor device manufacturing process, the insulating layer 224 releases oxygen, which can be supplied to the semiconductor layer 230. By supplying oxygen to the semiconductor layer 230, particularly the channel formation region 230i, oxygen deficiencies or V Ｏ H can be reduced. Therefore, the transistor 200 can be made into a transistor that exhibits good electrical characteristics and is highly reliable.

[0129] Furthermore, it is preferable to process the insulating layer 224 in an island shape, similar to the semiconductor layer 230. This ensures that when multiple transistors 200 are provided, each transistor 200 has an insulating layer 224 of approximately the same size. As a result, the amount of oxygen supplied from the insulating layer 224 to the semiconductor layer 230 in each transistor 200 is approximately the same. Therefore, variations in the electrical characteristics of the transistors 200 within the substrate surface can be suppressed. Also, by processing the insulating layer 224 in an island shape, at least a portion of the lower surface of the conductive layer 260 can be provided below the lower surface of the semiconductor layer 230 (see Figure 3A). This allows the conductive layer 260 to be provided facing the upper and side surfaces of the semiconductor layer 230, so that the electric field of the conductive layer 260 can act on the upper and side surfaces of the semiconductor layer 230.

[0130] It is preferable that at least one of the insulating layers 212, 214, 221, 222, 275, 282, and 283 functions as a barrier insulating layer against hydrogen. It is also preferable that at least one of the insulating layers 212, 214, 221, 222, 275, 282, and 283 functions as a barrier insulating layer against impurities. Furthermore, it is preferable that at least one of the insulating layers 212, 214, 221, 222, 275, 282, and 283 functions as a barrier insulating layer against oxygen. Note that it is not necessarily required to provide all of the insulating layers 212, 214, 221, 222, 275, 282, and 283. If sufficient barrier properties are provided against hydrogen, impurities, oxygen, etc., the insulating layers can be appropriately selected from insulating layers 212, 214, 221, 222, 275, 282, and 283. For example, the insulating layer 214 can be omitted, and the insulating layer 216 and conductive layer 205 can be formed in contact with the upper surface of the insulating layer 212.

[0131] In this specification, the term "barrier insulating layer" refers to an insulating layer that has barrier properties. Furthermore, "barrier property" refers to the property of making it difficult for the corresponding substance to diffuse (also referred to as the property of making it difficult for the corresponding substance to permeate, the property of having low permeability to the corresponding substance, or the function of suppressing the diffusion of the corresponding substance). When hydrogen is described as a corresponding substance, it refers to, for example, a hydrogen atom, a hydrogen molecule, and water molecules and OH groups. − This refers to at least one substance that is bonded with hydrogen, such as [substance name]. Furthermore, when an impurity is described as a corresponding substance, unless otherwise specified, it refers to an impurity in the channel-forming region or semiconductor layer, such as a hydrogen atom, hydrogen molecule, water molecule, nitrogen atom, nitrogen molecule, nitrogen oxide molecule (N ２ O, NO, and NO ２ This refers to at least one of the following: (etc.), and copper atoms, etc. Furthermore, when oxygen is described as a corresponding substance, it refers to at least one of the following: for example, an oxygen atom and an oxygen molecule.

[0132] It is preferable to use an insulator that has the function of suppressing hydrogen diffusion for insulating layer 212, insulating layer 221, insulating layer 275, and insulating layer 283. For example, it is preferable to use silicon nitride, which has higher hydrogen barrier properties, for insulating layer 212, insulating layer 221, insulating layer 275, and insulating layer 283.

[0133] The insulating layers 214, 222, and 282 preferably have the function of capturing or fixing hydrogen. For example, aluminum oxide can be used for the insulating layers 214 and 282. Furthermore, for example, it is preferable to use hafnium oxide, a material with a high dielectric constant (high-k), for the insulating layer 222 which functions as a second gate insulating layer.

[0134] By providing an insulating layer 212 having the function of suppressing hydrogen diffusion beneath the transistor 200, the diffusion of hydrogen from the lower layer of the transistor 200 can be suppressed. Furthermore, by providing an insulating layer 214 having the function of capturing or fixing hydrogen, hydrogen contained in the insulating layer 216, etc., can be captured or fixed to the insulating layer 214. This makes it possible to reduce excess hydrogen in and near the semiconductor layer 230.

[0135] Furthermore, by providing an insulating layer 221 having the function of suppressing hydrogen diffusion beneath the semiconductor layer 230, the diffusion of hydrogen from the layer below the semiconductor layer 230 can be suppressed. In addition, by providing an insulating layer 222 having the function of capturing or fixing hydrogen, hydrogen contained in the insulating layer 224, etc., can be captured or fixed to the insulating layer 222. This makes it possible to reduce excess hydrogen in and near the semiconductor layer 230.

[0136] Furthermore, by providing an insulating layer 275, which has the function of suppressing hydrogen diffusion, so as to cover the semiconductor layer 230, etc., it is possible to suppress the diffusion of hydrogen from the insulating layer 280 to the semiconductor layer 230, etc.

[0137] Furthermore, by providing an insulating layer 283 having the function of suppressing hydrogen diffusion on the transistor 200, the diffusion of hydrogen from above the transistor 200 can be suppressed. In addition, by providing an insulating layer 282 having the function of capturing or fixing hydrogen, hydrogen contained in the insulating layer 280, etc., can be captured or fixed to the insulating layer 282. This makes it possible to reduce excess hydrogen in the semiconductor layer 230 and its vicinity.

[0138] In this way, by surrounding the top and bottom of the transistor 200 with a barrier insulating layer against hydrogen, the diffusion of hydrogen into the semiconductor layer 230 is suppressed, and the V in the channel formation region 230i is reduced. Ｏ This allows for a reduction in H. This, in turn, improves the electrical characteristics and reliability of transistor 200.

[0139] It is preferable that the insulating layer 216, insulating layer 280, and insulating layer 285 each have a lower dielectric constant than the insulating layer 222. By using a material with a low dielectric constant as the interlayer insulating layer, parasitic capacitance occurring between wiring can be reduced.

[0140] For example, insulating layer 216, insulating layer 280, and insulating layer 285 can each be made of a material with a low dielectric constant as described in the [Insulating Layer] section below. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Materials such as silicon oxide, silicon oxynitride, and silicon oxide with vacancies are also preferred because they can easily form regions containing excess oxygen.

[0141] <Example of Semiconductor Device Configuration 2> Below, we will describe an example of a semiconductor device according to one aspect of the present invention that differs from the configurations shown in Figures 1A to 3B, etc. We will mainly describe the parts that differ from the description in <Example of Semiconductor Device Configuration 1> above, and will omit explanations of overlapping parts as appropriate.

[0142] Figure 4A is a plan view showing an example of the configuration of a semiconductor device. Figure 4B is a cross-sectional view between the dashed line A1 and A2 shown in Figure 4A. In the example shown in Figures 4A and 4B, the aspect ratio (H) of the openings 243a and 243b ＣＨ / W ＣＨ The resistance is lower than that shown in the examples in Figures 1A and 2A. In addition, the low-resistance region 230na has a region that does not overlap with the opening 243a, and the low-resistance region 230nb has a region that does not overlap with the opening 243b.

[0143] In the example shown in Figure 4B, the sides of the low-resistance region 230na and the sides of the low-resistance region 230nb have a tapered shape. In the example shown in Figure 4B, the distance La1 between the low-resistance region 230na and the channel-forming region 230i along the bottom surface of the semiconductor layer 230 is shorter than the distance La2 between the low-resistance region 230na and the channel-forming region 230i along the top surface of the semiconductor layer 230. Similarly, the distance Lb1 between the low-resistance region 230nb and the channel-forming region 230i along the bottom surface of the semiconductor layer 230 is shorter than the distance Lb2 between the low-resistance region 230nb and the channel-forming region 230i along the top surface of the semiconductor layer 230.

[0144] In the examples shown in Figures 4A and 4B, the distance between the low-resistance region 230na and the channel formation region 230i, and the distance between the low-resistance region 230nb and the channel formation region 230i can be made shorter than in the examples shown in Figures 1A and 2A. This reduces the offset region. As a result, the transistor 200 can obtain a large on-current and high frequency characteristics. Therefore, a semiconductor device with a high operating speed can be realized. On the other hand, in the examples shown in Figures 1A and 2A, the incorporation of impurity elements contained in the low-resistance region 230na or the low-resistance region 230nb into the channel formation region 230i can be suppressed compared to the examples shown in Figures 4A and 4B. Therefore, for example, the formation of oxygen vacancies in the channel formation region of the transistor can be suppressed. Therefore, a highly reliable semiconductor device can be realized. Here, the offset region refers to the region located between the low-resistance region 230na and the channel formation region 230i, and between the low-resistance region 230nb and the channel formation region 230i of the semiconductor layer 230, and where no gate electric field is applied.

[0145] When supplying impurity elements to the semiconductor layer 230 using ion implantation or ion doping, for example, by supplying the impurity elements from an oblique direction to the substrate surface, the low-resistance region 230na and low-resistance region 230nb shown in Figure 4B can be formed. Here, when supplying impurity elements from an oblique direction to the substrate surface, the aspect ratio (H) of the openings 243a and 243b ＣＨ / W ＣＨ A low aspect ratio (H) is preferable as it makes it easier to supply the impurity element to the semiconductor layer 230. ＣＨ / W ＣＨ ) can be, for example, 1 or less, preferably 0.8 or less, more preferably 0.6 or less, and even more preferably 0.5 or less. On the other hand, aspect ratio (H ＣＨ / W ＣＨ If the aspect ratio (H) is too low, for example, the thickness of the conductive layer 260 will become thin. As a result, for example, impurity elements supplied to the conductive layer 260 may pass through the conductive layer 260 and be supplied to the channel-forming region 230i. As a result, for example, oxygen vacancies may be formed in the channel-forming region 230i. Therefore, the aspect ratio (H) ＣＨ / WＣＨ ) is preferably set to, for example, 0.1 or higher.

[0146] When impurity elements are supplied to the substrate surface from an oblique direction, the side walls of opening 243a and opening 243b may also be supplied with these impurity elements. Therefore, in and around opening 243a, and in and around opening 243b, the insulating layers 275, 280, 282, 283, and 285 may have regions where the concentration of the impurity elements is higher than, for example, the concentration of the impurity elements in the channel-forming region 230i.

[0147] Figure 4A shows an example where the shape of openings 243a and 243b in plan view is a rectangular shape with rounded corners. Here, width W ＣＨ This can be, for example, the length of one side of the opening 243a in the channel length direction of the transistor 200.

[0148] By making the shape of the openings 243a and 243b in plan view, for example, a polygon such as a square, or a polygon with rounded corners, it is possible to easily form the low-resistance region 230na and low-resistance region 230nb near the channel-forming region 230i. On the other hand, by making the shape of the openings 243a and 243b in plan view, for example, circular, the processing accuracy when forming the openings 243a and 243b can be improved. Therefore, width W ＣＨ It can be made smaller.

[0149] Figure 5 is a plan view showing an example of the configuration of a semiconductor device. In Figure 5, in a plan view, an example is shown where the openings 243a and 243b are a combination of a circular shape and a square shape with rounded corners. In Figure 5, an example is shown where the diameter of the circle is longer than the length of the square in the channel width direction. Also, in Figure 5, an example is shown where the square is located on the conductive layer 260 side, i.e., on the channel formation region 230i side, relative to the circle. Here, the cross-sectional view between the dashed line A1-A2 shown in Figure 5 can be found in Figure 4B.

[0150] In the example shown in FIG. 5 as well, similar to the examples shown in FIGS. 4A and 4B, by reducing the aspect ratio (H ＣＨ / W ＣＨ ) of the opening 243a and the opening 243b, the low-resistance region 230na can be easily formed in the region between the opening 243a and the conductive layer 260. Similarly, the low-resistance region 230nb can be easily formed in the region between the opening 243b and the conductive layer 260. Thereby, similar to the examples shown in FIGS. 4A and 4B, the distance between the low-resistance region 230na and the channel formation region 230i, and the distance between the low-resistance region 230nb and the channel formation region 230i can be made shorter than those in the examples shown in FIGS. 1A and 2A.

[0151] By making the shapes of the opening 243a and the opening 243b in plan view the shapes shown in FIG. 5, compared with the case of making the shape shown in FIG. 4A, for example, the low-resistance region 230na and the low-resistance region 230nb can be more easily formed in the vicinity of the channel formation region 230i than in the example shown in FIG. 1A, while the occupied areas of the opening 243a and the opening 243b can be reduced. On the other hand, the openings 243a and 243b having the shapes shown in FIGS. 1A, 4A, etc. can be formed more easily than the openings 243a and 243b having the shapes shown in FIG. 5.

[0152] FIG. 6A is a diagram showing an example in which the conductive layer 205, the insulating layer 224, and the conductive layer 260 shown in FIG. 2A have a multilayer stacked structure. FIGS. 6B and 6C are enlarged views of the opening 289 shown in FIG. 6A and the region in the vicinity thereof. In FIGS. 6B and 6C, the insulating layer 250, the conductive layer 260, and the insulating layer 224, the semiconductor layer 230, the insulating layer 275, the insulating layer 280, the insulating layer 282, and the insulating layer 283 are shown. Further, in FIGS. 6B and 6C, an example in which the insulating layer 250 has a multilayer stacked structure is shown.

[0153] Figures 7A, 7B, and 7C are enlarged views of the opening 243a shown in Figure 6A and the surrounding region. Figures 7A to 7C show the insulating layer 241a, the conductive layer 245a, the semiconductor layer 230, the low-resistance region 230na, the insulating layer 275, the insulating layer 280, the insulating layer 282, the insulating layer 283, and the insulating layer 285. Figures 7A to 7C also show an example where the conductive layer 245a has a multi-layered structure. Here, the configuration of the conductive layer 245a shown in Figures 7A to 7C can also be applied to the conductive layer 245b. Therefore, the following description of the conductive layer 245a can also be applied to the conductive layer 245b.

[0154] Figure 6B shows an example in which the insulating layer 250 has a three-layer laminated structure consisting of an insulating layer 250_1 in contact with the semiconductor layer 230, an insulating layer 250_2 on insulating layer 250_1, and an insulating layer 250_3 on insulating layer 250_2. The insulating layer 250_1 has an oxygen barrier property, which suppresses the diffusion of oxygen contained in the semiconductor layer 230 into the conductive layer 260 and the oxidation of the conductive layer 260. It is preferable to use aluminum oxide or gallium oxide for the insulating layer 250_1.

[0155] Furthermore, it is preferable to use a material with a high dielectric constant (high-k) for the insulating layer 250_1. By using a high-k material as the insulating layer 250_1, it becomes possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the insulating layer 250, which functions as a gate insulating layer. In addition, it becomes possible to thin the equivalent oxide thickness (EOT) of the insulating layer 250. The above-mentioned aluminum oxide and gallium oxide are also high-k materials and can therefore be suitably used for the insulating layer 250_1. In addition to aluminum oxide and gallium oxide, other high-k materials that can be used for the insulating layer 250_1 include, for example, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxidized nitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxidized nitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0156] For example, it is preferable to use a material with a low dielectric constant as the insulating layer 250_2. For example, it is preferable that the insulating layer 250_2 has a silicon oxide film or a silicon oxidiznitride film.

[0157] The insulating layer 250_3 preferably has barrier properties against hydrogen. This configuration suppresses the diffusion of hydrogen into the semiconductor layer 230. Furthermore, the insulating layer 250_3 preferably has barrier properties against oxygen. The insulating layer 250_3 is provided between the channel-forming region 230i and the conductive layer 260. This configuration suppresses the diffusion of oxygen contained in the channel-forming region 230i into the conductive layer 260, preventing the formation of oxygen vacancies in the channel-forming region 230i. It also suppresses the diffusion of oxygen contained in the semiconductor layer 230 into the conductive layer 260, preventing the conductive layer 260 from oxidizing. The insulating layer 250_3 preferably has less oxygen permeability than the insulating layer 250_2. Furthermore, the insulating layer 250_3 preferably has a function to suppress the diffusion of hydrogen. This prevents impurities such as hydrogen contained in the conductive layer 260 from diffusing into the semiconductor layer 230. For example, silicon nitride is preferably used as the insulating layer 250_3.

[0158] The insulating layer 250 can have a three-layer structure in which a hafnium oxide film, a silicon oxide film, and a silicon nitride film are stacked in that order from the semiconductor layer 230 side. Furthermore, the film thicknesses of the hafnium oxide film, silicon oxide film, and silicon nitride film can be set to 2 nm, 2 nm, and 1 nm, respectively. This configuration allows excess oxygen in the semiconductor layer 230 to be discharged into the insulating layer 250, reducing the amount of excess oxygen in the semiconductor layer 230. Additionally, hydrogen in the semiconductor layer 230 can be captured or fixed. Therefore, the electrical characteristics and reliability of the transistor 200 can be improved. Alternatively, the insulating layer 250 can also have a three-layer structure in which a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in that order from the semiconductor layer 230 side.

[0159] Figure 6C shows an example in which an insulating layer 250_4 is provided between insulating layer 250_2 and insulating layer 250_3 shown in Figure 6B. An insulating material applicable to insulating layer 222 can be used as insulating layer 250_4. For example, by providing insulating layer 250_4, which has the function of capturing or fixing hydrogen, between insulating layer 250_3 and insulating layer 250_2, hydrogen contained in insulating layer 250_2 can be captured or fixed.

[0160] Preferably, the insulating layer 250 has a four-layer structure in which an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in that order from the semiconductor layer 230 side. With this configuration, hydrogen in the semiconductor layer 230 diffuses into the insulating layer 250, and the hydrogen can be captured or fixed therein. Therefore, the hydrogen concentration in the semiconductor layer 230 can be reduced.

[0161] The insulating layer 250 is preferably a thin film. For example, by setting the thickness of the insulating layer 250 to 1 nm or more and 20 nm or less, preferably 3 nm or more and 10 nm or less, the subthreshold swing value (also called the S value) can be reduced. The S value refers to the amount of change in gate voltage when the drain current is changed by one order of magnitude while the drain voltage is constant in the subthreshold region.

[0162] Furthermore, the film thickness of each layer constituting the insulating layer 250 is preferably 0.1 nm to 20 nm, more preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5.0 nm, more preferably 0.5 nm to 5.0 nm, more preferably 1.0 nm to less than 5.0 nm, and even more preferably 1.0 nm to 3.0 nm. It is preferable that each layer constituting the insulating layer 250 has at least a portion of the above-mentioned film thickness region.

[0163] In addition, the insulating layer 250 has a four-layer structure, and the insulating layer 250_3 may be omitted. For example, insulating layer 250_1 can be an insulating layer having the function of capturing or fixing oxygen, insulating layer 250_2 can be an insulating layer having a low dielectric constant, and insulating layer 250_4 can be an insulating layer having the function of capturing or fixing hydrogen. Specifically, the insulating layer 250 can be a three-layer structure in which an aluminum oxide film, a silicon oxide film, and a hafnium oxide film are stacked in that order from the semiconductor layer 230 side.

[0164] To make the thickness of insulating layers 250_1 to 250_4 as described above, it is preferable to deposit the films using chemical vapor deposition (ALD). Furthermore, to form insulating layers 250_1 to 250_4 with good coverage inside the opening 289, it is preferable to deposit the films using the ALD method.

[0165] Furthermore, in forming the insulating layer 250 having a laminated structure of multiple insulating films, it is preferable to use the ALD process two or more times. For example, it is preferable that two or more of the multiple insulating films of the insulating layer 250 are formed using the ALD process. By forming at least two or more insulating films using the ALD process, the coverage and uniformity of the film thickness of the insulating layer 250 can be improved. In addition, productivity can be increased by continuously forming, for example, two or more insulating films using the ALD process.

[0166] Although the above describes a configuration in which the insulating layer 250 has a three-layer or four-layer structure, the present invention is not limited thereto. The insulating layer 250 can have at least one of insulating layers 250_1 to 250_4. By configuring the insulating layer 250 with one, two, or three layers from insulating layers 250_1 to 250_4, the manufacturing process of semiconductor devices can be simplified and productivity can be improved.

[0167] For example, Figure 6A shows an example in which the conductive layer 260 has a two-layer laminated structure consisting of conductive layer 260_1 and conductive layer 260_2 on conductive layer 260_1. It is preferable that conductive layer 260_1 is provided so as to enclose, for example, the bottom and sides of conductive layer 260_2.

[0168] For example, it is preferable to use titanium nitride as conductive layer 260_1 and tungsten as conductive layer 260_2. Alternatively, it is preferable to use tantalum nitride as conductive layer 260_1 and copper as conductive layer 260_2. By using such a configuration, the conductivity of conductive layer 260 can be increased.

[0169] Furthermore, the conductive layer 260 may have a laminated structure of three or more layers. For example, the conductive layer 260 may have a three-layer structure consisting of a tantalum nitride film, a titanium nitride film on the tantalum nitride film, and a tungsten film on the titanium nitride film.

[0170] Figure 6A shows an example where the insulating layer 224 has a two-layer laminated structure consisting of insulating layer 224_1 and insulating layer 224_2 on top of insulating layer 224_1. It is preferable to use a material with a low dielectric constant for insulating layer 224_1. For example, the insulating layer 224_1 can be made of the same material that can be used for insulating layer 250_2. That is, for example, silicon oxide or silicon oxynitride can be used for insulating layer 224_1.

[0171] The insulating layer 224_2 preferably has barrier properties against oxygen. This prevents oxygen contained in the semiconductor layer 230 from diffusing into the conductive layer 205 and oxidizing the conductive layer 205.

[0172] The insulating layer 224_2 can be made from the same material used for the insulating layer 250_1. For example, aluminum oxide or gallium oxide is preferably used for the insulating layer 224_2.

[0173] Figure 6A shows an example in which the conductive layer 205 has conductive layer 205_1 and conductive layer 205_2. Conductive layer 205_1 is provided in contact with the bottom surface and side wall of the opening in the insulating layer 216. Conductive layer 205_2 is provided so as to fill the recess of conductive layer 205_1 formed along the opening. Here, the height of the upper surface of conductive layer 205 is equal to or approximately equal to the height of the upper surface of insulating layer 216.

[0174] Here, the conductive layer 205_1 contains hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ It is preferable to have a conductive material that has the function of suppressing the diffusion of impurities such as copper atoms, etc. Alternatively, it is preferable to have a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one such as oxygen atoms and oxygen molecules).

[0175] By using a conductive material having the function of reducing hydrogen diffusion in the conductive layer 205_1, it is possible to prevent impurities such as hydrogen contained in the conductive layer 205_2 from diffusing into the semiconductor layer 230 via the insulating layer 216, etc. Furthermore, by using a conductive material having the function of suppressing oxygen diffusion in the conductive layer 205_1, it is possible to suppress oxidation of the conductive layer 205_2 and a decrease in conductivity. Examples of conductive materials having the function of suppressing oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. The conductive layer 205_1 can be a single-layer structure or a laminated structure of the above conductive material. For example, it is preferable that the conductive layer 205_1 has titanium nitride.

[0176] Furthermore, it is preferable to use a highly conductive material for the conductive layer 205_2. For example, it is preferable to use a conductive material mainly composed of tungsten, copper, or aluminum for the conductive layer 205_2. For example, it is preferable that the conductive layer 205_2 contains tungsten.

[0177] Figure 7A shows an example where the conductive layer 245a has a two-layer laminated structure, consisting of a conductive layer 245a1 provided along the opening 243a, and a conductive layer 245a2 provided inside the conductive layer 245a1 so as to fill the opening 243a. Figure 7A also shows an example where the upper end of the conductive layer 245a1, the upper surface of the conductive layer 245a2, the upper end of the insulating layer 241a, and the upper surface of the insulating layer 285 coincide or substantially coincide. Furthermore, Figure 7A shows an example where a recess 288 is formed on the upper surface of the low-resistance region 230na, and a part of the conductive layer 245a1 is embedded in the upper surface of the low-resistance region 230na. The recess 288 is formed, for example, by removing a part of the semiconductor layer 230 when the insulating film, which will become the insulating layer 241a and the insulating layer 241b, is processed by an anisotropic etching method. Note that a recess 288 can also be formed on the upper part of the low-resistance region 230nb.

[0178] The conductive layer 245a1 can be formed as a single layer or in a laminated configuration using a conductive material applicable to the conductive layer 205_1. By providing the conductive layer 245a1, it is possible to suppress the incorporation of impurities such as water and hydrogen into the semiconductor layer 230 through the conductive layer 245a2. The conductive layer 245a2 can use a conductive material applicable to the conductive layer 245a described above.

[0179] Figure 7B shows an example in which the recess 288 is not formed. For example, depending on the formation conditions of the insulating layer 241a, such as the dry etching treatment conditions, the recess 288 may not be formed. For example, when anisotropic etching is performed on the insulating film that will become the insulating layer 241a and insulating layer 241b under conditions where the etching selectivity ratio with the semiconductor layer 230 is high, and when the over-etching time is short, the recess 288 may not be formed.

[0180] Figure 7C shows an example where the upper end of the conductive layer 245a1 is located below the upper surface of the conductive layer 245a2. For example, when forming the conductive layer 245a1 using the sputtering method, the conductive layer 245a1 may not be formed along the side surface of the insulating layer 241a, but only on the upper surface of the low-resistance region 230na and its vicinity.

[0181] Figures 8A and 8B show examples in which an oxide layer 237 is provided between the semiconductor layer 230 and the insulating layer 250_1 shown in Figures 6B and 6C, respectively. The oxide layer 237 is a mixed layer formed at the interface between the semiconductor layer 230 and the insulating layer 250_1. In other words, the oxide layer 237 contains the elements that constitute the semiconductor layer 230 and the elements that constitute the insulating layer 250_1. For example, if the semiconductor layer 230 contains indium and oxygen, and the insulating layer 250_1 contains a metal element and oxygen, then the oxide layer 237 contains indium, the metal element, and oxygen. The mixed layer can also be described as a region where the semiconductor layer 230 and the insulating layer 250_1 are alloyed. Hereafter, the metal element contained in the insulating layer 250_1 may be referred to as the second element.

[0182] The second element is preferably an element that can have the same valency as the metallic element present in the semiconductor layer 230. For example, if the semiconductor layer 230 contains indium, the second element is preferably an element that can become a trivalent cation. Examples of the second element include aluminum and gallium. Specifically, when aluminum oxide is used as the insulating layer 250_1, the second element is aluminum. Also, when gallium oxide is used as the insulating layer 250_1, the second element is gallium. Because the oxide layer 237 contains the second element, even if the second element substitutes for indium, no carriers are generated, thus suppressing the n-type transformation of the oxide layer 237 or the semiconductor layer 230 near the oxide layer 237.

[0183] Aluminum and gallium have electronegativity close to that of indium. Therefore, oxides containing indium and at least one of aluminum and gallium have a nearly uniform electron distribution in each oxygen atom, resulting in a homogeneous structure. This is preferable because it makes it less prone to defects. It is also preferable because it makes it less prone to defects even when structural disorder occurs in the oxide layer 237 containing the oxide (for example, when it has an amorphous structure). Furthermore, it is particularly preferable to use aluminum as the second element. When aluminum is used as the second element, oxygen can be captured in the film. For example, excess oxygen that may be present in the semiconductor layer 230 can be captured by the aluminum in the insulating layer 250_1.

[0184] Based on the above, it is preferable that the second element is either aluminum or gallium, or both. By forming an oxide layer 237, which is a mixed layer of semiconductor layer 230 and insulating layer 250_1, surface defects formed on the semiconductor layer 230 can be reduced. Specifically, surface defects occurring at the interface between semiconductor layer 230 and oxide layer 237, and at the interface between oxide layer 237 and insulating layer 250_1, can be reduced to fewer than surface defects occurring at the interface between semiconductor layer 230 and insulating layer 250_1 when the oxide layer 237 is not formed. In addition, a carrier path is formed near the interface between semiconductor layer 230 and oxide layer 237. As a result, the effect of surface scattering can be reduced compared to when the oxide layer 237 is not formed. Therefore, the on-current of transistor 200 can be increased. Furthermore, the reliability of transistor 200 can be improved, thus enabling the realization of a highly reliable semiconductor device.

[0185] The oxide layer 237 preferably has a region with a film thickness of 0.1 nm or more and 2 nm or less, more preferably has a region with a film thickness of 0.1 nm or more and 1 nm or less, and even more preferably has a region with a film thickness of 0.2 nm or more and 1 nm or less. By setting the film thickness of the oxide layer 237 within the above range, miniaturization of the semiconductor device can be achieved.

[0186] The content of the second element in the oxide layer 237 is preferably 1 atomic% to 50 atomic%, more preferably 1 atomic% to 30 atomic%, and even more preferably 1 atomic% to 20 atomic%. By setting the content of the second element in the oxide layer 237 within the above range, the oxide layer 237 can function as a semiconductor layer. This makes it possible to realize a buried channel type transistor 200 in which the channel is farther away from the interface of the gate insulating layer. Therefore, the field-effect mobility of the transistor 200 can be increased.

[0187] Furthermore, the oxide layer 237 has a concentration gradient in which the concentration of the second element decreases from the lower surface of the insulating layer 250_1 toward the upper surface of the semiconductor layer 230. In other words, the oxide layer 237 has a concentration gradient in the film thickness direction in which the concentration of the second element decreases toward the semiconductor layer 230.

[0188] The oxide layer 237 can be confirmed, for example, by cross-sectional TEM (Transmission Electron Microscope) images, cross-sectional scanning transmission electron microscope (STEM) images, etc. Furthermore, the oxide layer 237 may also be confirmed at the interface between the semiconductor layer 230 and the insulating layer 250_1 and its surrounding areas by using SIMS or by performing line composition analysis by EDX.

[0189] The oxide layer 237 can be formed, for example, by heat treatment after the formation of the insulating layer 250. Alternatively, when forming the insulating layer 250_1 using a sputtering method, the sputtering damage can create an oxide layer 237 in which the components of the semiconductor layer 230 and the insulating layer 250 are mixed. In this case, the heat treatment may be omitted.

[0190] Furthermore, when the semiconductor layer 230 and the insulating layer 250 are formed continuously by the ALD method, an oxide layer 237 of any composition can be formed by using multiple different types of precursors. Alternatively, when multiple different types of precursors are introduced, an oxide layer 237 of any composition can be formed by controlling the number of cycles of each precursor. For example, a semiconductor layer 230 can be formed using an indium-containing precursor and an oxidizing agent, an oxide layer 237 can be formed using an indium-containing precursor, an aluminum-containing precursor and an oxidizing agent, and an insulating layer 250 can be formed using an aluminum-containing precursor and an oxidizing agent.

[0191] Figure 9 shows an example where the semiconductor layer 230 has a two-layer stacked structure consisting of semiconductor layer 230_1 and semiconductor layer 230_2 on top of semiconductor layer 230_1. In Figure 9, an example is shown where the channel formation region 230i, low-resistance region 230na, and low-resistance region 230nb are not formed in semiconductor layer 230_1, but these regions may be formed in semiconductor layer 230_1.

[0192] The semiconductor layer 230_2 can be made of the same material that can be used for the semiconductor layer 230 described above. For example, indium oxide can be used for the semiconductor layer 230_2. A channel-forming region 230i, a low-resistance region 230na, and a low-resistance region 230nb are formed in the semiconductor layer 230_2.

[0193] The semiconductor layer 230_1 preferably has a hexagonal or trigonal crystal structure. This allows the crystallinity of the semiconductor layer 230_2 to be enhanced by using the semiconductor layer 230_1 as a seed or nucleus.

[0194] As the semiconductor layer 230_1, zinc oxide, In-Ga oxide, GZO, AZO, IGZO, IAZO, or ITZO (registered trademark) can be used. It is preferable to use IGZO as the semiconductor layer 230_1. In this case, the semiconductor layer 230_1 has indium, gallium, zinc, and oxygen. More specifically, it is preferable to have a composition of In:Ga:Zn = 1:1:1 [atomic ratio] or close to that, or a composition of In:Ga:Zn = 1:3:2 [atomic ratio] or close to that.

[0195] IGZO and In-Sn-Zn oxides, etc., tend to have a CAAC (C-Axis Aligned Crystalline) structure. CAAC-OS has multiple layered crystals. The c-axis of these crystals is oriented in the direction normal to the surface on which it is formed.

[0196] When an oxide having a CAAC structure is used for the semiconductor layer 230_1, the c-axis direction of the semiconductor layer 230_1 is perpendicular or approximately perpendicular to the surface of the insulating layer 224. Therefore, by using an oxide that easily has a CAAC structure for the semiconductor layer 230_1, the controllability of the crystal plane of the crystal grains in the semiconductor layer 230_2 can be improved.

[0197] Furthermore, when the above-mentioned material is used as the semiconductor layer 230_1, the diffusion of impurities from structures formed below the semiconductor layer 230_1 to the semiconductor layer 230_2 can be suppressed. This improves the electrical characteristics of the transistor 200 and increases its reliability. Thus, a highly reliable semiconductor device can be realized.

[0198] A semiconductor layer may be provided on top of semiconductor layer 230_2. In this case, if semiconductor layer 230_1 is the first semiconductor layer and semiconductor layer 230_2 is the second semiconductor layer, then semiconductor layer 230 will have a three-layer stacked structure consisting of the first semiconductor layer, the second semiconductor layer on the first semiconductor layer, and the third semiconductor layer on the second semiconductor layer. Note that a third semiconductor layer may be provided, but semiconductor layer 230_1 may not be provided. That is, semiconductor layer 230 may have a two-layer stacked structure consisting of semiconductor layer 230_2 and the third semiconductor layer on top of semiconductor layer 230_2.

[0199] It is preferable to use a metal oxide as the third semiconductor layer, whose conduction band lower edge is located on the vacuum level side of the conduction band lower edge of semiconductor layer 230_2. In this case, semiconductor layer 230_2 can mainly function as a current path (channel). That is, semiconductor layer 230_2 has a channel-forming region 230i on the surface facing the third semiconductor layer and in its vicinity.

[0200] By using the above configuration, the number of carriers trapped at and near the interface of the semiconductor layer 230_2 can be reduced. In addition, the channel can be moved away from the surface of the insulating layer 250, reducing the effects of surface scattering. As a result, the field-effect mobility of the transistor 200 can be increased.

[0201] As metal oxides applicable to the third semiconductor layer, for example, In-Ga oxide, In-Zn oxide, In-Sn oxide, In-Ti oxide, In-Al-Zn oxide, In-Ga-Zn oxide, In-Sn-Zn oxide, In-Ti-Zn oxide, ITSO, etc. can be used. Alternatively, zinc oxide, AZO, Al-Sn oxide, etc. can be used.

[0202] The In-Zn oxide used in the third semiconductor layer can specifically have a composition of In:Zn = 1:1 [atomic ratio] or close to it, In:Zn = 2:1 [atomic ratio] or close to it, or In:Zn = 4:1 [atomic ratio] or close to it. Furthermore, the IGZO used in the third semiconductor layer can specifically have a composition of In:Ga:Zn = 1:1:1 [atomic ratio] or close to it, In:Ga:Zn = 1:3:2 [atomic ratio] or close to it, or In:Ga:Zn = 1:3:4 [atomic ratio] or close to it. Note that "close to" includes a range of ±30% of the desired atomic ratio.

[0203] The crystallinity of the metal oxide in the third semiconductor layer is not particularly limited. For example, the third semiconductor layer may include one or more amorphous semiconductors (semiconductors having an amorphous structure), single-crystal semiconductors (semiconductors having a single-crystal structure), or semiconductors having crystalline properties other than single crystals (microcrystalline semiconductors, polycrystalline semiconductors, or semiconductors having crystalline regions in part).

[0204] FIG. 10A, FIG. 10B, and FIG. 10C are cross-sectional views showing a configuration example of the conductive layer 205. In the examples shown in FIGS. 10A to 10C, the configuration of the conductive layer 205 is different from the configurations shown in FIGS. 2A, 6A, etc. In FIGS. 10A to 10C, in addition to the conductive layer 205, an insulating layer 212, an insulating layer 214, an insulating layer 216, an insulating layer 221, an insulating layer 222, and an insulating layer 224 are shown.

[0205] FIG. 10A shows an example in which the conductive layer 205 has a three-layer laminated structure of a conductive layer 205_3, a conductive layer 205_1 on the conductive layer 205_3, and a conductive layer 205_2 on the conductive layer 205_1. In the example shown in FIG. 10A, the conductive layer 205_3 is provided along the opening of the insulating layer 216. Further, the conductive layer 205_1 is provided along the side surface and the upper surface of the conductive layer 205_3 inside the above-described opening. Furthermore, the upper end portion of the conductive layer 205_1, the upper surface of the conductive layer 205_2, the upper end portion of the conductive layer 205_3, and the upper surface of the insulating layer 216 coincide or are substantially coincident.

[0206] For the conductive layer 205_3, it is preferable to use, for example, tantalum or tantalum nitride having a relatively high hydrogen barrier property. Since the conductive layer 205_3 is in contact with the insulating layer 216, tantalum nitride having a high oxygen barrier property is more preferable. For example, tantalum nitride can be formed as the conductive layer 205_3 by using a sputtering method. Since the sputtering method does not contain hydrogen gas in the film-forming gas, the hydrogen concentration of the conductive layer 205_3 can be reduced, which is preferable. Here, the conductive layer 205_3 preferably has a region with a hydrogen concentration of less than 1×10 ２２ cm −３ and more preferably has a region with a hydrogen concentration of less than 1×10 ２１ cm −３ and even more preferably has a region with a hydrogen concentration of less than 1×10 ２０ cm −３ In addition, when using the sputtering method, as shown in FIG. 10A, the film thickness of the portion of the conductive layer 205_3 substantially parallel to the substrate (which may be the insulating layer 212 or the insulating layer 214) may be thicker than the film thickness of the portion substantially perpendicular to the substrate.

[0207] Figure 10B shows an example in which a conductive layer 205_4 is provided between conductive layer 205_3 and conductive layer 205_1 shown in Figure 10A. In the example shown in Figure 10B, the upper end of conductive layer 205_1, the upper surface of conductive layer 205_2, the upper end of conductive layer 205_3, the upper end of conductive layer 205_4, and the upper surface of insulating layer 216 coincide or substantially coincide.

[0208] Since the conductive layer 205_4 does not come into contact with the insulating layer 216, it is preferable to use tantalum. For example, tantalum can be deposited as the conductive layer 205_4 using a sputtering method. The sputtering method is preferable because it does not contain hydrogen gas in the deposition gas, thus reducing the hydrogen concentration in the conductive layer 205_4. Also, when using the sputtering method, as shown in Figure 10B, the film thickness of the conductive layer 205_4 in the portion substantially parallel to the substrate (which may also be the insulating layer 212 or insulating layer 214) may be thicker than the film thickness of the portion substantially perpendicular to the substrate.

[0209] By using the above configuration, it is possible to prevent impurities such as hydrogen and metallic impurities such as copper contained in the lower layer of transistor 200 from diffusing into the conductive layer 205. Furthermore, it is possible to prevent impurities such as hydrogen and metallic impurities such as copper contained in the lower layer of transistor 200 from diffusing into the semiconductor layer 230 via the conductive layer 205.

[0210] Figure 10C shows an example in which a conductive layer 205_5 is provided on the conductive layer 205_2 shown in Figure 10A. In the example shown in Figure 10C, the upper end of conductive layer 205_1, the upper end of conductive layer 205_3, the upper surface of conductive layer 205_5, and the upper surface of insulating layer 216 coincide or substantially coincide.

[0211] The conductive layer 205_5 can be made of the same conductive material that can be used for conductive layer 205_1. By providing conductive layer 205_5, even if the upper surface of conductive layer 205_2 is lower than the upper end of conductive layer 205_1, the recess formed by conductive layer 205_1 and conductive layer 205_2 can be filled. Furthermore, even if a recess is formed in the center of the upper surface of conductive layer 205_2, this recess can also be filled. Therefore, the flatness of the upper surface of conductive layer 205 can be improved. In addition, the diffusion of impurities such as hydrogen and metallic impurities such as copper contained in conductive layer 205_2 can be blocked by conductive layer 205_5.

[0212] Figure 11A is a plan view showing an example of the configuration of a semiconductor device. Figure 11B is a cross-sectional view between the dashed lines A1 and A2 shown in Figure 11A. In the semiconductor devices shown in Figures 11A and 11B, the conductive layer 245a and the conductive layer 245b have regions that contact not only the upper surface of the semiconductor layer 230 but also the side surface of the semiconductor layer 230. Figure 11B shows an example in which the conductive layer 245a and the conductive layer 245b have regions that contact the side surface of the insulating layer 224 and regions that contact the upper surface of the insulating layer 222.

[0213] The semiconductor devices shown in Figures 11A and 11B have a larger contact area between the conductive layers 245a and 245b and the semiconductor layer 230 compared to the semiconductor devices shown in Figures 1A and 2A. This reduces the contact resistance between the conductive layers 245a and 245b and the semiconductor layer 230. Therefore, a semiconductor device with a high operating speed can be realized. On the other hand, the semiconductor devices shown in Figures 1A and 2A have a higher density arrangement of transistors 200 compared to the semiconductor devices shown in Figures 11A and 11B. Therefore, a highly integrated semiconductor device can be realized.

[0214] Figures 12A and 12B show examples where the insulating layer 224, as shown in Figures 2A and 3A, is not processed into an island shape, but has protrusions at positions overlapping with the semiconductor layer 230. In this case, the film thickness of the insulating layer 224 in the region that does not overlap with the semiconductor layer 230 is thinner than the film thickness in the region that overlaps with the semiconductor layer 230. When multiple transistors are provided on the same substrate, forming the insulating layer 224 in this way ensures that the semiconductor layer 230 of each transistor is formed on the same insulating layer 224. This reduces variations in the amount of oxygen supplied from the insulating layer 224 to the semiconductor layer 230 of each transistor. Therefore, variations in the electrical characteristics of each transistor can be reduced. In the insulating layer 224 having protrusions, as shown in Figure 12B, an opening may be provided in the region that does not overlap with the semiconductor layer 230 but overlaps with the insulating layer 250. In regions that do not overlap with the semiconductor layer 230 but overlap with the insulating layer 250, the upper surface of the insulating layer 222 can be in contact with the insulating layer 250. Alternatively, the opening may not be provided.

[0215] When the insulating layer 224 has a laminated structure of multiple layers, some of the layers on the semiconductor layer 230 side may be processed into island shapes, while the layers below that layer do not need to be processed into island shapes. For example, when the insulating layer 224 has the configuration shown in Figure 6A, insulating layer 224_2 can be processed into island shapes, while insulating layer 224_1 can be left unprocessed. For example, by processing insulating layer 224_2 under conditions where the etching selectivity ratio with insulating layer 224_1 is high, insulating layer 224_2 can be provided in island shapes, and insulating layer 224_1 can be provided over the entire upper surface of insulating layer 222.

[0216] <Materials for Semiconductor Devices> The following describes materials that can be used in semiconductor devices. Each layer constituting a semiconductor device may be a single-layer structure or a multilayer structure.

[0217] [Insulating Layers] For the insulating layers of the semiconductor device (insulating layer 212, insulating layer 214, insulating layer 216, insulating layer 221, insulating layer 222, insulating layer 224, insulating layer 241a, insulating layer 241b, insulating layer 250, insulating layer 275, insulating layer 280, insulating layer 282, insulating layer 283, insulating layer 285, etc.), it is preferable to use inorganic insulating films. Examples of inorganic insulating films include oxide insulating films, nitride insulating films, oxidized nitride insulating films, and nitrided oxide insulating films. Examples of oxide insulating films include silicon oxide films, aluminum oxide films, magnesium oxide films, gallium oxide films, germanium oxide films, yttrium oxide films, zirconium oxide films, lanthanum oxide films, neodymium oxide films, hafnium oxide films, tantalum oxide films, cerium oxide films, gallium zinc oxide films, and hafnium aluminate films. Examples of nitride insulating films include silicon nitride films and aluminum nitride films. Examples of oxidative nitride insulating films include silicon oxidative nitride films, aluminum oxidative nitride films, gallium oxidative nitride films, yttrium oxidative nitride films, and hafnium oxidative nitride films. Examples of nitride oxide insulating films include silicon oxidative nitride films and aluminum oxidative nitride films. In addition, an organic insulating film may be used for the insulating layer of the semiconductor device.

[0218] For example, as transistors become smaller and more integrated, thinning of the gate insulating layer can lead to problems such as leakage current. By using the aforementioned high-k material for the gate insulating layer, it becomes possible to lower the voltage during transistor operation while maintaining the physical film thickness. Furthermore, it becomes possible to thin the equivalent oxide thickness (EOT) of the gate insulating layer. On the other hand, by using a material with a low relative permittivity for the insulating layer that functions as an interlayer insulating layer, parasitic capacitance between wiring can be reduced. Therefore, it is preferable to select the material according to the function of the insulating layer. It should be noted that materials with a low relative permittivity also have high dielectric strength.

[0219] Examples of materials with low dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxide-nitride, and silicon nitride-oxide, as well as resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin. Other inorganic insulating materials with low dielectric constant include, for example, silicon oxide containing fluorine, silicon oxide containing carbon, and silicon oxide containing carbon and nitrogen. Also, for example, silicon oxide having vacancies can be used. These silicon oxides may contain nitrogen.

[0220] Furthermore, a ferroelectric material may be used for the insulating layer of the semiconductor device. Preferably, an oxide containing one or both hafnium and zirconium is used as the ferroelectric material. Examples of such oxides include metal oxides such as hafnium oxide, zirconium oxide, and hafnium-zirconium oxide. Alternatively, a material may be used in which element J1 (where element J1 is one or more selected from the other of hafnium and zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to a metal oxide containing either hafnium or zirconium as the ferroelectric material.

[0221] Furthermore, by adding a Group 3 element from the periodic table to an oxide containing one or both hafnium and zirconium, the oxygen vacancy concentration in the oxide increases, making it easier to form crystals with an orthorhombic crystal structure. This increases the proportion of crystals with an orthorhombic crystal structure, which is preferable because it allows for greater remanent polarization. On the other hand, if too much Group 3 element is added, the crystallinity of the oxide may decrease, making it difficult to exhibit ferroelectric properties. Therefore, the content of Group 3 elements in an oxide containing one or both hafnium and zirconium is preferably 0.1 atomic% to 10 atomic%, more preferably 0.1 atomic% to 5 atomic%, and even more preferably 0.1 atomic% to 3 atomic%. Here, the content of Group 3 elements refers to the ratio of the number of Group 3 elements to the sum of the number of atoms of all metal elements contained in the layer. The Group 3 element is preferably one or more selected from scandium, lanthanum, and yttrium, and more preferably one or both of lanthanum and yttrium.

[0222] Furthermore, a material that may possess ferroelectric properties is a metal nitride having at least one of elements M1 and M2, and nitrogen. Here, element M1 is one or more selected from aluminum, gallium, indium, etc. Element M2 is one or more selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. Another material that may possess ferroelectric properties is a material in which element M3 is added to the above metal nitride. Element M3 is one or more selected from magnesium, calcium, strontium, zinc, cadmium, etc.

[0223] Furthermore, SrTaO is an example of a material that may possess ferroelectric properties. ２ N and BaTaO ２ Perovskite-type oxynitrides such as N, and GaFeO with a κ-alumina structure. ３ Examples include lead titanate (PbTiO2) as a material that can possess ferroelectric properties. Ｘ), or piezoelectric ceramics having a perovskite structure such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), or barium titanate may be used.

[0224] While the above explanation uses metal oxides and metal nitrides as examples, it is not limited to these. For example, metal oxynitrides obtained by adding nitrogen to the aforementioned metal oxides, or metal nitrogen oxides obtained by adding oxygen to the aforementioned metal nitrides, may be used.

[0225] Furthermore, as a material that may possess ferroelectricity, for example, a mixture or compound consisting of multiple materials selected from the materials listed above can be used. Incidentally, since the crystal structure (properties) of the materials listed above may change not only depending on the film deposition conditions but also on various processes, in this specification, materials that exhibit ferroelectricity are not only called ferroelectrics, but also materials that may possess ferroelectricity.

[0226] In this specification, a layered structure of a material capable of ferroelectricity may be referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. Furthermore, a device having such a ferroelectric layer, metal oxide film, or metal nitride film may be referred to as a ferroelectric device in this specification.

[0227] The ferroelectric layer is preferably composed of crystals having an orthorhombic crystal structure, as this exhibits ferroelectric properties. The crystal structure of the crystals included in the ferroelectric layer may be one or more selected from tetragonal, orthorhombic, monoclinic, and hexagonal systems. Furthermore, the ferroelectric layer may have an amorphous structure. In this case, the ferroelectric layer may have a composite structure comprising both an amorphous and a crystalline structure.

[0228] Metal oxides containing either or both hafnium and zirconium are insulating materials that have the function of capturing or fixing hydrogen. Therefore, by using a metal oxide containing either or both hafnium and zirconium in at least a portion of the gate insulating layer, hydrogen contained in the oxide semiconductor layer can be captured or fixed, thereby reducing excess hydrogen in the oxide semiconductor layer. Furthermore, a transistor having this gate insulating layer can function as an FeFET (Ferroelectric Field Effect Transistor).

[0229] Furthermore, the electrical properties of a transistor using a metal oxide can be stabilized by surrounding it with an insulating layer that has the function of suppressing the permeation of impurities and oxygen. As an insulating layer that has the function of suppressing the permeation of impurities and oxygen, for example, an insulating layer containing one or more selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum can be used in a single layer or multilayer configuration. Specifically, as the material for the insulating layer that has the function of suppressing the permeation of impurities and oxygen, metal oxides such as aluminum oxide, magnesium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, nitrides such as aluminum nitride or silicon nitride, and nitride oxides such as silicon nitride can be used.

[0230] Specifically, materials for insulating layers that have the function of suppressing the permeation of impurities such as water and hydrogen, and oxygen, include metal oxides such as aluminum oxide, magnesium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and oxides containing aluminum and hafnium (hafnium aluminate). Also, nitrides such as aluminum nitride, titanium aluminum nitride, silicon nitride, and silicon nitride are also included. Furthermore, nitride oxides such as silicon nitride are also included. Additionally, gallium oxide is an example of an insulating layer material that has the function of suppressing oxygen permeation.

[0231] Furthermore, insulating layers that are in contact with the oxide semiconductor layer, such as gate insulating layers, or insulating layers provided near the oxide semiconductor layer, are preferably insulating layers that contain regions of excess oxygen. For example, by having an insulating layer containing regions of excess oxygen in contact with or near the oxide semiconductor layer, the oxygen vacancies in the oxide semiconductor layer can be reduced.

[0232] It is preferable to use a hydrogen barrier insulating layer for the insulating layer in contact with the oxide semiconductor layer, or an insulating layer provided near the oxide semiconductor layer. The hydrogen barrier properties of this insulating layer suppress the diffusion of hydrogen into the oxide semiconductor layer. A hydrogen barrier insulating layer can also be described as an insulating layer that has the function of suppressing hydrogen diffusion.

[0233] Examples of insulating materials having the function of capturing or fixing hydrogen include metal oxides such as hafnium oxides, magnesium oxides, aluminum oxides, aluminum and hafnium oxides (hafnium aluminate), and hafnium silicate. Furthermore, these metal oxides may also contain zirconium, for example, hafnium and zirconium oxides.

[0234] An insulating layer having the function of capturing or fixing hydrogen preferably has an amorphous structure. In metal oxides having an amorphous structure, some oxygen atoms have dangling bonds, thus having a high ability to capture or fix hydrogen. Therefore, by having an amorphous structure in the insulating layer, the function of capturing or fixing hydrogen can be enhanced.

[0235] By making the insulating layer amorphous, the formation of grain boundaries can be suppressed. Suppressing the formation of grain boundaries improves the flatness of the insulating layer. This makes the thickness distribution of the insulating layer more uniform, reducing areas with extremely thin film thickness, and thus improving the dielectric strength of the insulating layer. Furthermore, the thickness distribution of the film provided on the insulating layer can be made more uniform. In addition, by suppressing the formation of grain boundaries in the insulating layer, leakage current caused by defect levels at the grain boundaries can be reduced. Therefore, the insulating layer can function as an insulating film with low leakage current.

[0236] Furthermore, the function of capturing or fixing a corresponding substance can also be described as the property of making it difficult for the corresponding substance to diffuse. Therefore, the function of capturing or fixing a corresponding substance can be rephrased as barrier properties.

[0237] Examples of materials for the barrier insulating layer against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium (hafnium aluminate), oxides containing hafnium and zirconium (hafnium zirconium oxide), silicon nitride, or silicon nitride oxide.

[0238] The inorganic insulating layers listed as having the function of capturing or fixing hydrogen, and the function of suppressing hydrogen diffusion, also possess barrier properties against oxygen. Examples of materials for the oxygen barrier insulating layer include oxides containing one or both of aluminum and hafnium, magnesium oxide, zinc gallium oxide, silicon nitride, silicon oxide nitride, and the like. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and hafnium silicate.

[0239] [Conductive Layers] The conductive layers (conductive layer 205, conductive layer 245a, conductive layer 245b, conductive layer 260, etc.) of the semiconductor device are preferably made of metal elements selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, palladium, iridium, strontium, lanthanum, etc., or alloys composed of the aforementioned metal elements, or alloys combining the aforementioned metal elements. As alloys composed of the aforementioned metal elements, nitrides of the alloys or oxides of the alloys may be used. For example, it is preferable to use tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Alternatively, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements like phosphorus, or silicides such as nickel silicide may be used.

[0240] Furthermore, conductive materials containing nitrogen, such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum; conductive materials containing oxygen, such as oxides containing ruthenium oxide, strontium and ruthenium, or oxides containing lanthanum and nickel; and materials containing metallic elements such as titanium, tantalum, or ruthenium are preferred because they are conductive materials that are resistant to oxidation, conductive materials that have the function of suppressing oxygen diffusion, or materials that maintain conductivity even when absorbing oxygen. Examples of conductive materials containing oxygen include indium oxide containing tungsten oxide, In-Ti oxide, ITO, indium tin oxide containing titanium oxide, ITSO, and indium zinc oxide containing tungsten oxide. In this specification, conductive films formed using conductive materials containing oxygen are sometimes referred to as oxide conductive films.

[0241] Furthermore, multiple conductive layers formed from the above materials may be used in a laminated structure. For example, a laminated structure may be formed by combining the aforementioned metal element material with an oxygen-containing conductive material. Alternatively, a laminated structure may be formed by combining the aforementioned metal element material with a nitrogen-containing conductive material. Alternatively, a laminated structure may be formed by combining the aforementioned metal element material with an oxygen-containing conductive material and a nitrogen-containing conductive material.

[0242] Furthermore, when using a metal oxide for the channel formation region of a transistor, it is preferable to use a laminated structure for the conductive layer that functions as the gate electrode, which combines a material containing the aforementioned metal element with a conductive material containing oxygen. In this case, it is preferable to provide the conductive material containing oxygen on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen detached from the conductive material is more easily supplied to the channel formation region.

[0243] [Substrate] As a substrate for forming a transistor, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate can be used. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, there are semiconductor substrates having insulating regions within the aforementioned semiconductor substrates, such as SOI (Silicon On Insulator) substrates. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, or conductive resin substrates. Alternatively, there are substrates having metal nitrides, substrates having metal oxides, etc. Furthermore, there are substrates on which a conductor or semiconductor is provided on an insulating substrate, substrates on which a conductor or insulator is provided on a semiconductor substrate, and substrates on which a semiconductor or insulator is provided on a conductive substrate. Alternatively, substrates with elements mounted on them may be used. Examples of elements mounted on the substrate include capacitive elements, resistive elements, switch elements, light-emitting elements, or memory elements.

[0244] The above is a description of materials that can be used in semiconductor devices.

[0245] <Example of Semiconductor Device Fabrication Method> An example of a semiconductor device fabrication method according to one embodiment of the present invention will be described using Figures 13A to 16A. Here, the case of fabricating the semiconductor device shown in Figure 2A will be used as an example. Note that explanations of the materials and formation methods of each component may be omitted if they are the same as those described earlier.

[0246] Thin films (insulating films, semiconductor films, and conductive films, etc.) that constitute semiconductor devices can be formed using methods such as sputtering, chemical vapor deposition (CVD), molecular beam epitaxy (MBE), vacuum deposition, pulsed laser deposition (PLD), and ALD.

[0247] For film deposition using insulating targets, RF sputtering is preferable. DC sputtering is mainly used when depositing films using conductive targets. In addition to forming conductive films, DC sputtering can also be used to form insulating films by reactive sputtering using pulsed DC sputtering. Specifically, pulsed DC sputtering can be used when depositing compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0248] Furthermore, CVD methods can be classified into plasma-enhanced CVD (PECVD) methods, thermal CVD (TCD) methods, and photo-CVD (Photo CVD) methods, which utilize plasma. They can also be further divided into metal CVD (MCCVD) methods and metal-organic CVD (MOCVD) methods depending on the source gas used.

[0249] Plasma CVD allows for the production of high-quality films at relatively low temperatures. Thermal CVD, on the other hand, does not use plasma, thus minimizing plasma damage to the workpiece. For example, wiring, electrodes, and components (transistors, capacitive elements, etc.) in semiconductor devices can be charged up by receiving charge from the plasma. This accumulated charge can damage these components. In contrast, thermal CVD, which does not use plasma, avoids such plasma damage, resulting in higher yields for semiconductor devices. Furthermore, thermal CVD produces films with fewer defects because it avoids plasma damage during deposition.

[0250] Furthermore, ALD methods that can be used include thermal ALD, which carries out the reaction of the precursor and reactant using only thermal energy, and plasma ALD (PEALD: Plasma Enhanced ALD), which uses a plasma-excited reactant.

[0251] Furthermore, precursors used in the ALD method may contain elements such as carbon or chlorine. Therefore, films formed by the ALD method may contain higher levels of elements such as carbon or chlorine compared to films formed by other film formation methods. These elements can be quantified using XPS or SIMS. In one embodiment of the present invention, the metal oxide film formation method uses the ALD method, but because it employs conditions of high substrate temperature during film formation and / or impurity removal treatment, the amount of carbon and chlorine contained in the film may be lower compared to when the ALD method is used without these treatments.

[0252] Unlike film deposition methods in which particles emitted from a target or the like accumulate, the ALD method is a film deposition method in which a film is formed by a reaction on the surface of the workpiece. Therefore, it is less affected by the shape of the workpiece and is a film deposition method that has good step-level coverage. In particular, the ALD method has excellent step-level coverage and excellent thickness uniformity, making it suitable for coating the surface of openings with high aspect ratios, etc.

[0253] CVD and ALD methods differ from sputtering, where particles emitted from a target or other source are deposited. Therefore, they are less affected by the shape of the workpiece and are film deposition methods that provide good step-level coverage. In particular, the ALD method has excellent step-level coverage and excellent thickness uniformity, making it suitable for coating the surface of openings with high aspect ratios. However, since the ALD method has a relatively slow deposition rate, it is sometimes preferable to use it in combination with other film deposition methods such as the CVD method, which has a faster deposition rate.

[0254] Furthermore, the CVD method allows for the deposition of films with any desired composition by changing the flow rate ratio of the source gases. For example, in the CVD method, by changing the flow rate ratio of the source gases while deposition is occurring, films with continuously changing compositions can be deposited. When deposition is performed while changing the flow rate ratio of the source gases, the time required for deposition can be shortened compared to deposition using multiple deposition chambers, because time spent on transport or pressure adjustment is eliminated. Therefore, it may be possible to increase the productivity of semiconductor devices.

[0255] Furthermore, the ALD method allows for the deposition of films of any composition by using multiple different types of precursors. Alternatively, when using multiple different types of precursors, films of any composition can be deposited by controlling the number of cycles for each precursor.

[0256] There are two main methods of photolithography. One method involves forming a resist mask on the thin film to be processed, then processing the thin film by etching or other means, and removing the resist mask. The other method involves forming a photosensitive thin film, then exposing and developing it to process the thin film into the desired shape.

[0257] In photolithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture thereof. Other light sources such as ultraviolet light, KrF laser light, or ArF laser light can also be used. Exposure may also be performed using immersion lithography. Furthermore, extreme ultraviolet (EUV) light or X-rays may be used as the light source for exposure. An electron beam can also be used instead of the light source for exposure. Using extreme ultraviolet light, X-rays, or an electron beam is preferable because it enables extremely fine processing. Note that a photomask is not required when exposure is performed by scanning a beam such as an electron beam.

[0258] For etching thin films, methods such as dry etching, wet etching, and sandblasting can be used.

[0259] First, as shown in Figure 13A, a substrate (not shown) is prepared, an insulating layer 212 is deposited on the substrate, and an insulating layer 214 is deposited on the insulating layer 212. In this embodiment, a silicon nitride film is deposited as the insulating layer 212 using the sputtering method, and an aluminum oxide film is deposited as the insulating layer 214 using the sputtering method. By using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulating layer 212 and insulating layer 214 can be reduced.

[0260] Furthermore, it is preferable to perform a heat treatment before forming the insulating layer 212 to reduce the amount of water and hydrogen adsorbed on the substrate (including the circuit elements and interlayer insulating layer formed on the substrate). In this embodiment, the heat treatment temperature is set to 400°C.

[0261] Next, as shown in Figure 13A, an insulating layer 216 is formed on the insulating layer 214. In this embodiment, a silicon oxide film is formed as the insulating layer 216 using the sputtering method. By using the sputtering method, which does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulating layer 216 can be reduced.

[0262] It is preferable to continuously deposit insulating layers 212, 214, and 216 without exposure to the atmosphere. For example, it is preferable to use a multi-chamber type deposition apparatus. This allows for the deposition of insulating layers 212, 214, and 216 with reduced hydrogen content in the films, and further reduces the incorporation of hydrogen into the films between each deposition process.

[0263] Next, an opening is formed in the insulating layer 216 that reaches the insulating layer 214. This opening is formed in the region where the conductive layer 205 is formed. While wet etching may be used to form the opening, dry etching is preferable for microfabrication. Furthermore, it is preferable to select an insulator for the insulating layer 214 that functions as an etching stopper film when etching the insulating layer 216. For example, if silicon oxide or silicon oxynitride is used as the insulating layer 216, silicon nitride, aluminum oxide, or hafnium oxide may be used as the insulating layer 214.

[0264] After the above-mentioned opening is formed, a conductive film to become the conductive layer 205 is deposited, and a portion of the conductive film is removed by chemical mechanical polishing (CMP) until the insulating layer 216 is exposed. This makes it possible to form a conductive layer 205 embedded in the insulating layer 216, as shown in Figure 13A. In this embodiment, the conductive film is a laminated film of a titanium nitride film deposited using the CVD method and a tungsten film deposited on the titanium nitride film using the CVD method.

[0265] Next, as shown in Figure 13A, an insulating layer 221 is formed on the insulating layer 216 and the conductive layer 205, and then an insulating layer 222 is formed on the insulating layer 221. In this embodiment, a silicon nitride film is formed as the insulating layer 221 using the PEALD method, and a hafnium oxide film is formed as the insulating layer 222 using the thermal ALD method.

[0266] Next, as shown in Figure 13A, an insulating film 224f, which will become an insulating layer 224, is deposited on the insulating layer 222. In this embodiment, a silicon oxide film is deposited as the insulating film 224f using a sputtering method. By using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulating film 224f can be reduced. Since the insulating film 224f comes into contact with the semiconductor film 230f which will be deposited in a later step, it is preferable that the hydrogen concentration is reduced in this way.

[0267] Next, as shown in Figure 13A, a semiconductor film 230f is deposited on the insulating film 224f. In this embodiment, an indium oxide film is deposited as the semiconductor layer 230 using sputtering or ALD. Note that no conductive film, which will serve as the source and drain electrodes of the transistor, is deposited on the semiconductor film 230f.

[0268] Next, a heat treatment is preferable. For example, this heat treatment can be performed at a temperature of 450°C for 1 hour with a flow rate ratio of nitrogen gas to oxygen gas of 4:1. By performing this heat treatment, the crystallinity of the semiconductor layer 230 can be improved. This improves the on-current, S value, field-effect mobility, and frequency characteristics of the transistor 200, making it possible to realize a semiconductor device with good electrical characteristics. Furthermore, a highly reliable semiconductor device can be realized.

[0269] Furthermore, the heat treatment is preferably carried out in an atmosphere of nitrogen gas or an inert gas, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. The heat treatment may also be carried out under reduced pressure. Alternatively, after heat treatment in an atmosphere of nitrogen gas or an inert gas, the heat treatment may be carried out again in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to replenish the desorbed oxygen.

[0270] Furthermore, it is preferable that the gas used in the above heat treatment is highly purified. For example, the amount of water contained in the gas used in the above heat treatment is preferably 1 ppb or less, more preferably 0.1 ppb or less, and even more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent as much as possible from being incorporated into the semiconductor film 230f, etc. In addition, a highly purified gas can be used in the heat treatment before and after this step as well.

[0271] Furthermore, the heat treatment containing oxygen gas as described above can reduce impurities such as carbon, water, and hydrogen in the semiconductor film 230f. By reducing impurities in the film in this way, the crystallinity of the semiconductor film 230f can be improved, resulting in a denser, more compact structure. This increases the crystalline region in the semiconductor film 230f and reduces in-plane variation of the crystalline region within the semiconductor film 230f. Therefore, in-plane variation in the electrical characteristics of the transistor 200 can be reduced.

[0272] Furthermore, by performing a heat treatment, oxygen can be supplied to the semiconductor film 230f, thereby reducing oxygen deficiencies in the semiconductor film 230f. This can improve the reliability of the transistor 200.

[0273] Furthermore, by performing the heat treatment, hydrogen in the insulating layer 216, insulating film 224f, and semiconductor film 230f moves to the insulating layer 222 and is absorbed. In other words, hydrogen in the insulating layer 216, insulating film 224f, and semiconductor film 230f diffuses into the insulating layer 222. Therefore, the hydrogen concentration in the insulating layer 222 increases, but the hydrogen concentrations in the insulating layer 216, insulating film 224f, and semiconductor film 230f decrease. By providing an insulating layer 221 in contact with the lower surface of the insulating layer 222, it is possible to prevent moisture or impurities such as hydrogen from entering from below the insulating layer 221 during the heat treatment.

[0274] Next, the semiconductor film 230f and the insulating film 224f are processed into island-like structures using lithography. This forms the semiconductor layer 230 and the insulating layer 224, as shown in Figure 13B.

[0275] Dry etching or wet etching can be used to process the semiconductor film 230f and the insulating film 224f. Dry etching is suitable for microfabrication.

[0276] As shown in Figure 13B, the insulating layer 222 is exposed in areas that do not overlap with the insulating layer 224 and the semiconductor layer 230. However, this is not the only option; for example, as shown in Figure 12A, the insulating layer 224 can remain on top of the insulating layer 222 in areas that do not overlap with the semiconductor layer 230.

[0277] Furthermore, as shown in Figure 13B, the sides of the insulating layer 224 and the semiconductor layer 230 may be tapered. The taper angle of the sides of the insulating layer 224 and the semiconductor layer 230 can be, for example, 60° or more and less than 90°. By making the sides tapered in this way, the coverage of the insulating layer 275 and the like can be improved in subsequent processes, and defects such as porosity can be reduced.

[0278] Furthermore, although not limited to the above, the insulating layer 224 and the semiconductor layer 230 may be configured so that their sides are perpendicular or substantially perpendicular to the upper surface of the insulating layer 222. Such a configuration makes it possible to reduce the area and increase the density when providing multiple transistors.

[0279] In lithography, the resist is first exposed through a mask. Next, the exposed area is removed or left intact using a developer to form a resist mask. Then, by etching through the resist mask, conductors, semiconductors, or insulators can be processed into the desired shape. For example, a resist mask can be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, etc. Alternatively, immersion technology may be used, in which a liquid (e.g., water) is filled between the substrate and the projection lens for exposure. In addition, an electron beam or ion beam may be used instead of the aforementioned light. When using an electron beam or ion beam, a mask may not be necessary in some cases.

[0280] Furthermore, the resist mask that is no longer needed after processing can be removed by dry etching, such as ashing using oxygen plasma (hereinafter sometimes referred to as oxygen plasma treatment), wet etching, wet etching after dry etching, or dry etching after wet etching.

[0281] Furthermore, a hard mask consisting of an insulating layer or a conductive layer may be used beneath the resist mask. When using a hard mask, an insulating film or conductive film that will serve as the hard mask is formed on the semiconductor film 230f, a resist mask is formed on top of it, and the hard mask is etched to the desired shape. For example, tungsten may be used as the hard mask. Etching of the semiconductor film 230f, etc., may be performed after removing the resist mask, or it may be performed while the resist mask is still in place. In the latter case, the resist mask may disappear during etching. The hard mask may also be removed by etching after etching of the insulating layer 275, etc. On the other hand, if the material of the hard mask does not affect subsequent processes or can be used in subsequent processes, it is not always necessary to remove the hard mask.

[0282] Alternatively, a configuration may be used in which an SOC (Spin On Carbon) film and an SOG (Spin On Glass) film are deposited between the workpiece and the resist mask. By using the SOC film and SOG film as masks, the adhesion to the resist mask can be improved, and the durability of the mask pattern can be enhanced. For example, lithography can be performed by depositing the SOC film, SOG film, and resist mask in that order on the workpiece.

[0283] For dry etching, an etching gas containing halogens can be used. Specifically, an etching gas containing one or more of fluorine, chlorine, and bromine can be used. For example, as an etching gas, C ４ F ６ Gas, C ５ F ６ Gas, C ４ F ８ Gas, CF ４ Gas, SF６ Gas, CHF ３ Gas, CH ２ F ２ gas, Cl ２ Gas, BCl ３ Gas, SiCl ４ Gas, or BBr ３ Gases can be used individually or in mixtures of two or more gases. Furthermore, oxygen, carbon dioxide, nitrogen, helium, argon, hydrogen, or hydrocarbon gases can be appropriately added to the etching gas. Depending on the material being treated in the dry etching process, a gas containing hydrocarbons or hydrogen, but without halogen gases, can be used as the etching gas. Examples of hydrocarbons used in etching gases include methane (CH4). ４ ), ethane (C ２ H ６ ), propane (C ３ H ８ ), butane (C ４ H １０ ), ethylene (C ２ H ４ ), propylene (C ３ H ６ ), acetylene (C ２ H ２ ), and propine (C ３ H ４ One or more of the following can be used. The etching conditions can be set as appropriate according to the object to be etched.

[0284] As a dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high-frequency voltage to one electrode of the parallel plate electrodes. Alternatively, a high-frequency voltage of the same frequency may be applied to each of the parallel plate electrodes. Furthermore, a configuration in which multiple different high-frequency voltages are applied to the parallel plate electrodes may be used. Such a CCP etching apparatus is called a dual-frequency excited capacitively coupled plasma (DF-CCP) etching apparatus. In a DF-CCP etching apparatus, a configuration in which high-frequency voltages of different frequencies are applied to each of the parallel plate electrodes may be used. Alternatively, a configuration in which multiple different high-frequency voltages are applied to one of the parallel plate electrodes may be used. Alternatively, a dry etching apparatus having a high-density plasma source can be used. For example, an inductively coupled plasma (ICP) etching apparatus can be used as a dry etching apparatus having a high-density plasma source. The etching apparatus can be appropriately configured according to the object to be etched. In addition, reactive ion etching can be performed by applying a high-frequency voltage to the electrode on the substrate side of the dry etching apparatus to generate a self-bias potential. In reactive ion etching, etching is performed by accelerating ion species in the plasma and causing them to collide with the workpiece, thus enabling highly anisotropic etching.

[0285] Next, as shown in Figure 13C, an insulating layer 275 is formed covering the insulating layer 224 and the semiconductor layer 230, and then an insulating layer 280 is formed on top of the insulating layer 275. It is preferable to perform a CMP treatment after forming the insulating layer 280 to flatten the upper surface of the insulating layer 280.

[0286] As described above, a semiconductor layer 230 and an insulating layer 275 having a region in contact with the upper surface of the semiconductor layer 230 are formed by the steps shown in Figures 13A to 13C. The semiconductor layer 230 is formed to have, for example, indium oxide.

[0287] Next, as shown in Figure 13D, the insulating layer 280 and the insulating layer 275 are processed using lithography to form an opening 289 that reaches the semiconductor layer 230. The lithography method can be appropriately used as described above. To finely process the opening 289, it is preferable to use lithography using short-wavelength light such as EUV light or an electron beam.

[0288] Here, when a conductive film that will become the source electrode and drain electrode of the transistor is formed in the process shown in Figure 13A, the conductive film is also processed in the process shown in Figure 13D. Specifically, the region of the conductive film that overlaps with the opening 289 is removed using etching. Here, if the main component of the conductive film is the same as the main component of the semiconductor layer 230, the etching selectivity ratio between the conductive film and the semiconductor layer 230 will be low. For example, if the conductive film is an ITO film and the semiconductor layer 230 is an indium oxide film, the etching selectivity ratio between the conductive film and the semiconductor layer 230 will be low. Therefore, when processing the conductive film, the semiconductor layer 230 may be divided or deep recesses may be formed in the semiconductor layer 230. Specifically, in the region that overlaps with the opening 289, the semiconductor layer 230 may be divided or deep recesses may be formed in the semiconductor layer 230.

[0289] In one embodiment of the present invention, in the process shown in Figure 13A, conductive films that will serve as the source and drain electrodes of the transistor are not deposited on the semiconductor film 230f. Therefore, in the process shown in Figure 13D, division of the semiconductor layer 230 and the formation of deep depressions in the semiconductor layer 230 can be prevented, and a semiconductor device can be manufactured using a method with a high yield. Furthermore, since it is not necessary to deposit conductive films that will serve as the source and drain electrodes of the transistor on the semiconductor film 230f, the number of manufacturing steps for the semiconductor device can be reduced, and the productivity of the semiconductor device can be increased.

[0290] Next, as shown in Figure 13E, an insulating film 250f is formed to cover the insulating layer 280 and the semiconductor layer 230, forming the insulating layer 250.

[0291] Next, it is preferable to perform microwave processing in an oxygen-containing atmosphere. Here, microwave processing refers to processing using, for example, a device having a power supply that generates high-density plasma using microwaves. Furthermore, in this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less.

[0292] In microwave processing, it is preferable to use a microwave processing apparatus that has a power supply for generating high-density plasma using microwaves. Here, the frequency of the microwave processing apparatus is preferably 300 MHz to 300 GHz, more preferably 2.4 GHz to 2.5 GHz, and can be, for example, 2.45 GHz. By using high-density plasma, high-density oxygen radicals can be generated. Furthermore, the power of the power supply for applying microwaves to the microwave processing apparatus is preferably 1000 W to 10000 W, and more preferably 2000 W to 5000 W. The microwave processing apparatus may also have a power supply for applying RF to the substrate side. Furthermore, by applying RF to the substrate side, oxygen ions generated by the high-density plasma can be efficiently guided into the film.

[0293] Microwave treatment is preferably carried out under reduced pressure, with a pressure of 10 Pa to 1000 Pa, and more preferably 300 Pa to 700 Pa. The treatment temperature is preferably room temperature (25°C) to 750°C, more preferably 300°C to 500°C, and even more preferably 400°C to 450°C.

[0294] Furthermore, after microwave or plasma treatment, continuous heat treatment may be performed without exposure to the outside air. The heat treatment temperature is preferably, for example, 100°C to 750°C, more preferably 300°C to 500°C, and even more preferably 400°C to 450°C.

[0295] Microwave processing can be performed, for example, using oxygen gas and argon gas. Here, the oxygen flow rate ratio (O ２ / ( O ２+Ar)) is preferably greater than 0% and 100% or less, more preferably greater than 0% and 50% or less, more preferably 10% or more and 40% or less, and even more preferably 10% or more and 30% or less.

[0296] When the insulating film 250f is laminated, the microwave treatment described above is not necessarily performed after the insulating film 250f has been deposited. For example, when two or more layers of the insulating film 250f are laminated, the microwave treatment may be performed before depositing the layer that will be in contact with the conductive layer 260 to be formed in a later step, or after depositing the layer that will be in contact with the semiconductor layer 230, or after depositing the layer to be placed between these layers. Furthermore, the microwave treatment may be performed multiple times (at least twice or more).

[0297] Next, as shown in Figure 13E, a conductive film 260f, which will later become the conductive layer 260, is formed on the insulating film 250f. In this embodiment, the conductive film 260f is a laminated film of a titanium nitride film formed using the ALD method and a tungsten film formed on the titanium nitride film using the CVD method.

[0298] Next, the insulating film 250f and the conductive film 260f are polished by CMP treatment until the insulating layer 280 is exposed. In other words, the portions of the insulating film 250f and the conductive film 260f that are exposed from the opening 289 are removed. As a result, the insulating layer 250 and the conductive layer 260 on the insulating layer 250 can be formed so that they have a region located inside the opening 289, as shown in Figure 14A.

[0299] Next, as shown in Figure 14B, an insulating layer 282 is formed on the insulating layer 250, the conductive layer 260, and the insulating layer 280, an insulating layer 283 is formed on the insulating layer 282, and an insulating layer 285 is formed on the insulating layer 283. In this embodiment, an aluminum oxide film is formed as the insulating layer 282 using the sputtering method, a silicon nitride film is formed as the insulating layer 283 using the sputtering method, and a silicon oxide film is formed as the insulating layer 285 using the sputtering method.

[0300] Next, insulating layers 285, 283, 282, 280, and 275 are processed. This creates openings 243a and 243b in insulating layers 285, 283, 282, 280, and 275, as shown in Figure 14C. Openings 243a and 243b reach the semiconductor layer 230 and are formed to face each other with an opening 289 in between. The formation of openings 243a and 243b can be done using lithography. From the viewpoint of microfabrication, it is preferable to process the workpiece using a dry etching method when forming openings 243a and 243b.

[0301] Next, as shown in Figure 15A, impurity elements 271 are supplied to the semiconductor device. The process shown in Figure 15A allows for the supply of impurity elements 271 to the region overlapping with the opening 243a and the region overlapping with the opening 243b of the semiconductor layer 230. This allows for the formation of a low-resistance region 230na in the region overlapping with the opening 243a and a low-resistance region 230nb in the region overlapping with the opening 243b. Examples of impurity elements 271 include typical nonmetallic elements other than hydrogen, typical metallic elements, and transition elements (transition metals). For example, elements such as boron, phosphorus, magnesium, aluminum, and silicon are examples of impurity elements.

[0302] For supplying the impurity element 271, ion doping or ion implantation can be suitably used. These methods allow for highly precise control of the concentration profile in the depth direction by the ion acceleration voltage and dose.

[0303] By using an ion implantation method, in which the source gas is ionized and the ions are separated by mass before irradiation, the supply of elements other than impurity element 271 to the semiconductor device can be suppressed compared to the ion doping method. On the other hand, by using an ion doping method, in which the source gas is ionized and the ions are irradiated without mass separation, the productivity of the semiconductor device can be increased compared to the ion implantation method.

[0304] As the raw material gas for impurity element 271, the aforementioned gas containing the impurity element can be used. When supplying boron, typically B２ H ６ Gas, BF ３ Gas can be used. Also, when supplying phosphorus, pH is typically used. ３ Gases can be used. Alternatively, a mixed gas obtained by diluting these source gases with hydrogen or a noble gas may be used.

[0305] Other raw material gases include CH ４ , N ２ NH ３ , AlH ３ AlCl ３ SiH ４ Si ２ H ６ F ２ HF, H ２ , (C ５ H ５ ) ２ Magnesium (Mg), noble gases, etc., can be used. The raw material gas can be any of the above-mentioned gases individually or in a mixture of two or more. The ion source is not limited to gases; solids or liquids may be heated and vaporized.

[0306] Alternatively, the impurity element 271 may be supplied to the semiconductor layer 230 using, for example, plasma processing. In the case of plasma processing, the impurity element 271 can be supplied by generating plasma in a gas atmosphere containing the impurity element 271 to be supplied and performing plasma processing. As the apparatus for generating the plasma, a dry etching apparatus, an ashing apparatus, a plasma CVD apparatus, a high-density plasma CVD apparatus, etc., can be used.

[0307] Furthermore, it is preferable to perform the supply process of impurity elements 271 while heating the substrate (not shown). This allows for the repair of damage to the semiconductor layer 230 that occurs when impurity elements 271 are supplied. In other words, the supply of impurity elements 271 to the semiconductor layer 230 and the repair of damage caused by such supply can be performed in parallel.

[0308] In the supply process of impurity element 271, the substrate temperature is preferably 150°C or higher and below the strain point of the substrate, more preferably 200°C or higher and 500°C or lower, more preferably 200°C or higher and 450°C or lower, more preferably 250°C or higher and 400°C or lower, more preferably 250°C or higher and 350°C or lower, or more preferably 300°C or higher and 350°C or lower.

[0309] After supplying the impurity element 271, a heat treatment may be performed. By performing this heat treatment, damage to the semiconductor layer 230 sustained during the supply process of the impurity element 271 can be repaired.

[0310] The temperature of the heat treatment after supplying impurity element 271 is preferably 150°C or higher and below the strain point of the substrate, more preferably 200°C or higher and 700°C or lower, more preferably 200°C or higher and 650°C or lower, more preferably 250°C or higher and 500°C or lower, and more preferably 250°C or higher and 450°C or lower.

[0311] During the supply process of impurity elements, or after heating, some of the oxygen contained in the semiconductor layer 230 may diffuse into the low-resistance region 230na and combine with the impurity elements 271, as shown in Figure 2B. Similarly, some of the oxygen contained in the semiconductor layer 230 may diffuse into the low-resistance region 230nb and combine with the impurity elements 271. As a result, it is possible to deactivate excess oxygen contained in the semiconductor layer 230 by combining it with the impurity elements 271.

[0312] Furthermore, during the supply process of impurity elements, or during heating after supply, impurity elements 271 contained in the low-resistance region 230na and impurity elements 271 contained in the low-resistance region 230nb may diffuse. The diffusion of impurity elements 271 contained in the low-resistance region 230na may form a region 230nc that functions as an LDD region, as shown in Figure 2B. Similarly, the diffusion of impurity elements 271 contained in the low-resistance region 230nb may also form an LDD region.

[0313] As described above, in one aspect of the present invention, a highly reliable semiconductor device can be manufactured.

[0314] In the example shown in Figure 15A, the impurity element 271 is supplied to the semiconductor device with the upper surface of the insulating layer 285 exposed. In this case, the impurity element 271 is also supplied to the insulating layer 285. Therefore, the insulating layer 285 has regions where the concentration of the impurity element 271 is higher than, for example, the channel-forming region 230i.

[0315] In the process shown in Figure 14B, a mask layer may be formed on the insulating layer 285, for example, with a transmittance of impurity element 271 lower than that of the insulating layer 285. In this case, in the process shown in Figure 14C, openings 243a and 243b are formed not only in the insulating layers 275, 280, 282, 283, and 285, but also in the mask layer. Then, after supplying the impurity element 271 to the semiconductor device in the process shown in Figure 15A, the mask layer is removed. This suppresses the supply of impurity element 271 to the insulating layer 285. It also suppresses the supply of impurity element 271 to the insulating layers 283, 282, 280, and 275. As a result, it is possible to suppress fluctuations in the electrical characteristics of, for example, the transistor 200 due to impurity element 271 contained in the insulating layers 275, 280, 282, 283, or 285.

[0316] For example, a conductive material can be used for the mask layer. Alternatively, an insulating material or a semiconductor material may be used for the mask layer. When using an insulating material for the mask layer, a material with a high etching selectivity ratio with the insulating layer 285 should be used. When using a semiconductor material for the mask layer, a material with a high etching selectivity ratio with the semiconductor layer 230 should be used.

[0317] Figure 15A shows an example of supplying impurity element 271 to the semiconductor layer 230 from a direction perpendicular to the substrate surface. Figures 15B and 15C show examples of supplying impurity element 271 to the semiconductor layer 230 from a direction oblique to the substrate surface. For example, the process shown in Figure 15B can be performed first, followed by the process shown in Figure 15C. Alternatively, the process shown in Figure 15C can be performed first, followed by the process shown in Figure 15B. By supplying impurity element 271 to the semiconductor layer 230 from a direction oblique to the substrate surface, the semiconductor device shown in Figure 4B can be manufactured.

[0318] In Figures 15B and 15C, a dashed line, designated as axis B1-B2, is shown passing through the center of the surface of the substrate (not shown) and perpendicular to the surface of the substrate. The irradiation direction of the impurity element 271 shown in Figure 15C, specifically the irradiation direction of the ions of the impurity element 271, is symmetric with respect to axis B1-B2 to the irradiation direction of the impurity element 271 shown in Figure 15B. By performing both the processes shown in Figures 15B and 15C, that is, by supplying the impurity element 271 multiple times with different irradiation directions, low-resistance regions can be formed in both the region between the opening 243a and the conductive layer 260, and the region between the opening 243b and the conductive layer 260.

[0319] When the impurity element 271 is supplied to the semiconductor layer 230 in the manner shown in Figures 15B and 15C, as described above, the aspect ratio (H) of the openings 243a and 243b ＣＨ / W ＣＨ It is preferable that the ) is low. As a result, for example, when supplying impurity elements to the semiconductor layer 230 using an ion implantation method or an ion doping method, even if the impurity elements 271 are supplied to the semiconductor layer 230 from an oblique direction relative to the substrate surface, the impurity elements 271 can easily reach the semiconductor layer 230. Therefore, transistors with good electrical characteristics can be fabricated.

[0320] When impurity elements 271 are supplied to the substrate surface from an oblique direction, impurity elements 271 may also be supplied to the side walls of the opening 243a and the side walls of the opening 243b. Therefore, in the opening 243a and its vicinity, and in the opening 243b and its vicinity, the insulating layers 275, 280, 282, 283, and 285 may have regions where the concentration of impurity elements 271 is higher than, for example, the concentration of impurity elements 271 in the channel-forming region 230i.

[0321] In the examples shown in Figures 15B and 15C, the smaller the irradiation angle of the impurity element 271 to the substrate surface, specifically the irradiation angle of the ions of the impurity element 271 to the substrate surface, the easier it is to supply the impurity element 271 to the region between the opening 243a and the conductive layer 260 in the semiconductor layer 230, and the region between the opening 243b and the conductive layer 260. On the other hand, if the irradiation angle of the impurity element 271 to the substrate surface is too small, a large amount of impurity element 271 will not reach the semiconductor layer 230, making it difficult to form the low-resistance region 230na and the low-resistance region 230nb. The irradiation angle of the impurity element 271 to the substrate surface can be, for example, 10° or more and less than 90°, preferably 20° or more and 75° or less, and more preferably 30° or more and 60° or less. Here, the aspect ratio (H) of the openings 243a and 243b ＣＨ / W ＣＨ The lower the ) value, the smaller the irradiation angle of the impurity element 271 to the substrate surface, and the more effectively the impurity element can reach the semiconductor layer 230.

[0322] Next, as shown in Figure 16A, an insulating layer 241a is formed so as to have a region located inside the opening 243a, and an insulating layer 241b is formed so as to have a region located inside the opening 243b. For example, after depositing an insulating film to cover the openings 243a, 243b, and the insulating layer 285, the insulating layers 241a and 241b can be formed by processing the entire surface of the insulating film by anisotropic etching. This reduces the number of manufacturing steps for the semiconductor device compared to the case where the insulating layers 241a and 241b are formed using photolithography. In some cases, recesses 288, as shown in Figure 7A, etc., may be formed in the semiconductor layer 230 by this anisotropic etching. Specifically, recesses 288 may be formed in the low-resistance region 230na and the low-resistance region 230nb.

[0323] Next, as shown in Figure 16A, conductive films 245f, which will become conductive layers 245a and 245b, are formed such that they have a region located inside the opening 243a and a region located inside the opening 243b. The conductive film 245f is formed to have a region in contact with the semiconductor layer 230. Specifically, the conductive film 245f is formed to have a region in contact with the low-resistance region 230na and a region in contact with the low-resistance region 230nb. The conductive film 245f can be formed using, for example, sputtering, CVD, or ALD. The conductive film 245f can be formed to fill the openings 243a and 243b.

[0324] Next, a CMP treatment is performed to remove a portion of the conductive film 245f, exposing the upper surface of the insulating layer 285. As a result, the conductive film 245f remains inside the openings 243a and 243b, forming a conductive layer 245a with a region located inside the opening 243a, and a conductive layer 245b with a region located inside the opening 243b, as shown in Figure 16B. Note that the above CMP treatment may remove a portion of the upper surface of the insulating layer 285.

[0325] As described above, a semiconductor device having a transistor 200 can be fabricated. As previously stated, the conductive layer 245a functions as one of the source electrode and drain electrode of the transistor. The conductive layer 245b functions as the other of the source electrode and drain electrode of the transistor.

[0326] This embodiment can be combined with other embodiments as appropriate. Furthermore, if multiple configuration examples are shown within a single embodiment in this specification, these configuration examples can be combined as appropriate.

[0327] (Embodiment 2) This embodiment describes an indium oxide film that can be used in the semiconductor layer of a transistor in a semiconductor device according to one aspect of the present invention.

[0328] In this specification, indium oxide having at least a crystalline portion or crystalline region in the film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystal IO or crystalline IO include single-crystal indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0329] Indium oxide is a semiconductor material with completely different physical properties from oxide semiconductors such as In-Ga-Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0330] The carrier concentration dependence of the hole (Hall) mobility of indium oxide, silicon, and IGZO is described. Figure 17A shows silicon (Si) and indium oxide (InO Ｘ Figure 17B is a schematic diagram of the carrier concentration dependence of hole mobility for IGZO.

[0331] First, as indicated by the arrows in Figure 17B, IGZO tends to exhibit higher hole mobility as the carrier concentration increases. On the other hand, as indicated by the arrows in Figure 17A, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases (see Non-Patent Literature 3). This trend is similar to that of silicon, where the lower the concentration of dopants (impurities) in the material, the less impurity scattering occurs and the higher the hole mobility. In other words, the higher the purity and intrinsic nature of indium oxide, the higher its hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to silicon. Note that the properties of indium oxide shown in Figure 17A are assumed to be those of a single crystal. Therefore, when indium oxide is not a single crystal (for example, polycrystalline), the properties may differ from those shown in Figure 17A.

[0332] In Figure 17A, the range R1 with low carrier concentration exhibits extremely high hole mobility, making it a suitable carrier concentration range for, for example, the channel formation region of a transistor. For example, in the case of indium oxide, the range R1 has a carrier concentration of 1 × 10⁻⁶. １５ cm −３ This range includes, for example, 1 × 10 １４cm −３ The above is 1 x 10 １８ cm −３ The range is as follows: By sufficiently reducing the carrier concentration, the hole mobility value can be increased to 270 cm⁻¹. ２ It can be expected to be raised to the level of / (V・s).

[0333] Furthermore, in indium oxide, the region where the carrier concentration is in the range R1 may contain elements that lower the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Other elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0334] On the other hand, the range R2 with high carrier concentration has low electrical resistance and can be said to be a suitable range of carrier concentration for applications such as the source and drain regions of a transistor, or for resistors or transparent conductive films. The range R2 is when the carrier concentration value is 1 × 10⁻⁶. ２０ cm −３ This range includes, for example, 1 × 10 １９ cm −３ The above is 1 x 10 ２２ cm −３ The range is as follows: By making the carrier concentration sufficiently high, the resistivity can be increased to 1 × 10⁻⁶. −４ It is expected that the level can be reduced to below Ω·cm.

[0335] In the case of indium oxide, the region where the carrier concentration is in the range R2 may contain elements that increase the carrier concentration. For example, it is preferable to include elements common to the source and drain electrodes of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use elements whose oxides are conductive or semiconducting. As for the supply method of elements that increase the carrier concentration, a method of forming a film containing the element and diffusing it, ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment can be used. In this specification, unless otherwise specified, the presence or absence of mass separation is not limited. For example, in this specification, a method of supplying ions by mass separation is called ion implantation, and a method of supplying ions without mass separation is called ion doping.

[0336] In this way, indium oxide uses regions with low carrier concentrations for the transistor's channel formation region and regions with high carrier concentrations for the transistor's source and drain regions. In other words, indium oxide can be considered an oxide in which valence electron control is possible. Note that in IGZO, strain may be formed in the source and drain regions due to stress on the electrodes in contact with IGZO, and an n-type region may be formed. On the other hand, unlike IGZO, indium oxide allows for valence electron control, so it does not require strain to be formed in the film as in IGZO. Less strain in the film is expected to improve reliability. For example, by creating regions with carrier concentrations in the range R1 and range R2 shown in Figure 17A within the indium oxide film, a so-called n-i-n junction (a junction of an n-type region, an i-type region, and an n-type region) can be created. Note that valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technological concept that would not normally be conceived.

[0337] By applying the above technical concept, the indium oxide transistor described herein has two or more, preferably three or more, more preferably four or more, and most preferably five of the following features (1) to (5): (1) High on-current (in other words, high mobility). (2) Low off-current. (3) Normally off is possible. (4) High reliability. (5) High cutoff frequency (fT). For example, the indium oxide transistor described herein has high mobility, low off-current, and is normally off. This transistor is different from a transistor that is high mobility and normally on.

[0338] In addition, the i-type nature of a semiconductor means that the Fermi level (Ef) and the intrinsic Fermi level (Ei) are the same (Ef = Ei). As shown in Figure 17B, in IGZO, the lower the carrier concentration, the lower the hole mobility. Therefore, when Ef = Ei is reached, there are no carriers left (in other words, the material has properties similar to an insulator), and it may cease to function as a transistor. On the other hand, in indium oxide, as shown in Figure 17A, the lower the carrier concentration, the higher the hole mobility, and when Ef = Ei is reached, the hole mobility is maximized. That is, transistors containing indium oxide can achieve high field-effect mobility by setting Ef = Ei. Furthermore, because transistors containing indium oxide have a low carrier concentration, they tend to be normally off. Therefore, transistors containing indium oxide can be normally off and achieve high field-effect mobility.

[0339] Note that "normally-off" refers to a state where no current flows through the transistor when no potential is applied to the gate or when the gate-source voltage is 0 V. Also, "normally-off" can be evaluated by the threshold voltage (Vth) or shift value (Vsh) of the transistor. Unless otherwise specified, Vth shall be calculated by the constant current method. More specifically, Vth is the gate voltage (Vg) when the value of drain current (Id) × channel length (L) ÷ channel width (W) in the Id-Vg characteristics of the transistor becomes 1 nA (1 × 10 −９ A). Also, Vsh is the gate voltage (Vg) at the intersection of the tangent line with the maximum slope when the drain current (Id) in the Id-Vg characteristics of the transistor is expressed in logarithmic notation and the line of Id = 1 pA (1 × 10 −１２ A), or the Vg at the intersection of the extrapolated line from between two points with the maximum slope when Id is expressed in logarithmic notation in the Id-Vg characteristics of the transistor and the line of Id = 1 pA. For example, if either or both of Vth and Vsh are zero or positive values, it can be regarded as a normally-off transistor.

[0340] Also, in a transistor having indium oxide, in order to make the semiconductor i-type, that is, to achieve Ef = Ei, the film structure in contact with the indium oxide film is important. For example, in a transistor having indium oxide, a film structure in which a silicon oxide film, a hafnium oxide film, and a silicon nitride film in contact with the indium oxide film are laminated can be cited. By adopting such a film structure, Ef = Ei can be achieved, and a highly reliable semiconductor device can be obtained.

[0341] In the above-mentioned film structure, instead of the silicon oxide film, an oxygen-containing film such as a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, or a gallium oxide film can also be used. Also, in the above-mentioned film structure, instead of the silicon nitride film, a silicon nitride oxide film, a silicon oxynitride film, etc. can also be used. Also, the hafnium oxide film located closer to the indium oxide film side than the silicon nitride film functions as a hydrogen gettering site.

[0342] Further, the above-described film structure can be regarded as a structure in which a film capable of supplying oxygen to the indium oxide film (for example, a silicon oxide film), a film capable of gettering hydrogen (for example, a hafnium oxide film), and a film that suppresses the ingress of oxygen and hydrogen (for example, a silicon nitride film) are laminated from the indium oxide film side. By adopting such a structure, oxygen vacancies in the indium oxide film are replenished with oxygen in the silicon oxide film. Also, hydrogen in the indium oxide film is trapped by the hafnium oxide film by heat treatment or the like. Further, by providing the silicon nitride film, a film structure with less ingress of oxygen and hydrogen from the outside is obtained. That is, by adopting the above-described film structure, the indium oxide film can be made closer to the i-type. Therefore, the transistor having the above-described indium oxide film has high field-effect mobility and high reliability.

[0343] Next, the indium oxide film applied to the transistor will be described. The indium oxide film preferably has crystallinity (that is, has crystal grains). Examples of the film having crystal grains include a single crystal film, a polycrystalline film, or an amorphous film containing crystal grains (also referred to as a microcrystalline film). In particular, the indium oxide film is preferably a polycrystalline film, more preferably a single crystal film. A single crystal film does not have grain boundaries (also referred to as grain boundaries). Impurities that inhibit the flow of carriers (typically, insulating impurities, insulating oxides, etc.) tend to segregate at grain boundaries. By using a single crystal film, carrier scattering at grain boundaries and the like can be suppressed, and a transistor exhibiting high field-effect mobility can be realized. Also, excellent effects such as suppressing variations in transistor characteristics caused by the grain boundaries can be achieved.

[0344] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using polycrystalline films, it is preferable to use films with the largest possible grain size and few grain boundaries. In a transistor to which a polycrystalline indium oxide film is applied, if there are no grain boundaries in the channel formation region, or if no grain boundaries are observed, the channel formation region is located within the single-crystal region contained in the polycrystalline film, and therefore it can be considered a transistor to which single-crystal indium oxide is applied.

[0345] The crystallinity of indium oxide can be analyzed, for example, by X-ray diffraction (XRD), TEM, or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0346] Furthermore, in this specification, a semiconductor layer in which no grain boundaries are observed in the channel-forming region, a semiconductor layer in which the channel-forming region is contained within a single crystal grain, or a semiconductor layer in which the direction of the crystal axes is the same in at least two regions within the channel-forming region can be called a single crystal film. In addition, a semiconductor layer in which, within a single crystal grain in the channel-forming region, the direction of other crystal axes changes continuously with respect to a certain crystal axis or crystal orientation as the axis of rotation can be called a single crystal film.

[0347] The channel formation region refers to the area within the semiconductor layer that overlaps with (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, grain boundaries, crystal axes, and crystal orientation in the channel formation region can be confirmed by cross-sectional observation including the semiconductor layer, source electrode, and drain electrode.

[0348] The indium oxide film in the channel-forming region is preferable to have a low impurity concentration. Impurities in the indium oxide film in the channel-forming region can act as a scattering source for carriers, and thus can cause a decrease in field-effect mobility. Furthermore, these impurities can also inhibit crystal growth in the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The concentration of these impurities in the indium oxide film is preferably 0.1% or less, and more preferably 0.01% (100 ppm) or less. Note that elements such as carbon and hydrogen may be present in the deposition gas or precursor during film formation, and may remain in the indium oxide film in higher concentrations than the impurities mentioned above.

[0349] Furthermore, the indium oxide film in the channel-forming region may contain elements that can become trivalent cations like indium, as long as their crystals maintain a cubic crystal structure (Bixbite type). Examples include Group 13 elements of the periodic table such as gallium and aluminum, and Group 3 elements of the periodic table. Since these elements mainly exist as trivalent cations in the oxide, the carrier concentration of indium oxide can be kept low.

[0350] Furthermore, the indium oxide film described herein has a high film density. Here, an indium oxide film applicable to one aspect of the present invention (here, In ２ O ３ The membrane density of ) is shown in Table 1.

[0351]

[0352] As shown in Table 1, the film density of the indium oxide film was evaluated at six levels, Sample 1 to Sample 6. In Table 1, Condition 1 is the substrate condition for the indium oxide film, where Sample 1 to Sample 3 are glass, Sample 4 is a SiOx film formed by sputtering, and Sample 5 and Sample 6 are yttria-stabilized zirconia (YSZ). Condition 2 is the film deposition condition for the indium oxide film, where Sample 1 to Sample 3 are deposited by sputtering (SP), and Sample 4 to Sample 6 are deposited by ALD. Furthermore, condition 3 is the heat treatment condition after indium oxide film deposition. Sample 1, Sample 4, and Sample 5 are without heat treatment (as-depo), Sample 2 is baked at 350°C in a CDA atmosphere, Sample 3 is baked at 650°C in a CDA atmosphere, and Sample 6 is baked at 250°C in a vacuum atmosphere.

[0353] In Table 1, CDA stands for Clean Dry Air. It is preferable that the hydrogen and water content in the atmosphere during the heat treatment after indium oxide film formation (corresponding to condition 3) be kept to a minimum. It is preferable to use a high-purity gas with a dew point of -60°C or lower, preferably -100°C or lower, as this atmosphere.

[0354] As shown in Table 1, the indium oxide film tends to have a higher film density when heat-treated compared to when it is not heat-treated (Sample 1, Sample 4, or Sample 5). This is because the heat treatment causes impurity elements (e.g., carbon, nitrogen, hydrogen, argon, etc.) to be removed from the film, resulting in a higher purity in the indium oxide film. Furthermore, as shown in Sample 5 and Sample 6, the indium oxide film on YSZ has a film density of 7.00 g / cm³. ３ It exceeds [value]. The theoretical value of the film density of the indium oxide film is 7.18 g / cm³. ３ In this specification, the range of film density for indium oxide films is 6.70 g / cm³. ３ 7.18g / cm or more ３ The following, preferably 6.90 g / cm³３ 7.18g / cm or more ３ The following, and more preferably 7.00 g / cm³ ３ 7.18g / cm or more ３ The following applies:

[0355] Furthermore, film density can be evaluated using methods such as Rutherford backscattering (RBS) or X-ray reflectivity (XRR). Differences in film density can sometimes be evaluated using transmission electron microscopy (TEM) images of the cross-section. In TEM observation, a high film density results in a darker (more intense) transmission electron (TE) image, while a low film density results in a fainter (brighter) transmission electron (TE) image.

[0356] By using such an indium oxide film in a transistor, the field-effect mobility of the transistor can be increased to 50 cm². ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ It can be set to (V・s) or more.

[0357] One of the characteristics of indium oxide films is that they have higher oxygen permeability (diffusivity) compared to IGZO films. As shown in Figure 17C, indium oxide films (InO Ｘ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and oxygen molecules (O) ２ It is released as water molecules (H) by reacting with hydrogen contained in the membrane. ２ It may also be released as O. Furthermore, oxygen deficiencies (V) can form in the membrane. Ｏ If oxygen atoms are present, diffusing oxygen atoms will fill the oxygen deficiency. Indium oxide films allow oxygen to diffuse easily, so they can be said to fill oxygen deficiencies more easily than IGZO films.

[0358] Thus, because indium oxide films are more likely to reduce oxygen vacancies in the film compared to IGZO films, applying such indium oxide films to transistors makes it possible to realize transistors with extremely high reliability.

[0359] Furthermore, as shown in Figure 17C, the indium oxide film diffuses hydrogen. Hydrogen diffusing into the indium oxide film from the outside permeates the film and forms hydrogen molecules (H ２ It is released as ) or by reacting with oxygen contained in the film, and released as water molecules. The above-mentioned oxygen and hydrogen diffuse through the indium oxide film by heat treatment. The temperature of the heat treatment is 200°C to 700°C, preferably 350°C to 650°C, and more preferably 400°C to 500°C.

[0360] Transistors using indium oxide films are storage-type transistors that use electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, in a transistor, the on-current or field-effect mobility of the transistor can be increased.

[0361] Table 2 shows single crystal indium oxide (here, In ２ O ３ The effective masses of indium oxide and single-crystal silicon (Si) are shown below. As shown in Table 2, indium oxide is characterized by a small effective electron mass and a large effective hole mass. Furthermore, the effective electron mass of indium oxide is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in transistors, transistors with high field-effect mobility and high frequency characteristics (also called f-characteristics) can be realized. In addition, because the effective hole mass is large, transistors with extremely low off-currents can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width is 1 fA (1 × 10⁻¹⁶) in an environment of 125°C. −１５ A) Less than or equal to, or 1aA (1 × 10 −１８ A) Less than or equal to 1aA (1 × 10) in a room temperature (25°C) environment. −１８ A) Less than or equal to, or 1zA (1 × 10⁻¹⁰ −２１A) The following is possible. Furthermore, as shown in Table 2, indium oxide has a smaller effective electron mass and a larger effective hole mass than silicon, so it may be possible to realize a transistor with higher field-effect mobility and lower off-current than a Si transistor.

[0362]

[0363] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. It is preferable to use a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with the indium oxide for the seed layer. This improves the crystallinity of the indium oxide film. A substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0364] One method for evaluating the degree of lattice mismatch is to use the following lattice mismatch value. The lattice mismatch Δa [%] of the crystals in the formed film (in this case, the indium oxide film) relative to the crystals in the seed layer is given by Δa = ((L １ -L ２ ) / L ２ It is calculated as ) × 100. Here L １ L is the length of the unit cell vector of the crystals in the formed film, or the lattice constant. ２ is the length of the unit cell vector of the crystal in the seed layer, or the lattice constant.

[0365] The lattice mismatch Δa between the seed layer and the indium oxide film is preferably small in absolute value, and most preferably zero. For example, Δa can be -5% or more and 5% or less, preferably -4% or more and 4% or less, more preferably -3% or more and 3% or less, and even more preferably -2% or more and 2% or less.

[0366] Here, the indium oxide crystal has a cubic structure (bixbite type). For example, yttria-stabilized zirconia (YSZ) crystals can have a cubic structure (fluorite type). The lattice mismatch of the indium oxide crystal with respect to the cubic YSZ crystal is in the range of -2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on a YSZ substrate.

[0367] Furthermore, the crystal structure of the seed layer and the crystal structure of the indium oxide film do not necessarily have to be the same in terms of crystal system or crystal orientation. For example, a film with a hexagonal or trigonal crystal structure can be used beneath an indium oxide film with a cubic crystal structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to crystal orientation necessary for epitaxial growth can be met. Examples of hexagonal or trigonal crystals include wurtzite-type structures and YbFe. ２ O ４ Type structure, Yb ２ Fe ３ O ７ These include type structures and their modified type structures. YbFe ２ O ４ Type structure or Yb ２ Fe ３ O ７ An example of a crystal with a crystalline structure is IGZO. Indium oxide single crystal films can be formed not only on YSZ substrates but also on insulating films. On the other hand, it is difficult to form silicon single crystal films on insulating films. Silicon crystals have a diamond structure. Thus, in terms of single crystals, indium oxide and silicon have similar properties. However, when comparing indium oxide and silicon from the perspective of whether single crystals can be formed on insulating films, they have different properties.

[0368] Here, we compare transistors with crystalline indium oxide films, transistors with IGZO (In, Ga, Zn compound oxide) films, and transistors with silicon (Si) films. This comparison is shown in Table 3.

[0369]

[0370] In Table 3, transistors with a crystalline indium oxide film are explicitly labeled as "Crystal IO (LSI)" for LSI applications. Hereafter, they may simply be referred to as "Crystal IO". Transistors with a Si film are explicitly labeled as "Si (LSI)" for LSI applications. Hereafter, they may simply be referred to as "Si". Transistors with an IGZO film are explicitly labeled as "IGZO (Display)" for Display applications. Hereafter, they may simply be referred to as "IGZO". In Table 3, ◎ represents +2 points, ○ represents +1 point, △ represents 0 points, and × represents -1 point. Total is the sum of the points for ◎, ○, △, and × shown in Table 3. A higher point value indicates better performance than a lower point value.

[0371] In Table 3, the first comparison item is minimal off-current, in which crystalline IO and IGZO are superior to Si. The second comparison item is on-current (Ion) characteristics, in which Si, crystalline IO, and IGZO have the highest characteristics. The third comparison item is reliability, in which crystalline IO and Si are superior to IGZO. The fourth comparison item is channel length miniaturization, in which crystalline IO and IGZO are superior to Si. In the channel length miniaturization item, VFET represents a vertical transistor, UFET represents a U-shaped transistor, and 3D structure represents a three-dimensional structure. The fifth comparison item is cutoff frequency, in which crystalline IO and Si are superior to IGZO. The sixth comparison item is improved integration density, in which Si is superior to crystalline IO and IGZO. Furthermore, the seventh comparison item is threshold voltage controllability (Vth controllability), in which Si is superior to crystalline IO and IGZO. The eighth comparison item is radiation resistance, in which crystalline IO and IGZO are superior to Si. The ninth comparison item is 3D (multi-stage) integrated structure, in which crystalline IO and IGZO are superior to Si. The tenth comparison item is the potential for self-heating, in which crystalline IO and IGZO are superior to Si.

[0372] As shown in Table 3, as the Total score, Crystal IO (LSI) is 8 points, and Si (LSI) and IGZO (Display) are each 4 points. Thus, the semiconductor device of one aspect of the present invention, particularly the semiconductor device having a crystalline indium oxide film, may replace the semiconductor device using Si.

[0373] This embodiment can be appropriately combined with other embodiments. Also, in this specification, when multiple configuration examples are shown within one embodiment, the configuration examples can be appropriately combined.

[0374] (Embodiment 3) In this embodiment, a semiconductor device 900 according to one aspect of the present invention will be described. The semiconductor device 900 can function as a memory device.

[0375] FIG. 18 shows a block diagram illustrating a configuration example of the semiconductor device 900. The semiconductor device 900 shown in FIG. 18 includes a drive circuit 910 and a memory array 920. The memory array 920 includes one or more memory cells 950. FIG. 18 shows an example in which the memory array 920 includes a plurality of memory cells 950 arranged in a matrix.

[0376] The transistor 200 described in Embodiment 1 can be applied to the memory cell 950. By using the transistor described in Embodiment 1, the operating speed of the memory device can be improved. Also, miniaturization and high integration of the memory device can be achieved. Further, the capacity per area of the memory device can be increased.

[0377] The drive circuit 910 includes a PSW 931 (power switch), a PSW 932, and a peripheral circuit 915. The peripheral circuit 915 includes a peripheral circuit 911, a control circuit 912, and a voltage generation circuit 928.

[0378] In the semiconductor device 900, each circuit, each signal, and each voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or other signals may be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are external input signals, and signal RDA is an external output signal. Signal CLK is a clock signal.

[0379] Furthermore, signals BW, CE, and GW are control signals. Signal CE is the chip enable signal, signal GW is the global write enable signal, and signal BW is the byte write enable signal. Signal ADDR is the address signal. Signal WDA is the write data signal, and signal RDA is the read data signal. Signals PON1 and PON2 are power gating control signals. Signals PON1 and PON2 may be generated by the control circuit 912.

[0380] The control circuit 912 is a logic circuit that has the function of controlling the overall operation of the semiconductor device 900. For example, the control circuit 912 performs logical operations on signals CE, GW, and BW to determine the operating mode of the semiconductor device 900 (e.g., write operation, read operation). Alternatively, the control circuit 912 generates control signals for the peripheral circuit 911 so that this operating mode is executed.

[0381] The voltage generation circuit 928 has the function of generating a negative voltage. The signal WAKE has the function of controlling the input of the signal CLK to the voltage generation circuit 928. For example, when a high-level signal is given as the signal WAKE, the signal CLK is input to the voltage generation circuit 928, and the voltage generation circuit 928 generates a negative voltage.

[0382] The peripheral circuit 911 is a circuit for writing and reading data to and from the memory cell 950. The peripheral circuit 911 includes a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.

[0383] The row decoder 941 and column decoder 942 have the function of decoding the ADDR signal. The row decoder 941 is a circuit for specifying the row to access, and the column decoder 942 is a circuit for specifying the column to access. The row driver 923 has the function of selecting the row specified by the row decoder 941. The column driver 924 has the function of writing data to the memory cell 950, reading data from the memory cell 950, and holding the read data.

[0384] The input circuit 925 has the function of holding the signal WDA. The data held by the input circuit 925 is output to the column driver 924. The output data of the input circuit 925 is the data (Din) to be written to the memory cell 950. The data (Dout) read by the column driver 924 from the memory cell 950 is output to the output circuit 926. The output circuit 926 has the function of holding Dout. The output circuit 926 also has the function of outputting Dout to the outside of the semiconductor device 900. The data output from the output circuit 926 is the signal RDA.

[0385] PSW931 provides V to peripheral circuit 915 ＤＤ It has the function of controlling the supply. PSW932 has the function of V to line driver 923 ＨＭ It has a function to control the supply. Here, the high power supply potential of the semiconductor device 900 is V ＤＤ Therefore, the low power supply potential is GND (ground potential). Also, V ＨＭ This is a high power supply potential used to raise the word line to a high level, V ＤＤ It is higher than that. The on / off state of PSW931 is controlled by signal PON1, and the on / off state of PSW932 is controlled by signal PON2. In Figure 18, in peripheral circuit 915, V ＤＤ The number of power domains supplied is set to one, but it can be multiple. In this case, a power switch is provided for each power domain.

[0386] Using Figures 19A to 19G, an example of a memory cell configuration applicable to the memory cell 950 will be explained.

[0387] [DOSRAM] Figure 19A shows an example of the circuit configuration of a memory cell of a DRAM (Dynamic Random Access Memory). In this specification, a DRAM using an OS transistor is called a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). The memory cell 951 has a transistor M1 and a capacitive element CA.

[0388] Transistor M1 may have a front gate (sometimes simply called a gate) and a back gate. In this case, the back gate may be connected to a wire to which a constant potential or signal is supplied, or the front gate and back gate may be connected.

[0389] One of the source and drain terminals of transistor M1 is connected to one electrode of the capacitive element CA, the other of the source and drain terminals of transistor M1 is connected to wiring BIL, and the gate of transistor M1 is connected to wiring WOL. The other electrode of the capacitive element CA is connected to wiring CAL.

[0390] Wiring BIL functions as a bit line, and wiring WOL functions as a word line. Wiring CAL functions as wiring for applying a predetermined potential to the other electrode of the capacitive element CA. When writing and reading data, it is preferable to apply a low-level potential (sometimes called a reference potential) to wiring CAL.

[0391] Data writing and reading are performed by applying a high-level potential to the wiring WOL, turning on transistor M1, and creating a conductive state (a state in which current can flow) between the wiring BIL and one electrode of the capacitive element CA.

[0392] Furthermore, the memory cell that can be used in memory cell 950 is not limited to memory cell 951, and the circuit configuration can be changed. For example, the memory cell 952 may have the configuration shown in Figure 19B. Memory cell 952 is an example in which there is no capacitive element CA and wiring CAL. One of the source and drain of transistor M1 is electrically floating.

[0393] In the memory cell 952, the potential written via transistor M1 is held in the capacitance (also called parasitic capacitance) between the source and drain of transistor M1 and the gate. In Figure 19B, this parasitic capacitance is shown by a dashed line. This configuration significantly simplifies the structure of the memory cell.

[0394] Furthermore, it is preferable to use an OS transistor as transistor M1. Using an OS transistor can improve the operating speed of the memory device. In addition, OS transistors have the characteristic of having an extremely small off-current. By using an OS transistor as transistor M1, the leakage current of transistor M1 can be made very small. In other words, since the written data can be held by transistor M1 for a long time, the frequency of refreshing the memory cell can be reduced. Alternatively, the refresh operation of the memory cell can be made unnecessary. Also, because the leakage current is very small, multi-level data or analog data can be held in memory cells 951 and 952.

[0395] Here, an example of the structure of a DOSRAM will be explained using Figure 20. In Figure 20, the X direction is parallel to the channel width direction of the transistor, the Y direction is perpendicular to the X direction, and the Z direction is perpendicular to both the X and Y directions.

[0396] As shown in Figure 20, the memory cell 951 has a transistor M1 and a capacitive element CA. The capacitive element CA has a conductive layer 410, an insulating layer 430 on the conductive layer 410, and a conductive layer 420 on the insulating layer 430. The conductive layer 410 functions as one electrode of the capacitive element CA. The conductive layer 420 functions as the other electrode of the capacitive element CA. The insulating layer 430 functions as the dielectric of the capacitive element CA. The capacitive element CA constitutes a MIM (Metal-Insulator-Metal) capacitance.

[0397] Figure 20 shows an example where the capacitive element CA is planar in shape, but the memory device shown in this embodiment is not limited to this. For example, the capacitive element CA can also be cylindrical in shape.

[0398] For the conductive layer 410 and conductive layer 420, materials that can be used for conductive layer 260, for example, can be used. For conductive layer 410 and conductive layer 420, for example, tungsten can be used. Figure 20 shows an example in which the insulating layer 430 and the conductive layer 420 on the insulating layer 430 cover the top and side surfaces of the conductive layer 410. This allows the side surfaces of the conductive layer 410 to function as part of the capacitive element CA. Therefore, the capacitance of the capacitive element CA can be increased compared to the case in which the insulating layer 430 and conductive layer 420 do not cover the side surfaces of the conductive layer 410.

[0399] It is preferable to use the high-k material shown in Embodiment 1 for the insulating layer 430. This allows the insulating layer 430 to be made thick enough to suppress leakage current, while also ensuring sufficient capacitance of the capacitive element CA. Furthermore, since the insulating layer 430 is formed covering the conductive layer 410, it is preferable to form it using a film deposition method with good coverage, such as the ALD method or the CVD method.

[0400] Furthermore, the insulating layer 430 can also be a laminated structure. For example, it is preferable to have a laminated structure of a high-k material and a material with a higher dielectric strength than the high-k material. For materials with high dielectric strength, refer to Embodiment 1. Here, as shown in Embodiment 1, a material with high dielectric strength is also a material with a low relative permittivity. The insulating layer 430 can be, for example, a laminated structure of aluminum oxide, which is a high-k material, and silicon oxide with high dielectric strength on the aluminum oxide.

[0401] Furthermore, as the insulating layer 430, for example, an insulating film laminated in the order of zirconium oxide film, aluminum oxide film, and zirconium oxide film can be used. Alternatively, as the insulating layer 430, for example, an insulating film laminated in the order of zirconium oxide film, aluminum oxide film, zirconium oxide film, and aluminum oxide film can be used. Alternatively, as the insulating layer 430, for example, an insulating film laminated in the order of hafnium zirconium oxide film, aluminum oxide film, hafnium zirconium oxide film, and aluminum oxide film can be used. By using an insulating film with relatively high dielectric strength, such as an aluminum oxide film, the dielectric strength can be improved, and electrostatic discharge breakdown of the capacitive element CA can be suppressed.

[0402] Alternatively, the insulating layer 430 may be made of a material capable of having ferroelectric properties as shown in Embodiment 1.

[0403] An insulating layer 213 is provided beneath the insulating layer 212 located beneath the transistor M1. The insulating layer 213 functions as an interlayer insulating layer. The insulating layer 213 can be made of the same material that can be used for the insulating layer 280.

[0404] A conductive layer 412 is provided on the conductive layer 245a, the insulating layer 241a, and the insulating layer 285. The conductive layer 412 may have a region that contacts the upper surface of the conductive layer 245a, for example. This allows the conductive layer 245a and the conductive layer 412 to be connected. The conductive layer 412 functions as wiring.

[0405] A conductive layer 410 is provided on the conductive layer 245b, the insulating layer 241b, and the insulating layer 285. The conductive layer 410 may have a region that contacts the upper surface of the conductive layer 245b, for example. This allows the conductive layer 245b and the conductive layer 410 to be connected. The conductive layer 410 is made of the same material as the conductive layer 412 and can be formed using the same process.

[0406] An insulating layer 487 is provided on the capacitive element CA, on the conductive layer 412, and on the insulating layer 285. The insulating layer 487 is provided so as to cover the conductive layer 420 and the conductive layer 412. An insulating layer 488 is provided on the insulating layer 487.

[0407] For the insulating layer 487, it is preferable to use an insulating film that has the function of capturing or fixing hydrogen. For example, it is preferable to use an aluminum oxide film for the insulating layer 487. For the insulating layer 488, it is preferable to use an insulating film that has the function of suppressing hydrogen diffusion. For example, it is preferable to use a silicon nitride film with higher hydrogen barrier properties for the insulating layer 488.

[0408] Furthermore, it is preferable that the insulating layer 487 has a laminated structure. For example, if the insulating layer 487 has a two-layer laminated structure, it is preferable that the first layer (lower layer) is deposited using the ALD method and the second layer (upper layer) is deposited using the sputtering method. For example, the first layer of the insulating layer 487 can be an aluminum oxide film deposited by the thermal ALD method, and the second layer of the insulating layer 487 can be an aluminum oxide film deposited by the sputtering method. By depositing the second layer of the insulating layer 487 using the sputtering method after the first layer of the insulating layer 487 has been deposited, the capacitive element CA and the like can be protected from the impact of ion collisions caused by the sputtering deposition of the second layer of the insulating layer 487. In addition, by depositing the first layer of the insulating layer 487 using the ALD method, which has good step coverage, the first layer of the insulating layer 487 can be deposited without forming pinholes or step breaks even on steps of the capacitive element CA and the like.

[0409] Furthermore, it is preferable that the insulating layer 488 has a laminated structure. For example, if the insulating layer 488 has a two-layer laminated structure, it is preferable that the first layer (lower layer) is deposited using the sputtering method and the second layer (upper layer) is deposited using the ALD method. For example, the first layer of the insulating layer 488 can be silicon oxide deposited by the sputtering method, and the second layer of the insulating layer 488 can be silicon oxide deposited by the PEALD method. Even if a pinhole or step is formed in the first layer of the insulating layer 488 near a step in a capacitive element CA or the like, the barrier properties against hydrogen can be maintained by covering it with the second layer of the insulating layer 488 deposited by the ALD method, which has good step coverage properties.

[0410] In this way, by providing the insulating layer 488 on top of the capacitive element CA, the diffusion of hydrogen from the upper layer of the capacitive element CA can be suppressed. Furthermore, by providing the insulating layer 487 below the insulating layer 488, hydrogen contained in the capacitive element CA, insulating layer 285, etc., can be captured or fixed to the insulating layer 487.

[0411] An insulating layer 450 is provided on the insulating layer 488. The insulating layer 450 functions as an interlayer insulating layer. The insulating layer 450 can be made from the same material that can be used for the insulating layer 280.

[0412] The insulating layers 487, 488, and 450 have openings that reach the conductive layer 420. The conductive layer 440 is provided such that it has a region located inside the opening. The conductive layer 440 functions as a plug and is connected to the conductive layer 420. The conductive layer 440 can, for example, be in contact with the upper surface of the conductive layer 420. The conductive layer 440 can be made of, for example, the same material that can be used for the conductive layers 245a and 245b.

[0413] In Figure 20, conductive layers 410, 412, 420, and 440 are shown as single-layer structures, but the configuration is not limited to this, and a laminated structure of two or more layers is also possible. For example, a laminated structure of a conductive film with barrier properties and a conductive film with high conductivity is possible. For example, a laminated structure of a titanium nitride film and a tungsten film on the titanium nitride film is possible.

[0414] A conductive layer 462 is provided on the conductive layer 440 and on the insulating layer 450. The conductive layer 462 is connected to the conductive layer 440. The conductive layer 462 may have a region that is in contact with the upper surface of the conductive layer 440, for example. The conductive layer 420 and the conductive layer 462 are connected via the conductive layer 440. The conductive layer 462 functions as wiring. For example, the conductive layer 462 can be made of the same material that can be used for the conductive layer 260.

[0415] In Figure 20, the conductive layer 462 is shown as a single-layer structure, but the structure is not limited to this configuration and can also be a laminated structure of two or more layers. For example, a highly conductive metal material can be sandwiched between metal materials with high heat resistance. Aluminum, copper, etc. can be used as the highly conductive metal material. Molybdenum, titanium, tungsten, and other metal materials, or nitrides thereof, can be used as the metal material with high heat resistance.

[0416] For example, the conductive layer 462 can be made into a five-layer laminated structure. For instance, highly conductive aluminum can be used for the third layer of the conductive layer 462, highly heat-resistant titanium for the first (bottom) and fourth layers, and highly heat-resistant titanium nitride for the second and fifth (top) layers. With such a configuration, even if aluminum with low heat resistance is used, defects such as hillocks, whiskers, or migration can be suppressed. Therefore, the conductive layer 462 can function as a highly conductive wiring.

[0417] An insulating layer 470 is provided on the conductive layer 462 and on the insulating layer 450. The insulating layer 470 functions as an interlayer insulating layer. The insulating layer 470 can be made of the same material that can be used for the insulating layer 280.

[0418] [NOSRAM] Figure 19C shows an example of a circuit configuration for a gain cell type memory cell with two transistors and one capacitance element. The memory cell 953 has a transistor M2, a transistor M3, and a capacitance element CB. In this specification, a memory device having a gain cell type memory cell using an OS transistor for transistor M2 is called NOSRAM (Nonvolatil Oxide Semiconductor RAM).

[0419] One of the source and drain of transistor M2 is connected to one electrode of the capacitive element CB, the other of the source and drain of transistor M2 is connected to wiring WBL, and the gate of transistor M2 is connected to wiring WOL. The other electrode of the capacitive element CB is connected to wiring CAL. One of the source and drain of transistor M3 is connected to wiring RBL, the other of the source and drain of transistor M3 is connected to wiring SL, and the gate of transistor M3 is connected to one electrode of the capacitive element CB.

[0420] Wiring WBL functions as a write bit line, wiring RBL functions as a read bit line, and wiring WOL functions as a word line. Wiring CAL functions as wiring for applying a predetermined potential to the other electrode of the capacitive element CB. When writing data, during data retention, and when reading data, it is preferable to apply a low-level potential (sometimes called a reference potential) to wiring CAL.

[0421] Data writing is performed by applying a high-level potential to the wiring WOL, turning on transistor M2, and creating a conductive state between the wiring WBL and one electrode of the capacitive element CB. Specifically, when transistor M2 is ON, a potential corresponding to the information to be recorded in the wiring WBL is applied, and this potential is written to one electrode of the capacitive element CB and the gate of transistor M3. Subsequently, a low-level potential is applied to the wiring WOL, turning off transistor M2, thereby maintaining the potential of one electrode of the capacitive element CB and the potential of the gate of transistor M3.

[0422] Data is read by applying a predetermined potential to the wiring SL. The current flowing between the source and drain of transistor M3, and the potential of one of the source and drain of transistor M3, are determined by the potential of the gate of transistor M3 and the potential of the other of the source and drain of transistor M3. Therefore, by reading the potential of the wiring RBL connected to one of the source and drain of transistor M3, the potential held at one electrode of the capacitive element CB (or the gate of transistor M3) can be read. In other words, the information written to this memory cell can be read from the potential held at one electrode of the capacitive element CB (or the gate of transistor M3).

[0423] Alternatively, for example, the wiring WBL and wiring RBL may be combined into a single wiring BIL. An example of the circuit configuration of such a memory cell is shown in Figure 19D. Memory cell 954 is configured such that the wiring WBL and wiring RBL of memory cell 953 are combined into a single wiring BIL, and the other source and drain of transistor M2, and one source and drain of transistor M3 are connected to the wiring BIL. In other words, memory cell 954 is configured to operate with the write bit line and the read bit line as a single wiring BIL.

[0424] The memory cell 955 shown in Figure 19E is an example where the capacitive element CB and wiring CAL in memory cell 953 are omitted. Similarly, the memory cell 956 shown in Figure 19F is an example where the capacitive element CB and wiring CAL in memory cell 954 are omitted. By using such a configuration, the integration density of memory cells can be increased.

[0425] Furthermore, it is preferable to use an OS transistor for at least transistor M2. In particular, it is preferable to use OS transistors for transistors M2 and M3. By using an OS transistor as transistor M2, the written data can be held by transistor M2 for a long time, thereby reducing the frequency of memory cell refresh. Alternatively, it may be possible to eliminate the need for memory cell refresh operations. In addition, because the leakage current is very small, multi-level data or analog data can be held in memory cells 953 to 956.

[0426] Memory cells 953 to 956, which use an OS transistor as transistor M2, represent one form of NOSRAM.

[0427] Furthermore, a Si transistor may be used as transistor M3. Si transistors can increase field-effect mobility and can also be made into p-channel transistors, thus increasing the flexibility of circuit design.

[0428] Figure 19G also shows a gain cell type memory cell 957 with three transistors and one capacitance element. The memory cell 957 has transistors M4 to M6 and a capacitance element CC.

[0429] One source and drain of transistor M4 is connected to one electrode of capacitive element CC, the other source and drain of transistor M4 is connected to wiring BIL, and the gate of transistor M4 is connected to wiring WOL. The other electrode of capacitive element CC is connected to one source and drain of transistor M5 and to wiring GNDL. The other source and drain of transistor M5 is connected to one source and drain of transistor M6, and the gate of transistor M5 is connected to one electrode of capacitive element CC. The other source and drain of transistor M6 is connected to wiring BIL, and the gate of transistor M6 is connected to wiring RWL.

[0430] Wiring BIL functions as a bit line, wiring WOL functions as a write word line, and wiring RWL functions as a read word line. Wiring GNDL is a wire that provides a low level potential.

[0431] Data writing is performed by applying a high-level potential to the wiring WOL, turning on transistor M4, and creating a conductive state between the wiring BIL and one electrode of the capacitive element CC. Specifically, when transistor M4 is ON, a potential corresponding to the information to be recorded in wiring BIL is applied, and this potential is written to one electrode of the capacitive element CC and the gate of transistor M5. Subsequently, a low-level potential is applied to the wiring WOL, turning off transistor M4, thereby maintaining the potential of one electrode of the capacitive element CC and the potential of the gate of transistor M5.

[0432] Data is read by precharging the wiring BIL to a predetermined potential, then electrically freezing the wiring BIL, and applying a high-level potential to the wiring RWL. As the wiring RWL reaches a high-level potential, transistor M6 turns ON, and the other source and drain of the wiring BIL become conductive. At this time, the potential of the wiring BIL is applied to the other source and drain of transistor M5, but the potential of the other source and drain of transistor M5, and the potential of the wiring BIL change depending on the potential held by one electrode of the capacitive element CC (or the gate of transistor M5). Here, by reading the potential of the wiring BIL, the potential held by one electrode of the capacitive element CC (or the gate of transistor M5) can be read. In other words, the information written to this memory cell can be read from the potential held by one electrode of the capacitive element CC (or the gate of transistor M5).

[0433] Furthermore, it is preferable to use an OS transistor for at least transistor M4.

[0434] Note that Si transistors may be used as transistors M5 and M6. As mentioned above, depending on the crystal state of the silicon used in the semiconductor layer, Si transistors may have a higher field-effect mobility than OS transistors.

[0435] The drive circuit 910 and memory array 920 of the semiconductor device 900 may be provided on the same plane. Alternatively, as shown in Figure 21A, the drive circuit 910 and memory array 920 may be stacked on top of each other. By stacking the drive circuit 910 and memory array 920, the signal propagation distance can be shortened. Furthermore, as shown in Figure 21B, multiple memory arrays 920 may be stacked on top of the drive circuit 910.

[0436] Figure 22 is a cross-sectional view showing an example of the configuration of a semiconductor device 900 in which multiple layers of memory arrays 920 are stacked. The semiconductor device 900 shown in Figure 22 has a drive circuit 910 which is a layer having transistors 310, etc., and memory arrays 920[1] to memory arrays 920[m] (where m is an integer of 2 or more; in the example shown in Figure 22, m is an integer of 3 or more) on the drive circuit 910. Here, the layer provided as the first layer (bottommost) is referred to as memory array 920[1], the layer provided as the second layer is referred to as memory array 920[2], and the layer provided as the mth layer (topmost) is referred to as memory array 920[m], as shown in Figure 22. In other words, a memory device according to one aspect of the present invention may have a configuration in which multiple layers are stacked, with each layer containing a memory cell.

[0437] Figure 22 illustrates a transistor 310 in the drive circuit 910. The transistor 310 is provided on a substrate 311 and includes a conductive layer 316 that functions as a gate, an insulating layer 315 that functions as a gate insulating layer, a semiconductor region 313 that includes a part of the substrate 311, a low-resistance region 314a that functions as one of the source region and drain region, and a low-resistance region 314b that functions as the other of the source region and drain region. It is also preferable that an element isolation layer 318 is provided between adjacent transistors 310. The transistor 310 may be either a p-channel type transistor or an n-channel type transistor. For example, a single-crystal silicon substrate can be used as the substrate 311.

[0438] In this transistor 310, the semiconductor region 313 (part of the substrate 311) where the channel is formed has a convex shape. Furthermore, the sides and top surface of the semiconductor region 313 are covered by a conductive layer 316 via an insulating layer 315. The conductive layer 316 may be made of a material that adjusts the work function. Such a transistor 310 is also called a FIN type transistor because it utilizes the convex portion of the semiconductor substrate. Furthermore, there may be an insulating layer in contact with the upper part of the convex portion that functions as a mask for forming the convex portion. In addition, although the case of forming the convex portion by processing a part of the semiconductor substrate is shown here, a semiconductor film having a convex shape may be formed by processing an SOI substrate.

[0439] Note that the transistor 310 shown in Figure 22 is just one example, and its structure is not limited to that; an appropriate transistor can be used depending on the circuit configuration or driving method.

[0440] Between each structure, there may be an interlayer insulating layer, wiring, and a wiring layer containing plugs, etc. Furthermore, multiple wiring layers may be provided depending on the design. Here, conductive layers that function as plugs or wiring may be grouped together and assigned the same reference numeral. Also, in this specification, the wiring and the plug connected to the wiring may be a single integrated unit. That is, there may be cases where a part of the conductive layer functions as wiring, and cases where a part of the conductive layer functions as a plug.

[0441] For example, on the transistor 310, insulating layers 320, 322, 324, and 326 are stacked in order as interlayer insulating layers. In addition, conductive layers such as 328 are embedded in insulating layers 320 and 322. In addition, conductive layers such as 330 are embedded in insulating layers 324 and 326. Conductive layers 328 and 330 function as plugs or wiring, respectively.

[0442] Furthermore, the insulating layer, which functions as an interlayer insulating layer, may also function as a planarizing film that covers the uneven shape below it. For example, the upper surface of the insulating layer 322 may be planarized by CMP treatment to improve its flatness.

[0443] Applicable insulators for interlayer insulating layers include insulating oxides, nitrides, oxidized nitrides, nitride oxides, metal oxides, metal oxidized nitrides, and metal nitride oxides.

[0444] For example, by using a material with a low dielectric constant for an insulating layer that functions as an interlayer insulating layer, parasitic capacitance between wiring can be reduced. Therefore, it is preferable to select the material according to the function of the insulating layer.

[0445] An insulating layer 208 is provided on the drive circuit 910. The insulating layer 208 functions as an interlayer insulating layer. The insulating layer 208 can be made of the same material that can be used for the insulating layer 216.

[0446] An opening is provided in the insulating layer 208, and a conductive layer 207 is provided such that it has a region located inside the opening. The conductive layer 207 functions as a plug and is connected to the drive circuit 910. The conductive layer 207 can be made of the same material that can be used for the conductive layer 440 shown in Figure 20.

[0447] A conductive layer 209 is provided on the conductive layer 207 and the insulating layer 208. The conductive layer 209 functions as wiring and is connected to the conductive layer 207. The conductive layer 209 may have, for example, a region that is in contact with the upper surface of the conductive layer 207. The conductive layer 209 can be made of the same material that can be used for the conductive layer 462 shown in Figure 20.

[0448] An insulating layer 213 is provided on the conductive layer 209 and on the insulating layer 208. On the insulating layer 213, similar to the memory device shown in Figure 20, an insulating layer 212 and an insulating layer 214 on the insulating layer 212 are provided. The insulating layer 213, insulating layer 212, and insulating layer 214 are provided with openings that reach the conductive layer 209, and the conductive layer 211 is provided such that it has a region located inside the opening. The conductive layer 211 functions as a plug and is connected to the conductive layer 209. The conductive layer 211 may have, for example, a region that is in contact with the upper surface of the conductive layer 209. The conductive layer 211 can be made of the same material that can be used for the conductive layer 440 shown in Figure 20.

[0449] Each memory array 920[1] to 920[m] includes a plurality of memory cells 951. Each memory cell 951 has conductive layers 231, 232, 233, 234, 235, and 236 that function as plugs or wiring. The conductive layer 245b included in each memory cell 951 is connected to the conductive layer 211 via conductive layers 231 to 236. Thus, the conductive layer 245b included in each memory cell 951 is connected to the drive circuit 910 via conductive layers 207, 209, 211, and 231 to 236.

[0450] The conductive layer 231 is provided inside the opening in the insulating layer 216. The conductive layer 232 is provided inside the opening that reaches the conductive layer 231, and is provided inside the opening that reaches the conductive layer 231, and is provided inside the opening that reaches the conductive layer 231, and is provided inside the opening that reaches the conductive layer 231, and is provided inside the opening that reaches the conductive layer 232, and is provided inside the conductive layer 245b, and is provided inside the opening that reaches the conductive layer 233, and is provided inside the opening that reaches the conductive layer 233, and is provided inside the opening that reaches the conductive layer 233, and is provided inside the opening that reaches the conductive layer 233, and is provided inside the opening that reaches the conductive layer 234, and is provided inside the opening that reaches the conductive layer 235 insulating layer 470, and is provided inside the opening that reaches the conductive layer 212, and is provided inside the opening that reaches the conductive layer 235, and is provided inside the insulating layer 212, and is provided inside the opening that reaches the conductive layer 235, and is provided inside the insulating layer 212, and is provided inside the opening that reaches the conductive layer 235, and is provided inside the insulating layer 212, and is provided inside the insulating layer 212, and is provided inside the opening that reaches the conductive layer 235, and is provided inside the insulating layer 212, and is provided inside the insulating layer 212, and is provided inside the insulating layer 212, and is provided inside the insulating layer

[0451] The conductive layer 231 has the same material as the conductive layer 205 and can be formed using the same process. The conductive layers 232 and 236 can use the same materials as the conductive layer 211. The conductive layer 233 has the same material as the conductive layer 410 and can be formed using the same process. The conductive layer 234 has the same material as the conductive layer 440 and can be formed using the same process. The conductive layer 235 has the same material as the conductive layer 462 and can be formed using the same process.

[0452] As shown in Figure 22, conductive layers 231 to 236 are shared in adjacent memory cells 951. In addition, in adjacent memory cells 951, the configuration on the right and the configuration on the left are arranged symmetrically with respect to conductive layers 232, 234, and 236.

[0453] In the memory array 920 described above, memory arrays 920[1] to 920[m] can be stacked. By arranging the memory arrays 920[1] to 920[m] of the memory array 920 perpendicular to the substrate surface on which the drive circuit 910 is provided, the memory density of the memory cells 951 can be improved. Furthermore, the memory array 920 can be repeatedly manufactured in the perpendicular direction using the same manufacturing process. The semiconductor device 900 can reduce the manufacturing cost of the memory array 920.

[0454] Next, an example of a processing unit that can be equipped with the above-mentioned memory device and other semiconductor devices will be described.

[0455] Figure 23 shows a block diagram of the arithmetic unit 960. The arithmetic unit 960 shown in Figure 23 can be applied to a CPU, for example. The arithmetic unit 960 can also be applied to processors such as GPUs (Graphics Processing Units), TPUs (Tensor Processing Units), and NPUs (Neural Processing Units) that have a large number of processor cores (tens to hundreds) capable of parallel processing, more so than a CPU.

[0456] The arithmetic unit 960 shown in Figure 23 has an ALU 962 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 962c, an instruction decoder 963, an interrupt controller 964, a timing controller 965, a register 966, a register controller 967, a bus interface 968, a cache 969, and a cache interface 969i on a substrate 961. The substrate 961 can be a semiconductor substrate, an SOI substrate, a glass substrate, etc. It may also have a rewritable ROM and a ROM interface. In addition, the cache 969 and the cache interface 969i may be provided on a separate chip.

[0457] The cache 969 is connected to the main memory, which is located on a separate chip, via a cache interface 969i. The cache interface 969i has the function of supplying a portion of the data held in the main memory to the cache 969. The cache interface 969i also has the function of outputting a portion of the data held in the cache 969 to the ALU 962 or register 966, etc., via the bus interface 968.

[0458] As will be described later, a memory array 920 can be stacked on the arithmetic unit 960. The memory array 920 can be used as a cache. In this case, the cache interface 969i may have the function of supplying data held in the memory array 920 to the cache 969. In this case, it is preferable that a drive circuit 910 is included in part of the cache interface 969i.

[0459] Alternatively, the cache 969 can be omitted, and only the memory array 920 can be used as the cache.

[0460] The arithmetic unit 960 shown in Figure 23 is merely one example of a simplified configuration, and actual arithmetic units 960 have a wide variety of configurations depending on their application. For example, it is preferable to have a so-called multi-core configuration in which the configuration including the arithmetic unit 960 shown in Figure 23 is considered one core, and multiple such cores are included, with each core operating in parallel. The more cores there are, the higher the computational performance can be. While a larger number of cores is preferable, it is preferable to have, for example, two, preferably four, more preferably eight, even more preferably twelve, and even more preferably sixteen or more cores. Furthermore, in cases where very high computational performance is required, such as for server applications, it is preferable to have a multi-core configuration with 16 or more, preferably 32 or more, and even more preferably 64 or more cores. In addition, the number of bits that the arithmetic unit 960 can handle in its internal arithmetic circuitry, data bus, etc., can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.

[0461] Instructions input to the arithmetic unit 960 via the bus interface 968 are input to the instruction decoder 963, decoded, and then input to the ALU controller 962c, interrupt controller 964, register controller 967, and timing controller 965.

[0462] The ALU controller 962c, interrupt controller 964, register controller 967, and timing controller 965 perform various controls based on the decoded instructions. Specifically, the ALU controller 962c generates signals to control the operation of the ALU 962. The interrupt controller 964 processes interrupt requests from external input / output devices, peripheral circuits, etc., during program execution of the arithmetic unit 960, based on their priority, mask state, etc. The register controller 967 generates the address of register 966 and reads and writes to register 966 according to the state of the arithmetic unit 960.

[0463] Furthermore, the timing controller 965 generates signals that control the timing of the operation of the ALU 962, ALU controller 962c, instruction decoder 963, interrupt controller 964, and register controller 967. For example, the timing controller 965 includes an internal clock generation unit that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits mentioned above.

[0464] In the arithmetic unit 960 shown in Figure 23, the register controller 967 selects a data retention operation in register 966 according to instructions from ALU 962. That is, it selects whether to retain data in the memory cell of register 966 using a flip-flop or using a capacitive element. If data retention using a flip-flop is selected, power potential is supplied to the memory cell in register 966. If data retention using a capacitive element is selected, data is rewritten to the capacitive element, and the supply of power potential to the memory cell in register 966 can be stopped.

[0465] The memory array 920 and the arithmetic unit 960 can be installed on top of each other. Figures 24A and 24B show perspective views of the semiconductor device 970A. The semiconductor device 970A has a layer 930 on which memory arrays are provided on the arithmetic unit 960. The layer 930 is provided with memory arrays 920L1, 920L2, and 920L3. The arithmetic unit 960 and each memory array have overlapping regions. To make the configuration of the semiconductor device 970A easier to understand, Figure 24B shows the arithmetic unit 960 and layer 930 separately.

[0466] By stacking the layer 930 containing the memory array and the arithmetic unit 960, the connection distance between them can be shortened. Therefore, the communication speed between them can be increased. In addition, power consumption can be reduced due to the short connection distance.

[0467] As a method for stacking the layer 930 having the memory array and the arithmetic unit 960, one may use a method in which the layer 930 having the memory array is directly stacked on the arithmetic unit 960 (also called monolithic stacking), or one may use a method in which the arithmetic unit 960 and the layer 930 are formed on different substrates, the two substrates are bonded together, and they are connected using through-via or conductive film bonding technology (such as Cu-Cu bonding). The former does not require consideration of positional misalignment during bonding, so not only can the chip size be reduced, but manufacturing costs can also be reduced.

[0468] Here, the arithmetic unit 960 does not have a cache 969, and the memory arrays 920L1, 920L2, and 920L3 provided in layer 930 can each be used as caches. In this case, for example, memory array 920L1 can be used as an L1 cache (also called a level 1 cache), memory array 920L2 can be used as an L2 cache (also called a level 2 cache), and memory array 920L3 can be used as an L3 cache (also called a level 3 cache). Of the three memory arrays, memory array 920L3 has the largest capacity and the lowest access frequency. Also, memory array 920L1 has the smallest capacity and the highest access frequency.

[0469] Furthermore, when the cache 969 provided in the arithmetic unit 960 is used as the L1 cache, each memory array provided in layer 930 can be used as a lower-level cache or main memory, respectively. Main memory has a larger capacity than cache and is accessed less frequently.

[0470] Furthermore, as shown in Figure 24B, drive circuits 910L1, 910L2, and 910L3 are provided. Drive circuit 910L1 is connected to memory array 920L1 via connecting electrode 940L1. Similarly, drive circuit 910L2 is connected to memory array 920L2 via connecting electrode 940L2, and drive circuit 910L3 is connected to memory array 920L3 via connecting electrode 940L3.

[0471] Note that while this example shows three memory arrays functioning as a cache, it may also use one, two, or four or more arrays.

[0472] When the memory array 920L1 is used as a cache, the drive circuit 910L1 may function as part of the cache interface 969i, or the drive circuit 910L1 may be configured to be connected to the cache interface 969i. Similarly, the drive circuits 910L2 and 910L3 may also function as part of the cache interface 969i, or be configured to be connected to it.

[0473] Whether the memory array 920 functions as a cache or as main memory is determined by the control circuit 912 of each drive circuit 910. Based on signals supplied from the arithmetic unit 960, the control circuit 912 can make some of the multiple memory cells 950 of the semiconductor device 900 function as RAM.

[0474] The semiconductor device 900 can have some of its multiple memory cells 950 function as a cache and the other part function as main memory. In other words, the semiconductor device 900 can have both cache and main memory functions. A semiconductor device 900 according to one aspect of the present invention can function as a universal memory, for example.

[0475] Alternatively, a layer 930 having a single memory array 920 may be superimposed on the arithmetic unit 960. Figure 25A shows a perspective view of the semiconductor device 970B.

[0476] In the semiconductor device 970B, a single memory array 920 can be divided into multiple areas, each used for a different function. Figure 25A shows an example where area L1 is used as the L1 cache, area L2 as the L2 cache, and area L3 as the L3 cache.

[0477] Furthermore, in the semiconductor device 970B, the capacities of each of the regions L1 to L3 can be changed according to the situation. For example, if it is desired to increase the capacity of the L1 cache, this can be achieved by increasing the area of ​​region L1. By adopting such a configuration, the efficiency of arithmetic processing can be improved, and the processing speed can be increased.

[0478] Furthermore, multiple memory arrays may be stacked. Figure 25B shows a perspective view of the semiconductor device 970C.

[0479] The semiconductor device 970C has a layer 930L1 with a memory array 920L1, a layer 930L2 with a memory array 920L2 on top of it, and a layer 930L3 with a memory array 920L3 on top of that. The memory array 920L1, which is physically closest to the arithmetic unit 960, can be used as the upper cache, and the memory array 920L3, which is furthest away, can be used as the lower cache or main memory. By using this configuration, the capacity of each memory array can be increased, thereby improving processing power.

[0480] This embodiment can be combined with other embodiments as appropriate. Furthermore, if multiple configuration examples are shown within a single embodiment in this specification, these configuration examples can be combined as appropriate.

[0481] (Embodiment 4) In this embodiment, an example of the applicable range of a semiconductor device according to one aspect of the present invention will be described with reference to Figure 26. The memory device according to one aspect of the present invention uses an oxide transistor (hereinafter sometimes referred to as an OS transistor) and a capacitive element. Since the off-current of the OS transistor is extremely small, a memory device using an OS transistor has excellent retention characteristics and can function as a non-volatile memory.

[0482] In semiconductor devices such as computers, various types of memory devices are used depending on the application. Figure 26 shows a conceptual diagram illustrating the hierarchy of memory devices used in semiconductor devices. In Figure 26, the conceptual diagram illustrating the hierarchy of memory devices is shown as a triangle, where memory devices located in the upper layers of the triangle require faster operating speeds, and memory devices located in the lower layers of the triangle require larger storage capacity and higher recording density.

[0483] Figure 26 shows, from the top layer of the triangle upwards, the memory embedded as registers in the CPU, GPU, and NPU processing units, cache memory (sometimes simply referred to as cache; typically L1, L2, and L3 caches), main memory represented by DRAM, and storage memory represented by 3D NAND and Hard Disk (HDD: also called Hard Disk Drive).

[0484] Memory integrated as registers in arithmetic processing units such as CPUs, GPUs, and NPUs is used for temporary storage of calculation results and is therefore frequently accessed by the processing unit. Consequently, a fast operating speed is more important than a large storage capacity. Registers also have the function of holding configuration information for the processing unit.

[0485] Cache memory has the function of duplicating and storing a portion of the data held in DRAM. By duplicating frequently used data and storing it in cache memory, the speed of data access can be increased. Although the required storage capacity of cache memory is less than that of DRAM, it is required to operate at a faster speed than DRAM. Also, data that has been rewritten in cache memory is duplicated and supplied to DRAM.

[0486] A storage device according to one aspect of the present invention can be applied as DRAM.

[0487] Although Figure 26 only shows cache memory up to the L3 cache, the invention is not limited to this. For example, a storage device according to one embodiment of the present invention can be used as the lowest level of the cache, either the LLC (Last Level cache) or the FLC (Final Level cache).

[0488] DRAM has the function of storing programs, data, etc., read from 3D NAND.

[0489] 3D NAND has the function of storing data that needs to be preserved for a long time, as well as various programs used in computing devices (for example, models of artificial neural networks). Therefore, 3D NAND requires a large memory capacity and high recording density rather than a fast operating speed.

[0490] Hard disks offer high capacity and non-volatile properties. Alternatively, SSDs (Solid State Drives) can be used as a substitute for hard disks.

[0491] A memory device according to one aspect of the present invention can be configured monolithically with peripheral circuits by using OS transistors. Furthermore, monolithic stacking with peripheral circuits is also possible by using OS transistors. Therefore, it has advantages in terms of data access with peripheral circuits. Also, because it can be stacked with peripheral circuits, the integration density can be increased. Moreover, a memory device according to one aspect of the present invention can retain data for a long period of time by using OS transistors. Therefore, when used as DRAM, the refresh frequency can be reduced.

[0492] Furthermore, the memory device according to one aspect of the present invention can reduce leakage current by using an OS transistor. Therefore, for example, sufficient data retention can be achieved even if the capacitance value of the capacitive element is reduced. Thus, for example, by using the memory device according to one aspect of the present invention as a DRAM, the operating speed of the DRAM, such as the rewriting speed, may be increased.

[0493] Furthermore, the memory device according to one aspect of the present invention has a capacitive element containing a ferroelectric material, enabling long-term data retention. Therefore, when used as a DRAM, the refresh frequency can be reduced. In addition, the reliability of the memory device can be improved.

[0494] A storage device according to one aspect of the present invention can be used in the area of ​​Target 2 and the area of ​​Target 1 shown in Figure 26. In particular, it can be preferably used in the area of ​​Target 1.

[0495] As shown by the hatched areas in Figure 26, Target 1 includes the boundary region between the DRAM and 3D NAND (Target 1_1) and the boundary region between the DRAM and cache (L1, L2, L3) (Target 1_2). Examples of Target 1_2 include the LLC and FLC mentioned earlier.

[0496] By replacing the storage device according to one aspect of the present invention with DRAM, power consumption can be reduced. With this configuration, power consumption can be reduced to half or less, preferably one-tenth or less, more preferably one-hundredth or less, and even more preferably one-thousandth or less, compared to a configuration using DRAM. Therefore, the storage device according to one aspect of the present invention can be suitably used in Target 1.

[0497] Furthermore, the storage device according to one aspect of the present invention is capable of long-term data retention and also offers advantages in terms of data access. Therefore, the storage device according to one aspect of the present invention can be suitably used in Target 1_1, which is a region of Target 1 with a relatively low rewrite frequency. By applying the storage device according to one aspect of the present invention to Target 1_1, the reliability of the storage device can be improved. In addition, the integration density of the storage device may be increased. Furthermore, the power consumption of the storage device may be reduced.

[0498] Furthermore, since the storage device according to one aspect of the present invention has a high operating speed and advantages in terms of data access, it can be suitably used in Target 1_2, which has a higher rewrite frequency among Target 1. By applying the storage device according to one aspect of the present invention to Target 1_2, the computational efficiency of the storage device can be increased and power consumption can be reduced.

[0499] Another means of reducing power consumption is to stack memory devices such as DRAM and FeRAM (including semiconductor devices according to one aspect of the present invention) on top of arithmetic processing units such as CPUs, GPUs, and NPUs. A configuration in which arithmetic processing units and memory devices are stacked is called a monolithic stack. By using a monolithic stack configuration for arithmetic processing units and memory devices, the power consumption required for data access between the arithmetic processing units and memory devices can be significantly reduced. Therefore, by deploying information processing devices, including supercomputers (also called HPCs (High Performance Computers)), computers, and servers, that employ such a configuration worldwide, it is possible to mitigate global warming.

[0500] Thus, a memory device using an oxide semiconductor according to one aspect of the present invention can be applied to a wide range of memories, from memories integrated as registers in arithmetic processing units such as CPUs, GPUs, and NPUs, to memories in the boundary region between DRAM and 3D NAND.

[0501] This embodiment can be combined with other embodiments as appropriate. Furthermore, if multiple configuration examples are shown within a single embodiment in this specification, these configuration examples can be combined as appropriate.

[0502] (Embodiment 5) In this embodiment, an application example of a semiconductor device according to one aspect of the present invention will be described with reference to Figures 27A to 28E.

[0503] A semiconductor device according to one aspect of the present invention can be used, for example, in electronic components, large computers, space equipment, data centers (also referred to as DCs), and various electronic devices. By using a semiconductor device according to one aspect of the present invention, lower power consumption and higher performance can be achieved in electronic components, large computers, space equipment, data centers, and various electronic devices.

[0504] Examples of electronic devices include television sets, desktop or notebook computers, computer monitors, digital signage, large game machines such as pachinko machines, and other electronic devices with relatively large screens, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, personal digital assistants, and audio playback devices.

[0505] The electronic device of this embodiment may have sensors (including functions for detecting, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared radiation).

[0506] The electronic device of this embodiment can have a variety of functions. For example, it can have a function to display various information (still images, videos, or text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date, or time, a function to execute various software (programs), a wireless communication function, a function to read programs or data recorded on a recording medium, and so on.

[0507] [Electronic Components] Figure 27A shows a perspective view of a substrate (mounted substrate 989) on which electronic components 980 are mounted. The electronic component 980 shown in Figure 27A has a semiconductor device 981 inside a mold 984. Some details are omitted in Figure 27A to show the inside of the electronic component 980. The electronic component 980 has a land 985 on the outside of the mold 984. The land 985 is connected to an electrode pad 986, and the electrode pad 986 is connected to the semiconductor device 981 via a wire 987. The electronic component 980 is mounted on a printed circuit board 988, for example. Multiple such electronic components are combined and connected on the printed circuit board 988 to complete the mounted substrate 989.

[0508] Furthermore, the semiconductor device 981 has a drive circuit layer 982 and a storage layer 983. The storage layer 983 has a configuration in which multiple memory cell arrays are stacked. The configuration in which the drive circuit layer 982 and the storage layer 983 are stacked can be a monolithic stack configuration. In a monolithic stack configuration, the layers can be connected without using through-electrode technology such as TSV (Through Silicon Via) and bonding technology such as Cu-Cu direct bonding. By monolithically stacking the drive circuit layer 982 and the storage layer 983, for example, a so-called on-chip memory configuration can be achieved in which memory is directly formed on the processor. By using an on-chip memory configuration, it is possible to speed up the operation of the interface portion between the processor and the memory.

[0509] Furthermore, by using an on-chip memory configuration, the size of connection wiring can be reduced compared to technologies using through-hole electrodes such as TSVs, making it possible to increase the number of connection pins. Increasing the number of connection pins enables parallel operation, which in turn improves the memory bandwidth (also called memory bandwidth).

[0510] Furthermore, it is preferable to form the multiple memory cell arrays of the memory layer 983 using OS transistors and to stack these multiple memory cell arrays monolithically. By configuring the multiple memory cell arrays in a monolithic stack, it is possible to improve either or both of the memory bandwidth and / or the memory access latency. Bandwidth is the amount of data transferred per unit time, and access latency is the time from access to the start of data exchange. In the case of a configuration using Si transistors in the memory layer 983, it is difficult to create a monolithic stack configuration compared to OS transistors. Therefore, in a monolithic stack configuration, OS transistors can be said to have a superior structure compared to Si transistors.

[0511] The semiconductor device 981 may also be referred to as a die. In this specification, a die refers to a chip piece obtained in the semiconductor chip manufacturing process by forming a circuit pattern on, for example, a disc-shaped substrate (also called a wafer) and cutting it into cubes. Examples of semiconductor materials that can be used for dies include silicon (Si), silicon carbide (SiC), or gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) is sometimes called a silicon die.

[0512] Next, a perspective view of the electronic component 990 is shown in Figure 27B. The electronic component 990 is an example of a SiP (System in Package) or MCM (Multi-Chip Module). The electronic component 990 has an interposer 991 provided on a package substrate 992 (printed circuit board), and a semiconductor device 994 and a plurality of semiconductor devices 981 are provided on the interposer 991.

[0513] Electronic component 990 shows an example where the semiconductor device 981 is used as a high-bandwidth memory (HBM). Furthermore, the semiconductor device 994 can be used in integrated circuits such as CPUs, GPUs, or FPGAs (Field Programmable Gate Arrays).

[0514] The package substrate 992 can be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate. The interposer 991 can be, for example, a silicon interposer or a resin interposer.

[0515] The interposer 991 has multiple wirings and functions to connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 991 also has the function of connecting integrated circuits provided on the interposer 991 to electrodes provided on the package substrate 992. For these reasons, the interposer is sometimes called a "redistribution board" or "intermediate board". In addition, through electrodes may be provided on the interposer 991, and these through electrodes may be used to connect the integrated circuits and the package substrate 992. Furthermore, in silicon interposers, TSVs can also be used as through electrodes.

[0516] In HBMs, many connections are necessary to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted requires fine and high-density wiring. For this reason, it is preferable to use a silicon interposer for mounting the HBM.

[0517] Furthermore, in SiP and MCM using silicon interposers, reliability degradation due to differences in expansion coefficients between the integrated circuit and the interposer is less likely to occur. In addition, because silicon interposers have high surface flatness, connection failures between the integrated circuit and the silicon interposer are less likely to occur. In particular, in 2.5D packages (2.5-dimensional packaging) where multiple integrated circuits are arranged side by side on the interposer, it is preferable to use a silicon interposer.

[0518] On the other hand, when connecting multiple integrated circuits with different terminal pitches using silicon interposers and TSVs, space such as the width of the terminal pitch is required. Therefore, when attempting to reduce the size of the electronic component 990, the width of the terminal pitch becomes a problem, and it may become difficult to provide the many wires necessary to achieve a wide memory bandwidth. For this reason, as mentioned above, a monolithic stacked configuration using OS transistors is preferable. A composite structure combining a memory cell array stacked using TSVs and a monolithic stacked memory cell array may also be used.

[0519] Alternatively, a heat sink (heat dissipation plate) may be provided on top of the electronic component 990. If a heat sink is provided, it is preferable to align the heights of the integrated circuits provided on the interposer 991. For example, in the electronic component 990 shown in this embodiment, it is preferable to align the heights of the semiconductor device 981 and the semiconductor device 994.

[0520] To mount the electronic component 990 onto another substrate, electrodes 993 may be provided at the bottom of the package substrate 992. Figure 27B shows an example in which the electrodes 993 are formed with solder balls. By providing solder balls in a matrix at the bottom of the package substrate 992, BGA (Ball Grid Array) mounting can be achieved. Alternatively, the electrodes 993 may be formed with conductive pins. By providing conductive pins in a matrix at the bottom of the package substrate 992, PGA (Pin Grid Array) mounting can be achieved.

[0521] The electronic component 990 can be mounted on other boards using various mounting methods, not limited to BGA and PGA. Examples of mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).

[0522] [Large-scale computer] Next, Figure 28A shows a perspective view of the large-scale computer 5600. The large-scale computer 5600 shown in Figure 28A has multiple rack-mount type computers 5620 housed in rack 5610. The large-scale computer 5600 may also be called a supercomputer.

[0523] The computer 5620 can have the configuration shown in the perspective view in Figure 28B, for example. In Figure 28B, the computer 5620 has a motherboard 5630, which has multiple slots 5631 and multiple connection terminals. A PC card 5621 is inserted into a slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to the motherboard 5630.

[0524] The PC card 5621 shown in Figure 28C is an example of a processing board equipped with a CPU, GPU, storage device, etc. The PC card 5621 has a board 5622. The board 5622 also has connection terminals 5623, 5624, 5625, semiconductor device 5626, semiconductor device 5627, semiconductor device 5628, and connection terminal 5629. Although Figure 28C shows semiconductor devices other than semiconductor devices 5626, 5627, and 5628, you can refer to the descriptions of semiconductor devices 5626, 5627, and 5628 below for details on these semiconductor devices.

[0525] The connector 5629 has a shape that allows it to be inserted into the slot 5631 of the motherboard 5630, and functions as an interface for connecting the PC card 5621 and the motherboard 5630. Examples of standards for the connector 5629 include PCIe.

[0526] Terminals 5623, 5624, and 5625 can serve as interfaces for, for example, power supply and signal input to the PC card 5621. They can also serve as interfaces for, for example, outputting signals calculated by the PC card 5621. Examples of the standards for terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). When outputting video signals from terminals 5623, 5624, and 5625, examples of the standards include HDMI (registered trademark).

[0527] The semiconductor device 5626 has terminals (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be connected by inserting these terminals into sockets (not shown) provided on the board 5622.

[0528] The semiconductor device 5627 has multiple terminals, and the semiconductor device 5627 and the board 5622 can be connected by soldering these terminals to the wiring provided on the board 5622, for example, using a reflow soldering method. Examples of semiconductor devices 5627 include FPGAs, GPUs, CPUs, etc. For example, an electronic component 990 can be used as the semiconductor device 5627.

[0529] The semiconductor device 5628 has multiple terminals, and the semiconductor device 5628 and the board 5622 can be connected by soldering these terminals to the wiring provided on the board 5622, for example, using a reflow soldering method. Examples of the semiconductor device 5628 include a memory device. For example, an electronic component 990 can be used as the semiconductor device 5628.

[0530] The 5600 mainframe computer can also function as a parallel computer. By using the 5600 mainframe computer as a parallel computer, it is possible to perform large-scale calculations necessary for, for example, artificial intelligence training and inference.

[0531] [Space Equipment] A semiconductor device according to one aspect of the present invention can be suitably used in space equipment.

[0532] One embodiment of the present invention includes an OS transistor. Compared to Si transistors, OS transistors exhibit smaller fluctuations in electrical properties due to radiation exposure. In other words, they have high resistance to radiation, making them highly reliable and suitable for use in environments where radiation may be incident. For example, OS transistors are suitable for use in outer space. Specifically, OS transistors can be used in transistors constituting semiconductor devices installed in space shuttles, artificial satellites, or space probes. Examples of radiation include X-rays and neutrons. Outer space refers, for example, to an altitude of 100 km or higher, but outer space as described herein may include one or more of the thermosphere, mesosphere, and stratosphere.

[0533] Figure 28D shows an example of space equipment, specifically a satellite 6800. The satellite 6800 comprises a body 6801, solar panels 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. In Figure 28D, a planet 6804 is shown as an example in outer space.

[0534] Furthermore, although not shown in Figure 28D, a battery management system (also known as a BMS) or a battery control circuit may be provided with the secondary battery 6805. Using an OS transistor in the aforementioned battery management system or battery control circuit is preferable because it consumes little power and has high reliability even in outer space.

[0535] Furthermore, outer space is an environment with radiation levels more than 100 times higher than those on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, as well as particle radiation such as alpha rays, beta rays, neutrons, protons, heavy ions, and mesons.

[0536] When sunlight shines on the solar panel 6802, the power necessary for the satellite 6800 to operate is generated. However, if, for example, the solar panel is not exposed to sunlight, or if the amount of sunlight shining on the solar panel is low, the amount of power generated will decrease. Therefore, there is a possibility that the power necessary for the satellite 6800 to operate may not be generated. To operate the satellite 6800 even under conditions of low power generation, it is advisable to equip the satellite 6800 with a secondary battery 6805. Note that solar panels are sometimes called solar cell modules.

[0537] The artificial satellite 6800 can generate a signal. This signal is transmitted via antenna 6803, and can be received by, for example, a receiver on the ground or another artificial satellite. By receiving the signal transmitted by the artificial satellite 6800, the position of the receiver that received the signal can be measured. Thus, the artificial satellite 6800 can constitute a satellite positioning system.

[0538] Furthermore, the control device 6807 has the function of controlling the artificial satellite 6800. The control device 6807 is configured using, for example, one or more selected from a CPU, GPU, and memory device. It is preferable to use a semiconductor device including an OS transistor, which is one embodiment of the present invention, for the control device 6807.

[0539] Furthermore, the satellite 6800 can be configured to include sensors. For example, by configuring it to include a visible light sensor, the satellite 6800 can have the function of detecting sunlight reflected after hitting an object on the ground. Alternatively, by configuring it to include a thermal infrared sensor, the satellite 6800 can have the function of detecting thermal infrared radiation emitted from the Earth's surface. Thus, the satellite 6800 can function, for example, as an Earth observation satellite.

[0540] In this embodiment, an artificial satellite was used as an example of space equipment, but the invention is not limited thereto. For example, a semiconductor device according to one aspect of the present invention can be suitably used in space equipment such as spacecraft, space capsules, and space probes.

[0541] As explained above, OS transistors have superior advantages compared to Si transistors, such as the ability to achieve a wider memory bandwidth and higher radiation resistance.

[0542] [Data Center] One embodiment of the present invention is suitably used in storage systems applied to data centers and the like. Data centers are required to manage data over the long term, such as ensuring the immutability of data. Managing data over the long term requires the installation of storage and servers to store vast amounts of data, securing a stable power supply to hold the data, or securing cooling equipment required for data storage, etc., which necessitates the construction of larger buildings.

[0543] By using a semiconductor device according to one aspect of the present invention in a storage system applied to a data center, it is possible to reduce the power required for data retention and miniaturize the semiconductor device that holds the data. Therefore, it is possible to miniaturize the storage system, the power supply for data retention, and the cooling equipment. Consequently, it is possible to save space in the data center.

[0544] Furthermore, since the semiconductor device according to one aspect of the present invention has low power consumption, heat generation from the circuit can be reduced. Therefore, adverse effects on the circuit itself, peripheral circuits, and modules due to such heat generation can be reduced. In addition, by using the semiconductor device according to one aspect of the present invention, a data center that operates stably even in high-temperature environments can be realized. Therefore, the reliability of the data center can be improved.

[0545] Figure 28E shows a storage system applicable to a data center. The storage system 7010 shown in Figure 28E has multiple servers 7001sb as hosts 7001, and multiple storage devices 7003md as storage 7003. The host 7001 and storage 7003 are connected via a storage area network 7004 and a storage control circuit 7002.

[0546] Host 7001 corresponds to a computer that accesses data stored in storage 7003. The hosts 7001 may be connected to each other via a network.

[0547] Although storage 7003 uses flash memory to shorten data access speed, that is, the time required for data storage and output, this time is significantly longer than the time required by DRAM, which can be used as cache memory within the storage. In storage systems, to solve the problem of the long access speed of storage 7003, cache memory is usually provided inside the storage to shorten the time required for data storage and output.

[0548] The aforementioned cache memory is used internally by the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the cache memory within the storage control circuit 7002 and the storage 7003, and then output to the host 7001 or the storage 7003.

[0549] By using OS transistors as the transistors for storing the aforementioned cache memory data, and configuring them to maintain a potential corresponding to the data, the frequency of refresh can be reduced, thereby lowering power consumption. Furthermore, miniaturization is possible by stacking the memory cell arrays.

[0550] Furthermore, by applying a semiconductor device according to one aspect of the present invention to one or more selected from electronic components, large computers, space equipment, data centers, and electronic devices, power consumption can be reduced. Therefore, as energy demand is expected to increase with the performance or integration of semiconductor devices, using a semiconductor device according to one aspect of the present invention can reduce carbon dioxide (CO2) emissions. ２ It is also possible to reduce greenhouse gas emissions, such as those represented by [specific examples of greenhouse gas emissions]. Furthermore, because the semiconductor device according to one aspect of the present invention consumes little power, it is also effective as a measure against global warming.

[0551] This embodiment can be combined with other embodiments as appropriate. Furthermore, if multiple configuration examples are shown within a single embodiment in this specification, these configuration examples can be combined as appropriate.

[0552] 200: Transistor, 205: Conductive layer, 205_1: Conductive layer, 205_2: Conductive layer, 205_3: Conductive layer, 205_4: Conductive layer, 205_5: Conductive layer, 207: Conductive layer, 208: Insulating layer, 209: Conductive layer, 211: Conductive layer, 212: Insulating layer, 213: Insulating layer, 214: Insulating layer, 216: Insulating layer, 221: Insulating layer, 222: Insulating layer, 224: Insulating layer, 224_1: Insulating layer, 224_2: Insulating layer, 224f: Insulating film, 230: Semiconductor layer, 230_1: Semiconductor layer, 230_2: Semiconductor layer, 230f: Semiconductor film, 230i: Channel formation region, 230na: Low Resistive region, 230nb: Low resistance region, 230nc: Region, 231: Conductive layer, 232: Conductive layer, 233: Conductive layer, 234: Conductive layer, 235: Conductive layer, 236: Conductive layer, 237: Oxide layer, 241a: Insulating layer, 241b: Insulating layer, 243a: Opening, 243b: Opening, 245a: Conductive layer, 245b: Conductive layer, 245f: Conductive film, 250: Insulating layer, 250_1: Insulating layer, 250_2: Insulating layer, 250_3: Insulating layer, 250_4: Insulating layer, 250f: Insulating film, 260: Conductive layer, 260_1: Conductive layer, 260_2: Conductive layer, 260f: Conductive film, 271: Impurity source Element, 275: insulating layer, 280: insulating layer, 282: insulating layer, 283: insulating layer, 285: insulating layer, 288: recess, 289: opening, 310: transistor, 311: substrate, 313: semiconductor region, 314a: low resistance region, 314b: low resistance region, 315: insulating layer, 316: conductive layer, 318: element isolation layer, 320: insulating layer, 322: insulating layer, 324: insulating layer, 326: insulating layer, 328: conductive layer, 330: conductive layer, 410: conductive layer, 412: conductive layer, 420: conductive layer, 430: insulating layer, 440: conductive layer, 450: insulating layer, 462: conductive layer, 470: insulating layer, 487 : insulating layer, 488: insulating layer, 900: semiconductor device, 910: drive circuit, 911: peripheral circuit, 912: control circuit, 915: peripheral circuit, 920[1]: memory array, 920[2]: memory array, 920[m]: memory array, 920: memory array, 923: row driver, 924: column driver, 925: input circuit, 926: output circuit, 927: sense amplifier, 928: voltage generation circuit, 930: layer, 931: PSW, 932: PSW, 941: row decoder, 942: column decoder, 950: memory cell, 951: memory cell, 952: memory cell,953: Memory cell, 954: Memory cell, 955: Memory cell, 956: Memory cell, 957: Memory cell, 960: Arithmetic unit, 961: Substrate, 962: ALU, 962c: ALU controller, 963: Instruct...

Claims

It comprises a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a first insulating layer, and a second insulating layer. The first insulating layer has a region that is in contact with the upper surface of the semiconductor layer, The first insulating layer has a first opening, a second opening, and a third opening, each having a region that overlaps with the semiconductor layer. The first opening has a region located between the second opening and the third opening, The second insulating layer is provided inside the first opening such that it has a region in contact with the semiconductor layer. The first conductive layer is provided on the second insulating layer such that it has a region located inside the first opening. The second conductive layer is provided inside the second opening such that it has a region in contact with the upper surface of the semiconductor layer. The third conductive layer is provided inside the third opening such that it has a region in contact with the upper surface of the semiconductor layer. The semiconductor layer has a first region in contact with the second conductive layer, a second region in contact with the third conductive layer, and a third region overlapping with the first conductive layer. The concentration of the first element in the first region is higher than the concentration of the first element in the second conductive layer and the concentration of the first element in the third region. The concentration of the first element in the second region is higher than the concentration of the first element in the third conductive layer and the concentration of the first element in the third region. The semiconductor layer has indium oxide, A semiconductor device wherein the first element is one or more of boron, phosphorus, aluminum, magnesium, and silicon. 　 In claim 1, The first element is boron in the semiconductor device. 　 In claim 1 or claim 2, The first region and the second region each have a concentration of the first element of 1 × 10⁻⁶ １９ cm −３ A semiconductor device having a region greater than or equal to the above. 　 In claim 3, The third region has a concentration of the first element of 1 × 10⁻⁶ １８ cm −３ A semiconductor device having the following region. 　 In claim 1 or claim 2, A semiconductor device in which the concentration of the first element between the first region and the third region is less than the concentration of the first element in the first region and higher than the concentration of the first element in the third region. 　 A first step of forming a semiconductor layer and a first insulating layer having a region in contact with the upper surface of the semiconductor layer, A second step involves processing the first insulating layer to form a first opening in the first insulating layer that reaches the semiconductor layer, A third step of forming a second insulating layer and a first conductive layer on the second insulating layer such that it has a region located inside the first opening, A fourth step involves processing the first insulating layer to form a second opening and a third opening in the first insulating layer that reach the semiconductor layer and face each other across the first opening, A fifth step of supplying the first element to a first region overlapping with the second opening of the semiconductor layer and a second region overlapping with the third opening, A method for manufacturing a semiconductor device, comprising a sixth step of forming a second conductive layer in contact with the first region, and a third conductive layer in contact with the second region. 　 In claim 6, A method for manufacturing a semiconductor device, wherein the first element is one or more of boron, phosphorus, aluminum, magnesium, and silicon. 　 In claim 6, The method for manufacturing a semiconductor device involves supplying the first element using an ion implantation method or an ion doping method. 　 In any one of claims 6 to 8, A method for manufacturing a semiconductor device, wherein in the first step, the semiconductor layer is formed to have indium oxide.

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