Power conversion device

Abstract

A converter cell (10) included in a power conversion device comprises a cell control unit (15), a first switching circuit (21), and a second switching circuit (22). The first switching circuit (21) comprises a first semiconductor device (31), a second semiconductor device (32), and a first energy storage element (EP). The second switching circuit (22) comprises a third semiconductor device (33), a fourth semiconductor device (34), and a second energy storage element (EN). The converter cell (10) includes first to fourth gate control units (91 to 94). If a short-circuit current flowing through a semiconductor device to be driven is detected, one gate control unit of the first to fourth gate control units (91 to 94) controls the driven semiconductor device to be set to an OFF state and transmits abnormality detection information. If the abnormality detection information is received, the cell control unit (15) transmits, to the first to fourth gate control units (91 to 94), a control signal for controlling each driven semiconductor device to be set to an OFF state.

Description

Power conversion device

[0001] The present disclosure relates to a power conversion device.

[0002] In recent years, a modular multilevel converter (MMC: Modular Multilevel Converter) is known as a high-voltage and large-capacity power conversion device applied to high-voltage systems such as power grids. The MMC is composed of arms in which converter cells are cascade-connected. The converter cell includes a plurality of semiconductor switches and capacitors, and outputs the voltage across the capacitor or zero voltage by turning on and off the semiconductor switches. In addition, there is known a power conversion device that enables continuous operation by short-circuiting the converter cell using a bypass element when an abnormality occurs in the converter cell.

[0003] For example, the power conversion device according to Japanese Patent No. 5889498 (Patent Document 1) is configured to turn on semiconductor elements selected to continuously form a current path that does not include a bypass element among a plurality of semiconductor elements during a period until a closed circuit of the bypass element is established when an abnormality of the converter cell is detected.

[0004] Japanese Patent No. 5889498

[0005] In Patent Document 1, when an abnormality occurs in the converter cell, it is considered to prevent damage to the bypass element by suppressing the overcurrent flowing through the bypass element along with the closed-circuit operation of the bypass element. The converter cell according to Patent Document 1 is composed of a half-bridge circuit or a full-bridge circuit.

[0006] On the other hand, in a converter cell having a configuration in which two half-bridge circuits are connected in series, the voltage applied to the entire converter cell can be divided by the two half-bridge circuits, so the voltage applied to each half-bridge circuit can be reduced. In the converter cell having such a configuration, a circuit short circuit may occur during an abnormality. Therefore, it is necessary to protect the semiconductor elements included in the converter cell even when such a circuit short circuit occurs. However, Patent Document 1 does not teach or suggest a solution means for realizing such protection.

[0007] One objective of this disclosure is to provide a power conversion device capable of protecting semiconductor elements contained in a converter cell when a malfunction occurs in a converter cell composed of two half-bridge circuits connected in series.

[0008] According to one embodiment, a power converter is provided comprising a plurality of converter cells connected in series. Each of the plurality of converter cells includes a cell control unit, a first switching circuit and a second switching circuit connected in series, and a first input / output terminal and a second input / output terminal. The first switching circuit includes a first semiconductor element, a second semiconductor element, and a first energy storage element connected in parallel to a series assembly including the first and second semiconductor elements. The first input / output terminal is connected to the connection point between the negative terminal of the first semiconductor element and the positive terminal of the second semiconductor element. The second switching circuit includes a third semiconductor element, a fourth semiconductor element, and a second energy storage element connected in parallel to a series assembly including the third and fourth semiconductor elements. The second input / output terminal is connected to the connection point between the negative terminal of the third semiconductor element and the positive terminal of the fourth semiconductor element. Each of the multiple converter cells further includes a first gate control unit for driving a first semiconductor element, a second gate control unit for driving a second semiconductor element, a third gate control unit for driving a third semiconductor element, and a fourth gate control unit for driving a fourth semiconductor element. When one of the first to fourth gate control units detects a short-circuit current flowing through a semiconductor element to be driven by one of the first to fourth semiconductor elements, it controls the driven semiconductor element to an off state and transmits abnormality detection information to the cell control unit. When the cell control unit receives abnormality detection information, it transmits a control signal to each of the first to fourth gate control units to control the semiconductor element to be driven by that gate control unit to an off state.

[0009] According to this disclosure, it is possible to protect the semiconductor elements contained in a converter cell when an abnormality occurs in a converter cell composed of two half-bridge circuits connected in series.

[0010] This is a schematic diagram of the power converter. This is a diagram showing an example of the converter cell configuration. This is a diagram showing an example of a short-circuit current path. This is a diagram showing another example of a short-circuit current path. This is a diagram showing an example of a short-circuit current path that may occur when a bypass element is closed. This is a diagram showing another example of a short-circuit current path that may occur when a bypass element is closed. This is a diagram illustrating an example of a short-circuit current detection method. This is a diagram illustrating another example of a short-circuit current detection method. This is a diagram illustrating yet another example of a short-circuit current detection method. This is a flowchart illustrating an example of a gate control unit processing procedure. This is a flowchart illustrating another example of a gate control unit processing procedure. This is a flowchart illustrating an example of a cell control unit processing procedure.

[0011] This embodiment will be described below with reference to the drawings. In the following description, identical parts are denoted by the same reference numerals. Their names and functions are also the same. Therefore, detailed descriptions of them will not be repeated.

[0012] <Configuration of the Power Converter> Figure 1 is a schematic diagram of the power converter. Referring to Figure 1, the power converter 100 includes a power converter 110 which includes a plurality of converter cells 10 connected in series with each other, and a control device 120 for controlling the power converter 110. A “converter cell” is also called a “submodule” or “unit converter”. The power converter 110 is composed of modular multilevel converters. Typically, the power converter 110 performs power conversion between a DC circuit 130 and an AC circuit 150.

[0013] The power converter 110 includes a plurality of leg circuits 40u, 40v, and 40w (hereinafter also collectively referred to as "leg circuits 40") connected in parallel to each other between the positive DC terminal (i.e., the high-potential DC terminal) Np and the negative DC terminal (i.e., the low-potential DC terminal) Nn.

[0014] The leg circuits 40 are provided for each of the multiple phases that make up the alternating current. The leg circuits 40 are connected between the DC circuit 130 and the AC circuit 150 and perform power conversion between the two circuits. Figure 1 shows the case where the AC circuit 150 is a three-phase AC system, and three leg circuits 40u, 40v, and 40w are provided corresponding to the U phase, V phase, and W phase, respectively. The AC terminals Nu, Nv, and Nw provided on the leg circuits 40u, 40v, and 40w, respectively, are connected to the AC circuit 150 via the transformer 140. The AC circuit 150 is, for example, an AC power system including an AC power source.

[0015] The positive DC terminal Np and negative DC terminal Nn, which are commonly connected to each leg circuit 40, are connected to the DC circuit 130. The DC circuit 130 is, for example, the DC terminal of a DC power system including a DC power transmission network or other power conversion device.

[0016] The leg circuit 40u includes a positive arm from the positive DC terminal Np to the AC terminal Nu, and a negative arm from the negative DC terminal Nn to the AC terminal Nu. The AC terminal Nu, which is the connection point between the positive and negative arms, is connected to the transformer 140. Leg circuits 40v and 40w have a similar configuration.

[0017] The positive arm includes a plurality of cascaded transducer cells 10 and a reactor 14P. The plurality of transducer cells 10 and the reactor 14P are connected in series with each other. The negative arm includes a plurality of cascaded transducer cells 10 and a reactor 14N. The plurality of transducer cells 10 and the reactor 14N are connected in series with each other.

[0018] The reactor 14P may be inserted at any position on the positive arm, and the reactor 14N may be inserted at any position on the negative arm. There may be multiple reactors 14P and 14N. Reactors 14P and 14N may be magnetically coupled to form a single reactor. Only reactor 14P or only reactor 14N may be provided. Alternatively, instead of providing reactors, a configuration may be used in which parasitic inductance, such as wiring inductance, serves as a substitute for the reactors.

[0019] The control device 120 controls the power converter 110 based on detection signals detected by various electrical quantity detectors (not shown) (for example, an AC voltage detector, an AC current detector, a DC voltage detector, an arm current detector, etc.). The control device 120 may be configured by a dedicated circuit, or part or all of it may be configured by an FPGA (Field Programmable Gate Array), ASIC (Application Specific Integrated Circuit), microprocessor, etc.

[0020] <Configuration of the converter cell> Figure 2 shows an example of the configuration of a converter cell. Referring to Figure 2, the converter cell 10 includes a cell control unit 15, gate control units 91 to 94, a series-connected switching circuit 21 and a switching circuit 22, a bypass element 25, a high-potential input / output terminal Po, and a low-potential input / output terminal No.

[0021] The switching circuits 21 and 22 are composed of half-bridge circuits. Specifically, the switching circuit 21 includes a semiconductor element 31, a semiconductor element 32, and a capacitor EP as an energy storage element.

[0022] The semiconductor element 31 includes a switching element 31s and a diode 31d. The diode 31d is connected in antiparallel (i.e., in parallel and in the reverse bias direction) to the switching element 31s. The semiconductor element 32 includes a switching element 32s and a diode 32d. The diode 32d is connected in antiparallel to the switching element 32s. The switching element 31s may also be configured to include the diode 31d.

[0023] The switching circuit 22 includes a semiconductor element 33, a semiconductor element 34, and a capacitor EN as an energy storage element. The semiconductor element 33 includes a switching element 33s and a diode 33d. The diode 33d is connected in antiparallel to the switching element 33s. The semiconductor element 34 includes a switching element 34s and a diode 34d. The diode 34d is connected in antiparallel to the switching element 34s.

[0024] The switching elements 31s, 32s, 33s, and 34s are composed of, for example, IGBTs (Insulated Gate Bipolar Transistors), GCTs (Gate Commutated Turn-off Thyristors), and MOSFETs (Metal Oxide Semiconductor Field-Effect Transistors).

[0025] Capacitor EP is connected in parallel to a series array containing semiconductor elements 31 and 32, and maintains a DC voltage. An input / output terminal Po is connected to the connection point between the negative terminal of semiconductor element 31 and the positive terminal of semiconductor element 32. The positive terminal of capacitor EP is connected to the positive terminal of semiconductor element 31, and the negative terminal of capacitor EP is connected to the negative terminal of semiconductor element 32.

[0026] Capacitor EN is connected in parallel to the series assembly containing semiconductor elements 33 and 34. Input / output terminal No. is connected to the connection point between the negative terminal of semiconductor element 33 and the positive terminal of semiconductor element 34. The positive terminal of capacitor EN is connected to the positive terminal of semiconductor element 33, and the negative terminal of capacitor EN is connected to the negative terminal of semiconductor element 34.

[0027] The bypass element 25 is connected between the input / output terminal Po and the input / output terminal No. When the bypass element 25 is closed (i.e., turned on), the converter cell 10 is bypassed. For example, the bypass element 25 is used to bypass the converter cell 10 when any of its elements (e.g., semiconductor elements 31-34, etc.) fails. This allows the power converter 110 to continue operating by utilizing the other converter cells 10 even if any of the converter cells 10 fail.

[0028] The gate control units 91 to 94 are provided in accordance with the semiconductor elements 31 to 34, respectively. Therefore, the targets of the gate control units 91 to 94 are the semiconductor elements 31 to 34, respectively.

[0029] The gate control unit 91 includes a gate drive circuit for driving the semiconductor element 31 and a detection circuit for detecting abnormal current (i.e., overcurrent) flowing through the semiconductor element 31. The gate control unit 91 is connected to the semiconductor element 31 via control lines 91a and 91b. Specifically, the gate control unit 91 drives and controls the semiconductor element 31 via control line 91a and receives a detection signal for the current flowing through the semiconductor element 31 via control line 91b.

[0030] Similarly, the gate control unit 92 drives and controls the semiconductor element 32 via control line 92a and receives a detection signal for the current flowing through the semiconductor element 32 via control line 92b. The gate control unit 93 drives and controls the semiconductor element 33 via control line 93a and receives a detection signal for the current flowing through the semiconductor element 33 via control line 93b. The gate control unit 94 drives and controls the semiconductor element 34 via control line 94a and receives a detection signal for the current flowing through the semiconductor element 34 via control line 94b.

[0031] The cell control unit 15 controls the operation of the gate control units 91 to 94. During steady-state operation (for example, power conversion operation when no abnormality occurs in the semiconductor elements 31 to 34 included in the switching circuits 21 and 22), the cell control unit 15 transmits signals to the gate control units 91 to 94 to control the switching elements 31s to 34s to an ON state or an OFF state. The gate control units 91 to 94 output voltage pulses to turn the switching elements 31s to 34s ON or OFF according to these signals. When the switching elements 31s to 34s are controlled to an ON or OFF state, a zero voltage or a positive voltage is output between the input / output terminals Po and No. The operation of the cell control unit 15 and the gate control units 91 to 94 when an abnormality occurs in the semiconductor elements 31 to 34 will be described later.

[0032] The cell control unit 15 and gate control units 91-94 are implemented by a processing circuit. For example, the processing circuit is composed of an FPGA, ASIC, or a combination thereof.

[0033] In the converter cell 10 shown in Figure 2, two switching circuits 21 and 22 are connected in series, thus reducing the voltage applied to each switching circuit 21 and 22. Therefore, this configuration of the converter cell 10 is particularly useful when the voltage applied to the converter cell 10 becomes high due to the miniaturization and high density of the MMC.

[0034] <Operation in the event of a switching circuit abnormality> When the cell control unit 15 detects an abnormality in any of the converter cells 10 (for example, a failure of a semiconductor element, an abnormality in the control power supply used in the gate drive circuit of the semiconductor element, an abnormal current flowing through the semiconductor element, etc.), it transmits information indicating the abnormality of the converter cell 10 to the control device 120, which is higher level than the cell control unit 15. The control device 120 determines whether the abnormality of the converter cell 10 is correct. If the control device 120 determines that the converter cell 10 is abnormal (i.e., the abnormality of the converter cell 10 is correct), it transmits an instruction to the cell control unit 15 to close the bypass element 25 of the converter cell 10. The cell control unit 15 closes the bypass element 25 according to the instruction. As a result, the converter cell 10 is bypassed.

[0035] If the number of converter cells 10 is designed to be redundant so that operation equivalent to steady-state operation is performed, then even if one of the converter cells 10 fails, the power converter 110 can continue to perform power conversion operation by bypassing the failed converter cell 10. However, the following problems may occur.

[0036] Figure 3 shows an example of a short-circuit current path. Referring to Figure 3, we assume that a semiconductor element 31 constituting the upper arm of the switching circuit 21 becomes short-circuited due to a failure or control abnormality in the semiconductor element 31. When semiconductor element 32 is turned on while semiconductor element 31 is short-circuited, semiconductor elements 31 and 32 become short-circuited, the energy charge stored in capacitor EP is discharged, and a short-circuit current (i.e., overcurrent) flows through the path R1 of capacitor EP, semiconductor element 31, and semiconductor element 32.

[0037] Furthermore, if the semiconductor element 31 is turned on when the semiconductor element 31 is short-circuited due to a failure or control abnormality of the semiconductor element 32 constituting the lower arm of the switching circuit 21, a short-circuit current will flow through path R1.

[0038] Figure 4 shows another example of a short-circuit current path. Referring to Figure 4, we assume a case where a semiconductor element 33, which constitutes the upper arm of the switching circuit 22, becomes short-circuited due to a failure or control abnormality in the semiconductor element 33. When semiconductor element 34 is turned on while semiconductor element 33 is short-circuited, semiconductor elements 33 and 34 become short-circuited, the energy charge stored in capacitor EN is discharged, and a short-circuit current (i.e., overcurrent) flows through the path R2 of capacitor EN, semiconductor element 33, and semiconductor element 34.

[0039] Furthermore, if a semiconductor element 33 is turned on when a semiconductor element 34, which constitutes the lower arm of the switching circuit 22, malfunctions or a control abnormality occurs and the semiconductor element 34 becomes short-circuited, a short-circuit current will flow through path R2. Hereinafter, the short circuits shown in paths R1 and R2 will also be referred to as "local short circuits".

[0040] If a short-circuit current cannot be immediately interrupted, the power module forming the semiconductor elements 31-34, the connecting busbar, and surrounding electronic components may be scattered, and radiated and conducted noise may be generated when these explode. In this case, the cell control unit 15, the gate control units 91-94, and the bypass element 25 will fail or malfunction. As a result, if the converter cell 10 cannot be properly bypassed, the power converter 110 will be unable to continuously perform power conversion operations. Therefore, when a short-circuit current occurs, it is necessary to immediately detect the short-circuit current and interrupt (i.e., control the semiconductor elements 31-34 to the off state). The state in which the semiconductor elements 31-34 are controlled (fixed) to the off state is also called the gate block state.

[0041] Hereinafter, a control procedure for controlling the semiconductor elements 31 to 34 (specifically, the switching elements 31s to 34s) to an off state when a local short circuit occurs will be described. As an example, the case where an abnormality occurs in the semiconductor element 31 will be described.

[0042] Suppose that the gate control unit 91 detects an abnormality related to a short circuit failure of the semiconductor element 31 (hereinafter also referred to as a "short circuit related abnormality"). An example of a short circuit related abnormality is an abnormality in which the resistance value between the collector and emitter (or drain-source in the case of a MOSFET) of the semiconductor element 31 decreases due to deterioration or accidental failure of the semiconductor element 31, and the capacitor EP voltage cannot be maintained. Another example is an operation abnormality of the gate drive circuit included in the gate control unit 91. This is an abnormality in which an on signal is input at the timing when an off signal should be input to the semiconductor element 31, and the semiconductor element 31 is unintentionally turned on. When these abnormalities occur, the resistance value between the collector and emitter (or drain-source in the case of a MOSFET) of the semiconductor element 31 becomes unintentionally decreased.

[0043] When the semiconductor element 32 in a healthy state is turned on by the gate control unit 92 in a state where a short circuit related abnormality has occurred in the semiconductor element 31, as shown in FIG. 3, the energy charged in the capacitor EP is discharged, causing a short circuit current to flow through the path R1 and a local short circuit to occur.

[0044] At this time, the voltage of the capacitor EP is divided by the semiconductor element 31 and the semiconductor element 32. That is, with a high voltage divided and applied to the semiconductor element 31 (or the semiconductor element 32), a short circuit current flows, causing energy to concentrate on the semiconductor element 31 (or the semiconductor element 32), and at least one of the semiconductor element 31 and the semiconductor element 32 may be destroyed. Hereinafter, this destruction mode is also referred to as "local short circuit destruction".

[0045] To prevent such local short-circuit breakdown, the gate control unit 91 receives information for detecting a short-circuit current (e.g., a current detection signal) from the control line 91b, and when it determines that the semiconductor element 31 is abnormal (i.e., a short-circuit current is flowing through the semiconductor element 31), regardless of the signal received from the cell control unit 15, it immediately controls the semiconductor element 31 (specifically, the switching element 31s) to the off state by its own judgment.

[0046] Further, when the gate control unit 91 detects an abnormality in the semiconductor element 31, in addition to the above control for turning off the semiconductor element 31, it transmits abnormality detection information to the cell control unit 15. When the cell control unit 15 receives the abnormality detection information, it transmits an off control signal for controlling the semiconductor elements 31 to 34 to the off state to the gate control units 91 to 94. When the gate control units 91 to 94 receive the off control signal from the cell control unit 15, they control the semiconductor elements 31 to 34 to the off state.

[0047] Here, the reason why the cell control unit 15 transmits an off control signal to the gate control units 91 to 94 when it receives abnormality detection information indicating an abnormality in the semiconductor element 31 from the gate control unit 91 will be explained.

[0048] First, the gate control unit 91 is configured to control the semiconductor element 31 to the off state by its own judgment when it detects an abnormality in the semiconductor element 31. However, in preparation for unforeseen circumstances, the cell control unit 15 transmits an off control signal to the gate control unit 91.

[0049] Also, when the gate control unit 91 is malfunctioning, there is a possibility that the semiconductor element 31 cannot be controlled to the off state even if an abnormality is detected by the gate control unit 91. Therefore, assuming that the gate control unit 91 is malfunctioning, the cell control unit 15 transmits an off control signal to the gate control unit 92. The gate control unit 92 controls the semiconductor element 32 (specifically, the switching element 32s) to the off state according to the received off control signal.

[0050] Furthermore, if a local short circuit occurs in the switching circuit 21, the switching circuit 22 may malfunction due to the effects of the local short circuit, potentially causing a local short circuit in path R2. As a result, if the bypass element 25 does not operate properly and the converter cell 10 cannot be bypassed, the power converter 110 will be unable to continuously perform power conversion operations. Therefore, the cell control unit 15 transmits an off control signal to the gate control units 93 and 94. The gate control units 93 and 94 control the semiconductor elements 33 and 34 of the switching circuit 22 (specifically, the switching elements 33s and 34s) to the off state according to the received off control signal.

[0051] If a local short circuit occurs in the switching circuit 21, a short-circuit current will flow through semiconductor elements 31 and 32. In this case, the gate control unit 91 uses the current detection signal received via the control line 91b to determine if the current flowing through semiconductor element 31 is abnormal, and the gate control unit 92 uses the current detection signal received via the control line 91b to determine if the current flowing through semiconductor element 32 is abnormal.

[0052] Here, the same current flows through semiconductor elements 31 and 32, but there is a strict difference between the current detection signal received by the gate control unit 91 and the current detection signal received by the gate control unit 92. Therefore, a time difference occurs between the timing T1 at which the gate control unit 91 determines that semiconductor element 31 is abnormal and the timing T2 at which the gate control unit 92 determines that semiconductor element 32 is abnormal.

[0053] For example, if timing T1 is earlier than timing T2, the gate control unit 91 first determines that the semiconductor element 31 is abnormal, and controls the semiconductor element 31 to the off state, while abnormality detection information is transmitted to the cell control unit 15. Then, while the cell control unit 15 is transmitting the off control signal to the gate control unit 92, the gate control unit 92 determines that the semiconductor element 32 is abnormal. In this case, the gate control unit 92 controls the semiconductor element 32 to the off state at the earlier of the timing of receiving the off control signal from the cell control unit 15 and the timing of its own determination.

[0054] The above describes a typical case where the gate control unit 91 detects an abnormality in the semiconductor element 31, but similar control is performed when the gate control unit 92 detects an abnormality in the semiconductor element 32. For example, when the gate control unit 92 detects a short-circuit current flowing through the semiconductor element 32, it controls the semiconductor element 32 to an off state based on its own judgment and transmits abnormality detection information to the cell control unit 15. When the cell control unit 15 receives the abnormality detection information, it transmits an off control signal to the gate control units 91 to 94.

[0055] Similar control is performed when an abnormality in the semiconductor elements 33 and 34 is detected by the gate control units 93 and 94, respectively. For example, when the gate control unit 93 detects a short-circuit current flowing through the semiconductor element 33, it controls the semiconductor element 33 to the OFF state based on its own judgment and transmits abnormality detection information to the cell control unit 15. When the gate control unit 94 detects a short-circuit current flowing through the semiconductor element 34, it controls the semiconductor element 34 to the OFF state based on its own judgment and transmits abnormality detection information to the cell control unit 15. When the cell control unit 15 receives the abnormality detection information, it transmits an OFF control signal to the gate control units 91 to 94.

[0056] Furthermore, each gate control unit 91 to 94 controls the semiconductor element to be driven to the off state at the earlier of the timing of receiving the off control signal and the timing of its own determination. Specifically, if each gate control unit 91 to 94 detects a short-circuit current flowing through the semiconductor element to be driven before receiving the off control signal (i.e., before the timing of receiving the off control signal), it controls the semiconductor element to be driven to the off state based on its own determination. On the other hand, if each gate control unit 91 to 94 receives the off control signal before detecting a short-circuit current flowing through the semiconductor element to be driven (i.e., before the timing of its own detection of the short-circuit current), it controls the semiconductor element to be driven to the off state based on the reception of the off control signal.

[0057] Therefore, if one of the gate control units 91 to 94 (also referred to as "gate control unit X" for convenience) detects a short-circuit current flowing through a semiconductor element among the semiconductor elements 31 to 34 that is the target of gate control unit X, it controls the target semiconductor element to an off state and transmits abnormality detection information to the cell control unit 15. When the cell control unit 15 receives the abnormality detection information, it transmits a control signal to each of the gate control units 91 to 94 to control the semiconductor element that the gate control unit is the target of to an off state.

[0058] Furthermore, when each of the gate control units 91 to 94 receives an off control signal, if the semiconductor element to be driven by that gate control unit is not controlled to be in the off state, it controls the semiconductor element to be driven to be in the off state.

[0059] The above control procedure allows the short-circuit current flowing through paths R1 and R2 to be interrupted as quickly as possible.

[0060] <Operation when bypass element is incorrectly switched on> The above describes a configuration in which, when a short-circuit-related abnormality occurs in semiconductor elements 31 to 34, the semiconductor elements 31 to 34 are controlled to an off state based on the self-determination of the gate control units 91 to 94 or the off control signal from the cell control unit 15. Here, we will describe a configuration to prevent damage to semiconductor elements 31 to 34 when the semiconductor elements 31 to 34 are in a normal state, but the bypass element 25 is incorrectly switched on (i.e., closed).

[0061] Figure 5 shows an example of a short-circuit current path that may occur when the bypass element is closed. Referring to Figure 5, when the bypass element 25 malfunctions (i.e., closes) due to the influence of noise or the like, and the semiconductor element 31 is controlled to be ON, the energy charged in the capacitor EP is discharged, and a short-circuit current (i.e., overcurrent) flows through the path R3 passing through the capacitor EP, semiconductor element 31, bypass element 25, and semiconductor element 33.

[0062] Figure 6 shows another example of a short-circuit current path that may occur when the bypass element is closed. Referring to Figure 6, when the semiconductor element 34 is controlled to be ON when the bypass element 25 malfunctions due to noise or other influences, the energy charged in the capacitor EN is discharged, and a short-circuit current flows through the path R4 passing through the capacitor EN, semiconductor element 32, bypass element 25, and semiconductor element 34.

[0063] The bypass element 25 has a large inductance component. Therefore, the inductance components of paths R3 and R4 are larger than those of paths R1 and R2 in the local short circuit described above. Consequently, the short-circuit current is limited by the inductance component of the bypass element 25, and the rate of current rise per unit time is lower compared to the local short circuit. Hereafter, a short circuit as shown in paths R3 and R4 will also be referred to as a "bypass element short circuit".

[0064] If a bypass element short circuit occurs, a current of several tens of kA to several hundred kA will flow through the bypass element 25, which may cause mechanical damage to the bypass element 25, such as melting. In this case, it may become impossible to properly bypass the converter cell 10.

[0065] When a bypass element short circuit occurs in path R3 as shown in Figure 5, an overcurrent flows while the voltage of capacitor EP is applied to the semiconductor element 31, which may cause energy destruction of the semiconductor element 31. In this case, the power module forming the semiconductor element 31, connecting busbars, and surrounding electronic components may scatter, potentially causing failure of the cell control unit 15, gate control units 91-94, and bypass element 25. Furthermore, the semiconductor element 32 may also malfunction and turn on, potentially causing a local short circuit based on path R1 as shown in Figure 3. In addition, the switching circuit 22 may also malfunction, potentially causing a local short circuit based on path R2 as shown in Figure 4.

[0066] Due to these effects, if the malfunctioning bypass element 25 fails to maintain a closed state, the power converter 110 will be unable to continuously perform power conversion operations. Furthermore, since the converter cell 10 is in a healthy state to begin with, if a short circuit of the bypass element can be prevented, the converter cell 10 can be restored to its normal state by repairing the bypass element 25.

[0067] The following describes a control procedure for controlling semiconductor elements 31 to 34 to the OFF state when a bypass element short circuit occurs. As an example, the case in which the gate control unit 91 detects a short circuit current will be described.

[0068] The gate control unit 91 receives a current detection signal from the control line 91b and, if it determines that the semiconductor element 31 is abnormal (i.e., a short-circuit current is flowing through the semiconductor element 31), it controls the semiconductor element 31 to the OFF state based on its own judgment, regardless of the signal received from the cell control unit 15.

[0069] Furthermore, the gate control unit 91 controls the semiconductor element 31 to the OFF state and transmits abnormality detection information indicating an abnormality in the semiconductor element 31 to the cell control unit 15. When the cell control unit 15 receives the abnormality detection information, it transmits an OFF control signal to the gate control units 91 to 94 to control the semiconductor elements 31 to 34 to the OFF state. When the gate control units 91 to 94 receive the OFF control signal from the cell control unit 15, they control the semiconductor elements 31 to 34 to the OFF state.

[0070] Here, we will explain why the cell control unit 15 sends an off control signal to the gate control units 91 to 94 when it receives abnormality detection information from the gate control unit 91.

[0071] When a short-circuit current flows along the path R3 shown in Figure 5, even if the semiconductor element 33 (specifically, the switching element 33s) is turned off, the diode 33d will still allow the short-circuit current to flow. Therefore, the cell control unit 15 transmits an off control signal to the gate control unit 91. The gate control unit 91 controls the semiconductor element 31 to the off state according to the received off control signal.

[0072] However, if the short-circuit current in path R3 is not successfully interrupted by the off-control of semiconductor element 31, semiconductor element 31 will fail. If semiconductor element 32 is controlled to the ON state while semiconductor element 31 has failed, a local short circuit in path R1 will occur as shown in Figure 3. In order to prevent this local short circuit, semiconductor element 32 must also be controlled to the OFF state, so the cell control unit 15 transmits an OFF control signal to the gate control unit 92.

[0073] Furthermore, if a bypass element short circuit occurs along path R3 when the semiconductor element 31 is turned on during the closing of the bypass element 25, then when the semiconductor element 34 is turned on by normal control, a bypass element short circuit occurs along path R4 as shown in Figure 6. When a short-circuit current flows along path R4, the short-circuit current cannot be interrupted even if the semiconductor element 32 (specifically, the switching element 32s) is turned off, so it is necessary to turn off the semiconductor element 34. For this reason, the cell control unit 15 transmits an off control signal to the gate control unit 94. The gate control unit 94 controls the semiconductor element 34 to the off state according to the received off control signal.

[0074] However, if the short-circuit current in path R4 is not successfully interrupted by the off-control of semiconductor element 34, semiconductor element 34 will fail. If semiconductor element 33 is turned on while semiconductor element 34 has failed, a local short circuit in path R2 will occur as shown in Figure 4. In order to prevent this local short circuit, it is necessary to control semiconductor element 33 to the off state as well, so the cell control unit 15 transmits an off control signal to the gate control unit 93.

[0075] Furthermore, if a bypass element short circuit occurs along path R3, a short-circuit current flows through semiconductor elements 31 and 33. In this case, the gate control unit 91 uses the current detection signal received via control line 91b to determine if the current flowing through semiconductor element 31 is abnormal, and the gate control unit 93 uses the current detection signal received via control line 93b to determine if the current flowing through semiconductor element 33 is abnormal.

[0076] Although the same current flows through semiconductor elements 31 and 33, there is a strict difference between the current detection signal received by the gate control unit 91 and the current detection signal received by the gate control unit 93. Therefore, a time difference occurs between the timing T3 at which the gate control unit 91 determines that semiconductor element 31 is abnormal and the timing T4 at which the gate control unit 93 determines that semiconductor element 33 is abnormal.

[0077] For example, if timing T3 is earlier than timing T4, the gate control unit 91 first turns off the semiconductor element 31 and transmits abnormality detection information to the cell control unit 15. Then, while the cell control unit 15 is transmitting the off control signal to the gate control unit 93, the gate control unit 93 determines that the semiconductor element 33 is abnormal. In this case, the gate control unit 93 controls the semiconductor element 33 to the off state at the earlier of the timing of receiving the off control signal from the cell control unit 15 and the timing of its own determination.

[0078] The above describes a typical case where the gate control unit 91 detects a short-circuit current flowing through the semiconductor element 31. However, similar control is performed when the gate control unit 92 detects a short-circuit current flowing through the semiconductor element 32. For example, when the gate control unit 92 detects a short-circuit current flowing through the semiconductor element 32, it controls the semiconductor element 32 to an off state based on its own judgment and transmits abnormality detection information to the cell control unit 15. When the cell control unit 15 receives the abnormality detection information, it transmits an off control signal to the gate control units 91 to 94.

[0079] Similar control is performed when the gate control units 93 and 94 detect a short-circuit current flowing through the semiconductor elements 33 and 34, respectively. For example, when the gate control unit 93 detects a short-circuit current flowing through the semiconductor element 33, it controls the semiconductor element 33 to the OFF state based on its own judgment and transmits abnormality detection information to the cell control unit 15. When the gate control unit 94 detects a short-circuit current flowing through the semiconductor element 34, it controls the semiconductor element 34 to the OFF state based on its own judgment and transmits abnormality detection information to the cell control unit 15. When the cell control unit 15 receives the abnormality detection information, it transmits an OFF control signal to the gate control units 91 to 94.

[0080] The above control procedure allows the short-circuit current flowing through paths R3 and R4 to be interrupted as quickly as possible.

[0081] Thus, although the short-circuit current path during a bypass element short circuit is different from the short-circuit current path during a local short circuit, it is understood that the operation of each gate control unit 91 to 94 when it detects a short-circuit current flowing to the semiconductor element to be driven during a bypass element short circuit is the same as the operation of each gate control unit 91 to 94 during a local short circuit.

[0082] <Short-circuit current detection method> Figure 7 is a diagram illustrating an example of a short-circuit current detection method. Referring to Figure 7, current sensors 51 to 63 are provided in the converter cell 10. Current sensor 51 is provided between capacitor EP and semiconductor element 31, current sensor 52 is provided between semiconductor element 31 and the connection point of semiconductor elements 31 and 32, current sensor 53 is provided between the connection point of semiconductor elements 31 and 32 and semiconductor element 32, and current sensor 54 is provided between semiconductor element 32 and the connection point of semiconductor elements 32 and 33.

[0083] Current sensor 55 is provided between the connection point of semiconductor elements 32 and 33 and semiconductor element 33, current sensor 56 is provided between semiconductor element 33 and the connection point of semiconductor elements 33 and 34. Current sensor 57 is provided between the connection point of semiconductor elements 33 and 34 and semiconductor element 34, and current sensor 58 is provided between capacitor EN and semiconductor element 34.

[0084] Current sensor 59 is provided between the connection point of capacitors EP and EN and the connection point of semiconductor elements 32 and 33. Current sensor 60 is provided between the connection point of semiconductor elements 31 and 32 and input / output terminal Po. Current sensor 61 is provided between input / output terminal Po and bypass element 25, and current sensor 62 is provided between input / output terminal No and bypass element 25. Current sensor 63 is provided between the connection point of semiconductor elements 33 and 34 and input / output terminal No.

[0085] The gate control units 91 to 94 each receive a current detection signal from at least one of the current sensors 51 to 63 via control lines 91b to 94b. Based on the at least one current detection signal, the gate control units 91 to 94 detect the short-circuit current flowing through the semiconductor elements 31 to 34.

[0086] For example, the gate control unit 91 detects the short-circuit current flowing through the semiconductor element 31 based on the current detection signal from the current sensor 51 or current sensor 52. For example, the gate control unit 91 determines that a short-circuit current is flowing through the semiconductor element 31 if the current indicated by the current detection signal from the current sensor 51 is greater than or equal to a threshold. The gate control unit 92 detects the short-circuit current flowing through the semiconductor element 32 based on the current detection signal from the current sensor 53 or current sensor 54. The gate control unit 93 detects the short-circuit current flowing through the semiconductor element 33 based on the current detection signal from the current sensor 55 or current sensor 56. The gate control unit 94 detects the short-circuit current flowing through the semiconductor element 34 based on the current detection signal from the current sensor 57 or current sensor 58. Note that each of the gate control units 91 to 94 may also use the current detection signals from other current sensors to detect the current flowing through the semiconductor element to be driven.

[0087] Furthermore, the converter cell 10 only needs to include a current sensor necessary for each gate control unit 91 to 94 to detect the short-circuit current flowing through the semiconductor element to be driven. Therefore, the converter cell 10 does not need to include all of the current sensors 51 to 63 as shown in Figure 7.

[0088] Figure 8 is a diagram illustrating another example of a short-circuit current detection method. Referring to Figure 8, the converter cell 10 has a gate drive circuit 80 (for example, a gate drive circuit included in the gate control unit 91), a detection unit 82 (for example, a detection circuit of the gate control unit 91) for detecting short-circuit currents, and a cutoff unit 83 that performs a cutoff operation when a short-circuit current is detected, with respect to the target semiconductor element 81 (for example, semiconductor element 31).

[0089] The detection unit 82 determines whether the collector potential is above a specified potential when an ON signal is input to the semiconductor element 81. When a short-circuit current is flowing, the voltage across capacitor EP is applied across the semiconductor element 81, causing the ON state voltage to rise. On the other hand, when no short-circuit current is flowing, the voltage drop across the semiconductor element 81 is several volts. The detection unit 82 determines whether a short-circuit current is flowing by comparing the detected collector potentials using a comparator.

[0090] The interruption unit 83 receives a signal from the detection unit 82 and performs an interruption operation on the semiconductor element 81. The interruption unit 83 may employ a "soft interruption" method, which interrupts the signal through a larger resistance than during normal operation.

[0091] Figure 9 illustrates yet another example of a short-circuit current detection method. Referring to Figure 9, the gate control unit detects the short-circuit current by utilizing the parasitic inductances 71-76 of the wiring of the converter cell 10.

[0092] Assume a local short circuit occurs, and a short-circuit current flows through path R1 (see Figure 3). In this case, a self-induced electromotive force generated in path R1 based on the time change of the short-circuit current generates voltages across the parasitic inductance 71 on the emitter side of semiconductor element 31 and the parasitic inductance 72 on the emitter side of semiconductor element 32. Typically, the gate control unit 91 detects the short-circuit current flowing through semiconductor element 31 based on the voltage of the parasitic inductance 71 on the emitter side of semiconductor element 31 to be driven. Specifically, the gate control unit 91 determines that the short-circuit current has occurred when the voltage of the parasitic inductance 71 is above a threshold. Similarly, the gate control unit 92 determines that a short-circuit current is flowing through semiconductor element 32 when the voltage of the parasitic inductance 72 is above a threshold.

[0093] The cell control unit 15 may receive a detection result from the gate control units 91 and 92 indicating that a short-circuit current has occurred in the semiconductor elements 31 and 32, and may determine that a short-circuit current indicated by path R1 has occurred based on the detection result.

[0094] Assume a local short circuit occurs, and a short-circuit current flows through path R2 (see Figure 4). In this case, a voltage is generated across the parasitic inductance 73 on the emitter side of semiconductor element 33 and the parasitic inductance 74 on the emitter side of semiconductor element 34 due to the self-induced electromotive force generated in path R2 based on the time change of the short-circuit current. Typically, the gate control unit 93 determines that a short-circuit current is flowing through semiconductor element 33 when the voltage across the parasitic inductance 73 is above a threshold. Similarly, the gate control unit 94 determines that a short-circuit current is flowing through semiconductor element 34 when the voltage across the parasitic inductance 74 is above a threshold.

[0095] The cell control unit 15 may receive a detection result from the gate control units 93 and 94 indicating that a short-circuit current has occurred in the semiconductor elements 33 and 34, and may determine that a short-circuit current shown in path R2 has occurred based on the detection result.

[0096] To detect a local short circuit following path R1, it is sufficient to detect at least one voltage across parasitic inductors 71 and 72. To detect a local short circuit shown in path R2, it is sufficient to detect at least one voltage across parasitic inductors 73 and 74.

[0097] Assume that a bypass element short circuit occurs and a short-circuit current flows through path R3 (see Figure 5). In this case, a voltage is generated in the parasitic inductance 71, parasitic inductance 75, or the combined inductance of parasitic inductances 71 and 75 due to the self-induced electromotive force generated in path R3 based on the time change of the short-circuit current. A voltage is also generated in the parasitic inductance 76, parasitic inductance 73, or the combined inductance of parasitic inductances 76 and 73. For example, the gate control unit 91 determines that a short-circuit current is flowing through semiconductor element 31 if the voltage of the combined inductance of parasitic inductances 71 and 75 is above a threshold. For example, the gate control unit 93 determines that a short-circuit current is flowing through semiconductor element 33 if the voltage of the combined inductance of parasitic inductances 76 and 73 is above a threshold.

[0098] The cell control unit 15 may receive a detection result from the gate control units 91 and 93 indicating that a short-circuit current has occurred in the semiconductor elements 31 and 33, and may determine that a short-circuit current indicated by path R3 has occurred based on the detection result.

[0099] Assume that a bypass element short circuit occurs and a short-circuit current flows through path R4 (see Figure 6). In this case, a voltage is generated in the parasitic inductance 72, parasitic inductance 75, or the combined inductance of parasitic inductances 72 and 75 due to the self-induced electromotive force generated in path R4 based on the time change of the short-circuit current. A voltage is also generated in the parasitic inductance 76, parasitic inductance 74, or the combined inductance of parasitic inductances 76 and 74. For example, the gate control unit 92 determines that a short-circuit current is flowing through semiconductor element 32 if the voltage of the combined inductance of parasitic inductances 72 and 75 is above a threshold. For example, the gate control unit 94 determines that a short-circuit current is flowing through semiconductor element 34 if the voltage of the combined inductance of parasitic inductances 76 and 74 is above a threshold.

[0100] The cell control unit 15 may receive a detection result from the gate control units 92 and 94 indicating that a short-circuit current has occurred in the semiconductor elements 32 and 34, and may determine that a short-circuit current shown in path R4 has occurred based on the detection result.

[0101] When detecting the short-circuit current flowing through the bypass element 25, if the detection method using the collector potential described in Figure 8 is used, the rise in the collector potential is slow, which can make it difficult or time-consuming to detect the short-circuit current itself. In this respect, the detection method in Figure 9 is more useful than the detection method in Figure 8.

[0102] <Flowchart> As described above, regardless of whether it is a local short circuit or a bypass element short circuit, the gate control units 91 to 94 perform the same processing when a short circuit current is detected. Here, the processing procedure of any gate control unit among the gate control units 91 to 94 and the processing procedure of the cell control unit 15 will be explained.

[0103] Figure 10 is a flowchart showing an example of the processing procedure of the gate control unit. Referring to Figure 10, the gate control unit (for example, the gate control unit 91) determines whether or not it has detected a short-circuit current flowing through the semiconductor element to be driven (for example, the semiconductor element 31 to be driven by the gate control unit 91) based on the current detection signal received via the corresponding control line (step S10). If no short-circuit current is detected (NO in step S10), the gate control unit performs step S10 again. On the other hand, if a short-circuit current is detected (YES in step S10), the gate control unit determines whether or not the semiconductor element to be driven (hereinafter also simply referred to as "target semiconductor element") is already controlled to the OFF state based on the OFF control signal received from the cell control unit 15 (step S12).

[0104] If the target semiconductor element is controlled to be in the off state (YES in step S12), the gate control unit terminates processing. If the target semiconductor element is not controlled to be in the off state (NO in step S12), the gate control unit controls the target semiconductor element to be in the off state based on its own judgment (step S14). Subsequently, the gate control unit transmits abnormality detection information to the cell control unit 15 (step S16).

[0105] Figure 11 is a flowchart showing another example of the processing procedure of the gate control unit. Referring to Figure 11, the gate control unit determines whether or not it has received an off control signal from the cell control unit 15 (step S30). If it has not received an off control signal (NO in step S30), the gate control unit repeats step S30. On the other hand, if it has received an off control signal (YES in step S30), the gate control unit determines, by its own judgment, whether or not the target semiconductor element has already been controlled to the off state (step S32).

[0106] If the target semiconductor element is controlled to be in the off state (YES in step S32), the gate control unit terminates the process. If the target semiconductor element is not controlled to be in the off state (NO in step S32), the gate control unit controls the target semiconductor element to be in the off state based on the off control signal (step S34).

[0107] Each gate control unit 91 to 94 executes the processes shown in the flowcharts in Figures 10 and 11 in parallel. As a result, each gate control unit 91 to 94 turns off the target semiconductor element at the earlier of the timing of detecting the short-circuit current flowing through the target semiconductor element and the timing of receiving the off control signal.

[0108] Figure 12 is a flowchart showing an example of the processing procedure of the cell control unit. Referring to Figure 12, the cell control unit 15 determines whether or not it has received abnormality detection information from any of the gate control units 91 to 94 (step S50). If abnormality detection information has not been received (NO in step S50), the cell control unit 15 repeats the process of step S50. If abnormality detection information has been received (YES in step S50), the cell control unit 15 sends an OFF control signal to each of the gate control units 91 to 94 (step S52).

[0109] <Advantages> According to this embodiment, if a short-circuit-related abnormality occurs in any of the semiconductor elements 31 to 34, the short-circuit current due to the local short circuit following paths R1 and R2 can be interrupted as quickly as possible. Therefore, the normal semiconductor elements included in the converter cell 10 can be protected. Also, if the semiconductor elements 31 to 34 are in a normal state but the bypass element 25 is mistakenly switched on, the short-circuit current due to the bypass element short circuit following paths R3 and R4 can be interrupted as quickly as possible. Therefore, the semiconductor elements included in the converter cell 10 can be protected. Consequently, in both cases of semiconductor element abnormality and mistaken switch-on of the bypass element, the bypass element 25 operates normally and the converter cell 10 can be bypassed normally. Therefore, the operation of the power converter 100 can be continued.

[0110] Other embodiments. (1) In the embodiments described above, a configuration was described in which the gate control units 91 to 94 each detect the short-circuit current flowing through the semiconductor elements 31 to 34 to be driven. However, considering the paths R1 and R2 of the short-circuit current during a local short circuit and the paths R3 and R4 of the short-circuit current during a bypass element short circuit, it is not necessary for all of the gate control units 91 to 94 to detect the short-circuit current.

[0111] Specifically, referring to Figures 3 and 5, the semiconductor element 31 is included in both path R1 and path R3. Therefore, if a local short circuit occurs in path R1 or a bypass element short circuit occurs in path R3, the semiconductor element 31 is controlled to an off state, thereby interrupting the short-circuit current flowing through paths R1 and R3.

[0112] For example, suppose a short-circuit current flows through path R1 or path R3. In this case, the gate control unit 91 detects the short-circuit current flowing through the semiconductor element 31 and, based on its own judgment, controls the semiconductor element 31 to the OFF state. This interrupts the short-circuit current flowing through path R1 or path R3. The gate control unit 91 also transmits abnormality detection information to the cell control unit 15. Based on the receipt of this abnormality detection information, the cell control unit 15 transmits an OFF control signal to the gate control units 91 to 94. As a result, the semiconductor elements 31 to 34 driven by each gate control unit 91 to 94 are controlled to the OFF state, and consequently, the short-circuit current flowing through all paths R1 to R4 is interrupted.

[0113] Next, referring to Figures 4 and 6, both paths R2 and R4 include the semiconductor element 34. Therefore, if a local short circuit occurs in path R2 or a bypass element short circuit occurs in path R4, the semiconductor element 34 is controlled to an off state, thereby interrupting the short-circuit current flowing through paths R2 and R4.

[0114] For example, suppose a short-circuit current flows through path R2 or path R4. In this case, the gate control unit 94 detects the short-circuit current flowing through the semiconductor element 34 and, based on its own judgment, controls the semiconductor element 34 to the OFF state. This interrupts the short-circuit current flowing through path R2 or path R4. The gate control unit 94 also transmits abnormality detection information to the cell control unit 15. Based on the receipt of this abnormality detection information, the cell control unit 15 transmits an OFF control signal to the gate control units 91 to 94. As a result, the semiconductor elements 31 to 34 driven by each of the gate control units 91 to 94 are controlled to the OFF state, and consequently, the short-circuit currents flowing through all paths R1 to R4 are interrupted.

[0115] Therefore, a configuration may be chosen in which gate control units 91 and 94 are selected as gate control units having a detection circuit for detecting short-circuit current. In this case, gate control units 91 and 94 each have the function of controlling semiconductor elements 31 and 34 to the off state based on their own judgment, but gate control units 92 and 93 do not have this function. Therefore, gate control units 92 and 93 each control semiconductor elements 32 and 33 to the off state based on the off control signal received from the cell control unit 15.

[0116] (2) The restart of the converter cell 10 after the semiconductor elements 31 to 34 have been controlled to the off state according to the embodiment described above will be explained. When a local short circuit or bypass element short circuit occurs and the semiconductor elements 31 to 34 are controlled to the off state (for example, gate blocked), the charge of capacitors EP and EN is retained. However, strictly speaking, when the voltage Vep of capacitor EP and the voltage Ven of capacitor EN are applied to the semiconductor elements 31 to 34, leakage current is generated in the semiconductor elements 31 to 34, and capacitors EP and EN discharge naturally. However, the discharge time depends on the degree of leakage current, and in the case of semiconductor elements with low leakage current, the charge of capacitor EP and the charge of capacitor EN may be retained for several minutes to several hours.

[0117] When capacitors EP and EN are charged, that is, when a voltage is applied to semiconductor elements 31 to 34, and the on / off control of semiconductor elements 31 to 34 is resumed (for example, when semiconductor elements 31 to 34 in a gate-blocked state are deblocked (i.e., when semiconductor elements 31 to 34 can be turned on and off)), a local short circuit or bypass element short circuit may occur again. In this case, the gate control units 91 to 94 can control each semiconductor element 31 to 34 to the off state by detecting the short-circuit current. However, the short-circuit current may flow through the switching circuits 21 and 22 many times, potentially causing wear on the semiconductor elements 31 to 34 and the bypass element 25.

[0118] Therefore, it is preferable to restart the converter cell 10 (i.e., restart the on / off control of semiconductor elements 31-34) when voltages Vep and Ven become low. The capacitor voltage that allows restarting is determined by the operator. Here, let's assume that the capacitor voltage at which restarting can be initiated is "Vth".

[0119] The cell control unit 15 constantly monitors the voltages Vep and Ven and maintains the off state of semiconductor elements 31-34 until both voltages Vep and Ven fall below the capacitor voltage Vth. When both voltages Vep and Ven fall below the capacitor voltage Vth, the cell control unit 15 resumes the on / off control of semiconductor elements 31-34 that were maintained in the off state (i.e., deblocks semiconductor elements 31-34 that were in a gate-block state). Specifically, the cell control unit 15 sends a deblock command to each gate control unit 91-94. When gate control units 91-94 receive a deblock command, they each resume the on / off control of semiconductor elements 31-34.

[0120] As a result, when capacitors EP and EN are in a low-voltage state, the converter cell 10 is restarted, and semiconductor elements 31 to 34 are controlled on and off. Even if a local short circuit or bypass element short circuit occurs again, the degree of wear can be reduced. Specifically, the short-circuit current can be reduced, and the energy of the semiconductor elements when a short circuit occurs can be reduced.

[0121] (3) In the above-described embodiment, when an abnormality is detected in the semiconductor element of the converter cell 10, the cell control unit 15 closes the bypass element 25 in accordance with the instruction to close the bypass element 25 received from the control device 120, but the embodiment is not limited to this configuration.

[0122] For example, the cell control unit 15 may execute control to close the bypass element 25 when it receives abnormality detection information from any of the gate control units 91 to 94. In this case, the cell control unit 15 transmits an off control signal to each of the gate control units 91 to 94 during the period before the bypass element 25 is closed in response to the control. As a result, the semiconductor elements 31 to 34 are controlled to the off state before the bypass element 25 is closed. Therefore, at the time the bypass element 25 is actually closed, any short-circuit current that may flow through path R3 or path R4 is suppressed, preventing damage to the bypass element 25.

[0123] (4) The configurations illustrated above as embodiments are examples of the configurations of the present disclosure and can be combined with other known technologies, and can be modified, such as by omitting parts, without departing from the gist of the present disclosure. Furthermore, in the embodiments described above, processes and configurations described in other embodiments may be adopted as appropriate.

[0124] The embodiments disclosed herein should be considered in all respects to be illustrative and not restrictive. The scope of this disclosure is indicated by the claims rather than by the foregoing description, and all modifications within the meaning and scope of the claims are intended to be included.

[0125] 10 Converter cell, 14N, 14P reactor, 15 Cell control unit, 21, 22 Switching circuit, 25 Bypass element, 31-34, 81 Semiconductor element, 31d-34d Diode, 31s-34s Switching element, 40u-40w Reg circuit, 51-63 Current sensor, 71-76 Parasitic inductance, 80 Gate drive circuit, 82 Detection unit, 83 Cutoff unit, 91-94 Gate control unit, 100 Power converter, 110 Power converter, 120 Control device, 130 DC circuit, 140 Transformer, 150 AC circuit, EN, EP Capacitor, Nn Negative DC terminal, No, Po Input / Output terminal, Np Positive DC terminal, Nu, Nv, Nw AC terminal, R1-R4 Path.

Claims

1. A power conversion device comprising a plurality of converter cells connected in series, wherein each of the plurality of converter cells includes a cell control unit, a first switching circuit and a second switching circuit connected in series, a first input / output terminal and a second input / output terminal, the first switching circuit includes a first semiconductor element, a second semiconductor element, and a first energy storage element connected in parallel to a series assembly including the first semiconductor element and the second semiconductor element, the first input / output terminal is connected to the connection point between the negative terminal of the first semiconductor element and the positive terminal of the second semiconductor element, the second switching circuit includes a third semiconductor element, a fourth semiconductor element, and a second energy storage element connected in parallel to a series assembly including the third semiconductor element and the fourth semiconductor element, the second input / output terminal is connected to the connection point between the negative terminal of the third semiconductor element and the positive terminal of the fourth semiconductor element, Each of the plurality of converter cells further includes a first gate control unit for driving the first semiconductor element, a second gate control unit for driving the second semiconductor element, a third gate control unit for driving the third semiconductor element, and a fourth gate control unit for driving the fourth semiconductor element, wherein when one of the first to fourth gate control units detects a short-circuit current flowing through the semiconductor element to be driven by the first gate control unit, it controls the semiconductor element to be driven to an off state and transmits abnormality detection information to the cell control unit, and when the cell control unit receives the abnormality detection information, it transmits a control signal to each of the first to fourth gate control units to control the semiconductor element to be driven by the gate control unit to an off state, power converter device.

2. The power conversion device according to claim 1, wherein each of the first to fourth gate control units, upon receiving the control signal, controls the semiconductor element to be driven by the gate control unit to be in the off state if the semiconductor element to be driven by the gate control unit is not controlled to be in the off state.

3. The power conversion device according to claim 1 or claim 2, wherein the gate control unit in 1 is the first gate control unit or the fourth gate control unit.

4. The power conversion device according to claim 3, wherein the gate control unit of item 1 detects a short-circuit current flowing through the semiconductor element to be driven based on the voltage of the parasitic inductance on the emitter side of the semiconductor element to be driven among the first to fourth semiconductor elements.

5. The power conversion device according to any one of claims 1 to 4, wherein the cell control unit maintains the off state of the first to fourth semiconductor elements until both the first voltage of the first energy storage element and the second voltage of the second energy storage element fall below a threshold after receiving the abnormality detection information.

6. The power converter according to any one of claims 1 to 5, wherein each of the plurality of converter cells further includes a bypass element connected between the first input / output terminal and the second input / output terminal, the cell control unit, upon receiving the abnormality detection information, executes control to close the bypass element, and transmits the control signal to each of the first to fourth gate control units during the period before the closure of the bypass element is established in response to the control.

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