Light detection device

Abstract

[Problem] To be able to improve noise characteristics. [Solution] This light detection device comprises: a first electrode; a first semiconductor region of a first conductivity type that is connected to the first electrode; a second semiconductor region of a second conductivity type that is positioned in a different layer from the first semiconductor region, and is positioned so as to be in contact with a portion of the perimeter of the first semiconductor region without being in contact with the entire perimeter of the same in plan view; a second electrode that is connected to the second semiconductor region; a third semiconductor region that is positioned in the surroundings of the first semiconductor region and the second semiconductor region, and converts incident light into an electric charge; and an avalanche region that is positioned in a location where the first semiconductor region and the second semiconductor region are in contact, and multiplies the electric charge resulting from the conversion by the third semiconductor region.

Description

Optical detection device

[0001] The present disclosure relates to an optical detection device.

[0002] A SPAD (Single Photon Avalanche Diode) that multiplies the charge obtained by photoelectrically converting one incident photon is known (see Patent Documents 1 to 3). Compared with a conventional CMOS (Complementary Metal-Oxide-Semiconductor) image sensor or the like, a SPAD can detect weak light at high sensitivity and high speed.

[0003] Japanese Patent Application Laid-Open No. 2018-201005 Japanese Patent Application Laid-Open No. 2022-83067 Japanese Patent Application Laid-Open No. 2024-12455

[0004] However, in Patent Document 1, an avalanche multiplication region is arranged along the optical propagation direction of the well layer, which is a region for performing photoelectric conversion. As a result, the photoelectric conversion region of the well layer becomes narrower by the amount of the avalanche multiplication region provided, the sensitivity decreases, and the noise characteristics may deteriorate. In addition, in Patent Document 2, the P+-type semiconductor region and the N+-type semiconductor region constituting the avalanche region face each other at the corners. Therefore, the position where the electric field becomes maximum shifts inside the N+-type semiconductor region from the PN junction interface. Since the N+-type semiconductor region has a high impurity concentration and includes a high defect region, when a strong electric field region shifts to the N+-type semiconductor region, the DCR (Darck Count Rate) deteriorates and the noise characteristics deteriorate. Patent Document 3 also has the same problem as Patent Document 2.

[0005] Therefore, the present disclosure provides an optical detection device that can improve noise characteristics.

[0006] To solve the above problems, the present disclosure provides a photodetector comprising: a first electrode; a first semiconductor region of a first conductivity type connected to the first electrode; a second semiconductor region of a second conductivity type arranged on a different layer from the first semiconductor region and arranged so as to contact a part of the outer periphery of the first semiconductor region in a plan view, rather than the entire outer periphery; a second electrode connected to the second semiconductor region; a third semiconductor region arranged around the first and second semiconductor regions and converting incident light into electric charge; and an avalanche region arranged at the point where the first and second semiconductor regions are in contact and multiplying the electric charge converted by the third semiconductor region.

[0007] The system may comprise a plurality of second semiconductor regions, each arranged separately on the same layer and each arranged in contact with a portion of the outer periphery of the first semiconductor region in a plan view.

[0008] The second semiconductor region and the first semiconductor region may be joined at one corner of each.

[0009] The semiconductor region may also include a fourth semiconductor region that is located on the same layer as the second semiconductor region and overlaps with at least a portion of the first semiconductor region in a plan view, and has a lower impurity concentration than the second semiconductor region, or a lower impurity concentration than the first semiconductor region.

[0010] The fifth semiconductor region of the first conductivity type is located on the same layer as the first semiconductor region and is arranged to overlap at least a portion of the second semiconductor region in a plan view, and has a lower impurity concentration than the first semiconductor region. Alternatively, the fifth semiconductor region may be located on the same layer as the first semiconductor region and is arranged to overlap at least a portion of the second semiconductor region in a plan view.

[0011] It may have a second insulating region arranged to surround the first electrode.

[0012] Furthermore, the present disclosure provides a photodetector comprising: a first electrode; a first semiconductor region of a first conductivity type connected to the first electrode; a second semiconductor region of a second conductivity type, at least a portion of which is arranged on the same layer as the first semiconductor region and is arranged to be in contact with at least a portion of the outer periphery of the first semiconductor region in a plan view; a second electrode connected to the second semiconductor region; a third semiconductor region arranged around the first and second semiconductor regions and converting incident light into electric charge; and an avalanche region arranged along the junction surface where the first and second semiconductor regions are in contact and multiplying the charge converted in the third semiconductor region.

[0013] The semiconductor may also include at least one of the following: a fourth semiconductor region of the first conductivity type, which is located on the light incident side of the second semiconductor region and overlaps with at least a portion of the second semiconductor region in a plan view, and has a lower impurity concentration than the first semiconductor region; or a fifth semiconductor region of the second conductivity type, which is located on the light incident side of the first semiconductor region and overlaps with at least a portion of the first semiconductor region in a plan view, and has a lower impurity concentration than the second semiconductor region.

[0014] The fourth semiconductor region of the second conductivity type may be provided, which is located on the light incident surface side of the first semiconductor region and the second semiconductor region, and is arranged to overlap with at least a portion of the first semiconductor region and the second semiconductor region in a plan view, and has a lower impurity concentration than the second semiconductor region.

[0015] The second semiconductor region may be arranged so as to be in contact with the entire outer periphery of the first semiconductor region in a plan view.

[0016] The second semiconductor region may be arranged so as not to be in contact with the entire outer periphery of the first semiconductor region in a plan view, but to be in contact with a part of the outer periphery.

[0017] The first semiconductor region and the second semiconductor region may each be joined to one surface.

[0018] The second semiconductor region may be arranged radially or linearly from the first semiconductor region in a plan view.

[0019] The second semiconductor region may be positioned on a line connecting the first electrode and the second electrode in a plan view.

[0020] The system may include a plurality of second electrodes, each spaced apart from the others and electrically connected to the second semiconductor region.

[0021] The first semiconductor region, the second semiconductor region, the third semiconductor region, and the avalanche region may include pixels that are triangular or polygonal, circular, or elliptical in a plan view.

[0022] If the pixel is polygonal in plan view, the second electrode may be placed at each corner of the polygon.

[0023] The second electrode may be arranged in a ring shape along the outer circumference of the pixel in a plan view.

[0024] The first electrode and the second electrode may be arranged at a distance from each other along a direction intersecting the plane of incidence of light.

[0025] The first semiconductor region, the second semiconductor region, the third semiconductor region, and the avalanche region may have a SPAD (Single Photon Avalanche Diode).

[0026] A plan view of a pixel according to the first embodiment of this disclosure. A longitudinal section of the pixel in Figure 1 along the line A-A. A longitudinal section of the pixel in Figure 1 along the line B-B. A cross-sectional view of the pixel in Figures 2A and 2B along the line C-C. A cross-sectional view of the pixel in Figures 2A and 2B along the line D-D. A cross-sectional view of the pixel in Figures 2A and 2B along the line E-E. An enlarged cross-sectional view of the pixel near the PN junction region in Figure 2A. A diagram showing the stacked structure of the photodetector according to the first embodiment of this disclosure. A diagram showing the stacked structure of the photodetector according to a modified example. A diagram showing the equivalent resistance inside the pixel according to the first embodiment of this disclosure. An equivalent circuit diagram of the equivalent resistance in Figure 6. A longitudinal section of a pixel according to the first comparative example. An enlarged cross-sectional view of the area near the PN junction region in Figure 8. A diagram showing the equivalent resistance inside the pixel according to the first comparative example. An equivalent circuit diagram of the equivalent resistance in Figure 10. A plan view of a pixel according to the second comparative example. A cross-sectional view of a pixel according to the second comparative example. An enlarged cross-sectional view of the vicinity of the PN junction region of a pixel according to the second comparative example. A plan view of a pixel according to the second embodiment of this disclosure. A longitudinal cross-sectional view of the pixel in Figure 15 along the A-A line. A longitudinal cross-sectional view of the pixel in Figure 15 along the B-B line. A plan view of a pixel according to the first modified example of Figure 15. A plan view of a pixel according to the second modified example of Figure 15. A longitudinal cross-sectional view of a pixel in Figure 18 along the F-F line. A plan view of a pixel according to the third modified example of Figure 15. A plan view of a pixel according to the fourth modified example of Figure 15. A plan view of a pixel according to the fifth modified example of Figure 15. A longitudinal cross-sectional view of a pixel according to the third embodiment of this disclosure. A cross-sectional view of a pixel in Figure 23 along the E-E line. A longitudinal cross-sectional view of a pixel according to the fourth embodiment of this disclosure. A cross-sectional view of a pixel in Figure 25 along the C-C line. A cross-sectional view of a pixel in Figure 25 along the D-D line. A longitudinal cross-sectional view of a pixel according to one modified example of Figure 25. A longitudinal cross-sectional view of a pixel according to the fifth embodiment of this disclosure. A longitudinal section of a pixel according to the sixth embodiment of this disclosure. A plan view of a pixel according to the seventh embodiment of this disclosure. A longitudinal section of the pixel in Figure 30 along the line A-A. A longitudinal section of the pixel in Figure 30 along the line B-B. A cross-sectional view of the pixel in Figures 31A and 31B along the line E-E. A cross-sectional view of the pixel in Figure E-E according to the first modified example of Figure 30. A longitudinal section of the pixel according to the second modified example of Figure 30. A plan view of the pixel according to the third modified example of Figure 30. A longitudinal section of the pixel according to the fourth modified example of Figure 30. A longitudinal section of a pixel according to the eighth embodiment of this disclosure. A longitudinal section of a pixel according to one modified example of Figure 37. A cross-sectional view of the pixel in Figure 38 along the line G-G. A longitudinal section of a pixel according to the ninth embodiment of this disclosure. A cross-sectional view of the pixel in Figure G-G along the line G-G.A block diagram of a distance measuring system according to the tenth embodiment of this disclosure. A block diagram showing an example of the schematic configuration of a vehicle control system. An explanatory diagram showing an example of the installation positions of the external information detection unit and the imaging unit.

[0027] The embodiments of the photodetector will be described below with reference to the drawings. While the main components of the photodetector will be described below, there may be components and functions not shown or described in the drawings. The following description does not exclude any components or functions not shown or described.

[0028] (First Embodiment) Figure 1 is a plan view of a pixel 1 arranged in a photodetector according to the first embodiment of the present disclosure. More specifically, Figure 1 is a plan view of the pixel 1 seen from below a predetermined height. The pixel 1 has a first electrode 2, a second electrode 3, a first semiconductor region 4, a second semiconductor region 5, a third semiconductor region 6, and a semiconductor region 7. A lens and a color filter are provided above the predetermined height of the pixel 1, as will be described later. The predetermined height refers to the location of the second semiconductor region 5, which will be described later.

[0029] Pixel 1 has a photoelectric conversion element (e.g., SPAD). The first electrode 2 is, for example, the cathode electrode of the photoelectric conversion element. The second electrode 3 is, for example, the anode electrode of the photoelectric conversion element.

[0030] Furthermore, pixel 1 has a photoelectric conversion region that converts incident light into electric charge, and an avalanche region that multiplies the charge converted in the photoelectric conversion region. The first semiconductor region 4 and the second semiconductor region 5 have a PN junction region H where their corners are in contact. An avalanche region is formed near the PN junction region H. The third semiconductor region 6 is a region that constitutes at least a part of the above-mentioned photoelectric conversion region.

[0031] The first semiconductor region 4 is connected to the first electrode 2. The second semiconductor region 5 is connected to the second electrode 3 via the semiconductor region 7.

[0032] The first semiconductor region 4 is implanted with impurities of a first conductivity type. The second semiconductor region 5 and the semiconductor region 7 are implanted with impurities of a second conductivity type. The first electrode 2 may be formed from a semiconductor region of a first conductivity type with a higher impurity concentration than the first semiconductor region 4. The second electrode 3 may be formed from a semiconductor region of a second conductivity type with a higher impurity concentration than the second semiconductor region 5.

[0033] This specification describes an example in which the first electrode 2, the second electrode 3, the first semiconductor region 4, the second semiconductor region 5, and the semiconductor region 7 are, respectively, an n(n+) type semiconductor region, a p(p+) type semiconductor region, an n type semiconductor region, a p type semiconductor region, and an n type semiconductor region. However, the specification is not limited to this example, and the first electrode 2, the second electrode 3, the first semiconductor region 4, the second semiconductor region 5, and the semiconductor region 7 may also be, respectively, a p(p+) type semiconductor region, an n(n+) type semiconductor region, a p type semiconductor region, an n type semiconductor region, and a p type semiconductor region.

[0034] In pixel 1, photons are detected in the photoelectric conversion region (third semiconductor region 6, etc.), and electric charge (e.g., electrons) is generated based on the photons. The generated charge is accelerated by the strong electric field of the avalanche region and collides with atoms in the first semiconductor region 4 and the second semiconductor region 5, causing collisional ionization and generating new charge. As the newly generated charge undergoes repeated collisional ionization, the charge is rapidly multiplied (avalanche multiplication), and the voltage between the first electrode 2 and the second electrode 3 fluctuates greatly (e.g., decreases). By detecting the voltage fluctuation between the first electrode 2 and the second electrode 3 in pixel 1, photons incident on pixel 1 can be detected one photon at a time.

[0035] The avalanche multiplication described above can be stopped by releasing the charge generated by the avalanche multiplication outside the pixel 1 through the first electrode 2 and the second electrode 3. The voltage between the first electrode 2 and the second electrode 3 that fluctuates due to the avalanche multiplication (breakdown voltage), or the timing of stopping the avalanche multiplication, is also referred to as the quench characteristic in this specification. The quench characteristic is influenced by the path that the charge takes to be transported to the first electrode 2 and the second electrode 3. In the pixel 1, it is desirable that there is no variation in the quench characteristic each time a photon is detected.

[0036] Next, the layout configuration of pixel 1 in plan view will be described. Figure 1 shows the first electrode 2, second electrode 3, first semiconductor region 4, second semiconductor region 5, and semiconductor region 7 arranged in multiple layers of pixel 1 in a plan view. Details of the layers of pixel 1 will be described later.

[0037] The first electrode 2 is positioned, for example, in the center of the pixel 1. The first semiconductor region 4 is, for example, a region with a larger area than the first electrode 2 and is positioned to cover the first electrode 2. Figure 1 shows an example where the first semiconductor region 4 is a circular region with a larger diameter than the first electrode 2.

[0038] In pixel 1 of Figure 1, multiple second semiconductor regions 5 are arranged radially from the first semiconductor region 4. In the example of Figure 1, four second semiconductor regions 5 are arranged to form a cross. That is, in pixel 1 of Figure 1, four avalanche regions are formed near the four PN junction regions H between the first semiconductor region 4 and the second semiconductor regions 5. Note that avalanche regions can be formed not only in the PN junction regions H, but also in the interface region between the first semiconductor region 4 and the third semiconductor region 6 (for example, the interface region Ha described later).

[0039] In pixel 1 of Figure 1, multiple second electrodes 3 are arranged at a distance from the second semiconductor region 5. Figure 1 shows an example where four second electrodes 3 are arranged at the four corners of a rectangular pixel 1. That is, in Figure 1, the second electrodes 3 are arranged to be away from the first electrode 2.

[0040] The first electrode 2 and the second electrode 3 are arranged, for example, on a substrate as described later. As described above, by arranging the second electrode 3 away from the first electrode 2 in a plan view, the electric field between the first electrode 2 and the second electrode 3 on the substrate surface is mitigated, and the deterioration of the DCR can be suppressed.

[0041] The third semiconductor region 6 is positioned around the first semiconductor region 4 and the second semiconductor region 5. The semiconductor region 7 is positioned between the second electrode 3 and the second semiconductor region 5. In the example shown in Figure 1, the semiconductor region 7 is positioned on the side wall of the pixel 1.

[0042] FIG. 1 illustrates a path K1 of charges (e.g., holes) generated by avalanche multiplication. The path K1 is a path through which holes generated in any one of a plurality of avalanche regions are transported to any one of a plurality of second electrodes 3. As shown in the path K1, the holes are transported to the second electrode 3 via the second semiconductor region 5 and the semiconductor region 7.

[0043] In the pixel 1, there may be a plurality of paths K1 through which holes pass. A corresponding second semiconductor region 5 is provided in each of the plurality of paths K1. For example, by symmetrically arranging the plurality of second semiconductor regions 5 in the pixel 1 and making the shapes and sizes of the plurality of second semiconductor regions 5 uniform, the path lengths through which the holes pass through the plurality of paths K1 can be made substantially the same. Thereby, the variation in the above-described quenching characteristics can be suppressed.

[0044] FIG. 2A is a longitudinal sectional view of the pixel 1 in the direction of line A-A in FIG. 1. In FIG. 2A, the cross section of the second semiconductor region 5 is shown. FIG. 2B is a longitudinal sectional view of the pixel 1 in the direction of line B-B in FIG. 1. In FIG. 2B, the cross section of the second electrode 3 is shown. Light is incident from above in FIGS. 2A and 2B.

[0045] FIGS. 2A and 2B illustrate a substrate 11 on which a first electrode 2, a second electrode 3, a first semiconductor region 4, a second semiconductor region 5, a third semiconductor region 6, and a semiconductor region 7 are arranged. The substrate 11 is, for example, a silicon (Si) substrate. The first electrode 2 and the second electrode 3 are connected to wiring layers in the substrate 11. In this specification, the first semiconductor region 4, the second semiconductor region 5, the third semiconductor region 6, the semiconductor region 7, and the substrate 11 may be collectively referred to as the substrate 11. Further, FIG. 2A shows an interface region Ha on the light incident surface side of the first semiconductor region 4 and the third semiconductor region 6 where an avalanche region is formed.

[0046] Also, in FIGS. 2A and 2B, a lens (on-chip lens) 12 and a color filter 13 of the pixel 1 are shown. The lens 12 is arranged to face the substrate 11 and condenses incident light onto the photoelectric conversion region of the pixel 1.

[0047] The color filter 13 transmits or blocks light of a predetermined wavelength among the incident light to the pixel 1. For the color filter 13, for example, a color filter that transmits visible light or an infrared (near-infrared) pass filter that transmits infrared rays can be used. By changing the color filter 13 disposed on the pixel 1, the use of the pixel 1 can be changed.

[0048] For example, by disposing a color filter 13 that transmits any one of red, green, or blue light on the pixel 1, the pixel 1 can be used as a Red pixel, a Green pixel, or a Blue pixel. By disposing one or more of a Red pixel, a Green pixel, or a Blue pixel (hereinafter also referred to as an RGB pixel) in the light detection device according to the first embodiment of the present disclosure, gradation information can be obtained from the incident light, and color image data and the like can be generated. Further, when an infrared filter is disposed as the color filter 13, the pixel 1 can be used as an IR pixel. By disposing an IR pixel in the light detection device, the light detection device can be used for applications such as distance measurement or optical communication. It is also possible to dispose both RGB pixels and IR pixels in the light detection device. In this case, for the color filter 13 disposed on the RGB pixel, a filter in which a color filter that transmits any one of red, green, or blue light and an infrared cut (IR Cut) filter are laminated can be used. Further, for the color filter 13 disposed on the IR pixel, for example, a filter in which a color filter that transmits red light and a color filter that transmits blue light are laminated can be used as an infrared filter.

[0049] The pixel 1 may include a pixel transistor that transfers the charges of the first electrode 2 and the second electrode 3 or supplies charges to the first electrode 2 and the second electrode 3. Further, an interlayer insulating film that insulates the pixel 1 from other layers (such as a wiring layer) may be disposed on the pixel 1. In FIGS. 2A and 2B, illustration of the pixel transistor and the interlayer insulating film is omitted.

[0050] Figure 2A illustrates the sensitive region A1 and the insensitive region A2 of the third semiconductor region 6. Sensitive region A1 is the region of the third semiconductor region 6 located on the light incident surface side than the first semiconductor region 4 and the second semiconductor region 5. Insensitive region A2 is the region of the third semiconductor region 6 other than sensitive region A1.

[0051] In the third semiconductor region 6, when a charge is generated by photoelectric conversion in the sensitivity region A1, the generated charge passes through the avalanche region. As a result, the pixel 1 can detect the avalanche-multiplied charge, and thus a photon can be detected in the sensitivity region A1.

[0052] On the other hand, even if a charge is generated in the insensitive region A2, the generated charge does not pass through the avalanche region and does not undergo avalanche multiplication. Therefore, in pixel 1, photons cannot be detected in the insensitive region A2. In pixel 1, it is desirable to increase the sensitivity region A1 and decrease the insensitive region A2.

[0053] Figure 3A is a cross-sectional view of pixel 1 in Figures 2A and 2B along the C-C line. Figure 3B is a cross-sectional view of pixel 1 in Figures 2A and 2B along the D-D line. Figure 3C is a cross-sectional view of pixel 1 in Figures 2A and 2B along the E-E line. In this specification, the C-C line direction, D-D line direction, and E-E line direction of pixel 1 in Figures 2A and 2B are referred to as the first layer L1, the second layer L2, and the third layer L3, respectively. The first layer L1, the second layer L2, and the third layer L3 are arranged in this order from the substrate 11 side.

[0054] As shown in Figure 3A, the first layer L1 contains a first electrode 2, a second electrode 3, a third semiconductor region 6, and a semiconductor region 7. As shown in Figure 3B, the second layer L2 contains a first semiconductor region 4, a third semiconductor region 6, and a semiconductor region 7. As shown in Figure 3C, the third layer L3 contains a plurality of second semiconductor regions 5 and a third semiconductor region 6.

[0055] As shown in Figure 3C, the multiple second semiconductor regions 5 are arranged separately within the same third layer L3.

[0056] Figure 4 is an enlarged cross-sectional view of the vicinity of the PN junction region H in Figure 2A. Figure 4 shows the first semiconductor region 4 and the second semiconductor region 5 that form the avalanche region, the third semiconductor region 6 arranged around them, the first electrode 2 connected to the first semiconductor region 4, and the interface region Ha on the light incident surface side of the first semiconductor region 4 and the third semiconductor region 6.

[0057] In pixel 1, a potential gradient is formed such that the potential decreases sharply from the second semiconductor region 5 to the first semiconductor region 4.

[0058] Furthermore, Figure 4 illustrates the region G within the avalanche region where the electric field is strongest. As shown in Figure 1, the multiple second semiconductor regions 5 are arranged so that, in a plan view, they touch a part of the outer periphery of the first semiconductor region 4, but do not touch the entire outer periphery of the first semiconductor region 4. This allows region G to be brought closer to the PN junction region H. In other words, by having the second semiconductor regions 5 touch only a part of the outer periphery of the first semiconductor region 4, the problem of the region G, where the electric field is strongest, shifting to, for example, the interior of the first semiconductor region 4 is eliminated. When region G is located in the PN junction region H, the DCR can be improved and noise characteristics can be enhanced compared to when region G is shifted to the first semiconductor region 4.

[0059] Furthermore, in the example shown in Figure 1, multiple second semiconductor regions 5 are arranged in a cross shape extending in the direction of opposite sides of the pixel 1 in a plan view. In this case, when the (100) plane of the substrate (silicon substrate) 11 is used, the strong electric field in the PN junction region H faces the (110) plane, thus further improving the DCR.

[0060] Figure 5A shows a photodetector 10 according to the first embodiment of the present disclosure. The photodetector 10 can be made up of, for example, a laminated substrate formed by stacking a plurality of substrates (chips). The photodetector 10 in Figure 5A has a two-layer structure formed by bonding a first substrate 21 and a second substrate 22 in that order. These substrates are joined by vias or the like. In addition to vias, the first substrate 21 and the second substrate 22 may also be joined by Cu-Cu bonding or bumps.

[0061] For example, a pixel array section 25 is arranged on the first substrate 21. The pixel array section 25 has a plurality of pixels 1. The plurality of pixels 1 in the pixel array section 25 are arranged, for example, in a two-dimensional direction. The first substrate 21 may include a substrate 11 such as that shown in Figure 2A.

[0062] For example, a logic circuit 26 is arranged on the second substrate 22. The logic circuit 26 performs predetermined signal processing based on photons detected by multiple pixels 1. Predetermined signal processing includes, for example, image data generation processing or histogram generation.

[0063] Figure 5B shows a modified photodetector 10a. The photodetector 10a in Figure 5B has a three-layer structure formed by bonding a first substrate 21, a second substrate 22, and a third substrate 23 in that order. For example, a pixel array section 25 is arranged on the first substrate 21. For example, a plurality of pixel circuits 27 are arranged on the second substrate 22. A logic circuit 26 is arranged on the third substrate 23. The pixel circuits 27 include, for example, a pulse generation circuit that outputs a pulse signal based on the voltage fluctuation when a pixel 1 detects a photon, and a counter that measures the number of photons detected by the pixel 1.

[0064] Furthermore, the components placed on each chip are not limited to those described above. The light detection device 10 may also be composed of four or more stacked chips, or it may be composed of a single flat chip. In addition, at least a portion of the logic circuit 26 may be placed outside the light detection device 10.

[0065] Figure 6 shows the equivalent resistance inside a pixel 1 according to the first embodiment of the present disclosure. An equivalent resistance R1 is formed between a first semiconductor region 4 and a second semiconductor region 5, and equivalent resistances R2 and R3 are formed in series between the first electrode 2 and the third semiconductor region 6 above it. The second semiconductor region 5 is electrically connected to the second electrode 3. The voltage V1 of equivalent resistance R1 corresponds to the multiplication gradient between the first semiconductor region 4 and the second semiconductor region 5. The voltage V2 of equivalent resistance R2 corresponds to the transfer gradient within the third semiconductor region 6. The voltage V3 of equivalent resistance R3 corresponds to the multiplication gradient between the third semiconductor region 6 and the first semiconductor region 4.

[0066] Figure 7 is an equivalent circuit diagram of the equivalent resistors R1, R2, and R3 in Figure 6. Equivalent resistor R1 is connected between the first electrode 2 (Vcathode) and the second electrode 3 (Vanode). Equivalent resistors R2 and R3, which are connected in series, are connected between the first electrode 2 and the second electrode 3.

[0067] As shown in Figures 6 and 7, the voltage applied between the first electrode 2 and the second electrode 3 is directly applied across the equivalent resistor R1. Therefore, the voltage V1 applied across the equivalent resistor R1 can be increased without increasing the voltage level applied between the first electrode 2 and the second electrode 3. Thus, the voltage level applied between the first electrode 2 and the second electrode 3 can be reduced, and power consumption can be reduced.

[0068] Figure 8 is a longitudinal cross-sectional view of a pixel 100 according to the first comparative example. Pixel 100 has a second semiconductor region 101 that has a different shape from the second semiconductor region 5 in Figure 2A. Pixel 100 differs from pixel 1 in Figure 2A, etc., in that the second semiconductor region 101 is arranged to cover the first semiconductor region 4 in a plan view. In the first comparative example, an avalanche region is formed in the region (PN junction region H) where the second semiconductor region 101 and the first semiconductor region 4 are in surface contact.

[0069] In pixel 100, the second semiconductor region 101 is positioned to face the substrate 11. Therefore, the avalanche region (PN junction region H) of pixel 1 is formed to face the substrate 11. The region G within the avalanche region that has the strongest electric field is formed, for example, in the PN junction region H of the first semiconductor region 4 and the second semiconductor region 101.

[0070] Figure 9 is an enlarged cross-sectional view of the vicinity of the PN junction region H in Figure 8. Pixel 100 has a steep potential gradient in the depth direction of the semiconductor substrate (vertical direction in Figure 9). On the other hand, there is no steep potential gradient in the planar direction of the semiconductor substrate (horizontal direction in Figure 9).

[0071] Figure 10 shows the equivalent resistance inside the pixel 100 according to the first comparative example. Figure 11 is the equivalent circuit diagram of the equivalent resistance in Figure 10. Equivalent resistances R101 and R102 are shown in Figures 10 and 11. The voltage V101 of equivalent resistance R101 corresponds to the transfer gradient in the third semiconductor region 6. The voltage V102 of equivalent resistance R102 corresponds to the multiplication gradient between the second semiconductor region 101 and the first semiconductor region 4.

[0072] The pixel 100 in the first comparative example does not have the second semiconductor region 5 in Figure 2A. Therefore, the equivalent circuit diagram shown in Figure 10 does not have an equivalent resistance corresponding to the equivalent resistance R1 in Figure 6.

[0073] In the first comparative example, there is no equivalent resistance corresponding to the equivalent resistance R1 in Figure 6, so a multiplication gradient due to the equivalent resistance R1 is not formed. Therefore, in the first comparative example, in order to perform the desired charge multiplication between the second semiconductor region 101 and the first semiconductor region 4, it is necessary to apply a high voltage between the first electrode 2 and the second electrode 3, which increases power consumption.

[0074] In contrast, the pixel 1 according to the first embodiment of this disclosure can perform charge multiplication even when the power supply voltage between the first electrode 2 and the second electrode 3 is lower than that of the pixel 100 according to the first comparative example, and can reduce power consumption compared to the first comparative example.

[0075] Next, the pixel 200 relating to the second comparative example will be described. Figure 12 is a plan view of the pixel 200 relating to the second comparative example. More specifically, Figure 12 is a plan view of the pixel 200 looking downwards from a predetermined height. The cross-sectional view in the direction of line A-A in Figure 12 is the same as that in Figure 2A.

[0076] Figure 13 is a cross-sectional view of pixel 200 in the E-E direction (see Figure 2A) according to the second comparative example. The cross-sectional views of pixel 200 in the C-C direction and the D-D direction according to the second comparative example are the same as those in Figures 3A and 3B.

[0077] Pixel 200 has a second semiconductor region 201 corresponding to the second semiconductor region 5 in Figure 2A. As shown in Figure 13, the second semiconductor region 201 is located in the third layer L3 of the pixel 200 and has a hole in its center. As shown in Figure 12, the first semiconductor region 4 is located in the hole in a layer different from the third layer L3 (specifically, the second layer L2).

[0078] The second semiconductor region 201 is arranged to surround the first semiconductor region 4 in a plan view. In other words, the pixel 200 differs from pixel 1 in Figure 1 in that the second semiconductor region 201 is in contact with the entire outer periphery of the first semiconductor region 4 in a plan view.

[0079] Figure 14 is an enlarged cross-sectional view of the PN junction region H in the pixel 200 according to the second comparative example. Figure 14 shows the region G in the avalanche region where the electric field is strongest. As described above, the second semiconductor region 201 is arranged to be in contact with the entire outer periphery of the first semiconductor region 4 in a plan view. In the pixel 200, the potential of the second semiconductor region 201 strongly influences the formation position of region G. As a result, region G of the pixel 200 is formed in a position shifted from the PN junction region H of the first semiconductor region 4 and the second semiconductor region 201 into the interior of the first semiconductor region 4.

[0080] In pixel 200, region G is formed inside the first semiconductor region 4, which is a highly defective region with a high impurity concentration, resulting in a deterioration of DCR.

[0081] In contrast, in pixel 1 of Figure 1, the structure is such that multiple second semiconductor regions 5 do not touch the entire outer periphery of the first semiconductor region 4 in a plan view, thereby allowing adjustment of the potential gradient between the first semiconductor region 4 and the second semiconductor region 5. In pixel 1, region G can be formed in the PN junction region H of the first semiconductor region 4 and the second semiconductor region 5. As a result, pixel 1 can improve DCR and noise characteristics compared to pixel 200.

[0082] Figure 12 illustrates the hole paths K201 and K202 generated by avalanche multiplication. In pixel 200, holes are transported to the second electrode 3 via the second semiconductor region 201. Within the second semiconductor region 201, there may be hole paths with different path lengths. For example, there may be a path K201 that goes linearly from the avalanche region to the second electrode 3, and a path K202 that detours from the avalanche region to the side wall of pixel 200 before going to the second electrode 3.

[0083] In other words, there is variation in the path length through which holes pass in pixel 200. Therefore, variations in quench characteristics are likely to occur in pixel 200. Note that the above-mentioned variations in quench characteristics can also occur in pixel 100 in the first comparative example in Figure 8.

[0084] In contrast to pixel 100 in Figure 8 and pixel 200 in Figure 12, pixel 1 in Figure 1 can equalize the path lengths of the multiple paths K1 through which holes pass. As a result, variations in quench characteristics can be suppressed compared to pixel 200, etc.

[0085] As described above, the photodetector 10 according to the first embodiment of this disclosure has a first semiconductor region 4 that forms an avalanche region in a PN junction region H, and a plurality of second semiconductor regions 5. The plurality of second semiconductor regions 5 are arranged on a different layer from the first semiconductor region 4. Furthermore, the plurality of second semiconductor regions 5 are arranged so as to be in contact with a part of the outer periphery of the first semiconductor region 4 in a plan view, but not in contact with the entire outer periphery of the first semiconductor region 4.

[0086] In the photodetector 10, by structuring the multiple second semiconductor regions 5 so that they do not touch the entire outer periphery of the first semiconductor region 4, the potential gradient can be adjusted, preventing the region G with the strongest electric field from forming inside the first semiconductor region 4 or the second semiconductor region 5. This improves the DCR.

[0087] Furthermore, when multiple second semiconductor regions 5 are arranged to form a straight line extending in the direction of opposite sides of the pixel 1, using a Si(100) substrate for the substrate 11 makes it possible to direct the strong electric field of the PN junction region H to (110). This improves the DCR.

[0088] Furthermore, in the photodetector 10, by arranging the second electrode 3 at the four corners of the pixel 1 and the first electrode 2 at the center of the pixel 1, the distance between the second electrode 3 and the first electrode 2 can be increased in a plan view. This reduces the electric field between the first electrode 2 and the second electrode 3 on the surface of the substrate 11, further improving the DCR.

[0089] Furthermore, the photodetector 10 can equalize the path length of the hole transport path from the avalanche region to the second electrode 3. This suppresses variations in quench characteristics, such as variations in breakdown voltage and variations in the timing of avalanche multiplication stopping.

[0090] The light detection device 10 can improve noise characteristics by improving the DCR and suppressing variations in quench characteristics.

[0091] Furthermore, in the photodetector 10, the applied voltage between the first electrode 2 and the second electrode 3 can be applied almost unchanged to the avalanche region formed near the PN junction region between the first semiconductor region 4 and the second semiconductor region 5, enabling charge multiplication with minimal voltage loss. Therefore, charge multiplication can be performed even with a low voltage applied between the first electrode 2 and the second electrode 3, reducing power consumption compared to the first comparative example.

[0092] (Second Embodiment) Various modifications are possible for the planar configuration of the pixel 1. Figure 15 is a plan view of a pixel 1a according to the second embodiment of this disclosure, viewed from below a predetermined height. In the pixel 1a of Figure 15, a plurality of second electrodes 3 are arranged, for example, at the midpoints of each side of the rectangular pixel 1a. As a result, the pixel 1a has a configuration in which the second semiconductor region 5 is arranged on a plurality of straight lines connecting the first electrode 2 and the plurality of second electrodes 3.

[0093] Figure 16A is a longitudinal cross-sectional view of pixel 1a in Figure 15 along the A-A line. Figure 16A shows a cross-section of the second electrode 3 and the second semiconductor region 5. Figure 16B is a longitudinal cross-sectional view of pixel 1a in Figure 15 along the B-B line.

[0094] Figure 15 illustrates the charge path K2 generated by avalanche multiplication. As shown in Figure 15, the first electrode 2, the second electrode 3, and the second semiconductor region 5 are aligned in a straight line, allowing the path length of path K2 to be shortened compared to path K1 in Figure 1. This further reduces the variation in quench characteristics compared to pixel 1 in Figure 1. In addition, it reduces voltage fluctuations during photon detection at pixel 1a, thereby reducing power consumption.

[0095] Figure 17 is a plan view of the first modified pixel 1b, looking downwards from a predetermined height. In the pixel 1b shown in Figure 17, similar to the pixel 1 in Figure 1, second electrodes 3 are arranged at the four corners of the rectangular pixel 1b. In addition, second semiconductor regions 5 are arranged on multiple straight lines connecting the first electrode 2 and the multiple second electrodes 3. That is, the multiple second semiconductor regions 5 are arranged to form an X shape on the diagonal of the pixel 1b.

[0096] In pixel 1b of Figure 17, similar to pixel 1 of Figure 1, the distance between the second electrode 3 and the first electrode 2 in a plan view can be increased, improving the DCR. Also, in pixel 1b, similar to pixel 1a of Figure 15, the charge path K3 generated by avalanche multiplication can be shortened, further reducing variations in quench characteristics and voltage fluctuations during photon detection.

[0097] In pixel 1b of Figure 17, for example, a Si(100) substrate can be used as the substrate 11, which is a substrate rotated 45 degrees in the plane direction of Figure 17 (a substrate with a 45-degree notch). This makes it possible to direct the strong electric field of the PN junction region H in the (110) direction, that is, towards the second electrode 3 when viewed from the PN junction region H, and improves the DCR, similar to pixel 1 in Figure 1.

[0098] Figure 18 is a plan view of a pixel 1c according to a second modified example, looking downwards from a predetermined height. In the pixel 1c shown in Figure 18, the first electrode 2 is located at one of the four corners of the pixel 1c, and the second electrode 3 is located at one of the four diagonal corners of the pixel 1c. The first semiconductor region 4 is arranged to cover the first electrode 2. The second semiconductor region 5 is located on a straight line connecting the first electrode 2 and the second electrode 3.

[0099] Figure 19 is a longitudinal cross-sectional view of pixel 1c in Figure 18 along the F-F line. Figure 19 shows cross-sections of the first electrode 2, the second electrode 3, the first semiconductor region 4, and the second semiconductor region 5.

[0100] In pixel 1c of Figures 18 and 19, the distance between the second electrode 3 and the first electrode 2 in a plan view can be increased even further than in pixel 1 of Figure 1. This allows for further improvement of DCR.

[0101] Pixel 1c in Figure 19 has a configuration in which the first semiconductor region 4 and the second semiconductor region 5 are joined at one corner. In this specification, pixel 1c is also called a one-point contact type pixel. In contrast, pixel 1 in Figure 1 is also called a four-point contact type pixel.

[0102] The number of junctions between the first semiconductor region 4 and the second semiconductor region 5 can be arbitrarily adjusted. Increasing the number of junctions allows for a larger avalanche region, thereby improving the photon detection sensitivity. Conversely, decreasing the number of junctions reduces the avalanche region, improving the DCR due to the tunneling effect.

[0103] Figure 20 is a plan view of a pixel 1d according to the third modified example, looking downwards from a predetermined height. The pixel 1d in Figure 20 is a two-point contact type pixel in which a first semiconductor region 4 and two second semiconductor regions 5 are joined. Note that the second electrode 3 and semiconductor region 7 are not shown in Figure 20.

[0104] Figure 21 is a plan view of a pixel 1e according to a fourth modified example, looking downwards from a predetermined height. The pixel 1e in Figure 21 has an annular second electrode 3 arranged along the outer circumference of the pixel 1e. This makes it possible to reduce the resistance between the first electrode 2 and the second electrode 3 compared to the pixel 1 in Figure 1.

[0105] In Figure 1, pixel 1, etc., shows a rectangular (for example, square) pixel configuration in a plan view. The planar shape of the pixel can be arbitrarily adjusted. Figure 22 is a plan view of pixel 1f according to the fifth modified example, looking down from a predetermined height. Pixel 1f has a polygonal shape (for example, octagon).

[0106] In pixel 1f, the second semiconductor region 5 is positioned on a straight line connecting the first electrode 2 and the second electrode 3. This shortens the charge path (not shown) generated by avalanche multiplication, thereby suppressing variations in quench characteristics.

[0107] In addition to the above, pixel 1 may be a polygon with more than one triangle, a circle, or an ellipse when viewed from above. Furthermore, if pixel 1 is a polygon when viewed from above, the second electrode 3 may be placed at least a portion of each corner.

[0108] As described above, various planar configurations are possible for the pixel according to the second embodiment of this disclosure. In a configuration in which the second semiconductor region 5 is arranged on a straight line connecting the first electrode 2 and the second electrode 3, variations in quench characteristics can be suppressed more effectively than in the pixel 1 of Figure 1. By arranging the second semiconductor region 5 in an X shape, it is possible to achieve both the suppression of variations in quench characteristics and the improvement of DCR by electric field relaxation between the first electrode 2 and the second electrode 3 on the surface of the substrate 11.

[0109] (Third Embodiment) Figure 23 is a longitudinal cross-sectional view of a pixel 1g according to the third embodiment of the present disclosure. Figure 24 is a transverse cross-sectional view of the pixel 1g in Figure 23 along the E-E line. The pixel 1g has a fourth semiconductor region 31 which is located on the same layer as the second semiconductor region 5 (i.e., the third layer L3). The fourth semiconductor region 31 is located such that it overlaps with at least a portion of the first semiconductor region 4 in a plan view.

[0110] The fourth semiconductor region 31 is a region of second conductivity type (e.g., p-type) with a lower impurity concentration than the second semiconductor region 5. Alternatively, the fourth semiconductor region 31 may be a region of first conductivity type (e.g., n-type) with a lower impurity concentration than the first semiconductor region 4.

[0111] By providing the fourth semiconductor region 31, the power consumption reduction effect described in Figures 6 and 7 can be more easily achieved. The fourth semiconductor region 31 may also be applied to the pixel 1a, etc., according to the second embodiment of this disclosure.

[0112] (Fourth Embodiment) Figure 25 is a longitudinal cross-sectional view of a pixel 1h according to the fourth embodiment of the present disclosure. Figure 26A is a transverse cross-sectional view of the pixel 1h in Figure 25 along the line C-C. Figure 26B is a transverse cross-sectional view of the pixel 1h in Figure 25 along the line D-D.

[0113] Pixel 1h has a fifth semiconductor region 41 which is located on the same layer as the first semiconductor region 4. The fifth semiconductor region 41 is located, for example, on the first layer L1 and the second layer L2. The fifth semiconductor region 41 is located such that it overlaps with at least a portion of the second semiconductor region 5 in a plan view.

[0114] The second semiconductor region 5 is a region of the first conductivity type (e.g., n-type) with a lower impurity concentration than the first semiconductor region 4.

[0115] The fifth semiconductor region 41 is positioned to prevent impurities forming the second semiconductor region from entering the substrate 11 side surface (also referred to as the Well proximity effect in this specification) during the formation process of the second semiconductor region 5, more specifically, during the impurity injection process.

[0116] When impurities of the first conductivity type diffuse from the second semiconductor region 5, a high electric field is formed on the surface of the substrate 11, and the DCR deteriorates. The fifth semiconductor region 41 can improve the DCR of the pixel 1h by preventing impurity diffusion from the second semiconductor region 5.

[0117] Figure 27 is a longitudinal cross-sectional view of a modified pixel 1i. Pixel 1i has an insulating region (first insulating region) 42 instead of a fifth semiconductor region 41. The insulating region 42, like the fifth semiconductor region 41, can prevent impurity diffusion in the second semiconductor region 5 and improve the DCR.

[0118] The pixel 1i in Figure 27 may have a configuration that includes both an insulating region 42 and a fifth semiconductor region 41. The insulating region 42 and the fifth semiconductor region 41 may be applied to pixels 1a, etc., according to the second and third embodiments of this disclosure.

[0119] (Fifth Embodiment) Figure 28 is a longitudinal cross-sectional view of a pixel 1j according to the fifth embodiment of the present disclosure. Pixel 1j differs from pixel 1 in Figure 2A, etc., in that the first electrode 2 is embedded in the substrate 11. The substrate 11 in Figure 28 has an interlayer insulating film (second insulating region) 51 arranged to surround the first electrode 2.

[0120] In pixel 1j of Figure 28, the interlayer insulating film 51 protects the first electrode 2 from the effects of impurity diffusion in the second semiconductor region 5. This improves the DCR, similar to pixel 1h in Figure 25.

[0121] (Sixth Embodiment) Figure 29 is a longitudinal cross-sectional view of a pixel 1k according to the sixth embodiment of the present disclosure. The pixel 1k has a stepped inter-pixel isolation region 61. The second electrode 3 in Figure 29 is arranged on the inter-pixel isolation region 61. As a result, in the pixel 1k, the layer on which the first electrode 2 is arranged (fourth layer L4) and the layer on which the second electrode 3 is arranged (fifth layer L5) are different.

[0122] The second electrode 3 can be placed, for example, on the layer in which the second semiconductor region 5 is arranged.

[0123] In pixel 1k, the distance between the first electrode 2 and the second electrode 3 can be increased compared to pixel 1 in Figure 1. This improves the DCR.

[0124] Furthermore, in pixel 1k of Figure 29, the second electrode 3 can be positioned closer to the PN junction region H of the first semiconductor region 4 and the second semiconductor region 5 than in pixel 1 of Figure 1. This shortens the path through which holes pass between the avalanche region and the second electrode 3, further suppressing variations in quench characteristics.

[0125] (Seventh Embodiment) In the first to sixth embodiments, an example was shown in which the corners of the first semiconductor region 4 and the second semiconductor region 5 are joined together. In the following embodiments, the first semiconductor region 4 and the second semiconductor region 5 are characterized by having a joining interface.

[0126] Figure 30 is a plan view of a pixel 71 viewed from a predetermined height below according to the seventh embodiment of the present disclosure. Figure 31A is a longitudinal cross-sectional view of the pixel 71 in Figure 30 along the line A-A. Figure 31B is a longitudinal cross-sectional view of the pixel 71 in Figure 30 along the line B-B. Figure 31B shows a cross-section of the second electrode 3.

[0127] As shown in Figures 31A and 31B, pixel 71 differs from pixel 1 in Figure 1 in that at least a portion of the second semiconductor region 5 is located on the same layer as the first semiconductor region 4.

[0128] As shown in Figures 31A and 31B, the pixel 71 has the same height on the light incident surface side of the first semiconductor region 4 and the second semiconductor region 5. The junction interface between the first semiconductor region 4 and the second semiconductor region 5 is a PN junction region H. In the PN junction region H in Figures 31A and 31B, an electric field vector is formed in the planar direction of the substrate 11.

[0129] In pixel 71, the second semiconductor region 5 is positioned in accordance with the position of the side surface of the first semiconductor region 4. As a result, the second semiconductor region 5 is positioned at a height closer to the substrate 11 than in the first to sixth embodiments, which reduces the dead region A2 where photons cannot be detected, and thus improves the photon detection sensitivity.

[0130] Furthermore, not limited to the examples in Figures 31A and 31B, if at least a portion of the second semiconductor region 5 is positioned at the same height as at least a portion of the first semiconductor region 4, the dead region A2 can be reduced.

[0131] Figure 32 is a cross-sectional view of pixel 71 in Figures 31A and 31B along the line E-E. Note that the cross-sectional views of pixel 71 in Figures 31A and 31B along the lines C-C and D-D are the same as those in Figures 3A and 3B.

[0132] The third layer L3 in Figure 32 has a first semiconductor region 4 and a second semiconductor region 5. The first semiconductor region 4 is located in the center of the pixel 71. The second semiconductor region 5 is located so as to be in contact with the entire outer periphery of the first semiconductor region 4 in a plan view.

[0133] Figure 33 is a cross-sectional view of a pixel in the E-E direction according to the first modified example. The third layer L3 in Figure 33 has a first semiconductor region 4, a second semiconductor region 5, and a third semiconductor region 6. Figure 33 differs from the configuration in Figure 32 in that the second semiconductor region 5 is arranged to touch a part of the outer periphery of the first semiconductor region 4 in a plan view, but not the entire outer periphery of the first semiconductor region 4.

[0134] In the configuration shown in Figure 33, similar to pixel 1 in Figure 1, the path length of the hole transport path can be made uniform, thereby suppressing variations in quench characteristics. Furthermore, the strongest electric field region can be prevented from forming inside the first semiconductor region 4 or the second semiconductor region 5, thereby improving the DCR.

[0135] Figure 33 shows an example in which multiple second semiconductor regions 5 are arranged to form a cross shape. Note that the multiple second semiconductor regions 5 may also be arranged to form an X shape, as in Figure 17, or they may be arranged in a straight line, as in Figure 20. Furthermore, the second electrode 3 may be arranged on multiple straight lines connecting the first electrode 2 and the multiple second semiconductor regions 5, or it may be placed at a position further away from the first electrode 2 (for example, at the four corners of the pixel 71).

[0136] Figure 34 is a longitudinal cross-sectional view of a pixel 71a according to a second modified example. The pixel 71a in Figure 34 is a one-point contact type pixel in which the first semiconductor region 4 and the second semiconductor region 5 are joined together on one surface. The planar configuration of the pixel 71a is the same as in Figure 14. In the pixel 71a, the distance between the second electrode 3 and the first electrode 2 can be increased in a planar view, thereby improving the DCR.

[0137] Figure 35 is a plan view of the pixel 71b according to the third modified example, looking downward from a predetermined height. Similar to the pixel 1e in Figure 17, the pixel 71b has an annular second electrode 3 arranged along the outer circumference of the pixel 71b. This reduces the resistance between the first electrode 2 and the second electrode 3.

[0138] Figure 36 is a longitudinal cross-sectional view of a pixel 71c according to the fourth modified example. Similar to the pixel 1k in Figure 29, the pixel 71c increases the distance between the first electrode 2 and the second electrode 3 by an inter-pixel separation region 61. In addition, the second electrode 3 is positioned close to the PN junction region H of the first semiconductor region 4 and the second semiconductor region 5. As a result, similar to the pixel 1k in Figure 29, improvement of DCR and suppression of variations in quench characteristics can be achieved.

[0139] As another variation, the pixel 71 may be composed of a polygon with more than one triangle, a circle, or an ellipse in plan view. The second electrode 3 may be placed at least a part of each corner of the polygon, or at the midpoint of each side, etc. In the case of the pixel 71, the fifth semiconductor region 41 in Figure 25 or the insulating region 42 in Figure 27 may be placed between the second semiconductor region 5 and the substrate 11. Also, similar to Figure 28, the second electrode 3 may be embedded in the interlayer insulating film 51.

[0140] Thus, in the pixel 71 according to the seventh embodiment of this disclosure, by positioning the second semiconductor region 5 in accordance with the side surface of the first semiconductor region 4, a junction interface (PN junction region H) can be formed between the first semiconductor region 4 and the second semiconductor region 5, and the insensitive region A2 in which photons cannot be detected can be reduced, thereby improving the noise characteristics by improving the photon detection sensitivity.

[0141] (Eighth Embodiment) Figure 37 is a longitudinal cross-sectional view of a pixel 71d according to the eighth embodiment of the present disclosure. The pixel 71d in Figure 37 has a fourth semiconductor region 81 which is positioned on the light incident surface side of the second semiconductor region 5 and which overlaps with at least a part of the second semiconductor region 5 in a plan view. The fourth semiconductor region 81 is a first conductivity type (e.g., n-type) region with a lower impurity concentration than the first semiconductor region 4.

[0142] In pixel 71d, the fourth semiconductor region 81 can attract the charge e into the strong electric field (i.e., the PN junction region H).

[0143] Figure 38 is a longitudinal cross-sectional view of a pixel 71e according to one modification. The pixel 71e in Figure 38 has a fourth semiconductor region 81 and a fifth semiconductor region 82. The fifth semiconductor region 82 is located on the light incident surface side of the first semiconductor region 4 and is arranged so as to overlap with at least a part of the first semiconductor region 4 in a plan view. It is a region of second conductivity type (e.g., p-type) with a lower impurity concentration than the second semiconductor region 5. The fifth semiconductor region 82 can draw charge e into a strong electrolytic field, similar to the fourth semiconductor region 81. Note that the fourth semiconductor region 81 may be omitted in the pixel 71e.

[0144] Figure 39 is a cross-sectional view of the pixel 71e in Figure 38 in the G-G direction. In this specification, the G-G direction of the pixel 71e in Figure 38 is also referred to as the sixth layer L6. The sixth layer L6 is located closer to the light incident surface than the third layer L3. The sixth layer L6 has a fourth semiconductor region 81, a fifth semiconductor region 82, a third semiconductor region 6, and a semiconductor region 7.

[0145] Figure 39 shows the arrangement of the sixth layer L6 when multiple second semiconductor regions 5 are arranged in a cross shape, as shown in Figure 33. It is desirable that the fourth semiconductor region 81 be arranged so as to overlap the multiple second semiconductor regions 5 in a plan view. That is, if multiple second semiconductor regions 5 are arranged in a cross shape, it is desirable that multiple fourth semiconductor regions 81 be arranged in a cross shape as well.

[0146] (Ninth Embodiment) Figure 40 is a longitudinal cross-sectional view of a pixel 71f according to the ninth embodiment of the present disclosure. The pixel 71f in Figure 40 has a fourth semiconductor region 85 which is positioned on the light incident surface side of the first semiconductor region 4 and the second semiconductor region 5, and which overlaps with at least a portion of the first semiconductor region 4 and the second semiconductor region 5 in a plan view. The fourth semiconductor region 85 is a second conductivity type (e.g., p-type) region with a lower impurity concentration than the second semiconductor region 5.

[0147] Figure 41 is a cross-sectional view of pixel 71f in Figure 40 in the G-G direction. The sixth layer L6 shown in Figure 41 has a fourth semiconductor region 85 and a semiconductor region 7. The fourth semiconductor region 85 is, for example, arranged over the entire area surrounded by the semiconductor region 7.

[0148] In the pixel 71f shown in Figure 40, the fourth semiconductor region 85 can strengthen the electric field in the central part of the pixel 71f. This allows for a further improvement in the light detection sensitivity of the pixel 71f.

[0149] (Tenth Embodiment) Figure 42 is a block diagram showing the configuration of a distance measuring system 90 according to the tenth embodiment of the present disclosure. The distance measuring system 90 of Figure 42 can measure the distance of an object M. The distance measuring system 90 has a light-emitting device 91 and a distance measuring device 92. The distance measuring device 92 has a light detection device 10, a light emission timing control unit 93, a control unit 94, a time-of-flight detection unit 95, a histogram generation unit 96, and a distance detection unit 97.

[0150] The light emission timing control unit 93, the control unit 94, the time-of-flight detection unit 95, the histogram generation unit 96, and some or all of the distance detection unit 97 (hereinafter referred to as the distance measuring unit) may be arranged within the light detection device 10. For example, the distance measuring unit may be arranged in the logic circuit 26 shown in Figure 5A. Also, the light emission device 91 and the distance measuring device 92 may be arranged on the same semiconductor substrate (or a multilayer semiconductor substrate).

[0151] The light-emitting device 91 intermittently emits light pulses (TX: Transmitter exchange) signals toward object M. The light detection device 10 repeatedly receives reflected light pulses (RX: Received exchange) signals that are generated when the TX signal is reflected by object M.

[0152] The light-emitting device 91 has, for example, a plurality of light-emitting elements arranged in a two-dimensional direction. Furthermore, the light-emitting device 91 can adjust the pulse width and phase of the individual TX signals emitted by the plurality of light-emitting elements through the control of the light-emitting timing control unit 93.

[0153] The control unit 94 controls the light detection device 10 and the light emission timing control unit 93. For example, the control unit 94 generates a clock signal that synchronizes the light emission operation of the light emission device 91 with the light receiving operation of the light detection device 10.

[0154] The time of flight detection unit 95 detects the time of flight from when the light-emitting device 91 emits a TX signal until the light detection device 10 receives an RX signal. The histogram generation unit 96 generates a histogram classifying the frequency of RX signal reception for predetermined unit reception periods based on the time of flight repeatedly detected by the time of flight detection unit 95. The distance detection unit 97 detects the distance between the distance measuring system 90 and object M based on the generated histogram.

[0155] The photodetector 10 according to the first to ninth embodiments of this disclosure has high photon detection sensitivity. As a result, the distance measuring system 90 can measure distances with high accuracy even in distance measurements where the light intensity of the reflected light pulse signal tends to be low, such as measuring the distance to an object M located at a long distance. The photodetector 10 may be applied not only to the distance measuring system but also to an image processing system, etc.

[0156] (Application Examples) The technology disclosed herein can be applied to a variety of products. For example, the technology disclosed herein may be implemented as a device mounted on any type of mobile vehicle, such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, robots, construction machinery, or agricultural machinery (tractors).

[0157] Figure 43 is a block diagram showing a schematic configuration example of a vehicle control system 7000, which is an example of a mobile control system to which the technology described herein may be applied. The vehicle control system 7000 comprises a plurality of electronic control units connected via a communication network 7010. In the example shown in Figure 43, the vehicle control system 7000 comprises a drive system control unit 7100, a body system control unit 7200, a battery control unit 7300, an external information detection unit 7400, an internal information detection unit 7500, and an integrated control unit 7600. The communication network 7010 connecting these plurality of control units may be an in-vehicle communication network conforming to any standard such as CAN (Controller Area Network), LIN (Local Interconnect Network), LAN (Local Area Network), or FlexRay®.

[0158] Each control unit comprises a microcomputer that performs calculations according to various programs, a storage unit that stores programs executed by the microcomputer or parameters used in various calculations, and a drive circuit that drives various controlled devices. Each control unit is equipped with a network interface for communication with other control units via the communication network 7010, and a communication interface for communication with devices or sensors inside or outside the vehicle via wired or wireless communication. Figure 43 shows the functional configuration of the integrated control unit 7600, which includes a microcomputer 7610, a general-purpose communication interface 7620, a dedicated communication interface 7630, a positioning unit 7640, a beacon receiver 7650, an in-vehicle equipment interface 7660, an audio / image output unit 7670, an in-vehicle network interface 7680, and a storage unit 7690. Other control units similarly include a microcomputer, a communication interface, and a storage unit.

[0159] The drivetrain control unit 7100 controls the operation of devices related to the vehicle's drivetrain according to various programs. For example, the drivetrain control unit 7100 functions as a control device for generating driving force for the vehicle, such as an internal combustion engine or a drive motor; a driving force transmission mechanism for transmitting driving force to the wheels; a steering mechanism for adjusting the steering angle of the vehicle; and a braking device for generating braking force for the vehicle. The drivetrain control unit 7100 may also function as a control device such as an ABS (Antilock Brake System) or an ESC (Electronic Stability Control).

[0160] A vehicle state detection unit 7110 is connected to the drive system control unit 7100. The vehicle state detection unit 7110 includes, for example, a gyro sensor for detecting the angular velocity of the axial rotation motion of the vehicle body, an acceleration sensor for detecting the acceleration of the vehicle, or at least one of the sensors for detecting the amount of operation of the accelerator pedal, the amount of operation of the brake pedal, the steering angle of the steering wheel, the engine speed, or the rotational speed of the wheels. The drive system control unit 7100 performs calculation processing using the signals input from the vehicle state detection unit 7110 and controls the internal combustion engine, drive motor, electric power steering system, brake system, etc.

[0161] The body system control unit 7200 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 7200 functions as a control device for a keyless entry system, a smart key system, a power window system, or various lamps such as headlights, reverse lights, brake lights, turn signals, or fog lights. In this case, the body system control unit 7200 may receive radio waves transmitted from a portable device that replaces a key or signals from various switches. The body system control unit 7200 receives these radio waves or signals and controls the vehicle's door lock system, power window system, lamps, etc.

[0162] The battery control unit 7300 controls the secondary battery 7310, which is the power source for the drive motor, according to various programs. For example, the battery control unit 7300 receives information such as battery temperature, battery output voltage, or remaining battery capacity from the battery device equipped with the secondary battery 7310. The battery control unit 7300 uses these signals to perform calculations and controls the temperature of the secondary battery 7310 or the cooling device provided in the battery device.

[0163] The external information detection unit 7400 detects information from outside the vehicle equipped with the vehicle control system 7000. For example, at least one of the imaging unit 7410 and the external information detection unit 7420 is connected to the external information detection unit 7400. The imaging unit 7410 includes at least one of the following: a Time of Flight (ToF) camera, a stereo camera, a monocular camera, an infrared camera, and other cameras. The external information detection unit 7420 includes at least one of the following: an environmental sensor for detecting the current weather or climate, or an ambient information detection sensor for detecting other vehicles, obstacles, or pedestrians around the vehicle equipped with the vehicle control system 7000.

[0164] The environmental sensor may be at least one of the following: a raindrop sensor for detecting rain, a fog sensor for detecting fog, a sunshine sensor for detecting the degree of sunlight, and a snow sensor for detecting snowfall. The ambient information detection sensor may be at least one of the following: an ultrasonic sensor, a radar device, and a LIDAR (Light Detection and Ranging, Laser Imaging Detection and Ranging) device. These imaging unit 7410 and external information detection unit 7420 may be provided as independent sensors or devices, or as a device in which multiple sensors or devices are integrated.

[0165] Here, Figure 44 shows an example of the installation location of the imaging unit 7410 and the external information detection unit 7420. The imaging units 7910, 7912, 7914, 7916, and 7918 are installed, for example, at least one of the following locations on the vehicle 7900: the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the passenger compartment. The imaging unit 7910 installed on the front nose and the imaging unit 7918 installed on the upper part of the windshield inside the passenger compartment mainly acquire images of the front of the vehicle 7900. The imaging units 7912 and 7914 installed on the side mirrors mainly acquire images of the sides of the vehicle 7900. The imaging unit 7916 installed on the rear bumper or back door mainly acquires images of the rear of the vehicle 7900. The imaging unit 7918 installed on the upper part of the windshield inside the passenger compartment is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, or lanes.

[0166] Figure 44 shows an example of the imaging range of each imaging unit 7910, 7912, 7914, and 7916. Imaging range a shows the imaging range of imaging unit 7910 located on the front nose, imaging ranges b and c show the imaging ranges of imaging units 7912 and 7914 located on the side mirrors, respectively, and imaging range d shows the imaging range of imaging unit 7916 located on the rear bumper or back door. For example, by superimposing the image data captured by imaging units 7910, 7912, 7914, and 7916, an overhead view image of the vehicle 7900 can be obtained.

[0167] The external information detection units 7920, 7922, 7924, 7926, 7928, and 7930, which are installed on the front, rear, sides, corners, and the upper part of the windshield inside the vehicle 7900, may be, for example, ultrasonic sensors or radar devices. The external information detection units 7920, 7926, and 7930, which are installed on the front nose, rear bumper, back door, and the upper part of the windshield inside the vehicle 7900, may be, for example, LIDAR devices. These external information detection units 7920 to 7930 are mainly used for detecting preceding vehicles, pedestrians, or obstacles.

[0168] Returning to Figure 43, the explanation continues. The external information detection unit 7400 causes the imaging unit 7410 to capture images of the area outside the vehicle and receives the captured image data. The external information detection unit 7400 also receives detection information from the connected external information detection unit 7420. If the external information detection unit 7420 is an ultrasonic sensor, radar device, or LIDAR device, the external information detection unit 7400 emits ultrasonic waves or electromagnetic waves and receives information on the received reflected waves. Based on the received information, the external information detection unit 7400 may perform object detection processing such as detecting people, vehicles, obstacles, signs, or characters on the road surface, or distance detection processing. Based on the received information, the external information detection unit 7400 may perform environmental recognition processing to recognize rainfall, fog, or road surface conditions. Based on the received information, the external information detection unit 7400 may calculate the distance to an object outside the vehicle.

[0169] Furthermore, the external information detection unit 7400 may perform image recognition processing or distance detection processing to recognize people, vehicles, obstacles, signs, or characters on the road surface based on the received image data. The external information detection unit 7400 may perform distortion correction or alignment processing on the received image data, and may also synthesize image data captured by different imaging units 7410 to generate an overhead view image or a panoramic image. The external information detection unit 7400 may also perform viewpoint transformation processing using image data captured by different imaging units 7410.

[0170] The in-vehicle information detection unit 7500 detects information inside the vehicle. The in-vehicle information detection unit 7500 is connected to, for example, a driver status detection unit 7510 that detects the driver's state. The driver status detection unit 7510 may include a camera that images the driver, a biosensor that detects the driver's biometric information, or a microphone that collects sounds inside the vehicle. The biosensor is installed, for example, on the seat or steering wheel and detects the biometric information of an occupant sitting in the seat or a driver holding the steering wheel. Based on the detection information input from the driver status detection unit 7510, the in-vehicle information detection unit 7500 may calculate the driver's level of fatigue or concentration, or determine whether the driver is dozing off. The in-vehicle information detection unit 7500 may perform processing such as noise cancellation on the collected audio signals.

[0171] The integrated control unit 7600 controls the overall operation of the vehicle control system 7000 according to various programs. An input unit 7800 is connected to the integrated control unit 7600. The input unit 7800 is implemented by a device that can be operated by the passenger, such as a touch panel, buttons, a microphone, a switch, or a lever. The integrated control unit 7600 may also receive data obtained by voice recognition of voice input from the microphone. The input unit 7800 may be, for example, a remote control device using infrared or other radio waves, or an externally connected device such as a mobile phone or PDA (Personal Digital Assistant) that is compatible with the operation of the vehicle control system 7000. The input unit 7800 may be, for example, a camera, in which case the passenger can input information by gesture. Alternatively, data obtained by detecting the movement of a wearable device worn by the passenger may be input. Furthermore, the input unit 7800 may include, for example, an input control circuit that generates an input signal based on the information input by the passenger using the above input unit 7800 and outputs it to the integrated control unit 7600. Passengers and others can input various data or instruct the vehicle control system 7000 to perform processing operations by operating this input unit 7800.

[0172] The storage unit 7690 may include a ROM (Read Only Memory) for storing various programs executed by a microcomputer, and a RAM (Random Access Memory) for storing various parameters, calculation results, or sensor values. The storage unit 7690 may also be implemented using a magnetic storage device such as an HDD (Hard Disk Drive), a semiconductor storage device, an optical storage device, or a magneto-optical storage device.

[0173] The general-purpose communication interface 7620 is a general-purpose communication interface that mediates communication between the external environment 7750 and various devices present in the external environment 7750. The general-purpose communication interface 7620 may implement cellular communication protocols such as GSM (Global System of Mobile communications), WiMAX (registered trademark), LTE (registered trademark) (Long Term Evolution), or LTE-A (LTE-Advanced), or other wireless communication protocols such as wireless LAN (also known as Wi-Fi (registered trademark)) and Bluetooth (registered trademark). The general-purpose communication interface 7620 may connect, for example, to devices (e.g., application servers or control servers) located on an external network (e.g., the Internet, a cloud network, or a carrier-specific network) via a base station or access point. Furthermore, the general-purpose communication I / F 7620 may connect to terminals located near the vehicle (for example, terminals belonging to the driver, pedestrians, or shops, or MTC (Machine Type Communication) terminals) using, for example, P2P (Peer To Peer) technology.

[0174] The dedicated communication interface 7630 is a communication interface that supports communication protocols developed for use in vehicles. The dedicated communication interface 7630 may implement standard protocols such as WAVE (Wireless Access in Vehicle Environment), DSRC (Dedicated Short Range Communications), or cellular communication protocols, which are combinations of lower-layer IEEE 802.11p and upper-layer IEEE 1609. The dedicated communication interface 7630 typically performs V2X communication, a concept that includes one or more of the following: vehicle-to-vehicle communication, vehicle-to-infrastructure communication, vehicle-to-home communication, and vehicle-to-pedestrian communication.

[0175] The positioning unit 7640 performs positioning by receiving, for example, GNSS (Global Navigation Satellite System) signals from GNSS satellites (for example, GPS signals from GPS (Global Positioning System) satellites) and generates location information including the vehicle's latitude, longitude, and altitude. The positioning unit 7640 may also determine its current location by exchanging signals with a wireless access point, or it may acquire location information from a terminal such as a mobile phone, PHS, or smartphone that has a positioning function.

[0176] The beacon receiver 7650 receives radio waves or electromagnetic waves transmitted from, for example, a radio station installed on a road, and acquires information such as the current location, traffic congestion, road closures, or travel time. The functions of the beacon receiver 7650 may also be included in the dedicated communication interface 7630 described above.

[0177] The in-vehicle equipment interface 7660 is a communication interface that mediates connections between the microcomputer 7610 and various in-vehicle equipment 7760 located inside the vehicle. The in-vehicle equipment interface 7660 may establish a wireless connection using wireless communication protocols such as wireless LAN, Bluetooth®, NFC (Near Field Communication), or WUSB (Wireless USB). Furthermore, the in-vehicle equipment I / F 7660 may establish a wired connection such as USB (Universal Serial Bus), HDMI (High-Definition Multimedia Interface), or MHL (Mobile High-definition Link) via connection terminals (and, if necessary, cables) not shown. The in-vehicle equipment 7760 may include, for example, at least one of the following: a mobile device or wearable device owned by a passenger, or an information device brought into or installed in the vehicle. The in-vehicle equipment 7760 may also include a navigation device that searches for a route to any destination. The in-vehicle equipment I / F 7660 exchanges control signals or data signals with these in-vehicle equipment 7760s.

[0178] The in-vehicle network interface 7680 is an interface that mediates communication between the microcomputer 7610 and the communication network 7010. The in-vehicle network interface 7680 transmits and receives signals and other data in accordance with a predetermined protocol supported by the communication network 7010.

[0179] The microcomputer 7610 of the integrated control unit 7600 controls the vehicle control system 7000 according to various programs based on information acquired via at least one of the general-purpose communication I / F 7620, dedicated communication I / F 7630, positioning unit 7640, beacon receiver 7650, in-vehicle equipment I / F 7660, and in-vehicle network I / F 7680. For example, the microcomputer 7610 may calculate control target values ​​for the drive force generator, steering mechanism, or braking device based on acquired information from inside and outside the vehicle, and output control commands to the drive system control unit 7100. For example, the microcomputer 7610 may perform coordinated control aimed at realizing ADAS (Advanced Driver Assistance System) functions, including vehicle collision avoidance or impact mitigation, following driving based on distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning. Furthermore, the microcomputer 7610 may perform cooperative control for purposes such as autonomous driving, where the vehicle drives autonomously without driver intervention, by controlling the drive force generating device, steering mechanism, or braking device, etc., based on the acquired information about the vehicle's surroundings.

[0180] The microcomputer 7610 may generate three-dimensional distance information between the vehicle and surrounding structures, people, and other objects based on information acquired via at least one of the general-purpose communication I / F 7620, dedicated communication I / F 7630, positioning unit 7640, beacon receiver 7650, in-vehicle equipment I / F 7660, and in-vehicle network I / F 7680, and create local map information including surrounding information of the vehicle's current location. The microcomputer 7610 may also predict dangers such as vehicle collision, proximity of pedestrians, or entry into a closed road based on the acquired information, and generate a warning signal. The warning signal may be, for example, a signal to generate a warning sound or to illuminate a warning lamp.

[0181] The audio-image output unit 7670 transmits at least one of audio and image output signals to an output device capable of visually or audibly notifying the vehicle's occupants or those outside the vehicle. In the example shown in Figure 43, the output devices are exemplified as an audio speaker 7710, a display unit 7720, and an instrument panel 7730. The display unit 7720 may include, for example, at least one of an onboard display and a head-up display. The display unit 7720 may also have an AR (Augmented Reality) display function. The output device may be other devices besides these, such as headphones, wearable devices such as glasses-type displays worn by occupants, projectors, or lamps. If the output device is a display device, the display device visually displays the results obtained from various processes performed by the microcomputer 7610 or information received from other control units in various formats such as text, images, tables, and graphs. If the output device is an audio output device, the audio output device converts the audio signal, consisting of reproduced audio data or sound data, into an analog signal and outputs it audibly.

[0182] In the example shown in Figure 43, at least two control units connected via the communication network 7010 may be integrated into a single control unit. Alternatively, each control unit may be composed of multiple control units. Furthermore, the vehicle control system 7000 may include other control units not shown. Also, in the above description, some or all of the functions performed by one control unit may be assigned to other control units. In other words, as long as information is transmitted and received via the communication network 7010, predetermined calculation processing may be performed by any of the control units. Similarly, a sensor or device connected to one control unit may be connected to another control unit, and multiple control units may transmit and receive detection information to and from each other via the communication network 7010.

[0183] In the vehicle control system 7000 described above, the light detection device 10 according to this embodiment, as described using Figure 5A, can be applied to the imaging unit 7410 in the application example shown in Figure 43. This improves the light detection sensitivity of the imaging unit 7410, enabling the generation of clear image data even in dark places, or realizing high-precision distance measurement.

[0184] The technology can take the following configurations: (1) A photodetector comprising: a first electrode; a first semiconductor region of a first conductivity type connected to the first electrode; a second semiconductor region of a second conductivity type arranged on a different layer from the first semiconductor region and arranged so as to contact a part of the outer periphery of the first semiconductor region in a plan view, rather than the entire outer periphery; a second electrode connected to the second semiconductor region; a third semiconductor region arranged around the first and second semiconductor regions and converting incident light into electric charge; and an avalanche region arranged at the point where the first and second semiconductor regions meet and multiplying the charge converted by the third semiconductor region. (2) The photodetector according to (1), comprising a plurality of second semiconductor regions, each arranged spaced apart on the same layer and arranged so as to contact a part of the outer periphery of the first semiconductor region in a plan view. (3) The photodetector according to (1), wherein the second semiconductor region and the first semiconductor region are joined at one corner each. (4) A photodetector according to any one of (1) to (3), comprising a fourth semiconductor region of the second conductivity type having a lower impurity concentration than the second semiconductor region, or a fourth semiconductor region of the first conductivity type having a lower impurity concentration than the first semiconductor region, which is arranged on the same layer as the second semiconductor region and overlaps with at least a portion of the first semiconductor region in a plan view. (5) A photodetector according to any one of (1) to (4), comprising a fifth semiconductor region of the first conductivity type having a lower impurity concentration than the first semiconductor region, which is arranged on the same layer as the first semiconductor region and overlaps with at least a portion of the second semiconductor region in a plan view, or at least one first insulating region arranged on the same layer as the first semiconductor region and overlaps with at least a portion of the second semiconductor region in a plan view. (6) A photodetector according to any one of (1) to (5), which has a second insulating region arranged to surround the first electrode.(7) A photodetector comprising: a first electrode; a first semiconductor region of a first conductivity type connected to the first electrode; a second semiconductor region of a second conductivity type, at least a portion of which is arranged on the same layer as the first semiconductor region and is arranged to be in contact with at least a portion of the outer periphery of the first semiconductor region in a plan view; a second electrode connected to the second semiconductor region; a third semiconductor region arranged around the first and second semiconductor regions and converting incident light into electric charge; and an avalanche region arranged along the junction surface where the first and second semiconductor regions are in contact and multiplying the charge converted in the third semiconductor region. (8) The photodetector according to (7), comprising at least one of the following: a fourth semiconductor region of the first conductivity type, which is located on the incident light side of the second semiconductor region and overlaps with at least a portion of the second semiconductor region in a plan view, and has a lower impurity concentration than the first semiconductor region; or a fifth semiconductor region of the second conductivity type, which is located on the incident light side of the first semiconductor region and overlaps with at least a portion of the first semiconductor region in a plan view, and has a lower impurity concentration than the second semiconductor region. (9) The photodetector according to (7), comprising a fourth semiconductor region of the second conductivity type, which is located on the incident light side of the first and second semiconductor regions and overlaps with at least a portion of the first and second semiconductor regions in a plan view, and has a lower impurity concentration than the second semiconductor region. (10) The photodetector according to any one of (7) to (9), wherein the second semiconductor region is located in contact with the entire outer periphery of the first semiconductor region in a plan view. (11) The photodetector according to any one of (7) to (9), wherein the second semiconductor region is arranged in a plan view such that it does not touch the entire outer periphery of the first semiconductor region but touches a part of its outer periphery. (12) The photodetector according to (11), wherein the first semiconductor region and the second semiconductor region are joined together by one surface each. (13) The photodetector according to any one of (1) to (12), wherein the second semiconductor region is arranged radially or linearly from the first semiconductor region in a plan view.(14) The photodetector according to any one of (1) to (12), wherein the second semiconductor region is arranged on a line connecting the first electrode and the second electrode in a plan view. (15) The photodetector according to any one of (1) to (14), comprising a plurality of second electrodes, each spaced apart from the others and electrically connected to the second semiconductor region. (16) The photodetector according to any one of (1) to (15), comprising the first semiconductor region, the second semiconductor region, the third semiconductor region, and the avalanche region, and comprising pixels that are triangular or polygonal, circular, or elliptical in a plan view. (17) The photodetector according to (16), wherein if the pixel is polygonal in a plan view, the second electrode is arranged at each corner of the polygon. (18) The photodetector according to (16), wherein the second electrode is arranged in a ring along the outer circumference of the pixel in a plan view. (19) The photodetector according to any one of (1) to (18), wherein the first electrode and the second electrode are arranged spaced apart along a direction intersecting the plane of incident light. (20) The photodetector according to any one of (1) to (19), wherein the first semiconductor region, the second semiconductor region, the third semiconductor region, and the avalanche region have a SPAD (Single Photon Avalanche Diode).

[0185] The aspects of this disclosure are not limited to the individual embodiments described above, but include various modifications that a person skilled in the art could conceive, and the effects of this disclosure are not limited to those described above. In other words, various additions, modifications, and partial deletions are possible, as long as they do not depart from the conceptual idea and spirit of this disclosure derived from the claims and their equivalents.

[0186] 1, 1a, 1b, 1c, 1d, 1e, 1f, 1g, 1h, 1i, 1j, 1k, 71, 71a, 71b, 71c, 71d, 71e, 71f, 100, 200 pixels, 2 first electrode, 3 second electrode, 4 first semiconductor region, 5, 101, 201 second semiconductor region, 6 third semiconductor region, 7 semiconductor region, 10, 10a light detection device, 11 substrate, 12 lens, 13 color filter, 21 first substrate, 22 second substrate, 23 third substrate, 25 pixel array section, 26 logic circuit, 27 pixel circuit, 31, 81, 85 fourth semiconductor region, 41, 82 fifth semiconductor region, 42 insulating region, 51 interlayer insulating film, 61 interpixel isolation region, 90 distance measuring system, 91 light emitting device, 92 distance measuring device, 93 Light emission timing control unit, 94 control unit, 95 time of flight detection unit, 96 histogram generation unit, 97 distance detection unit

Claims

1. A photodetector comprising: a first electrode; a first semiconductor region of a first conductivity type connected to the first electrode; a second semiconductor region of a second conductivity type arranged on a different layer from the first semiconductor region and arranged so as to contact a part of the outer periphery of the first semiconductor region in a plan view, but not the entire outer periphery; a second electrode connected to the second semiconductor region; a third semiconductor region arranged around the first and second semiconductor regions and converting incident light into electric charge; and an avalanche region arranged at the point where the first and second semiconductor regions are in contact and multiplying the electric charge converted by the third semiconductor region.

2. The photodetector according to claim 1, comprising a plurality of second semiconductor regions, each arranged separately on the same layer and each arranged in contact with a part of the outer periphery of the first semiconductor region in a plan view.

3. The photodetector according to claim 1, wherein the second semiconductor region and the first semiconductor region are joined at one corner each.

4. The photodetector according to claim 1, further comprising a fourth semiconductor region which is arranged in the same layer as the second semiconductor region and overlaps with at least a portion of the first semiconductor region in a plan view, and which has a lower impurity concentration than the second semiconductor region, or a lower impurity concentration than the first semiconductor region, and which has a lower impurity concentration than the first semiconductor region, a second conductivity type or a first conductivity type.

5. The photodetector according to claim 1, comprising at least one of the following: a fifth semiconductor region of a first conductivity type, which is arranged on the same layer as the first semiconductor region and overlaps with at least a portion of the second semiconductor region in a plan view, and has a lower impurity concentration than the first semiconductor region; or a first insulating region, which is arranged on the same layer as the first semiconductor region and overlaps with at least a portion of the second semiconductor region in a plan view.

6. The photodetector according to claim 1, further comprising a second insulating region arranged to surround the first electrode.

7. A photodetector comprising: a first electrode; a first semiconductor region of a first conductivity type connected to the first electrode; a second semiconductor region of a second conductivity type, at least a portion of which is arranged on the same layer as the first semiconductor region and is arranged to be in contact with at least a portion of the outer periphery of the first semiconductor region in a plan view; a second electrode connected to the second semiconductor region; a third semiconductor region arranged around the first and second semiconductor regions and converting incident light into electric charge; and an avalanche region arranged along the junction surface where the first and second semiconductor regions are in contact and multiplying the charge converted by the third semiconductor region.

8. The photodetector according to claim 7, comprising at least one of the following: a fourth semiconductor region of the first conductivity type, which is located on the light incident surface side of the second semiconductor region and overlaps with at least a portion of the second semiconductor region in a plan view, and has a lower impurity concentration than the first semiconductor region; or a fifth semiconductor region of the second conductivity type, which is located on the light incident surface side of the first semiconductor region and overlaps with at least a portion of the first semiconductor region in a plan view, and has a lower impurity concentration than the second semiconductor region.

9. The photodetector according to claim 7, further comprising a fourth semiconductor region of a second conductivity type, which is positioned on the light incident surface side of the first semiconductor region and the second semiconductor region, and which overlaps with at least a portion of the first semiconductor region and the second semiconductor region in a plan view, and which has a lower impurity concentration than the second semiconductor region.

10. The photodetector according to claim 7, wherein the second semiconductor region is arranged to be in contact with the entire outer periphery of the first semiconductor region in a plan view.

11. The photodetector according to claim 7, wherein the second semiconductor region is arranged so as to not be in contact with the entire outer periphery of the first semiconductor region in a plan view, but in contact with a part of the outer periphery.

12. The photodetector according to claim 11, wherein the first semiconductor region and the second semiconductor region are joined together by one surface each.

13. The photodetector according to claim 1, wherein the second semiconductor region is arranged radially or linearly from the first semiconductor region in a plan view.

14. The photodetector according to claim 1, wherein the second semiconductor region is arranged on a line connecting the first electrode and the second electrode in a plan view.

15. The photodetector according to claim 1, comprising a plurality of second electrodes, each spaced apart from the others and electrically connected to the second semiconductor region.

16. The photodetector according to claim 1, having the first semiconductor region, the second semiconductor region, the third semiconductor region, and the avalanche region, and comprising pixels that are triangular or polygonal, circular, or elliptical in a plan view.

17. The light detection device according to claim 16, wherein, if the pixel is polygonal in plan view, the second electrode is arranged at each corner of the polygon.

18. The photodetector according to claim 16, wherein the second electrode is arranged in a ring shape along the outer circumference of the pixel in a plan view.

19. The light detection device according to claim 1, wherein the first electrode and the second electrode are arranged at a distance from each other along a direction intersecting the plane of incident light.

20. The photodetector according to claim 1, wherein the first semiconductor region, the second semiconductor region, the third semiconductor region, and the avalanche region each have a SPAD (Single Photon Avalanche Diode).

Images