Semiconductor device

Abstract

This semiconductor device comprises: a semiconductor layer of a first conductivity type; an impurity region of a second conductivity type, that is formed in an inner portion of the semiconductor layer and forms a bipolar diode with the semiconductor layer; and a trench electrode-type rectification structure that is formed in a peripheral portion of the semiconductor layer and forms a unipolar diode with the semiconductor layer.

Description

Semiconductor device

[0001] This application claims priority based on Patent Application No. 2024-180601 filed with the Japan Patent Office on October 16, 2024, and the entire contents of this application are incorporated herein by reference. The present disclosure relates to a semiconductor device.

[0002] Patent Document 1 (US2008 / 0012050A1) discloses a semiconductor device having a trench gate type transistor and a Schottky barrier diode formed on a semiconductor substrate.

[0003] U.S. Patent Application Publication No. 2008 / 0012050

[0004] [Summary] The present disclosure provides a semiconductor device having a novel layout.

[0005] The present disclosure provides a semiconductor device including a semiconductor layer of a first conductivity type, an impurity region of a second conductivity type formed in an inner portion of the semiconductor layer and forming a bipolar diode with the semiconductor layer, and a trench electrode type rectifying structure formed in a peripheral portion of the semiconductor layer and forming a unipolar diode with the semiconductor layer.

[0006] The present disclosure provides a semiconductor device including a semiconductor layer of a first conductivity type, an impurity region of a second conductivity type formed in an inner portion of the semiconductor layer and forming a bipolar diode with the semiconductor layer, a diode region of the first conductivity type formed in a peripheral portion of the semiconductor layer, and a planar type electrode disposed on the peripheral portion of the semiconductor layer and forming a unipolar diode with the diode region.

[0007] The above or further other objects, features, and effects will be clarified by a detailed description with reference to the accompanying drawings.

[0008] Figure 1 is a plan view showing a semiconductor device according to the first embodiment. Figure 2 is a cross-sectional view along the line II-II shown in Figure 1. Figure 3 is a plan view showing an example of the layout of the first main surface. Figure 4 is an enlarged plan view showing the active region. Figure 5 is an enlarged plan view showing the periphery of the active region. Figure 6 is a cross-sectional view along the line VI-VI shown in Figure 4. Figure 7 is a cross-sectional view along the line VII-VII shown in Figure 4. Figure 8 is a cross-sectional view along the line VIII-VIII shown in Figure 5. Figure 9 is a cross-sectional perspective view showing the active region. Figure 10 is a cross-sectional view of the outer region along the line XX shown in Figure 1. Figure 11A is an enlarged cross-sectional view showing a first example of the outer region shown in Figure 10. Figure 11B is an enlarged cross-sectional view showing a second example of the outer region shown in Figure 10. Figure 11C is an enlarged cross-sectional view showing a third example of the outer region shown in Figure 10. Figure 11D is an enlarged cross-sectional view showing a fourth example of the outer region shown in Figure 10. Figure 11E is an enlarged cross-sectional view showing a fifth example of the outer region shown in Figure 10. Figure 11F is an enlarged cross-sectional view showing a sixth example of the outer region shown in Figure 10. Figure 12 is a circuit diagram showing the electrical configuration of the semiconductor device shown in Figure 1. Figure 13 is a graph showing the electrical behavior of the semiconductor device shown in Figure 1. Figure 14 is a plan view showing an example of the layout of the first main surface of the semiconductor device according to the second embodiment. Figure 15A is an enlarged cross-sectional view showing a first example of the outer region shown in Figure 14. Figure 15B is an enlarged cross-sectional view showing a second example of the outer region shown in Figure 14. Figure 15C is an enlarged cross-sectional view showing a third example of the outer region shown in Figure 14. Figure 15D is an enlarged cross-sectional view showing a fourth example of the outer region shown in Figure 14. Figure 15E is an enlarged cross-sectional view showing a fifth example of the outer region shown in Figure 14. Figure 15F is an enlarged cross-sectional view showing a sixth example of the outer region shown in Figure 14. Figure 16 is a plan view showing an example of the layout of the first main surface of the semiconductor device according to the third embodiment. Figure 17 is a cross-sectional view of the outer region. Figure 18A is an enlarged cross-sectional view showing a first example of the outer region shown in Figure 17. Figure 18B is an enlarged cross-sectional view showing a second example of the outer region shown in Figure 17. Figure 18C is an enlarged cross-sectional view showing a third example of the outer region shown in Figure 17. Figure 19 is a plan view showing an example of the layout of the first main surface of a semiconductor device according to the fourth embodiment. Figure 20 is an enlarged cross-sectional view showing the outer region shown in Figure 19. Figure 21 is a cross-sectional perspective view showing the active region of a semiconductor device according to the fifth embodiment.Figure 22 is a cross-sectional perspective view showing the active region of the semiconductor device according to the sixth embodiment. Figure 23 is a cross-sectional view showing the active region of the semiconductor device according to the seventh embodiment. Figure 24 is an enlarged plan view showing the active region of the semiconductor device according to the eighth embodiment. Figure 25 is a cross-sectional view along the line XXV-XXV shown in Figure 24. Figure 26 is a cross-sectional perspective view showing the active region. Figure 27 is a cross-sectional view of the outer region. Figure 28 is a cross-sectional perspective view showing the active region of the semiconductor device according to the ninth embodiment.

[0009] [Detailed Explanation] The specific form is described in detail below with reference to the attached drawings. The attached drawings are all schematic diagrams and are not strictly accurate; relative positions, scales, ratios, angles, etc., do not necessarily match. Corresponding structures in the attached drawings are given the same reference numerals, and redundant explanations are omitted or simplified. For structures whose explanations are omitted or simplified, the explanation given before the omission or simplification applies.

[0010] In this specification, open language terms such as "including" and "having" are described as encompassing closed language terms such as "consisting of." When the term "substantially" is used in this specification, it includes not only numerical values ​​(forms) that are equal to the numerical value (form) being compared, but also numerical errors (form errors) within a range of ±10% relative to the numerical value (form) being compared.

[0011] This specification uses terms such as "First," "Second," and "Third," but these are symbols attached to the names of each structure to clarify the order of explanation, and are not intended to limit the names of each structure.

[0012] In this specification, the conductivity type of a semiconductor (impurity) is indicated using "p-type" or "n-type," but "p-type" may be referred to as the "first conductivity type" and "n-type" as the "second conductivity type."

[0013] "P-type" is a conductivity type derived from trivalent elements, while "n-type" is a conductivity type derived from pentavalent elements. Trivalent elements are at least one of boron, aluminum, gallium, and indium. Pentavalent elements are at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0014] Figure 1 is a plan view showing a semiconductor device 1A according to the first embodiment. Figure 2 is a cross-sectional view taken along the line II-II shown in Figure 1. Figure 3 is a plan view showing an example of the layout of the first main surface 3. Figure 4 is an enlarged plan view showing the active region 8. Figure 5 is an enlarged plan view showing the peripheral edge of the active region 8.

[0015] Figure 6 is a cross-sectional view along the line VI-VI shown in Figure 4. Figure 7 is a cross-sectional view along the line VII-VII shown in Figure 4. Figure 8 is a cross-sectional view along the line VIII-VIII shown in Figure 5. Figure 9 is a cross-sectional perspective view showing the active region 8. Figure 10 is a cross-sectional view of the peripheral edge of the tip 2 along the line XX shown in Figure 1. Figure 11A is an enlarged cross-sectional view showing a first example of the outer region 9 (rectifier structure 30 and source finger electrode 53) shown in Figure 10.

[0016] Referring to Figures 1 to 10, semiconductor device 1A is a semiconductor switching device having an insulated gate type transistor structure Tr as an example of a device structure (functional device). The transistor structure Tr has a trench gate type vertical structure.

[0017] The semiconductor device 1A includes a chip 2 formed in a hexahedral shape (specifically, a rectangular parallelepiped shape). In this embodiment, the chip 2 includes a single crystal of a wide-bandgap semiconductor. In other words, the semiconductor device 1A is a "wide-bandgap semiconductor device". The chip 2 may also be referred to as a "semiconductor chip," "wide-bandgap semiconductor chip," etc.

[0018] Wide-bandgap semiconductors are semiconductors that have a bandgap greater than that of silicon (Si). Examples of wide-bandgap semiconductors include gallium nitride (GaN), silicon carbide (SiC), and diamond (C). In this configuration, chip 2 is a "SiC chip" containing a hexagonal SiC single crystal as an example of a wide-bandgap semiconductor. In other words, semiconductor device 1A is a "SiC semiconductor device".

[0019] Hexagonal SiC single crystals have multiple polytypes, including 2H (Hexagonal)-SiC single crystals, 4H-SiC single crystals, and 6H-SiC single crystals. In this embodiment, an example is shown in which chip 2 contains a 4H-SiC single crystal, but chip 2 may contain other polytypes. Of course, chip 2 may also contain cubic or polycrystalline materials. For example, chip 2 may contain a 3C (Cubic)-SiC single crystal or a 3C-SiC polycrystalline material.

[0020] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connected to the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a rectangular shape in a plan view (hereinafter simply referred to as "plan view") taken from the thickness direction Z of the chip 2. The thickness direction Z is also the vertical direction of the first main surface 3 and the second main surface 4.

[0021] The first main surface 3 and the second main surface 4 are formed by the c-planes of the SiC single crystal. The first main surface 3 may be formed by the silicon plane ((0001) plane) of the SiC single crystal, and the second main surface 4 may be formed by the carbon plane ((000-1) plane) of the SiC single crystal.

[0022] The first side surface 5A extends in the first direction X. The second side surface 5B is connected to the first side surface 5A and extends in the second direction Y, which intersects (specifically, is perpendicular to) the first direction X. The third side surface 5C is connected to the second side surface 5B and extends in the first direction X. The fourth side surface 5D is connected to the first side surface 5A and the third side surface 5C and extends in the second direction Y.

[0023] In this embodiment, the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y is the a-axis direction ([11-20] direction) of the SiC single crystal. Alternatively, the first direction X may be the a-axis direction and the second direction Y may be the m-axis direction. Alternatively, the first direction X may be a direction that intersects both the a-axis and m-axis directions, and the second direction Y may be a direction that intersects both the a-axis and m-axis directions.

[0024] In the following, the direction extending along the first main surface 3 may be referred to as the "horizontal direction." The horizontal direction is the direction along the XY plane (horizontal plane) formed by the first direction X and the second direction Y, and is perpendicular to the thickness direction Z.

[0025] The chip 2 (first main surface 3 and second main surface 4) has an off-angle that is inclined at a predetermined angle in a predetermined off-direction with respect to the c-plane of the SiC single crystal. In other words, the c-axis ((0001) axis) of the SiC single crystal is inclined by the amount of the off-angle from the thickness direction Z (vertical line) toward the off-direction. The off-direction is preferably the a-axis direction (i.e., the second direction Y) of the SiC single crystal. The off-direction may also be the m-axis direction of the SiC single crystal.

[0026] The off-angle may be greater than 0° and less than or equal to 10°. The off-angle may have a value that falls within at least one of the following ranges: greater than 0° and less than or equal to 1°, 1° to 2.5°, 2.5° to 5°, 5° to 7.5°, and 7.5° to 10°.

[0027] The off-angle is preferably 5° or less. The off-angle is particularly preferably 2° or more and 4.5° or less. The off-angle is typically set in the range of 4° ± 0.1°. This specification does not exclude a configuration in which the off-angle is 0° (i.e., a configuration in which the first principal surface 3 is just plane to the c-plane).

[0028] The semiconductor device 1A includes an n-type first semiconductor layer 6 formed in the region on the second main surface 4 side within the chip 2. The first semiconductor layer 6 may also be referred to as the "first layer (region)," the "drain layer (region)," etc. The first semiconductor layer 6 extends in layers along the second main surface 4 and forms the second main surface 4 and the first to fourth side surfaces 5A to 5D.

[0029] The first semiconductor layer 6 includes a single crystal of a wide-bandgap semiconductor. In this embodiment, the first semiconductor layer 6 is a SiC substrate containing a hexagonal SiC single crystal. The first semiconductor layer 6 includes a 4H-SiC single crystal and has the aforementioned off-direction and off-angle. Of course, the first semiconductor layer 6 may be made of other polytypes. The first semiconductor layer 6 may be made of a 3C-SiC polycrystal.

[0030] The first semiconductor layer 6 may have a substantially constant n-type impurity concentration in the thickness direction Z. The n-type impurity concentration of the first semiconductor layer 6 may be adjusted by a single pentavalent element. Preferably, the first semiconductor layer 6 contains a pentavalent element other than phosphorus. In this embodiment, the concentration of the first semiconductor layer 6 is adjusted by nitrogen as the pentavalent element.

[0031] The first semiconductor layer 6 may have a thickness greater than 0 μm and 500 μm or less. The thickness of the first semiconductor layer 6 may have a value that falls within at least one of the following ranges: greater than 0 μm and 1 μm or less, 1 μm or more and 50 μm or less, 50 μm or more and 100 μm or less, 100 μm or more and 150 μm or less, 150 μm or more and 200 μm or less, 200 μm or more and 250 μm or less, 250 μm or more and 300 μm or less, 300 μm or more and 350 μm or less, 350 μm or more and 400 μm or more and 400 μm or more and 450 μm or more and 500 μm or less.

[0032] The semiconductor device 1A includes an n-type second semiconductor layer 7 formed in the region on the first main surface 3 side relative to the first semiconductor layer 6 within the chip 2. The second semiconductor layer 7 may also be referred to as the "second layer (region)," "drain layer (region)," "drift layer (region)," etc. The second semiconductor layer 7 is stacked on top of the first semiconductor layer 6 and forms the upper part of the chip 2. The second semiconductor layer 7 extends in layers along the first main surface 3 (first semiconductor layer 6) and forms the first main surface 3 and the first to fourth side surfaces 5A to 5D.

[0033] The second semiconductor layer 7 includes a single crystal of a wide-bandgap semiconductor. In this embodiment, the second semiconductor layer 7 is a SiC layer containing a hexagonal SiC single crystal. In this embodiment, the second semiconductor layer 7 consists of an epitaxial layer containing a 4H-SiC single crystal (hexagonal) and has the aforementioned off-direction and off-angle. Of course, the second semiconductor layer 7 may have a polytype different from that of the first semiconductor layer 6.

[0034] The second semiconductor layer 7 has a lower n-type impurity concentration than the first semiconductor layer 6. The n-type impurity concentration of the second semiconductor layer 7 may be approximately constant in the thickness direction Z. Of course, the n-type impurity concentration of the second semiconductor layer 7 may have a concentration gradient that gradually increases and / or decreases in the stacking direction (crystal growth direction).

[0035] The n-type impurity concentration of the second semiconductor layer 7 is preferably adjusted by at least one pentavalent element. For example, the n-type impurity concentration of the second semiconductor layer 7 may be adjusted by at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth. The second semiconductor layer 7 preferably contains a pentavalent element other than phosphorus.

[0036] The second semiconductor layer 7 preferably contains at least nitrogen as a pentavalent element. If the second semiconductor layer 7 contains two or more pentavalent elements, it is preferable that the second semiconductor layer 7 contains at least two of nitrogen, arsenic, and antimony.

[0037] The second semiconductor layer 7 has a thickness less than the thickness of the first semiconductor layer 6. The thickness of the second semiconductor layer 7 may be greater than 0 μm and 25 μm or less. The thickness of the second semiconductor layer 7 may be a value that falls within at least one of the following ranges: greater than 0 μm and 2.5 μm or less, 2.5 μm or more and 5 μm or less, 5 μm or more and 7.5 μm or less, 7.5 μm or more and 10 μm or less, 10 μm or more and 12.5 μm or less, 12.5 μm or more and 15 μm or less, 15 μm or more and 17.5 μm or less, 17.5 μm or more and 20 μm or less, 20 μm or more and 22.5 μm or less, and 22.5 μm or more and 25 μm or less.

[0038] The semiconductor device 1A includes an active region 8 set on the first main surface 3. The active region 8 includes a device structure (transistor structure Tr) and is a region where an output current (drain current) is generated. The active region 8 is set in the inner part of the first main surface 3, spaced apart from the periphery of the first main surface 3 (first to fourth side surfaces 5A to 5D). In a plan view, the active region 8 is set as a polygon (a quadrilateral in this embodiment) having four sides parallel to the periphery of the first main surface 3.

[0039] The ratio of the surface area of ​​the active region 8 to the surface area of ​​the first main surface 3 (area ratio) may be 0.5 or more and less than 1. The area ratio may have a value that falls within at least one of the following ranges: 0.5 or more and 0.6 or less, 0.6 or more and 0.7 or less, 0.7 or more and 0.8 or less, 0.8 or more and 0.9 or less, 0.9 or more and 0.95 or less, and 0.95 or more and less than 1.

[0040] The semiconductor device 1A includes an outer region 9 set outside the active region 8 on the first main surface 3. The outer region 9 is a region that does not include the device structure (transistor structure Tr). The outer region 9 is set at the periphery of the first main surface 3. The outer region 9 is provided in the region between the periphery of the first main surface 3 and the active region 8. In a plan view, the outer region 9 extends in a band shape along the active region 8 and is set in a polygonal ring (a quadrilateral ring in this embodiment) that surrounds the active region 8.

[0041] The semiconductor device 1A includes a p-type body region 10 formed in the inner portion (active region 8) of the second semiconductor layer 7. The body region 10 may also be called an "impurity region". The body region 10 forms a bipolar diode DB with the second semiconductor layer 7. A source potential may be applied to the body region 10. The source potential may be a reference potential that serves as the basis for circuit operation. The reference potential may be the ground potential.

[0042] The body region 10 is formed on the surface of the first main surface 3 and replaces the conductivity type of the second semiconductor layer 7 from n-type to p-type. The body region 10 is formed in the active region 8 with a gap from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3, but is not formed in the outer region 9. The body region 10 is formed throughout the entire active region 8 and extends in layers along the first main surface 3.

[0043] The body region 10 is formed at a distance from the bottom of the second semiconductor layer 7 toward the first main surface 3 side, and faces the first semiconductor layer 6 with a part of the second semiconductor layer 7 interposed therebetween. The body region 10 may be formed at a distance from the depth position of the middle part of the second semiconductor layer 7 toward the first main surface 3 side. The body region 10 may have a portion located on the first semiconductor layer 6 side with respect to the depth position of the middle part of the second semiconductor layer 7.

[0044] The body region 10 forms a pn junction with the second semiconductor layer 7. Thereby, a bipolar diode DB including the second semiconductor layer 7 as a cathode region and the body region 10 as an anode region is formed.

[0045] The semiconductor device 1A includes a plurality of trench-type (trench electrode type) gate structures 15 formed in the inner part (active region 8) of the second semiconductor layer 7. The gate structure 15 may be referred to as a "trench structure", a "trench gate structure", or the like. A gate potential (gate signal) as a control potential is applied to the plurality of gate structures 15.

[0046] The plurality of gate structures 15 are formed in the active region 8 at a distance from the periphery of the first main surface 3 and are not formed in the outer region 9. The plurality of gate structures 15 are arranged at intervals in the first direction X in plan view and extend in a strip shape in the second direction Y, respectively. The plurality of gate structures 15 are arranged in a stripe shape extending in the second direction Y (= a-axis direction) in plan view. The extending direction of the plurality of gate structures 15 coincides with the off-direction of the SiC single crystal.

[0047] The gate structure 15 may have a width greater than 0 μm and 10 μm or less. The width of the gate structure 15 may have a value belonging to at least one of the ranges of greater than 0 μm and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, 4 μm or more and 5 μm or less, 5 μm or more and 6 μm or less, 6 μm or more and 7 μm or less, 7 μm or more and 8 μm or less, 8 μm or more and 9 μm or less, and 9 μm or more and 10 μm or less. The width of the gate structure 15 is preferably 5 μm or less.

[0048] The spacing between the gate structures 15 may be less than the width of the gate structure 15. The spacing between the gate structures 15 may be greater than the width of the gate. The spacing between the gate structures 15 may be greater than 0 μm and 10 μm or less.

[0049] The spacing of the gate structure 15 may be greater than 0 μm and fall within at least one of the following ranges: 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, 4 μm or more and 5 μm or less, 5 μm or more and 6 μm or less, 6 μm or more and 7 μm or less, 7 μm or more and 8 μm or less, 8 μm or more and 9 μm or less, and 9 μm or more and 10 μm or less.

[0050] The multiple gate structures 15 are formed at intervals from the bottom of the second semiconductor layer 7 toward the first main surface 3, and face the first semiconductor layer 6 with a portion of the second semiconductor layer 7 in between. The multiple gate structures 15 are formed almost perpendicular to the first main surface 3. The multiple gate structures 15 may be formed in a tapered shape toward the bottom of the second semiconductor layer 7.

[0051] The side walls of the multiple gate structures 15, together with the first main surface 3, define the curved open ends. The side walls (long sides) of the multiple gate structures 15 are formed by the m-plane ((1-100) plane) of the SiC single crystal. The side walls (long sides) of the multiple gate structures 15 may also be formed by the a-plane ((11-20) plane) of the SiC single crystal, depending on the direction of extension of the gate structure 15.

[0052] The bottom walls of the multiple gate structures 15 are formed by the c-planes (Si planes) of the SiC single crystal. The bottom walls of the multiple gate structures 15 may extend substantially flat along the horizontal direction. The bottom walls of the multiple gate structures 15 may be curved in an arc toward the second main surface 4.

[0053] The inclination angle (absolute value) of the side wall (long side) of the gate structure 15 with respect to the horizontal plane may be 85° or more and 95° or less. The inclination angle may have a value that falls within at least one of the following ranges: 85° or more and 87.5° or less, 87.5° or more and 90° or less, 90° or more and 92.5° or less, and 92.5° or more and 95° or less. Preferably, the inclination angle is 87° or more and 93° or less.

[0054] The gate structure 15 has a depth less than the thickness of the second semiconductor layer 7. The depth of the gate structure 15 may be greater than 0 μm and 3 μm or less. The depth of the gate structure 15 may have a value that falls within at least one of the following ranges: greater than 0 μm and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, 1.75 μm or more and 2 μm or less, 2 μm or more and 2.25 μm or less, 2.25 μm or more and 2.5 μm or less, 2.5 μm or more and 2.75 μm or less, and 2.75 μm or more and 3 μm or less.

[0055] The gate structure 15 may have an aspect ratio of 1 to 3. The aspect ratio of the gate structure 15 is the ratio of the depth of the gate structure 15 to the width of the gate structure 15. The aspect ratio may have a value that falls within at least one of the following ranges: 1 to 1.5, 1.5 to 2, 2 to 2.5, and 2.5 to 3.

[0056] The multiple gate structures 15 each include a trench 16, an insulating film 17, an embedded electrode 18, and an embedded insulator 19. The trench 16 may be referred to as the "first trench," the insulating film 17 as the "gate insulating film," and the embedded electrode 18 as the "first embedded electrode" or "gate embedded electrode." The trench 16 is formed on the first main surface 3 and demarcates the wall surfaces (side walls and bottom walls) of the gate structure 15.

[0057] The insulating film 17 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The insulating film 17 may include a silicon oxide film containing the oxide of the chip 2 (second semiconductor layer 7). The insulating film 17 may include a silicon oxide film containing oxides other than the oxide of the chip 2.

[0058] The insulating film 17 coats the wall surface of the trench 16 in a film-like manner. In this embodiment, the insulating film 17 has an upper end located on the bottom wall side of the trench 16 with respect to the height position of the first main surface 3, and a portion of the chip 2 is exposed from the wall surface of the open end of the trench 16.

[0059] The upper end of the insulating film 17 is preferably located on the opening side of the trench 16 with respect to the depth position of the middle part of the trench 16. The thickness of the portion of the insulating film 17 that covers the bottom wall of the trench 16 may be greater than the thickness of the portion of the insulating film 17 that covers the side walls of the trench 16.

[0060] The thickness of the insulating film 17 may be 10 nm or more and 250 nm or less. The thickness of the insulating film 17 may have a value that falls within at least one of the following ranges: 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, 125 nm or more and 150 nm or less, 150 nm or more and 175 nm or less, 175 nm or more and 200 nm or less, 200 nm or more and 225 nm or less, and 225 nm or more and 250 nm or less.

[0061] The embedded electrode 18 includes either a metal conductor or a non-metallic conductor, or both. The embedded electrode 18 may also include conductive polysilicon. In this case, the embedded electrode 18 may include either p-type conductive polysilicon or n-type conductive polysilicon, or both. It is preferable that the embedded electrode 18 is made of n-type conductive polysilicon.

[0062] The embedded electrode 18 is embedded in the trench 16 via an insulating film 17 and faces the second semiconductor layer 7 via the insulating film 17. The embedded electrode 18 has an electrode surface located on the bottom wall side of the trench 16 with respect to the height position of the first main surface 3. The electrode surface is located on the first main surface 3 side with respect to the depth position of the middle part of the trench 16. The electrode surface may also be located on the bottom wall side of the trench 16 with respect to the depth position of the middle part of the trench 16. The electrode surface may have a recess that is indented toward the bottom wall side.

[0063] The embedded insulator 19 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The embedded insulator 19 may include an insulating material that is different from or the same as the insulating material of the insulating film 17. In this embodiment, the embedded insulator 19 includes a silicon oxide film having properties different from those of the insulating film 17.

[0064] The embedded insulator 19 may have a single-layer or multi-layer structure including at least one of the following: NSG film (Nondoped Silicate Glass film), PSG film (Phosphorus Silicon Glass film), and BPSG film (Boron Phosphorus Silicon Glass film). The NSG film is an impurity-free silicon oxide film, the PSG film is a silicon oxide film containing phosphorus, and the BPSG film is a silicon oxide film containing both phosphorus and boron.

[0065] The embedded insulator 19 preferably has a single-layer or multilayer structure including at least an NSG film. The embedded insulator 19 may also have a multilayer structure including an NSG film and a PSG film stacked in this order from the chip 2 side. The embedded insulator 19 may also have a multilayer structure including an NSG film, a PSG film, and a BPSG film stacked in this order from the chip 2 side. The embedded insulator 19 may also have a single-layer or multilayer structure including a silicon oxide film containing the oxide of the embedded electrode 18.

[0066] The embedded insulator 19 covers the embedded electrode 18 within the trench 16. In this configuration, the embedded insulator 19 is embedded in the trench 16 via the insulating film 17 and is in contact with the insulating film 17 and the embedded electrode 18 within the trench 16. In other words, the embedded insulator 19 has a portion that faces the chip 2 in the horizontal direction via the insulating film 17.

[0067] The buried insulator 19 has an insulating surface exposed from the trench 16. The insulating surface is formed at a distance from the height of the first main surface 3 towards the bottom wall of the trench 16, and a portion of the chip 2 is exposed from the opening end of the trench 16. The insulating surface is located on the opening side of the trench 16 with respect to the depth of the middle part of the trench 16. The insulating surface may also be located on the bottom wall side of the trench 16 with respect to the depth of the middle part of the trench 16.

[0068] The insulating surface exposes the upper end of the insulating film 17. In this embodiment, the insulating surface is flush with the upper end of the insulating film 17. That is, the insulating surface is formed flush with the upper end of the insulating film 17. The insulating surface may be located on the side of the first main surface 3 or on the bottom wall side of the trench 16, rather than on the upper end of the insulating film 17. The insulating surface may be formed flush with the first main surface 3 together with the upper end of the insulating film 17.

[0069] The embedded insulator 19 may cover the upper end of the insulating film 17 and be in direct contact with the side wall (tip 2) of the trench 16. In this embodiment, the insulating surface has a recess that sinks inward from the side wall of the trench 16. The insulating surface may also have a raised portion that rises inward from the side wall of the trench 16.

[0070] In this embodiment, the embedded insulator 19 has a thickness greater than the thickness of the insulating film 17. Preferably, the thickness of the embedded insulator 19 is less than the thickness of the embedded electrode 18. The ratio of the thickness of the embedded insulator 19 to the depth of the trench 16 may be greater than 0 and less than or equal to 0.5. The thickness ratio may have a value that falls within at least one of the following ranges: greater than 0 and less than or equal to 0.1, 0.1 to 0.2, 0.2 to 0.3, 0.3 to 0.4, and 0.4 to 0.5.

[0071] The semiconductor device 1A includes a plurality of n-type source regions 20 formed in the inner portion (active region 8) of the second semiconductor layer 7. The source regions 20 have an n-type impurity concentration higher than the n-type impurity concentration of the second semiconductor layer 7. The n-type impurity concentration of the source regions 20 is higher than the p-type impurity concentration of the body region 10.

[0072] Multiple source regions 20 are formed in the surface layer of the body region 10, in the regions between the multiple gate structures 15. The multiple source regions 20 extend in layers along the first main surface 3. The multiple source regions 20 are formed at intervals in the second direction Y, following the extending direction of the multiple gate structures 15, and are adjacent to two gate structures 15 corresponding to the first direction X.

[0073] In this configuration, the multiple source regions 20 extend in a strip-like manner in the second direction Y, following the direction of extension of the corresponding multiple gate structures 15. With respect to the second direction Y, the length of the source regions 20 is greater than the spacing between the multiple gate structures 15.

[0074] With respect to the multiple source regions 20 formed on both sides of the multiple gate structures 15, the multiple source regions 20 on the other side face the multiple source regions 20 on the one side in the first direction X. Of course, the multiple source regions 20 on the other side may also face the region between the multiple source regions 20 on the one side in the first direction X.

[0075] Multiple source regions 20 are formed at intervals from the bottom of the body region 10 toward the first main surface 3, and face the second semiconductor layer 7 via a part of the body region 10. Multiple source regions 20 may have portions located on the bottom wall side of the multiple gate structures 15 with respect to the depth position of the intermediate part of the multiple gate structures 15. Multiple source regions 20 may be formed at intervals from the depth position of the intermediate part of the multiple gate structures 15 toward the first main surface 3.

[0076] Each of the multiple source regions 20 has a portion located on the first main surface 3 side with respect to the electrode surface of the embedded electrode 18, and a portion located on the bottom wall side of the gate structure 15 with respect to the electrode surface of the embedded electrode 18. Each of the multiple source regions 20 has a portion located on the first main surface 3 side with respect to the insulating surface of the embedded insulator 19, and a portion located on the bottom wall side of the gate structure 15 with respect to the insulating surface of the embedded insulator 19.

[0077] The multiple source regions 20 have portions that face the embedded electrode 18 in the horizontal direction and portions that face the embedded insulator 19 in the horizontal direction. The multiple source regions 20 face the embedded electrode 18 and the embedded insulator 19 via the insulating film 17. In this embodiment, the multiple source regions 20 have portions that run along the open end of the trench 16.

[0078] The multiple source regions 20 have a depth greater than the thickness between the bottom of the body region 10 and the bottoms of the multiple source regions 20. The depth of the multiple source regions 20 may be less than the thickness between the bottom of the body region 10 and the bottoms of the multiple source regions 20.

[0079] The semiconductor device 1A includes a plurality of p-type contact regions 21 formed in the inner portion (active region 8) of the second semiconductor layer 7. The contact regions 21 have a higher p-type impurity concentration than the p-type impurity concentration of the body region 10.

[0080] Multiple contact regions 21 are formed in the surface layer of the body region 10, in the regions between the multiple gate structures 15, thereby increasing the p-type impurity concentration of the body region 10. The multiple contact regions 21 extend in layers along the first main surface 3. The multiple contact regions 21 are formed at intervals in the second direction Y, following the extension direction of the multiple gate structures 15, and are adjacent to two gate structures 15 corresponding to the first direction X.

[0081] Multiple contact regions 21 are each interposed in the region between multiple source regions 20 with respect to the second direction Y. Multiple contact regions 21 may be connected to multiple source regions 20 in the second direction Y. Multiple contact regions 21 may be formed at a distance from multiple source regions 20 in the second direction Y and may face multiple source regions 20 via a part of the body region 10.

[0082] With respect to the multiple contact regions 21 formed on both sides of the multiple gate structures 15, the multiple contact regions 21 on the other side face the multiple contact regions 21 on the one side in the first direction X. Of course, the multiple contact regions 21 on the other side may also face the region between the multiple contact regions 21 on the one side (multiple source regions 20) in the first direction X.

[0083] Multiple contact regions 21 are formed at intervals from the bottom of the body region 10 toward the first main surface 3, and face the second semiconductor layer 7 via a part of the body region 10. Multiple contact regions 21 may have portions located on the bottom wall side of the multiple gate structures 15 with respect to the depth position of the intermediate part of the multiple gate structures 15. Multiple contact regions 21 may be formed at intervals from the depth position of the intermediate part of the multiple gate structures 15 toward the first main surface 3.

[0084] Each of the multiple contact regions 21 has a portion located on the first main surface 3 side with respect to the electrode surface of the embedded electrode 18, and a portion located on the bottom wall side of the gate structure 15 with respect to the electrode surface of the embedded electrode 18. Each of the multiple contact regions 21 has a portion located on the first main surface 3 side with respect to the insulating surface of the embedded insulator 19, and a portion located on the bottom wall side of the gate structure 15 with respect to the insulating surface of the embedded insulator 19.

[0085] The multiple contact regions 21 have portions that face the embedded electrode 18 in the horizontal direction and portions that face the embedded insulator 19 in the horizontal direction. The multiple contact regions 21 face the embedded electrode 18 and the embedded insulator 19 via the insulating film 17. In this embodiment, the multiple contact regions 21 have portions that run along the opening end of the trench 16.

[0086] The contact region 21 may have a depth greater than the depth of the source region 20. The depth of the contact region 21 may be less than the depth of the source region 20. The depth of the contact region 21 may be greater than the thickness between the bottom of the body region 10 and the bottom of the contact region 21. The depth of the contact region 21 may be less than the thickness between the bottom of the body region 10 and the bottom of the contact region 21.

[0087] The length of the multiple contact regions 21 in the second direction Y is adjusted according to the channel area to be formed. The channel area is the total planar area of ​​the multiple source regions 20. The channel area increases or decreases in proportion to the increase or decrease in the total planar area of ​​the multiple contact regions 21. It is preferable that the total planar area of ​​the multiple contact regions 21 is less than the channel area.

[0088] The multiple contact regions 21 may extend in a band shape in the second direction Y, following the direction of extension of the multiple gate structures 15 in a plan view. The lengths of the multiple contact regions 21 in the second direction Y may be equal or different from each other. The length of the contact regions 21 may be greater or less than the width of the gate structures 15. The length of the contact regions 21 may be greater or less than the spacing between the multiple gate structures 15.

[0089] The semiconductor device 1A includes a plurality of p-type well regions 22 formed in the inner portion (active region 8) of the second semiconductor layer 7. The well regions 22 may also be referred to as "gate well regions". The p-type impurity concentration in the well regions 22 may be higher or lower than the p-type impurity concentration in the body region 10. The p-type impurity concentration in the well regions 22 is lower than the p-type impurity concentration in the contact region 21. Source potentials are applied to the plurality of well regions 22.

[0090] Multiple well regions 22 are formed within the second semiconductor layer 7, spaced apart from each other in the horizontal direction (first direction X), and the conductivity type of the second semiconductor layer 7 is changed from n-type to p-type. Each of the multiple well regions 22 is formed in the regions below (specifically directly below) the multiple gate structures 15, and they overlap with the multiple gate structures 15 in a one-to-one correspondence in the thickness direction Z.

[0091] The multiple well regions 22 each extend in a strip-like manner in the second direction Y, following the extending direction of the corresponding gate structure 15 in a plan view. The multiple well regions 22 are arranged in a stripe-like manner extending in the second direction Y in a plan view. The extending direction of the multiple well regions 22 coincides with the off-direction of the SiC single crystal. With respect to the second direction Y, both ends of the multiple well regions 22 may be located inward or outward compared to both ends of the multiple gate structures 15.

[0092] Multiple well regions 22 may be formed at intervals in the second direction Y in a one-to-many correspondence with respect to the corresponding gate structure 15. Multiple well regions 22 may extend in the first direction X according to the extension direction of the multiple gate structures 15. In this case, the multiple well regions 22 intersect (specifically orthogonal) in the off direction.

[0093] Multiple well regions 22 are formed in the thickness range between the bottom of the second semiconductor layer 7 and the bottom walls of the multiple gate structures 15, and extend vertically in the thickness direction Z. The multiple well regions 22 are formed at intervals from the bottom of the second semiconductor layer 7 towards the bottom walls of the multiple gate structures 15, and face the first semiconductor layer 6 via a portion of the second semiconductor layer 7.

[0094] Each of the multiple well regions 22 has an upper end located on the bottom wall side of the corresponding gate structure 15, and a bottom located on the bottom side of the second semiconductor layer 7. The upper ends of the multiple well regions 22 are formed with a gap between the bottom of the body region 10 and the bottom wall side of the corresponding gate structure 15. The upper ends of the multiple well regions 22 are connected to the bottom wall of the corresponding gate structure 15 and face the embedded electrode 18 via the insulating film 17.

[0095] The upper ends of the multiple well regions 22 may have portions that run along the side walls of the corresponding gate structures 15. In other words, the multiple well regions 22 may face the embedded electrodes 18 via an insulating film 17 at the side walls of the corresponding gate structures 15.

[0096] The upper ends of the multiple well regions 22 may bulge out on both sides of the corresponding gate structure 15. The bottoms of the multiple well regions 22 may be located on the bottom wall side of the multiple gate structures 15 or on the bottom side of the second semiconductor layer 7 with respect to the depth position of the intermediate portion of the second semiconductor layer 7. The upper ends of the multiple well regions 22 may be formed with a gap between the bottom wall of the corresponding gate structure 15 and the bottom side of the second semiconductor layer 7.

[0097] In this configuration, the depth of the well region 22 relative to the bottom wall of the gate structure 15 is greater than the depth of the gate structure 15 relative to the first main surface 3. The depth of the well region 22 may also be less than the depth of the gate structure 15 relative to the first main surface 3.

[0098] The depth of the well region 22 may be 0.5 μm or more and 5 μm or less. The depth of the well region 22 may have a value that falls within at least one of the following ranges: 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or more and 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0099] Multiple well regions 22 form pn junctions with the second semiconductor layer 7. Multiple well regions 22 may also form a superjunction structure with charge balance with the second semiconductor layer 7. In this case, the depletion layer extending from the multiple well regions 22 becomes integrated in the regions between the multiple well regions 22.

[0100] Each of the multiple well regions 22 may be formed by a single p-type impurity region extending in the thickness direction Z. Each of the multiple well regions 22 may be formed by a plurality of p-type impurity regions connected to each other in the thickness direction Z.

[0101] The semiconductor device 1A includes a plurality of p-type well contact regions 23 formed in the inner portion (active region 8) of the second semiconductor layer 7. The well contact regions 23 have a higher p-type impurity concentration than the body region 10. The p-type impurity concentration in the well contact regions 23 is higher than the p-type impurity concentration in the well region 22.

[0102] The p-type impurity concentration in the well contact region 23 may be approximately equal to the p-type impurity concentration in the contact region 21. The p-type impurity concentration in the well contact region 23 may be higher or lower than the p-type impurity concentration in the contact region 21.

[0103] Multiple well contact regions 23 are formed in regions along multiple gate structures 15, and the conductivity type of the second semiconductor layer 7 is changed from n-type to p-type. The multiple well contact regions 23 are formed at intervals in the second direction Y in a one-to-many correspondence with respect to one corresponding gate structure 15.

[0104] Multiple well contact regions 23 are formed in regions adjacent to multiple contact regions 21 in the first direction X, and are interposed in regions between multiple source regions 20 in the second direction Y. Multiple well contact regions 23 extend along the bottom and side walls of the corresponding gate structure 15, electrically connecting the corresponding well region 22 to the body region 10.

[0105] Each of the multiple well contact regions 23 has a bottom wall portion along the bottom wall of the corresponding gate structure 15, and a side wall portion along the side wall of the corresponding gate structure 15. The bottom wall portion is connected to the bottom wall of the corresponding gate structure 15 and faces the embedded electrode 18 via an insulating film 17.

[0106] The bottom wall portion has a width greater than the width of the corresponding gate structure 15 and protrudes from both sides of the corresponding gate structure 15. The bottom wall portion is formed with a gap from the bottom of the corresponding well region 22 to the bottom wall side of the corresponding gate structure 15 and is connected to the corresponding well region 22. The p-type impurity concentration of the bottom wall portion relative to the well region 22 is increased by the amount of the p-type impurity concentration of the well region 22.

[0107] The sidewall extends along the sidewall of the corresponding gate structure 15 and faces the embedded electrode 18 via an insulating film 17. The sidewall is connected to the body region 10. In this embodiment, the sidewall is connected to one or more (in this embodiment, more) adjacent contact regions 21 in the first direction X.

[0108] The sidewall portion is connected to the bottom wall portion of the gate structure 15 on the bottom wall side. This allows the well contact region 23 to electrically connect the corresponding well region 22 to the body region 10. The sidewall portion has a width less than the thickness of the bottom wall portion. The width of the sidewall portion is the horizontal width relative to the sidewall of the gate structure 15. On the bottom wall side of the gate structure 15, the p-type impurity concentration in the sidewall portion is lower than that in the bottom wall portion.

[0109] The semiconductor device 1A includes a p-type outer well region 25 formed on the surface of the first main surface 3 at the periphery (outer region 9) of the second semiconductor layer 7. The p-type impurity concentration in the outer well region 25 may be higher or lower than the p-type impurity concentration in the body region 10. The p-type impurity concentration in the outer well region 25 is lower than the p-type impurity concentration in the contact region 21. The outer well region 25 forms a bipolar diode DB with the second semiconductor layer 7. A source potential is applied to the outer well region 25.

[0110] The outer well region 25 is formed on the surface of the first main surface 3 and replaces the conductivity type of the second semiconductor layer 7 from n-type to p-type. The outer well region 25 extends in layers along the first main surface 3. The outer well region 25 is formed with a gap between the periphery of the first main surface 3 and the inward side of the first main surface 3 (towards the active region 8).

[0111] The outer well region 25 extends in a band shape along the active region 8 in a plan view. In this configuration, the outer well region 25 is formed as a polygonal ring (a quadrilateral ring in this configuration) with four sides parallel to the periphery of the first main surface 3 in a plan view, and surrounds the active region 8 (multiple gate structures 15).

[0112] The outer well region 25 may have an edge portion that connects a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y in an arc shape (preferably a quarter-circular arc shape). The outer well region 25 has an inner edge portion on the inner side of the first main surface 3 and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion of the outer well region 25 demarcates the boundary between the active region 8 and the outer region 9.

[0113] The inner edge of the outer well region 25 may be connected to either or both of the body region 10 and the well region 22. The inner edge of the outer well region 25 may be connected to the ends of a plurality of gate structures 15. The outer edge of the outer well region 25 is formed at a distance from the periphery of the first main surface 3 and extends substantially parallel to the inner edge of the outer well region 25.

[0114] The outer well region 25 is formed with a gap from the bottom of the second semiconductor layer 7 toward the first main surface 3 and faces the first semiconductor layer 6 via a part of the second semiconductor layer 7. The outer well region 25 may be formed with a gap from the depth position of the middle part of the second semiconductor layer 7 toward the first main surface 3, or it may have a portion located toward the bottom of the second semiconductor layer 7 relative to the depth position of the middle part of the second semiconductor layer 7.

[0115] In this embodiment, the outer well region 25 has a depth less than the depth of the multiple gate structures 15. The depth of the outer well region 25 may be greater than the depth of the multiple gate structures 15. The depth of the outer well region 25 may be approximately equal to the depth of the body region 10. The depth of the outer well region 25 may be greater than or less than the depth of the body region 10.

[0116] In this configuration, the depth of the outer well region 25 is smaller than the depth of the well region 22. The depth of the outer well region 25 may be approximately equal to the depth of the well region 22, or it may be greater than the depth of the well region 22.

[0117] The outer well region 25 forms a pn junction with the second semiconductor layer 7. This forms a bipolar diode DB including the second semiconductor layer 7 as the cathode region and the outer well region 25 as the anode region. In other words, the outer well region 25 together with the body region 10 forms a bipolar diode DB.

[0118] When a reverse bias voltage is applied, the depletion layer extends from the outer well region 25 to the second semiconductor layer 7. The depletion layer extending from the outer well region 25 extends the depletion layer extending from the body region 10 (active region 8) to the peripheral edge of the first main surface 3, thereby mitigating the electric field strength (electric field concentration) at the peripheral edge of the active region 8.

[0119] The semiconductor device 1A includes a p-type outer contact region 26 formed on the surface of the outer well region 25. The outer contact region 26 has a higher p-type impurity concentration than the p-type impurity concentration of the outer well region 25.

[0120] The p-type impurity concentration in the outer contact region 26 is higher than that in the body region 10. The p-type impurity concentration in the outer contact region 26 may be approximately equal to that in the contact region 21. The p-type impurity concentration in the outer contact region 26 may be greater or less than that in the contact region 21.

[0121] The outer contact region 26 extends in a band shape along the outer well region 25 in a plan view. In this configuration, the outer contact region 26 is formed as a polygonal ring (a quadrilateral ring in this configuration) with four sides parallel to the periphery of the first main surface 3 in a plan view, and surrounds the active region 8 (multiple gate structures 15).

[0122] The outer contact region 26 may have an edge portion that connects a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y in an arc shape (preferably a quarter-circular arc shape). Of course, the semiconductor device 1A may include a plurality of outer contact regions 26. In this case, the plurality of outer contact regions 26 may be formed with spacing between them following the extending direction of the outer well region 25.

[0123] The outer contact region 26 has an inner edge on the inner side of the first main surface 3 and an outer edge on the peripheral side of the first main surface 3. In this embodiment, the inner edge of the outer contact region 26 is formed at intervals from the plurality of gate structures 15 on the peripheral side of the first main surface 3. The inner edge of the outer contact region 26 may be connected to the plurality of gate structures 15. In this case, the inner edge of the outer contact region 26 may be connected to the body region 10.

[0124] The outer edge of the outer contact region 26 is formed with a gap between it and the periphery of the first main surface 3, on the inward side of the first main surface 3. In this configuration, the outer edge of the outer contact region 26 is formed with a gap between it and the outer edge of the outer well region 25, on the inward side of the first main surface 3, and extends substantially parallel to the inner edge of the outer contact region 26.

[0125] The outer contact region 26 is formed with a gap from the bottom of the outer well region 25 toward the first main surface 3, and faces the second semiconductor layer 7 via a portion of the outer well region 25. The outer contact region 26 has a depth less than the depth of the multiple gate structures 15. The depth of the outer contact region 26 is less than the depth of the body region 10. The depth of the outer contact region 26 may be greater than the depth of the body region 10.

[0126] The semiconductor device 1A includes at least one (or more in this embodiment) p-type field region 27 formed on the surface of the first main surface 3 at the peripheral edge (outer region 9) of the second semiconductor layer 7. The multiple field regions 27 may be formed in an electrically floating state. The multiple field regions 27 may be fixed to the source potential.

[0127] The number of field regions 27 may be between 1 and 20. The number of field regions 27 may be a value that falls within at least one of the following ranges: between 1 and 5, between 5 and 10, between 10 and 15, and between 15 and 20. Typically, the number of field regions 27 is between 1 and 8. In this embodiment, the semiconductor device 1A includes 6 field regions 27.

[0128] Multiple field regions 27 have a p-type impurity concentration lower than that of the outer contact region 26. The p-type impurity concentration of the multiple field regions 27 may be approximately equal to that of the outer well region 25. The p-type impurity concentration of the multiple field regions 27 may be higher or lower than that of the outer well region 25.

[0129] The p-type impurity concentrations in the multiple field regions 27 are lower than the p-type impurity concentrations in the contact region 21. The p-type impurity concentrations in the multiple field regions 27 may be higher or lower than the p-type impurity concentrations in the body region 10. The p-type impurity concentrations in the multiple field regions 27 may be approximately equal to the p-type impurity concentrations in the well region 22. The p-type impurity concentrations in the multiple field regions 27 may be higher or lower than the p-type impurity concentrations in the well region 22.

[0130] Multiple field regions 27 are formed at intervals from each other on the surface of the second semiconductor layer 7 at the periphery of the first main surface 3, and the conductivity type of the second semiconductor layer 7 is changed from n-type to p-type. Multiple field regions 27 are formed at intervals from the periphery of the first main surface 3 and the active region 8, in the region between the periphery of the first main surface 3 and the active region 8. Multiple field regions 27 are formed at intervals from the outer well region 25 toward the periphery of the first main surface 3.

[0131] The multiple field regions 27 extend in a band shape along the outer well region 25 in a plan view. In this embodiment, the multiple field regions 27 are formed in a polygonal ring shape (a quadrilateral ring shape in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view, and surround the active region 8 (multiple gate structures 15). The multiple field regions 27 may have edge portions that connect the portion extending in a band shape in the first direction X and the portion extending in a band shape in the second direction Y in an arc shape (preferably a quarter-circular arc shape).

[0132] Multiple field regions 27 are formed at intervals from the bottom of the second semiconductor layer 7 toward the first main surface 3, and face the first semiconductor layer 6 via a portion of the second semiconductor layer 7. The multiple field regions 27 may be formed at intervals from the depth position of the middle part of the second semiconductor layer 7 toward the first main surface 3, or they may have portions located toward the bottom of the second semiconductor layer 7 relative to the depth position of the middle part of the second semiconductor layer 7.

[0133] In this configuration, the multiple field regions 27 have a depth greater than the depth of the body region 10. The depth of the multiple field regions 27 may be approximately equal to the depth of the body region 10. In this configuration, the depth of the multiple field regions 27 is greater than the depth of the multiple gate structures 15. The depth of the multiple field regions 27 may be less than the depth of the multiple gate structures 15.

[0134] The depth of the multiple field regions 27 is greater than the depth of the outer contact region 26. The depth of the multiple field regions 27 is greater than the depth of the outer well region 25. The depth of the multiple field regions 27 may be approximately equal to the depth of the outer well region 25. The depth of the multiple field regions 27 may be less than the depth of the outer well region 25.

[0135] Multiple field regions 27 form a pn junction with the second semiconductor layer 7. When a reverse bias voltage is applied, multiple depletion layers spread from the multiple field regions 27 to the second semiconductor layer 7. The depletion layers spreading from the multiple field regions 27 extend the depletion layer spreading from the outer well region 25 (active region 8) toward the periphery of the first main surface 3, thereby mitigating the electric field strength (electric field concentration) at the periphery of the first main surface 3.

[0136] The width, depth, spacing, and p-type impurity concentration of the multiple field regions 27 are arbitrary and can take various values ​​depending on the electric field to be relaxed. The width of the multiple field regions 27 may be approximately constant or non-uniform. The width of the multiple field regions 27 may gradually increase or decrease toward the periphery of the first main surface 3.

[0137] The depths of the multiple field regions 27 may be approximately constant or non-uniform. The depths of the multiple field regions 27 may gradually increase or decrease toward the peripheral edge of the first main surface 3. The multiple field regions 27 may each have a relatively shallow portion and a deeper portion that is deeper than the shallow portion. The shallow portion may be formed on the inner side and the deep portion may be formed on the peripheral side.

[0138] The spacing between the multiple field regions 27 may be approximately constant or non-uniform. The spacing between the multiple field regions 27 may gradually increase or decrease toward the periphery of the first main surface 3. The p-type impurity concentration in the multiple field regions 27 may be approximately constant or non-uniform. The p-type impurity concentration in the multiple field regions 27 may gradually increase or decrease toward the periphery of the first main surface 3.

[0139] The semiconductor device 1A includes a rectifier structure 30 formed on the peripheral edge (outer region 9) of the second semiconductor layer 7. The rectifier structure 30 may also be referred to as a "unipolar rectifier structure". The rectifier structure 30 forms a unipolar diode DU having a heterojunction formed of a semiconductor and a conductor. In other words, the unipolar diode DU is a heterojunction diode.

[0140] In this configuration, the unipolar diode DU is a Schottky barrier diode, an example of a heterojunction diode. The unipolar diode DU is formed as a freewheeling diode for a transistor structure Tr.

[0141] The rectifier structure 30 is supplied with a potential other than the gate potential. The rectifier structure 30 is supplied with a reference potential (i.e., source potential) that serves as the reference for circuit operation. The rectifier structure 30 is electrically connected to the outer well region 25 and the outer contact region 26. In other words, the rectifier structure 30 is electrically connected to the body region 10, the source region 20, and the contact region 21. In this configuration, the rectifier structure 30 is of the trench electrode type.

[0142] The rectifier structure 30 is formed on the peripheral edge of the first main surface 3, spaced apart from the periphery of the first main surface 3 and the plurality of gate structures 15 (active region 8). The rectifier structure 30 is formed spaced apart from the plurality of field regions 27 (the innermost field region 27) toward the active region 8. Specifically, the rectifier structure 30 is formed spaced apart from the outer edge of the outer well region 25 toward the active region 8. More specifically, the rectifier structure 30 is formed spaced apart from the outer edge of the outer contact region 26 toward the active region 8.

[0143] The rectifier structure 30 extends in a strip shape along the active region 8 in a plan view. In this embodiment, the rectifier structure 30 is formed in a polygonal ring shape (a quadrilateral ring shape in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view, and surrounds the active region 8 (a plurality of gate structures 15). The rectifier structure 30 may have an edge portion that connects the portion extending in a strip shape in the first direction X and the portion extending in a strip shape in the second direction Y in an arc shape (preferably a quarter-circular arc shape).

[0144] The rectifier structure 30 penetrates the outer well region 25 and the outer contact region 26 so as to reach the second semiconductor layer 7, and is electrically connected to the second semiconductor layer 7, the outer well region 25, and the outer contact region 26. The rectifier structure 30 is located inward from the inner and outer edges of the outer contact region 26 and penetrates the inner portion of the outer contact region 26.

[0145] The rectifying structure 30 has a first side wall on the inner (active region 8) side of the first main surface 3, a second side wall on the peripheral side of the first main surface 3, and a bottom wall connecting the first and second side walls. The first and second side walls have a surface formed by the m-plane of the SiC single crystal and a surface formed by the a-plane of the SiC single crystal, respectively. The first and second side walls may together with the first main surface 3 to define an open end that is curved in an arc shape (circular arc shape).

[0146] The first and second side walls may be formed substantially perpendicular to the first main surface 3. In other words, the flow straightening structure 30 may have a vertical shape in cross-section. The first and second side walls may be inclined obliquely in the tapering direction with respect to the first main surface 3. In other words, the flow straightening structure 30 may be formed in a tapered shape (tapering shape) in cross-section.

[0147] The inclination angle (absolute value) of the first side wall (second side wall) relative to the horizontal plane may be 85° or more and 95° or less. The inclination angle may have a value that falls within at least one of the following ranges: 85° or more and 87.5° or less, 87.5° or more and 90° or less, 90° or more and 92.5° or more and 95° or less. Preferably, the inclination angle is 87° or more and 93° or less.

[0148] The first and second side walls are electrically connected to the outer well region 25 and the outer contact region 26 in the region on the first main surface 3 side relative to the bottom of the outer well region 25, and are electrically connected to the second semiconductor layer 7 in the region on the bottom side of the second semiconductor layer 7 relative to the bottom of the outer well region 25.

[0149] The bottom wall is formed by the c-plane of a SiC single crystal. The bottom wall may extend almost flat along the horizontal direction. The bottom wall may be curved in an arc toward the second main surface 4. The bottom wall is formed with a gap from the bottom of the second semiconductor layer 7 toward the first main surface 3 and faces the first semiconductor layer 6 through a part of the second semiconductor layer 7.

[0150] The bottom wall may be formed with a gap from the depth position of the middle part of the second semiconductor layer 7 toward the first main surface 3, or it may be located toward the first semiconductor layer 6 with respect to the depth position of the middle part of the second semiconductor layer 7. In this embodiment, the bottom wall of the rectifier structure 30 is located below the depth position of the bottom wall of the gate structure 15 (towards the bottom of the second semiconductor layer 7). The bottom wall of the rectifier structure 30 may be located above the depth position of the bottom wall of the gate structure 15 (towards the first main surface 3).

[0151] In this embodiment, the rectifier structure 30 has a width greater than or equal to the width of the gate structure 15. Specifically, the width of the rectifier structure 30 is greater than the width of the gate structure 15. Of course, the width of the rectifier structure 30 may be approximately equal to the width of the gate structure 15. The width of the rectifier structure 30 may be less than the width of the gate structure 15. The width of the rectifier structure 30 may be greater than 0 μm and 10 μm or less.

[0152] The width of the rectifier structure 30 may be greater than 0 μm and fall within at least one of the following ranges: 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, 4 μm or more and 5 μm or less, 5 μm or more and 6 μm or less, 6 μm or more and 7 μm or less, 7 μm or more and 8 μm or less, 8 μm or more and 9 μm or less, and 9 μm or more and 10 μm or less. Preferably, the width of the rectifier structure 30 is 5 μm or less.

[0153] In this embodiment, the rectifier structure 30 has a depth greater than or equal to the depth of the gate structure 15. Specifically, the depth of the rectifier structure 30 is greater than the depth of the gate structure 15. Of course, the depth of the rectifier structure 30 may be approximately equal to the depth of the gate structure 15. The depth of the rectifier structure 30 may be less than the depth of the gate structure 15. The depth of the rectifier structure 30 may be greater than 0 μm and 5 μm or less.

[0154] The depth of the rectifier structure 30 may be greater than 0 μm and fall within at least one of the following ranges: 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, 1.75 μm or more and 2 μm or less, 2 μm or more and 2.25 μm or less, 2.25 μm or more and 2.5 μm or less, 2.5 μm or more and 2.75 μm or less, 2.75 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or more and 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0155] The rectifier structure 30 may have an aspect ratio different from that of the gate structure 15. The aspect ratio of the rectifier structure 30 is the ratio of the depth of the rectifier structure 30 to the width of the rectifier structure 30. The aspect ratio of the rectifier structure 30 may be greater than or less than that of the gate structure 15. The aspect ratio of the gate structure 15 may be approximately equal to that of the gate structure 15.

[0156] The aspect ratio of the rectifier structure 30 may be greater than 0 and less than or equal to 5. The aspect ratio may have a value that falls within at least one of the following ranges: 1 to 1.5, 1.5 to 2, 2 to 2.5, and 2.5 to 3.

[0157] The rectifier structure 30 forms a Schottky junction as a heterojunction at the connection interface with the second semiconductor layer 7. This forms a unipolar diode DU including the second semiconductor layer 7 as the cathode region and the rectifier structure 30 as the anode region.

[0158] The rectifier structure 30 includes an outer trench 31 and an outer embedded electrode 32. The outer trench 31 may be referred to as the "second trench," and the outer embedded electrode 32 may be referred to as the "second embedded electrode." The outer trench 31 is formed on the first main surface 3 and demarcates the walls (first side wall, second side wall, and bottom wall) of the rectifier structure 30.

[0159] The outer embedded electrode 32 may have a single-layer structure including a single conductive film, or a laminated structure including multiple conductive films. The single conductive film or multiple conductive films may include either a metal film or a non-metallic conductive film, or both.

[0160] The outer embedded electrode 32 may include a metal film containing at least one of the following: magnesium (Mg), aluminum (Al), titanium (Ti), vanadium (V), chromium (Cr), manganese (Mn), cobalt (Co), nickel (Ni), copper (Cu), zirconium (Zr), niobium (Nb), molybdenum (Mo), palladium (Pd), silver (Ag), indium (In), tin (Sn), tantalum (Ta), tungsten (W), platinum (Pt), and gold (Au).

[0161] The outer embedded electrode 32 may include an alloy film containing at least one of the following: magnesium alloy, aluminum alloy, titanium alloy, vanadium alloy, chromium alloy, manganese alloy, cobalt alloy, nickel alloy, copper alloy, zirconium alloy, niobium alloy, molybdenum alloy, palladium alloy, silver alloy, indium alloy, tin alloy, tantalum alloy, tungsten alloy, platinum alloy, and gold alloy.

[0162] The outer embedded electrode 32 may include a conductive film containing conductive polysilicon as an example of a non-metallic conductor. The conductive film may contain either p-type conductive polysilicon or n-type conductive polysilicon, or both. The outer embedded electrode 32 may contain the same or a different conductive material as the conductive material of the embedded electrode 18.

[0163] The outer embedded electrode 32 is directly embedded in the outer trench 31 without an insulating film and is mechanically and electrically connected to the wall surface (chip 2) of the outer trench 31. Specifically, the outer embedded electrode 32 has a portion that is electrically connected to the outer well region 25 and the outer contact region 26 in the region above the bottom of the outer well region 25, and a portion that forms a heterojunction (Schottky junction) with the second semiconductor layer 7 in the region below the bottom of the outer well region 25.

[0164] In this embodiment, the outer embedded electrode 32 has a laminated structure including multiple electrodes. Specifically, the outer embedded electrode 32 includes a base electrode 33 and a main electrode 34. The base electrode 33 is formed as a barrier electrode for the second semiconductor layer 7 and has a single-layer structure consisting of a single conductive film or a laminated structure consisting of multiple conductive films.

[0165] In this embodiment, the base electrode 33 has a laminated structure including a first electrode 33a and a second electrode 33b (see Figure 11A). The first electrode 33a consists of a metal film containing any one of the aforementioned metals or an alloy film containing any one of the aforementioned alloys. In this embodiment, the first electrode 33a consists of a titanium film.

[0166] The first electrode 33a covers the walls of the outer trench 31 in a film-like manner, following the shape of the outer trench walls (first side wall, second side wall, and bottom wall). The first electrode 33a defines a recess space within the outer trench 31 along the walls of the outer trench 31. In this configuration, the first electrode 33a has a portion that covers the open end of the outer trench 31.

[0167] The first electrode 33a is mechanically and electrically connected to the wall surface of the outer trench 31. The first electrode 33a is mechanically and electrically connected to the second semiconductor layer 7, the outer well region 25, and the outer contact region 26. The first electrode 33a forms a heterojunction (Schottky junction) with the second semiconductor layer 7.

[0168] The first electrode 33a may have a thickness of 10 nm to 200 nm. The thickness of the first electrode 33a may have a value that falls within at least one of the following ranges: 10 nm to 25 nm, 25 nm to 50 nm, 50 nm to 75 nm, 75 nm to 100 nm, 100 nm to 125 nm, 125 nm to 150 nm, 150 nm to 175 nm, and 175 nm to 200 nm.

[0169] The second electrode 33b consists of a metal film containing one of the aforementioned metals or an alloy film containing one of the aforementioned alloys. The second electrode 33b is made of a different conductor than the first electrode 33a. In this embodiment, the second electrode 33b consists of a titanium nitride film (titanium alloy film).

[0170] The second electrode 33b is stacked on top of the first electrode 33a. The second electrode 33b covers the walls of the outer trench 31 (first side wall, second side wall, and bottom wall) in a film-like manner via the first electrode 33a, and defines a recess space along the walls of the outer trench 31 within the outer trench 31.

[0171] The second electrode 33b is electrically connected to the second semiconductor layer 7, the outer well region 25, and the outer contact region 26 via the first electrode 33a. In this embodiment, the second electrode 33b has a portion that covers the open end of the outer trench 31 via the first electrode 33a. In this embodiment, the second electrode 33b has a thickness greater than the thickness of the first electrode 33a. The thickness of the second electrode 33b may be less than the thickness of the first electrode 33a.

[0172] The thickness of the second electrode 33b may be 10 nm or more and 300 nm or less. The thickness of the second electrode 33b may have a value that falls within at least one of the following ranges: 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, 125 nm or more and 150 nm or less, 150 nm or more and 175 nm or less, 175 nm or more and 200 nm or less, 200 nm or more and 225 nm or less, 225 nm or more and 250 nm or less, 250 nm or more and 275 nm or more and 300 nm or less.

[0173] The main electrode 34 consists of a metal film containing one of the aforementioned metals, an alloy film containing one of the aforementioned alloys, or a nonmetallic conductive film containing one of the aforementioned nonmetallic conductors. The main electrode 34 is made of a different conductor than the first electrode 33a and the second electrode 33b. In this embodiment, the main electrode 34 is made of tungsten. In other words, the main electrode 34 contains a conductive material different from the conductive material of the embedded electrode 18. Of course, the main electrode 34 may also contain the same type of conductive material as the conductive material of the embedded electrode 18.

[0174] The main electrode 34 is embedded in the outer trench 31 via the base electrode 33. The main electrode 34 has a portion located on the opening side with respect to the depth position of the middle part of the outer trench 31, and a portion located on the bottom wall side with respect to the depth position of the middle part of the outer trench 31. The main electrode 34 has a portion located on the first main surface 3 side with respect to the bottom of the outer well region 25, and a portion located on the bottom wall side of the outer trench 31 with respect to the bottom of the outer well region 25.

[0175] The main electrode 34 has a portion that faces the second semiconductor layer 7, the outer well region 25, and the outer contact region 26 via the base electrode 33, and is electrically connected to the second semiconductor layer 7, the outer well region 25, and the outer contact region 26 via the base electrode 33. The main electrode 34 faces the embedded electrode 18 and the embedded insulator 19 in the horizontal direction.

[0176] The main electrode 34 has an electrode surface exposed from the outer trench 31. The electrode surface is formed with a gap from the height of the first main surface 3 towards the bottom wall side of the outer trench 31, exposing the first main surface 3. The electrode surface exposes the base electrode 33 from the opening end of the outer trench 31. The electrode surface is located on the first main surface 3 side with respect to the bottom of the outer well region 25.

[0177] The electrode surface is located on the opening side of the outer trench 31 with respect to the depth position of the middle part of the outer trench 31. The electrode surface may also be located on the bottom wall side of the outer trench 31 with respect to the depth position of the middle part of the outer trench 31. The electrode surface is located on the opening side with respect to the depth position of the bottom of the outer contact region 26. The electrode surface may also be located on the bottom wall side with respect to the depth position of the bottom of the outer contact region 26.

[0178] The electrode surface of the main electrode 34 may be located on the first main surface 3 side of the height position of the electrode surface of the embedded electrode 18. The electrode surface of the main electrode 34 may be located on the bottom wall side of the height position of the electrode surface of the embedded electrode 18. The electrode surface of the main electrode 34 may have a recess that is indented toward the bottom wall side.

[0179] The ratio of the thickness of the main electrode 34 to the depth of the outer trench 31 may be 0.5 or more and 1 or less. The ratio may have a value that falls within at least one of the following ranges: 0.5 or more and 0.6 or less, 0.6 or more and 0.7 or less, 0.7 or more and 0.8 or less, 0.8 or more and 0.9 or less, and 0.9 or more and 1 or less. The ratio is preferably 0.8 or more.

[0180] The semiconductor device 1A includes one or more (one in this embodiment) p-type trench well regions 35 formed in the peripheral region (outer region 9) of the second semiconductor layer 7, below the rectification structure 30.

[0181] The trench well region 35 has a p-type impurity concentration lower than that of the outer contact region 26. The p-type impurity concentration in the trench well region 35 may be higher or lower than that of the outer well region 25. The p-type impurity concentration in the trench well region 35 may be approximately equal to that of the well region 22. The p-type impurity concentration in the trench well region 35 may be higher or lower than that of the well region 22.

[0182] The p-type impurity concentration in the trench well region 35 may be higher or lower than the p-type impurity concentration in the body region 10. The p-type impurity concentration in the trench well region 35 is lower than the p-type impurity concentration in the contact region 21. The trench well region 35 forms a bipolar diode DB with the second semiconductor layer 7.

[0183] The trench well region 35 is formed in a region along the bottom wall of the rectifier structure 30, and replaces the conductivity type of the second semiconductor layer 7 from n-type to p-type. In a plan view, the trench well region 35 extends in a band shape following the direction of extension of the rectifier structure 30.

[0184] In this embodiment, the trench well region 35 is formed as a polygonal ring (a quadrangular ring in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view, and surrounds the active region 8 (a plurality of gate structures 15). The trench well region 35 may have an edge portion that connects a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y in an arc shape (preferably a quarter-circular arc shape).

[0185] The trench well region 35 may have a width approximately equal to the width of the flow straightening structure 30. The trench well region 35 may have a width smaller than the width of the flow straightening structure 30 and be formed inward from the first and second side walls of the flow straightening structure 30. The trench well region 35 may have a width larger than the width of the flow straightening structure 30 and have portions that protrude outward from the first and second side walls of the flow straightening structure 30.

[0186] The trench well region 35 is formed in a thickness range between the bottom of the second semiconductor layer 7 and the bottom wall of the rectifier structure 30. In this embodiment, the trench well region 35 extends horizontally. The trench well region 35 may also extend vertically in the thickness direction Z. The trench well region 35 is formed with a gap from the bottom of the second semiconductor layer 7 toward the bottom wall of the rectifier structure 30 and faces the first semiconductor layer 6 via a portion of the second semiconductor layer 7.

[0187] The trench well region 35 has an upper end located on the bottom wall side of the rectifying structure 30 and a bottom located on the bottom side of the second semiconductor layer 7. The upper end of the trench well region 35 is formed with a gap between the bottom of the outer well region 25 and the bottom wall side of the rectifying structure 30. The upper end of the trench well region 35 is connected to the bottom wall of the rectifying structure 30.

[0188] Specifically, the upper end of the trench well region 35 is mechanically and electrically connected to the rectifier structure 30 (outer embedded electrode 32). In other words, the trench well region 35 is electrically connected to the outer well region 25 and the outer contact region 26 via the rectifier structure 30 (outer embedded electrode 32).

[0189] The upper end of the trench well region 35 may be formed with a gap between it and the bottom wall of the rectifier structure 30, towards the bottom of the second semiconductor layer 7. The upper end of the trench well region 35 may bulge out on both sides of the rectifier structure 30.

[0190] The bottom of the trench well region 35 is formed with a gap between it and the first main surface 3 from the bottom of the second semiconductor layer 7, and faces the first semiconductor layer 6 through a portion of the second semiconductor layer 7. The bottom of the trench well region 35 may be located on the bottom wall side of the rectifier structure 30 or on the bottom side of the second semiconductor layer 7 with respect to the depth position of the middle portion of the second semiconductor layer 7.

[0191] In this embodiment, the bottom of the trench well region 35 is located at approximately the same depth as the bottoms of the multiple field regions 27. The bottom of the trench well region 35 may be located on the bottom wall side of the rectifier structure 30 or on the bottom side of the second semiconductor layer 7 with respect to the depth position of the bottoms of the multiple field regions 27.

[0192] In this embodiment, the bottom of the trench well region 35 is located on the bottom side of the second semiconductor layer 7 than the depth position of the bottom of the well region 22. The bottom of the trench well region 35 may be located at approximately the same depth as the bottom of the well region 22. The bottom of the trench well region 35 may be located on the bottom wall side of the rectifying structure 30 than the depth position of the bottom of the well region 22.

[0193] In this configuration, the depth of the trench well region 35 relative to the bottom wall of the flow straightening structure 30 is smaller than the depth of the flow straightening structure 30 relative to the first main surface 3. The depth of the trench well region 35 may be larger than the depth of the flow straightening structure 30 relative to the first main surface 3.

[0194] The depth of the trench well region 35 may be 0.5 μm or more and 5 μm or less. The depth of the trench well region 35 may have a value that falls within at least one of the following ranges: 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or more and 4 μm or more and 4.5 μm or more and 5 μm or less.

[0195] The trench well region 35 forms a pn junction with the second semiconductor layer 7. This forms a bipolar diode DB that includes the second semiconductor layer 7 as the cathode region and the trench well region 35 as the anode region.

[0196] The trench well region 35 may be formed by a single p-type impurity region extending in the thickness direction Z. The trench well region 35 may be formed by a plurality of p-type impurity regions connected to each other in the thickness direction Z. The semiconductor device 1A may include a plurality of trench well regions 35. In this case, the plurality of trench well regions 35 may be formed at intervals following the direction of extension of the rectification structure 30 in a plan view.

[0197] Referring again to Figure 10, the semiconductor device 1A includes an insulating interlayer film 40 that selectively covers the first main surface 3. In this embodiment, the interlayer film 40 has a laminated structure including a first interlayer film 41 and a second interlayer film 42. The first interlayer film 41 may be referred to as the "main surface insulating film," and the second interlayer film 42 may be referred to as the "upper insulating film."

[0198] The first interlayer film 41 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The first interlayer film 41 may include a silicon oxide film containing the oxide of the chip 2 (second semiconductor layer 7). The first interlayer film 41 may include a silicon oxide film containing oxides other than the oxide of the chip 2. The first interlayer film 41 may include an insulator of the same type as the insulating film 17.

[0199] The first interlayer film 41 selectively covers the first main surface 3 in a film-like manner in the active region 8 and the outer region 9. The first interlayer film 41 covers the first main surface 3 at the periphery of the active region 8, exposing a plurality of gate structures 15. Specifically, the first interlayer film 41 is connected to a plurality of insulating films 17, exposing a plurality of embedded insulators 19. In other words, the first interlayer film 41 forms a single insulating film integral with the plurality of insulating films 17.

[0200] The first interlayer membrane 41 covers the outer well region 25, the outer contact region 26, and multiple field regions 27 in the outer region 9. The first interlayer membrane 41 is continuous with the first to fourth side surfaces 5A to 5D. The first interlayer membrane 41 may be formed with an inward gap from the first to fourth side surfaces 5A to 5D, exposing the peripheral edge of the first main surface 3.

[0201] The first interlayer film 41 may have a thickness approximately equal to the thickness of the plurality of insulating films 17. The thickness of the first interlayer film 41 may be 10 nm or more and 250 nm or less. The thickness of the first interlayer film 41 may have a value that falls within at least one of the following ranges: 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, 125 nm or more and 150 nm or less, 150 nm or more and 175 nm or less, 175 nm or more and 200 nm or less, 200 nm or more and 225 nm or less, and 225 nm or more and 250 nm or less.

[0202] The second interlayer film 42 may contain at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The second interlayer film 42 may have a single-layer structure or a laminated structure containing at least one of an NSG film, a PSG film, and a BPSG film. It is preferable that the second interlayer film 42 has a single-layer structure or a laminated structure containing at least an NSG film.

[0203] The second interlayer film 42 may have a laminated structure including an NSG film and a PSG film stacked in this order from the chip 2 side. The second interlayer film 42 may have a laminated structure including an NSG film, a PSG film, and a BPSG film stacked in this order from the chip 2 side. The second interlayer film 42 may contain an insulator of the same type as the embedded insulator 19. The second interlayer film 42 may contain an insulator of the same type as the first interlayer film 41.

[0204] The second interlayer membrane 42 covers the first interlayer membrane 41 in a film-like manner in the active region 8 and the outer region 9. The second interlayer membrane 42 covers a plurality of gate structures 15 at the periphery of the active region 8. Specifically, the second interlayer membrane 42 penetrates a plurality of trenches 16 from above the first interlayer membrane 41 and covers a plurality of embedded electrodes 18 within the plurality of trenches 16.

[0205] The second interlayer membrane 42 is connected to a plurality of embedded insulators 19 within the trench 16. In this embodiment, the second interlayer membrane 42 is integrally formed with the plurality of embedded insulators 19. The connection portion of the second interlayer membrane 42 to the plurality of embedded insulators 19 may be considered as part of the plurality of embedded insulators 19, or as part of the second interlayer membrane 42.

[0206] The second interlayer membrane 42 covers the first main surface 3 via the first interlayer membrane 41 in the outer region 9. Specifically, the second interlayer membrane 42 covers the outer well region 25, the outer contact region 26, and a plurality of field regions 27 via the first interlayer membrane 41. The second interlayer membrane 42 is continuous with the first to fourth side surfaces 5A to 5D. The outer edge of the second interlayer membrane 42 is formed with a gap inward from the first to fourth side surfaces 5A to 5D, and may expose either or both of the peripheral edge of the first main surface 3 and the first interlayer membrane 41.

[0207] The second interlayer membrane 42 has a thickness greater than the thickness of the first interlayer membrane 41. The thickness of the second interlayer membrane 42 may be 0.1 μm or more and 5 μm or less. The thickness of the second interlayer membrane 42 may have a value that falls within at least one of the following ranges: 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or more and 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0208] The semiconductor device 1A includes one or more (one in this embodiment) gate wirings 43 selectively routed within the interlayer film 40 in the outer region 9. The gate wirings 43 are electrically connected to a plurality of gate structures 15 and provide gate potentials to the plurality of gate structures 15. The gate wirings 43 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon. Preferably, the gate wirings 43 have the same conductive material as the embedded electrode 18.

[0209] The gate wiring 43 is positioned on the first interlayer film 41 and covered by the second interlayer film 42. The gate wiring 43 is positioned on the periphery of the first main surface 3, spaced apart from the periphery of the first main surface 3 and the multiple gate structures 15. The gate wiring 43 is formed spaced apart from the multiple field regions 27 (the innermost field region 27) toward the active region 8.

[0210] The gate wiring 43 is formed with a gap between the outer edge of the outer well region 25 and the active region 8. The gate wiring 43 is formed with a gap between the outer edge of the outer contact region 26 and the active region 8. The gate wiring 43 is formed with a gap between the rectifier structure 30 and the active region 8. In a plan view, the gate wiring 43 extends in a strip shape along the active region 8.

[0211] In this embodiment, the gate wiring 43 is formed in a polygonal ring shape (a quadrilateral ring shape in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view, and surrounds the active region 8 (a plurality of gate structures 15). The gate wiring 43 may also be formed in the shape of an ended strip. The gate wiring 43 may have an edge portion that connects the portion extending in a strip shape in the first direction X and the portion extending in a strip shape in the second direction Y in an arc shape (preferably a quarter-circular arc shape).

[0212] The gate wiring 43 has an inner edge on the inner side of the first main surface 3 and an outer edge on the peripheral side of the first main surface 3. The inner edge of the gate wiring 43 is mechanically and electrically connected to the ends of the multiple gate structures 15. Specifically, the inner edge of the gate wiring 43 enters into the multiple trenches 16 from above the first interlayer membrane 41 and is mechanically and electrically connected to the multiple embedded electrodes 18 within the multiple trenches 16.

[0213] In this configuration, the gate wiring 43 is formed integrally with the multiple buried electrodes 18 as the lead-out portion of the multiple buried electrodes 18. The connection portion of the gate wiring 43 to the multiple buried electrodes 18 may be considered as part of the multiple buried electrodes 18, or as part of the gate wiring 43.

[0214] The semiconductor device 1A includes one or more (one in this embodiment) source openings 44 formed in the interlayer film 40 in the active region 8. The source openings 44 penetrate the interlayer film 40 and expose multiple gate structures 15 collectively. Specifically, the source openings 44 expose multiple embedded insulators 19, body regions 10, multiple source regions 20, and multiple contact regions 21.

[0215] The semiconductor device 1A includes one or more (in this embodiment, more than one) gate openings 45 formed in the interlayer film 40 in the outer region 9. The multiple gate openings 45 penetrate the interlayer film 40 and selectively expose the gate wiring 43.

[0216] In this configuration, the multiple gate openings 45 extend in a strip-like shape following the direction of extension of the gate wiring 43. The multiple gate openings 45 may be formed at intervals in the direction of extension of the gate wiring 43. The multiple gate openings 45 may be formed in a polygonal or circular shape in plan view. The multiple gate structures 15 may be formed in a square or hexagonal shape in plan view.

[0217] The multiple gate openings 45 may have portions that extend in a strip shape in a first direction X and portions that extend in a strip shape in a second direction Y when viewed from above. The multiple gate openings 45 may have edge portions that connect the portions that extend in the first direction X and the portions that extend in the second direction Y in an arc shape (preferably a quarter arc shape) when viewed from above. Of course, the semiconductor device 1A may include one gate opening 45 that extends in a strip shape along the gate wiring 43.

[0218] The semiconductor device 1A includes one or more (in this embodiment, one) outer openings 46 formed in the interlayer film 40. In this embodiment, the outer openings 46 include a first opening 46a formed in the first interlayer film 41 and a second opening 46b formed in the second interlayer film 42. The first opening 46a may be referred to as the "lower opening" or "first outer opening." The second opening 46b may be referred to as the "upper opening" or "second outer opening."

[0219] The first opening 46a penetrates the first interlayer film 41 and selectively exposes the rectifier structure 30. The first opening 46a is formed with a gap from the gate wiring 43 toward the rectifier structure 30, and with a gap from the periphery of the first main surface 3 toward the rectifier structure 30. The first opening 46a is formed with a gap from multiple field regions 27 (the innermost field region 27) toward the rectifier structure 30.

[0220] The first opening 46a extends in a strip shape following the direction of extension of the rectifying structure 30. The first opening 46a has a portion that extends in a strip shape in a first direction X and a portion that extends in a strip shape in a second direction Y. In this embodiment, the first opening 46a is formed as an endless polygonal ring (for example, a quadrilateral ring) having four sides parallel to the periphery of the first main surface 3, and surrounds the active region 8 (multiple gate structures 15).

[0221] The first opening 46a may be formed in the shape of a strip with an end. The first opening 46a may have an edge portion that connects the portion extending in a strip shape in the first direction X and the portion extending in a strip shape in the second direction Y in an arc shape (preferably a quarter arc shape) when viewed from above.

[0222] In this configuration, the first opening 46a has a width greater than or equal to the width of the rectifying structure 30 in cross-sectional view, exposing the entire upper end of the rectifying structure 30 (the electrode surface of the outer embedded electrode 32). In this configuration, the first opening 46a has a width greater than the width of the rectifying structure 30, exposing the portion of the first main surface 3 located around (both sides of) the rectifying structure 30.

[0223] In this configuration, the first opening 46a has a width less than or equal to the width of the outer contact region 26 and is formed on the side of the flow straightening structure 30 that is closer to the inner and outer edges of the outer contact region 26. Of course, the first opening 46a may have a width greater than the width of the outer contact region 26, exposing part or all of the outer contact region 26.

[0224] The first opening 46a has a first wall portion on the inner side of the first main surface 3 and a second wall portion on the peripheral side of the first main surface 3. The first wall portion is spaced apart from the first side wall of the flow straightening structure 30 on the inner side of the first main surface 3. In this embodiment, the first wall portion is located on the inner edge side of the outer contact region 26, exposing the inner edge of the outer contact region 26 between itself and the first side wall. The first wall portion may be located on the inner side of the first main surface 3 beyond the inner edge of the outer contact region 26 and may be located above the outer well region 25.

[0225] The second wall portion is separated from the second side wall of the rectifying structure 30 at a distance from the peripheral edge of the first main surface 3. In this configuration, the second wall portion is located on the outer edge side of the outer contact region 26, exposing the outer edge of the outer contact region 26 between itself and the second side wall. The second wall portion may be located on the peripheral edge side of the first main surface 3, further than the inner edge of the outer contact region 26, and may be located above the outer well region 25.

[0226] The second opening 46b penetrates the second interlayer film 42 at a position overlapping part or all of the first opening 46a, selectively exposing the rectifier structure 30. In other words, the second opening 46b together with the first opening 46a forms a single outer opening 46. The second opening 46b is formed with a gap from the gate wiring 43 toward the rectifier structure 30, and with a gap from the periphery of the first main surface 3 toward the rectifier structure 30. The second opening 46b is formed with a gap from multiple field regions 27 (the innermost field region 27) toward the rectifier structure 30.

[0227] The second opening 46b extends in a strip shape following the direction of extension of the rectifying structure 30. The second opening 46b has a portion that extends in a strip shape in the first direction X and a portion that extends in a strip shape in the second direction Y. In this embodiment, the second opening 46b is formed as an endless polygonal ring (for example, a quadrilateral ring) having four sides parallel to the periphery of the first main surface 3, and surrounds the active region 8 (multiple gate structures 15).

[0228] The second opening 46b may be formed in the shape of an ended strip. The second opening 46b may have an edge portion that connects the portion extending in the strip shape in the first direction X and the portion extending in the strip shape in the second direction Y in an arc shape (preferably a quarter arc shape) when viewed in plan. In this embodiment, the second opening 46b is formed in a tapered shape in which the opening width gradually narrows from the opening end toward the first main surface 3 when viewed in cross-section. The second opening 46b may be formed substantially perpendicular to the first main surface 3 when viewed in cross-section.

[0229] In this configuration, the second opening 46b has a width greater than or equal to the width of the rectifier structure 30, exposing the entire upper end of the rectifier structure 30 (the electrode surface of the outer embedded electrode 32). In this configuration, the second opening 46b has a width greater than the width of the rectifier structure 30, exposing the portion of the first main surface 3 located around (both sides of) the rectifier structure 30.

[0230] In this configuration, the second opening 46b has a width less than or equal to the width of the outer contact region 26 and is formed on the side of the flow straightening structure 30 that is closer to the inner and outer edges of the outer contact region 26. Of course, the second opening 46b may have a width greater than the width of the outer contact region 26, exposing part or all of the outer contact region 26.

[0231] In this embodiment, the second opening 46b has an opening end width greater than or equal to the width of the first opening 46a. Specifically, the opening end width of the second opening 46b is greater than the width of the first opening 46a. The opening end width of the second opening 46b may be approximately equal to the width of the first opening 46a. The opening end width of the second opening 46b may be less than the width of the first opening 46a. The opening end width of the second opening 46b may be greater than or less than the thickness of the interlayer film 40.

[0232] The second opening 46b has a first wall portion on the inner side of the first main surface 3 and a second wall portion on the peripheral side of the first main surface 3. The first wall portion is spaced apart from the first side wall of the flow straightening structure 30 on the inner side of the first main surface 3. The first wall portion is located on the inner edge side of the outer contact region 26 and exposes the inner edge of the outer contact region 26 between itself and the first side wall. The first wall portion may be located on the inner side of the first main surface 3 beyond the inner edge of the outer contact region 26 and may be located above the outer well region 25.

[0233] The second wall portion is partitioned from the second side wall of the flow straightening structure 30 at a distance from the peripheral edge of the first main surface 3. The second wall portion is located on the outer edge side of the outer contact region 26, exposing the outer edge of the outer contact region 26 between itself and the second side wall. The second wall portion may be located on the peripheral edge side of the first main surface 3, further than the outer edge of the outer contact region 26, and may be located above the outer well region 25.

[0234] In this configuration, the second opening 46b is connected to the first opening 46a. That is, the first wall of the second opening is connected to the first wall of the first opening 46a, and the second wall of the second opening is connected to the second wall of the first opening 46a.

[0235] The first wall of the second opening 46b may be located closer to the flow straightening structure 30 than the first wall of the first opening 46a. In other words, the second interlayer membrane 42 may cover the first wall of the first opening 46a. The second wall of the second opening 46b may be located closer to the flow straightening structure 30 than the second wall of the first opening 46a. In other words, the second interlayer membrane 42 may cover the second wall of the first opening 46a.

[0236] The semiconductor device 1A may include a plurality of outer openings 46. In this case, the plurality of outer openings 46 are formed at intervals in the direction of extension of the rectifier structure 30 and include a first opening 46a and a second opening 46b, respectively. The plurality of outer openings 46 may extend in a strip shape following the direction of extension of the rectifier structure 30. The plurality of outer openings 46 may be formed in a polygonal or circular shape in plan view. For example, the plurality of outer openings 46 may be formed in a square or hexagonal shape in plan view.

[0237] The semiconductor device 1A includes a source electrode 50 located in the inner portion (active region 8) of the first main surface 3. The source electrode 50 may also be referred to as the "first main electrode," "first terminal (electrode)," "first pad (electrode)," "source pad electrode," etc. The source electrode 50 is located on the interlayer film 40.

[0238] In this embodiment, the source electrode 50 has a first pad portion 50a, a second pad portion 50b, and a third pad portion 50c. The first pad portion 50a has a relatively large surface area and forms the main body of the source electrode 50. In this embodiment, the first pad portion 50a is formed in a polygonal shape (a quadrilateral shape in this embodiment) with four sides parallel to the periphery of the first main surface 3 in a plan view, and is offset towards the fourth side surface 5D relative to the central part of the first main surface 3.

[0239] The second pad portion 50b has a flat area less than that of the first pad portion 50a and extends in a strip-like (square-shaped) manner from one end of the first pad portion 50a in the first direction X (the end on the first side surface 5A side) toward the fourth side surface 5D. The third pad portion 50c has a flat area less than that of the first pad portion 50a and extends in a strip-like (square-shaped) manner from the other end of the first pad portion 50a in the second direction Y (the end on the third side surface 5C side) toward the fourth side surface 5D, and faces the second pad portion 50b in the second direction Y.

[0240] The flat area of ​​the third pad portion 50c may be approximately equal to the flat area of ​​the second pad portion 50b. The flat area of ​​the third pad portion 50c may be larger or smaller than the flat area of ​​the second pad portion 50b. Either or both of the second pad portion 50b and the third pad portion 50c may be used as terminal portions for current monitoring.

[0241] The source electrode 50 may have only one of the second pad portion 50b and the third pad portion 50c. The source electrode 50 may consist only of the first pad portion 50a and may not have both the second pad portion 50b and the third pad portion 50c.

[0242] The source electrode 50 enters the source opening 44 from above the interlayer film 40 and collectively covers the first main surface 3 and the multiple gate structures 15 within the source opening 44 in a film-like manner. The source electrode 50 is electrically insulated from the multiple gate structures 15 within the source opening 44 and is mechanically and electrically connected to the body region 10, the multiple source regions 20, and the multiple contact regions 21.

[0243] The source electrode 50 has a peripheral portion that faces the ends of the multiple gate structures 15 via the interlayer film 40. The peripheral portion of the source electrode 50 is drawn out from the active region 8 to the outer region 9 and faces the first main surface 3 via the interlayer film 40 and gate wiring 43. The peripheral portion of the source electrode 50 faces the outer well region 25 in the stacking direction.

[0244] The peripheral edge of the source electrode 50 is formed with a gap between it and the active region 8 from the multiple field regions 27. The peripheral edge of the source electrode 50 is formed with a gap between it and the active region 8 from the outer edge of the outer well region 25. The peripheral edge of the source electrode 50 is formed with a gap between it and the active region 8 from the outer edge of the outer contact region 26.

[0245] The peripheral edge of the source electrode 50 is formed with a gap between it and the rectifier structure 30 towards the active region 8. The peripheral edge of the source electrode 50 is formed with a gap between it and the inner edge of the outer contact region 26 towards the active region 8. The peripheral edge of the source electrode 50 is formed with a gap between it and the outer edge of the gate wiring 43 towards the active region 8. The peripheral edge of the source electrode 50 may be located on top of the outer contact region 26.

[0246] The source electrode 50 may have a single-layer structure comprising a single metal film, or a multilayer structure comprising multiple metal films. The source electrode 50 may contain a metal film comprising at least one of the following: magnesium (Mg), aluminum (Al), titanium (Ti), vanadium (V), chromium (Cr), manganese (Mn), cobalt (Co), nickel (Ni), copper (Cu), zirconium (Zr), niobium (Nb), molybdenum (Mo), palladium (Pd), silver (Ag), indium (In), tin (Sn), tantalum (Ta), tungsten (W), platinum (Pt), and gold (Au).

[0247] The source electrode 50 may include an alloy film containing at least one of the following: magnesium alloy, aluminum alloy, titanium alloy, vanadium alloy, chromium alloy, manganese alloy, cobalt alloy, nickel alloy, copper alloy, zirconium alloy, niobium alloy, molybdenum alloy, palladium alloy, silver alloy, indium alloy, tin alloy, tantalum alloy, tungsten alloy, platinum alloy, and gold alloy.

[0248] In this embodiment, the source electrode 50 has a laminated structure including a base electrode 51 and a main electrode 52 stacked in this order from the first main surface 3 side. The base electrode 51 is formed as a barrier electrode for the second semiconductor layer 7 and has a single-layer structure consisting of a single metal film or a laminated structure consisting of multiple metal films.

[0249] In this embodiment, the base electrode 51 has a laminated structure including a first electrode 51a and a second electrode 51b. The first electrode 51a consists of a metal film containing any one of the aforementioned metals or an alloy film containing any one of the aforementioned alloys. In this embodiment, the first electrode 51a consists of a titanium film. In other words, the first electrode 51a is made of the same type of conductor as the first electrode 33a of the outer embedded electrode 32. Of course, the first electrode 51a may be made of a different conductor than the first electrode 33a.

[0250] The first electrode 51a extends from above the interlayer film 40 into the source opening 44. The first electrode 51a has a portion that covers the interlayer film 40 in a film-like manner, a portion that covers the wall surface of the source opening 44 in a film-like manner, and a portion that covers the first main surface 3 in a film-like manner within the source opening 44.

[0251] The first electrode 51a is electrically insulated from the multiple gate structures 15 within the source opening 44 and is mechanically and electrically connected to the body region 10, the multiple source regions 20, and the multiple contact regions 21.

[0252] The first electrode 51a covers the insulating surfaces of the multiple embedded insulators 19 and is electrically isolated from the multiple embedded electrodes 18 by the multiple embedded insulators 19. In this configuration, the first electrode 51a has portions that extend from the first main surface 3 into the multiple trenches 16 and are mechanically and electrically connected to the multiple source regions 20 and the multiple contact regions 21 via the side walls and open ends of the multiple trenches 16.

[0253] The first electrode 51a has a peripheral portion that faces the ends of the multiple gate structures 15 via the interlayer film 40. The peripheral portion of the first electrode 51a is drawn out from the active region 8 to the outer region 9 and faces the first main surface 3 via the interlayer film 40 and gate wiring 43.

[0254] The peripheral edge of the first electrode 51a faces the outer well region 25 in the stacking direction. The peripheral edge of the first electrode 51a is formed with a gap between it and the active region 8 from the multiple field regions 27. The peripheral edge of the first electrode 51a is formed with a gap between it and the active region 8 from the outer edge of the outer well region 25. The peripheral edge of the first electrode 51a is formed with a gap between it and the active region 8 from the outer edge of the outer contact region 26.

[0255] The peripheral edge of the first electrode 51a is formed with a gap between it and the rectifier structure 30 towards the active region 8. The peripheral edge of the first electrode 51a is formed with a gap between it and the inner edge of the outer contact region 26 towards the active region 8. The peripheral edge of the first electrode 51a is formed with a gap between it and the outer edge of the gate wiring 43 towards the active region 8. The peripheral edge of the first electrode 51a may be located on the outer contact region 26.

[0256] The first electrode 51a has a thickness less than the thickness of the interlayer film 40. The thickness of the first electrode 51a may be approximately equal to the thickness of the first electrode 33a. The thickness of the first electrode 51a may be greater than or less than the thickness of the first electrode 33a.

[0257] The thickness of the first electrode 51a may be 10 nm or more and 100 nm or less. The thickness of the first electrode 51a may have a value that falls within at least one of the following ranges: 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, 125 nm or more and 150 nm or less, 150 nm or more and 175 nm or more and 200 nm or less.

[0258] The second electrode 51b consists of a metal film containing one of the aforementioned metals or an alloy film containing one of the aforementioned alloys. The second electrode 51b consists of a different metal film or alloy film than the first electrode 51a. In this embodiment, the second electrode 51b consists of a titanium nitride film (titanium alloy film). In other words, the second electrode 51b consists of the same type of conductor as the second electrode 33b of the outer embedded electrode 32. Of course, the second electrode 51b may be made of a different conductor than the second electrode 33b.

[0259] The second electrode 51b covers the first electrode 51a in a film-like manner and penetrates the source opening 44 from above the interlayer film 40. The second electrode 51b has a portion that covers the interlayer film 40 in a film-like manner via the first electrode 51a, a portion that covers the wall surface of the source opening 44 in a film-like manner via the first electrode 51a, and a portion that covers the first main surface 3 in a film-like manner via the first electrode 51a.

[0260] The second electrode 51b is electrically insulated from the multiple gate structures 15 within the source opening 44 and is electrically connected to the body region 10, the multiple source regions 20, and the multiple contact regions 21 via the first electrode 51a.

[0261] In this configuration, the second electrode 51b enters the plurality of trenches 16 from the first main surface 3 and covers the side walls and open ends of the plurality of trenches 16 via the first electrode 51a. The second electrode 51b has a portion that is electrically connected to the plurality of source regions 20 and the plurality of contact regions 21 via the first electrode 51a at the open ends of the plurality of trenches 16.

[0262] The second electrode 51b has a peripheral edge that faces the ends of the multiple gate structures 15 via the interlayer film 40 and the first electrode 51a. The peripheral edge of the second electrode 51b is drawn out from the active region 8 to the outer region 9 and faces the first main surface 3 via the first interlayer film 41, gate wiring 43, interlayer film 40 and the first electrode 51a.

[0263] The peripheral edge of the second electrode 51b faces the outer well region 25 in the stacking direction. The peripheral edge of the second electrode 51b is formed with a gap between it and the active region 8 from the multiple field regions 27. The peripheral edge of the second electrode 51b is formed with a gap between it and the active region 8 from the outer edge of the outer well region 25. The peripheral edge of the second electrode 51b is formed with a gap between it and the active region 8 from the outer edge of the outer contact region 26.

[0264] The peripheral edge of the second electrode 51b is formed with a gap between it and the rectification structure 30 towards the active region 8. The peripheral edge of the second electrode 51b is formed with a gap between it and the inner edge of the outer contact region 26 towards the active region 8. The peripheral edge of the second electrode 51b is formed with a gap between it and the outer edge of the gate wiring 43 towards the active region 8. The peripheral edge of the second electrode 51b may be located on the outer contact region 26.

[0265] The second electrode 51b has a thickness less than the thickness of the interlayer film 40. In this embodiment, the thickness of the second electrode 51b is greater than the thickness of the first electrode 51a. The thickness of the second electrode 51b may be less than the thickness of the first electrode 51a. In this embodiment, the thickness of the second electrode 51b is greater than the thickness of the first electrode 33a. The thickness of the second electrode 51b may be less than the thickness of the first electrode 33a. The thickness of the second electrode 51b may be approximately equal to the thickness of the second electrode 33b. The thickness of the second electrode 51b may be greater than or less than the thickness of the second electrode 33b.

[0266] The thickness of the second electrode 51b may be 10 nm or more and 300 nm or less. The thickness of the second electrode 51b may have a value that falls within at least one of the following ranges: 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, 125 nm or more and 150 nm or less, 150 nm or more and 175 nm or less, 175 nm or more and 200 nm or less, 200 nm or more and 225 nm or less, 225 nm or more and 250 nm or less, 250 nm or more and 275 nm or more and 300 nm or less.

[0267] The main electrode 52 consists of a metal film containing one of the aforementioned metals, an alloy film containing one of the aforementioned alloys, or a nonmetallic conductive film containing one of the aforementioned nonmetallic conductors. The main electrode 52 is made of a different conductor than the first electrode 51a and the second electrode 51b.

[0268] In this embodiment, the main electrode 52 is made of an aluminum alloy. The aluminum alloy may include at least one of AlSi alloy, AlCu alloy, and AlSiCu alloy. The main electrode 52 is made of a different conductor than the main electrode 34 of the outer embedded electrode 32. Of course, the main electrode 52 may be made of the same type of conductor as the main electrode 34.

[0269] The main electrode 52 covers the base electrode 51 in a film-like manner and penetrates the source opening 44 from above the interlayer film 40. The main electrode 52 has a portion that covers the interlayer film 40 in a film-like manner via the base electrode 51, a portion that covers the wall surface of the source opening 44 in a film-like manner via the base electrode 51, and a portion that covers the first main surface 3 in a film-like manner via the base electrode 51.

[0270] The main electrode 52 is electrically insulated from the multiple gate structures 15 within the source opening 44 and is electrically connected to the body region 10, the multiple source regions 20, and the multiple contact regions 21 via the base electrode 51.

[0271] In this configuration, the main electrode 52 enters the multiple trenches 16 from the first main surface 3 and covers the side walls and open ends of the multiple trenches 16 via the base electrode 51. The main electrode 52 has a portion that is electrically connected to the multiple source regions 20 and the multiple contact regions 21 via the base electrode 51 at the open ends of the multiple trenches 16.

[0272] The main electrode 52 has a peripheral portion that faces the ends of the multiple gate structures 15 via the interlayer film 40 and the base electrode 51. The peripheral portion of the main electrode 52 is drawn out from the active region 8 to the outer region 9 and faces the first main surface 3 via the first interlayer film 41, gate wiring 43, interlayer film 40 and the base electrode 51.

[0273] The peripheral edge of the main electrode 52 faces the outer well region 25 in the stacking direction. The peripheral edge of the main electrode 52 is formed with a gap between it and the active region 8 from the multiple field regions 27. The peripheral edge of the main electrode 52 is formed with a gap between it and the active region 8 from the outer edge of the outer well region 25. The peripheral edge of the main electrode 52 is formed with a gap between it and the active region 8 from the outer edge of the outer contact region 26.

[0274] The peripheral edge of the main electrode 52 is formed with a gap between it and the rectifier structure 30 towards the active region 8. The peripheral edge of the main electrode 52 is formed with a gap between it and the inner edge of the outer contact region 26 towards the active region 8. The peripheral edge of the main electrode 52 is formed with a gap between it and the outer edge of the gate wiring 43 towards the active region 8. The peripheral edge of the main electrode 52 may be located on top of the outer contact region 26.

[0275] The main electrode 52 has a thickness greater than the thickness of the base electrode 51 (the total thickness of the first electrode 51a and the second electrode 51b). In this embodiment, the thickness of the main electrode 52 is greater than the thickness of the interlayer film 40. The thickness of the main electrode 52 may be less than the thickness of the interlayer film 40.

[0276] The thickness of the main electrode 52 may be 0.1 μm or more and 5 μm or less. The thickness of the main electrode 52 may have a value that falls within at least one of the following ranges: 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or more and 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0277] The semiconductor device 1A includes a source finger electrode 53 drawn out from the source electrode 50 onto the first main surface 3. The source finger electrode 53 may also be called a "source wire," "source finger," etc. The source finger electrode 53 transmits the source potential applied to the source electrode 50 to other regions.

[0278] The source finger electrode 53 is drawn out from the first pad portion 50a of the source electrode 50 onto the interlayer film 40. The source finger electrode 53 is routed around the periphery of the first main surface 3 and the region between the source electrode 50, extending in a band shape along the active region 8. In this configuration, the source finger electrode 53 is drawn out from the side of the first pad portion 50a on the second side surface 5B side onto the outer opening 46.

[0279] The source finger electrode 53 has a portion that extends in a strip shape in a first direction X and a portion that extends in a strip shape in a second direction Y when viewed from above. In this embodiment, the source finger electrode 53 is formed in a polygonal ring shape (a quadrangular ring shape in this embodiment) having four sides parallel to the periphery of the first main surface 3, and surrounds the source electrode 50. The source finger electrode 53 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter-circular arc shape).

[0280] The source finger electrode 53 enters the outer opening 46 from above the interlayer film 40 and is mechanically and electrically connected to the rectifier structure 30 within the outer opening 46. As a result, the source potential applied to the source electrode 50 is applied to the outer contact region 26, the outer well region 25, and the trench well region 35 via the rectifier structure 30.

[0281] The source finger electrode 53 has an inner edge portion on the inner side of the first main surface 3 and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion of the source finger electrode 53 is spaced apart from the plurality of gate structures 15 on the peripheral side of the first main surface 3 and faces the outer well region 25 in the stacking direction. The inner edge portion of the source finger electrode 53 is spaced apart from the gate wiring 43 on the peripheral side of the first main surface 3.

[0282] The inner edge of the source finger electrode 53 may be formed with a gap between the middle portion of the outer well region 25 and the peripheral edge of the first main surface 3. The inner edge of the source finger electrode 53 may face the outer contact region 26 in the stacking direction.

[0283] The outer edge of the source finger electrode 53 is formed with a gap between it and the multiple field regions 27 on the inward side of the first main surface 3. This prevents the dispersion path of the electric field from being shielded by the source finger electrode 53, and the electric field (electric field lines) is appropriately dispersed by the multiple field regions 27.

[0284] In this embodiment, the outer edge of the source finger electrode 53 is formed at a distance from the outer edge of the outer well region 25 toward the inward side of the first main surface 3, and is located on the outer well region 25. The outer edge of the source finger electrode 53 may also be located on the outer contact region 26. The outer edge of the source finger electrode 53 may also be located on the second semiconductor layer 7.

[0285] The source finger electrode 53, like the source electrode 50, has a laminated structure including a base electrode 51 and a main electrode 52 stacked in this order from the first main surface 3 side. The base electrode 51 has a laminated structure including a first electrode 51a and a second electrode 51b.

[0286] The first electrode 51a comprehensively covers the region of the interlayer film 40 where the outer opening 46 is formed, and extends from above the interlayer film 40 into the outer opening 46. The first electrode 51a has a portion that covers the insulating surface of the interlayer film 40 in a film-like manner, a portion that covers the wall surface of the outer opening 46 in a film-like manner, and a portion that covers the rectifier structure 30 in a film-like manner.

[0287] In this configuration, the first electrode 51a has a portion that covers the first interlayer film 41 and the second interlayer film 42 on the wall surface of the outer opening 46. The first electrode 51a has a portion that covers the first main surface 3 within the outer opening 46. The first electrode 51a is mechanically and electrically connected to the outer contact region 26 on both sides of the rectifier structure 30. In this configuration, the first electrode 51a enters the outer trench 31 from above the first main surface 3.

[0288] The first electrode 51a has a portion that is mechanically and electrically connected to the outer contact region 26 via the side wall and open end of the outer trench 31. The first electrode 51a has a portion that covers the outer embedded electrode 32 in a film-like manner and is mechanically and electrically connected to the outer embedded electrode 32. In this embodiment, the first electrode 51a is mechanically and electrically connected to the base electrode 33 and the main electrode 34 of the outer embedded electrode 32.

[0289] The second electrode 51b, via the first electrode 51a, comprehensively covers the region of the interlayer film 40 where the outer opening 46 is formed, and extends from above the interlayer film 40 into the outer opening 46. The second electrode 51b has a portion that covers the insulating surface of the interlayer film 40 via the first electrode 51a, a portion that covers the wall surface of the outer opening 46 via the first electrode 51a, and a portion that covers the rectifier structure 30 via the first electrode 51a.

[0290] The second electrode 51b has a portion that covers the first main surface 3 via the first electrode 51a within the outer opening 46. The second electrode 51b is electrically connected to the outer contact region 26 via the first electrode 51a on both sides of the rectifier structure 30. In this configuration, the second electrode 51b enters the outer trench 31 from above the first main surface 3.

[0291] The second electrode 51b has a portion that is electrically connected to the outer contact region 26 via the first electrode 51a at the side wall and opening end of the outer trench 31. The second electrode 51b has a portion that covers the outer embedded electrode 32 in a film-like manner via the first electrode 51a and is electrically connected to the outer embedded electrode 32. In this embodiment, the second electrode 51b is electrically connected to the base electrode 33 and the main electrode 34 of the outer embedded electrode 32 via the first electrode 51a.

[0292] The main electrode 52, via the base electrode 51, comprehensively covers the region of the interlayer film 40 where the outer opening 46 is formed, and penetrates the outer opening 46 from above the interlayer film 40. The main electrode 52 has a portion that covers the insulating surface of the interlayer film 40 via the base electrode 51, a portion that covers the wall surface of the outer opening 46 via the base electrode 51, and a portion that covers the rectifier structure 30 via the base electrode 51.

[0293] In this configuration, the main electrode 52 has a portion that covers the first main surface 3 via the base electrode 51 within the outer opening 46. In this configuration, the main electrode 52 is electrically connected to the outer contact region 26 via the base electrode 51 on both sides of the rectifier structure 30. In this configuration, the main electrode 52 enters the outer trench 31 from above the first main surface 3.

[0294] The main electrode 52 has portions that are electrically connected to the outer contact region 26 via the base electrode 51 at the side walls and opening ends of the outer trench 31. The main electrode 52 has portions that cover the outer embedded electrode 32 in a film-like manner via the base electrode 51 and is electrically connected to the outer embedded electrode 32. In this embodiment, the main electrode 52 is electrically connected to the base electrode 33 and the main electrode 34 of the outer embedded electrode 32 via the base electrode 51.

[0295] The semiconductor device 1A includes a gate electrode 54 disposed on the first main surface 3. The gate electrode 54 may also be referred to as the "second main electrode," "second terminal (electrode)," "second pad (electrode)," "gate pad electrode," etc. The gate electrode 54 is disposed on the interlayer film 40 at a distance from the source electrode 50 and the source finger electrode 53.

[0296] The gate electrode 54 is positioned in the region on the fourth side surface 5D side relative to the first pad portion 50a, and faces the central portion of the fourth side surface 5D and the first pad portion 50a in the first direction X. The gate electrode 54 is interposed in the region between the second pad portion 50b and the third pad portion 50c, and faces both the second pad portion 50b and the third pad portion 50c in the second direction Y.

[0297] The gate electrode 54 is formed in a polygonal shape (a quadrilateral in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view. The gate electrode 54 has a planar area less than the planar area of ​​the source electrode 50. The planar area of ​​the gate electrode 54 is less than the planar area of ​​the first pad portion 50a. The planar area of ​​the gate electrode 54 may be larger or smaller than the planar area of ​​the second pad portion 50b (third pad portion 50c).

[0298] In this embodiment, the gate electrode 54 does not have a direct electrical connection to the gate wiring 43. Of course, the gate electrode 54 may be mechanically and electrically connected to the gate wiring 43 via one or more gate openings 45.

[0299] The gate electrode 54 has a portion that faces the outer well region 25 via the interlayer film 40. In this embodiment, the gate electrode 54 has a portion that faces the multiple gate structures 15 via the interlayer film 40. Of course, the gate electrode 54 may be formed at a distance from the multiple gate structures 15 and may not face the multiple gate structures 15 in the stacking direction.

[0300] Although not shown in the illustration, the gate electrode 54, like the source electrode 50, includes a base electrode 51 and a main electrode 52 stacked in this order from the interlayer film 40 side. The base electrode 51 has a stacked structure including the base electrode 51 and the second electrode 51b.

[0301] The semiconductor device 1A includes a gate finger electrode 55 drawn out from the gate electrode 54 onto the first main surface 3. The gate finger electrode 55 may also be called a "gate wiring," "gate finger," etc. The gate finger electrode 55 transmits the gate potential applied to the gate electrode 54 to other regions.

[0302] The gate finger electrode 55 is drawn out from the gate electrode 54 onto the interlayer film 40. The gate finger electrode 55 is routed in a strip-like manner in the region between the source electrode 50 and the source finger electrode 53. In a plan view, the gate finger electrode 55 has a portion that extends in a strip-like manner in a first direction X and a portion that extends in a strip-like manner in a second direction Y.

[0303] In this embodiment, the gate finger electrode 55 is formed in the shape of an ended band having four sides parallel to the periphery of the first main surface 3, and surrounds the source electrode 50. The gate finger electrode 55 is positioned closer to the periphery of the first main surface 3 than the ends of the plurality of gate structures 15. The gate finger electrode 55 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter-circular arc shape).

[0304] The gate finger electrode 55 enters the multiple gate openings 45 from above the interlayer film 40 and is mechanically and electrically connected to the gate wiring 43 within the multiple gate openings 45. As a result, the gate potential applied to the gate electrode 54 is applied to the multiple gate structures 15 via the gate wiring 43 and the gate finger electrode 55.

[0305] The gate finger electrode 55 has an inner edge portion on the inner side of the first main surface 3 and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion of the gate finger electrode 55 is formed at a distance from the plurality of gate structures 15 on the peripheral side of the first main surface 3. In other words, the gate finger electrode 55 does not face the plurality of gate structures 15 in the stacking direction.

[0306] The inner edge of the gate finger electrode 55 is positioned on the gate wiring 43. The inner edge of the gate finger electrode 55 is horizontally opposed to the peripheral edge of the source electrode 50 on the gate wiring 43. The inner edge of the gate finger electrode 55 is formed with a gap from the middle of the gate wiring 43 toward the peripheral edge of the first main surface 3.

[0307] The outer edge of the gate finger electrode 55 is drawn out from above the gate wiring 43 towards the periphery of the first main surface 3 and does not face the gate wiring 43 in the stacking direction. The outer edge of the gate finger electrode 55 is formed with a gap between it and the multiple field regions 27 on the inward side of the first main surface 3. The outer edge of the gate finger electrode 55 is formed with a gap between it and the outer edge of the outer well region 25 on the inward side of the first main surface 3.

[0308] The outer edge of the gate finger electrode 55 is formed with a gap between it and the rectifying structure 30, on the inward side of the first main surface 3. In this configuration, the outer edge of the gate finger electrode 55 is formed with a gap between it and the inner edge of the outer contact region 26, on the inward side of the first main surface 3, and faces the outer well region 25.

[0309] The outer edge of the gate finger electrode 55 is horizontally opposed to the inner edge of the source finger electrode 53. The outer edge of the gate finger electrode 55 may be located on the outer contact region 26. The outer edge of the gate finger electrode 55 may be located on the second semiconductor layer 7.

[0310] The gate finger electrode 55, like the gate electrode 54, has a laminated structure including a base electrode 51 and a main electrode 52 stacked in this order from the first main surface 3 side. The base electrode 51 has a laminated structure including a first electrode 51a and a second electrode 51b.

[0311] The first electrode 51a comprehensively covers the region of the interlayer film 40 where multiple gate openings 45 are formed, and extends from above the interlayer film 40 into the multiple gate openings 45. The first electrode 51a has a portion that covers the insulating surface of the interlayer film 40 in a film-like manner, a portion that covers the wall surfaces of the multiple gate openings 45 in a film-like manner, and a portion that covers the gate wiring 43 within the multiple gate openings 45 in a film-like manner. The first electrode 51a is mechanically and electrically connected to the gate wiring 43 within the multiple gate openings 45.

[0312] The second electrode 51b, via the first electrode 51a, collectively covers the region of the interlayer film 40 where multiple gate openings 45 are formed, and penetrates the multiple gate openings 45 from above the interlayer film 40.

[0313] The second electrode 51b has a portion that covers the interlayer film 40 in a film-like manner via the first electrode 51a, a portion that covers the walls of the multiple gate openings 45 in a film-like manner via the first electrode 51a, and a portion that covers the gate wiring 43 in a film-like manner within the multiple gate openings 45 via the first electrode 51a. The second electrode 51b is electrically connected to the gate wiring 43 within the multiple gate openings 45 via the first electrode 51a.

[0314] The main electrode 52, via the base electrode 51, collectively covers the region of the interlayer film 40 where multiple gate openings 45 are formed, and penetrates the multiple gate openings 45 from above the interlayer film 40.

[0315] The main electrode 52 has a portion that covers the interlayer film 40 in a film-like manner via the base electrode 51, a portion that covers the wall surfaces of the multiple gate openings 45 in a film-like manner via the base electrode 51, and a portion that covers the gate wiring 43 in a film-like manner within the multiple gate openings 45 via the base electrode 51. The main electrode 52 is electrically connected to the gate wiring 43 within the multiple gate openings 45 via the base electrode 51.

[0316] The semiconductor device 1A includes a drain electrode 56 that covers the second main surface 4. The drain electrode 56 may also be referred to as the "third main electrode," "third terminal (electrode)," "third pad (electrode)," "drain pad electrode," etc. The drain electrode 56 is mechanically and electrically connected to the first semiconductor layer 6. The drain electrode 56 forms ohmic contact with the first semiconductor layer 6.

[0317] The drain electrode 56 may cover the entire area of ​​the second main surface 4 and may be connected to the periphery (first to fourth side surfaces 5A to 5D) of the second main surface 4. The drain electrode 56 may partially cover the second main surface 4 so that the periphery of the second main surface 4 is exposed.

[0318] The breakdown voltage that can be applied between the source electrode 50 and the drain electrode 56 (between the first main surface 3 and the second main surface 4) may be 500V or more and 3000V or less. The breakdown voltage may have a value that falls within at least one of the following ranges: 500V or more and 750V or less, 750V or more and 1000V or less, 1000V or more and 1250V or less, 1250V or more and 1500V or less, 1500V or more and 1750V or less, 1750V or more and 2000V or less, 2000V or more and 2250V or more and 2250V or more and 2500V or more and 3000V or less.

[0319] The aforementioned outer region 9 may have the configuration shown in Figures 11B to 11F. Figures 11B to 11F are enlarged cross-sectional views showing the second to sixth examples of the outer region 9 shown in Figure 10. Although the configurations of the second to sixth examples are shown individually in Figures 11B to 11F, the outer region 9 may simultaneously include at least two of the configurations of the first to sixth examples. Furthermore, the configurations of the first to sixth examples can be combined as appropriate.

[0320] Referring to Figure 11B (second example), the aforementioned outer opening 46 includes a first opening 46a on the first interlayer membrane 41 side and a second opening 46b on the second interlayer membrane 42 side. In this embodiment, the first opening 46a has a width greater than the width of the rectifying structure 30, and the second opening 46b has a width smaller than the width of the rectifying structure 30. In other words, the second interlayer membrane 42 covers the first and second walls of the first opening 46a on the first main surface 3.

[0321] In this configuration, the second opening 46b is formed only directly above the rectifier structure 30, exposing the electrode surface of the outer embedded electrode 32 (main electrode 34). In other words, the second interlayer membrane 42 has portions that cover both ends (underlayment electrodes 33) of the rectifier structure 30.

[0322] In this configuration, the aforementioned source finger electrode 53 enters the outer opening 46 from above the interlayer film 40 (second interlayer film 42) and is mechanically and electrically connected to the rectifier structure 30 within the outer opening 46. In other words, in this configuration, the source finger electrode 53 does not have a mechanical connection to the first main surface 3.

[0323] The source finger electrode 53 includes a base electrode 51 and a main electrode 52. The base electrode 51 has a laminated structure including a first electrode 51a and a second electrode 51b. The first electrode 51a enters the outer opening 46 from above the interlayer membrane 40 (second interlayer membrane 42) and is mechanically and electrically connected to the rectifying structure 30 (outer embedded electrode 32) within the outer opening 46. In other words, in this embodiment, the source finger electrode 53 does not have a mechanical connection to the first main surface 3.

[0324] The second electrode 51b enters the outer opening 46 from above the interlayer membrane 40 (second interlayer membrane 42) and is electrically connected to the rectifier structure 30 (outer embedded electrode 32) via the second electrode 51b within the outer opening 46. The main electrode 52 enters the outer opening 46 from above the interlayer membrane 40 (second interlayer membrane 42) and is electrically connected to the rectifier structure 30 (outer embedded electrode 32) via the base electrode 51 within the outer opening 46.

[0325] Referring to Figure 11C (third example), the outer opening 46 described above is integrally formed with the outer trench 31 in this embodiment. The outer opening 46 includes a first opening 46a on the first interlayer membrane 41 side and a second opening 46b on the second interlayer membrane 42 side. The first and second walls of the first opening 46a are connected to the first and second side walls of the outer trench 31, respectively.

[0326] The first and second walls of the second opening 46b are connected to the first and second side walls of the outer trench 31, respectively. In this configuration, the second opening 46b extends substantially perpendicular to the first main surface 3. The second opening 46b may be formed in a tapered shape, with the opening width gradually narrowing toward the outer trench 31.

[0327] In this configuration, the aforementioned outer embedded electrode 32 has a first portion embedded in the outer trench 31 and a second portion embedded in the outer opening 46. The first portion is mechanically and electrically connected to the walls of the outer trench 31 (first side wall, second side wall, and bottom wall). The second portion is in contact with the interlayer membrane 40 within the outer opening 46. Specifically, the second portion is in contact with the first interlayer membrane 41.

[0328] The outer embedded electrode 32 includes a base electrode 33 and a main electrode 34. In this embodiment, the base electrode 33 includes a first electrode 33a and a second electrode 33b. The first electrode 33a covers the wall surface of the outer trench 31 and the wall surface of the outer opening 46 in a film-like manner. The first electrode 33a forms a heterojunction (Schottky junction) with the second semiconductor layer 7 and is electrically connected to the outer well region 25 and the outer contact region 26.

[0329] The second electrode 33b coats the wall surface of the outer trench 31 and the wall surface of the outer opening 46 in a film-like manner via the first electrode 33a. The second electrode 33b is electrically connected to the second semiconductor layer 7, the outer well region 25, and the outer contact region 26 via the first electrode 33a.

[0330] The main electrode 34 is embedded in the outer trench 31 and the outer opening 46 via the base electrode 33. In other words, the main electrode 34 has a portion embedded in the outer trench 31 via the base electrode 33, and a portion embedded in the outer opening 46 via the base electrode 33.

[0331] The main electrode 34 has a portion that faces the second semiconductor layer 7, the outer well region 25, and the outer contact region 26 via the base electrode 33, and is electrically connected to the second semiconductor layer 7, the outer well region 25, and the outer contact region 26 via the base electrode 33. The main electrode 34 also has a portion that faces the interlayer film 40 (first interlayer film 41 and second interlayer film 42) via the base electrode 33.

[0332] In this configuration, the aforementioned source finger electrode 53 enters the outer opening 46 from above the interlayer membrane 40 (second interlayer membrane 42) and is mechanically and electrically connected to the rectifier structure 30 within the outer opening 46.

[0333] Specifically, in this configuration, the source finger electrode 53 is mechanically and electrically connected to the rectifier structure 30 at a height relative to the first main surface 3, on the insulating surface side of the interlayer film 40. More specifically, in this configuration, the source finger electrode 53 is mechanically and electrically connected to the outer embedded electrode 32 within the second opening 46b.

[0334] The source finger electrode 53 includes a base electrode 51 and a main electrode 52. The base electrode 51 has a laminated structure including a first electrode 51a and a second electrode 51b. The first electrode 51a enters the outer opening 46 (second opening 46b) from above the interlayer membrane 40 (second interlayer membrane 42) and is mechanically and electrically connected to the outer embedded electrode 32 within the outer opening 46.

[0335] The second electrode 51b enters the outer opening 46 (second opening 46b) from above the interlayer membrane 40 (second interlayer membrane 42) and is electrically connected to the outer embedded electrode 32 via the first electrode 51a within the outer opening 46. The main electrode 52 enters the outer opening 46 (second opening 46b) from above the interlayer membrane 40 (second interlayer membrane 42) and is electrically connected to the outer embedded electrode 32 via the base electrode 51 within the outer opening 46.

[0336] Referring to Figure 11D (Fourth Example), in this embodiment, the outer embedded electrode 32 of the rectifier structure 30 does not have a base electrode 33 and includes a main electrode 34 embedded integrally in the outer trench 31. The main electrode 34 consists of a metal film containing one of the aforementioned metals, an alloy film containing one of the aforementioned alloys, or a nonmetallic conductive film containing one of the aforementioned nonmetallic conductors. The main electrode 34 may be made of tungsten or conductive polysilicon.

[0337] The main electrode 34 is directly embedded in the outer trench 31 and is mechanically and electrically connected to the wall surface (chip 2) of the outer trench 31. Specifically, the main electrode 34 forms a heterojunction (Schottky junction) with the second semiconductor layer 7 and is electrically connected to the outer well region 25 and the outer contact region 26.

[0338] The source finger electrode 53 includes a base electrode 51 and a main electrode 52. The base electrode 51 has a laminated structure including a first electrode 51a and a second electrode 51b. The first electrode 51a coats the main electrode 34 in a film-like manner within the outer trench 31 and is mechanically and electrically connected to the main electrode 34. The first electrode 51a may also be mechanically and electrically connected to the outer contact region 26 via the open end of the outer trench 31.

[0339] The second electrode 51b covers the main electrode 34 in a film-like manner within the outer trench 31 via the first electrode 51a. The second electrode 51b may have a portion that covers the side wall and open end of the outer trench 31 via the first electrode 51a. The main electrode 52 covers the main electrode 34 within the outer trench 31 via the base electrode 51. The main electrode 52 may have a portion that covers the side wall and open end of the outer trench 31 via the base electrode 51.

[0340] Referring to Figure 11E (Fifth Example), the aforementioned source finger electrode 53 includes a base electrode 51 and a main electrode 52. In this embodiment, the base electrode 51 is integrally formed with the base electrode 33 of the outer embedded electrode 32, and the main electrode 52 is formed separately from the main electrode 34 of the outer embedded electrode 32. The configuration in which the base electrode 51 is integrally formed with the base electrode 33 and the main electrode 52 is formed separately from the main electrode 34 is also applicable to the first to fourth examples described above.

[0341] The base electrode 51 has a laminated structure including a first electrode 51a and a second electrode 51b. The first electrode 51a extends from above the interlayer film 40 (second interlayer film 42) into the outer opening 46. The first electrode 51a has a portion that covers the insulating surface of the interlayer film 40 in a film-like manner, a portion that covers the wall surface of the outer opening 46 in a film-like manner, and a portion that covers the first main surface 3 (outer contact region 26) within the outer opening 46 in a film-like manner.

[0342] The first electrode 51a enters the outer trench 31 from above the first main surface 3 and is connected to the first electrode 33a of the outer embedded electrode 32 within the outer trench 31. In other words, the first electrode 51a is formed as a single electrode film with the first electrode 33a. At the open end of the outer trench 31, the connection portion between the first electrode 33a and the first electrode 51a may be considered as part of the first electrode 33a or as part of the first electrode 51a.

[0343] The second electrode 51b enters the outer opening 46 from above the interlayer film 40 (second interlayer film 42). The second electrode 51b has a portion that covers the insulating surface of the interlayer film 40 in a film-like manner via the first electrode 51a, a portion that covers the wall surface of the outer opening 46 in a film-like manner via the first electrode 51a, and a portion that covers the first main surface 3 (outer contact region 26) in a film-like manner within the outer opening 46 via the first electrode 51a.

[0344] The second electrode 51b enters the outer trench 31 from above the first main surface 3 and is connected to the second electrode 33b of the outer embedded electrode 32 within the outer trench 31. In other words, the second electrode 51b is formed as a single electrode film with the second electrode 33b. At the open end of the outer trench 31, the connection portion between the second electrode 33b and the second electrode 51b may be considered as part of the second electrode 33b or as part of the second electrode 51b.

[0345] The main electrode 52 enters the outer opening 46 from above the interlayer film 40 (second interlayer film 42). The main electrode 52 has a portion that covers the insulating surface of the interlayer film 40 in a film-like manner via the base electrode 51, a portion that covers the wall surface of the outer opening 46 in a film-like manner via the base electrode 51, and a portion that covers the first main surface 3 (outer contact region 26) in a film-like manner within the outer opening 46 via the base electrode 51.

[0346] The main electrode 52 has a portion that directly covers the outer embedded electrode 32 in a film-like manner within the outer trench 31. Specifically, the main electrode 52 is mechanically and electrically connected to the main electrode 34 of the outer embedded electrode 32.

[0347] Referring to Figure 11F (Sixth Example), the aforementioned source finger electrode 53 includes a base electrode 51 and a main electrode 52. In this embodiment, the base electrode 51 is integrally formed with the base electrode 33 of the outer embedded electrode 32, and the main electrode 52 is integrally formed with the main electrode 34 of the outer embedded electrode 32. The configuration in which the base electrode 51 is integrally formed with the base electrode 33 and the main electrode 52 is integrally formed with the main electrode 34 is also applicable to the first to fourth examples described above.

[0348] The base electrode 51 has a laminated structure including a first electrode 51a and a second electrode 51b. The first electrode 51a extends from above the interlayer film 40 (second interlayer film 42) into the outer opening 46. The first electrode 51a has a portion that covers the insulating surface of the interlayer film 40 in a film-like manner, a portion that covers the wall surface of the outer opening 46 in a film-like manner, and a portion that covers the first main surface 3 (outer contact region 26) within the outer opening 46 in a film-like manner.

[0349] The first electrode 51a enters the outer trench 31 from above the first main surface 3 and is integrally formed with the first electrode 33a of the outer embedded electrode 32 within the outer trench 31. In other words, the first electrode 51a is formed as a single electrode film with the first electrode 33a. At the open end of the outer trench 31, the connection portion between the first electrode 33a and the first electrode 51a may be considered as a part of the first electrode 33a or as a part of the first electrode 51a.

[0350] The second electrode 51b extends from above the interlayer film 40 (second interlayer film 42) into the outer opening 46 (second opening 46b). The second electrode 51b has a portion that covers the insulating surface of the interlayer film 40 in a film-like manner via the first electrode 51a, a portion that covers the wall surface of the outer opening 46 in a film-like manner via the first electrode 51a, and a portion that covers the first main surface 3 (outer contact region 26) in a film-like manner within the outer opening 46 via the first electrode 51a.

[0351] The second electrode 51b enters the outer trench 31 from above the first main surface 3 and is integrally formed with the second electrode 33b of the outer embedded electrode 32 within the outer trench 31. In other words, the second electrode 51b is formed as a single electrode film with the second electrode 33b. At the open end of the outer trench 31, the connection portion between the second electrode 33b and the second electrode 51b may be considered as part of the second electrode 33b or as part of the second electrode 51b.

[0352] The main electrode 52 enters the outer opening 46 from above the interlayer film 40 (second interlayer film 42). The main electrode 52 has a portion that covers the insulating surface of the interlayer film 40 in a film-like manner via the base electrode 51, a portion that covers the wall surface of the outer opening 46 in a film-like manner via the base electrode 51, and a portion that covers the first main surface 3 (outer contact region 26) in a film-like manner within the outer opening 46 via the base electrode 51.

[0353] The main electrode 52 enters the outer trench 31 from above the first main surface 3 and is integrally formed with the main electrode 34 of the outer embedded electrode 32 within the outer trench 31. In other words, the main electrode 52 is formed as a single electrode film with the main electrode 34. At the opening of the outer trench 31, the connection portion between the main electrode 34 and the main electrode 52 may be considered as part of the main electrode 34 or as part of the main electrode 52.

[0354] Figure 12 is a circuit diagram showing the electrical configuration of the semiconductor device 1A shown in Figure 1. The semiconductor device 1A includes a transistor structure Tr, a bipolar type bipolar diode DB, a unipolar type monopolar diode DU, a source electrode 50, a gate electrode 54, and a drain electrode 56.

[0355] The transistor structure Tr is formed in the active region 8 and includes a drain, gate, and source. The drain of the transistor structure Tr includes a first semiconductor layer 6 and a second semiconductor layer 7. The gate of the transistor structure Tr includes a plurality of gate structures 15. The source of the transistor structure Tr includes a plurality of source regions 20.

[0356] The bipolar diode DB consists of a pn junction diode. The bipolar diode DB includes an anode and a cathode. The anode of the bipolar diode DB includes a body region 10, a plurality of contact regions 21, a well region 22, an outer well region 25, an outer contact region 26, and a trench well region 35. The cathode of the bipolar diode DB includes a first semiconductor layer 6 and a second semiconductor layer 7.

[0357] The anode of the bipolar diode DB is connected to the source of the transistor structure Tr, and the cathode of the bipolar diode DB is connected to the drain of the transistor structure Tr. The bipolar diode DB has a first threshold voltage Vth1. The bipolar diode DB has a first area. The first area is the total connection area of ​​the body region 10, well region 22, outer well region 25 and trench well region 35 with respect to the second semiconductor layer 7.

[0358] The unipolar diode DU consists of a heterojunction diode (Schottky junction diode). The unipolar diode DU includes an anode and a cathode. The anode of the unipolar diode DU includes a rectifier structure 30 (outer embedded electrode 32). The cathode of the unipolar diode DU includes a first semiconductor layer 6 and a second semiconductor layer 7.

[0359] The anode of the unipolar diode DU is connected to the source of the transistor structure Tr, and the cathode of the unipolar diode DU is connected to the drain of the transistor structure Tr. In other words, the unipolar diode DU is connected in parallel with the bipolar diode DB, and together with the bipolar diode DB, it forms a freewheeling diode for the transistor structure Tr.

[0360] The unipolar diode DU has a second threshold voltage Vth2 which is less than the first threshold voltage Vth1. The unipolar diode DU has a second area which is less than the first area. The second area of ​​the unipolar diode DU is the connection area of ​​the rectifier structure 30 (outer embedded electrode 32) to the second semiconductor layer 7.

[0361] The second area of ​​the unipolar diode DU is less than the connection area of ​​the body region 10 to the second semiconductor layer 7. The second area of ​​the unipolar diode DU is less than the connection area of ​​the well region 22 to the second semiconductor layer 7. The second area of ​​the unipolar diode DU is less than the connection area of ​​the outer contact region 26 to the second semiconductor layer 7.

[0362] The second area of ​​the unipolar diode DU may be larger than the connection area of ​​the trench well region 35 to the second semiconductor layer 7. The second area of ​​the unipolar diode DU may be less than the connection area of ​​the trench well region 35 to the second semiconductor layer 7.

[0363] The source electrode 50 is electrically connected to the source of the transistor structure Tr, the anode of the bipolar diode DB, and the anode of the unipolar diode DU. The gate electrode 54 is electrically connected to the gate of the transistor structure Tr. The drain electrode 56 is electrically connected to the drain of the transistor structure Tr, the cathode of the bipolar diode DB, and the cathode of the unipolar diode DU.

[0364] Figure 13 is a graph (simulation) showing the electrical behavior of the semiconductor device 1A shown in Figure 1. The graph in Figure 13 shows the characteristics of the forward current IF when a forward voltage VF is applied to the bipolar diode DB and the unipolar diode DU. In Figure 13, the vertical axis represents the forward current IF [A] and the horizontal axis represents the forward voltage VF [V].

[0365] The forward voltage VF is the voltage that brings the source electrode 50 to a positive potential and the drain electrode 56 to a negative potential. In other words, the forward voltage VF is the reverse bias voltage VDS related to the transistor structure Tr, and the forward current IF is the drain current IDS related to the transistor structure Tr.

[0366] Referring to Figure 13, when semiconductor device 1A switches from the ON state to the OFF state, a forward voltage VF as a back electromotive force is generated in the bipolar diode DB and the unipolar diode DU. As a result, the bipolar diode DB and the unipolar diode DU switch to freewheeling operation.

[0367] The unipolar diode DU has a second threshold voltage Vth2 which is less than the first threshold voltage Vth1 of the bipolar diode DB. Therefore, the unipolar diode DU turns on before the bipolar diode DB turns on, and carries a forward current IF as a freewheeling current. This reduces forward energy loss. In this configuration, the design ensures that only the unipolar diode DU is turned on during normal freewheeling operation. Therefore, the freewheeling current is handled only by the unipolar diode DU.

[0368] The first semiconductor layer 6 may have basal plane dislocation (BPD) defects. Basal plane dislocation defects are dislocations located on the c-plane, which is the basal plane of a SiC single crystal. If the first semiconductor layer 6 has an off-direction and an off-angle, the basal plane dislocation defects extend in the off-direction with an inclination equal to the off-angle. Basal plane dislocation defects are typically 1 cm long. －２ More than 10000cm －２ It has the following density:

[0369] When holes, acting as minority carriers, are supplied to the second semiconductor layer 7 during reflux operation, the holes recombine with electrons, acting as majority carriers, within the second semiconductor layer 7, releasing energy. While the majority of holes recombine with electrons in the second semiconductor layer 7, a small number of holes may reach the first semiconductor layer 6. If holes recombine with electrons at or near a basal plane dislocation defect, the atoms of the basal plane dislocation defect may migrate from the first semiconductor layer 6 to the second semiconductor layer 7 due to the energy generated by the recombination.

[0370] In this case, atom migration resulting from a basal plane dislocation defect may extend to the second semiconductor layer 7 as a single Shockley stacking fault (1SSF). A single Shockley stacking fault traps conduction carriers during freewheeling, causing an increase in on-voltage and on-resistance. This type of problem is known as bipolar degradation.

[0371] In semiconductor device 1A, the unipolar diode DU operates dominantly during freewheeling, thereby suppressing the supply of holes as minority carriers to the second semiconductor layer 7. As a result, the number of holes reaching the first semiconductor layer 6 is reduced, and bipolar degradation caused by basal plane dislocation defects is suppressed.

[0372] On the other hand, when a surge current Is occurs during freewheeling, the bipolar diode DB turns on in addition to the monopolar diode DU. The surge current Is, due to snapback, draws an inverted increase curve from the increase curve due to the monopolar diode DU, and then drops sharply (see dashed line).

[0373] As a result, the surge current Is is handled by both the bipolar diode DB and the unipolar diode DU, while simultaneously suppressing the increase in the forward voltage VF. Furthermore, the first area of ​​the bipolar diode DB is larger than the second area of ​​the unipolar diode DU. Therefore, when a surge current Is is applied, current concentration in the bipolar diode DB is suppressed, and the on-delay of the bipolar diode DB is also suppressed.

[0374] As described above, the semiconductor device 1A may include an n-type second semiconductor layer 7 (semiconductor layer), a p-type body region 10 (impurity region), and a rectifier structure 30. The second semiconductor layer 7 may have a first main surface 3. The body region 10 is formed in the inner part of the second semiconductor layer 7 and may form a bipolar diode DB with the second semiconductor layer 7. The rectifier structure 30 is formed on the peripheral edge of the second semiconductor layer 7 and may form a unipolar diode DU with the second semiconductor layer 7.

[0375] This configuration provides a novel semiconductor device 1A. For example, with this semiconductor device 1A, the freewheeling current during freewheeling operation is processed by a single-pole diode DU, while the surge current Is is processed by both a bipolar diode DB and a single-pole diode DU. Furthermore, with the trench-type rectifier structure 30, the formation area of ​​the single-pole diode DU in the outer region 9 is expanded in the thickness direction Z. Such a configuration is effective in achieving reduced energy loss and suppression of bipolar degradation.

[0376] The second semiconductor layer 7 may contain SiC. This configuration provides a semiconductor device 1A as a SiC semiconductor device with a novel layout. With semiconductor device 1A, the electrical characteristics are appropriately improved by the physical properties of SiC. In particular, since SiC semiconductor devices are used in relatively high voltage environments, the effect of reducing energy loss and the effect of suppressing bipolar degradation are effective in improving electrical characteristics.

[0377] The semiconductor device 1A may include a p-type trench well region 35 formed in the region below the rectifier structure 30 within the second semiconductor layer 7. In this case, the trench well region 35 may form a bipolar diode DB with the second semiconductor layer 7. With this configuration, the surge current Is can be handled by both the bipolar diode DB and the unipolar diode DU.

[0378] Furthermore, with this configuration, electric field concentration on the rectifier structure 30 is mitigated by a depletion layer extending from the trench well region 35. The trench well region 35 may be electrically connected to the rectifier structure 30. With this configuration, the electrical response characteristics of the trench well region 35 are improved by the rectifier structure 30.

[0379] The semiconductor device 1A may include a p-type outer well region 25 formed in the second semiconductor layer 7 in the outer region 9. In this case, the outer well region 25 may form a bipolar diode DB with the second semiconductor layer 7. With this configuration, the surge current Is can be handled by both the bipolar diode DB and the unipolar diode DU.

[0380] In this case, the rectifier structure 30 may penetrate the outer well region 25. With this configuration, the electric field strength (electric field concentration) in the outer region 9 is mitigated by the depletion layer that extends from the outer well region 25. Furthermore, with this configuration, the electric field concentration on the rectifier structure 30 is mitigated by the depletion layer that extends from the outer well region 25.

[0381] The rectifier structure 30 may have a portion electrically connected to the outer well region 25, and a portion that forms a unipolar diode DU with the second semiconductor layer 7 in a region closer to the bottom wall of the outer trench 31 than to the bottom of the outer well region 25. With this configuration, the rectifier structure 30 forms a unipolar diode DU while improving the electrical response characteristics of the outer well region 25.

[0382] The semiconductor device 1A may include a p-type outer contact region 26 formed on the surface of the outer well region 25. In this case, the rectifier structure 30 may penetrate both the outer well region 25 and the outer contact region 26. With this configuration, the electrical response characteristics of the outer well region 25 are improved by the outer contact region 26.

[0383] The rectifier structure 30 may have a portion electrically connected to the outer well region 25 and the outer contact region 26, and a portion that forms a unipolar diode DU with the second semiconductor layer 7 in a region closer to the bottom wall of the outer trench 31 than to the bottom of the outer well region 25. With this configuration, the rectifier structure 30 forms a unipolar diode DU, while the rectifier structure 30 and the outer contact region 26 improve the electrical response characteristics of the outer well region 25.

[0384] The semiconductor device 1A may include at least one p-type field region 27 formed in the second semiconductor layer 7 in the outer region 9. With this configuration, the electric field strength (electric field concentration) in the outer region 9 is mitigated by the depletion layer extending from the field region 27. In this case, the rectifier structure 30 may be formed with a gap between the field region 27 and the active region 8.

[0385] The semiconductor device 1A may include an interlayer film 40 and a source finger electrode 53 (electrode). The interlayer film 40 may cover the second semiconductor layer 7. The source finger electrode 53 may penetrate the interlayer film 40 on the peripheral edge side of the second semiconductor layer 7 and be electrically connected to the rectifier structure 30.

[0386] The semiconductor device 1A may include a source electrode 50 (main electrode). The source electrode 50 may penetrate the interlayer film 40 on the inner side of the second semiconductor layer 7 and be electrically connected to the body region 10. In this case, the source finger electrode 53 may be led out from the source electrode 50. With this configuration, the body region 10 and the rectifier structure 30 are fixed at the same potential, and the bipolar diode DB and the unipolar diode DU are appropriately connected in parallel.

[0387] The semiconductor device 1A may include a trench electrode type gate structure 15. The gate structure 15 may penetrate the body region 10 in the inner part of the second semiconductor layer 7. The rectifier structure 30 may have a width greater than or equal to the width of the gate structure 15. The rectifier structure 30 may have a depth greater than or equal to the depth of the gate structure 15.

[0388] The semiconductor device 1A may include a p-type well region 22 formed in the region below the gate structure 15 within the second semiconductor layer 7. With this configuration, the breakdown voltage is improved by the depletion layer that extends from the well region 22.

[0389] Figure 14 is a plan view showing an example of the layout of the first main surface 3 of the semiconductor device 1B according to the second embodiment. Figure 15A is an enlarged cross-sectional view showing a first example of the rectifier structure 30 and source finger electrode 53 shown in Figure 14.

[0390] In this embodiment, the semiconductor device 1B includes a plurality of trench electrode type rectifier structures 30 that form a second semiconductor layer 7 and a unipolar diode DU at the periphery (outer region 9) of the second semiconductor layer 7. The number of the plurality of rectifier structures 30 is arbitrary and may be between two and twenty.

[0391] The number of rectifier structures 30 may be a value that falls within at least one of the following ranges: 2 to 4, 4 to 6, 6 to 8, 8 to 10, 10 to 12, 12 to 14, 14 to 16, 16 to 18, and 18 to 20.

[0392] The multiple rectifier structures 30 are formed on the peripheral edge of the first main surface 3, spaced apart from the periphery of the first main surface 3 and the multiple gate structures 15. The multiple rectifier structures 30 are formed spaced apart from each other in the horizontal direction.

[0393] The multiple rectifier structures 30 are formed with a gap between them and the active region 8, starting from the innermost field region 27. Specifically, the multiple rectifier structures 30 are formed with a gap between them and the active region 8, starting from the outer edge of the outer well region 25. More specifically, the multiple rectifier structures 30 are formed with a gap between them and the active region 8, starting from the outer edge of the outer contact region 26.

[0394] The multiple rectifier structures 30 each extend in a strip shape along the active region 8 in a plan view. In this embodiment, the multiple rectifier structures 30 are each formed in a polygonal ring shape (a quadrilateral ring shape in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view, and surround the active region 8 (multiple gate structures 15). The multiple rectifier structures 30 may each have edge portions that connect the portion extending in a strip shape in the first direction X and the portion extending in a strip shape in the second direction Y in an arc shape (preferably a quarter-circular arc shape).

[0395] Multiple rectifier structures 30 penetrate the outer well region 25 and the outer contact region 26 so as to reach the second semiconductor layer 7, and are electrically connected to the second semiconductor layer 7, the outer well region 25, and the outer contact region 26. Multiple rectifier structures 30 are located inward from the inner and outer edges of the outer contact region 26 and penetrate the inner portion of the outer contact region 26.

[0396] The multiple rectifier structures 30 each have, as in the first embodiment, a first side wall on the inner (active region 8) side of the first main surface 3, a second side wall on the peripheral side of the first main surface 3, and a bottom wall connecting the first and second side walls. The description of the width, depth, and aspect ratio of the multiple rectifier structures 30 is the same as in the first embodiment. Also, as in the first embodiment, the multiple rectifier structures 30 each include an outer trench 31 and an outer embedded electrode 32.

[0397] In this embodiment, the semiconductor device 1B includes a plurality of p-type trench well regions 35 formed in the peripheral region (outer region 9) of the second semiconductor layer 7, in the region below the plurality of rectifier structures 30. The plurality of trench well regions 35 are formed horizontally within the second semiconductor layer 7, spaced apart from each other. The plurality of trench well regions 35 are formed in the regions below (specifically directly below) the plurality of rectifier structures 30, and overlap with the plurality of rectifier structures 30 in a one-to-one correspondence in the thickness direction Z.

[0398] The multiple trench well regions 35 extend in a band-like shape in a plan view, following the direction of extension of the corresponding rectifying structure 30. In this configuration, the multiple trench well regions 35 are formed in a polygonal ring (a quadrilateral ring in this configuration) with four sides parallel to the periphery of the first main surface 3 in a plan view, and surround the active region 8 (multiple gate structures 15).

[0399] The multiple trench well regions 35 may have edge portions that connect the portions extending in a strip shape in a first direction X and the portions extending in a strip shape in a second direction Y in an arc shape (preferably in a quarter arc shape). The multiple trench well regions 35 may be formed in a one-to-many correspondence with the corresponding flow straightening structure 30 and may be formed at intervals following the extending direction of the corresponding flow straightening structure 30.

[0400] Multiple trench well regions 35 are formed in the thickness range between the bottom of the second semiconductor layer 7 and the bottom walls of the multiple rectifier structures 30. In this embodiment, the multiple trench well regions 35 extend horizontally. The multiple trench well regions 35 may also extend vertically in the thickness direction Z. The multiple trench well regions 35 are formed at intervals from the bottom of the second semiconductor layer 7 towards the bottom walls of the multiple rectifier structures 30 and face the first semiconductor layer 6 via a portion of the second semiconductor layer 7.

[0401] The multiple trench well regions 35, as in the first embodiment, each have an upper end located on the bottom wall side of the corresponding rectifier structure 30 and a bottom located on the bottom side of the second semiconductor layer 7. The upper end of the trench well region 35 is formed with a gap between the bottom of the outer well region 25 and the bottom wall side of the corresponding rectifier structure 30. The upper end of the trench well region 35 is connected to the bottom wall of the rectifier structure 30.

[0402] The multiple trench well regions 35 may form a superjunction structure with charge balance with the second semiconductor layer 7. In this case, the depletion layer extending from the multiple trench well regions 35 becomes integrated in the region between the multiple trench well regions 35.

[0403] The semiconductor device 1B includes one or more (one in this embodiment) outer openings 46 formed in the interlayer film 40, similar to the first embodiment. The outer openings 46 include a first opening 46a formed in the first interlayer film 41 and a second opening 46b formed in the second interlayer film 42.

[0404] The first opening 46a penetrates the first interlayer film 41 and selectively exposes the multiple flow straightening structures 30. The first opening 46a is formed with a gap between the gate wiring 43 and the multiple flow straightening structures 30, and with a gap between the periphery of the first main surface 3 and the multiple flow straightening structures 30. The first opening 46a is formed with a gap between the multiple field regions 27 (the innermost field region 27) and the multiple flow straightening structures 30.

[0405] The first opening 46a extends in a strip shape following the direction of extension of the plurality of rectifying structures 30. The first opening 46a has a portion that extends in a strip shape in a first direction X and a portion that extends in a strip shape in a second direction Y. In this embodiment, the first opening 46a is formed as an endless polygonal ring (for example, a quadrilateral ring) having four sides parallel to the periphery of the first main surface 3, and surrounds the active region 8 (the plurality of gate structures 15).

[0406] The first opening 46a may be formed in the shape of a strip with an end. The first opening 46a may have an edge portion that connects the portion extending in a strip shape in the first direction X and the portion extending in a strip shape in the second direction Y in an arc shape (preferably a quarter arc shape) when viewed from above.

[0407] In this configuration, the first opening 46a has a width greater than or equal to the width of the multiple rectifier structures 30 in cross-sectional view, and exposes the entire upper end of the multiple rectifier structures 30 (the electrode surface of the outer embedded electrode 32). In this configuration, the first opening 46a has a width greater than the width of the multiple rectifier structures 30, and exposes the portion of the first main surface 3 located around (both sides of) the multiple rectifier structures 30.

[0408] In this configuration, the first opening 46a has a width less than or equal to the width of the outer contact region 26 and is formed on the side of the multiple flow straightening structures 30 that is closer to the inner and outer edges of the outer contact region 26. Of course, the first opening 46a may have a width greater than the width of the outer contact region 26, exposing part or all of the outer contact region 26.

[0409] The first opening 46a has a first wall portion on the inner side of the first main surface 3 and a second wall portion on the peripheral side of the first main surface 3. The first wall portion is spaced apart from the first side wall of the innermost (innermost) flow straightening structure 30 on the inner side of the first main surface 3. In this configuration, the first wall portion is located on the inner edge side of the outer contact region 26, exposing the inner edge of the outer contact region 26 between itself and the first side wall. The first wall portion may be located further inward of the first main surface 3 than the inner edge of the outer contact region 26, and may be located above the outer well region 25.

[0410] The second wall portion is separated from the second side wall of the outermost (outermost) flow straightening structure 30 by a gap on the peripheral side of the first main surface 3. In this configuration, the second wall portion is located on the outer edge side of the outer contact region 26, exposing the outer edge of the outer contact region 26 between itself and the second side wall. The second wall portion may be located on the peripheral side of the first main surface 3, further than the outer edge of the outer contact region 26, and may be located above the outer well region 25.

[0411] The second opening 46b penetrates the second interlayer membrane 42 at a position overlapping part or all of the first opening 46a, selectively exposing multiple flow-rectifying structures 30. In other words, the second opening 46b together with the first opening 46a forms a single outer opening 46.

[0412] The second opening 46b is formed with a gap between the gate wiring 43 and the multiple rectifier structures 30, and is formed with a gap between the periphery of the first main surface 3 and the multiple rectifier structures 30. The second opening 46b is formed with a gap between the multiple field regions 27 (the innermost field region 27) and the multiple rectifier structures 30.

[0413] The second opening 46b extends in a strip shape following the direction of extension of the plurality of rectifying structures 30. The second opening 46b has a portion that extends in a strip shape in the first direction X and a portion that extends in a strip shape in the second direction Y. In this embodiment, the second opening 46b is formed as an endless polygonal ring (for example, a quadrilateral ring) having four sides parallel to the periphery of the first main surface 3, and surrounds the active region 8 (the plurality of gate structures 15).

[0414] The second opening 46b may be formed in the shape of an ended strip. The second opening 46b may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in the shape of an arc (preferably a quarter-circular arc) when viewed from above.

[0415] In this configuration, the second opening 46b is formed in a tapered shape, with the opening width gradually narrowing from the opening end toward the first main surface 3 in a cross-sectional view. The second opening 46b may also be formed substantially perpendicular to the first main surface 3 in a cross-sectional view.

[0416] In this configuration, the second opening 46b has a width greater than or equal to the width of the multiple rectifier structures 30, and exposes the entire upper end of the multiple rectifier structures 30 (the electrode surface of the outer embedded electrode 32). In this configuration, the second opening 46b has a width greater than the width of the multiple rectifier structures 30, and exposes the portion of the first main surface 3 located around (both sides of) the multiple rectifier structures 30.

[0417] In this configuration, the second opening 46b has a width less than or equal to the width of the outer contact region 26 and is formed on the side of the multiple flow straightening structures 30 that is closer to the inner and outer edges of the outer contact region 26. Of course, the second opening 46b may have a width greater than the width of the outer contact region 26, exposing part or all of the outer contact region 26.

[0418] In this embodiment, the second opening 46b has an opening end width greater than or equal to the width of the first opening 46a. Specifically, the opening end width of the second opening 46b is greater than the width of the first opening 46a. The opening end width of the second opening 46b may be approximately equal to the width of the first opening 46a. The opening end width of the second opening 46b may be less than the width of the first opening 46a. The opening end width of the second opening 46b may be greater than or less than the thickness of the interlayer film 40.

[0419] The second opening 46b has a first wall portion on the inner side of the first main surface 3 and a second wall portion on the peripheral side of the first main surface 3. The first wall portion is spaced apart from the first side wall of the innermost (innermost) flow straightening structure 30 on the inner side of the first main surface 3. The first wall portion is located on the inner edge side of the outer contact region 26, exposing the inner edge of the outer contact region 26 between itself and the first side wall. The first wall portion may be located further inward of the first main surface 3 than the inner edge of the outer contact region 26, and may be located above the outer well region 25.

[0420] The second wall portion is partitioned from the second side wall of the outermost (outermost) flow straightening structure 30, with a gap between it and the peripheral edge of the first main surface 3. The second wall portion is located on the outer edge side of the outer contact region 26, exposing the outer edge of the outer contact region 26 between it and the second side wall. The second wall portion may be located on the peripheral edge side of the first main surface 3, further than the outer edge of the outer contact region 26, and may be located above the outer well region 25.

[0421] In this configuration, the second opening 46b is connected to the first opening 46a. That is, the first wall of the second opening is connected to the first wall of the first opening 46a, and the second wall of the second opening is connected to the second wall of the first opening 46a.

[0422] The first wall of the second opening 46b may be located on the side of the multiple flow straightening structures 30 that is closer to the first wall of the first opening 46a. In other words, the second interlayer membrane 42 may cover the first wall of the first opening 46a. The second wall of the second opening 46b may be located on the side of the multiple flow straightening structures 30 that is closer to the second wall of the first opening 46a. In other words, the second interlayer membrane 42 may cover the second wall of the first opening 46a.

[0423] The semiconductor device 1B may include a plurality of outer openings 46. In this case, the plurality of outer openings 46 are formed at intervals in the extending direction of the plurality of rectifier structures 30 and each includes a first opening 46a and a second opening 46b. The plurality of outer openings 46 may extend in a strip shape following the extending direction of the plurality of rectifier structures 30. The plurality of outer openings 46 may be formed in a polygonal or circular shape in plan view. The plurality of outer openings 46 may be formed in a square or hexagonal shape in plan view.

[0424] The source finger electrode 53 has a laminated structure including a base electrode 51 and a main electrode 52, which are stacked in this order from the first main surface 3 side, as in the first embodiment. The base electrode 51 has a laminated structure including a first electrode 51a and a second electrode 51b.

[0425] The first electrode 51a comprehensively covers the region of the interlayer film 40 where the outer opening 46 is formed, and extends from above the interlayer film 40 into the outer opening 46. The first electrode 51a has a portion that covers the insulating surface of the interlayer film 40 in a film-like manner, a portion that covers the wall surface of the outer opening 46 in a film-like manner, and a portion that covers the multiple rectifier structures 30 in a film-like manner.

[0426] In this configuration, the first electrode 51a has a portion that covers the first main surface 3 within the outer opening 46. In this configuration, the first electrode 51a is mechanically and electrically connected to the outer contact region 26 on both sides of the plurality of rectifier structures 30. In this configuration, the first electrode 51a extends from above the first main surface 3 into the plurality of outer trenches 31.

[0427] The first electrode 51a has a portion that is mechanically and electrically connected to the outer contact region 26 via the side walls and open ends of the multiple outer trenches 31. The first electrode 51a has a portion that covers the multiple outer embedded electrodes 32 in a film-like manner and is mechanically and electrically connected to the multiple outer embedded electrodes 32. In this embodiment, the first electrode 51a is mechanically and electrically connected to the base electrode 33 and the main electrode 34 of the multiple outer embedded electrodes 32.

[0428] The second electrode 51b, via the first electrode 51a, comprehensively covers the region of the interlayer film 40 where the outer opening 46 is formed, and extends from above the interlayer film 40 into the outer opening 46. The second electrode 51b has a portion that covers the insulating surface of the interlayer film 40 via the first electrode 51a, a portion that covers the wall surface of the outer opening 46 via the first electrode 51a, and a portion that covers the multiple rectifier structures 30 via the first electrode 51a.

[0429] In this configuration, the second electrode 51b has a portion that covers the first main surface 3 via the first electrode 51a within the outer opening 46. In this configuration, the second electrode 51b is electrically connected to the outer contact region 26 via the first electrode 51a on both sides of the plurality of rectifier structures 30. In this configuration, the second electrode 51b enters into the plurality of outer trenches 31 from above the first main surface 3.

[0430] The second electrode 51b has portions that are electrically connected to the outer contact region 26 via the first electrode 51a at the side walls and open ends of the multiple outer trenches 31. The second electrode 51b has portions that cover the multiple outer embedded electrodes 32 in a film-like manner via the first electrode 51a and is electrically connected to the multiple outer embedded electrodes 32. In this embodiment, the second electrode 51b is electrically connected to the base electrode 33 and the main electrode 34 of the multiple outer embedded electrodes 32 via the first electrode 51a.

[0431] The main electrode 52, via the base electrode 51, comprehensively covers the region of the interlayer film 40 where the outer opening 46 is formed, and penetrates the outer opening 46 from above the interlayer film 40. The main electrode 52 has a portion that covers the insulating surface of the interlayer film 40 via the base electrode 51, a portion that covers the wall surface of the outer opening 46 via the base electrode 51, and a portion that covers the rectifier structure 30 via the base electrode 51.

[0432] In this configuration, the main electrode 52 has a portion that covers the first main surface 3 via the base electrode 51 within the outer opening 46. In this configuration, the main electrode 52 is electrically connected to the outer contact region 26 via the base electrode 51 on both sides of the plurality of rectifier structures 30. In this configuration, the main electrode 52 enters into the plurality of outer trenches 31 from above the first main surface 3.

[0433] The main electrode 52 has portions that are electrically connected to the outer contact region 26 via the base electrode 51 at the side walls and opening ends of the multiple outer trenches 31. The main electrode 52 has portions that cover the multiple outer embedded electrodes 32 in a film-like manner via the base electrode 51 and is electrically connected to the outer embedded electrodes 32. In this embodiment, the main electrode 52 is electrically connected to the base electrode 33 and the main electrode 34 of the multiple outer embedded electrodes 32 via the base electrode 51.

[0434] The aforementioned outer region 9 may have the configuration shown in Figures 15B to 15F. Figures 15B to 15F are enlarged cross-sectional views showing the second to sixth examples of the outer region 9 shown in Figure 14. Although the configurations of the second to sixth examples are shown individually in Figures 15B to 15F, the outer region 9 may simultaneously include at least two of the configurations of the first to sixth examples. Furthermore, the configurations of the first to sixth examples can be combined as appropriate.

[0435] Referring to Figure 15B (second example), in this embodiment, the semiconductor device 1B includes a plurality of outer openings 46 formed in the interlayer film 40 in a one-to-one correspondence with the plurality of rectifier structures 30. In this embodiment, the plurality of outer openings 46 include a first opening 46a on the first interlayer film 41 side and a second opening 46b on the second interlayer film 42 side, respectively.

[0436] In this configuration, the first opening 46a has a width greater than the width of the corresponding rectifying structure 30, and the second opening 46b has a width smaller than the width of the corresponding rectifying structure 30. In other words, the second interlayer membrane 42 covers the first and second wall portions of the multiple first openings 46a on the first main surface 3.

[0437] In this configuration, the second opening 46b is formed only directly above the corresponding rectifier structure 30, exposing the electrode surface of the outer embedded electrode 32 (main electrode 34). In other words, the second interlayer membrane 42 has a portion that covers both ends (underlying electrode 33) of the corresponding rectifier structure 30, and the second opening 46b does not have a portion that exposes the first main surface 3.

[0438] In this configuration, the aforementioned source finger electrode 53 enters into a plurality of outer openings 46 from above the interlayer film 40 (second interlayer film 42) and is mechanically and electrically connected to a plurality of rectifying structures 30 within the plurality of outer openings 46. In other words, in this configuration, the source finger electrode 53 does not have a mechanical connection to the first main surface 3.

[0439] The source finger electrode 53 includes a base electrode 51 and a main electrode 52. The base electrode 51 has a laminated structure including a first electrode 51a and a second electrode 51b. The first electrode 51a enters a plurality of outer openings 46 from above the interlayer membrane 40 (second interlayer membrane 42) and is mechanically and electrically connected to a plurality of rectifying structures 30 (outer embedded electrodes 32) within the plurality of outer openings 46. In other words, in this embodiment, the source finger electrode 53 does not have a mechanical connection to the first main surface 3.

[0440] The second electrode 51b enters into multiple outer openings 46 from above the interlayer membrane 40 (second interlayer membrane 42) and is electrically connected to multiple rectifier structures 30 (outer embedded electrodes 32) via the second electrode 51b within the multiple outer openings 46. The main electrode 52 enters into multiple outer openings 46 from above the interlayer membrane 40 (second interlayer membrane 42) and is electrically connected to multiple rectifier structures 30 (outer embedded electrodes 32) via the base electrode 51 within the multiple outer openings 46.

[0441] Referring to Figure 15C (third example), in this embodiment, the semiconductor device 1B includes a plurality of outer openings 46 formed in the interlayer film 40 in a one-to-one correspondence with a plurality of rectifier structures 30. In this embodiment, the plurality of outer openings 46 are integrally formed with the corresponding outer trenches 31.

[0442] The multiple outer openings 46 each include a first opening 46a on the first interlayer membrane 41 side and a second opening 46b on the second interlayer membrane 42 side. The first and second walls of the first opening 46a are connected to the first and second side walls of the corresponding outer trench 31, respectively.

[0443] The first and second walls of the second opening 46b are connected to the first and second side walls of the corresponding outer trench 31, respectively. In this embodiment, the second opening 46b extends substantially perpendicular to the first main surface 3. The second opening 46b may be formed in a tapered shape, with the opening width gradually narrowing toward the corresponding outer trench 31.

[0444] In this embodiment, each of the multiple outer embedded electrodes 32 has a first portion embedded in a corresponding outer trench 31 and a second portion embedded in a corresponding outer opening 46. The first portion is mechanically and electrically connected to the wall surface (first side wall, second side wall and bottom wall) of the corresponding outer trench 31. The second portion is in contact with the interlayer membrane 40 within the corresponding outer opening 46. Specifically, the second portion is in contact with the first interlayer membrane 41 and the first interlayer membrane 41.

[0445] The plurality of outer embedded electrodes 32 each include a base electrode 33 and a main body electrode 34. In this embodiment, the base electrode 33 includes a first electrode 33a and a second electrode 33b. The first electrode 33a film-covers the wall surface of the corresponding outer trench 31 and the wall surface of the corresponding outer opening 46. The first electrode 33a forms a hetero-junction (Schottky junction) with the second semiconductor layer 7 and is electrically connected to the outer well region 25 and the outer contact region 26.

[0446] The second electrode 33b film-covers the wall surface of the corresponding outer trench 31 and the wall surface of the corresponding outer opening 46 via the first electrode 33a. The second electrode 33b is electrically connected to the second semiconductor layer 7, the outer well region 25, and the outer contact region 26 via the first electrode 33a.

[0447] The main body electrode 34 is embedded in the corresponding outer trench 31 and the corresponding outer opening 46 via the base electrode 33. That is, the main body electrode 34 has a portion embedded in the outer trench 31 via the base electrode 33 and a portion embedded in the outer opening 46 via the base electrode 33.

[0448] The main body electrode 34 has a portion facing the second semiconductor layer 7, the outer well region 25, and the outer contact region 26 via the base electrode 33, and is electrically connected to the second semiconductor layer 7, the outer well region 25, and the outer contact region 26 via the base electrode 33. The main body electrode 34 has a portion facing the interlayer film 40 (the first interlayer film 41 and the second interlayer film 42) via the base electrode 33.

[0449] In this embodiment, the aforementioned source finger electrode 53 enters into the plurality of outer openings 46 from above the interlayer film 40 (the second interlayer film 42) and is mechanically and electrically connected to the rectifying structure 30 within the plurality of outer openings 46.

[0450] Specifically, in this form, the source finger electrode 53 is mechanically and electrically connected to a plurality of rectifying structures 30 at a height position on the insulating surface side of the interlayer film 40 from the first main surface 3. More specifically, in this form, the source finger electrode 53 is mechanically and electrically connected to a plurality of outer buried electrodes 32 within a plurality of outer openings 46 (second openings 46b).

[0451] The source finger electrode 53 includes a base electrode 51 and a main body electrode 52. The base electrode 51 has a stacked structure including a first electrode 51a and a second electrode 51b. The first electrode 51a enters a plurality of outer openings 46 (second openings 46b) from above the interlayer film 40 (second interlayer film 42) and is mechanically and electrically connected to a plurality of outer buried electrodes 32 within the plurality of outer openings 46.

[0452] The second electrode 51b enters a plurality of outer openings 46 (second openings 46b) from above the interlayer film 40 (second interlayer film 42) and is electrically connected to a plurality of outer buried electrodes 32 through the plurality of first electrodes 51a within the plurality of outer openings 46. The main body electrode 52 enters a plurality of outer openings 46 (second openings 46b) from above the interlayer film 40 (second interlayer film 42) and is electrically connected to a plurality of outer buried electrodes 32 through the base electrode 51 within the plurality of outer openings 46.

[0453] Referring to FIG. 15D (the fourth example), in this form, the outer buried electrodes 32 of the plurality of rectifying structures 30 do not have a base electrode 33 and each include a main body electrode 34 embedded as an integral body in the corresponding outer trench 31. The main body electrode 34 is made of a metal film including any one of the aforementioned metal groups, an alloy film including any one of the aforementioned alloy groups, or a non-metal conductor film including any one of the aforementioned non-metal conductors. The main body electrode 34 may be made of tungsten or conductive polysilicon.

[0454] The main electrode 34 is directly embedded in the corresponding outer trench 31 and is mechanically and electrically connected to the wall surface (chip 2) of the corresponding outer trench 31. Specifically, the main electrode 34 forms a heterojunction (Schottky junction) with the second semiconductor layer 7 and is electrically connected to the outer well region 25 and the outer contact region 26.

[0455] The source finger electrode 53 includes a base electrode 51 and a main electrode 52. The base electrode 51 has a laminated structure including a first electrode 51a and a second electrode 51b. The first electrode 51a coats the main electrode 34 in a film-like manner within a plurality of outer trenches 31 and is mechanically and electrically connected to the plurality of main electrode 34. The first electrode 51a may also be mechanically and electrically connected to the outer contact region 26 via the open ends of the plurality of outer trenches 31.

[0456] The second electrode 51b coats the multiple main electrodes 34 in a film-like manner via the first electrode 51a within the multiple outer trenches 31. The second electrode 51b may have portions that cover the side walls and open ends of the multiple outer trenches 31 via the first electrode 51a.

[0457] The main electrode 52 covers multiple main electrodes 34 within multiple outer trenches 31 via the base electrode 51. The main electrode 52 may have portions that cover the side walls and open ends of the multiple outer trenches 31 via the base electrode 51.

[0458] Referring to Figure 15E (Fifth Example), the aforementioned source finger electrode 53 includes a base electrode 51 and a main electrode 52. In this embodiment, the base electrode 51 is integrally formed with the base electrode 33 of the multiple outer embedded electrodes 32, and the main electrode 52 is formed separately from the main electrode 34 of the multiple outer embedded electrodes 32. The configuration in which the base electrode 51 is integrally formed with the base electrode 33 and the main electrode 52 is formed separately from the main electrode 34 is also applicable to the first to fourth examples described above.

[0459] The base electrode 51 has a laminated structure including a first electrode 51a and a second electrode 51b. The first electrode 51a penetrates into a plurality of outer openings 46 (second openings 46b) from above the interlayer film 40 (second interlayer film 42). The first electrode 51a has a portion that covers the insulating surface of the interlayer film 40 in a film-like manner, a portion that covers the wall surface of the outer opening 46 in a film-like manner, and a portion that covers the first main surface 3 (outer contact region 26) within the outer opening 46 in a film-like manner.

[0460] The first electrode 51a enters into a plurality of outer trenches 31 from above the first main surface 3 and is connected to the first electrode 33a of a plurality of outer embedded electrodes 32 within the plurality of outer trenches 31. In other words, the first electrode 51a is formed as a single electrode film with the plurality of first electrodes 33a. At the open ends of the plurality of outer trenches 31, the connection portion between the plurality of first electrodes 33a and the first electrode 51a may be considered as part of the plurality of first electrodes 33a or as part of the first electrode 51a.

[0461] The second electrode 51b extends from above the interlayer film 40 (second interlayer film 42) into the outer opening 46 (second opening 46b). The second electrode 51b has a portion that covers the insulating surface of the interlayer film 40 in a film-like manner via the first electrode 51a, a portion that covers the wall surface of the outer opening 46 in a film-like manner via the first electrode 51a, and a portion that covers the first main surface 3 (outer contact region 26) in a film-like manner within the outer opening 46 via the first electrode 51a.

[0462] The second electrode 51b enters the outer trench 31 from above the first main surface 3 and is connected to the second electrodes 33b of the multiple outer embedded electrodes 32 within the outer trench 31. In other words, the second electrode 51b is formed as a single electrode film with the multiple second electrodes 33b. At the open ends of the multiple outer trenches 31, the connection portion between the multiple second electrodes 33b and the second electrode 51b may be considered as part of the multiple second electrodes 33b or as part of the second electrode 51b.

[0463] The main electrode 52 enters the outer opening 46 from above the interlayer film 40 (second interlayer film 42). The main electrode 52 has a portion that covers the insulating surface of the interlayer film 40 in a film-like manner via the base electrode 51, a portion that covers the wall surface of the outer opening 46 in a film-like manner via the base electrode 51, and a portion that covers the first main surface 3 (outer contact region 26) in a film-like manner within the outer opening 46 via the base electrode 51.

[0464] The main electrode 52 has a portion that directly covers the multiple outer embedded electrodes 32 in a film-like manner within the multiple outer trenches 31. Specifically, the main electrode 52 is mechanically and electrically connected to the main electrodes 34 of the multiple outer embedded electrodes 32.

[0465] Referring to Figure 15F (Sixth Example), the aforementioned source finger electrode 53 includes a base electrode 51 and a main electrode 52. In this embodiment, the base electrode 51 is integrally formed with the base electrode 33 of the multiple outer embedded electrodes 32, and the main electrode 52 is integrally formed with the main electrode 34 of the multiple outer embedded electrodes 32. The configuration in which the base electrode 51 is integrally formed with the base electrode 33 and the main electrode 52 is integrally formed with the main electrode 34 is also applicable to the first to fourth examples described above.

[0466] The base electrode 51 has a laminated structure including a first electrode 51a and a second electrode 51b. The first electrode 51a extends from above the interlayer film 40 (second interlayer film 42) into the outer opening 46 (second opening 46b). The first electrode 51a has a portion that covers the insulating surface of the interlayer film 40 in a film-like manner, a portion that covers the wall surface of the outer opening 46 in a film-like manner, and a portion that covers the first main surface 3 (outer contact region 26) within the outer opening 46 in a film-like manner.

[0467] The first electrode 51a enters into a plurality of outer trenches 31 from above the first main surface 3 and is integrally formed with the first electrode 33a of the plurality of outer embedded electrodes 32 within the plurality of outer trenches 31.

[0468] In other words, the first electrode 51a is formed as a single electrode film with a plurality of first electrodes 33a. At the open ends of the plurality of outer trenches 31, the connection portion of the plurality of first electrodes 33a and the first electrode 51a may be considered as part of the plurality of first electrodes 33a or as part of the first electrode 51a.

[0469] The second electrode 51b extends from above the interlayer film 40 (second interlayer film 42) into the outer opening 46 (second opening 46b). The second electrode 51b has a portion that covers the insulating surface of the interlayer film 40 in a film-like manner via the first electrode 51a, a portion that covers the wall surface of the outer opening 46 in a film-like manner via the first electrode 51a, and a portion that covers the first main surface 3 (outer contact region 26) in a film-like manner within the outer opening 46 via the first electrode 51a.

[0470] The second electrode 51b enters into a plurality of outer trenches 31 from above the first main surface 3 and is integrally formed with the second electrode 33b of the plurality of outer embedded electrodes 32 within the plurality of outer trenches 31.

[0471] In other words, the second electrode 51b is formed as a single electrode film with a plurality of second electrodes 33b. At the open ends of the plurality of outer trenches 31, the connection portions of the plurality of second electrodes 33b and the second electrode 51b may be considered as part of the plurality of second electrodes 33b or as part of the second electrode 51b.

[0472] The main electrode 52 enters the outer opening 46 from above the interlayer film 40 (second interlayer film 42). The main electrode 52 has a portion that covers the insulating surface of the interlayer film 40 in a film-like manner via the base electrode 51, a portion that covers the wall surface of the outer opening 46 in a film-like manner via the base electrode 51, and a portion that covers the first main surface 3 (outer contact region 26) in a film-like manner within the outer opening 46 via the base electrode 51.

[0473] The main electrode 52 enters into multiple outer trenches 31 from above the first main surface 3 and is integrally formed with the main electrode 34 of multiple outer embedded electrodes 32 within the multiple outer trenches 31.

[0474] In other words, the main electrode 52 is formed as a single electrode film with the main electrode 34. At the openings of the multiple outer trenches 31, the connection portions of the multiple main electrodes 34 and the main electrode 52 may be considered as part of the multiple main electrodes 34 or as part of the main electrode 52.

[0475] Figure 16 is a plan view showing an example of the layout of the first main surface 3 of the semiconductor device 1C according to the third embodiment. Figure 17 is a cross-sectional view of the outer region 9. Figure 18A is an enlarged cross-sectional view showing a first example of the outer region 9 shown in Figure 17. The semiconductor device 1C has a configuration that is a modification of the configuration of the outer region 9 of the semiconductor device 1A.

[0476] The semiconductor device 1C includes an n-type diode region 60 formed in the second semiconductor layer 7 in the outer region 9. In this embodiment, the diode region 60 is formed using a part of the second semiconductor layer 7 and has an n-type impurity concentration approximately equal to that of the second semiconductor layer 7. The n-type impurity concentration of the diode region 60 may be higher or lower than that of the second semiconductor layer 7.

[0477] The diode region 60 is formed in the outer region 9, spaced apart from the periphery of the first main surface 3 and the active region 8. In plan view, the diode region 60 extends in a band shape along the active region 8. In this embodiment, the diode region 60 is formed in a polygonal ring shape (a quadrilateral ring in this embodiment) with four sides parallel to the periphery of the first main surface 3 in plan view, and surrounds the active region 8 (multiple gate structures 15).

[0478] The diode region 60 may have an edge portion that connects a portion extending in a strip shape in a first direction X and a portion extending in a strip shape in a second direction Y in an arc shape (preferably a quarter-circular arc shape). The diode region 60 has an inner edge portion on the inner side of the first main surface 3 and an outer edge portion on the peripheral side of the first main surface 3.

[0479] In this form, the diode region 60 is connected to the first semiconductor layer 6. When the n-type impurity concentration of the diode region 60 is different from that of the second semiconductor layer 7, the diode region 60 may be formed at a distance from the bottom of the second semiconductor layer 7 toward the first main surface 3 side and may face the first semiconductor layer 6 through a part of the second semiconductor layer 7.

[0480] In this case, the diode region 60 may be formed at a distance from the depth position of the middle part of the second semiconductor layer 7 toward the first main surface 3 side, or may have a portion located on the bottom side of the second semiconductor layer 7 with respect to the depth position of the middle part of the second semiconductor layer 7.

[0481] In this form, the diode region 60 has a depth greater than the depth of the plurality of gate structures 15. The depth of the diode region 60 may be smaller than the depth of the plurality of gate structures 15. In this form, the diode region 60 has a width greater than the width of the plurality of gate structures 15. The width of the diode region 60 may be smaller than the width of the plurality of gate structures 15.

[0482] The semiconductor device 1C includes an outer well region 25 formed in the peripheral portion (outer region 9) of the second semiconductor layer 7. The p-type impurity concentration of the outer well region 25 may be higher or lower than the p-type impurity concentration of the body region 10. The p-type impurity concentration of the outer well region 25 is lower than the p-type impurity concentration of the contact region 21.

[0483] In this form, the outer well region 25 is formed on both sides of the diode region 60. Specifically, the outer well region 25 includes an inner first outer well region 25A and an outer second outer well region 25B. The outer well region 25 may consist of only one of the first outer well region 25A and the second outer well region 25B.

[0484] The first outer well region 25A is formed in the region on the inner side (active region 8 side) of the first main surface 3 relative to the diode region 60, and demarcates the diode region 60 from the inner side of the first main surface 3. The first outer well region 25A is formed in the surface layer of the second semiconductor layer 7, and replaces the conductivity type of the second semiconductor layer 7 from n type to p type.

[0485] The first outer well region 25A extends in layers along the first main surface 3. In a plan view, the first outer well region 25A extends in a band shape along the active region 8 (diode region 60). In this configuration, the first outer well region 25A is formed as a polygonal ring (a quadrilateral ring in this configuration) with four sides parallel to the periphery of the first main surface 3 in a plan view, and surrounds the active region 8 (multiple gate structures 15).

[0486] The first outer well region 25A may have an edge portion that connects a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y in an arc shape (preferably a quarter arc shape). The first outer well region 25A has an inner edge portion on the inner side of the first main surface 3 and an outer edge portion on the peripheral side of the first main surface 3.

[0487] The inner edge defines the boundary between the active region 8 and the outer region 9. The inner edge may be connected to either or both of the body region 10 and the well region 22. The inner edge may be connected to a plurality of gate structures 15. The outer edge extends substantially parallel to the inner edge and defines the diode region 60.

[0488] The first outer well region 25A is formed with a gap from the bottom of the second semiconductor layer 7 toward the first main surface 3 and faces the first semiconductor layer 6 through a part of the second semiconductor layer 7. The first outer well region 25A may be formed with a gap from the depth position of the middle part of the second semiconductor layer 7 toward the first main surface 3, or it may have a portion located toward the bottom of the second semiconductor layer 7 relative to the depth position of the middle part of the second semiconductor layer 7.

[0489] In this embodiment, the first outer well region 25A has a depth greater than the depth of the multiple gate structures 15. The depth of the first outer well region 25A may be less than the depth of the multiple gate structures 15.

[0490] The depth of the first outer well region 25A may be approximately equal to the depth of the body region 10. The depth of the first outer well region 25A may be greater than or less than the depth of the body region 10. In this embodiment, the depth of the first outer well region 25A is approximately equal to the depth of the well region 22. The depth of the first outer well region 25A may be greater than or less than the depth of the well region 22.

[0491] The first outer well region 25A forms a pn junction with the second semiconductor layer 7 and the diode region 60. This forms a bipolar diode DB including the second semiconductor layer 7 as the cathode region and the first outer well region 25A as the anode region.

[0492] When a reverse bias voltage is applied, the depletion layer that extends from the first outer well region 25A extends the depletion layer that extends from the body region 10 (active region 8) towards the periphery of the first main surface 3, thereby mitigating the electric field strength (electric field concentration) in the outer region 9.

[0493] The second outer well region 25B is formed in the peripheral region of the first main surface 3 relative to the diode region 60, and demarcates the diode region 60 from the peripheral side of the first main surface 3. The second outer well region 25B faces the first outer well region 25A across the diode region 60, and together with the first outer well region 25A, demarcates the diode region 60. The second outer well region 25B is formed in the surface layer of the second semiconductor layer 7, and replaces the conductivity type of the second semiconductor layer 7 from n-type to p-type.

[0494] The second outer well region 25B extends in layers along the first main surface 3. In plan view, the second outer well region 25B extends in a band shape along the active region 8 (diode region 60). In this configuration, the second outer well region 25B is formed as a polygonal ring (a quadrilateral ring in this configuration) with four sides parallel to the periphery of the first main surface 3 in plan view, and surrounds the active region 8 (multiple gate structures 15).

[0495] The second outer well region 25B may have an edge portion that connects a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y in an arc shape (preferably a quarter arc shape). The second outer well region 25B has an inner edge portion on the inner side of the first main surface 3 and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion extends along the diode region 60 and defines the diode region 60. The outer edge portion extends substantially parallel to the inner edge portion.

[0496] The second outer well region 25B is formed with a gap from the bottom of the second semiconductor layer 7 toward the first main surface 3 and faces the first semiconductor layer 6 through a part of the second semiconductor layer 7. The second outer well region 25B may be formed with a gap from the depth position of the middle part of the second semiconductor layer 7 toward the first main surface 3, or it may have a portion located toward the bottom of the second semiconductor layer 7 relative to the depth position of the middle part of the second semiconductor layer 7.

[0497] The second outer well region 25B has a depth approximately equal to the depth of the first outer well region 25A. The depth of the second outer well region 25B may be greater or less than the depth of the first outer well region 25A. The second outer well region 25B has a depth greater than the depth of the multiple gate structures 15. The depth of the second outer well region 25B may be less than the depth of the multiple gate structures 15.

[0498] The depth of the second outer well region 25B may be approximately equal to the depth of the body region 10. The depth of the second outer well region 25B may be greater than or less than the depth of the body region 10. The depth of the second outer well region 25B may be approximately equal to the depth of the well region 22. The depth of the second outer well region 25B may be greater than or less than the depth of the well region 22.

[0499] The second outer well region 25B forms a pn junction with the second semiconductor layer 7 and the diode region 60. This forms a bipolar diode DB including the second semiconductor layer 7 as the cathode region and the second outer well region 25B as the anode region.

[0500] When a reverse bias voltage is applied, the depletion layer extending from the second outer well region 25B extends the depletion layer extending from the first outer well region 25A toward the periphery of the first main surface 3, thereby mitigating the electric field strength (electric field concentration) in the outer region 9. The depletion layer extending from the second outer well region 25B may be integrated with the depletion layer extending from the first outer well region 25A in the diode region 60.

[0501] The semiconductor device 1C includes an outer contact region 26 formed on the surface of the outer well region 25. The outer contact region 26 has a higher p-type impurity concentration than the p-type impurity concentration of the outer well region 25.

[0502] The p-type impurity concentration in the outer contact region 26 is higher than that in the body region 10. The p-type impurity concentration in the outer contact region 26 may be approximately equal to that in the contact region 21. The p-type impurity concentration in the outer contact region 26 may be greater or less than that in the contact region 21.

[0503] In this embodiment, the outer contact region 26 is formed on both sides of the diode region 60. Specifically, the outer contact region 26 includes an inner first outer contact region 26A and an outer second outer contact region 26B. The outer contact region 26 may consist of only one of the first outer contact region 26A and the second outer contact region 26B.

[0504] The first outer contact region 26A is formed on the surface of the first outer well region 25A and extends in layers along the first main surface 3. In a plan view, the first outer contact region 26A extends in a strip shape along the active region 8 (diode region 60).

[0505] In this embodiment, the first outer contact region 26A is formed as a polygonal ring (a quadrilateral ring in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view, and surrounds the active region 8 (a plurality of gate structures 15). The first outer contact region 26A may have an edge portion that connects a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y in an arc shape (preferably a quarter-circular arc shape).

[0506] The first outer contact region 26A has a first extension 62A that crosses the outer edge of the first outer well region 25A and extends into the diode region 60. The first extension 62A replaces the conductivity type of a part of the diode region 60 from n-type to p-type. The first extension 62A is formed with a gap between the inner edge of the second outer well region 25B and the outer edge of the first outer well region 25A, and partitions a part of the diode on the surface of the first main surface 3.

[0507] The first outer contact region 26A has an inner edge portion on the inner side of the first main surface 3 and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion is located within the first outer well region 25A. The inner edge portion may be formed at intervals from the plurality of gate structures 15. The inner edge portion may be connected to the ends of the plurality of gate structures 15. The outer edge portion is located within the diode region 60 as the first extension portion 62A.

[0508] The first outer contact region 26A is formed with a gap from the bottom of the first outer well region 25A toward the first main surface 3, and faces the second semiconductor layer 7 via a part of the first outer well region 25A.

[0509] The first outer contact region 26A may be formed with a gap from the depth position of the intermediate part of the first outer well region 25A toward the first main surface 3, or it may have a portion located toward the bottom side of the first outer well region 25A relative to the depth position of the intermediate part of the first outer well region 25A.

[0510] The first outer contact region 26A has a depth smaller than the depth of the multiple gate structures 15. The depth of the first outer contact region 26A may be greater than the depth of the multiple gate structures 15. The depth of the first outer contact region 26A may be greater than or less than the depth of the body region 10.

[0511] The second outer contact region 26B is formed on the surface of the second outer well region 25B and extends in layers along the first main surface 3. In a plan view, the second outer contact region 26B extends in a strip-like shape along the active region 8 (diode region 60).

[0512] In this embodiment, the second outer contact region 26B is formed as a polygonal ring (a quadrilateral ring in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view, and surrounds the active region 8 (a plurality of gate structures 15). The second outer contact region 26B may have an edge portion that connects a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y in an arc shape (preferably a quarter-circular arc shape).

[0513] The second outer contact region 26B has a second extension 62B that crosses the inner edge of the second outer well region 25B and extends into the diode region 60. The second extension 62B replaces the conductivity type of a part of the diode region 60 from n-type to p-type.

[0514] The second extension 62B is formed at a distance from the outer edge of the first outer well region 25A toward the inner edge of the second outer well region 25B, and partitions a part of the diode on the surface of the first main surface 3. Specifically, the second extension 62B is formed at a distance from the first extension 62A of the first outer contact region 26A, and together with the first extension 62A, partitions a part of the diode.

[0515] The second outer contact region 26B has an inner edge portion on the inner side of the first main surface 3 and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion is located within the diode region 60 as a second extension portion 62B. The outer edge portion is located within the second outer well region 25B.

[0516] The second outer contact region 26B is formed with a gap from the bottom of the second outer well region 25B toward the first main surface 3, and faces the second semiconductor layer 7 via a part of the second outer well region 25B.

[0517] The second outer contact region 26B may be formed with a gap from the depth position of the middle part of the second outer well region 25B toward the first main surface 3, or it may have a portion located toward the bottom side of the second outer well region 25B relative to the depth position of the middle part of the second outer well region 25B.

[0518] The second outer contact region 26B has a depth approximately equal to the depth of the first outer contact region 26A. The depth of the second outer contact region 26B may be greater or less than the depth of the first outer contact region 26A.

[0519] The depth of the second outer contact region 26B is less than the depth of the multiple gate structures 15. The depth of the second outer contact region 26B may be greater than the depth of the multiple gate structures 15. The depth of the second outer contact region 26B may be greater than or less than the depth of the body region 10.

[0520] The semiconductor device 1C, as in the first embodiment, includes at least one (multiple in this embodiment) p-type field regions 27 formed on the peripheral edge (outer region 9) of the second semiconductor layer 7. In this embodiment, the multiple field regions 27 are formed with a gap between them and the peripheral edge of the first main surface 3, extending from the diode region 60. Specifically, the multiple field regions 27 are formed with a gap between them and the peripheral edge of the first main surface 3, extending from the second outer well region 25B.

[0521] The multiple field regions 27 have a depth approximately equal to the depth of the first outer contact region 26A and the depth of the second outer contact region 26A. The depth of the multiple field regions 27 may be greater than or less than the depth of the first outer contact region 26A. The depth of the multiple field regions 27 may be greater than or less than the depth of the second outer contact region 26B. The other configurations of the multiple field regions 27 are the same as in the first embodiment.

[0522] The semiconductor device 1C, as in the first embodiment, includes an interlayer film 40 that selectively covers the first main surface 3. The interlayer film 40 has a laminated structure including a first interlayer film 41 and a second interlayer film 42. In this embodiment, the first interlayer film 41 covers the first outer well region 25A, the second outer well region 25B, the first outer contact region 26A, the second outer contact region 26B, and a plurality of field regions 27 in the outer region 9.

[0523] In this configuration, the second interlayer membrane 42 covers the first outer well region 25A, the second outer well region 25B, the first outer contact region 26A, the second outer contact region 26B, and multiple field regions 27 via the first interlayer membrane 41 in the outer region 9.

[0524] The semiconductor device 1C, as in the first embodiment, includes one or more (one in this embodiment) outer openings 46 formed in the interlayer film 40. The outer openings 46 penetrate the first interlayer film 41 and the second interlayer film 42, selectively exposing the diode region 60. In other words, in this embodiment, the second opening 41b communicates with the first opening 41a, and together with the first opening 41a, forms one outer opening 46.

[0525] The outer opening 46 is formed with a gap between it and the diode region 60 from the gate wiring 43, and also with a gap between it and the periphery of the first main surface 3 towards the diode region 60. The outer opening 46 is formed with a gap between it and the diode region 60 from the multiple field regions 27 (the innermost field region 27).

[0526] The outer opening 46 extends in a strip shape following the direction of extension of the diode region 60. The outer opening 46 has a portion that extends in a strip shape in a first direction X and a portion that extends in a strip shape in a second direction Y. In this embodiment, the outer opening 46 is formed as an endless polygonal ring (for example, a quadrilateral ring) having four sides parallel to the periphery of the first main surface 3, and surrounds the active region 8 (multiple gate structures 15).

[0527] The outer opening 46 may be formed in the shape of a strip with ends. The outer opening 46 may have an edge portion that connects the portion extending in a strip shape in the first direction X and the portion extending in a strip shape in the second direction Y in an arc shape (preferably a quarter arc shape) when viewed from above.

[0528] In this configuration, the outer opening 46 is formed in a tapered shape, with the opening width gradually narrowing from the opening end toward the first main surface 3 in a cross-sectional view. The outer opening 46 may also be formed substantially perpendicular to the first main surface 3 in a cross-sectional view.

[0529] In this configuration, the outer opening 46 has a width greater than the width of the diode region 60 in cross-sectional view, exposing the diode region 60, the first extension 62A of the first outer contact region 26A, and the second extension 62B of the second outer contact region 26B. In this configuration, the outer opening 46 overlaps the outer edge of the first outer well region 25A and the inner edge of the second outer well region 25B in the thickness direction Z.

[0530] In this configuration, the outer opening 46 exposes the inner portion of the first outer contact region 26A in the portion that overlaps with the outer edge of the first outer well region 25A in the thickness direction Z, and exposes the inner portion of the second outer contact region 26B in the portion that overlaps with the inner edge of the second outer well region 25B in the thickness direction Z.

[0531] The outer opening 46 has a first wall portion on the side of the first outer well region 25A and a second wall portion on the side of the second outer well region 25B. The first wall portion is partitioned from the inner edge of the first outer contact region 26A toward the second outer well region 25B with a gap between them.

[0532] The second wall portion is partitioned with a gap between the outer edge of the second outer contact region 26B and the first outer well region 25A. The outer opening 46 may expose the entire area of ​​both the first outer contact region 26A and the entire area of ​​the second outer contact region 26B.

[0533] The semiconductor device 1C includes an outer recess 61 formed on the first main surface 3 in the portion exposed from the outer opening 46. The outer recess 61 is the portion that forms the bottom wall of the outer opening 46 and is carved out in the thickness direction Z from the first main surface 3. The semiconductor device 1C does not necessarily have to have an outer recess 61, and the bottom wall of the outer opening 46 may be formed by the first main surface 3.

[0534] The outer recess 61 extends in a band shape in a plan view, following the direction of extension of the outer opening 46. The outer recess 61 has a portion that extends in a band shape in a first direction X and a portion that extends in a band shape in a second direction Y. In this embodiment, the outer recess 61 is formed as an endless polygonal ring (for example, a quadrilateral ring) with four sides parallel to the periphery of the first main surface 3, and surrounds the active region 8 (multiple gate structures 15).

[0535] The outer recess 61 may be formed in the shape of an ended strip. The outer recess 61 may have an edge portion that connects the portion extending in a strip shape in the first direction X and the portion extending in a strip shape in the second direction Y in an arc shape (preferably a quarter arc shape) when viewed from above.

[0536] The outer recess 61 has a depth smaller than the depth of the first outer well region 25A and the depth of the second outer well region 25B, exposing the diode region 60, the first extension 62A of the first outer contact region 26A, and the second extension 62B of the second outer contact region 26B.

[0537] In this embodiment, the depth of the outer recess 61 is smaller than the depth of the first outer contact region 26A and the depth of the second outer contact region 26B. The outer recess 61 exposes the diode region 60, the first extension 62A, and the second extension 62B from the bottom wall.

[0538] The semiconductor device 1C, as in the first embodiment, includes a source finger electrode 53 drawn out from the source electrode 50 onto the first main surface 3. In this embodiment, the source finger electrode 53 is formed as a planar electrode type rectifier structure (30) that forms a diode region 60 and a unipolar diode DU. The rectifier structure (30) may be considered to include the diode region 60 and the source finger electrode 53.

[0539] The source finger electrode 53 enters the outer opening 46 from above the interlayer film 40 and is mechanically and electrically connected to the diode region 60, the first extension 62A of the first outer contact region 26A, and the second extension 62B of the second outer contact region 26B within the outer opening 46 (outer recess 61 in this configuration).

[0540] The source potential applied to the source electrode 50 is applied to the first outer well region 25A via the first outer contact region 26A, and to the second outer well region 25B via the second outer contact region 26B.

[0541] The source finger electrode 53 forms a Schottky junction as a heterojunction at the connection interface with the diode region 60. In this embodiment, the source finger electrode 53 forms a Schottky junction with the diode region 60 at the bottom wall of the outer recess 61. This forms a unipolar diode DU including the source finger electrode 53 as the anode region and the diode region 60 as the cathode region.

[0542] The source finger electrode 53 has an inner edge portion on the inner side of the first main surface 3 and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion is positioned at a distance from the gate wiring 43 towards the peripheral side of the first main surface 3 and faces the first outer well region 25A in the stacking direction. The inner edge portion may also be formed at a distance from the middle of the first outer well region 25A towards the peripheral side of the first main surface 3. The inner edge portion may also face the first outer contact region 26A in the stacking direction.

[0543] The outer edge is formed at intervals from multiple field regions 27 toward the inward side of the first main surface 3. In this embodiment, the outer edge is formed at intervals from the inner edge of the second outer well region 25B toward the peripheral edge of the first main surface 3 and is located on the second outer well region 25B. The outer edge may face the second outer contact region 26B. The outer edge may face the second semiconductor layer 7.

[0544] The source finger electrode 53 may also include a metal film containing at least one of magnesium (Mg), aluminum (Al), titanium (Ti), vanadium (V), chromium (Cr), manganese (Mn), cobalt (Co), nickel (Ni), copper (Cu), zirconium (Zr), niobium (Nb), molybdenum (Mo), palladium (Pd), silver (Ag), indium (In), tin (Sn), tantalum (Ta), tungsten (W), platinum (Pt), and gold (Au), as in the first embodiment.

[0545] The source finger electrode 53 may include an alloy film containing at least one of the following: magnesium alloy, aluminum alloy, titanium alloy, vanadium alloy, chromium alloy, manganese alloy, cobalt alloy, nickel alloy, copper alloy, zirconium alloy, niobium alloy, molybdenum alloy, palladium alloy, silver alloy, indium alloy, tin alloy, tantalum alloy, tungsten alloy, platinum alloy, and gold alloy.

[0546] The source finger electrode 53 may include a conductive film containing conductive polysilicon as an example of a nonmetallic conductor. The conductive film may contain either p-type conductive polysilicon or n-type conductive polysilicon, or both.

[0547] The source finger electrode 53 has a laminated structure including a base electrode 51 and a main electrode 52 stacked in this order from the first main surface 3 side, similar to the first embodiment. The base electrode 51 is formed as a barrier electrode for the second semiconductor layer 7 and has a single-layer structure consisting of a single conductive film or a laminated structure consisting of multiple conductive films.

[0548] In this embodiment, the base electrode 51 has a laminated structure including a first electrode 51a and a second electrode 51b. The first electrode 51a consists of a metal film containing any one of the aforementioned metals or an alloy film containing any one of the aforementioned alloys. In this embodiment, the first electrode 51a consists of a titanium film.

[0549] The first electrode 51a comprehensively covers the region of the interlayer film 40 where the outer opening 46 is formed, and extends from above the interlayer film 40 into the outer opening 46. The first electrode 51a has a portion that covers the insulating surface of the interlayer film 40 in a film-like manner, a portion that covers the wall surface of the outer opening 46 in a film-like manner, and a portion that covers the first main surface 3 (outer recess 61 in this embodiment) in a film-like manner.

[0550] In this configuration, the first electrode 51a covers the diode region 60, the first extension 62A, and the second extension 62B in a film-like manner with its first main surface 3 (outer recess 61), and is mechanically and electrically connected to the diode region 60, the first extension 62A, and the second extension 62B. The first electrode 51a forms a Schottky junction with the diode region 60 and an ohmic junction with the first outer contact region 26A and the second outer contact region 26B.

[0551] The portion of the first electrode 51a that covers the outer recess 61 may be formed with a gap between it and the bottom wall side of the outer recess 61, relative to the height position of the first main surface 3. The portion of the first electrode 51a that covers the outer recess 61 may have a portion located on the bottom wall side of the outer recess 61 with respect to the height position of the first main surface 3, and a portion located on the interlayer film 40 side with respect to the height position of the first main surface 3.

[0552] The first electrode 51a may have a thickness of 10 nm to 200 nm. The thickness of the first electrode 51a may have a value that falls within at least one of the following ranges: 10 nm to 25 nm, 25 nm to 50 nm, 50 nm to 75 nm, 75 nm to 100 nm, 100 nm to 125 nm, 125 nm to 150 nm, 150 nm to 175 nm, and 175 nm to 200 nm.

[0553] The second electrode 51b consists of a metal film containing one of the aforementioned metals or an alloy film containing one of the aforementioned alloys. The second electrode 51b is made of a different conductor than the first electrode 51a. In this embodiment, the second electrode 51b consists of a titanium nitride film (titanium alloy film).

[0554] The second electrode 51b is stacked on top of the first electrode 51a. The second electrode 51b covers the region of the interlayer film 40 where the outer opening 46 is formed in one piece via the first electrode 51a, and penetrates the outer opening 46 from above the interlayer film 40.

[0555] The second electrode 51b has a portion that covers the insulating surface of the interlayer film 40 in a film-like manner via the first electrode 51a, a portion that covers the wall surface of the outer opening 46 in a film-like manner via the first electrode 51a, and a portion that covers the first main surface 3 (outer recess 61 in this embodiment) in a film-like manner via the first electrode 51a.

[0556] In this configuration, the second electrode 51b is electrically connected to the diode region 60, the first extension 62A, and the second extension 62B via the first electrode 51a at the first main surface 3 (outer recess 61).

[0557] In this embodiment, the second electrode 51b has a thickness greater than the thickness of the first electrode 51a. The thickness of the second electrode 51b may be less than the thickness of the first electrode 51a. The portion of the second electrode 51b that covers the outer recess 61 may be formed with a gap between it and the bottom wall side of the outer recess 61, from the height position of the first main surface 3.

[0558] The portion of the second electrode 51b that covers the outer recess 61 may have a portion located on the bottom wall side of the outer recess 61 with respect to the height position of the first main surface 3, and a portion located on the interlayer film 40 side with respect to the height position of the first main surface 3.

[0559] The thickness of the second electrode 51b may be 10 nm or more and 300 nm or less. The thickness of the second electrode 51b may have a value that falls within at least one of the following ranges: 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, 125 nm or more and 150 nm or less, 150 nm or more and 175 nm or less, 175 nm or more and 200 nm or less, 200 nm or more and 225 nm or less, 225 nm or more and 250 nm or less, 250 nm or more and 275 nm or more and 300 nm or less.

[0560] The main electrode 52 consists of a metal film containing one of the aforementioned metals, an alloy film containing one of the aforementioned alloys, or a nonmetallic conductive film containing one of the aforementioned nonmetallic conductors. The main electrode 52 is made of a different conductor than the first electrode 51a and the second electrode 51b. In this embodiment, the main electrode 52 consists of an aluminum alloy film. The aluminum alloy may contain at least one of AlSi alloy, AlCu alloy, and AlSiCu alloy.

[0561] The main electrode 52 covers the base electrode 51 in a film-like manner. The main electrode 52, via the base electrode 51, comprehensively covers the region of the interlayer film 40 in which the outer opening 46 is formed, and penetrates the outer opening 46 from above the interlayer film 40.

[0562] The main electrode 52 has a portion that covers the insulating surface of the interlayer film 40 in a film-like manner via the base electrode 51, a portion that covers the wall surface of the outer opening 46 in a film-like manner via the base electrode 51, and a portion that covers the first main surface 3 (outer recess 61 in this embodiment) in a film-like manner via the base electrode 51.

[0563] In this embodiment, the main electrode 52 is electrically connected to the diode region 60, the first extension 62A, and the second extension 62B via the base electrode 51 on the first main surface 3 (outer recess 61). The main electrode 52 may cover the base electrode 51 on the bottom wall side of the outer recess 61, above the height position of the first main surface 3. The main electrode 52 may also cover the base electrode 51 on the interlayer film 40 side, above the height position of the first main surface 3.

[0564] The main electrode 52 has a thickness greater than the thickness of the base electrode 51 (the total thickness of the first electrode 51a and the second electrode 51b). In this embodiment, the thickness of the main electrode 52 is greater than the thickness of the interlayer film 40. The thickness of the main electrode 52 may be less than the thickness of the interlayer film 40.

[0565] The thickness of the main electrode 52 may be 0.1 μm or more and 5 μm or less. The thickness of the main electrode 52 may have a value that falls within at least one of the following ranges: 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or more and 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0566] The aforementioned outer region 9 may have the configuration shown in Figures 18B to 18C. Figures 18B to 18C are enlarged cross-sectional views showing second and third examples of the outer region 9 shown in Figure 17. Although the configurations of the second and third examples are shown individually in Figures 18B to 18C, the outer region 9 may simultaneously include at least two of the configurations of the first to third examples. Furthermore, the configurations of the first to third examples can be combined as appropriate.

[0567] Referring to Figure 18B (second example), the first outer contact region 26A does not necessarily have to have the first extension 62A. Also, the second outer contact region 26B does not necessarily have to have the second extension 62B. The diode region 60 may be partitioned by either the first outer well region 25A or the second outer well region 25B, or by both.

[0568] In this embodiment, the first outer contact region 26A is formed on the surface of the first outer well region 25A, spaced apart from the outer edge of the first outer well region 25A. The first outer contact region 26A is formed in the region between the central part and the outer edge of the first outer well region 25A. In this embodiment, the first outer contact region 26A is biased towards the outer edge of the first outer well region 25A relative to the central part of the first outer well region 25A.

[0569] In this embodiment, the second outer contact region 26B is formed on the surface of the second outer contact region 26B, spaced apart from the inner edge of the second outer well region 25B. The second outer contact region 26B is formed in the region between the central part of the second outer well region 25B and the inner edge of the second outer well region 25B. In this embodiment, the second outer contact region 26B is biased towards the inner edge of the second outer well region 25B relative to the central part of the second outer well region 25B.

[0570] In this configuration, the outer opening 46 exposes the diode region 60, the outer edge of the first outer well region 25A, the inner edge of the second outer well region 25B, the outer edge of the first outer contact region 26A, and the inner edge of the second outer contact region 26B.

[0571] The outer recess 61, like the outer opening 46, exposes the diode region 60, the outer edge of the first outer well region 25A, the inner edge of the second outer well region 25B, the outer edge of the first outer contact region 26A, and the inner edge of the second outer contact region 26B.

[0572] The source finger electrode 53 has a laminated structure including a base electrode 51 and a main electrode 52, which are stacked in this order from the first main surface 3 side, as in the first embodiment. The base electrode 51 has a laminated structure including a first electrode 51a and a second electrode 51b.

[0573] The first electrode 51a is mechanically and electrically connected to the diode region 60, the outer edge of the first outer well region 25A, the inner edge of the second outer well region 25B, the outer edge of the first outer contact region 26A, and the inner edge of the second outer contact region 26B in the first main surface 3 (outer recess 61).

[0574] The second electrode 51b is electrically connected to the diode region 60, the outer edge of the first outer well region 25A, the inner edge of the second outer well region 25B, the outer edge of the first outer contact region 26A, and the inner edge of the second outer contact region 26B via the first electrode 51a on the first main surface 3 (outer recess 61).

[0575] The main electrode 52 is electrically connected to the diode region 60, the outer edge of the first outer well region 25A, the inner edge of the second outer well region 25B, the outer edge of the first outer contact region 26A, and the inner edge of the second outer contact region 26B via the base electrode 51 on the first main surface 3 (outer recess 61).

[0576] Referring to Figure 18C (third example), the outer opening 46 does not necessarily have to overlap the outer edge of the first outer well region 25A and the inner edge of the second outer well region 25B in the thickness direction Z. In this embodiment, the outer opening 46 has a width less than the width of the diode region 60. The width of the diode region 60 is the horizontal distance between the first outer well region 25A and the second outer well region 25B.

[0577] In other words, the outer opening 46 exposes the diode region 60, the first extension 62A, and the second extension 62B at a distance from the first outer well region 25A and the second outer well region 25B. If the first extension 62A and the second extension 62B are not formed, the outer opening 46 may expose only the diode region 60.

[0578] The outer recess 61 does not necessarily have to overlap the outer edge of the first outer well region 25A and the inner edge of the second outer well region 25B in the thickness direction Z. In this embodiment, the outer recess 61 has a width less than the width of the diode region 60.

[0579] The outer recess 61 is spaced apart from the first outer well region 25A and the second outer well region 25B, exposing the diode region 60, the first extension 62A, and the second extension 62B. If the first extension 62A and the second extension 62B are not formed, the outer recess 61 may expose only the diode region 60.

[0580] The source finger electrode 53 has a laminated structure including a base electrode 51 and a main electrode 52, which are stacked in this order from the first main surface 3 side, as in the first embodiment. The base electrode 51 has a laminated structure including a first electrode 51a and a second electrode 51b.

[0581] The first electrode 51a is mechanically and electrically connected to the diode region 60, the first outer contact region 26A, and the second outer contact region 26B in the first main surface 3 (outer recess 61). In other words, the first electrode 51a is electrically connected to the first outer well region 25A and the second outer well region 25B via the first outer contact region 26A and the second outer contact region 26B.

[0582] The second electrode 51b is electrically connected to the diode region 60, the first outer contact region 26A, and the second outer contact region 26B via the first electrode 51a on the first main surface 3 (outer recess 61). The main electrode 52 is electrically connected to the diode region 60, the first outer contact region 26A, and the second outer contact region 26B via the base electrode 51 on the first main surface 3 (outer recess 61).

[0583] As described above, the semiconductor device 1C may include an n-type second semiconductor layer 7, a p-type body region 10 (impurity region), an n-type diode region 60, and a planar electrode type source finger electrode 53 (electrode). The body region 10 may be formed in the inner part of the second semiconductor layer 7 and may form a bipolar diode DB with the second semiconductor layer 7.

[0584] The diode region 60 may be formed on the periphery of the second semiconductor layer 7. The source finger electrode 53 may be placed on the periphery of the second semiconductor layer 7 and form a unipolar diode DU with the diode region 60.

[0585] This configuration provides a novel semiconductor device 1C. For example, in this semiconductor device 1C, the freewheel current during freewheel operation is handled by a single-pole diode DU, while the surge current Is is handled by both a bipolar diode DB and a single-pole diode DU. Such a configuration is effective in reducing energy loss and suppressing bipolar degradation.

[0586] The second semiconductor layer 7 may contain SiC. This configuration provides a semiconductor device 1A as a SiC semiconductor device with a novel layout. With this semiconductor device 1A, the electrical characteristics are appropriately improved by the physical properties of SiC. In particular, since SiC semiconductor devices are used in relatively high voltage environments, the effect of reducing energy loss and the effect of suppressing bipolar degradation are effective in improving electrical characteristics.

[0587] The semiconductor device 1C may include a p-type outer well region 25 that demarcates the diode region 60 at the periphery of the second semiconductor layer 7. In this case, the outer well region 25 may form a bipolar diode DB with the second semiconductor layer 7. With this configuration, the surge current Is can be handled by both the bipolar diode DB and the unipolar diode DU. Furthermore, with this configuration, the electric field strength (electric field concentration) in the outer region 9 is mitigated by a depletion layer that extends from the outer well region 25.

[0588] The source finger electrode 53 may be electrically connected to the outer well region 25. This configuration allows the bipolar diode DB and the unipolar diode DU to be properly electrically connected in the outer region 9.

[0589] The semiconductor device 1C may include a p-type outer contact region 26. The outer contact region 26 is formed on the surface of the outer well region 25 and may have a higher impurity concentration than the outer well region 25. With this configuration, the electrical response characteristics of the outer well region 25 are improved by the outer contact region 26. In this case, the source finger electrode 53 may be electrically connected to the outer contact region 26.

[0590] The outer contact region 26 may have an extension that is drawn out from the outer well region 25 toward the diode region 60. In this case, the source finger electrode 53 may be electrically connected to the diode region 60 and the extension of the outer contact region 26. With this configuration, the extension of the outer contact region 26 becomes a guard region for the periphery of the unipolar diode DU. As a result, electric field concentration at the periphery of the diode region 60 is suppressed by the extension of the outer contact region 26.

[0591] The semiconductor device 1C may include at least one p-type field region 27 formed in the outer region 9 at a distance from the diode region 60 toward the periphery of the second semiconductor layer 7. With this configuration, the electric field strength (electric field concentration) in the outer region 9 is mitigated by the depletion layer that extends from the field region 27. In this case, the source finger electrode 53 may be formed at a distance from the field region 27 toward the inward side of the first main surface 3.

[0592] The semiconductor device 1C may include an interlayer film 40 covering the second semiconductor layer 7. In this case, the source finger electrode 53 may penetrate the interlayer film 40 and be electrically connected to the diode region 60.

[0593] The semiconductor device 1C may include a source electrode 50 (main electrode). The source electrode 50 may penetrate the interlayer film 40 on the inner side of the second semiconductor layer 7 and be electrically connected to the body region 10. In this case, the source finger electrode 53 may be led out from the source electrode 50. With this configuration, the body region 10 and the diode region 60 are fixed at the same potential, and the bipolar diode DB and the unipolar diode DU are appropriately connected in parallel.

[0594] The semiconductor device 1C may include a trench electrode type gate structure 15. The gate structure 15 may penetrate the body region 10 in the inner part of the second semiconductor layer 7. The diode region 60 may have a width greater than or equal to the width of the gate structure 15. The diode region 60 may have a depth greater than or equal to the depth of the gate structure 15.

[0595] The semiconductor device 1C may include a p-type well region 22 formed in the region below the gate structure 15 within the second semiconductor layer 7. With this configuration, the breakdown voltage is improved by the depletion layer that extends from the well region 22.

[0596] Figure 19 is a plan view showing an example of the layout of the first main surface 3 of the semiconductor device 1D according to the fourth embodiment. Figure 20 is an enlarged cross-sectional view showing the outer region 9 shown in Figure 19. Referring to Figures 19 and 20, the semiconductor device 1D in this embodiment includes a plurality (two in this embodiment) of diode regions 60 formed at intervals in the second semiconductor layer 7 in the outer region 9.

[0597] The number of diode regions 60 is arbitrary and may be between 2 and 20. The number of diode regions 60 may be a value that falls within at least one of the following ranges: 2 to 4, 4 to 6, 6 to 8, 8 to 10, 10 to 12, 12 to 14, 14 to 16, 16 to 18, and 18 to 20.

[0598] The multiple diode regions 60 extend in a strip shape along the active region 8 in a plan view. In this embodiment, the multiple diode regions 60 are formed in a polygonal ring shape (a quadrilateral ring shape in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view, and surround the active region 8 (multiple gate structures 15). The multiple diode regions 60 may have edge portions that connect the portion extending in a strip shape in the first direction X and the portion extending in a strip shape in the second direction Y in an arc shape (preferably a quarter-circular arc shape).

[0599] In this embodiment, the outer well region 25 is formed on both sides of the plurality of diode regions 60. Specifically, the outer well region 25 includes an inner first outer well region 25A, an outer second outer well region 25B, and one or more (one in this embodiment) intermediate third outer well region 25C. The outer well region 25 may include only either the first outer well region 25A or the second outer well region 25B.

[0600] The first outer well region 25A is formed in the region on the inner side (active region 8 side) of the first main surface 3 relative to the inner diode region 60, and demarcates the inner diode region 60 from the inner side of the first main surface 3. The first outer well region 25A is formed in the surface layer of the second semiconductor layer 7, and replaces the conductivity type of the second semiconductor layer 7 from n type to p type.

[0601] The first outer well region 25A extends in layers along the first main surface 3. In a plan view, the first outer well region 25A extends in a band shape along the active region 8 (the inner diode region 60). In this configuration, the first outer well region 25A is formed as a polygonal ring (a quadrilateral ring in this configuration) with four sides parallel to the periphery of the first main surface 3 in a plan view, and surrounds the active region 8 (multiple gate structures 15).

[0602] The first outer well region 25A may have an edge portion that connects a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y in an arc shape (preferably a quarter arc shape). The first outer well region 25A has an inner edge portion on the inner side of the first main surface 3 and an outer edge portion on the peripheral side of the first main surface 3.

[0603] The inner edge defines the boundary between the active region 8 and the outer region 9. The inner edge may be connected to either or both of the body region 10 and the well region 22. The inner edge may be connected to a plurality of gate structures 15. The outer edge extends substantially parallel to the inner edge and defines the inner diode region 60.

[0604] The first outer well region 25A is formed with a gap from the bottom of the second semiconductor layer 7 toward the first main surface 3 and faces the first semiconductor layer 6 through a part of the second semiconductor layer 7. The first outer well region 25A may be formed with a gap from the depth position of the middle part of the second semiconductor layer 7 toward the first main surface 3, or it may have a portion located toward the bottom of the second semiconductor layer 7 relative to the depth position of the middle part of the second semiconductor layer 7.

[0605] In this embodiment, the first outer well region 25A has a depth greater than the depth of the multiple gate structures 15. The depth of the first outer well region 25A may be less than the depth of the multiple gate structures 15.

[0606] The depth of the first outer well region 25A may be approximately equal to the depth of the body region 10. The depth of the first outer well region 25A may be greater than or less than the depth of the body region 10. The depth of the first outer well region 25A may be approximately equal to the depth of the well region 22. The depth of the first outer well region 25A may be greater than or less than the depth of the well region 22.

[0607] The first outer well region 25A forms a pn junction with the second semiconductor layer 7 and the inner diode region 60. This forms a bipolar diode DB including the second semiconductor layer 7 as the cathode region and the first outer well region 25A as the anode region.

[0608] When a reverse bias voltage is applied, the depletion layer that extends from the first outer well region 25A extends the depletion layer that extends from the body region 10 (active region 8) towards the periphery of the first main surface 3, thereby mitigating the electric field strength (electric field concentration) in the outer region 9.

[0609] The second outer well region 25B is formed in the peripheral region of the first main surface 3 relative to the outer diode region 60, and demarcates the outer diode region 60 from the peripheral side of the first main surface 3. The second outer well region 25B is formed in the surface layer of the second semiconductor layer 7, and replaces the conductivity type of the second semiconductor layer 7 from n-type to p-type.

[0610] The second outer well region 25B extends in layers along the first main surface 3. In a plan view, the second outer well region 25B extends in a strip-like manner along the active region 8 (outer diode region 60).

[0611] In this embodiment, the second outer well region 25B is formed as a polygonal ring (a quadrilateral ring in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view, and surrounds the active region 8 (a plurality of gate structures 15). The second outer well region 25B may have an edge portion that connects a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y in an arc shape (preferably a quarter-circular arc shape).

[0612] The second outer well region 25B has an inner edge on the inner side of the first main surface 3 and an outer edge on the peripheral side of the first main surface 3. The inner edge extends along the outer diode region 60 and defines the outer diode region 60. The outer edge extends substantially parallel to the inner edge.

[0613] The second outer well region 25B is formed with a gap from the bottom of the second semiconductor layer 7 toward the first main surface 3 and faces the first semiconductor layer 6 through a part of the second semiconductor layer 7. The second outer well region 25B may be formed with a gap from the depth position of the middle part of the second semiconductor layer 7 toward the first main surface 3, or it may have a portion located toward the bottom of the second semiconductor layer 7 relative to the depth position of the middle part of the second semiconductor layer 7.

[0614] The second outer well region 25B has a depth approximately equal to the depth of the first outer well region 25A. The depth of the second outer well region 25B may be greater or less than the depth of the first outer well region 25A. The second outer well region 25B has a depth greater than the depth of the multiple gate structures 15. The depth of the second outer well region 25B may be less than the depth of the multiple gate structures 15.

[0615] The depth of the second outer well region 25B may be approximately equal to the depth of the body region 10. The depth of the second outer well region 25B may be greater than or less than the depth of the body region 10. The depth of the second outer well region 25B may be approximately equal to the depth of the well region 22. The depth of the second outer well region 25B may be greater than or less than the depth of the well region 22.

[0616] The second outer well region 25B forms a pn junction with the second semiconductor layer 7 and the outer diode region 60. This forms a bipolar diode DB including the second semiconductor layer 7 as the cathode region and the second outer well region 25B as the anode region. When a reverse bias voltage is applied, the depletion layer spreading from the second outer well region 25B extends the depletion layer spreading from the first outer well region 25A side to the peripheral edge of the first main surface 3, thereby mitigating the electric field strength (electric field concentration) of the outer region 9.

[0617] The third outer well region 25C is an outer well region 25 that demarcates one or more diode regions 60 in the region between the inner diode region 60 and the outer diode region 60.

[0618] The third outer well region 25C is formed in the region between the inner diode region 60 and the outer diode region 60, and demarcates the inner diode region 60 and the outer diode region 60. The third outer well region 25C faces the first outer well region 25A across the inner diode region 60 and faces the second outer well region 25B across the outer diode region 60.

[0619] The third outer well region 25C is formed on the surface of the second semiconductor layer 7 and replaces the conductivity type of the second semiconductor layer 7 from n-type to p-type. The third outer well region 25C extends in layers along the first main surface 3. In a plan view, the third outer well region 25C extends in a strip-like shape along the active region 8 (multiple diode regions 60).

[0620] In this embodiment, the third outer well region 25C is formed as a polygonal ring (a quadrilateral ring in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view, and surrounds the active region 8 (a plurality of gate structures 15). The third outer well region 25C may have an edge portion that connects a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y in an arc shape (preferably a quarter-circular arc shape).

[0621] The third outer well region 25C has an inner edge on the inner side of the first main surface 3 and an outer edge on the peripheral side of the first main surface 3. The inner edge extends along the inner diode region 60 and defines the inner diode region 60. The outer edge extends along the outer diode region 60 and defines the outer diode region 60.

[0622] The third outer well region 25C is formed with a gap from the bottom of the second semiconductor layer 7 toward the first main surface 3 and faces the first semiconductor layer 6 through a part of the second semiconductor layer 7. The third outer well region 25C may be formed with a gap from the depth position of the middle part of the second semiconductor layer 7 toward the first main surface 3, or it may have a portion located toward the bottom of the second semiconductor layer 7 relative to the depth position of the middle part of the second semiconductor layer 7.

[0623] The third outer well region 25C has a depth approximately equal to the depth of the first outer well region 25A. The depth of the third outer well region 25C may be greater than or less than the depth of the first outer well region 25A. The depth of the third outer well region 25C is approximately equal to the depth of the second outer well region 25B. The depth of the third outer well region 25C may be greater than or less than the depth of the second outer well region 25B.

[0624] The third outer well region 25C has a depth greater than the depth of the multiple gate structures 15. The depth of the third outer well region 25C may be less than the depth of the multiple gate structures 15.

[0625] The depth of the third outer well region 25C may be approximately equal to the depth of the body region 10. The depth of the third outer well region 25C may be greater than or less than the depth of the body region 10. The depth of the third outer well region 25C may be approximately equal to the depth of the well region 22. The depth of the third outer well region 25C may be greater than or less than the depth of the well region 22.

[0626] In this embodiment, the third outer well region 25C has a width smaller than the width of the first outer well region 25A. The width of the third outer well region 25C may be greater than the width and depth of the first outer well region 25A. The width of the third outer well region 25C may be greater than or less than the width of the second outer well region 25B. The width of the third outer well region 25C may be approximately equal to the width of the second outer well region 25B.

[0627] The third outer well region 25C forms a pn junction with the second semiconductor layer 7, the inner diode region 60, and the outer diode region 60. This forms a bipolar diode DB including the second semiconductor layer 7 as the cathode region and the third outer well region 25C as the anode region.

[0628] When a reverse bias voltage is applied, the depletion layer extending from the third outer well region 25C causes the depletion layer extending from the first outer well region 25A to extend towards the periphery of the first main surface 3, thereby mitigating the electric field strength (electric field concentration) in the outer region 9.

[0629] The depletion layer extending from the third outer well region 25C may be integrated with the depletion layer extending from the first outer well region 25A in the inner diode region 60. The depletion layer extending from the third outer well region 25C may be integrated with the depletion layer extending from the second outer well region 25B in the outer diode region 60.

[0630] In this embodiment, the outer contact region 26 is formed on both sides of the plurality of diode regions 60. Specifically, the outer contact region 26 includes an inner first outer contact region 26A, an outer second outer contact region 26B, and one or more (one in this embodiment) intermediate third outer contact region 26C.

[0631] The outer contact region 26 may be composed of one or two of the first outer contact region 26A, the second outer contact region 26B, and the third outer contact region 26C.

[0632] The first outer contact region 26A is formed on the surface of the first outer well region 25A and extends in layers along the first main surface 3. In a plan view, the first outer contact region 26A extends in a strip shape along the active region 8 (the inner diode region 60).

[0633] In this embodiment, the first outer contact region 26A is formed as a polygonal ring (a quadrilateral ring in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view, and surrounds the active region 8 (a plurality of gate structures 15). The first outer contact region 26A may have an edge portion that connects a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y in an arc shape (preferably a quarter-circular arc shape).

[0634] The first outer contact region 26A has a first extension 62A that crosses the outer edge of the first outer well region 25A and extends into the diode region 60. The first extension 62A replaces the conductivity type of a part of the inner diode region 60 from n-type to p-type.

[0635] The first extension 62A is formed with a gap between it and the third outer well region 25C towards the first outer well region 25A, and partitions a part of the inner diode at the surface layer of the first main surface 3. The first outer contact region 26A does not necessarily have to have the first extension 62A, and may be formed in the inner part of the first outer well region 25A.

[0636] The first outer contact region 26A has an inner edge on the inner side of the first main surface 3 and an outer edge on the peripheral side of the first main surface 3. The inner edge defines the boundary between the active region 8 and the outer region 9. The inner edge may be connected to either or both of the body region 10 and the well region 22. The inner edge may be connected to a plurality of gate structures 15. The outer edge extends substantially parallel to the inner edge and defines the inner diode region 60 as the first extension 62A.

[0637] The first outer contact region 26A is formed with a gap from the bottom of the first outer well region 25A toward the first main surface 3, and faces the second semiconductor layer 7 via a part of the first outer well region 25A. The first outer contact region 26A may be formed with a gap from the depth position of the middle part of the first outer well region 25A toward the first main surface 3, or it may have a portion located toward the bottom of the first outer well region 25A relative to the depth position of the middle part of the first outer well region 25A.

[0638] The first outer contact region 26A has a depth smaller than the depth of the multiple gate structures 15. The depth of the first outer contact region 26A may be greater than the depth of the multiple gate structures 15. The depth of the first outer contact region 26A may be greater than or less than the depth of the body region 10.

[0639] The second outer contact region 26B is formed on the surface of the second outer well region 25B and extends in layers along the first main surface 3. In a plan view, the second outer contact region 26B extends in a band shape along the active region 8 (outer diode region 60).

[0640] In this embodiment, the second outer contact region 26B is formed as a polygonal ring (a quadrilateral ring in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view, and surrounds the active region 8 (a plurality of gate structures 15). The second outer contact region 26B may have an edge portion that connects a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y in an arc shape (preferably a quarter-circular arc shape).

[0641] The second outer contact region 26B has a second extension 62B that crosses the inner edge of the second outer well region 25B and extends into the outer diode region 60. The second extension 62B replaces the conductivity type of the outer diode region 60 from n-type to p-type.

[0642] The second extension 62B is formed with a gap between it and the third outer well region 25C, and partitions a portion of the outer diode on the surface of the first main surface 3. The second outer contact region 26B does not necessarily have to have the second extension 62B, and may be formed in the inner part of the second outer well region 25B.

[0643] The second outer contact region 26B has an inner edge portion on the inner side of the first main surface 3 and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion is located within the outer diode region 60 as a second extension portion 62B. The outer edge portion is located within the second outer well region 25B.

[0644] The second outer contact region 26B is formed with a gap from the bottom of the second outer well region 25B toward the first main surface 3, and faces the second semiconductor layer 7 via a part of the second outer well region 25B.

[0645] The second outer contact region 26B may be formed with a gap from the depth position of the middle part of the second outer well region 25B toward the first main surface 3, or it may have a portion located toward the bottom side of the second outer well region 25B relative to the depth position of the middle part of the second outer well region 25B.

[0646] The second outer contact region 26B has a depth approximately equal to the depth of the first outer contact region 26A. The depth of the second outer contact region 26B may be greater or less than the depth of the first outer contact region 26A.

[0647] The depth of the second outer contact region 26B is less than the depth of the multiple gate structures 15. The depth of the second outer contact region 26B may be greater than the depth of the multiple gate structures 15. The depth of the second outer contact region 26B may be greater than or less than the depth of the body region 10.

[0648] The third outer contact region 26C is formed on the surface of the third outer well region 25C and extends in layers along the first main surface 3. In a plan view, the third outer contact region 26C extends in a strip-like manner along the active region 8 (multiple diode regions 60).

[0649] In this embodiment, the third outer contact region 26C is formed as a polygonal ring (a quadrilateral ring in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view, and surrounds the active region 8 (a plurality of gate structures 15). The third outer contact region 26C may have an edge portion that connects a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y in an arc shape (preferably a quarter-circular arc shape).

[0650] The third outer contact region 26C has a third extension 62C that extends into the inner diode region 60 and a fourth extension 62D that extends into the outer diode region 60. The third outer contact region 26C does not necessarily have to have the third extension 62C and the fourth extension 62D, and may be formed in the inner part of the third outer well region 25C.

[0651] The third extension 62C replaces the conductivity type of a portion of the inner diode region 60 from n-type to p-type. The third extension 62C is formed with a gap between the first outer well region 25A and the third outer well region 25C, and partitions a portion of the inner diode at the surface layer of the first main surface 3. The third extension 62C is formed with a gap between it and the first extension 62A, and together with the first extension 62A, partitions a portion of the inner diode.

[0652] The fourth extension 62D replaces the conductivity type of a portion of the outer diode region 60 from n-type to p-type. The fourth extension 62D is formed with a gap between the second outer well region 25B and the third outer well region 25C, and partitions a portion of the outer diode at the surface layer of the first main surface 3. The fourth extension 62D is formed with a gap between it and the second extension 62B, and together with the second extension 62B, partitions a portion of the outer diode.

[0653] The third outer contact region 26C has an inner edge portion on the inner side of the first main surface 3 and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion is located within the inner diode region 60 as a third extension portion 62C. The outer edge portion is located within the outer diode region 60 as a fourth extension portion 62D.

[0654] The third outer contact region 26C is formed with a gap from the bottom of the third outer well region 25C toward the first main surface 3, and faces the second semiconductor layer 7 via a part of the third outer well region 25C. The third outer contact region 26C may be formed with a gap from the depth position of the middle part of the third outer well region 25C toward the first main surface 3, or it may have a portion located toward the bottom of the third outer well region 25C relative to the depth position of the middle part of the third outer well region 25C.

[0655] The third outer contact region 26C has a depth approximately equal to the depth of the first outer contact region 26A. The depth of the third outer contact region 26C may be greater or less than the depth of the first outer contact region 26A. The third outer contact region 26C has a depth approximately equal to the depth of the second outer contact region 26B. The depth of the third outer contact region 26C may be greater or less than the depth of the second outer contact region 26B.

[0656] The depth of the third outer contact region 26C is less than the depth of the multiple gate structures 15. The depth of the third outer contact region 26C may be greater than the depth of the multiple gate structures 15. The depth of the third outer contact region 26C may be greater than or less than the depth of the body region 10.

[0657] The semiconductor device 1D, as in the third embodiment, includes at least one (multiple in this embodiment) p-type field regions 27 formed on the peripheral edge (outer ...

Claims

1. A semiconductor device comprising: a semiconductor layer of a first conductivity type; an impurity region of a second conductivity type formed in the inner part of the semiconductor layer and forming a bipolar diode with the semiconductor layer; and a trench electrode type rectifier structure formed in the peripheral part of the semiconductor layer and forming a unipolar diode with the semiconductor layer.

2. The semiconductor device according to claim 1, wherein the semiconductor layer includes SiC.

3. The semiconductor device according to claim 1 or 2, further comprising a second conductivity type trench well region formed in the region below the rectification structure within the semiconductor layer.

4. The semiconductor device according to any one of claims 1 to 3, further comprising a second conductivity type well region formed on the periphery of the semiconductor layer, wherein the rectifier structure penetrates the well region and has a portion that forms the semiconductor layer and the unipolar diode in a region below the bottom of the well region.

5. The semiconductor device according to claim 4, further comprising a second conductivity type contact region formed on the surface of the well region and having a higher impurity concentration than the well region, wherein the rectification structure penetrates the well region and the contact region.

6. The semiconductor device according to any one of claims 1 to 5, further comprising at least one field region of a second conductivity type formed on the peripheral edge of the semiconductor layer, wherein the rectifier structure is formed at a distance from the field region toward the inward portion of the semiconductor layer.

7. The semiconductor device according to any one of claims 1 to 6, further comprising: an interlayer film covering the semiconductor layer; and an electrode penetrating the interlayer film and electrically connected to the rectifier structure.

8. The semiconductor device according to claim 7, further comprising a main electrode that penetrates the interlayer film and is electrically connected to the impurity region, wherein the electrode is connected to the main electrode.

9. The semiconductor device according to any one of claims 1 to 8, further comprising a trench electrode type gate structure that penetrates the impurity region in the inner portion of the semiconductor layer.

10. The semiconductor device according to claim 9, wherein the rectifier structure has a width greater than or equal to the width of the gate structure.

11. The semiconductor device according to claim 9 or 10, wherein the rectifier structure has a depth greater than or equal to the depth of the gate structure.

12. The semiconductor device according to any one of claims 9 to 11, further comprising a gate well region of a second conductivity type formed in the region below the gate structure within the semiconductor layer.

13. A semiconductor device comprising: a semiconductor layer of a first conductivity type; an impurity region of a second conductivity type formed in the inner part of the semiconductor layer and forming a bipolar diode with the semiconductor layer; a diode region of the first conductivity type formed on the peripheral edge of the semiconductor layer; and a planar electrode disposed on the peripheral edge of the semiconductor layer and forming a unipolar diode with the diode region.

14. The semiconductor device according to claim 13, wherein the semiconductor layer includes SiC.

15. The semiconductor device according to claim 13 or 14, further comprising a second conductivity type well region that demarcates the diode region at the periphery of the semiconductor layer.

16. The semiconductor device according to claim 15, further comprising a second conductivity type contact region formed on the surface of the well region and having a higher impurity concentration than the well region.

17. The semiconductor device according to claim 16, wherein the contact region has an extension drawn out from the well region to the diode region.

18. The semiconductor device according to any one of claims 13 to 17, further comprising at least one field region of a second conductivity type formed at a distance from the diode region toward the periphery of the semiconductor layer, wherein the electrode is formed at a distance from the field region toward the inward side of the semiconductor layer.

19. The semiconductor device according to any one of claims 13 to 18, further comprising an interlayer film covering the semiconductor layer, wherein the electrode is electrically connected to the diode region through the interlayer film.

20. The semiconductor device according to any one of claims 13 to 19, further comprising a gate structure formed in the inner portion of the semiconductor layer.

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