Asymmetric PMOS fets

Abstract

Circuits and methods for integrated circuits particularly useful in high-quality low-noise amplifiers (LNA) that are sensitive, provide good amplification, are physically compact, and can withstand relatively high drain-to-source voltages. LNA embodiments include an N-type MOSFET (NFET) or P-type MOSFET (PFET) device co-fabricated with one or more serially-coupled asymmetric PFET devices of several types. The asymmetry of the novel asymmetric PFET device provides a shorter gate length (LG) and thus a higher transconductance (gm). In addition, the inventive asymmetric PFET device has a higher hole mobility brought about by introducing strain in the conduction channel (especially at or near the source of the device) and / or by use of silicon germanium (SiGe) regions within the asymmetric PFET structure. The resulting asymmetric PFET devices have higher Vtsat and lower built-in voltage Vbi (thus higher IDS) characteristics than conventional symmetric PFET devices.

Description

Attorney Docket No. P3133-PCT Inventors: Jagar Singh et al.Asymmetric PMOS FETSCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] The present application claims priority to U.S. Provisional Patent Application No. 63 / 709,430, filed on October 19, 2024, entitled “Asymmetric PMOS FETS” with docket number PER-536-PROV, the contents of which are incorporated herein by reference in their entirety.BACKGROUND(1) Technical Field

[0002] The invention relates to electronic circuits, and more particularly to amplifier circuits.(2) Background

[0003] Many modem electronic systems include radio frequency (RF) receivers; examples include cellular telephones, personal computers, tablet computers, wireless network components, televisions, cable system “set top” boxes, and radar systems. Many RF receivers are paired with RF transmitters in the form of transceivers, which often are quite complex two- way radios. In some cases, RF transceivers are capable of transmitting and receiving across multiple frequencies in multiple bands.

[0004] Amplifiers are a common component in RF transmitters, receivers, and transceivers, and are frequently used for power amplification of transmitted RF signals and for low-noise amplification of received RF signals. For many RF systems, particularly those requiring low power and / or portability (e.g., cellular telephones, WiFi-connected computers, cameras, and other devices), it has become common to use metal-oxide semiconductor fieldeffect transistors (MOSFETs) to create low-cost, low-power integrated circuits (ICs). MOSFET devices include bulk MOSFETs, silicon-on-insulator (SOI) MOSFETs, and silicon- on-sapphire (SOS) MOSFETs (SOS being a type of SOI fabrication technology).

[0005] In many environments, receiving an RF signal requires a high-quality low-noise amplifier (LNA) as part of an RF “front end” (RFFE) receiver or transceiver chain of circuits. It is desirable that an LNA be sensitive, provide suitable amplification, be physically compact,Attorney Docket No. P3133-PCT Inventors: Jagar Singh et al. and in many applications be able to withstand relatively high drain-to-source voltages. The present invention is directed to novel embodiments of LNAs that meet these and other criteria.Attorney Docket No. P3133-PCT Inventors: Jagar Singh et al.SUMMARY

[0006] The present invention encompasses circuits and methods for integrated circuits particularly useful in high-quality low-noise amplifiers (LNA) that are sensitive, provide good amplification, are physically compact, and can withstand relatively high drain-to-source voltages. LNA embodiments include an N-type MOSFET (NFET) or P-type MOSFET (PFET) device co-fabricated with one or more serially-coupled asymmetric PFET devices of several types.

[0007] The present invention improves the performance of conventional symmetric PFET devices by designing an asymmetric PFET device. The asymmetry of the novel asymmetric PFET device provides a shorter gate length (LG) and thus a higher transconductance (gm). In addition, the inventive asymmetric PFET device has a higher hole mobility brought about by introducing strain in the conduction channel (especially at or near the source of the device) and / or by use of silicon germanium (SiGe) regions within the asymmetric PFET structure. The resulting asymmetric PFET devices have higher Vtsat (VTH measured at saturation) and lower built-in voltage Vbi (thus higher IDS) characteristics than conventional symmetric PFET devices.

[0008] Embodiments include an asymmetric PFET device having a source, a body laterally adjacent the source, a drift region laterally adjacent the body, a drain laterally adjacent the drift region, at least one of a lightly-doped drain region or a doped halo region between the source and the body, and a gate structure positioned with respect to the body so as to be able to influence current flow through the body between the source and the drain. Embodiments of the asymmetric PFET device may include a stepped gate oxide layer. Embodiments of the asymmetric PFET device may have at least a source region fabricated at least in part with a silicon germanium alloy.

[0009] A significant benefit of the IC structures described above, and variations of such structures, is the space savings in IC layouts resulting from the use of shared regions between adjacent devices, particularly when concatenating multiple FET devices and sharing drain / source or drain / drain regions.

[0010] The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention should be apparent from the description and drawings, and from the claims.Attorney Docket No. P3133-PCT Inventors: Jagar Singh et al.DESCRIPTION OF THE DRAWINGS

[0011] FIG. 1 is a simplified schematic diagram of an example LNA circuit.

[0012] FIG. 2A is a stylized cross-sectional view of an SOI IC structure for an asymmetric PFET device that may be used as the common-gate asymmetric PFET MCG of FIG. 1.

[0013] FIG. 2B is a stylized cross-sectional view of a gate structure that includes a stepped GOX layer.

[0014] FIG. 3 is a stylized cross-sectional view of an SOI IC structure that implements a first version of the amplifier core shown in FIG. 1.

[0015] FIG. 4 is a stylized cross-sectional view of an SOI IC structure that implements a second version of the amplifier core shown in FIG. 1.

[0016] FIGS. 5A-5H are stylized cross-sectional views of various SOI IC structures for an asymmetric PFET device having source regions that include SiGe.

[0017] FIGS. 6A-6H are cross-sectional stylized views of example fabrication stages for the novel asymmetric PFET devices of FIGS. 2-4, where the active layer (by way of example only) is Si having a <110> orientation.

[0018] FIGS. 7A-7B are cross-sectional stylized views of a first set of alternative fabrication stages for an asymmetric PFET device that includes an SiGe source region.

[0019] FIGS. 8A-8B are cross-sectional stylized views of a second set of alternative fabrication stages for an asymmetric PFET device that includes an SiGe source region.

[0020] FIGS. 9A-9C are cross-sectional stylized views of a third set of alternative fabrication stages for an asymmetric PFET device that includes an SiGe source region.

[0021] FIG. 10 is a process flowchart showing one fabrication process for an asymmetric PFET device that is suitable for some contemporary IC front-end-of-line (FEOL) foundries.

[0022] FIG. 11 is a cross-sectional stylized view of a novel asymmetric PFET device that includes both a SiGe drain and a stress liner.Attorney Docket No. P3133-PCT Inventors: Jagar Singh et al.

[0023] FIG. 12 is a top plan view of a first configuration of BTS structures for multiple asymmetric PFETs devices co-fabricated with an NFET device

[0024] FIG. 13 is a top plan view of a second configuration of BTS structures for multiple asymmetric PFETs devices co-fabricated with an NFET device

[0025] FIG. 14 is a top plan view of a substrate that may be, for example, a printed circuit board or chip module substrate (e.g.. a thin- film tile).

[0026] FIG. 15 illustrates a prior art wireless communication environment comprising different wireless communication systems, and which may include one or more mobile wireless devices.

[0027] FIG. 16 is a block diagram of a transceiver that might be used in a wireless device, such as a cellular telephone, and which may beneficially incorporate an embodiment of the present invention for improved performance.

[0028] Like reference numbers and designations in the various drawings indicate like elements unless the context requires otherwise.Attorney Docket No. P3133-PCT Inventors: Jagar Singh et al.DETAILED DESCRIPTION

[0029] The present invention encompasses circuits and methods for integrated circuits particularly useful in high-quality low-noise amplifiers (LNA) that are sensitive, provide good amplification, are physically compact, and can withstand relatively high drain-to-source voltages. LNA embodiments include an N-type MOSFET (NFET) or P-type MOSFET (PFET) device co-fabricated with one or more serially-coupled asymmetric PFET devices of several types.

[0030] A conventional symmetric PFET has poor current capability due to the lower mobility of holes - the charge carrier in PFET devices - compared to electrons, the charge carrier in NFETs. A conventional symmetric PFET device also has a lower unity current gain frequency t than a conventional symmetric NFET device, and thus has a lower operating frequency limit.

[0031] The present invention improves the performance of conventional symmetric PFET devices by designing an asymmetric PFET device. The novel asymmetric PFET device has a shorter gate length (LG) and thus a higher transconductance (gm). In addition, the inventive asymmetric PFET device has a higher hole mobility brought about by introducing strain in the conduction channel (especially at or near the source of the device) and / or by use of silicon germanium (SiGe) regions within the asymmetric PFET structure. The resulting asymmetric PFET devices have higher Vtsat (VT measured at saturation) and lower built-in voltage Vbi (thus higher IDS) characteristics than conventional symmetric PFET devices.

[0032] FIG. 1 is a simplified schematic diagram of an example LNA circuit 100. In the illustrated example, the LNA circuit 100 includes an amplifier core 102 comprising a stack of two series-connected FETs: a common-source FET Mcs and a common-gate asymmetric PFET MCG coupled in a cascode arrangement. The common-source FET Mcs may be a symmetric N- type FET (NFET), an asymmetric NFET, a symmetric PFET, or an asymmetric PFET. In some embodiments, the common-source FET Mcs may be an extended-drain FET device to better withstand high drain-source voltages.

[0033] An optional asymmetric PFET device stack 104 may be coupled to the source of the common-gate asymmetric PFET MCG to handle higher voltages. In the illustrated example, an RF input signal applied to an RF input terminal RFJN is coupled through an impedance matching inductor LIN and a DC blocking capacitor CIN to the control gate of the common-Attorney Docket No. P3133-PCT Inventors: Jagar Singh et al. source FET Mcs (which may be regarded as an input port INT of the amplification core 102) and to the control gate of the common-gate asymmetric PFET MCG and any device within the optional asymmetric PFET device stack 104.

[0034] A first terminal of the conduction channel (drain to source) of the common-source FET Mcs may be regarded as a degeneration port DT of the amplification core 102. A degeneration inductor LDG is coupled between the degeneration port DT of the amplification core 102 and a reference potential, such as circuit ground.

[0035] The drain of the common-gate asymmetric PFET MCG is connected to a second terminal of the conduction channel of the common- source FET Mcs- A node between the common-gate asymmetric PFET MCG and the common-source FET Mcs provides an amplified RF output signal at what may be regarded as an amplified- signal port AST of the amplification core 102. A bias generator circuit (not shown) may be included to provide a suitable bias voltage VBIAS through an inductor L. In some embodiments, the inductor L may be replaced by a resistor or more complex circuitry.

[0036] In the illustrated example, the amplification core 102 is coupled to a voltage source terminal VDD through a load module 106. In the illustrated example, the load module 106 includes a load inductor LLD coupled in parallel with a de-queuing resistor RDQ. The amplification core 102 is also coupled to a terminal VCAS through a DC -blocking output capacitor COUT-

[0037] In preferred embodiments of the LNA 100, the common-source FET Mcs would be fabricated as a thin-gate oxide device to provide high performance, while the common-gate asymmetric PFET device MCG and the devices in the optional asymmetric PFET device stack 104 may be fabricated as thick-gate oxide devices to withstand higher drain-source voltages.

[0038] The LNA circuit 100 of FIG. 1 is a basic LNA architecture. As will be appreciated by one of ordinary skill in the art, a number of variant LNAs may benefit from the use of the present invention. For example, additional control and configuration switches may be included, and the LNA circuit 100 may include more than one amplifier core 102. Additional circuitry may include (1 ) an output cl mp coupled between the output terminal RFOUT and the reference potential to clamp transient signals, (2) a filter capacitor coupled between the voltage source terminal VDD and the reference potential to filter noise that may be present at that node, and (3) a clamp diode coupled between the voltage source terminal VDD and the amplified-signal portAttorney Docket No. P3133-PCT Inventors: Jagar Singh et al.AST to reduce the voltage swing at the LNA output, which will benefits parameter specifications (e.g., output saturation power) that are required in many applications. In some variants, the bias voltage VBIAS may be variable, the degeneration inductor LDG may be variable and / or bypassable, the load module 106 may include additional and / or more complex (e.g. , variable and / or bypassable) LRC components, and feedback circuitry may be coupled between the amplified-signal port AST and the input port INT. Configuration switches may be used to selectively connect or disconnect various circuit elements, for example, to accommodate different gain modes of operation.

[0039] FIG. 2A is a stylized cross-sectional view of an SOI IC structure 200 for an asymmetric PFET device that may be used as the common-gate asymmetric PFET MCG of FIG. 1. The SOI IC structure 200 includes a substrate 202, a buried-oxide (BOX) insulator layer 204, and an active layer 206 (note that the dimensions for the elements of the SOI IC structure 200 are not to scale; some dimensions have been exaggerated for clarity or emphasis). The substrate 202 is typically a semiconductor material such as silicon, but other materials may be used. The BOX layer 204 is a dielectric, and is often SiO2 formed as a “top” surface of the silicon substrate 202. For some insulating substrates e.g., glass or sapphire), the BOX layer 204 may be omitted, since such a substrate provides the function of the BOX layer without a silicon handle wafer. Some embodiments may include a trap-rich layer (not shown) between the BOX layer 204 and the substrate 202. A trap-rich layer mitigates parasitic surface conduction and improves device performance at high frequencies.

[0040] The BOX layer 204 and the active layer 206 (which may include multiple FET devices) may be collectively referred to as a “device region” or “substructure” for convenience (noting that other structures or regions may intrude into the substructure in particular IC designs). The active layer 206 may include some combination of implants and / or layers that include dopants, dielectrics, polysilicon, conductors, passivation, and other materials to form active and / or passive electronic components and / or mechanical structures. A superstructure (not shown) of various elements, regions, and structures may be fabricated on or above the substructure in order to implement particular functionality. The superstructure may include, for example, conductive interconnections from one or more FET devices to other components (including other FET devices) and / or external contacts, passivation layers, and protective coatings.Attorney Docket No. P3133-PCT Inventors: Jagar Singh et al.

[0041] The asymmetric PFET device shown in FIG. 2A includes bounding shallow trench isolation (STI) structures 208, a P+ source 210, an N-type body 212 (also known as an “N- well”), a gate structure 214, and a P+ drain 216. A P- drift region 218 may be interposed between the body 212 and the drain 216 to provide an improved ability to withstand relative high drain-to-source voltages. The designation “P- means a lesser concentration of P-type dopant (e.g., boron) than the designation “P+”.

[0042] The gate structure 214 is positioned with respect to the N-type body 212 so as to be able to influence current flow through the body. In the illustrated example, the gate structure 214 includes a conductive layer 220, such as P+ doped polysilicon, atop an insulating gate oxide (GOX) layer 222. In the illustrated example, the gate structure 214 is surrounded by insulating spacers 224, which may be formed in multiple layers (two layers, separated by a dotted line, are shown for each illustrated insulating spacer 224). Parts of the gate structure 214 and the drain 216 may be coated with a dielectric, such as SiCh, SisN4, etc., which in turn may be overlaid with a salicide block (SAB) layer, such as SiN - see FIG. 6H for an example.

[0043] A conductive source contact 226, a conductive gate contact 228, and a conductive drain contact 230, which may be self-aligned silicides (also known as “salicides”), are respectively formed in electrical and physical contact with the source 210, the gate conductive layer 220, and the drain 216. The salicides may be, for example, NiSi. Stylized electrical terminals S, G, and D are shown coupled to the corresponding source contact 226, the gate contact 228, and the drain contact 230.

[0044] The illustrated asymmetric PFET device includes a lightly-doped drain (LDD) region 232 and a doped halo region 234 formed between portions of the source 210 and the body 212, and may extend underneath the gate structure 214. The doped halo region 234 mitigates punch-through while the LDD region 232 mitigates avalanche breakdown. More specifically, the doped halo region 234 increases a sub-surface electric field to reduce so-called punch-through, or short channel, conduction between the source 210 and the drain 216, thus increasing the channel breakdown voltage of the device. The LDD region 232 extends the source 210 underneath the gate structure 214 and modulates the threshold voltage VTH, transconductance gm, and leakage current of the device.Attorney Docket No. P3133-PCT Inventors: Jagar Singh et al.

[0045] Notably, the asymmetric PFET device of FIG. 2A does not include a drain-side LDD region or doped halo region, unlike a symmetric PFET device - hence the characterization of the PFET device of FIG. 2A as “asymmetric”.

[0046] Another characteristic of the asymmetric PFET device of FIG. 2A is that the source 210 preferably is fabricated at least in part with a silicon germanium alloy (e.g., as a heterogeneous or homogenous SiGe alloy, including Ge-doped Si as well as graded Ge and Si mixtures) so as to introduce strain below the gate structure 214 and within the channel region in the N-type body 212. The increased channel region strain increases hole mobility and the saturation velocity Vsat, particularly for asymmetric PFET devices having a strained channel region with a gate length LG of about 45nm or less. Such strained channel asymmetric PFET devices can achieve a hole mobility that approximately equals - and in many embodiments exceeds - the electron mobility of NFET devices. As noted above, the resulting asymmetric PFET devices have higher Vtsat and lower built-in voltage Vbi (thus higher IDS) characteristics than conventional symmetric PFET devices.

[0047] Yet another characteristic of the asymmetric PFET device of FIG. 2 A is that the drain 216 is preferably Si, which provides a higher bandgap than SiGe and thus a higher junction breakdown characteristic.

[0048] In some embodiments, an asymmetric PFET device may use a stepped configuration for the GOX layer 222. A stepped GOX layer includes a thin (in the Z dimension) subregion adjacent to the source-side of the gate structure and a thick subregion adjacent to the drain-side of the gate structure. The thin and thick subregions of a stepped GOX layer will exhibit different threshold voltage VTH characteristics. The thin GOX subregion creates a higher potential barrier when negative gate voltages are applied compared to an asymmetric PFET device having only a thick GOX, resulting in a substantial improvement (~25% in some embodiments) in the drain-to-source breakdown voltage VBD of the device. For example, FIG. 2B is a stylized cross-sectional view of a gate structure 215 that includes a stepped GOX layer 223. The thicker subregion at the drain-side of the GOX layer 223 reduces the electric-field at the interface of the gate and the drain region and improves both GIDL (gate-induced drain leakage) and TDDB (Time-Dependent Dielectric Breakdown) compared to an asymmetric PFET having only a thin GOX layer. Note that the “thin” region of a stepped GOX layer for a common-gate asymmetric PFET device may still be thicker than the GOX layer of an NFET or PFET used for a common-source FET device.Attorney Docket No. P3133-PCT Inventors: Jagar Singh et al.

[0049] A stepped insulating GOX layer 223 may be fabricated using additive or subtractive process steps. For example, an additive process may include forming a thin layer of GOX over the active layer 206, then masking the GOX to expose stripes over which additional oxide may be grown to form the thick regions, then removing the masking material (e.g., a photolithographic polymer). As another example, a subtractive process may include forming a thick layer of GOX over the active layer 206, then masking the GOX to protect stripes of thick GOX material, then etching the unprotected GOX to a desired thinness, then removing the masking material.

[0050] An important aspect of the present invention is the implementation of the LNA 100 of FIG. 1 and variations of that circuit in compact and efficient integrated circuits (ICs) capable of withstanding relatively high drain-source voltages. FIG. 3 is a stylized cross-sectional view of an SOI IC structure 300 that implements a first version of the amplifier core 102 shown in FIG. 1. The illustrated IC structure 300 essentially combines the asymmetric PFET device of FIG. 2A (with the same reference numbers) with a symmetric NFET device. The bounding STI structures 208 shown in FIG. 2A are omitted to avoid clutter, but would essentially bound both devices but would not be interposed between shared regions of the devices.

[0051] Referring to FIG. 3, the NFET device includes an N+ source 310, a P-type body 312 (also known as a “P-well”), a gate structure 314, and an N+ drain 316. The illustrated gate structure 314 includes a conductive layer 320, such as N+ doped polysilicon, atop an insulating GOX layer 322. In the illustrated example, the gate structure 314 is surrounded by insulating spacers 324, which may be formed in multiple layers (two layers, separated by a dotted line, are shown for each illustrated insulating spacer 324). Parts of the gate structure 314 and the drain 316 may be coated with a dielectric, such as SiO2, Sij r, etc., which in turn may be overlaid with a SAB layer, such as SisN4 - see FIG. 6H for an example.

[0052] A conductive source contact 326, a conductive gate contact 328, and a conductive drain contact 330, which may be salicides, are respectively formed in electrical and physical contact with the source 310, the gate conductive layer 320, and the drain 316. Stylized electrical terminals S, G, and D are shown coupled to the corresponding source contact 326, the gate contact 328, and the drain contact 330. The drain 316 of the NFET device and the drain 216 of the asymmetric PFET device abut and are capped by a shared conductive drain contact 330, 230, thus allowing a common drain / drain (D / D) terminal.Attorney Docket No. P3133-PCT Inventors: Jagar Singh et al.

[0053] The illustrated symmetric NFET device includes a lightly-doped drain (LDD) region 332 and a doped halo region 334 formed underneath the gate structure 314 (1) between portions of the source 310 and the body 312, and (2) between portions of the drain 316 and the body 312. Again, the doped halo regions 334 mitigate punch-through while the LDD regions 332 mitigate avalanche breakdown. Some embodiments may omit one or the other of the LDD regions 332 or the doped halo regions 334.

[0054] In the illustrated example, the source 310 and drain 316 of the common-source NFET device are both Si, but may include other materials, including SiGe. The common-source NFET device is preferably fabricated as a thin-gate oxide device to provide high performance, while the asymmetric PFET device, functioning as the common-gate FET MCG, is preferably fabricated as a thick-gate oxide device to withstand higher voltages. In general, gate oxide thickness is a function of gate length, so “thin” and “thick” with respect to the gate oxide will depend on the gate length of a particular FET design.

[0055] The example embodiment of FIG. 3 shows that the GOX layer 222 in the gate structure 214 of the asymmetric PFET device is thicker (e.g. about 70 ) than the GOX layer 322 in the gate structure 314 of the NFET device. As should be clear, other dimensions for the thick GOX layer 222 and the thin GOX layer 322 may be used in particular applications. The thicker GOX layer 222 in the gate structure 214 of the asymmetric PFET device reduces the electric-field at the interface of the gate and the drain region and improves both GIDL and TDDB compared to a PFET device having a thinner GOX layer. The thinner GOX layer 322 in the gate structure 314 of the NFET device provides for higher performance.

[0056] FIG. 3 illustrates an NFET device for the common-source FET Mcs and an asymmetric PFET device for the common-gate FET MCG- In alternative embodiments, the common-source FET Mcs may be a PFET device. For example, FIG. 4 is a stylized cross- sectional view of an SOI IC structure 400 that implements a second version of the amplifier core 102 shown in FIG. 1. The illustrated IC structure 400 essentially combines the asymmetric PFET device of FIG. 2A (with the same reference numbers) with a symmetric PFET device. The bounding STI structures 208 shown in FIG. 2A are omitted to avoid clutter, but would essentially bound both devices but would not be interposed between shared regions of the devices.Attorney Docket No. P3133-PCTInventors: Jagar Singh et al.

[0057] The common-source PFET device includes a P+ source 410, an N-type body 412 (also known as an “N-well”), a gate structure 414, and a P+ drain 416. The illustrated gate structure 414 includes a conductive layer 420, such as P+ doped polysilicon, atop an insulating GOX layer 422. In the illustrated example, the gate structure 414 is surrounded by insulating spacers 424, which may be formed in multiple layers (two layers, separated by a dotted line, are shown for each illustrated insulating spacer 424). Parts of the gate structure 414 and the drain 416 may be coated with a dielectric, such as SiCL, Si4N4, etc., which in turn may be overlaid with a SAB layer, such as Si4N4- see FIG. 6H for an example.

[0058] A conductive source contact 426, a conductive gate contact 428, and a conductive drain contact 430, which may be salicides, are respectively formed in electrical and physical contact with the source 410, the gate conductive layer 420, and the drain 416. Stylized electrical terminals S, G, and D are shown coupled to the corresponding source contact 426, the gate contact 428, and the drain contact 440, respectively. The source 410 of the common-source PFET device and the drain 216 of the common-gate asymmetric PFET device are a P+ shared region and are capped by a shared conductive drain contact 426, 230, thus allowing a common source / drain (S / D) terminal.

[0059] The illustrated symmetric common-source PFET device includes a lightly-doped drain (LDD) region 432 and a doped halo region 434 formed underneath the gate structure 414 (1) between portions of the source 410 and the body 412, and (2) between portions of the drain 416 and the body 412. Again, the doped halo regions 434 mitigate punch-through while the LDD regions 432 mitigate avalanche breakdown. Some embodiments may omit one or the other of the LDD regions 332 or the doped halo regions 334.

[0060] In the illustrated example, the source 410 and drain 416 of the common-source PFET device are both Si, but may include other materials, including SiGe. The common-source PFET device is preferably fabricated as a thin-gate oxide device to provide high performance, while the asymmetric PFET device, functioning as the common-gate FET MCG, is preferably fabricated as a thick-gate oxide device to withstand higher voltages.

[0061] In alternative embodiments, the common-source FET Mcs may be an asymmetric NFET, an asymmetric PFET, or an extended-drain FET device. Additional asymmetric PFET devices within the optional asymmetric PFET device stack 104 may be abutted, drain-to-Attorney Docket No. P3133-PCT Inventors: Jagar Singh et al. source, to the illustrated asymmetric PFET devices of FIGS. 3 and 4 to withstand even higher drain- source voltages.

[0062] In some embodiments, it may be useful to fabricate the spacers 224 to be asymmetric. For example, the thickness (in the X dimension) of the drain-side spacer 224 may be greater than the thickness of the source-side spacer 224. For example, a drain-side dielectric spacer may have a thickness of about 1-2 kA, while a source-side spacer may have a thickness of about 2-4 kA. Asymmetric spacers may provide a higher breakdown voltage due to being thicker on the drain-side of the gate structure 214.

[0063] For asymmetric PFET devices such as those shown in FIGS. 2-4, performance may be improved by fabricating all or a portion of the source 210 so as to include SiGe in the form of a heterogeneous or homogenous SiGe alloy, including Ge-doped Si, graded Ge and Si mixtures, or the like. The active layer 206 may be Si having a <110>, <100>, or <111> orientation. An SiGe source region exerts compression on the N-well channel of the asymmetric PFET device, thereby improving hole mobility. Hole mobility in Ge and SiGe generally is greater than hole mobility in Si alone, particularly when the active layer 206 has a <110> orientation. For example, in an active layer 206 of Si having a < 110> orientation, Ge has about 4 to 5 times greater hole mobility than Si when compressed to between 2 and 3 gigapascals (GPa), with various SiGe alloys having intermediate hole mobilities. Increased hole mobility for Ge and SiGe also occurs in Si having a <100> or <111 > orientation. Leaving the drain 216 as Si provides a higher junction breakdown characteristic.

[0064] A further advantage of an asymmetric PFET architecture is the existence of an N- type channel, which may result in low leakage current at active layer edges (no dopant segregation to cause leakage). In some embodiments, the existence of an N-type channel may result in a low channel resistance, which increases the BVON of the device. Low bipolar action of an asymmetric PFET device at its source also improves the BVON. Due to the presence of an extended drift region 218, an asymmetric PFET device also has a high junction breakdown BVDSS value.

[0065] FIGS. 5A-5H are stylized cross-sectional views of various SOI IC structures for an asymmetric PFET device having source regions 210 that include SiGe. The substrate, contacts, and upper regions of the gate structure are omitted from the figures to avoid clutter. The GOXAttorney Docket No. P3133-PCT Inventors: Jagar Singh et al. layer 222 is shown to indicate relative position of regions formed within the active layer 206, but the figures do not represent the typical order of region or layer fabrication.

[0066] In FIG. 5A, the P+ source 210 is fabricated by, for example, etching or forming a cavity in the active layer 206 down to the BOX layer 206 on the source-side edge of the channel region and filling the cavity with SiGe. In FIG. 5B, the P+ SiGe source 210 does not extend all the way down to the BOX layer 204, achieved, for example, by controlling the etch time for making the cavity for the SiGe material. The SiGe source 210 extends into the source-side edge of the channel region with a rounded shape resulting from use of a particular etchant (details below). The introduction of SiGe increases the interatomic spacing within the crystal structure of the source 210, thereby compressing the channel region of the device within the N-well 212. Such compression significantly improves hole mobility within the asymmetric PFET device.

[0067] In FIG. 5C, the P+ source 210 is fabricated by, for example, etching or forming a cavity in the active layer 206 down to the BOX layer 206 on the source-side edge of the channel region and filling the cavity with SiGe. In FIG. 5D, the P+ SiGe source 210 is not etched or formed so as to extend all the way down to the BOX layer 204. The SiGe source 210 extends into the source- side edge of the channel region with an angled or pointed shape resulting from use of a particular etchant (details below). Again, the introduction of Ge into Si increases the interatomic spacing within the crystal structure of the SiGe regions, thereby compressing the channel region of the device to significantly improve hole mobility within the asymmetric PFET.

[0068] In FIG. 5E, the P+ source 210 is fabricated by, for example, etching or forming a cavity in the active layer 206 down to the BOX layer 206 on the source-side edge of the channel region and filling the cavity with SiGe. Alternatively, the P+ source 210 may be formed by epitaxial growth of SiGe on a thin layer of Si above the BOX layer 206, with the other illustrated structures formed around the SiGe. In FIG. 5F, the P+ SiGe source 210 is not etched or formed so as to extend all the way down to the BOX layer 204. The P+ source 210 is fabricated so that the SiGe does not extend significantly into the channel region. Nevertheless, the introduction of Ge into Si increases the interatomic spacing within the crystal structure of the SiGe regions, thereby compressing the channel region of the device to improve hole mobility within the asymmetric PFET device.Attorney Docket No. P3133-PCT Inventors: Jagar Singh et al.

[0069] In some embodiments, the source-side cavity is not completely filled with SiGe, allowing a cap of Si to be formed over the SiGe (see dotted lines within the source 210 in FIGS. 5E and 5F indicating that Si could be formed above that line). The structures shown in FIGS. 5A-5D and 5G-5H may be similarly modified to include a cap of Si over the SiGe within the source 210. Alternatively, a Si cap may be formed over a source-side cavity completely filled with SiGe, thus forming a raised source, reducing parasitic resistance. A silicon cap may also be beneficial for ease of implementation of additional process steps (e.g., growing oxides or forming silicides).

[0070] In FIG. 5G, the P+ source 210 is fabricated, for example, by implanting Ge into an Si region in the active layer 206 down to the BOX layer 206 on the source-side edge of the channel region. In FIG. 5H, the P+ SiGe source 210 is not implanted with Ge so as to extend SiGe all the way down to the BOX layer 204. Again, the introduction of Ge into Si increases the interatomic spacing within the crystal structure of the SiGe regions, thereby compressing the channel region of the device to significantly improve hole mobility within the asymmetric PFET.

[0071] FIGS. 6A-6H are cross-sectional stylized views of example fabrication stages for the novel asymmetric PFET devices of FIGS. 2-4, where the active layer 206 (by way of example only) is Si having a < 110> orientation. The stages would be essentially the same for the asymmetric PFET devices of FIGS. 5C-5F with the exception of the selection of etchant for the region in which the P+ SiGe source 210 is formed.

[0072] FIG. 6A shows a portion of an active layer 206 formed on a BOX layer 204, which is in turn formed on top of a substrate 202. Additionally, isolation structures 208 and a N-type body region or well 212 have been formed in a conventional manner. In some embodiments, the active layer 206 may be formed directly on top of a bulk Si substrate 206, thus omitting the BOX layer 204, so long as some form of isolation is provided (and possibly a buried N+ layer). If needed, the semiconductor active layer 206 may be thinned to a suitable thickness, such as by chemical-mechanical polishing (CMP). For example, commercially available SOI wafers may have an active layer thickness of about 750A. It may be useful for some applications, particularly for RF ICs, to thin the active layer 206, for example, to about 500A.

[0073] FIG. 6B shows a gate structure 214 formed in contact with a surface of the active layer 206. The gate structure 214 includes a conductive layer 220 e.g., P+ doped polysilicon)Attorney Docket No. P3133-PCT Inventors: Jagar Singh et al. in contact with an insulating GOX layer 222, and surrounding insulating spacers 224. The gate structure 214 may be formed by conventional MOSFET fabrication processes such as thermal oxidation, epitaxial deposition, photolithographic masking and etching, etc.

[0074] FIG. 6C shows that an etchant block 600 of SiO has been formed over the conductive layer 220 of the gate structure 214 and that the active layer 206 has been masked and etched to form a void 602 within the active layer 206. The void 602 is the location where the P+ SiGe source 210 is to be formed. In FIG. 6C, the void 602 extends into the <110> channel material with a rounded or undercut shape resulting from use of an isotropic silicon etchant such as NH4OH, KOH, or ethylenediamine pyrocatechol (EDP).

[0075] A pointed shape for the void 602 matching the SiGe regions shown in FIG. 5C may be formed by using an anisotropic silicon etchant such as tetra methyl ammonium hydroxide (TMAH) A straight-walled void matching the SiGe regions shown in FIG. 5E may be formed, for example, by dry plasma etching.

[0076] As shown in FIGS. 5B, 5D, and 5F, the Z-dimension of the void 602 need not extend all the way down to the BOX layer 204, which may be controlled, for example, by the duration of etching. Indeed, it may be useful to leave a thin layer of Si within the void 602 to serve as a seed layer for subsequent epitaxial growth of a SiGe alloy.

[0077] FIG. 6D shows that the void 602 of FIG. 6C has been filled with a SiGe alloy, such as by chemical vapor deposition (CVD), to become a SiGe source 210.

[0078] FIG. 6E shows that the Si active layer 206 on the drain-side of the gate structure 214 is doped (e.g., by angled ion implantation after suitable masking) with a P- material (e.g., boron) to form a P- drift region 218. The implantation is generally performed at an angle so that a portion of the N-well material (including a portion underneath the gate structure 214) is also converted into the P- drift region 218.

[0079] FIG. 6F shows that the active layer 206 on the source-side of the gate structure 214 is doped (<?.g., by angled ion implantation after suitable masking) with a suitable dopant to form an LDD region 232 and a halo region 234 within the N-well material (including a portion underneath the gate structure 214). Note that the tilt angles of implantation for the LDD region 232 and the halo region 234 may differ.Attorney Docket No. P3133-PCT Inventors: Jagar Singh et al.

[0080] FIG. 6G shows that a portion of the P- SiGe drift region 214 of FIG. 6F has been defined by masking and then doped with a P+ dopant (e.g., boron) to transform that region into the P+ SiGe drain 216. Doping may be by ion implantation or diffusion. Subsequently, N+ material may be implanted in selected areas of the P+ SiGe source 210 and the P+ SiGe drain 216 to form body-tied-to-source connections.

[0081] FIG. 6H shows that part of the etchant block 600 (see FIG. 6G) has been removed, part of the gate structure 214 and the exposed portions of the P- drift region 218 has been coated with a dielectric 240 (SiC , SisN4, etc.), and an SAB layer 242 (e.g., Si3N4) has been formed over the dielectric 240. A conductive source contact 226, a conductive gate contact 228, and a conductive drain contact 230, which may be salicides, have been respectively formed in contact with the P+ SiGe source 210, the conductive layer 220 of the gate structure 214, and the P+ Si drain 216. Stylized electrical terminals S, G, and D are shown coupled to the corresponding source contact 226, gate contact 228, and drain contact 230.

[0082] FIGS. 7A-7B are cross-sectional stylized views of a first set of alternative fabrication stages for an asymmetric PFET device that includes an SiGe source region. The fabrication stages shown in FIGS. 6A-6B would be followed by the fabrication stage shown in FIG. 7A.

[0083] FIG. 7 A shows that the active layer 206 has been masked and etched (e.g., by dry plasma etching) down to the BOX layer 204 to form a vertical-sidewall void 702 within the active layer 206. The void 702 is the location where the P+ SiGe source 210 is to be formed. In some embodiments, etching may be stopped before reaching the BOX layer 204, as in the example shown in FIG. 5F.

[0084] FIG. 7B shows that the void 702 of FIG. 7A has been filled with a SiGe alloy (such as by CVD, LPCVD, or an epitaxial deposition-like process), to become a filled SiGe source 210. Fabrication may then continue as shown in FIGS. 6E-6H.

[0085] FIGS. 8A-8B are cross-sectional stylized views of a second set of alternative fabrication stages for an asymmetric PFET device that includes an SiGe source region. The fabrication stages shown in FIGS. 6A-6B would be followed by the fabrication stage shown in FIG. 8A. FIG. 8A shows that the active layer 206 has been masked to define a Si region 802 within the active layer 206 and that the defined region 802 is implanted (e.g., by ionAttorney Docket No. P3133-PCT Inventors: Jagar Singh et al. implantation) with Ge (that masking material has been omitted to avoid clutter). Region 802 is the location where the P+ SiGe source 210 is to be formed.

[0086] FIG. 8B shows the device structure of FIG. 8A after implantation of Ge into the defined region 802 and annealing of the structure sufficiently to diffuse the Ge so as to create a graded SiGe source 210. As illustrated, some of the diffused Ge may intrude into the channel region underneath the gate structure 214. The graded SiGe 210 imposes compression across the channel region, thus improving hole mobility. Fabrication may then continue as shown in FIGS. 6E-6H.

[0087] FIGS. 9A-9C are cross-sectional stylized views of a third set of alternative fabrication stages for an asymmetric PFET device that includes an SiGe source region. The fabrication stages shown in FIGS. 6A-6B would be followed by the fabrication stage shown in FIG. 9A.

[0088] FIG. 9A shows that the active layer 206 has been masked and partially etched (e.g. , by dry plasma etching) to form a vertical-sidewall void 902 within the active layer 206 with a Si base 904 (z.e., an unetched remainder of the silicon active layer 206). The void 902 and its underlying Si base 904 is the location where the P+ SiGe source 210 is to be formed.

[0089] FIG. 9B shows the device structure of FIG. 9A after deposition of Ge into the region 906 (e.g., by CVD) so as to occupy some or all of the void 902 of FIG. 9A.

[0090] FIG. 9C shows the device structure of FIG. 9B after being subjected to heat treatment sufficient to diffuse the Ge region 906 into the Si base 904 of FIG. 9B to create a graded SiGe source 210. As illustrated, some of the diffused Ge may intrude into the channel region underneath the gate structure 214. The graded SiGe source 210 imposes compression across the channel region, thus improving hole mobility. In some embodiments, diffusion of Ge is controlled so as to not reach all of way to the BOX layer 204. Fabrication may then continue as shown in FIGS. 6E-6H.

[0091] It should be appreciated that fabrication of a symmetric NFET device, an asymmetric NFET device, or a symmetric PFET device, as well as extended-drain variants, may be accomplished using process steps identical to, or very similar to, the process steps for fabricating the asymmetric PFETs shown in FIGS. 6A-6H, 7A-7B, 8A-8B, and / or 9A-9C.Attorney Docket No. P3133-PCT Inventors: Jagar Singh et al.

[0092] Note that not all steps that may be performed during the manufacture of an - asymmetric PFET device as part of an IC are shown in the aforementioned figures. Such steps may vary between IC foundries and may include (but are not limited to) substrate thinning, planarization, special implantations, annealing, formation of ohmic contacts, and formation of additional temporary or permanent structures (e.g. , drift regions, substrate contacts, passivation layers, salicide blocks, replacement metal gate (RMG)), etc. After formation of a basic MOSFET structure, back-end-of-line (BEOL) processes may be applied, such as fabrication of electrical contacts (pads), vias, insulating layers (dielectrics), metallization layers, and bonding sites for die-to-package connections.

[0093] A number of different processes may be used to fabricate the asymmetric PFET devices described in this disclosure. FIG. 10 is a process flowchart 1000 showing one fabrication process for an asymmetric PFET device that is suitable for some contemporary IC front-end-of-line (FEOL) foundries. Note that some conventional steps, such as planarization, passivation, details of masking and etching, and superstructure formation have been omitted as known to those of ordinary skill in the art. The illustrated process includes:(1) If needed, thinning the semiconductor active layer (e.g., Si, Ge, SiGe, SiC, or the like) formed on a substrate to a suitable thickness (Step 1002).(2) Forming shallow trench isolation (STI) regions (Step 1004).(3) Implanting N-type wells (Step 1006).(4) Performing gate oxidation (Step 1008).(5) Depositing gate material (e.g., P+ poly-Si), patterning (e.g., masking and etching) to define gate structures, and forming gate structure spacers (Step 1010).(6) Defining and forming a SiGe region for the source 210 (Step 1012). This may be done, for example, by etching voids in the active layer 206 and depositing SiGe within the voids (see, e.g., FIGS. 6C-6D and 7A-7B); implanting Ge into a defined regions of the Si active layer 206 to form a SiGe source 210 (see, e.g., FIGS. 8A-8B); or etching partial a void in the Si active layer 206, depositing Ge within the partial void, and thermally diffusing the Ge into the Si to form a graded SiGe source 210 (see, e.g., FIGS. 9A-9C).(7) Patterning a drift region 218 and angle implanting P- dopant (Step 1014)Attorney Docket No. P3133-PCT Inventors: Jagar Singh et al.(8) Optionally, patterning source-side halo and / or LDD regions and angle implanting dopant (Step 1016).(9) Implanting a P+ drain region and one or more N+ body contact regions (Step 1018).(10) Depositing a salicide block layer and patterning to define contact regions (Step 1020).(11) Depositing or forming salicide (e.g., N Si) in the defined contact regions and annealing (Step 1022).

[0094] As should be appreciated, other “recipes” that include additive and / or subtractive process steps may be used to fabricate essentially the same asymmetric PFET device structures of the type described in this disclosure. Further, the fabrications steps may be performed in any feasible order.

[0095] In some embodiments, the drain 216 may include SiGe, formed in a manner similar to the formation of the SiGe source 210. In some embodiments, a highly compressive nitride stress liner (e.g. , SisNa) may be deposited over the source 210 and possibly some portion of the gate structure 214 after the formation of salicide contacts. The stress liner may transfer stress to the channel, further enhancing hole mobility. For example, FIG. 11 is a cross-sectional stylized view of a novel asymmetric PFET device that includes both a SiGe drain 216 and a stress liner 1102.

[0096] Embodiments of the illustrated IC structures described above, and variations of such structures, may include raised or sunken source and / or drain regions. Raised source and / or drain regions generally reduce parasitic resistance. Doping for the drift region 218 of the asymmetric PFETs need not be uniform, and may vary along at least the X dimension of the device.

[0097] It is common to include a body-tied-to-source (BTS) structure for MOSFETs, and a BTS configuration may be used with the device architectures described above. In N-type MOSFETS, a BTS structure generally comprises a small region of isolated P+ material located within the N+ source region or extending out from the edge of the device that couples to the body of the device. In P-type MOSFETS, a BTS structure generally comprises a small region of isolated N+ material located within the P+ source region or extending from the edge of theAttorney Docket No. P3133-PCT Inventors: Jagar Singh et al. device that couples to the body of the device. A BTS structure thus provides a body terminal for the device, which is commonly (but not necessarily) connected to the source.

[0098] A BTS structure in an asymmetric PFET fabricated on an SOI substrate is of a special importance - the BTS structure eliminates or substantially mitigates the floating body current effect; mitigates turn-on of the parasitic bipolar devices inherent in the device; improves the breakdown voltage of the device; improves electro-static discharge (ESD) protection for the device; improves the output impedance of the device (very important for analog circuits); and improves device and circuitry performance and capability, and in particular improves circuit linearity, reliability, and power consumption in analog and digital circuitry, especially for such devices as RF and mmWave switches, low- noise amplifiers (LNAs), and power amplifiers (PAs).

[0099] FIG. 12 is a top plan view of a first configuration of BTS structures for multiple asymmetric PFETs devices 1202-1, 1202-2, 1202-3 co-fabricated with an NFET device 1204. Each device includes a respective gate, G1-G4. Electrical terminals 1206 are symbolically shown as squares with an interior “X” (not all terminals are labeled to avoid clutter). The drain DN of the NFET device 1204 (which may be symmetric, asymmetric, or have an extended drain) is shown as coupled to the drain Dp of a first asymmetric PFET device 1202-1. The source Sp of the asymmetric PFET device 1202-1 is coupled to the drain Dp of a second asymmetric PFET device 1202-2, and the source Sp of the asymmetric PFET device 1202-2 is coupled to the drain Dp of a third asymmetric PFET device 1202-3. Each asymmetric PFET device 1202- / ? includes two end-positioned BTS structures comprising N+ body contact regions 1208 (associated terminals are omitted to avoid clutter). Placing the BTS structures along and parallel to the X-dimension edges of the asymmetric PFET devices 1202- / ? reduces current leakage by increasing the VTH at those edges. Having more than one BTS structure provides more efficient electron (e-) collection compared to a single central BTS structure. However, in some embodiments, a single central BTS structure may be sufficient.

[0100] FIG. 13 is a top plan view of a second configuration of BTS structures for multiple asymmetric PFETs devices 1202-1, 1202-2, 1202-3 co-fabricated with an NFET device 1204. Similar in most aspects to the example shown in FIG. 12, one difference is the inclusion of both end-positioned N+ body contact regions 1208 and multiple interior-positioned N+ body contact regions 1302 (not all interior body contact regions are labeled to avoid clutter). TheAttorney Docket No. P3133-PCT Inventors: Jagar Singh et al. added interior body contact regions 1302 provide even more efficient electron (e-) collection than the configuration shown in FIG. 12.

[0101] For some applications, it may not be necessary to include BTS structures since holes have a lower impact ionization rate. Omitting some or all BTS structures may save IC layout area.

[0102] In variations of the embodiments of FIGS. 12 and 13, the NFET device 1204 may be replaced by a PFET device (which may be symmetric or asymmetric), in which case the source and drain regions of the PFET device would be reversed with respect to the illustrated NFET device 1204 (see also FIG. 4).

[0103] It should be appreciated that a number of features described in this disclosure may be “mixed and matched” to create further variations without departing from the scope of the invention. For instance, one or more asymmetric PFET devices in an IC structure may include a secondary gate structure. As another example, one or more of the PFET devices in an IC structure may include a stepped GOX layer. Accordingly, the invention is not limited to the specific examples described and illustrated in this disclosure.

[0104] A benefit of the IC structures described above, and variations of such structures, is the space savings in IC layouts resulting from the use of shared regions between adjacent devices, particularly when concatenating multiple FET devices and sharing drain / source or drain / drain regions. In addition, space savings may also be achieved due to the higher breakdown BVDSS value of such devices, which gives designers freedom to reduce the transistor count for a particular application.

[0105] Circuits and devices in accordance with the present invention may be used alone or in combination with other components, circuits, and devices. Embodiments of the present invention may be encased in IC packages and / or in modules for ease of handling, manufacture, and / or improved performance. In particular, IC embodiments of this invention are often used in modules in which one or more of such ICs are combined with other circuit components or blocks (e.g., filters, amplifiers, passive components, and possibly additional ICs) into one package. The ICs and / or modules are then typically combined with other components, often on a printed circuit board, to form part of an end-product such as a cellular telephone, laptop computer, or electronic tablet, or to form a higher-level module which may be used in a wide variety of products, such as vehicles, test equipment, medical devices, etc. Through variousAttorney Docket No. P3133-PCT Inventors: Jagar Singh et al. configurations of modules and assemblies, such ICs typically enable a mode of communication, often wireless communication.

[0106] As one example of further integration of embodiments of the present invention with other components, FIG. 14 is a top plan view of a substrate 1400 that may be, for example, a printed circuit board or chip module substrate (e.g. , a thin-film tile). In the illustrated example, the substrate 1400 includes multiple ICs 1402a-1402d having terminal pads 1404 which would be interconnected by conductive vias and / or traces on and / or within the substrate 1400 or on the opposite (back) surface of the substrate 1400 (to avoid clutter, the surface conductive traces are not shown and not all terminal pads are labelled). The ICs 1402a-1402d may embody, for example, signal switches, active and / or passive filters, amplifiers (including one or more LNAs), and other circuitry. For example, IC 1402b may incorporate one or more instances of an LNA having an IC structure like the structures described in this disclosure.

[0107] The substrate 1400 may also include one or more passive devices 1406 embedded in, formed on, and / or affixed to the substrate 1400. While shown as generic rectangles, the passive devices 1406 may be, for example, filters, capacitors, inductors, transmission lines, resistors, antennae elements, transducers (including, for example, MEMS-based transducers, such as accelerometers, gyroscopes, microphones, pressure sensors, etc.), batteries, etc., interconnected by conductive traces on or in the substrate 1400 to other passive devices 1406 and / or the individual ICs 1402a-1402d.

[0108] The front or back surface of the substrate 1400 may be used as a location for the formation of other structures. For example, one or more antennae may be formed on or affixed to the front or back surface of the substrate 1400; one example of a front-surface antenna 1408 is shown, coupled to an IC die 1402b, which may include RF front-end circuitry. Thus, by including one or more antennae on the substrate 1400, a complete radio may be created.

[0109] Embodiments of the present invention are useful in a wide variety of larger radio frequency (RF) circuits and systems for performing a range of functions, including (but not limited to) RF power amplifiers, RF low-noise amplifiers (LNAs), antenna beam-steering systems, charge pump devices, pull-down devices, etc. Such functions are useful in a variety of applications, such as radar systems (including phased array and automotive radar systems), radio systems (including cellular radio systems), and test equipment.Attorney Docket No. P3133-PCTInventors: Jagar Singh et al.

[0110] Radio system usage includes wireless RF systems (including base stations, relay stations, and hand-held transceivers) that use various technologies and protocols, including various types of orthogonal frequency-division multiplexing (“OFDM”), quadrature amplitude modulation (“QAM”), Code-Division Multiple Access (“CDMA”), Time-Division Multiple Access (“TDMA”), Wide Band Code Division Multiple Access (“W-CDMA”), Global System for Mobile Communications (“GSM”), Long Term Evolution (“LTE”), 5G, 6G, and WiFi (<?.g. , 802.11a, b, g, ac, ax, be) protocols, as well as other radio communication standards and protocols.

[0111] As an example of wireless RF system usage, FIG. 15 illustrates a prior art wireless communication environment 1500 comprising different wireless communication systems 1502 and 1504, and which may include one or more mobile wireless devices 1506. A wireless device 1506 may be a cellular phone, a wireless-enabled computer or tablet, or some other wireless communication unit or device. A wireless device 1506 may also be referred to as a mobile station, user equipment, an access terminal, or some other terminology known in the telecommunications industry.

[0112] A wireless device 1506 may be capable of communicating with multiple wireless communication systems 1502, 1504 using one or more of telecommunication protocols such as the protocols noted above. A wireless device 1506 also may be capable of communicating with one or more satellites 1508, such as navigation satellites (e.g. , GPS) and / or telecommunication satellites. The wireless device 1506 may be equipped with multiple antennas, externally and / or internally, for operation on different frequencies and / or to provide diversity against deleterious path effects such as fading and multi-path interference.

[0113] The wireless communication system 1502 may be, for example, a CDMA-based system that includes one or more base station transceivers (BSTs) 1510 and at least one switching center (SC) 1512. Each BST 1510 provides over-the-air RF communication for wireless devices 1506 within its coverage area. The SC 1512 couples to one or more BSTs 1510 in the wireless system 1502 and provides coordination and control for those BSTs 1510.

[0114] The wireless communication system 1504 may be, for example, a TDMA-based system that includes one or more transceiver nodes 1514 and a network center (NC) 1516. Each transceiver node 1514 provides over-the-air RF communication for wireless devices 1506Attorney Docket No. P3133-PCT Inventors: Jagar Singh et al. within its coverage area. The NC 1516 couples to one or more transceiver nodes 1514 in the wireless system 1504 and provides coordination and control for those transceiver nodes 1514.

[0115] In general, each BST 1510 and transceiver node 1514 is a fixed station that provides communication coverage for wireless devices 1506, and may also be referred to as base stations or some other terminology known in the telecommunications industry. The SC 1512 and the NC 1516 are network entities that provide coordination and control for the base stations and may also be referred to by other terminologies known in the telecommunications industry.

[0116] An important aspect of any wireless system, including the systems shown in FIG. 15, is in the details of how the component elements of the system perform. FIG. 16 is a block diagram of a transceiver 1600 that might be used in a wireless device, such as a cellular telephone, and which may beneficially incorporate an embodiment of the present invention for improved performance. As illustrated, the transceiver 1600 includes a mix of RF analog circuitry for directly conveying and / or transforming signals on an RF signal path, non-RF analog circuity for operational needs outside of the RF signal path e.g., for bias voltages and switching signals), and digital circuitry for control and user interface requirements. In this example, a receiver path Rx includes RF Front End (RFFE), Intermediate Frequency (IF) Block, Back-End, and Baseband sections (noting that in some implementations, the differentiation between sections may be different). The various illustrated sections and circuit elements may be embodied in one die or multiple IC dies. For example, the RF Front End in the illustrated example may include an RFFE module and a Mixing Block, which may be embodied in (or as part of) different IC dies or modules. The different dies and / or modules may be coupled by transmission lines TIN and TOUT (e.g., microstrips, co-planar waveguides, or an equivalent structure or circuit), either or both of which may have, for example, a 50Q impedance.

[0117] The receiver path Rx receives over-the-air RF signals through at least one antenna 1602 and a switching unit 1604, which may be implemented with active switching devices (e.g., field effect transistors or FETs) and / or with passive devices that implement frequencydomain multiplexing, such as a diplexer or duplexer. An RF filter 1606 passes desired received RF signals to at least one low noise amplifier (LNA) 1608a, the output of which is coupled from the RFFE Module to at least one LNA 1608b in the Mixing Block (through transmission line TIN in this example). The LNA(s) 1608b may provide buffering, input matching, and reverse isolation. In some embodiments, the LNA(s) 1608a and 1608b may be a single LNA.Attorney Docket No. P3133-PCT Inventors: Jagar Singh et al.The LNA(s) 1608a and 1608b may include asymmetric PFET devices in accordance with the present invention.

[0118] The output of the LNA(s) 1608b is combined in a corresponding mixer 1610 with the output of a first local oscillator 1612 to produce an IF signal. The IF signal may be amplified by an IF amplifier 1614 and subjected to an IF filter 1616 before being applied to a demodulator 1618, which may be coupled to a second local oscillator 1620. The demodulated output of the demodulator 1618 is transformed to a digital signal by an analog-to-digital converter 1622 and provided to one or more system components 1624 (e.g., a video graphics circuit, a sound circuit, memory devices, etc.). The converted digital signal may represent, for example, video or still images, sounds, or symbols, such as text or other characters.

[0119] In the illustrated example, a transmitter path Tx includes Baseband, Back-End, IF Block, and RF Front End sections (again, in some implementations, the differentiation between sections may be different). Digital data from one or more system components 1624 is transformed to an analog signal by a digital-to-analog converter 1626, the output of which is applied to a modulator 1628, which also may be coupled to the second local oscillator 1620. The modulated output of the modulator 1628 may be subjected to an IF filter 1630 before being amplified by an IF amplifier 1632. The output of the IF amplifier 1632 is then combined in a mixer 1634 with the output of the first local oscillator 1612 to produce an RF signal. The RF signal may be amplified by a driver 1636, the output of which is coupled to a power amplifier (PA) 1638 (through transmission line TOUT in this example). The amplified RF signal may be coupled to an RF filter 1640, the output of which is coupled to at least one antenna 1602 through the switching unit 804.

[0120] The operation of the transceiver 1600 is controlled by a microprocessor 1642 in known fashion, which interacts with system control components 1644 (e.g., user interfaces, memory / storage devices, application programs, operating system software, power control, etc.). In addition, the transceiver 1600 will generally include other circuitry, such as bias circuitry 1646 (which may be distributed throughout the transceiver 1600 in proximity to transistor devices), electro-static discharge (ESD) protection circuits, testing circuits (not shown), factory programming interfaces (not shown), etc.

[0121] In modem transceivers, there are often more than one receiver path Rx and transmitter path Tx, for example, to accommodate multiple frequencies and / or signalingAttorney Docket No. P3133-PCTInventors: Jagar Singh et al. modalities. Further, as should be apparent to one of ordinary skill in the art, some components of the transceiver 1600 may be positioned in a different order (e.g., filters) or omitted. Other components can be (and often are) added, such as (by way of example only) additional filters, impedance matching networks, variable phase shifters / attenuators, power dividers, etc.

[0122] Another aspect of the invention includes corresponding methods for fabricating an integrated circuit. A first method includes fabricating an asymmetric PFET integrated circuit device by forming a source; forming a body laterally adjacent the source; forming a drift region laterally adjacent the body; forming a drain laterally adjacent the drift region; forming at least one of a lightly-doped drain region or a doped halo region between the source and the body; and forming a gate structure positioned with respect to the body so as to be able to influence current flow through the body between the source and the drain.

[0123] A second method includes fabricating a MOSFET device having a source, a body laterally adjacent the source, a drain laterally adjacent the body, and a gate structure positioned with respect to the body so as to be able to influence current flow through the body; and cofabricating an asymmetric PFET device having a source, a body laterally adjacent the source, a drift region laterally adjacent the body, a drain laterally adjacent the drift region, at least one of a lightly-doped drain region or a doped halo region between the source and the body, and a gate structure positioned with respect to the body so as to be able to influence current flow through the body between the source and the drain; wherein the drain of the asymmetric PFET device shares a common electrical contact with one of the source or the drain of the MOSFET device.

[0124] Additional aspects of the above methods include one or more of the following: wherein the MOSFET device is a symmetric NFET and the drain of the symmetric NFET shares the common electrical contact with the drain of the asymmetric PFET device; wherein the MOSFET device is an asymmetric NFET and the drain of the asymmetric NFET shares the common electrical contact with the drain of the asymmetric PFET device; wherein the MOSFET device is a symmetric PFET and the source of the symmetric PFET shares the common electrical contact with the drain of the asymmetric PFET device; wherein the MOSFET device is an asymmetric NFET and the source of the asymmetric PFET shares the common electrical contact with the drain of the asymmetric PFET device; wherein the gate structure of the asymmetric PFET device includes a stepped gate oxide layer; further including fabricating at least the source of the asymmetric PFET device at least in part with a siliconAttorney Docket No. P3133-PCT Inventors: Jagar Singh et al. germanium alloy; wherein the asymmetric PFET device includes two end-positioned body- tied- to-source structures; wherein the asymmetric PFET device includes two end-positioned body contact regions and at least one interior-positioned body contact region; and / or further including co-fabricating at least one additional asymmetric PFET device, each including source, a body laterally adjacent the source, a drift region laterally adjacent the body, a drain laterally adjacent the drift region, at least one of a lightly-doped drain region or a doped halo region between the source and the body, and a gate structure positioned with respect to the body so as to be able to influence current flow through the body between the source and the drain, wherein the drain of each additional asymmetric PFET device is shared in common with the source of the asymmetric PFET device or the source of one of the additional asymmetric PFET devices.

[0125] The term “MOSFET”, as used in this disclosure, includes any field effect transistor (FET) having an insulated gate whose voltage or charge level determines the conductivity of the transistor, and encompasses insulated gates having a metal or metal-like, insulator, and / or semiconductor structure. The terms “metal” or “metal-like” include at least one electrically conductive material (such as aluminum, copper, or other metal, or highly doped polysilicon, graphene, or other electrical conductor), “insulator” includes at least one insulating material (such as silicon oxide or other dielectric material), and “semiconductor” includes at least one semiconductor material.

[0126] As used in this disclosure, the term “radio frequency” (RF) refers to a rate of oscillation in the range of about 3 kHz to about 300 GHz. This term also includes the frequencies used in wireless communication systems. An RF frequency may be the frequency of an electromagnetic wave or of an alternating voltage or current in a circuit.

[0127] With respect to the figures referenced in this disclosure, the dimensions for the various elements are not to scale; some dimensions may be greatly exaggerated vertically and / or horizontally for clarity or emphasis. In addition, references to orientations and directions (e.g., “top”, “bottom”, “above”, “below”, “lateral”, “vertical”, “horizontal”, etc.) are relative to the example drawings, and not necessarily absolute orientations or directions.

[0128] Various embodiments of the invention can be implemented to meet a wide variety of specifications. Unless otherwise noted above, selection of suitable component values is a matter of design choice. Various embodiments of the invention may be implemented in anyAttorney Docket No. P3133-PCTInventors: Jagar Singh et al. suitable integrated circuit (IC) technology (including but not limited to MOSFET structures), or in hybrid or discrete circuit forms. Integrated circuit embodiments may be fabricated using any suitable substrates and processes, including but not limited to standard bulk silicon, high- resistivity bulk CMOS, silicon-on-insulator (SOI), and silicon-on-sapphire (SOS). Unless otherwise noted above, embodiments of the invention may be implemented in other transistor technologies, such as BiCMOS, LDMOS, and FinFET devices. However, embodiments of the invention are particularly useful when fabricated using an SOI or SOS based process, or when fabricated with processes having similar characteristics. Fabrication in CMOS using SOI or SOS processes enables circuits with low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity, and high frequency operation (i.e. , radio frequencies up to and exceeding 300 GHz). Monolithic IC implementation is particularly useful since parasitic capacitances generally can be kept low (or at a minimum, kept uniform across all units, permitting them to be compensated) by careful design.

[0129] Voltage levels may be adjusted, and / or voltage and / or logic signal polarities reversed, depending on a particular specification and / or implementing technology (e.g., NMOS, PMOS, or CMOS, and enhancement mode or depletion mode transistor devices). Component voltage, current, and power handling capabilities may be adapted as needed, for example, by adjusting device sizes, serially “stacking” components (particularly FETs) to withstand greater voltages, and / or using multiple components in parallel to handle greater currents. Additional circuit components may be added to enhance the capabilities of the disclosed circuits and / or to provide additional functionality without significantly altering the functionality of the disclosed circuits.

[0130] Conclusion

[0131] A number of embodiments of the invention have been described. It is to be understood that various modifications may be made without departing from the spirit and scope of the invention. For example, some of the steps described above may be order independent, and thus can be performed in an order different from that described. Further, some of the steps described above may be optional. Various activities described with respect to the methods identified above can be executed in repetitive, serial, and / or parallel fashion.

[0132] It is to be understood that the foregoing description is intended to illustrate and not to limit the scope of the invention, which is defined by the scope of the following claims, andAttorney Docket No. P3133-PCT Inventors: Jagar Singh et al. that other embodiments are within the scope of the claims. In particular, the scope of the invention includes any and all feasible combinations of one or more of the processes, machines, manufactures, or compositions of matter set forth in the claims below. (Note that the parenthetical labels for claim elements are for ease of referring to such elements, and do not in themselves indicate a particular required ordering or enumeration of elements; further, such labels may be reused in dependent claims as references to additional elements without being regarded as starting a conflicting labeling sequence).

Claims

Attorney Docket No. P3133-PCT Inventors: Jagar Singh et al.CLAIMS1. An asymmetric PFET device including:(a) a source;(b) a body laterally adjacent the source;(c) a drift region laterally adjacent the body;(d) a drain laterally adjacent the drift region;(e) at least one of a lightly-doped drain region or a doped halo region between the source and the body; and(f) a gate structure positioned with respect to the body so as to be able to influence current flow through the body between the source and the drain.

2. The asymmetric PFET device of claim 1, wherein the gate structure of the asymmetric PFET device includes a stepped gate oxide layer.

3. The asymmetric PFET device of claim 1, wherein at least the source of the asymmetric PFET device is fabricated at least in part with a silicon germanium alloy.

4. The asymmetric PFET device of claim 1, wherein the asymmetric PFET device includes two end-positioned body-tied-to-source structures.

5. The asymmetric PFET device of claim 1, wherein the asymmetric PFET device includes at least one interior-positioned body contact region.

6. The asymmetric PFET device of claim 1, wherein the asymmetric PFET device includes two end-positioned body contact regions and at least one interior-positioned body contact region.

7. An integrated circuit including:(a) a MOSFET device having a source, a body laterally adjacent the source, a drain laterally adjacent the body, and a gate structure positioned with respect to the body so as to be able to influence current flow through the body; and(b) an asymmetric PFET device having a source, a body laterally adjacent the source, a drift region laterally adjacent the body, a drain laterally adjacent the drift region, at least one of a lightly-doped drain region or a doped halo region between the source and the body, and a gate structure positioned with respect to the body so as to be able to influence current flow through the body between the source and the drain;Attorney Docket No. P3133-PCT Inventors: Jagar Singh et al. wherein the drain of the asymmetric PFET device shares a common electrical contact with one of the source or the drain of the MOSFET device.

8. The integrated circuit of claim 7, wherein the MOSFET device is a symmetric NFET and the drain of the symmetric NFET shares the common electrical contact with the drain of the asymmetric PFET device.

9. The integrated circuit of claim 7, wherein the MOSFET device is an asymmetric NFET and the drain of the asymmetric NFET shares the common electrical contact with the drain of the asymmetric PFET device.

10. The integrated circuit of claim 7, wherein the MOSFET device is a symmetric PFET and the source of the symmetric PFET shares the common electrical contact with the drain of the asymmetric PFET device.

11. The integrated circuit of claim 7, wherein the MOSFET device is an asymmetric NFET and the source of the asymmetric PFET shares the common electrical contact with the drain of the asymmetric PFET device.

12. The integrated circuit of claim 7, wherein the gate structure of the asymmetric PFET device includes a stepped gate oxide layer.

13. The integrated circuit of claim 7, wherein at least the source of the asymmetric PFET device is fabricated at least in part with a silicon germanium alloy.

14. The integrated circuit of claim 7, wherein the asymmetric PFET device includes two end- positioned body-tied-to-source structures.

15. The asymmetric PFET device of claim 7, wherein the asymmetric PFET device includes at least one interior-positioned body contact region.

16. The integrated circuit of claim 7, wherein the asymmetric PFET device includes two end- positioned body contact regions and at least one interior-positioned body contact region.

17. The integrated circuit of claim 7, further including at least one additional asymmetric PFET device, each including source, a body laterally adjacent the source, a drift region laterally adjacent the body, a drain laterally adjacent the drift region, at least one of a lightly-doped drain region or a doped halo region between the source and the body, and a gate structureAttorney Docket No. P3133-PCT Inventors: Jagar Singh et al. positioned with respect to the body so as to be able to influence current flow through the body between the source and the drain, wherein the drain of each additional asymmetric PFET device is shared in common with the source of the asymmetric PFET device or the source of one of the additional asymmetric PFET devices.

18. A method of fabricating an asymmetric PFET integrated circuit device including:(a) forming a source;(b) forming a body laterally adjacent the source;(c) forming a drift region laterally adjacent the body;(d) forming a drain laterally adjacent the drift region;(e) forming at least one of a lightly-doped drain region or a doped halo region between the source and the body; and(f) forming a gate structure positioned with respect to the body so as to be able to influence current flow through the body between the source and the drain.

19. The method claim 18, wherein the gate structure of the asymmetric PFET integrated circuit device includes a stepped gate oxide layer.

20. The method claim 18, wherein at least the source of the asymmetric PFET integrated circuit device is fabricated at least in part with a silicon germanium alloy.

21. The method claim 18, wherein the asymmetric PFET integrated circuit device includes two end-positioned body-tied-to-source structures.

22. The method claim 18, wherein the asymmetric PFET device includes at least one interior- positioned body contact region.

23. The method claim 18, wherein the asymmetric PFET integrated circuit device includes two end-positioned body contact regions and at least one interior-positioned body contact region.

24. A method of fabricating an integrated circuit, including:(a) fabricating a MOSFET device having a source, a body laterally adjacent the source, a drain laterally adjacent the body, and a gate structure positioned with respect to the body so as to be able to influence current flow through the body; andAttorney Docket No. P3133-PCT Inventors: Jagar Singh et al.(b) co-fabricating an asymmetric PFET device having a source, a body laterally adjacent the source, a drift region laterally adjacent the body, a drain laterally adjacent the drift region, at least one of a lightly-doped drain region or a doped halo region between the source and the body, and a gate structure positioned with respect to the body so as to be able to influence current flow through the body between the source and the drain; wherein the drain of the asymmetric PFET device shares a common electrical contact with one of the source or the drain of the MOSFET device.

25. The method of claim 24, wherein the MOSFET device is a symmetric NFET and the drain of the symmetric NFET shares the common electrical contact with the drain of the asymmetric PFET device.

26. The method of claim 24, wherein the MOSFET device is an asymmetric NFET and the drain of the asymmetric NFET shares the common electrical contact with the drain of the asymmetric PFET device.

27. The method of claim 24, wherein the MOSFET device is a symmetric PFET and the source of the symmetric PFET shares the common electrical contact with the drain of the asymmetric PFET device.

28. The method of claim 24, wherein the MOSFET device is an asymmetric NFET and the source of the asymmetric PFET shares the common electrical contact with the drain of the asymmetric PFET device.

29. The method of claim 24, wherein the gate structure of the asymmetric PFET device includes a stepped gate oxide layer.

30. The method of claim 24, further including fabricating at least the source of the asymmetric PFET device at least in part with a silicon germanium alloy.

31. The method of claim 24, wherein the asymmetric PFET device includes two end-positioned body-tied-to-source structures.

32. The method of claim 24, wherein the asymmetric PFET device includes at least one interior- positioned body contact region.Attorney Docket No. P3133-PCT Inventors: Jagar Singh et al.

33. The method of claim 24, wherein the asymmetric PFET device includes two end-positioned body contact regions and at least one interior-positioned body contact region.

34. The method of claim 24, further including co-fabricating at least one additional asymmetric PFET device, each including source, a body laterally adjacent the source, a drift region laterally adjacent the body, a drain laterally adjacent the drift region, at least one of a lightly- doped drain region or a doped halo region between the source and the body, and a gate structure positioned with respect to the body so as to be able to influence current flow through the body between the source and the drain, wherein the drain of each additional asymmetric PFET device is shared in common with the source of the asymmetric PFET device or the source of one of the additional asymmetric PFET devices.

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