Etching through silicon VIAS having different sizes with minimum depth loading

Abstract

A method for etching a substrate includes providing a substrate including a silicon layer, a dielectric layer, and a mask layer defining a first set of through silicon vias (TSVs) and a second set of TSVs with a first critical dimension (CD) and a second CD, respectively. The first CD and the second CD are different. The method includes depositing a silicon oxide layer using a nonconformal deposition process to provide reverse loading in one of the first set of TSVs and the second set of TSVs corresponding to a larger one of the first CD and the second CD; and performing a rapid alternating process including a plurality of cycles. Each of the plurality of cycles includes a deposition step, a clear step, and an etch step.

Description

Attorney Docket No. 12146-1 WOHDP Ref. No. 15545-001310-WO-POAETCHING THROUGH SILICON VIAS HAVING DIFFERENT SIZES WITH MINIMUM DEPTH LOADINGCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of U.S. Provisional Application No.63 / 707,482 filed on October 15, 2024. The entire disclosure of the above application is incorporated herein by reference.FIELD

[0002] The present disclosure relates to substrate processing systems, and more particularly to substrate processing systems configured to etch through silicon vias having different sizes in the same substrate and at the same time with minimum depth loading.BACKGROUND

[0003] The background description provided here is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.

[0004] During manufacturing of substrates such as semiconductor wafers, deposition and etch processes may be performed within a processing chamber. The substrate is arranged in the processing chamber on a substrate support such as an electrostatic chuck (ESC) or a pedestal. Process gases are introduced via a gas distribution device and plasma is struck in the processing chamber to enhance chemical reactions. Some substrate processing systems may be configured to etch high aspect ratio (HAR) through silicon vias (TSVs) using a rapid alternating process (RAP). During RAP, the substrate processing system rapidly switches between deposition, clear, and etch steps.SUMMARY

[0005] A method for etching a substrate includes providing a substrate including a silicon layer, a dielectric layer, and a mask layer defining a first set of through silicon vias (TSVs) and a second set of TSVs with a first critical dimension (CD) and a second CD, respectively. The first CD and the second CD are different. The method includesAttorney Docket No. 12146-1 WOHDP Ref. No. 15545-001310-WO-POA depositing a silicon oxide layer using a nonconformal deposition process to provide reverse loading in one of the first set of TSVs and the second set of TSVs corresponding to a larger one of the first CD and the second CD; and performing a rapid alternating process including a plurality of cycles. Each of the plurality of cycles includes a deposition step, a clear step, and an etch step.

[0006] In other features, the method includes setting a pressure in a processing chamber during the nonconformal deposition process in a range from 10 to 70 millitorr (mT). The method includes setting a pressure in a processing chamber during the nonconformal deposition process in a range from 35 to 50 millitorr (mT). The method includes providing a radio frequency (RF) bias to a substrate support during the nonconformal deposition process in a range from 0V to 600V. The method includes providing the RF bias to the substrate support during at least a portion of the rapid alternating process.

[0007] In other features, the silicon oxide layer is porous and erodible.

[0008] In other features, the method includes supplying a silicon-based precursor gas and an oxygen-based process gas during the nonconformal deposition process of the silicon oxide layer. The silicon-based precursor gas is selected from a group consisting of silicon tetrafluoride (SiF4), silicon tetrachloride (SiCk), and silane (SiFU). The oxygenbased process gas is selected from a group consisting of molecular oxygen (O2) and nitrous oxide (N2O).

[0009] In other features, the deposition step of the rapid alternating process includes depositing a fluorocarbon polymer layer. The fluorocarbon polymer layer is deposited using a conformal deposition process. The method includes depositing the silicon oxide layer and the rapid alternating process are performed in a single processing chamber. The method includes depositing the silicon oxide layer and the rapid alternating process are performed in different processing chambers. A ratio of a first flow rate of the oxygenbased process gas to a second flow rate of the silicon-based precursor gas is in a range from 1 :1 to 5:1 .

[0010] A substrate processing system for etching a substrate includes a processing chamber including a substrate support configured to support a substrate. The substrate includes a silicon layer, a dielectric layer, and a mask layer defining a first set of through silicon vias (TSVs) and a second set of TSVs with a first critical dimension (CD) and a second CD, respectively. The first CD and the second CD are different. The substrateAttorney Docket No. 12146-1 WOHDP Ref. No. 15545-001310-WO-POA processing system includes a dielectric window. A coil is arranged outside of the processing chamber adjacent to the dielectric window. A controller is configured to deposit a silicon oxide layer using a nonconformal deposition process to provide reverse loading in one of the first set of TSVs and the second set of TSVs corresponding to a larger one of the first CD and the second CD; and perform a rapid alternating process including a plurality of cycles. Each of the plurality of cycles includes a deposition step, a clear step, and an etch step.

[0011] In other features, the controller is configured to set a pressure in a processing chamber during the nonconformal deposition process of the silicon oxide layer in a range from 10 to 70 millitorr (mT). The controller is configured to set a pressure in a processing chamber during the nonconformal deposition process of the silicon oxide layer in a range from 35 to 50 millitorr (mT).

[0012] In other features, a radio frequency (RF) source is configured to selectively supply an RF bias to the substrate support. The RF bias is in a range from 0V to 600V. The controller is configured to provide the RF bias to the substrate support during at least a portion of the rapid alternating process.

[0013] In other features, the controller is configured supplying a silicon-based precursor gas and an oxygen-based process gas using a gas delivery system during the nonconformal deposition process of the silicon oxide layer. The silicon-based precursor gas is selected from a group consisting of silicon tetrafluoride (SiF4), silicon tetrachloride (SiCk), and silane (SiFU). The oxygen-based process gas is selected from a group consisting of molecular oxygen (O2) and nitrous oxide (N2O).

[0014] In other features, the controller is configured to deposit a fluorocarbon polymer layer during the rapid alternating process. The controller is configured to deposit the fluorocarbon polymer layer using a conformal deposition process. The controller is configured to supply a ratio of a first flow rate of the oxygen-based process gas to a second flow rate of the silicon-based precursor gas in a range from 1 :1 to 5:1 .

[0015] In other features, the silicon oxide layer is porous and erodible.

[0016] Further areas of applicability of the present disclosure will become apparent from the detailed description, the claims, and the drawings. The detailed description and specific examples are intended for purposes of illustration only and are not intended to limit the scope of the disclosure.Attorney Docket No. 12146-1 WOHDP Ref. No. 15545-001310-WO-POABRIEF DESCRIPTION OF THE DRAWINGS

[0017] The present disclosure will become more fully understood from the detailed description and the accompanying drawings, wherein:

[0018] FIGS. 1A to 1 C are side cross sections of an example of a substrate including through silicon vias (TSVs) having different critical dimensions after deposition of a conformal fluorocarbon polymer layer, after a clearing step, and after etching;

[0019] FIG. 2A is a plan view of an example of a mask layer for etching through silicon vias (TSVs) in a substrate;

[0020] FIG. 2B is a side cross section of an example of a substrate illustrating depth loading of the through silicon vias after a rapid alternating process;

[0021] FIG. 3A is a plan view of an example of a mask layer for etching through silicon vias (TSVs) in a substrate;

[0022] FIG. 3B is a side cross section of an example of a substrate illustrating depth loading of the through silicon vias after deposition of a non-conformal silicon oxide layer and a rapid alternating process according to the present disclosure;

[0023] FIG. 4 is a side cross section of an example of a substrate illustrating the non- conformal silicon oxide film deposited on the substrate prior to the rapid alternating process according to the present disclosure;

[0024] FIG. 5 is a functional block diagram of an example of a substrate processing system for depositing the non-conformal silicon oxide film and etching the substrate using a rapid alternating process according to the present disclosure; and

[0025] FIG. 6 is a flowchart of an example of a method for depositing the non-conformal silicon oxide layer and using a rapid alternating process to etch the substrate; and

[0026] FIG. 7 is a flowchart of an example of a method for depositing the non-conformal silicon oxide layer before and in between cycles of a rapid alternating process.

[0027] In the drawings, reference numbers may be reused to identify similar and / or identical elements.DETAILED DESCRIPTION

[0028] In some advanced packaging applications for manufacturing semiconductor devices, a substrate may include through silicon vias (TSVs) having two or more differentAttorney Docket No. 12146-1 WOHDP Ref. No. 15545-001310-WO-POA critical dimensions (CDs) that need to be etched at the same time. The amount of depth loading at various etching depth targets is typically limited due to the process margin requirements for subsequent processing steps. Aspect ratio dependent etching (ARDE) processes or reaction ion etching (RIE) with lag are typically used when etching TSVs.

[0029] Higher etch rates occur in TSVs with larger CDs as compared to TSVs with smaller CDs when using these processes. When the TSVs are etched at the same time, depth loading occurs. In other words, the TSVs with the larger CDs are etched deeper than the TSVs with smaller CDs. There are limits on the amount of depth loading that occur due to process margins of the subsequent steps.

[0030] Some conventional TSV etching methods rely on using a rapid alternating process including hundreds of cycles each including a deposition step, a clear step, and an etch step. During the deposition step, a conformal layer of film (e.g., a fluorocarbon (CFx) polymer layer) is deposited. However, a trade-off is required between depth loading and profile verticality when using this approach which may not be suitable for some applications.

[0031] The present disclosure relates to a method for etching through silicon vias (TSVs) having two or more different critical dimensions (CDs) in a single silicon layer at the same time while minimizing depth loading. In some examples, the first and second CDs of the TSVs are in a range from ~2 pm to ~7 pm, although other CDs may be used. Minimal depth loading at various depth targets is required due to the process margins of the subsequent processing steps.

[0032] The etching method for TSVs according to the present disclosure includes depositing a nonconformal silicon oxide (SiOx) layer using a gas mixture including a silicon-based precursor gas and an oxygen-based process gas. In some examples, the silicon-based precursor gas is selected from a group consisting of silicon tetrafluoride (SiF4), silicon tetrachloride (SiCk), and silane (SiH4), although other silicon-based precursor gases may be used. In some examples, the oxygen-based process gas is selected from a group consisting of molecular oxygen (O2) and nitrous oxide (N2O), although other oxygen-based process gases can be used.

[0033] The nonconformal silicon oxide layer is deposited on a top surface of the substrate and on side walls and bottom surfaces of first and second TSVs having first and second CDs, respectively. The first CD is greater than the second CD. Then, the rapid alternating process (RAP) is performed. The RAP includes a plurality of cycles eachAttorney Docket No. 12146-1 WOHDP Ref. No. 15545-001310-WO-POA including deposition, clear, and etch steps. In some examples, the deposition of the silicon oxide layer and the rapid alternating process are performed in the same processing chamber (e.g., an inductively coupled plasma (ICP) substrate processing system) as described further below. In other examples, the deposition of the silicon oxide layer and the rapid alternating process are performed in different processing chambers.

[0034] In some examples, the first CD of the first TSVs is greater than the second CD of the second TSVs. Due to the different CDs, the silicon oxide film that is deposited at the bottom of the first TSVs is thicker than the silicon oxide film deposited in the second TSVs. As a result, the thicker film in the first TSVs is reverse loaded to compensate for ARDE-induced depth loading that occurs during the rapid alternating process that follows. As a result, the method described herein minimizes the final depth loading after RAP. Mask selectivity is also improved by the silicon oxide layer since the silicon oxide layer deposited on the top surface is etched before a mask or photoresist layer.

[0035] The method described herein enables etching of TSVs with different CDs in single layer at the same time while meeting depth loading requirements for processing steps after RAP. The method provides an efficient and low-cost integration solution as compared to other methods that require additional fabrication steps.

[0036] Referring now to FIGS. 1 A to 1 C, a single cycle of a rapid alternating process (RAP) is shown to include a deposition step, a clear step, and an etch step. In this example, the substrate 10 includes a silicon layer 16, a dielectric layer 17, and a mask layer 18. The substrate 10 includes first and second through silicon vias (TSVs) 12 and 14 have first and second critical dimensions (CDi and CD2), respectively, where CD1 > CD2. In FIG. 1 A, a film 20 such as a fluorocarbon (CFx) polymer film is deposited onto the substrate 10 using a conformal deposition process. In other words, the film 20 has a uniform thickness on the top surface, side walls, and in the trench.

[0037] In FIG. 1 B, a clear step is shown. Some of the film 20 is etched to clear an etch front located on a bottom surface of the second TSVs 14. In FIG. 10, an etch phase is shown. The etching is predominantly in a downward direction due to cleared etch front and the remaining film 20 on the side walls.

[0038] In the example shown in FIGS. 1 A to 1 C, the TSVs 12 and 14 are shown to have the same depth after the RAP cycle. However, the etch processes that are typically used (e.g., aspect ratio dependent etching (ARDE) or reactive ion etch with lag) have etchAttorney Docket No. 12146-1 WOHDP Ref. No. 15545-001310-WO-POA rates that depend upon the CD of the TSV. In other words, higher etch rates occur in the TSVs with larger CDs, which increases depth loading.

[0039] Referring now to FIGS. 2A and 2B and FIGS. 3A and 3B, differences in depth loading are shown. In FIGS. 2A and 2B, the rapid alternating process without depositing the nonconformal silicon oxide layer is shown. In FIGS. 3A and 3B, the method according to the present disclosure includes depositing the nonconformal silicon oxide layer and the rapid alternating process. In FIGS. 2A and 2B, a substrate 40 includes a silicon-based layer 44, a dielectric layer 46 (e.g., silicon oxide (SiOx)), and a mask layer 48. Through silicon vias (TSVs) 52 and 54 are defined in the silicon-based layer 44 using the mask layer 48. The TSVs 52 and 54 have first and second critical dimensions (CDi and CD2), respectively, where CD1 > CD2.

[0040] During each RAP cycle, the polymer layer (CFx) is deposited conformally into the TSVs 52 and 54 and on a top surface of the layer of silicon-based layer 44. During subsequent clearing and etching steps over multiple RAP cycles, depth loading increases. Depth loading refers to the difference between the depth of the TSVs 52 and 54 after etching. As can be seen, a bottom surface 62 of the TSV 52 is etched deeper than a bottom surface of the TSV 54.

[0041] In FIGS. 3A and 3B, a substrate 80 is shown after processing including depositing the nonconformal silicon oxide layer and the rapid alternating process. The substrate 80 includes a silicon-based layer 84, a dielectric layer 86, and a mask layer 88. Through silicon vias (TSVs) 92 and 94 are defined in the silicon-based layer 84 using the mask layer 88. The TSVs 92 and 94 have first and second critical dimensions (CDi and CD2), respectively, where CDi > CD2.

[0042] The silicon oxide layer is deposited onto side walls and a bottom surface of the TSVs 92 and 94 and on a top surface of the substrate. After the rapid alternating process cycles, depth loading is minimal since the nonconformal silicon oxide layer reverse loads the TSVs. As can be seen, a bottom surface 98 of the TSV 92 is shown only slightly deeper than a bottom surface 96 of the TSV 94 and less than the depth loading in FIGS. 2A and 2B. Loading is minimized in response to the nonconformal silicon oxide layer that is deposited before the RAP.

[0043] Referring now to FIG. 4, the substrate 80 including the TSVs 92 and 94 is shown. The TSVs 92 and 94 have first and second critical dimensions (CDi and CD2), respectively, where CDi > CD2. A silicon oxide (SiOx) layer 100 is deposited into theAttorney Docket No. 12146-1 WOHDP Ref. No. 15545-001310-WO-POATSVs 92 and 94 and on a top surface 102 of the silicon-based layer 44. Process conditions are controlled to deposit thesilicon oxide layer 100 with different thicknesses of di at the bottom surface of the TSV 92, cfc at the bottom surface of the TSV 94, and ch on the top surface 102. In some examples, the silicon oxide layer 100 is deposited thicker on the top surface and in the trench as compared to the side walls.

[0044] Once the silicon oxide layer 100 is deposited, the rapid alternating process can begin. As can be appreciated, the deposition of the silicon oxide layer and the rapid alternating process are performed in the same processing chamber (e.g., an inductively coupled plasma (ICP) substrate processing system) as described further below. In other examples, the deposition of the silicon oxide layer and the rapid alternating process are performed in different processing chambers.

[0045] In some examples, the nonconformal silicon oxide layer is deposited and the substrate is processed using the rapid alternating process. In other examples, the nonconformal silicon oxide layer is deposited before the RAP begins and then deposited again one or more times between cycles of the RAP.

[0046] Additionally, the nonconformal silicon oxide (SiOx) layer may be porous and erodible. In such examples, the porosity and erodibility of the nonconformal silicon oxide layer may be due to, for example, a gas flow rate and / or a pressure during silicon oxide deposition for the etching process, as disclosed herein. In some examples, the gas flow rate and / or the pressure during the deposition of the nonconformal silicon oxide layer may be based on the characteristics of a substrate processing system undertaking the etching process. With this porous characteristic, the silicon oxide (SiOx) layer formed using a gas mixture including a silicon-based precursor gas and an oxygen-based process gas (as explained above) has a low density (e.g., lower than a density of silicon dioxide (SiO2)).

[0047] With this porosity and erodibility, the silicon oxide (SiOx) layer enables the etching process to take place while also minimizing depth loading without risk of etch stop over the silicon oxide layer. The silicon oxide layer may be etched during the silicon RAP process, facilitating subsequent integration steps and resulting in depth loading minimization. Further, as the silicon oxide layer is erodible, deposition of the silicon oxide layer does not have an impact on the mask layer (e.g., the mask layer 88 of FIG. 4) positioned below the silicon oxide layer. Instead, the silicon oxide layer increasesAttorney Docket No. 12146-1 WOHDP Ref. No. 15545-001310-WO-POA selectivity of the etching process since the silicon oxide layer is deposited on top of the mask layer.

[0048] Referring now to FIG. 5, an example of a substrate processing system 108 according to some embodiments of the present disclosure is shown. The substrate processing system 108 performs an inductively coupled plasma (ICP) process and includes a coil driving circuit 1 1 1. The coil driving circuit 1 1 1 includes an RF source 1 12 and a tuning circuit 1 13. The tuning circuit 1 13 may be directly connected to one or more inductive transformer coupled plasma (TCP) coils 1 16. In some examples, the TCP coils 1 16 include an inner coil arranged inside of an outer coil. The tuning circuit 1 13 may be connected by a reversing circuit 1 15 to one or more of the coils 1 16. The tuning circuit 1 13 tunes an output of the RF source 1 12 to a desired frequency and / or a desired phase, matches an impedance of the TCP coils 1 16, and splits power between the TCP coils 1 16. The reversing circuit 115 is used to selectively switch the polarity of current through one or more of the TCP coils 116. In some examples, the coil driving circuit 11 1 implements a transformer coupled capacitive tuning (TCCT) circuit to drive the TCP coils 1 16 with different power levels.

[0049] A gas distribution assembly 1 18 includes a showerhead (e.g., a gas plate) 120 and a dielectric window 124. In some embodiments, a plenum may be defined between the gas plate 120 and the dielectric window 124. The gas plate 120 is arranged between the dielectric window 124 and a processing chamber 128. In some examples, the dielectric window 124 is made of ceramic. In some embodiments, the gas plate 120 comprises ceramic or another dielectric material. The processing chamber 128 further comprises a substrate support 132 (or pedestal). The substrate support 132 may include an electrostatic chuck (ESC), or a mechanical chuck or other type of chuck.

[0050] In operation, a process gas is supplied to the processing chamber 128 via the gas plate 120 (e.g., a plurality of holes passing through the gas plate). The TCP coils 1 16 generate a varying magnetic field inside of the processing chamber 128 that ignites the plasma 140. The magnetic field excites gas molecules within the processing chamber 128 to generate the plasma 140. The plasma 140 etches exposed surfaces of the substrate 134. An RF source 150 and a bias matching circuit 152 may be used to bias the substrate support 132 during operation to control ion energy. In some examples, the RF source 150 and the bias matching circuit 152 are not used during deposition of the nonconformal silicon oxide layer.Attorney Docket No. 12146-1 WOHDP Ref. No. 15545-001310-WO-POA

[0051] A gas delivery system 156 may be used to supply a process gas mixture to the processing chamber 128. The gas delivery system 156 may include precursor, process, and / or inert gas sources 157 (e.g., including deposition gases, etch gases, carrier gases, inert gases, etc.), gas metering systems 158-1 and 158-2 such as valves and flow ratio controllers (e.g., mass flow controllers (MFCs)), and respective manifolds 159-1 and 159- 2. For example, the etch and deposition gas mixtures may be provided to the plenums of the gas plate 120 through the TCP coil 1 16 and via respective passages in the dielectric window 124.

[0052] A heater / cooler 164 may be used to heat / cool the substrate support 132 to a predetermined temperature. An exhaust system 165 includes a valve 166 and pump 167 to remove reactants from the processing chamber 128 by purging or evacuation.

[0053] A controller 154 may be used to control the etching process. The controller 154 monitors system parameters and controls delivery of the process gas mixtures, striking, maintaining, and extinguishing the plasma, removal of reactants, control pressure in the processing chamber, flow rates of precursor and process gases, and so on. Additionally, the controller 154 may control various aspects of the coil driving circuit 1 1 1 , the RF source 150, and the bias matching circuit 152, etc. In some embodiments, the substrate support 132 is temperature-tunable. In certain embodiments, a temperature controller 168 may be connected to a plurality of heating elements 170, such as thermal control elements (TCEs), arranged in the substrate support 132. The temperature controller 168 may be used to control the plurality of heating elements 170 to control a temperature of the substrate support 132 and the substrate 134. The gas distribution assembly 1 18 according to certain embodiments of the present disclosure includes a carrier ring 190 arranged between the gas plate 120 and a body of the processing chamber 128.

[0054] In some examples, the silicon oxide deposition step is performed at a pressure in a range from 10 to 70 millitorr (mT). In some examples, the silicon oxide deposition step is performed at a pressure in a range from 35 to 50 mT. Use of the lower pressure corresponds to an increased mean free path. In some examples, the pressure in the processing chamber is increased during the rapid alternating process. In some examples, the pressure in the processing chamber during the rapid alternating process is greater than 1 .5 times (e.g., 2 times) the pressure during silicon oxide deposition, although other pressures can be used.Attorney Docket No. 12146-1 WOHDP Ref. No. 15545-001310-WO-POA

[0055] In some examples, nonconformal silicon oxide deposition is selectively performed with a DC and / or RF bias (with an amplitude in a range from 0V to 600V) supplied to the substrate support. In some examples, the oxygen-based process gas is suppled at a flow rate that is greater than or equal to the flow rate of the silicon-based precursor gas. In some examples, a ratio of the flow rate of the oxygen-based process gas to the flow rate of the silicon-based precursor gas is in a range from 1 :1 to 5:1 . In some examples, a ratio of the flow rate of the oxygen-based process gas to the flow rate of the silicon-based precursor gas is in a range from 1.5:1 to 3:1 (e.g., 2:1 ). The silicon oxide film deposition does not impact the mask layer.

[0056] Referring now to FIG. 6, a method 200 for etching through silicon vias according to the present disclosure is shown. A substrate including mask defining two or more sets of TSVs having two or more different CDs is provided at 210. A nonconformal silicon oxide layer is deposited on the substrate to provide reverse loading in the TSVs with higher CDs at 214. Then, a rapid alternating process (RAP) including multiple cycles each including deposition, clear, and etch steps is performed at 218.

[0057] Referring now to FIG. 7, a method 250 for etching a substrate including two or more sets of TSVs having two or more different CDs according to the present disclosure is shown. In this example, the nonconformal silicon oxide layer is deposited before the rapid alternating process and one or more times between cycles of the rapid alternating process.

[0058] A substrate including mask defining two or more sets of TSVs having different CDs is provided at 260. A first nonconformal silicon oxide layer is deposited on the substrate (to provide reverse loading) at 264. 1stto Nthcycles of a rapid alternating process including M cycles (each including deposition, clear, and etch steps) are performed at 268 (where N and M are integers and N < M). A second nonconformal silicon oxide layer is deposited using nonconformal deposition on the substrate to provide reverse loading in the TSVs with higher CDs at 272. (N+1 ) to Mthcycles of a rapid alternating process including M cycles (each including deposition, clear, and etch steps) are performed at 276.

[0059] The foregoing description is merely illustrative in nature and is in no way intended to limit the disclosure, its application, or uses. The broad teachings of the disclosure can be implemented in a variety of forms. Therefore, while this disclosure includes particular examples, the true scope of the disclosure should not be so limited since otherAttorney Docket No. 12146-1 WOHDP Ref. No. 15545-001310-WO-POA modifications will become apparent upon a study of the drawings, the specification, and the following claims. It should be understood that one or more steps within a method may be executed in different order (or concurrently) without altering the principles of the present disclosure. Further, although each of the embodiments is described above as having certain features, any one or more of those features described with respect to any embodiment of the disclosure can be implemented in and / or combined with features of any of the other embodiments, even if that combination is not explicitly described. In other words, the described embodiments are not mutually exclusive, and permutations of one or more embodiments with one another remain within the scope of this disclosure.

[0060] Spatial and functional relationships between elements (for example, between modules, circuit elements, semiconductor layers, etc.) are described using various terms, including “connected,” “engaged,” “coupled,” “adjacent,” “next to,” “on top of,” “above,” “below,” and “disposed.” Unless explicitly described as being “direct,” when a relationship between first and second elements is described in the above disclosure, that relationship can be a direct relationship where no other intervening elements are present between the first and second elements, but can also be an indirect relationship where one or more intervening elements are present (either spatially or functionally) between the first and second elements. As used herein, the phrase at least one of A, B, and C should be construed to mean a logical (A OR B OR C), using a non-exclusive logical OR, and should not be construed to mean “at least one of A, at least one of B, and at least one of C.”

[0061] In some implementations, a controller is part of a system, which may be part of the above-described examples. Such systems can comprise semiconductor processing equipment, including a processing tool or tools, chamber or chambers, a platform, or platforms for processing, and / or specific processing components (a wafer pedestal, a gas flow system, etc.). These systems may be integrated with electronics for controlling their operation before, during, and after processing of a semiconductor wafer or substrate. The electronics may be referred to as the “controller,” which may control various components or subparts of the system or systems. The controller, depending on the processing requirements and / or the type of system, may be programmed to control any of the processes disclosed herein, including the delivery of processing gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, positional and operation settings, waferAttorney Docket No. 12146-1 WOHDP Ref. No. 15545-001310-WO-POA transfers into and out of a tool and other transfer tools and / or load locks connected to or interfaced with a specific system.

[0062] Broadly speaking, the controller may be defined as electronics having various integrated circuits, logic, non-transitory memory, and / or software that receive instructions, issue instructions, control operation, enable cleaning operations, enable endpoint measurements, and the like. The integrated circuits may include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and / or one or more microprocessors, or microcontrollers that execute program instructions (e.g., software). Program instructions may be instructions communicated to the controller in the form of various individual settings (or program files), defining operational parameters for carrying out a particular process on or for a semiconductor wafer or to a system. The operational parameters may, in some embodiments, be part of a recipe defined by process engineers to accomplish one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0063] The controller, in some implementations, may be a part of or coupled to a computer that is integrated with the system, coupled to the system, otherwise networked to the system, or a combination thereof. For example, the controller may be in the “cloud” or all or a part of a fab host computer system, which can allow for remote access of the wafer processing. The computer may enable remote access to the system to monitor current progress of fabrication operations, examine a history of past fabrication operations, examine trends or performance metrics from a plurality of fabrication operations, to change parameters of current processing, to set processing steps to follow a current processing, or to start a new process. In some examples, a remote computer (e.g., a server) can provide process recipes to a system over a network, which may include a local network or the Internet. The remote computer may include a user interface that enables entry or programming of parameters and / or settings, which are then communicated to the system from the remote computer. In some examples, the controller receives instructions in the form of data, which specify parameters for each of the processing steps to be performed during one or more operations. It should be understood that the parameters may be specific to the type of process to be performed and the type of tool that the controller is configured to interface with or control. Thus, as described above, the controller may be distributed, such as by comprising one or more discrete controllers that are networked together and working towards a common purpose, suchAttorney Docket No. 12146-1 WOHDP Ref. No. 15545-001310-WO-POA as the processes and controls described herein. An example of a distributed controller for such purposes would be one or more integrated circuits on a chamber in communication with one or more integrated circuits located remotely (such as at the platform level or as part of a remote computer) that combine to control a process on the chamber.

[0064] Without limitation, example systems may include a plasma etch chamber or module, a deposition chamber or module, a spin-rinse chamber or module, a metal plating chamber or module, a clean chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an atomic layer deposition (ALD) chamber or module, an atomic layer etch (ALE) chamber or module, an ion implantation chamber or module, a track chamber or module, and any other semiconductor processing systems that may be associated or used in the fabrication and / or manufacturing of semiconductor wafers.

[0065] As noted above, depending on the process step or steps to be performed by the tool, the controller might communicate with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout a factory, a main computer, another controller, or tools used in material transport that bring containers of wafers to and from tool locations and / or load ports in a semiconductor manufacturing factory.

Claims

Attorney Docket No. 12146-1 WOHDP Ref. No. 15545-001310-WO-POACLAIMSWhat is claimed is:1 . A method for etching a substrate, comprising: providing a substrate including a silicon layer, a dielectric layer, and a mask layer defining a first set of through silicon vias (TSVs) and a second set of TSVs with a first critical dimension (CD) and a second CD, respectively, wherein the first CD and the second CD are different; depositing a silicon oxide layer using a nonconformal deposition process to provide reverse loading in one of the first set of TSVs and the second set of TSVs corresponding to a larger one of the first CD and the second CD; and performing a rapid alternating process including a plurality of cycles, wherein each of the plurality of cycles includes a deposition step, a clear step, and an etch step.

2. The method of claim 1 , further comprising setting a pressure in a processing chamber during the nonconformal deposition process in a range from 10 to 70 millitorr (mT).

3. The method of claim 1 , further comprising setting a pressure in a processing chamber during the nonconformal deposition process in a range from 35 to 50 millitorr (mT).

4. The method of claim 1 , further comprising providing a radio frequency (RF) bias to a substrate support during the nonconformal deposition process in a range from 0V to 600V.

5. The method of claim 4, further comprising providing the RF bias to the substrate support during at least a portion of the rapid alternating process.

6. The method of claim 1 , further comprising supplying a silicon-based precursor gas and an oxygen-based process gas during the nonconformal deposition process of the silicon oxide layer.Attorney Docket No. 12146-1 WOHDP Ref. No. 15545-001310-WO-POA7. The method of claim 6, wherein the silicon-based precursor gas is selected from a group consisting of silicon tetrafluoride (SiF4), silicon tetrachloride (SiCk), and silane (SiH4).

8. The method of claim 6, wherein the oxygen-based process gas is selected from a group consisting of molecular oxygen (O2) and nitrous oxide (N2O).

9. The method of claim 1 , wherein the deposition step of the rapid alternating process includes depositing a fluorocarbon polymer layer.

10. The method of claim 9, wherein the fluorocarbon polymer layer is deposited using a conformal deposition process.

11. The method of claim 1 , wherein depositing the silicon oxide layer and the rapid alternating process are performed in a single processing chamber.

12. The method of claim 1 , wherein depositing the silicon oxide layer and the rapid alternating process are performed in different processing chambers.

13. The method of claim 7, wherein a ratio of a first flow rate of the oxygen-based process gas to a second flow rate of the silicon-based precursor gas is in a range from 1 :1 to 5:1.

14. The method of claim 1 , wherein the silicon oxide layer is porous and erodible.Attorney Docket No. 12146-1 WOHDP Ref. No. 15545-001310-WO-POA15. A substrate processing system for etching a substrate, comprising: a processing chamber including a substrate support configured to support a substrate, wherein the substrate includes a silicon layer, a dielectric layer, and a mask layer defining a first set of through silicon vias (TSVs) and a second set of TSVs with a first critical dimension (CD) and a second CD, respectively, and wherein the first CD and the second CD are different; a dielectric window; and a coil arranged outside of the processing chamber adjacent to the dielectric window; and a controller configured to: deposit a silicon oxide layer using a nonconformal deposition process to provide reverse loading in one of the first set of TSVs and the second set of TSVs corresponding to a larger one of the first CD and the second CD; and perform a rapid alternating process including a plurality of cycles, wherein each of the plurality of cycles includes a deposition step, a clear step, and an etch step.

16. The substrate processing system of claim 15, wherein the controller is configured to set a pressure in a processing chamber during the nonconformal deposition process of the silicon oxide layer in a range from 10 to 70 millitorr (mT).

17. The substrate processing system of claim 15, wherein the controller is configured to set a pressure in a processing chamber during the nonconformal deposition process of the silicon oxide layer in a range from 35 to 50 millitorr (mT).

18. The substrate processing system of claim 15, further comprising a radio frequency (RF) source configured to selectively supply an RF bias to the substrate support, wherein the RF bias is in a range from 0V to 600V.

19. The substrate processing system of claim 18, wherein the controller is configured to provide the RF bias to the substrate support during at least a portion of the rapid alternating process.Attorney Docket No. 12146-1 WOHDP Ref. No. 15545-001310-WO-POA20. The substrate processing system of claim 15, further comprising: a gas delivery system, wherein the controller is configured supplying a silicon-based precursor gas and an oxygen-based process gas using the gas delivery system during the nonconformal deposition process of the silicon oxide layer.21 . The substrate processing system of claim 20, wherein the silicon-based precursor gas is selected from a group consisting of silicon tetrafluoride (SiF4), silicon tetrachloride (SiCk), and silane (SiH4).

22. The substrate processing system of claim 20, wherein the oxygen-based process gas is selected from a group consisting of molecular oxygen (O2) and nitrous oxide (N2O).

23. The substrate processing system of claim 15, wherein the controller is configured to deposit a fluorocarbon polymer layer during the rapid alternating process.

24. The substrate processing system of claim 23, wherein the controller is configured to deposit the fluorocarbon polymer layer using a conformal deposition process.

25. The substrate processing system of claim 20, wherein the controller is configured to supply a ratio of a first flow rate of the oxygen-based process gas to a second flow rate of the silicon-based precursor gas in a range from 1 :1 to 5:1 .

26. The substrate processing system of claim 15, wherein the silicon oxide layer is porous and erodible.

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