HBC cell, cell assembly and photovoltaic system

Abstract

The present disclosure is applicable to the technical field of photovoltaics. Provided are an HBC cell, a cell assembly and a photovoltaic system. The HBC cell comprises: a silicon substrate, wherein the silicon substrate has a rear surface and a light-facing surface that are disposed opposite each other, first regions and second regions are alternately disposed on the rear surface of the silicon substrate, the first regions are polished regions, and the second regions are textured regions; and a first passivation layer, a first doped layer, a first conductive film layer and a first electrode that are stacked in sequence in each first region, and a second passivation layer, a second doped layer, a second conductive film layer and a second electrode that are stacked in sequence in each second region, wherein the first doped layer and the second doped layer are of different types, the first conductive film layer is not in communication with the second conductive film layer, and the width of the first electrode is less than the width of the second electrode. Increasing the width of a second electrode can improve the internal back-reflection capability of front incident light, thereby helping to improve the current output. The effect of contact resistance is reduced, thereby improving the transport efficiency of carriers.

Description

An HBC battery, battery module and photovoltaic system

[0001] Priority information

[0002] This disclosure claims priority to Chinese patent application No. 202422545379.6, filed on October 21, 2024, with the State Intellectual Property Office of China, entitled “An HBC Battery, Battery Module and Photovoltaic System”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure belongs to the field of photovoltaic technology, and in particular relates to an HBC cell, a cell module and a photovoltaic system. Background Technology

[0004] Significant progress has been made in existing HBC (Heterojunction with Back Contact) cells compared to BC (Back Contact) cells, but some technical problems still exist, which limit further improvements in photoelectric conversion efficiency and reductions in manufacturing costs.

[0005] Existing HBC solar cells have limitations in light reflection and absorption, contact resistance, and long-wavelength light response. Although textured surfaces are used to reduce surface reflection, they are not effective in improving long-wavelength light absorption and internal back reflection, resulting in some light energy not being fully utilized. Furthermore, traditional electrode designs, due to insufficient width and high contact resistance, hinder carrier transport, increase series resistance, and reduce the fill factor (FF), thus affecting the overall photoelectric conversion efficiency. Simultaneously, the passivation and doping layers in different regions are not optimally combined, limiting performance improvements. Therefore, design optimization and process improvements are needed to enhance cell efficiency.

[0006] Utility Model Content

[0007] This disclosure provides an HBC battery designed to address the problems of increased carrier recombination rate and insufficient stability in existing HBC batteries.

[0008] This disclosure is implemented as follows: an HBC battery includes:

[0009] A silicon substrate has a backlight surface and a light-facing surface arranged opposite to each other. A first region and a second region are formed on the backlight surface of the silicon substrate. The first region is a polished region and the second region is a textured region. The first region and the second region are arranged alternately and do not overlap.

[0010] A first passivation layer, a first doped layer, and a first conductive film layer are sequentially stacked in a first region; a second passivation layer, a second doped layer, and a second conductive film layer are sequentially stacked in a second region; the first doped layer and the second doped layer are of different shapes; and the first conductive film layer and the second conductive film layer are not connected.

[0011] A first electrode is stacked on a first conductive film layer and a second electrode is stacked on a second conductive film layer, wherein the width of the first electrode is smaller than the width of the second electrode.

[0012] Optionally, the thickness of the first electrode is greater than the thickness of the second electrode.

[0013] Optionally, the second passivation layer and the second doped layer extend into the first region and are stacked on top of the first doped layer.

[0014] Optionally, the first passivation layer is a tunneling oxide layer, and the first doped layer is a doped polysilicon layer;

[0015] The second passivation layer is at least one of an intrinsic amorphous silicon layer or a tunneling oxide layer, and the second doped layer is at least one of a doped amorphous silicon layer and a doped microcrystalline silicon layer.

[0016] Optionally, the first doped layer is an N-type doped layer and the second doped layer is a P-type doped layer.

[0017] Optionally, the width of the second electrode is 10-300 μm.

[0018] Optionally, the difference between the width of the second electrode and the width of the first electrode is less than or equal to 50 μm.

[0019] Optionally, the thickness of the first electrode is 10-30 μm.

[0020] Optionally, the difference between the thickness of the first electrode and the thickness of the second electrode is less than or equal to 10 μm.

[0021] Optionally, the distance between the first electrode and the second electrode is 200-500 μm.

[0022] This disclosure also provides a battery assembly including the HBC battery described above.

[0023] This disclosure also provides a photovoltaic system including the aforementioned battery module.

[0024] The beneficial effects achieved by this disclosure are that the alternating polished and textured regions on the back surface of the silicon substrate optimize light reflection and absorption performance. The first and second regions are respectively covered with different types of passivation layers, doped layers, conductive films, and electrodes. Increasing the width of the second electrode improves the internal back reflection capability of front-incident light, especially enhancing the spectral response to long-wavelength light. This contributes to increased current output. Furthermore, a wider electrode contact surface reduces the influence of contact resistance, thereby improving carrier transport efficiency. This improvement reduces series resistance, thus increasing the fill factor (FF). Overall, these changes significantly improve the photoelectric conversion efficiency of the cell. Attached Figure Description

[0025] Figure 1 is a schematic diagram of the first structure of the HBC battery provided in this disclosure;

[0026] Figure 2 is a schematic diagram of a second structure of the HBC battery provided in this disclosure;

[0027] Figure 3 is a schematic diagram of the third structure of the HBC battery provided in this disclosure;

[0028] Figure 4 is a schematic diagram showing the electrode dimensions of the first structure of the HBC battery provided in this disclosure.

[0029] Explanation of reference numerals in the attached figures: 110, First region; 111, First passivation layer; 112, First doped layer; 113, First conductive film layer; 114, First electrode; 120, Second region; 121, Second passivation layer; 122, Second doped layer; 123, Second conductive film layer; 124, Second electrode; 130, Isolation region; 140, Silicon substrate. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this disclosure, and should not be construed as limiting this disclosure. Furthermore, it should be understood that the specific embodiments described herein are merely for explaining this disclosure and are not intended to limit this disclosure.

[0031] In the description of this disclosure, it should be understood that the terms “length”, “width”, “upper”, “lower”, “left”, “right”, “horizontal”, “top”, “bottom”, etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0032] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this disclosure, "a plurality of" means two or more, unless otherwise explicitly specified.

[0033] In the description of this disclosure, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0034] In this disclosure, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0035] The following disclosure provides numerous different embodiments or examples for implementing various structures of this disclosure. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the scope of this disclosure. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, various specific examples of processes and materials are provided in this disclosure, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0036] This disclosure describes an alternating polished and textured region on the back surface of a silicon substrate, which optimizes light reflection and absorption performance. The first and second regions are respectively covered with different types of passivation layers, doped layers, conductive films, and electrodes. Increasing the width of the second electrode improves the internal back reflection capability of front-incident light, especially enhancing the spectral response to long-wavelength light. This contributes to improved current output. Furthermore, a wider electrode contact surface reduces the impact of contact resistance, thereby improving carrier transport efficiency. This improvement reduces series resistance, thus increasing the fill factor (FF). Overall, these changes significantly improve the photoelectric conversion efficiency of the cell.

[0037] Example 1

[0038] As shown in Figure 1, this embodiment provides an HBC battery, including:

[0039] A silicon substrate 140 has a backlight surface and a light-facing surface arranged opposite to each other. A first region 110 and a second region 120 are provided on the backlight surface of the silicon substrate 140. The first region 110 is a polished region and the second region 120 is a textured region. The first region 110 and the second region 120 are arranged alternately and do not overlap.

[0040] A first passivation layer 111, a first doped layer 112, and a first conductive film layer 113 are sequentially stacked in the first region 110; a second passivation layer 121, a second doped layer 122, and a second conductive film layer 123 are sequentially stacked in the second region 120; the first doped layer 112 and the second doped layer 122 are of different shapes; and the first conductive film layer 113 and the second conductive film layer 123 are not connected.

[0041] The first electrode 114 is stacked on the first conductive film layer 113 and the second electrode 124 is stacked on the second conductive film layer 123. The width of the first electrode 114 is smaller than the width of the second electrode 124.

[0042] The difference between the first doped layer 112 and the second doped layer 122 refers to the different doping types of the first doped layer 112 and the second doped layer 122.

[0043] HBC (Heterojunction with Back Contact) solar cells are a type of solar cell with a heterojunction structure and a back-contact design. They combine the advantages of different materials to improve photoelectric conversion efficiency. The heterojunction, formed on the back of the cell, is composed of different types of silicon materials (typically amorphous and polycrystalline silicon), which enhances the cell's performance.

[0044] The silicon substrate 140 has two main surfaces: a light-facing surface and a back-lighting surface. The light-facing surface directly faces the sunlight, while the back-lighting surface is on the opposite side. The two surfaces are positioned opposite each other.

[0045] Two distinct regions, a first region 110 and a second region 120, are arranged alternately on the backlight surface of the silicon substrate 140. Specifically, a plurality of first regions 110 and a plurality of second regions 120 are arranged alternately along a first direction, and both the first regions 110 and 120 extend along a second direction, which intersects the first direction. The first regions 110 and 120 can be arranged alternately along the lateral direction of the silicon substrate 140 and both extend along the longitudinal direction; that is, the first direction can be the lateral direction of the back contact battery, and the second direction can be the longitudinal direction of the back contact battery, and the two are perpendicular to each other. Of course, in other embodiments, the first direction and the second direction can also be other directions, for example, they can be the diagonal directions of the silicon substrate 140, and no specific limitation is made here. The first regions 110 and 120 do not overlap each other, and the first regions 110 and 120 can be arranged adjacent to each other, or other regions can be arranged between the first regions 110 and 120.

[0046] A first passivation layer 111, a first doped layer 112, and a first conductive film layer 113 are sequentially stacked in the first region 110, with each first region 110 having the first passivation layer 111, the first doped layer 112, and the first conductive film layer 113 sequentially stacked. A second passivation layer 121, a second doped layer 122, and a second conductive film layer 123 are sequentially stacked in the second region 120, with each second region 120 having the second passivation layer 121, the second doped layer 122, and the second conductive film layer 123 sequentially stacked.

[0047] Both the first and second conductive films can be TCO films or other films that combine light transmission and conductivity. Both can be single films or multilayer composite films; no specific restrictions are imposed here.

[0048] Understandably, the second region 120 is a textured region, and the second passivation layer 121 is stacked on the textured region. The part of the second passivation layer 121 that faces away from the silicon substrate 140 can be textured. Furthermore, the part of the second doped layer 122 that faces away from the silicon substrate 140 that faces away from the textured region can be textured, and the part of the second conductive film layer 123 that faces away from the silicon substrate 140 that faces away from the textured region can be textured.

[0049] A first conductive film layer is stacked on a first doped layer and covers at least a portion of the first doped layer. A second conductive film layer is stacked on a second doped layer and covers at least a portion of the textured area corresponding to the second doped layer. The second conductive film layer and the first conductive film layer are provided with an insulating gap. Specifically, a gap may be provided between the second conductive film layer and the first conductive film layer, or an insulating medium may be provided between the second conductive film layer and the first conductive film layer.

[0050] As shown in Figure 2, in some embodiments, an isolation region 130 is included, which is located between the first region 110 and the second region 120.

[0051] The isolation region 130 effectively separates the first region 110 and the second region 120, preventing the mixing and recombination of charge carriers. This allows charges to be separated and transported more efficiently within their respective regions. The isolation region 130 reduces the opportunity for photogenerated carriers to migrate across regions and lowers the probability of carrier recombination, thereby improving the photoelectric conversion efficiency of the solar cell.

[0052] A first electrode 114 is stacked on a first conductive film layer 113, and a second electrode 124 is stacked on a second conductive film layer 123. Typically, the electrodes are elongated strips. The extension direction of the first electrode 114 is consistent with the extension direction of the first region 110, and the extension direction of the second electrode 124 is consistent with the extension direction of the second region 120. The width of the electrodes is horizontal and perpendicular to their extension direction. As shown in Figure 4, the width of the first electrode 114 is D1, and the width of the second electrode 124 is D2.

[0053] The width of the second electrode 124 is greater than the width of the first electrode 114. The wider second electrode 124 increases the reflective surface area of ​​light inside the cell. When light is incident from the front and passes through the silicon substrate 140, some unabsorbed light reaches the back side. The wider electrode can reflect more of this light back into the silicon wafer, increasing the effective path length of the light within the silicon. Long-wavelength light (near-infrared light) has a longer wavelength and is generally more difficult to absorb in a cell. The high reflectivity of the wide electrode causes these wavelengths of light to be reflected and re-enter the silicon substrate 140 multiple times, thereby increasing the probability of absorption. This promotes the spectral response of long-wavelength light, thus increasing the current.

[0054] The wider second electrode 124 increases the contact area with the silicon substrate 140, enhancing the contact interface for current transport. The larger contact area reduces current density and mitigates the impact of contact resistance on current transport. Low contact resistance translates to smoother current transport, facilitating efficient carrier collection over a larger area, improving carrier transport efficiency, thereby reducing energy losses in the electrodes and conductive paths, lowering overall series resistance, and improving the output voltage and current performance of the solar cell. This results in an increased fill factor (FF) and enhanced carrier transport efficiency.

[0055] In this embodiment, by providing alternating polished and textured regions on the backlight surface of the silicon substrate 140, the light reflection and absorption performance can be optimized. The first region 110 and the second region 120 are respectively covered with different types of passivation layers, doped layers, conductive films, and electrodes. Increasing the width of the second electrode 124 improves the internal back reflection capability of front-incident light, especially enhancing the spectral response to long-wavelength light. This helps to improve current output. Furthermore, a wider electrode contact surface reduces the influence of contact resistance, thereby improving carrier transport efficiency. This improvement reduces series resistance, thus increasing the fill factor (FF). Overall, these changes significantly improve the photoelectric conversion efficiency of the battery.

[0056] Example 2

[0057] Based on Embodiment 1, the thickness of the first electrode 114 is greater than the thickness of the second electrode 124.

[0058] As shown in Figure 4, the thickness of the first electrode 114 is H1, and the thickness of the second electrode 124 is H2. The first electrode 114 is disposed within the first region 110. The polished surface has a lower surface roughness than the textured surface, improving the incident light efficiency, maximizing light entry, and reducing surface light loss. This allows more light energy to reach the silicon substrate 140 for effective conversion. The thicker first electrode 114 increases its ability to block and reflect light. This reflection, combined with the effect of the polished surface, further ensures that light can be reflected back to the silicon substrate 140 multiple times, improving overall light utilization.

[0059] The width of the first electrode 114 is smaller than that of the second electrode 124, but the increased thickness of the first electrode 114 provides sufficient cross-sectional area to support efficient current transmission, concentrate the current path, and ensure the stability of current transmission and lower resistance loss. The thicker electrode provides a greater contact depth, and even with a narrower width, the local resistance when current passes through the electrode can be reduced by increasing the thickness, thereby reducing the resulting energy loss.

[0060] Example 3

[0061] As shown in Figure 3, based on Embodiment 1, the second passivation layer 121 and the second doped layer 122 extend into the first region 110 and are stacked on the first doped layer 112.

[0062] By extending the second passivation layer 121 and the second doped layer 122 into the first region 110 and stacking them on top of the first doped layer 112, the alignment requirements between layers can be reduced. Since these layers can be stacked in the same region, the process is simpler, avoiding the complex steps required for precise patterning in different regions. This design allows for continuous deposition or diffusion processes on the same substrate without additional mask alignment or photolithography steps, reducing manufacturing difficulty and costs, and minimizing errors.

[0063] Example 4

[0064] Based on Example 1, the first passivation layer 111 is a tunneling oxide layer, and the first doped layer 112 is a doped polysilicon layer;

[0065] The second passivation layer 121 is at least one of an intrinsic amorphous silicon layer or a tunneling oxide layer, and the second doped layer 122 is at least one of a doped amorphous silicon layer and a doped microcrystalline silicon layer.

[0066] The first passivation layer 111 may be a tunneling oxide layer, for example, a tunneling silicon oxide layer, and the first doped layer 112 may be a doped polycrystalline silicon layer. The second passivation layer 121 may be at least one of an intrinsic amorphous silicon layer or a tunneling oxide layer (e.g., a tunneling silicon oxide layer), and the second doped layer 122 may be at least one of a doped amorphous silicon layer and a doped microcrystalline silicon layer.

[0067] In this case, the first passivation contact structure is a tunneling passivation contact structure, and the second passivation contact structure is a heterojunction passivation contact structure. Thus, by designing the first doped layer as a doped polycrystalline silicon layer and the second doped layer as at least one of a doped amorphous silicon layer and a doped microcrystalline silicon layer, the efficiency of the battery is improved.

[0068] Meanwhile, designing the region corresponding to the polycrystalline silicon doping as a polished area can prevent a significant reduction in the passivation effect of the polycrystalline silicon doping region, which would affect efficiency. Amorphous silicon doping, microcrystalline silicon doping, or a combination of amorphous and microcrystalline silicon doping offer better passivation. Designing the region corresponding to the amorphous silicon doping, microcrystalline silicon doping, or a combination of amorphous and microcrystalline silicon doping as a textured surface can improve the anti-reflection effect on the back side, thereby increasing the bifaciality of the battery. In other words, under these conditions, the bifaciality of the battery can be further improved while maintaining the passivation effect in the region corresponding to the first doped layer.

[0069] Example 5

[0070] Based on Example 4, the first doped layer is an N-type doped layer and the second doped layer is a P-type doped layer.

[0071] Based on Example 1, the amorphous silicon layer is a P-type amorphous silicon layer, and the polycrystalline silicon layer is an N-type polycrystalline silicon layer.

[0072] Amorphous silicon has a high defect state density, which traps electrons, resulting in low electron mobility. However, holes move relatively more smoothly in amorphous silicon, making it more suitable as a p-type material. Amorphous silicon as a p-type material can also effectively passivate the interface with polycrystalline or crystalline silicon substrates, reducing carrier recombination caused by interface defect states and thus improving interface quality. Furthermore, amorphous silicon as a p-type layer exhibits good long-term stability, has mature processing technology, and relatively easy-to-control process parameters, meeting the requirements of large-scale industrial production.

[0073] N-type polycrystalline silicon has a higher number of free electrons and higher electron mobility, which can effectively improve the conductivity of devices and reduce resistance loss. The crystal structure of polycrystalline silicon is superior to that of amorphous silicon, and it has a lower defect state density, which makes polycrystalline silicon, as an N-type material, better able to conduct electrons.

[0074] Setting the amorphous silicon layer to P-type and the polycrystalline silicon layer to N-type fully utilizes the advantages of each material, optimizes the transport and separation efficiency of charge carriers, and improves the photoelectric conversion efficiency.

[0075] Example 6

[0076] Based on Example 1, the width of the second electrode 124 is 10-300 μm.

[0077] A width range of 10-300 μm balances the relationship between light transmission and current collection. Narrower electrodes reduce light shading and improve light absorption efficiency, while sufficiently wide electrodes ensure effective current collection, thereby improving overall cell efficiency. Within this width range, the electrodes provide sufficient conductive paths to ensure effective current transmission, reduce resistive losses on the electrodes, and improve the fill factor (FF).

[0078] Meanwhile, this range of electrode widths accommodates various manufacturing technologies, such as screen printing, inkjet printing, or laser direct writing, allowing for flexible selection of different processes to achieve electrode patterns. It eliminates the need for extremely high alignment precision, and the wide width range provides a degree of manufacturing tolerance, reducing the complexity and cost of microfabrication processes.

[0079] Example 7

[0080] Based on Embodiment 1, the difference between the width of the second electrode 124 and the width of the first electrode 114 is less than or equal to 50 μm.

[0081] The difference in width between the first electrode 114 and the second electrode 124 is less than or equal to 50 μm, meaning that the electrode sizes are within a relatively close range. On one hand, this effectively reduces the problem of uneven light blocking caused by excessive electrode width differences. This helps to distribute the light transmission area more evenly, further improving light absorption and reducing shading effects, thereby improving photoelectric conversion efficiency. When the electrode width difference is small, the current collection path is more symmetrical, effectively preventing uneven current transmission caused by uneven electrode distribution. This helps to reduce areas with excessively high or low local current density, improving the overall current transmission efficiency of the battery.

[0082] On the other hand, when the width difference between the two electrodes is small, it ensures that the resistances of the first electrode 114 and the second electrode 124 are relatively matched, reducing impedance mismatch problems when current is transmitted between different electrodes and lowering resistance losses. Because the electrode width difference is small, the current distribution is more uniform as it flows through the electrodes, reducing the occurrence of localized heating. This helps improve the long-term stability of the device and reduces thermal stress and electrical performance degradation caused by uneven temperature distribution.

[0083] Example 8

[0084] Based on Example 1, the thickness of the first electrode 114 is 10-30 μm.

[0085] The 10-30 μm electrode thickness design ensures low series resistance. This moderate thickness provides sufficient conductive cross-sectional area, reducing resistive losses as current flows through the electrode, thus contributing to improved fill factor (FF) and overall energy conversion efficiency. Furthermore, the 10-30 μm electrode thickness is suitable for various common manufacturing processes, such as screen printing, electroplating, or vapor deposition. This thickness range simplifies thickness control and deposition processes while ensuring electrical performance, reducing production complexity and cost.

[0086] Example 9

[0087] Based on Embodiment 1, the difference between the thickness of the first electrode 114 and the thickness of the second electrode 124 is less than or equal to 10 μm.

[0088] When the thickness difference between the two electrodes is controlled within 10 μm, the difference in electrode resistance is correspondingly reduced. This ensures that there is no significant resistance non-uniformity when current flows between the two electrodes, thereby reducing power loss and improving the overall current transmission efficiency of the battery. A smaller thickness difference results in a more uniform current density within the electrodes, avoiding excessively high or low current in localized areas. This helps improve the battery's energy conversion efficiency and stability. Furthermore, an electrode thickness difference of less than 10 μm ensures a more uniform distribution of mechanical stress, reducing material fracture or deformation caused by uneven stress distribution. Especially under high temperatures or external forces, this design can significantly improve electrode durability.

[0089] Example 10

[0090] Based on Example 1, the distance between the first electrode 114 and the second electrode 124 is 200-500 μm.

[0091] The distance between the first electrode 114 and the second electrode 124 refers to the distance between two adjacent opposing sides of the first electrode 114 and the second electrode 124. Controlling the distance between the first electrode 114 and the second electrode 124 to 200-500 μm effectively reduces parasitic capacitance effects, minimizes coupling interference between electrodes, and ensures a uniform electric field distribution. This helps improve the switching speed and response efficiency of the device, making it particularly suitable for electronic devices requiring fast response. Appropriate electrode spacing can avoid short-circuit problems caused by electrodes being too close together, ensuring the safety and reliability of the battery or circuit.

[0092] An electrode spacing of 200-500μm provides more space for heat transfer and dissipation, preventing heat buildup between electrodes and reducing localized overheating. This is particularly important for high-power devices or large batteries operating continuously, helping to improve their thermal stability and long-term operational safety. A more reasonable electrode spacing helps to achieve a more uniform temperature distribution, preventing the formation of hot spots, reducing thermal stress concentration, and improving the overall lifespan and reliability of the device.

[0093] Example 11

[0094] This embodiment provides a battery assembly, including the HBC battery described in the above embodiment.

[0095] The beneficial effects of the battery assembly in this embodiment are equivalent to those of the HBC battery described above, and will not be repeated here.

[0096] Example 12

[0097] This embodiment provides a photovoltaic system, including the battery module described in the above embodiment.

[0098] The beneficial effects of the photovoltaic system in this embodiment are equivalent to the beneficial effects of the battery module described above, and will not be repeated here.

[0099] The above are merely preferred embodiments of this disclosure and are not intended to limit this disclosure. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. An HBC battery, wherein, include: A silicon substrate having a backlight surface and a light-facing surface disposed opposite to each other, a first region and a second region being disposed on the backlight surface of the silicon substrate, the first region being a polished region and the second region being a textured region, the first region and the second region being disposed alternately and not overlapping; A first passivation layer, a first doped layer, and a first conductive film layer are sequentially stacked in the first region, and a second passivation layer, a second doped layer, and a second conductive film layer are sequentially stacked in the second region. The first doped layer and the second doped layer are of different shapes, and the first conductive film layer and the second conductive film layer are not connected. as well as A first electrode is stacked on the first conductive film layer and a second electrode is stacked on the second conductive film layer, wherein the width of the first electrode is smaller than the width of the second electrode.

2. A HBC battery as claimed in claim 1, wherein, The thickness of the first electrode is greater than the thickness of the second electrode.

3. A HBC battery as claimed in claim 1, wherein, The second passivation layer and the second doped layer extend into the first region and are stacked on top of the first doped layer.

4. A HBC battery as claimed in claim 1, wherein, The first passivation layer is a tunneling oxide layer, and the first doped layer is a doped polysilicon layer; The second passivation layer is at least one of an intrinsic amorphous silicon layer or a tunneling oxide layer, and the second doped layer is at least one of a doped amorphous silicon layer and a doped microcrystalline silicon layer.

5. A HBC battery as claimed in claim 4, wherein, The first doped layer is an N-type doped layer, and the second doped layer is a P-type doped layer.

6. A HBC battery as claimed in claim 1, wherein, The width of the second electrode is 10-300 μm.

7. A HBC battery as claimed in claim 6, wherein, The difference between the width of the second electrode and the width of the first electrode is less than or equal to 50 μm.

8. A HBC battery as claimed in claim 2, wherein, The thickness of the first electrode is 10-30 μm.

9. A HBC battery as claimed in claim 8, wherein, The difference between the thickness of the first electrode and the thickness of the second electrode is less than or equal to 10 μm.

10. A HBC battery as claimed in claim 1, wherein, The distance between the first electrode and the second electrode is 200-500 μm.

11. A battery assembly, wherein, Includes the HBC battery as described in any one of claims 1 to 10.

12. A photovoltaic system, wherein, Includes the battery assembly as described in claim 11.

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