Photovoltaic cell, assembly and system

Abstract

Provided in the present disclosure are a photovoltaic cell, an assembly and a system. In the photovoltaic cell, a passivation layer on at least a partial region of a P-type doped layer has a first thickness, the passivation layer on at least a partial region of an N-type doped layer has a second thickness, and the passivation layer on at least a partial region of an isolation region has a third thickness, wherein the first thickness is greater than the second thickness, and the first thickness is greater than the third thickness.

Description

Photovoltaic cells, modules and systems

[0001] Cross-reference to related applications

[0002] This disclosure claims priority to Chinese Patent Application No. 202422553141.8, filed on October 21, 2024, entitled “A Back Contact Solar Cell, Battery Module and Photovoltaic System”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of solar cell technology, specifically to a back-contact solar cell, a cell module, and a photovoltaic system. Background Technology

[0004] Solar cells utilize the photovoltaic effect of semiconductors to convert sunlight into electrical energy. Solar cells mainly include bifacial contact solar cells and back-contact solar cells. Back-contact solar cells, with both positive and negative electrodes located on the back of the cell, completely avoid the shading caused by metal grid lines on the front surface, thus eliminating optical losses and significantly improving cell conversion efficiency compared to bifacial contact solar cells.

[0005] In existing technologies, the back side of a back-contact solar cell typically includes P-regions and N-regions arranged sequentially at intervals, with an isolation region between adjacent P-regions and N-regions. The P-regions are provided with a P-type doped layer, and the N-regions are provided with an N-type doped layer. Both the P-type and N-type doped layers are covered by a passivation layer. However, the passivation layer thickness on the P-type and N-type doped layers is usually set to the same value, failing to adequately consider the optimization of the interaction between the passivation layers on the P-type and N-type doped layers. This results in poor passivation performance in the P-region and suboptimal cell performance.

[0006] Public content

[0007] This disclosure provides a back-contact solar cell, which aims to solve the problems of poor P-region passivation performance and poor cell performance in existing back-contact solar cells.

[0008] This disclosure is implemented by providing a back-contact solar cell, comprising:

[0009] A silicon wafer has a first surface and a second surface opposite to each other. The first surface includes a P-region, an N-region, and an isolation region disposed between the P-region and the N-region.

[0010] A P-type doped layer located in the P-region;

[0011] An N-type doped layer is located in the N region;

[0012] Passivation layer, which covers P-type doped layer, N-type doped layer and isolation region;

[0013] The passivation layer on at least a portion of the P-type doped layer has a first thickness, the passivation layer on at least a portion of the N-type doped layer has a second thickness, and the passivation layer on at least a portion of the isolation region has a third thickness. The first thickness is greater than the second thickness, and the first thickness is greater than the third thickness.

[0014] In some embodiments, the second thickness is greater than or equal to the third thickness.

[0015] In some embodiments, the ratio of the first thickness to the second thickness is greater than 1 and less than or equal to 2.2.

[0016] In some embodiments, the ratio of the first thickness to the second thickness is between 1.02 and 1.8.

[0017] In some embodiments, the difference between the first thickness and the second thickness is 2.5 nm to 52 nm.

[0018] In some embodiments, the first thickness is 55nm to 260nm, and the second thickness is 50nm to 220nm.

[0019] In some embodiments, the first surface includes a first edge region and a first intermediate region, the first intermediate region being located inside the first edge region, and the first edge region being closer to the edge of the first surface than the first intermediate region;

[0020] The passivation layer located in the first intermediate region on the P-type doped layer has a first thickness, and the passivation layer located in the first intermediate region on the N-type doped layer has a second thickness.

[0021] In some embodiments, the passivation layer on the P-type doped layer located in the first edge region has a fourth thickness, and the passivation layer on the N-type doped layer located in the first edge region has a fifth thickness. The fourth thickness is greater than the first thickness, the fifth thickness is greater than the second thickness, and the fourth thickness is greater than the fifth thickness.

[0022] In some embodiments, the ratio of the fourth thickness to the first thickness is greater than 1.2 and less than or equal to 3.2.

[0023] In some embodiments, the ratio of the fifth thickness to the second thickness is greater than 1 and less than or equal to 3.

[0024] In some embodiments, the silicon wafer further includes a plurality of side surfaces connecting the first surface and the second surface; a passivation layer covers at least a portion of the side surfaces, and the passivation layer on at least a portion of the side surfaces has a sixth thickness, and the sixth thickness is greater than the first thickness.

[0025] In some embodiments, the second surface includes a second edge region and a second intermediate region, the second edge region being located at the junction of the first surface and the side surface, and the second intermediate region being located inside the second edge region;

[0026] The passivation layer also covers the second surface, and the passivation layer on the second edge region has a seventh thickness and the passivation layer on the second middle region has an eighth thickness, with the seventh thickness being greater than the eighth thickness.

[0027] In some embodiments, the isolation region is a trench formed on the first surface, and the passivation layer covers the sides and bottom of the trench.

[0028] In some embodiments, it also includes:

[0029] The tunneling layer is located between the P-type doped layer and the silicon wafer, and between the N-type doped layer and the silicon wafer.

[0030] In some embodiments, the distance from the back side of the passivation layer at the P region location on the first surface to the second surface is greater than the distance from the back side of the passivation layer at the N region location on the first surface to the second surface, and the distance from the back side of the passivation layer at the N region location on the first surface to the second surface is greater than the distance from the back side of the passivation layer at the isolation region location on the first surface to the second surface.

[0031] In some embodiments, the passivation layer is a stack of one or more of the following: an aluminum oxide film, a silicon oxide film, a silicon oxynitride film, and a silicon nitride film.

[0032] This disclosure also provides a battery assembly including the aforementioned back-contact solar cell.

[0033] This disclosure also provides a photovoltaic system including the aforementioned battery module.

[0034] The back-contact solar cell disclosed herein achieves an optimized design of the passivation layer thickness by setting the thickness of at least a portion of the passivation layer on the P-type doped layer to be greater than the thickness of at least a portion of the passivation layer on the N-type doped layer, and by setting the thickness of at least a portion of the passivation layer on the P-type doped layer to be greater than the thickness of at least a portion of the passivation layer on the isolation region. This improves the passivation effect of the P-region and thus enhances the cell efficiency of the back-contact solar cell. Attached Figure Description

[0035] Figure 1 is a schematic diagram of a back-contact solar cell provided in an embodiment of this disclosure;

[0036] Figure 2 is a schematic diagram of another back-contact solar cell provided in an embodiment of this disclosure. Detailed Implementation

[0037] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this disclosure.

[0038] The back-contact solar cell provided in this disclosure sets the thickness of at least a portion of the passivation layer on the P-type doped layer to be greater than the thickness of at least a portion of the passivation layer on the N-type doped layer, and sets the thickness of at least a portion of the passivation layer on the P-type doped layer to be greater than the thickness of at least a portion of the passivation layer on the isolation region. In this way, by increasing the thickness of the passivation layer on the P-type doped layer, the passivation layer on the P-type doped layer is made thicker than the passivation layers on the N-region and the isolation region. This achieves an optimized design of the thickness of the passivation layer on the P-type doped layer, the N-type doped layer, and the isolation region, which can improve the passivation effect of the P-region and thus improve the cell efficiency of the back-contact solar cell.

[0039] Please refer to Figure 1. This embodiment of the present disclosure provides a back-contact solar cell, including:

[0040] Silicon wafer 1 has a first surface 11 and a second surface 12 opposite to each other. The first surface 11 includes a P region 111, an N region 112, and an isolation region 113 disposed between the P region 111 and the N region 112.

[0041] A P-type doped layer 2 is provided in the P region 111;

[0042] An N-type doped layer 3 is provided in the N region 112;

[0043] Passivation layer 4 covers P-type doped layer 2, N-type doped layer 3 and isolation region 113;

[0044] The passivation layer 4 on at least a portion of the P-type doped layer 2 has a first thickness D1, the passivation layer 4 on at least a portion of the N-type doped layer 3 has a second thickness D2, and the passivation layer 4 on at least a portion of the isolation region 113 has a third thickness D3. The first thickness D1 is greater than the second thickness D2, and the first thickness D1 is greater than the third thickness D3.

[0045] Because the passivation effect of the P-type doped layer 2 in the back contact solar cell is worse than that of the N-type doped layer 3, and the passivation layer 4 on the P-type doped layer 2 in related technologies has the same thickness as the passivation layer 4 of the N-type doped layer 3 and the isolation region 113, the passivation effect of the P region 111 is poor, which affects the cell efficiency. In the back contact solar cell provided in this disclosure, the thickness of at least a portion of the passivation layer 4 on the P-type doped layer 2 is greater than the thickness of at least a portion of the passivation layer 4 on the N-type doped layer 3, and the thickness of at least a portion of the passivation layer 4 on the P-type doped layer 2 is greater than the thickness of at least a portion of the passivation layer 4 on the isolation region 113, that is, the first thickness D1 is greater than the second thickness D2, and the first thickness D1 is greater than the third thickness D3. Thus, by increasing the thickness of the passivation layer 4 of the P-type doped layer 2, the passivation layer 4 on the P-type doped layer 2 becomes thicker than the passivation layer 4 on the N-region 112 and the passivation layer 4 on the isolation region 113. This achieves an optimized design for the thickness coordination of the P-type doped layer 2, the N-type doped layer 3, and the passivation layer 4 on the isolation region 113, thereby improving the passivation effect of the P-region 111 and thus improving the cell efficiency of the back contact solar cell.

[0046] Specifically, in the embodiments of this application, the first surface 11 may be the back side of the silicon wafer 1, and the second surface 12 may be the front side of the silicon wafer 1. The silicon wafer 1 may be a P-type silicon wafer or an N-type silicon wafer, and there is no specific limitation here. The P-type doped layer 2 may be a P-type doped polycrystalline silicon layer, a P-type doped microcrystalline silicon layer, or the like. The N-type doped layer 3 may be an N-type doped polycrystalline silicon layer, an N-type doped microcrystalline silicon layer, or the like. The P-type doped layer 2 and the N-type doped layer 3 may be prepared by diffusion, deposition, or other methods, and there is no specific limitation here.

[0047] It should be noted that, in the embodiments disclosed herein, the passivation layer 4 on the P-type doped layer 2 may have a thickness greater than a portion of the passivation layer 4 on the N-type doped layer 3, or the passivation layer 4 on the P-type doped layer 2 may have a thickness greater than the passivation layer 4 on the N-type doped layer 3. Similarly, the passivation layer 4 on the N-type doped layer 3 may have a thickness greater than a portion of the passivation layer 4 on the isolation region 113, or the passivation layer 4 on the N-type doped layer 3 may have a thickness greater than the passivation layer 4 on the isolation region 113.

[0048] It is understood that in the back contact solar cell, the first surface 11 has a plurality of P-type doped layers 2 and a plurality of N-type doped layers 3, which are arranged alternately in sequence.

[0049] As one embodiment of this disclosure, the P-type doped layer 2 and the N-type doped layer 3 are one or a combination of at least two of doped polycrystalline silicon, doped microcrystalline silicon, doped nanocrystalline silicon, and doped amorphous silicon. In some embodiments, the P-type doped layer 2 and the N-type doped layer 3 are doped polycrystalline silicon.

[0050] In this embodiment, the P-type doped layer 2 is doped with a P-type dopant, and the N-type doped layer 3 is doped with an N-type dopant. The P-type dopant is a Group IIIA element dopant, and the N-type dopant is a Group VA element dopant. For example, the P-type dopant can be a boron dopant, and the N-type dopant can be a phosphorus dopant.

[0051] In this embodiment of the disclosure, the P-type doped layer 2 and the N-type doped layer 3 can be single-layer doped layers, or they can include two, three or more layers of doped layers to further improve the passivation effect of the battery.

[0052] As one embodiment of this disclosure, the ratio of the first thickness D1 to the second thickness D2 is greater than 1 and less than or equal to 2.2.

[0053] Specifically, in such an embodiment, the ratio of the first thickness D1 to the second thickness D2 can be any value among 1.01, 1.05, 1.1, 1.16, 1.2, 1.28, 1.3, 1.36, 1.4, 1.42, 1.5, 1.55, 1.6, 1.65, 1.7, 1.75, 1.8, 1.85, 1.9, 1.95, 2, 2.05, 2.1, 2.15, and 2.2, without any specific limitation.

[0054] The ratio of the first thickness D1 to the second thickness D2 is preferably 1 and less than or equal to 2.2. Through repeated research and verification, the inventors of this application have discovered that setting the ratio of the first thickness D1 to the second thickness D2 within this range in some embodiments can significantly improve the passivation effect of the region corresponding to P-region 111, which is beneficial to improving battery efficiency.

[0055] As one embodiment of this disclosure, the ratio of the first thickness D1 to the second thickness D2 is 1.02 to 1.8.

[0056] Specifically, in such an embodiment, the ratio of the first thickness D1 to the second thickness D2 can be any value among 1.02, 1.05, 1.1, 1.16, 1.2, 1.28, 1.3, 1.36, 1.4, 1.42, 1.5, 1.55, 1.6, 1.65, 1.7, 1.75, and 1.8, and no specific limitation is imposed here.

[0057] The ratio of the first thickness D1 to the second thickness D2 is preferably between 1.02 and 1.8. Through repeated research and verification, the inventors of this application have discovered that setting the ratio of the first thickness D1 to the second thickness D2 within this range in some embodiments can further improve the passivation effect of the region corresponding to P-region 111, which is beneficial for improving battery efficiency while maintaining a low cost.

[0058] As one embodiment of this disclosure, the first thickness D1 is 55nm to 260nm, and the second thickness D2 is 50nm to 220nm.

[0059] Specifically, in such an embodiment, the first thickness D1 can be any value among 52nm, 60nm, 80nm, 95nm, 100nm, 110nm, 125nm, 130nm, 140nm, 150nm, 165nm, 170nm, 180nm, 185nm, 190nm, 200nm, 210nm, 220nm, 230nm, 240nm, 250nm, and 260nm, without any specific limitation. The second thickness D2 can be any value among 50nm, 55nm, 90nm, 95nm, 100nm, 110nm, 125nm, 130nm, 140nm, 150nm, 165nm, 170nm, 180nm, 185nm, 190nm, 200nm, 210nm, and 220nm, without any specific limitation.

[0060] As one embodiment of this disclosure, the difference between the first thickness D1 and the second thickness D2 is 2.5 nm to 52 nm.

[0061] Specifically, in such an embodiment, the difference between the first thickness D1 and the second thickness D2 can be any value among 2.5nm, 3nm, 5nm, 8nm, 10nm, 12nm, 14nm, 15nm, 18nm, 20nm, 25nm, 28nm, 30nm, 35nm, 36nm, 39nm, 40nm, 42nm, 45nm, 48nm, 50nm, 51nm, and 52nm, without any specific limitation.

[0062] As one embodiment of this disclosure, the second thickness D2 is greater than or equal to the third thickness D3.

[0063] In this embodiment, the thickness of at least a portion of the passivation layer 4 on the N-type doped layer 3 is greater than or equal to the thickness of at least a portion of the passivation layer 4 on the isolation region 113, that is, the second thickness D2 is greater than or equal to the third thickness D3. In this application, the passivation layer 4 on the N-type doped layer 3 may have only a portion of its thickness greater than or equal to the thickness of a portion of the passivation layer 4 on the isolation region 113, or the thickness of the entire passivation layer 4 on the N-type doped layer 3 may be greater than or equal to the thickness of the entire passivation layer 4 on the isolation region 113.

[0064] This makes the passivation layer 4 on the N-type doped layer 3 thicker than the passivation layer 4 on the isolation region 113, or the passivation layer 4 on the N-type doped layer 3 has the same thickness as the passivation layer 4 on the isolation region 113, which is beneficial to improve the passivation effect of the N region 112, thereby improving the battery efficiency, and can reduce the amount of material used in the passivation layer 4 on the isolation region 113, thus reducing the production cost.

[0065] As an embodiment of this disclosure, the first surface 11 includes a first edge region A and a first intermediate region B, the first intermediate region B being located inside the first edge region A, and the first edge region A being closer to the edge of the first surface 11 than the first intermediate region B;

[0066] Among them, the passivation layer 4 of the P-type doped layer 2 located in the first intermediate region B has a first thickness D1, and the passivation layer 4 of the N-type doped layer 3 located in the first intermediate region B has a second thickness D2.

[0067] In this way, the thickness of the passivation layer 4 in the middle region of the P-type doped layer 2 can be greater than the thickness of the passivation layer 4 in the middle region of the N-type doped layer 3, thereby improving the passivation effect of the passivation layer 4 in the P region 111 in the middle region and thus improving the performance of the solar cell.

[0068] As an embodiment of this disclosure, the passivation layer 4 on the P-type doped layer 2 located in the first edge region A has a fourth thickness D4, and the passivation layer 4 on the N-type doped layer 3 located in the first edge region A has a fifth thickness D5. The fourth thickness D4 is greater than the first thickness D1, the fifth thickness D5 is greater than the second thickness D2, and the fourth thickness D4 is greater than the fifth thickness D5.

[0069] In this way, the thickness of the passivation layer 4 at the edge region of the P-type doped layer 2 can be greater than the thickness of the passivation layer 4 at the edge region of the N-type doped layer 3, that is, the fourth thickness D4 is greater than the fifth thickness D5, further improving the passivation effect of the P-region 111 at the edge region, thereby improving the performance of the back contact solar cell. Moreover, the fourth thickness D4 is greater than the first thickness D1, making the thickness of the passivation layer 4 at the edge region of the P-type doped layer 2 greater than the thickness of the passivation layer 4 at the middle region of the P-type doped layer 2, improving the passivation effect at the edge of the P-region 111; the fifth thickness D5 is greater than the second thickness D2, making the thickness of the passivation layer 4 at the edge region of the N-type doped layer 3 greater than the thickness of the N-type doped layer 3 at the middle region, improving the passivation effect at the edge of the N-region 112.

[0070] As one embodiment of this disclosure, the ratio of the fourth thickness D4 to the first thickness D1 is greater than 1.2 and less than or equal to 3.2.

[0071] The ratio of the fourth thickness D4 to the first thickness D1 can be any value among 1.2, 1.3, 1.5, 1.7, 1.8, 1.9, 2.0, 2.1, 2.2, 2.3, 2.4, 2.5, 2.6, 2.7, 2.8, 2.9, 3.0, 3.1, and 3.2.

[0072] The ratio of the fourth thickness D4 to the first thickness D1 is greater than 1.2 and less than or equal to 3.2. Setting the ratio of the first thickness D1 to the second thickness D2 within this range in some embodiments can significantly improve the passivation effect of the edge region of P area 111, which is beneficial to improving battery efficiency.

[0073] As one embodiment of this disclosure, the ratio of the fifth thickness D5 to the second thickness D2 is greater than 1 and less than or equal to 3.

[0074] The ratio of the fifth thickness D5 to the second thickness D2 can be any value among 1.01, 1.2, 1.5, 1.7, 1.8, 1.9, 2.0, 2.1, 2.2, 2.3, 2.4, 2.5, 2.6, 2.7, 2.8, 2.9, and 3.0.

[0075] The ratio of the fifth thickness D5 to the second thickness D2 is greater than 1 and less than or equal to 3, which can significantly improve the passivation effect of the edge region of N region 112, thus improving battery efficiency.

[0076] Referring to Figure 2, as an embodiment of this disclosure, the silicon wafer 1 further includes a plurality of side surfaces 13 connecting the first surface 11 and the second surface 12; a passivation layer 4 covers at least a portion of the side surfaces 13, and the passivation layer 4 on at least a portion of the side surfaces 13 has a sixth thickness D6, and the sixth thickness D6 is greater than the first thickness D1.

[0077] In this embodiment, the passivation layer 4 covers at least part of the side surface 13, which can passivate the side surface 13 of the silicon wafer 1, reduce edge recombination, and at the same time make the passivation effect in each area of ​​the silicon wafer 1 reach a better matching state, thereby further improving the battery efficiency.

[0078] As an embodiment of this disclosure, the second surface 12 has a second edge region C and a second intermediate region D, the second edge region C is located at the junction of the first surface 11 and the side surface 13, and the second intermediate region D is located inside the second edge region C;

[0079] The passivation layer 4 also covers the second surface 12. The passivation layer 4 on the second edge region C has a seventh thickness D7, and the passivation layer 4 on the second middle region D has an eighth thickness D8. The seventh thickness D7 is greater than the eighth thickness D8.

[0080] In this embodiment, the passivation layer 4 covers the second surface 12 of the silicon wafer 1, which can passivate the second surface 12 of the silicon wafer 1, thereby further improving the battery efficiency. The thickness of the passivation layer 4 on the second edge region C is greater than the thickness of the passivation layer 4 on the second intermediate region D, that is, the seventh thickness D7 is greater than the eighth thickness D8, which can improve the passivation effect of the edge region of the second surface 12 and reduce edge recombination.

[0081] As one embodiment of this disclosure, the isolation region 113 is a trench formed on the first surface 11, and the passivation layer 4 covers the sides and bottom of the trench. The thickness of the passivation layer 4 on the sides and bottom of the trench may be equal or unequal.

[0082] In this embodiment, a trench is formed on the back side of the silicon wafer 1, and the P-type doped layer 2 and the N-type doped layer 3 are isolated by the trench, thereby improving the isolation effect between the P-type doped layer 2 and the N-type doped layer 3. The passivation layer 4 covers the sides and bottom of the trench 121, thus improving the passivation matching effect at the trench 121, thereby improving the overall passivation performance and enhancing the performance of the solar cell.

[0083] As one embodiment of this disclosure, it also includes:

[0084] The tunneling layer 5 is disposed between the P-type doped layer 2 and the silicon wafer 1 and between the N-type doped layer 3 and the silicon wafer 1.

[0085] In this embodiment, the tunneling layer 5 is a stack of one or more of the following: silicon oxide layer, silicon oxynitride layer, and silicon nitride layer.

[0086] In this embodiment, the tunneling layer 5 serves to tunnel and passivate the surface of the silicon wafer 1, which helps to improve the efficiency of the solar cell. The thickness of the tunneling layer 5 in the P-region 111 and the N-region 112 can be set according to actual conditions. For example, the thickness of the tunneling layer 5 can be 0.5 to 5 nanometers.

[0087] In one embodiment of this disclosure, the distance from the back side of the passivation layer 4 at the P-region 111 position on the first surface 11 to the second surface 12 is greater than the distance from the back side of the passivation layer 4 at the N-region 112 position on the first surface 11 to the second surface 12, and the distance from the back side of the passivation layer 4 at the N-region 112 position on the first surface 11 to the second surface 12 is greater than the distance from the back side of the passivation layer 4 at the isolation region 113 position on the first surface 11 to the second surface 12. The back side of the passivation layer 4 is the side of the passivation layer 4 that faces away from the silicon wafer 1.

[0088] In this embodiment, the sum of the thicknesses of the silicon wafer 1, tunneling layer 5, P-type doped layer 2, and passivation layer 4 on the back of the P-type doped layer 2 in region P111 is greater than the sum of the thicknesses of the silicon wafer 1, tunneling layer 5, N-type doped layer 3, and passivation layer 4 on the back of the N-type doped layer 3 in region N112, and the sum of the thicknesses of the silicon wafer 1, tunneling layer 5, N-type doped layer 3, and passivation layer 4 on the back of the N-type doped layer 3 in region N112 is greater than the sum of the thicknesses of the silicon wafer 1 and passivation layer 4 in isolation region 113.

[0089] In this embodiment, since the passivation layer 4 of P region 111 is thicker than that of N region 112 and isolation region 113, the passivation layer 4 of P region 111 provides scratch resistance to the P-type doped layer 2. Therefore, P region 111 is less prone to scratches during battery transfer. Consequently, the distance from the back side of the passivation layer 4 at the P region 111 position on the first surface 11 to the second surface 12 is greater than the distance from the back side of the passivation layer 4 at the N region 112 position on the first surface 11 to the second surface 12. Furthermore, the distance from the back side of the passivation layer 4 at the N region 112 position on the first surface 11 to the second surface 12 is also greater. The distance from the back of the passivation layer 4 of the isolation region 113 on the first surface 11 to the second surface 12 is greater than that of the P region 111. This makes the height of the P region 111 higher than that of the N region 112 and the isolation region 113. As a result, during the transmission of the solar cell, only the passivation layer 4 of the P region 111 is in contact with the conveyor belt, while the N region 112 and the isolation region 113 are suspended in the air by a certain gap with the conveyor belt. This avoids scratching the N region 112 and the isolation region 113 during the transmission of the solar cell and solves the problem of scratches caused by the conveyor belt during the cell manufacturing process.

[0090] As an embodiment of this disclosure, the passivation layer 4 is a stack of one or more of the following: an aluminum oxide film, a silicon oxide film, a silicon oxynitride film, and a silicon nitride film.

[0091] The passivation layer 4 can be a single layer or composed of two or more layers stacked together. The materials of the passivation layer 4 in the P region 111, N region 112 and isolation region 113 can be the same or different. For example, the passivation layer 4 includes an aluminum oxide film layer and a silicon nitride film layer sequentially disposed from the first surface 11 toward the direction away from the silicon wafer 1.

[0092] In this embodiment, the passivation layer 4 can be a modular structure, meaning it can be deposited in stages, which facilitates control over the thickness differences of the passivation layer 4 in different regions of P-region 111, N-region 112, and isolation region 113. Of course, the passivation layer 4 can also be a monolithic structure.

[0093] This disclosure also provides a battery assembly including the back-contact solar cell described in the above embodiments. It should be noted that this battery assembly has the same or similar beneficial effects as the back-contact solar cell, and the related aspects between the two can be referred to each other; to avoid repetition, they will not be repeated here.

[0094] In this embodiment, multiple back-contact solar cells in the battery module can be connected in series to form a battery string, thereby achieving series current output. For example, the battery cells can be connected in series by setting solder strips (busbars, interconnecting strips), conductive backplates, etc.

[0095] It is understood that in such embodiments, the battery assembly may also include a metal frame, a backsheet, photovoltaic glass, and an encapsulating film. The encapsulating film may be filled between the front and back of the back-contact solar cell, the photovoltaic glass, adjacent cells, etc. As a filler, it may be a transparent colloid with good light transmittance and aging resistance. For example, the encapsulating film may be an EVA film or a POE film, and the specific choice can be made according to the actual situation, without limitation.

[0096] Photovoltaic glass can be applied to the encapsulating film on the front side of the back-contact solar cell. This photovoltaic glass can be ultra-clear glass, possessing high light transmittance, high transparency, and superior physical, mechanical, and optical properties. For example, ultra-clear glass can achieve a light transmittance of over 92%, protecting the solar cell while minimizing impact on its efficiency. Simultaneously, the encapsulating film bonds the photovoltaic glass and the back-contact solar cell together, providing sealing, insulation, and waterproofing.

[0097] The backsheet can be attached to the adhesive film on the back of the back-contact solar cell. The backsheet protects and supports the back-contact solar cell, providing reliable insulation, water resistance, and aging resistance. Multiple backsheet options are available, typically including tempered glass, acrylic glass, aluminum alloy TPT composite film, etc., and the specific choice depends on the specific circumstances and is not limited here. The backsheet, back-contact solar cell, adhesive film, and photovoltaic glass can be mounted on a metal frame. The metal frame serves as the main external support structure for the entire solar cell module, providing stable support and installation. For example, the solar cell module can be installed at the desired location using the metal frame.

[0098] This disclosure also provides a photovoltaic system including the battery module described above. It should be noted that this photovoltaic system has the same or similar beneficial effects as the back-contact solar cell described above, and the related aspects between the two can be referred to each other; to avoid repetition, they will not be repeated here.

[0099] In this embodiment, the photovoltaic system can be applied in photovoltaic power plants, such as ground-mounted power plants, rooftop power plants, and floating power plants. It can also be applied to equipment or devices that utilize solar energy to generate electricity, such as user solar power supplies, solar streetlights, solar cars, and solar buildings. Of course, it is understood that the application scenarios of the photovoltaic system are not limited to these; that is, the photovoltaic system can be applied in all fields that require solar energy to generate electricity. Taking a photovoltaic power generation system network as an example, the photovoltaic system may include a photovoltaic array, a combiner box, and an inverter. The photovoltaic array may be an array combination of multiple solar cell modules; for example, multiple solar cell modules can form multiple photovoltaic arrays. The photovoltaic array is connected to the combiner box, which can collect the current generated by the photovoltaic array. The collected current flows through the inverter and is converted into AC power required by the mains power grid before being connected to the mains power grid to achieve solar power supply.

[0100] The above are merely preferred embodiments of this disclosure and are not intended to limit this disclosure. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A back-contact solar cell, comprising: A silicon wafer having opposing first and second surfaces, the first surface including a P-region, an N-region, and an isolation region disposed between the P-region and the N-region; A P-type doped layer is provided in the P region; An N-type doped layer is provided in the N region; A passivation layer covering the P-type doped layer, the N-type doped layer, and the isolation region; The passivation layer on at least a portion of the P-type doped layer has a first thickness, the passivation layer on at least a portion of the N-type doped layer has a second thickness, and the passivation layer on at least a portion of the isolation region has a third thickness, wherein the first thickness is greater than the second thickness and the third thickness is greater than the third thickness.

2. The back-contact solar cell according to claim 1, wherein, The second thickness is greater than or equal to the third thickness.

3. The back-contact solar cell according to claim 1, wherein, The ratio of the first thickness to the second thickness is greater than 1 and less than or equal to 2.

2.

4. The back-contact solar cell according to claim 1, wherein, The ratio of the first thickness to the second thickness is between 1.02 and 1.

8.

5. The back-contact solar cell according to claim 1, wherein, The difference between the first thickness and the second thickness is 2.5 nm to 52 nm.

6. The back-contact solar cell according to claim 1, wherein, The first thickness is 55nm to 260nm, and the second thickness is 50nm to 220nm.

7. The back-contact solar cell according to claim 1, wherein, The first surface includes a first edge region and a first middle region, the first middle region being located inside the first edge region, and the first edge region being closer to the edge of the first surface than the first middle region; Wherein, the passivation layer located in the first intermediate region on the P-type doped layer has the first thickness, and the passivation layer located in the first intermediate region on the N-type doped layer has the second thickness.

8. The back-contact solar cell according to claim 7, wherein, The passivation layer on the P-type doped layer located in the first edge region has a fourth thickness, and the passivation layer on the N-type doped layer located in the first edge region has a fifth thickness. The fourth thickness is greater than the first thickness, the fifth thickness is greater than the second thickness, and the fourth thickness is greater than the fifth thickness.

9. The back-contact solar cell according to claim 8, wherein, The ratio of the fourth thickness to the first thickness is greater than 1.2 and less than or equal to 3.

2.

10. The back-contact solar cell according to claim 8, wherein, The ratio of the fifth thickness to the second thickness is greater than 1 and less than or equal to 3.

11. The back-contact solar cell according to claim 1, wherein, The silicon wafer also includes a plurality of side surfaces connecting the first surface and the second surface; the passivation layer covers at least a portion of the side surfaces, and the passivation layer on at least a portion of the side surfaces has a sixth thickness, and the sixth thickness is greater than the first thickness.

12. The back-contact solar cell according to claim 11, wherein, The second surface includes a second edge region and a second middle region, the second edge region being located at the junction of the first surface and the side surface, and the second middle region being located inside the second edge region; The passivation layer also covers the second surface, the passivation layer on the second edge region has a seventh thickness, the passivation layer on the second middle region has an eighth thickness, and the seventh thickness is greater than the eighth thickness.

13. The back-contact solar cell according to claim 1, wherein, The isolation area is a trench formed on the first surface, and the passivation layer covers the sides and bottom of the trench.

14. The back-contact solar cell according to claim 1, wherein, Also includes: A tunneling layer is disposed between the P-type doped layer and the silicon wafer, and between the N-type doped layer and the silicon wafer.

15. The back-contact solar cell according to claim 1, wherein, The distance from the back side of the passivation layer at the P region location on the first surface to the second surface is greater than the distance from the back side of the passivation layer at the N region on the first surface to the second surface, and the distance from the back side of the passivation layer at the N region on the first surface to the second surface is greater than the distance from the back side of the passivation layer at the isolation region on the first surface to the second surface.

16. The back-contact solar cell according to claim 1, wherein, The passivation layer is a stack of one or more of the following: aluminum oxide film, silicon oxide film, silicon oxynitride film, and silicon nitride film.

17. A battery assembly comprising a back-contact solar cell as described in any one of claims 1 to 16.

18. A photovoltaic system comprising the battery module as described in claim 17.

Images