Circuit board and semiconductor package

Abstract

This circuit board comprises: a build-up layer comprising a plurality of insulating layers stacked vertically; and a metal layer penetrating at least a portion of the build-up layer, wherein the metal layer comprises a first portion and second portions disposed on one and the other surfaces of the first portion, and the size of crystal grains in at least one region of the first portion is smaller than those in the second portions.

Description

Circuit boards and semiconductor packages

[0001] The present embodiment relates to a circuit board and a semiconductor package.

[0002]

[0003] A circuit board is a substrate in which a printed circuit is printed using a conductive material on an insulating substrate.

[0004] Circuit boards are configured in a structure where the mounting positions of various types of components are determined and circuit patterns connecting the components are printed and fixed on the flat surface to densely mount them on a flat plate, or in an embedded structure where components are embedded inside the printed circuit board.

[0005] Recently, in order to realize the miniaturization and multifunctionality of electronic components, circuit boards are being used in multilayer structures capable of high-density integration, and when devices such as Power Amplifiers (PAs) are embedded, coreless circuit boards are being used to achieve miniaturization and heat dissipation efficiency.

[0006] A coreless circuit board is formed with a stack via structure connected from the upper layer to the lower layer to facilitate heat dissipation, and a metal layer for heat dissipation may be disposed within the stack via.

[0007]

[0008] The present invention provides a circuit board and a semiconductor package capable of improving heat dissipation efficiency and productivity.

[0009] In addition, the invention provides a circuit board and a semiconductor package with improved interlayer bonding properties and the ability to uniformly form the surface of the circuit board through surface control of the metal layer placed within the via hole.

[0010]

[0011] A circuit board according to the present embodiment comprises a build-up layer including a plurality of insulating layers stacked along a vertical direction; and a metal layer penetrating at least a portion of the build-up layer, wherein the metal layer comprises a first portion and a second portion disposed on one side and the other side of the first portion, and the size of the crystal grains in at least one region of the first portion is smaller than the size of the crystal grains in the second portion.

[0012] The above build-up layer includes a hole in which the metal layer is disposed, and the first part may be disposed to penetrate the inner wall of the hole.

[0013] The above second part may protrude from the surface of the above build-up structure.

[0014] The above-mentioned first part includes a first-1 part arranged in a vertical direction and a first-2 part, and at least one region of the first part is the first-1 part, and the size of the crystal grains of the first-1 part may be smaller than the size of the crystal grains of the first-2 part.

[0015] The vertical thickness of the above 1-1 part may be smaller than the vertical thickness of the above 1-2 part.

[0016] It includes a plurality of power wiring portions disposed in each of the plurality of insulating layers, and a plurality of power via portions penetrating at least a portion of each of the plurality of insulating layers to electrically connect the plurality of power wiring portions, and the plurality of power wiring portions and the plurality of power via portions can be connected to the first portion.

[0017] The metal layer includes an upper portion disposed on the upper surface of the build-up layer and a lower portion disposed on the lower surface of the build-up layer, and the upper portion and the lower portion can each be connected to the plurality of power wiring portions disposed on the surface of the build-up layer.

[0018] The horizontal length of the upper part and the lower part may be longer than the horizontal length of the central part connecting the upper part and the lower part.

[0019] The vertical thickness of the above 1-1 part may be 1 µm to 2 µm.

[0020] A semiconductor package according to the present embodiment comprises: a build-up layer including a plurality of insulating layers stacked along a vertical direction; a metal layer penetrating at least a portion of the build-up layer; and a semiconductor chip disposed on the metal layer, wherein the metal layer comprises a first portion and a second portion disposed on one side and the other side of the first portion, and the size of the crystal grains in at least one region of the first portion is smaller than the size of the crystal grains in the second portion.

[0021]

[0022] In this embodiment, as the second part is implemented by the electroplating method through the first part, the shape of the metal layer can be formed in various ways corresponding to the shape of the hole, and since a separate process for bonding with the build-up layer is omitted, productivity can also be improved.

[0023] In addition, since the metal layer is formed by an electroplating method, the size of the crystal grains constituting the metal layer becomes smaller, allowing for high thermal conductivity and thus improving heat dissipation efficiency.

[0024] In addition, heat dissipation efficiency can be improved by reducing the amount of plating required to form the metal part and by using a metal part placement structure that considers the placement area of ​​the semiconductor chip.

[0025] In addition, it has the advantage of improving the reliability of the circuit board by increasing the adhesion between the metal part and the insulating layer constituting the build-up structure.

[0026] In addition, by forming a metal part through electroplating with dense crystal grains, there is an advantage of improving heat dissipation efficiency due to high thermal conductivity.

[0027]

[0028] FIG. 1 is a cross-sectional view of a circuit board according to a first embodiment of the present invention.

[0029] FIG. 2 is an enlarged view of A in FIG. 1.

[0030] FIG. 3 is a drawing of a crystal in the combined area of ​​the first and second parts according to the first embodiment of the present invention.

[0031] FIG. 4 is a drawing of a crystal of the second part within a metal layer according to the first embodiment of the present invention.

[0032] FIG. 5 is a graph showing the size of crystal grains in a metal layer according to the first embodiment of the present invention.

[0033] FIG. 6 is a plan view showing the upper surface of a circuit board according to the first embodiment of the present invention.

[0034] FIG. 7 is a perspective view of a semiconductor package according to a first embodiment of the present invention.

[0035] FIG. 8 is a cross-sectional view of a semiconductor package according to a first embodiment of the present invention.

[0036] FIG. 9 is a cross-sectional view of a circuit board according to a second embodiment of the present invention.

[0037] FIG. 10 is a drawing showing an enlarged view of one area of ​​FIG. 9.

[0038] FIG. 11 is a plan view showing the upper surface of a circuit board according to a second embodiment of the present invention.

[0039] FIGS. 12 to 16 are drawings for explaining the manufacturing process of a circuit board according to a second embodiment of the present invention.

[0040] FIG. 17 is a cross-sectional view of a semiconductor package according to a second embodiment of the present invention.

[0041] FIG. 18 is a perspective view of a semiconductor package according to a second embodiment of the present invention.

[0042] FIG. 19 is a cross-sectional view of a circuit board according to a third embodiment of the present invention.

[0043] FIG. 20 is a cross-sectional view of a circuit board according to a fourth embodiment of the present invention.

[0044]

[0045]

[0046] The present invention is susceptible to various modifications and may have various embodiments, and specific embodiments are illustrated and described in the drawings. However, this does not specify the present invention.

[0047] It should be understood that the embodiments are not intended to be limited and include all modifications, equivalents, and substitutions that fall within the spirit and scope of the invention.

[0048] However, the technical concept of the present invention is not limited to some of the described embodiments but can be implemented in various different forms, and within the scope of the technical concept of the present invention, one or more of the components among the embodiments may be selectively combined or substituted.

[0049] In addition, terms used in the embodiments of the present invention (including technical and scientific terms) shall be interpreted in a meaning generally understood by those skilled in the art to which the present invention pertains, unless explicitly and specifically defined otherwise. Commonly used terms, such as those defined in a dictionary, shall be interpreted in consideration of their contextual meaning as described in the present invention. If a commonly used term defined in a dictionary does not match the meaning it has in the context of the description of the present invention, it shall be interpreted in accordance with the meaning it has in the context of the description of the present invention. Furthermore, even if not explicitly defined in this application, it shall not be interpreted in an ideal or overly formal sense based on the description of the present invention.

[0050] Furthermore, the terms used in the embodiments of the present invention are for describing the embodiments and are not intended to limit the present invention. In this specification, the singular form may include the plural form unless specifically stated otherwise in the text.

[0051] Terms containing ordinal numbers, such as "first," "second," etc., may be used to describe various components, but the meaning of the components is not limited by the ordinal numbers. Terms containing ordinal numbers are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the second component may be named the first component, and similarly, the first component may be named the second component. Furthermore, if the meaning of the component does not depart from the scope of the present invention even without ordinal numbers such as "first" and "second," the component may be referred to by excluding the ordinal number.

[0052] The term "and / or" includes a combination of multiple related listed items or any of the multiple related listed items. Such a term is used merely to distinguish a component from other components and is not limited by the nature, order, sequence, etc. of the component.

[0053] In this application, terms such as “comprising,” “provided,” and “having” are intended to specify the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not excluding in advance the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0054] When referring to directions, vertical and horizontal directions are used for convenience of explanation. Additionally, the horizontal direction may include a first horizontal direction perpendicular to the vertical direction, and a second horizontal direction perpendicular to the first horizontal direction and the vertical direction. Furthermore, if the vertical and horizontal directions follow a Cartesian coordinate system, they may correspond to the first horizontal direction (X-axis), the second horizontal direction (Y-axis), and the vertical direction (Z-axis), respectively; if they follow a cylindrical coordinate system, the first horizontal direction may refer to the azimuth (Φ) direction (or circumferential direction), and the second horizontal direction may refer to the radius (ρ) direction (or centrifugal direction) separated from a specific configuration; and if they follow a spherical coordinate system, the first horizontal direction may refer to the azimuth (Φ) direction (or circumferential direction), and the second horizontal direction may refer to the radius (r) direction (or centrifugal direction) separated from a specific configuration. In particular, the vertical direction may refer to the polar angle (θ) direction formed by the second horizontal direction and the Z-axis. For convenience of explanation, the first horizontal direction, the second horizontal direction, and the vertical direction may be used by combining the Cartesian coordinate system, the cylindrical coordinate system, and the spherical coordinate system described above. However, unless otherwise specified, the vertical direction refers to the Z-axis according to the Cartesian coordinate system, and the horizontal direction refers to any direction that can be defined on the XY plane; when referring to the first horizontal direction and the second horizontal direction perpendicular to the first horizontal direction, the first horizontal direction refers to the X-axis and the second horizontal direction refers to the Y-axis.

[0055] Furthermore, when described as being formed or placed "above or below" each component, "above" or "below" includes not only cases where two components are in direct contact with each other, but also cases where one or more other components are formed or placed between the two components. Additionally, when expressed as "above or below," it may include the meaning of a downward direction as well as an upward direction relative to a single component.

[0056] Furthermore, the meaning that Configuration A is positioned between Configuration B and Configuration C may include the meaning that Configuration A is positioned such that at least a portion of it overlaps with Configurations B and C in the horizontal and / or vertical directions. Unless otherwise noted, even if Configuration C is located between a virtual line extending vertically and / or horizontally from Configuration A and a virtual line extending vertically and / or horizontally from Configuration B, the meaning may include that Configuration C is positioned between Configuration A and Configuration B.

[0057] Furthermore, the statement that Configuration A is exposed from Configuration B should be understood as meaning that Configuration A is exposed from Configuration B, not that Configuration A is exposed from the entire product; and unless there are special circumstances, it should not be understood as meaning that the entirety of Configuration A is covered by Configuration B. In other words, when Configuration A is stated to be exposed from Configuration B, it should be understood to mean that Configuration C, in addition to Configurations A and B, covers Configuration A exposed from Configuration B.

[0058] Additionally, where it is stated that a component is 'connected,' 'combined,' 'connected,' or 'contacted' with another component, this may include not only cases where the component is directly connected, combined, or connected to the other component, but also cases where it is 'connected,' 'combined,' or 'connected' due to another component located between the component and the other component. Accordingly, if component A is to be understood only as being directly 'connected,' 'combined,' 'connected,' or 'contacted' with component B, it is described as being 'directly connected,' 'directly combined,' 'directly connected,' or 'directly contacted.'

[0059] In addition, when it is stated that configuration A is 'fixed' to configuration B, it should be understood that configuration A is indirectly fixed to configuration B through configuration C and / or configuration D, etc., unless otherwise specifically mentioned, considering the function and purpose to be solved, and in cases where configuration A is to be understood only as being 'directly fixed' to configuration B, it is stated as being 'directly fixed'.

[0060] In addition, when described as “flat” or “located on the same plane,” it should not be interpreted according to the dictionary definition, but rather understood by a person with ordinary knowledge in the relevant technical field to the extent that process deviations are taken into account.

[0061] FIG. 1 is a cross-sectional view of a circuit board according to a first embodiment of the present invention, FIG. 2 is an enlarged view of A of FIG. 1, FIG. 3 is a view of a crystal in the combined region of a first part and a second part according to a first embodiment of the present invention, FIG. 4 is a view of a crystal in a second part within a metal layer according to a first embodiment of the present invention, FIG. 5 is a graph showing the size of crystal grains within a metal layer according to a first embodiment of the present invention, and FIG. 6 is a plan view showing the upper surface of a circuit board according to a first embodiment of the present invention.

[0062] Referring to FIGS. 1 to 6, a circuit board (10) according to the first embodiment of the present invention may include a build-up layer (100), a protective layer, a plurality of wiring portions, a plurality of via portions, and a metal layer (150).

[0063] The build-up layer (100) may include a plurality of insulating layers arranged in a vertical direction. For example, the build-up layer (100) may include a first insulating layer (101), a second insulating layer (102) disposed on the lower surface of the first insulating layer (101), a third insulating layer (103) disposed on the lower surface of the second insulating layer (102), a fourth insulating layer (104) disposed on the lower surface of the third insulating layer (103), a fifth insulating layer (105) disposed on the lower surface of the fourth insulating layer (104), and a sixth insulating layer (106) disposed on the lower surface of the fifth insulating layer (105). The number of insulating layers constituting the build-up layer (100) is exemplary, and the build-up layer (100) may include a greater or smaller number of insulating layers.

[0064] The first to sixth insulating layers (101, 102, 103, 104, 105, 106) may each be any insulating material, such as photocurable and / or thermosetting materials. As thermosetting insulating materials, an insulating material in which inorganic and / or organic fillers are dispersed within a resin, such as ABF (Ajinomoto Build-up Film), a product released by Ajinomoto, may be used, and a prepreg (PPG) containing glass fibers within a resin may be used. In addition, the resins described above may be, for example, epoxy resin, bismaleimide triazine resin (BT resin), phenolic resin, etc., and the inorganic and / or organic fillers may be provided with materials such as silica or plastic. When an insulating resin is used as a core, it may include a reinforcing material provided with glass fibers or aramid fibers. When the first to sixth insulating layers (101, 102, 103, 104, 105, 106) are photocurable insulators, the first to sixth insulating layers (101, 102, 103, 104, 105, 106) may each be a PID (Photo Imageable Dielectric). Additionally, some of the plurality of insulating layers may be provided with the same material as the protective layer.

[0065] The build-up layer (100) may include a hole (140). The hole (140) may have a shape that penetrates at least a portion of the build-up layer (100). The hole (140) may penetrate a plurality of insulating layers of a plurality of build-up layers (100). The hole (140) may be distinguished from a via hole in which a via portion is placed, in that it is not an area for electrical signal connection of the circuit board (10). The hole (140) may also be named a multilayer hole in that it penetrates a plurality of insulating layers. The hole (140) may have a shape that penetrates from one side of the build-up layer (100) to the other side. A metal layer (150) may be placed in the hole (140).

[0066] The hole (140) may include an upper region (141) having a shape in which the horizontal width gradually decreases as it extends downward from the upper surface of the build-up layer (100), and a lower region (142) having a shape in which the horizontal width gradually decreases as it extends upward from the lower surface of the build-up layer (100). The lower end of the upper region (141) and the upper end of the lower region (142) may be connected. By the upper region (141) and the lower region (142), the hole (140) may have an hourglass-shaped cross-sectional shape. For example, the upper region (141) may be defined from the upper surface of the first insulating layer (101) to the lower surface of the third insulating layer (103), and the lower region (142) may be defined from the lower surface of the third insulating layer (103) to the lower surface of the sixth insulating layer (106). Additionally, referring to FIG. 1, when the metal layer (150) includes a first part (160), the upper region (141) may be defined from the upper surface of the first insulating layer (101) to the upper surface of the first part (160). The first part (160) is positioned between the upper region (141) and the lower region (142), and is positioned such that its horizontal width is greater than that of the upper region (141) and the lower region (142).

[0067] The horizontal width of the hole (140) may be larger than the horizontal width of each of the multiple vias or multiple wiring sections. Accordingly, the placement area of ​​the metal layer (150) within the circuit board (10) can be secured widely.

[0068] The cross-sectional shape of the hole (140) may be square, but may also be circular.

[0069] The circuit board (10) may include a protective layer. The protective layer may include a first protective layer (191) and a second protective layer (192). The first protective layer (191) may be placed on the upper surface of the build-up layer (100). The first protective layer (191) may be placed on the upper surface of the first insulating layer (101). The second protective layer (192) may be placed on the lower surface of the build-up layer (100). The second protective layer (192) may be placed on the lower surface of the sixth insulating layer (106). When a semiconductor device is placed on the surface of the circuit board (10) using a material such as solder, the first protective layer (191) and the second protective layer (192) can perform the function of preventing short circuits between solders due to low wettability with the solder, and can prevent the problem of external contaminants penetrating into the build-up structure and reducing reliability. The first protective layer (191) and the second protective layer (192) may each be made of a photocurable insulating material. Accordingly, the first protective layer (190) and the second protective layer (198) are provided with a solder resist other than the aforementioned ABF, PPG, BT resin, and PID. However, they are not limited thereto and may be provided with various materials capable of performing low wettability with solder and thus preventing short circuits between solders as described above.

[0070] The circuit board (10) may include a circuit pattern. A plurality of wiring portions and a plurality of via portions may be arranged on the circuit board (10).

[0071] A plurality of wiring portions may each be disposed on the surface of a plurality of insulating layers. Here, the meaning of being disposed on the surface may also include the meaning that at least a portion of each of the plurality of wiring portions is embedded within a plurality of insulating layers or protective layers and exposed to the outside from the surface. A wiring portion may also be referred to as a pad portion.

[0072] A plurality of wiring sections may include a first wiring section (111) disposed on the lower surface of a first insulating layer (101), a second wiring section (112) disposed on the lower surface of a second insulating layer (102), a third wiring section (113) disposed on the lower surface of a third insulating layer (103), a fourth wiring section (114) disposed on the lower surface of a fourth insulating layer (104), and a fifth wiring section (115) disposed on the lower surface of a fifth insulating layer (105). The first to fifth wiring sections (111, 112, 113, 114, 115) each have a predetermined width in the horizontal direction within the build-up layer (100) and may be disposed along the vertical direction.

[0073] The circuit board (10) may include a pad portion. The pad portion may include a first pad portion (131) disposed on the upper surface of the build-up layer (100) and a second pad portion (132) disposed on the lower surface of the build-up layer (100). The first pad portion (131) may be disposed on the upper surface of the first insulating layer (101). The second pad portion (132) may be disposed on the lower surface of the sixth insulating layer (106). At least a portion of the first pad portion (131) may be embedded within the first protective layer (191). At least a portion of the second pad portion (132) may be embedded within the second protective layer (192).

[0074] The wiring portion is placed in each insulating layer and functions as a circuit that transmits signals. Additionally, the pad portion may function to connect with via electrodes for vertical connection between wiring portions placed within each insulating layer, or to connect with semiconductor devices and / or external circuit boards outside the circuit board. That is, the pad portion refers to a region of the wiring portion for connecting wiring portions placed within each insulating layer, such as vias, external circuit boards, and semiconductor devices. For the aforementioned functions, the horizontal width of the pad portion is provided to be wider than the horizontal width of the wiring portion. Furthermore, the wiring portion may have a longer length than the pad portion to implement circuit functions. Here, the width may be understood as following the first horizontal direction and the length as following the second horizontal direction; however, since this is a definition for convenience of explanation, it may also be understood as the width following the second horizontal direction and the length following the first horizontal direction to suit the circumstances.

[0075] The via may be a metallic material disposed in a via hole formed in each of a plurality of insulating layers to connect different wiring portions arranged in a vertical direction. Here, the via hole may have a shape that penetrates each of the plurality of insulating layers in a vertical direction.

[0076] The vias may include a first via (125) penetrating at least a portion of the first insulating layer (101), a second via (121) penetrating at least a portion of the second insulating layer (102), a third via (122) penetrating at least a portion of the third insulating layer (103), a fourth via (123) penetrating at least a portion of the fourth insulating layer (104), a fifth via (124) penetrating at least a portion of the fifth insulating layer (105), and a sixth via (126) penetrating at least a portion of the sixth insulating layer (106).

[0077] The first via section (125) can connect the first pad section (131) and the first wiring section (111). The second via section (121) can electrically connect the first wiring section (111) and the second wiring section (112). The third via section (122) can electrically connect the second wiring section (112) and the third wiring section (113). The fourth via section (123) can electrically connect the third wiring section (113) and the fourth wiring section (114). The fifth via section (124) can electrically connect the fourth wiring section (114) and the fifth wiring section (115). The sixth via section (126) can electrically connect the fifth wiring section (115) and the second pad section (132).

[0078] The first to third via sections (125, 121, 122) may each have a shape in which the horizontal width gradually decreases as it goes downward. The fourth to sixth via sections (123, 124, 126) may each have a shape in which the horizontal width gradually increases as it goes downward.

[0079] The vertical length of the fourth via (123) among the plurality of vias may be longer than the vertical length of any one of the first to third vias (125, 121, 122), the fifth via (124), and the sixth via (126). This is in consideration of the fact that the third wiring section (113) and the fourth wiring section (114) are arranged on the upper and lower surfaces, respectively, based on the fourth insulating layer (104), so that the first section (160), which will be described later, can be supported through the upper surface of the fourth insulating layer (104).

[0080] A plurality of wiring sections and a plurality of via sections are for signal transmission of the circuit board (10) and may not be electrically connected to the metal layer (150) to be described later.

[0081] The circuit board (10) may include a metal layer (150). The metal layer (150) may be a metal material. The metal layer (150) may be positioned to penetrate at least a portion of the build-up layer (100). The metal layer (150) may be positioned to penetrate the hole (140) of the build-up layer (100). A semiconductor chip (300, see FIG. 8) to be described later is placed on the metal layer (150), and accordingly, heat generated by the operation of the semiconductor chip (300) can be dissipated through the metal layer (150). The metal layer (150) may be named a heat dissipation part.

[0082] The area of ​​the upper and / or lower surface of the metal layer (150) may be 0.25 mm² or more and 25 mm² or less. This is in consideration of problems regarding yield or production efficiency that occur when the area of ​​the metal layer (150) is less than 0.25 mm², the contact area with the semiconductor chip for heat dissipation is insufficient and heat dissipation efficiency is reduced, and when the area of ​​the metal layer (150) exceeds 25 mm², the bending of the circuit board (10) increases or the area for arranging the wiring portion must be expanded.

[0083] The metal layer (150) may include an upper portion (154), a lower portion (155), and a central portion (151). The upper portion (154) and the lower portion (155) may each form the upper and lower portions of the metal layer (150). The upper portion (154) and the lower portion (155) may each be arranged to be offset in a horizontal direction from the build-up layer (100). The central portion (151) is arranged to connect the upper portion (154) and the lower portion (155), and may be arranged to overlap in a horizontal direction with respect to the build-up layer (100). The upper portion (154), the lower portion (155), and the central portion (151) are classified according to the arrangement area based on the build-up layer (100), and the metal layer (150) may be formed integrally by an electroplating method through the first portion (160).

[0084] The central portion (151) may be placed in the hole (140) of the build-up layer (100). In that it is placed in the hole (140), the central portion (151) may also be named a penetration portion. The central portion (151) may be placed between the upper portion (154) and the lower portion (155). The central portion (151) may include a first central portion (152) placed in the upper region (141) of the hole (140) and a second central portion (153) placed in the lower region (142) of the hole (140). The first central portion (152) may have a shape in which the width gradually decreases as it goes downward, corresponding to the shape of the upper region (141). The second central portion (153) may have a shape in which the width gradually increases as it goes downward, corresponding to the shape of the lower region (142). The first central portion (152) may be positioned to penetrate the first to third insulating layers (101, 102, 103). The second central portion (153) may be positioned to penetrate the fourth to sixth insulating layers (104, 105, 106). The horizontal width of the first central portion (152) and the second central portion (153) may be greater than the horizontal width of each of the plurality of wiring portions or plurality of via portions.

[0085] The upper portion (154) and the lower portion (155) can be positioned at the upper and lower ends of the central portion (151), respectively. The upper portion (154) and the lower portion (155) can also be named as protrusions in that they protrude vertically from the central portion (151), respectively. The upper portion (154) and the lower portion (155) can be positioned at the upper and lower ends of the build-up layer (100), respectively. The upper portion (154) can be positioned on the first insulating layer (101). The lower portion (155) can be positioned on the lower end of the sixth insulating layer (106). At least a portion of the upper portion (154) and the lower portion (155) can be embedded within the protective layers (191, 192) on the surface of the build-up layer (100), respectively.

[0086] The upper portion (154) and the lower portion (155) may have a rectangular cross-sectional shape. This is in consideration of the placement of the semiconductor chip (300) to be described later, and the semiconductor chip (300) may be placed on the upper portion (154) and the lower portion (155). However, this is not a limitation, and the cross-sectional shape of the upper portion (154) and the lower portion (155) may be circular.

[0087] The horizontal width of the upper portion (154) and the lower portion (155) may be greater than the horizontal width of the central portion (151) and / or the horizontal width of the hole (140). Accordingly, the bond between the metal layer (150) and the build-up layer (100) can be firmly formed through the upper portion (154) and the lower portion (155) positioned at both ends of the central portion (151). The horizontal width of the upper portion (154) and the lower portion (155) may be greater than the horizontal width of the first pad portion (131) or the second pad portion (132).

[0088] For example, the upper portion (154) and lower portion (155) of the metal layer (150) may include a first region that overlaps vertically with the central portion (151) and a second region that extends horizontally from the first region. The first region may overlap vertically with the central portion (151) and the hole (140) of the build-up layer (100). The second region is positioned vertically offset from the central portion (151) and may overlap vertically with a plurality of insulating layers within the build-up layer (100).

[0089] The metal layer (150) may include a first part (160) and a second part (180) disposed on one side and the other side of the first part (160), respectively. The first part (160) may also be named a seed layer. The first part (160) may be disposed between a plurality of second parts (180). The first part (160) may form a part of the aforementioned central part (151). The first part (160) may be disposed between the third insulating layer (103) or the fourth insulating layer (104). The first part (160) may be disposed such that at least a portion overlaps horizontally with the third wiring part (113). The first part (160) may be disposed such that at least a portion penetrates the inner wall of the hole (140). Accordingly, the first part (160) may have an area that overlaps vertically with at least a portion of a plurality of insulating layers within the build-up layer.

[0090] The horizontal length of the first part (160) may be longer than other regions within the central part (151). The first part (160) may function as a seed layer for forming a metal layer (150). A plating process for forming a metal layer (150) may be performed through the first part (160). Additionally, the strength of the metal layer (150) within the build-up layer (100) may be reinforced through relatively small crystal grains within the first part (160). Furthermore, the first part (160) may be positioned in the vertical center within the build-up layer (100) to minimize bending of the circuit board (10).

[0091] As illustrated in FIG. 2, the first part (160) may include a first-1 part (162) and a first-2 part (164). The first-2 part (164) may be placed on the first-1 part (162). The first-1 part (162) may have a first thickness (H1) in the vertical direction. The first-2 part (164) may have a second thickness (H2) that is thicker than the first thickness (H1) in the vertical direction. For example, the first thickness (H1) is 1 µm to 2 µm, and the vertical thickness of the first part (160), which is the sum of the first thickness (H1) and the second thickness (H2), may be 10 µm or more. For example, the vertical thickness of the first part (160) may be 20 µm to 30 µm. This takes into account that if the vertical thickness of the first part (160) is less than 10 µm, the bonding strength between the first part (160), which is the seed layer, and the plurality of insulating layers may decrease.

[0092] Part 1-1 (162) may be a metal foil. For example, the material of Part 1-1 (162) may be copper (Cu). Part 1-1 (162) may be a seed layer for forming Part 1-2 (164). Part 1-2 (162) may be formed by electroplating on one side of Part 1-1 (162). Part 1-2 (162) may be placed on the upper surface of Part 1-1 (162).

[0093] The first part (160) may include multiple regions with different grain sizes. For example, as shown in FIG. 3, the grain size forming the first-2 part (164) may be larger than the grain size forming the first-1 part (162). The grain size forming the first-2 part (164) may be larger than the grain size forming the second part (180). Accordingly, the first part (160), which functions as a seed layer for forming the second part (180), may have high thermal conductivity as it is composed of grains of multiple sizes, and the heat dissipation efficiency in the vertical central part of the circuit board (10) may be improved.

[0094] Part 1-1 (162) may be placed on the surface of Part 1 (160). The drawing shown in FIG. 3 is an Electron Backscatter-Diffraction (EBSD) image of a portion of the metal layer (150), showing the size of the crystal grains of the metal layer (150) and the crystal orientation of each crystal grain. As shown in FIG. 3, the size of the crystal grains constituting Part 1-1 (162) may be smaller than the size of the crystal grains forming Part 1-2 (164) or Part 2 (180). Accordingly, at the interface where Part 1 (160) and Part 2 (180) are joined, Part 1 (160) and Part 2 (180) can be more densely joined through Part 1-1 (162), which has a relatively small crystal grain size.

[0095] As illustrated in FIG. 3, the first-1 part (162) is positioned along the surface of the first part (160), and at least a portion may be positioned between the surface of the first part (160) and an insulating layer constituting the build-up layer.

[0096] According to the prior art, a seed layer for forming a metal layer is arranged by extending along a vertical direction on the inner wall of a through hole in an insulating layer. Subsequently, a metal layer is formed through a plating process. However, according to the prior art, during the plating process, plating proceeds isotropically on the seed layer arranged on the inner wall and on the seed layer on the first part, resulting in voids occurring inside the metal layer, concave dimples occurring on the upper surface of the metal layer, or protruding regions being formed on the surface of the metal layer, causing a problem of reduced flatness of the metal layer surface.

[0097] According to the present embodiment, the aforementioned problem can be prevented by not forming a seed layer on the inner wall of the hole (140) of the build-up layer so as not to cause such problems. That is, as shown in FIG. 3, the advantage is that the flatness of the surface of the metal layer (150) can be controlled by not forming a seed layer for electroplating of the metal layer (150) on the inner wall of the insulating layer and by arranging the size of the crystal grains of the first part (160) to be smaller than the crystal grains of the second part (180).

[0098] The circuit board (10) may include a plurality of power vias and power wirings that provide current to the first part (160). The plurality of power vias and power wirings may be electrically connected to the first part (160). Accordingly, current for plating the metal layer (150) may be provided to the first part (160).

[0099] A plurality of power via sections and power wiring sections can be electrically separated from the aforementioned first and second pad sections (131, 132), first to sixth via sections (125, 121, 122, 123, 124, 126), and first to fifth wiring sections (111, 112, 113, 114, 115).

[0100] A plurality of power wiring sections may include a first power wiring section (161) disposed on a first insulating layer (101), a second power wiring section (162) disposed on a second insulating layer (102), a third power wiring section (163) disposed on a third insulating layer (103), a fourth power wiring section (164) disposed on the lower surface of a fourth insulating layer (104), a fifth power wiring section (165) disposed on the lower surface of a fifth insulating layer (105), and a sixth power wiring section (166) disposed on the lower surface of a sixth insulating layer (106). Among these, the first power wiring section (161) disposed on the first insulating layer (101) and the sixth power wiring section (166) disposed on the lower surface of the sixth insulating layer (106) can each be connected to the upper portion (154) and the lower portion (155) of the metal layer (150). The surfaces of the first power wiring section (161) and the sixth power wiring section (166) are arranged to form a plane with the surfaces of the upper portion (154) and the lower portion (155), and accordingly, a wider space for placing semiconductor chips can be secured on the surface of the circuit board (10).

[0101] A plurality of power vias may include a first power via (171) penetrating at least a portion of the first insulating layer (101), a second power via (172) penetrating at least a portion of the second insulating layer (102), a third power via (173) penetrating at least a portion of the third insulating layer (103), a fourth power via (174) penetrating at least a portion of the fourth insulating layer (104), a fifth power via (175) penetrating at least a portion of the fifth insulating layer (105), and a sixth power via (176) penetrating at least a portion of the sixth insulating layer (106).

[0102] The first power via section (171) can electrically connect the first power wiring section (161) and the second power wiring section (162). The second power via section (172) can electrically connect the second power wiring section (162) and the third power wiring section (163). The third power via section (173) can electrically connect the third power wiring section (163) and the first section (160). The fourth power via section (174) can electrically connect the first section (160) and the fourth power wiring section (164). The fifth power via section (175) can electrically connect the fourth power wiring section (164) and the fifth power wiring section (165). The 6th power source via (176) can electrically connect the 5th power source wiring section (165) and the 6th power source wiring section (166).

[0103] Accordingly, power for plating the surface of the first-1 part (162) with the second part (164) and power for plating the surface of the first part (160) with the second part (180) can be provided through a plurality of power wiring sections and a plurality of power via sections, respectively.

[0104] The second part (180) may be disposed on one side and the other side of the first part (160), respectively. The second part (180) may be formed from the surface of the first part (160) by an electroplating method. The second part (180) may form a part of the central part (151) within the aforementioned metal layer (150), an upper part (154), and a lower part (155). The second part (180) may include a second-1 part (182) disposed on the first part (160) and a second-2 part disposed on the lower surface of the first part (160). The second-1 part (182) may have a shape in which the horizontal width gradually decreases as it approaches the first part (160), and the second-2 part (184) may have a shape in which the horizontal width gradually decreases as it approaches the first part (160).

[0105] Referring to the Electron Backcatter Diffraction (EBSD) illustrated in FIG. 4, crystals within the metal layer (150) forming the second part (180) may be arranged in multiple different crystal directions. The multiple crystals constituting the second part (180) may have different crystal directions such as (001), (101), (111), etc. Accordingly, the strength within the metal layer (150) may be increased through multiple crystals with different crystal directions.

[0106] The average size of the crystal grains in the metal layer (150) according to the embodiment may be 20 µm or less. More specifically, the average size of the crystal grains in the metal layer (150) may be 2 µm or less.

[0107] In the graph of FIG. 5, the Y-axis represents the Area-weighted Fracton within the metal layer (150), and the X-axis represents the size of the crystal grains of the metal layer (150). Accordingly, as a result of measuring the average size of the multiple crystal grains constituting the metal layer (150) through the graph of FIG. 5, the average size of the crystal grains forming the metal layer (150) according to the present embodiment was measured to be 1.07 μm. Therefore, as the metal layer (150) is implemented by an electroplating method, the size of the crystal grains constituting the metal layer (150) is reduced compared to the conventional method, which increases the durability of the metal layer (150) and has the advantage of having high thermal conductivity.

[0108] Conventional heat dissipation structures of circuit boards are implemented by embedding a single heat dissipation block (Coin) in a hole within the build-up layer. However, there was a problem in that productivity was low due to the structure of directly mounting the heat dissipation block within the build-up layer, and the design freedom was reduced because the shape of the heat dissipation block was controlled according to the shape of the hole within the build-up layer.

[0109] According to the present embodiment, as the second part (180) is implemented by the electrolytic plating method through the first part (160), the shape of the metal layer (150) can be formed in various ways corresponding to the shape of the hole (140), and since a separate process for bonding with the build-up layer is omitted, productivity can also be improved.

[0110] In addition, since the metal layer (150) is formed by an electrolytic plating method, the size of the crystal grains constituting the metal layer (150) is reduced compared to conventional methods, so it can have high thermal conductivity and thus improve heat dissipation efficiency.

[0111] FIG. 7 is a perspective view of a semiconductor package according to a first embodiment of the present invention, and FIG. 8 is a cross-sectional view of a semiconductor package according to a first embodiment of the present invention.

[0112] Referring to FIGS. 1, 7 and 8, a semiconductor package according to a first embodiment of the present invention may include a semiconductor chip (300) coupled to a circuit board (10). The semiconductor chip (300) is disposed on a first protective layer (191) and may be electrically connected to a first pad portion (131) through a wire (310).

[0113] As described above, the semiconductor chip (300) can be arranged to overlap vertically with the hole (140) of the circuit board (10). The semiconductor chip (300) can be arranged to overlap vertically with the metal layer (150).

[0114] The lower surface of the semiconductor chip (300) is supported by the upper surface of the metal layer (150), and accordingly, heat generated by the operation of the semiconductor chip (300) can be dissipated through the metal layer (150).

[0115] Meanwhile, a plurality of semiconductor chips (300) may be provided and placed on a circuit board (10). In this case, as shown in FIG. 7, the circuit board (10) may have a plurality of holes (140) and metal layers (150) corresponding to the number of semiconductor chips (300).

[0116] A semiconductor package may include a molding portion (400) disposed on a circuit board (10). A semiconductor chip (300) including a wire (310) may be embedded within the molding portion (400). The molding portion (400) may be bonded to the surface of a protective layer. Accordingly, the bonding state of the semiconductor chip (300) on the circuit board (10) can be firmly maintained.

[0117] Hereinafter, a circuit board according to the second embodiment of the present invention will be described.

[0118] FIG. 9 is a cross-sectional view of a circuit board according to a second embodiment of the present invention, FIG. 10 is an enlarged view of one area of ​​FIG. 9, and FIG. 11 is a plan view showing the upper surface of a circuit board according to a second embodiment of the present invention.

[0119] Referring to FIGS. 9 to 11, a circuit board (20) according to a second embodiment of the present invention may include a build-up structure (1100).

[0120] The build-up structure (1100) may include a plurality of insulating layers, a plurality of wiring portions, and a plurality of via portions.

[0121] The build-up structure (1100) may include a plurality of insulating layers stacked along a vertical direction. For example, the build-up structure (1100) may include a first insulating layer (1101), a second insulating layer (1102) disposed on the first insulating layer (1101), a third insulating layer (1103) disposed on the second insulating layer (1102), a fourth insulating layer (1104) disposed on the third insulating layer (1103), a fifth insulating layer (1105) disposed on the fourth insulating layer (1104), and a sixth insulating layer (1106) disposed on the fifth insulating layer (1105). The first insulating layer (1101) and the sixth insulating layer (1106) may each be disposed on one side and the other side of the build-up structure (1100). The number of insulating layers constituting the build-up structure (1100) is exemplary, and the build-up structure (1100) may include more or fewer insulating layers.

[0122] The first to sixth insulating layers (1101, 1102, 1103, 1104, 1105, 1106) may each be any insulating material, such as photocurable and / or thermosetting materials. As thermosetting insulating materials, insulating materials in which inorganic and / or organic fillers are dispersed within a resin, such as ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Corporation, may be used, and prepregs (PPG) containing glass fibers within a resin may be used. In addition, the resins described above may be, for example, epoxy resin, bismaleimide triazine resin (BT resin), phenolic resin, etc., and the inorganic and / or organic fillers may be provided with materials such as silica or plastic. When an insulating resin is used as a core, it may include a reinforcing material provided with glass fibers or aramid fibers. When the first to sixth insulating layers (1101, 1102, 1103, 1104, 1105, 1106) are photocurable insulators, the first to sixth insulating layers (1101, 1102, 1103, 1104, 1105, 1106) may each be a PID (Photo Imageable Dielectric). Additionally, some of the plurality of insulating layers may be provided with the same material as the protective layer.

[0123] The build-up structure (1100) may include a hole (1140). The hole (1140) may be positioned to penetrate at least a portion of the build-up structure (1100). For example, the hole (1140) may be shaped to penetrate from one side of the build-up structure (1100) to the other side. The horizontal width of the hole (1140) may be larger than the horizontal width of each of the multiple vias or multiple wiring sections. Accordingly, the placement area of ​​the metal part (1150) within the circuit board (20) can be secured widely.

[0124] The hole (1140) may have a shape that penetrates each of the first to sixth insulating layers (1101, 1102, 1103, 1104, 1105, 1106). In this case, the hole (1140) may include a first hole penetrating the first insulating layer (1101), a second hole penetrating the second insulating layer (1102), a third hole penetrating the third insulating layer (1103), a fourth hole penetrating the fourth insulating layer (1104), a fifth hole penetrating the fifth insulating layer (1105), and a sixth hole penetrating the sixth insulating layer (1106). Each of the first to third holes may have a shape in which the horizontal width gradually decreases as it faces the fourth insulating layer (1104). The fourth to sixth holes may each have a shape in which the horizontal width gradually decreases as it faces the third insulating layer (1103). Each hole formed in a plurality of insulating layers within the build-up structure (1100) may have its expansion direction reversed at the third insulating layer (1103) or the fourth insulating layer (1104) positioned at the vertical center of the build-up structure (1100). Accordingly, the metal part (1150) described later includes regions corresponding to the shape of each hole, thereby minimizing the bending phenomenon of the circuit board (20).

[0125] The cross-sectional shape of the hole (1140) may be square, but may also be circular.

[0126] A metal part (1150) can be placed in the hole (1140).

[0127] The build-up structure (1100) may include a circuit layer for transmitting electrical signals and / or power to an electronic device such as a semiconductor chip. The circuit layer may be disposed between a plurality of insulating layers and a plurality of insulating layers. The circuit layer may include a plurality of wiring portions and a plurality of via portions.

[0128] A plurality of wiring sections may each be disposed on the surface of a plurality of insulating layers. Here, the meaning of being disposed on the surface may also include the meaning that at least a portion of the plurality of wiring sections is embedded within each of the plurality of insulating layers or protective layers and exposed to the outside from the surface. A wiring section may also be referred to as a metal layer. Furthermore, the surface of the plurality of insulating layers includes a first surface, a second surface, and a side between the first surface and the second surface. Here, the first surface of the insulating layer may be understood as the upper surface, and the second surface of the insulating layer may be understood as the lower surface. The meaning of a wiring section being disposed on the surface is that it is disposed on at least one of the first surface, the second surface, or the side between the plurality of insulating layers. A structure may be formed in which wiring sections are disposed on both the first surface and the second surface of some of the insulating layers, and wiring sections are disposed on only one of the first surface or the second surface of other parts of the plurality of insulating layers.

[0129] A plurality of wiring sections may include a first wiring section (1111) disposed on the lower surface of a first insulating layer (1101), a second wiring section (1112) disposed on the lower surface of a second insulating layer (1102), a third wiring section (1113) disposed on the lower surface of a third insulating layer (1103), a fourth wiring section (1114) disposed on the upper surface of a third insulating layer (1103), a fifth wiring section (1115) disposed on the upper surface of a fourth insulating layer (1104), a sixth wiring section (1116) disposed on the upper surface of a fifth insulating layer (1105), and a seventh wiring section (1117) disposed on the upper surface of a sixth insulating layer (1106).

[0130] The via may be a metallic material disposed in a via hole formed in each of a plurality of insulating layers to connect a plurality of wiring portions facing each other in a vertical direction. Here, the via hole penetrates at least a portion of each of the plurality of insulating layers in a vertical direction, and a via may be disposed within the via hole.

[0131] The via section may include a first via section (1121) penetrating at least a portion of the first insulating layer (1101), a second via section (1122) penetrating at least a portion of the second insulating layer (1102), a third via section (1123) penetrating at least a portion of the third insulating layer (1103), a fourth via section (1124) penetrating at least a portion of the fourth insulating layer (1104), a fifth via section (1125) penetrating at least a portion of the fifth insulating layer (1105), and a sixth via section (1126) penetrating at least a portion of the sixth insulating layer (1106).

[0132] The first via section (1121) can electrically connect the first wiring section (1111) and the second wiring section (1112). The second via section (1122) can electrically connect the second wiring section (1112) and the third wiring section (1113). The third via section (1123) can electrically connect the third wiring section (1113) and the fourth wiring section (1114). The fourth via section (1124) can electrically connect the fourth wiring section (1114) and the fifth wiring section (1115). The fifth via section (1125) can electrically connect the fifth wiring section (1115) and the sixth wiring section (1116). The 6th via (1126) can electrically connect the 6th wiring section (1116) and the 7th wiring section (1117).

[0133] The first to third vias (1121, 1122, 1123) may each have a shape in which the horizontal width gradually decreases as it goes upward. The fourth to sixth vias (1124, 1125, 1126) may each have a shape in which the horizontal width gradually decreases as it goes downward.

[0134] The vertical length of the third via (1123) among the multiple vias may be longer than the vertical length of the other vias. This is because the third wiring section (1113) and the fourth wiring section (1114) are arranged on the upper and lower surfaces, respectively, based on the third insulating layer (1103). In some cases, the third insulating layer (1103) may function as a core layer, and in this case, the material of the third insulating layer (1103) may be different from the material of the first and second insulating layers (1101, 1102) and the fourth to sixth insulating layers (1104, 1105, 1106). For example, the material of the third insulating layer (1103) may be a prepreg including resin and glass fiber.

[0135] The circuit board (20) may include a metal part (1150). The metal part (1150) may be a metal material. The metal part (1150) may be positioned to penetrate at least a portion of the build-up structure (1100). The metal part (1150) may be positioned to penetrate a hole (1140) of the build-up structure (1100). A semiconductor chip (1300, see FIG. 17) to be described later is placed on the metal part (1150), and accordingly, heat generated by the operation of the semiconductor chip (1300) can be dissipated through the metal part (1150). The metal part (1150) may also be named a heat dissipation part.

[0136] The metal part (1150) may include a first part (1161) and a second part (1170) positioned above and below the first part (1161). The first part (1161) may be positioned to overlap the build-up structure (1100) along the horizontal direction. The second part (1170) may be positioned offset from the build-up structure (1100) along the horizontal direction. The first part (1161) and the second part (1170) may be formed as a single body.

[0137] The first part (1161) may be placed in the hole (1140). In that it is placed in the hole (1140), the first part (1161) may also be named a penetration part. The first part (1161) may include a first-1 part (1156) penetrating at least a portion of the first insulating layer (1101), a first-2 part (1154) penetrating at least a portion of the second insulating layer (1102), a first-3 part (1152) penetrating at least a portion of the third insulating layer (1103), a first-4 part (1151) penetrating at least a portion of the fourth insulating layer (1104), a first-5 part (1153) penetrating at least a portion of the fifth insulating layer (1105), and a first-6 part (1155) penetrating at least a portion of the sixth insulating layer (1106).

[0138] Parts 1-1 to 1-3 (1156, 1154, 1152) may each have a shape in which the horizontal width gradually decreases as it goes upward. Parts 1-4 to 1-6 (1151, 1153, 1155) may each have a shape in which the horizontal width gradually decreases as it goes downward.

[0139] The cross-sectional area of ​​the first part (1161) may be 0.25 mm2 or more and 25 mm2 or less. If the cross-sectional area of ​​the first part (1161) is 0.25 mm2 or less, heat transferred from the second part (1170) may not be efficiently conducted, and thus the heat dissipation efficiency may decrease. Additionally, if the cross-sectional area of ​​the first part (1161) exceeds 25 mm2, the placement space of the remaining area excluding the heat dissipation area within the circuit board (20) may be excessively reduced.

[0140] The second part (1170) may be positioned at the top and bottom of the first part (1161), respectively. The second part (1170) may also be named a protrusion in that it protrudes vertically from the first part (1161). The second part (1170) may be positioned at the top and bottom surfaces of the build-up structure (1100), respectively. The second part (1170) may include a second-1 part positioned on the surface of the first insulating layer (1101) and a second-2 part positioned on the surface of the sixth insulating layer (1106). The second-1 part and the second-2 part may each be embedded in the surface of the build-up structure (1100) by a molding part to be described later. At least one of the second-1 part and the second-2 part may be in contact with the semiconductor chip (1300).

[0141] The horizontal width of the second part (1170) may be larger than the horizontal width of the first part (1160). Accordingly, the contact area of ​​the semiconductor chip (1300) through the surface of the second part (1170) may be increased, and the placement area of ​​the first part (1161) for forming the second part (1170) within the circuit board (20) may be reduced. Additionally, the horizontal width of the second part (1170) may be formed to be larger than the horizontal width of the hole (1140) where the first part (1160) is placed, thereby maintaining a more robust bonding force with the surface of the build-up structure (1100) through the second part (1170).

[0142] The second part (1170) may have a rectangular cross-sectional shape. This is in consideration of the placement of the semiconductor chip (1300) to be described later, and the semiconductor chip (1300) may be placed on the second part (1170). However, this is not a limitation, and the cross-sectional shape of the second part (1170) may be circular.

[0143] The circuit board (20) may include a plating section (1160). The plating section (1160) may function as a seed layer for forming a metal section (1150). The plating section (1160) may be placed in the first section (1161). For example, the plating section (1160) may be placed between the first-third section (1152) and the first-fourth section (1151). The plating section (1160) may be placed between the third insulating layer (1103) and the fourth insulating layer (1104). The plating section (1160) may be embedded within the third insulating layer (1103) or the fourth insulating layer (1104). The plating section (1160) may be placed such that at least a portion overlaps horizontally with the fourth wiring section (1114). The horizontal length of the plating section (1160) may be longer than the horizontal length of the first section (1161). The horizontal length of the plating section (1160) may be the same as the horizontal length of the second section (1170).

[0144] Through the plating section (1160), not only is the plating process of the metal section (1150) carried out, but the strength of the metal section (1150) can also be reinforced within the build-up structure (1100). Additionally, the plating section (1160) is positioned in the vertical center within the build-up structure (1100) to minimize bending of the circuit board (20).

[0145] The size of the crystal grains constituting the plating portion (1160) may be smaller than the size of the crystal grains constituting the metal portion (1150). Accordingly, multiple regions having different crystal grain sizes are formed within the heat dissipation region, thereby increasing the strength of the heat dissipation region.

[0146] As illustrated in FIG. 10, the inner wall where the first part (1161) of each of the plurality of insulating layers constituting the build-up structure (1100) is disposed, or the side connecting the upper and lower surfaces of each of the first-1 to first-6 parts (1156, 1154, 1152, 1151, 1153, 1155), may be arranged at an angle to form a predetermined angle with respect to one surface of each of the plurality of insulating layers. For example, with respect to the upper surface of the plating part (1160) parallel to one surface of each of the plurality of insulating layers, the side of the first-4 part (1151) disposed on the plating part (1160) or the inner wall of the fourth insulating layer (1104) where the first-4 part (1151) is disposed may form a first angle (A) with respect to the upper surface of the plating part (1160). The first angle (A) may be 45 degrees or greater and 85 degrees or less. If the first angle (A) is less than 45 degrees, the arrangement area of ​​the metal part (1150) in the horizontal direction becomes excessively wide, increasing the amount of plating and causing a problem where the plating process is not carried out efficiently. If the first angle (A) exceeds 85 degrees, the inner wall of each insulating layer within the build-up structure (1100) forming the arrangement area of ​​the metal part (1150) may collapse, and there is a problem where the bonding force between the metal part (1150) and the inner wall of the insulating layer is weakened. Meanwhile, the aforementioned first angle (A) is defined based on the area where the horizontal width of parts 1-1 to 1-6 (1156, 1154, 1152, 1151, 1153, 1155) increases. Based on one side of each of parts 1-1 to 1-6 (1156, 1154, 1152, 1151, 1153, 1155) and another side having a wider horizontal width than said one side, the first angle (A) can be defined as the angle formed by one side of any one of parts 1-1 to 1-6 (1156, 1154, 1152, 1151, 1153, 1155) having a relatively smaller width and one side of any one of the plurality of insulating layers close to said one side.

[0147] According to the above structure, there is an advantage in that the reliability of the circuit board (20) can be improved by increasing the adhesion between the metal part (1150) and the insulating layer constituting the build-up structure (1100).

[0148] FIGS. 12 to 16 are drawings for explaining the manufacturing process of a circuit board according to a second embodiment of the present invention.

[0149] The manufacturing process of a circuit board according to the second embodiment of the present invention may include the step of forming a plating portion (1160) and a fourth wiring portion (1114) between the third insulating layer (1103) and the fourth insulating layer (1104), as shown in FIG. 12, and then placing a foil (1210) on the lower surface of the third insulating layer (1103) and the upper surface of the fourth insulating layer (1104), respectively. The foil (1210) may function as a seed layer for forming a via portion connected to the fourth wiring portion (1114).

[0150] Next, as illustrated in FIG. 13, heat dissipation holes (1222, 1224) for the arrangement of via holes and the first part (1161) can be formed through the lower surface of the third insulating layer (1103) and the upper surface of the fourth insulating layer (1104). The via holes and heat dissipation holes (1222, 1224) can be formed by a laser processing method. Accordingly, the third insulating layer (1103) and the fourth insulating layer (1104) can each have heat dissipation holes (1222, 1224) for the formation of the first-third part (1152) and the first-fourth part (1151), and via holes for the formation of the third via part (1123) and the fourth via part (1124) connected to the fourth wiring part (1114). After processing the via holes and heat dissipation holes (1222, 1224), a chemical copper (not shown), which serves as a seed layer for a plating process, may be deposited on the inner wall of the via hole or the inner wall of the heat dissipation hole (1222, 1224). The size of the crystal grains of the chemical copper may be smaller than the size of the crystal grains of the first-3 part (1152), the first-4 part (1151), the third via part (1123), and the fourth via part (1124). However, the chemical copper may be omitted.

[0151] Next, as illustrated in FIG. 14, an etching resist film (1230) having a hole pattern (1232) corresponding to the formation area of ​​heat dissipation holes (1222, 1224) and via holes may be attached to the lower surface of the third insulating layer (1103) and the upper surface of the fourth insulating layer (1104). Through ultraviolet exposure of the etching resist film (1230) and a photoresist development process, the heat dissipation holes (1222, 1224) and via holes may be opened in a vertical direction.

[0152] Next, as shown in FIG. 15, heat dissipation holes (1222, 1224) and via holes can be filled with a conductive conductor by an electrolytic plating method to form the first-third part (1152), the first-fourth part (1151), the third wiring part (1113), and the fifth wiring part (1115).

[0153] Afterwards, as shown in FIG. 16, the etching resist film (1230) can be removed from the surface of the insulating layer by etching. In this case, the foil (1210) placed between the etching resist film (1230) and the surface of the insulating layer can be removed together.

[0154] Afterwards, the second insulating layer (1102) and the fifth insulating layer (1105) are respectively laminated on the surface of the third insulating layer (1103) and the surface of the fourth insulating layer (1104), and the aforementioned process is repeated with foil placement on the surface in the same way, so that a circuit board (20) can be manufactured.

[0155] FIG. 17 is a cross-sectional view of a semiconductor package according to a second embodiment of the present invention, and FIG. 18 is a perspective view of a semiconductor package according to a second embodiment of the present invention.

[0156] Referring to FIGS. 9, 17 and 18, a semiconductor package according to a second embodiment of the present invention may include a semiconductor chip (1300) coupled to a circuit board (20). The semiconductor chip (1300) is placed on a build-up structure (1100) and may be electrically connected to a wiring portion (1117) through a wire (1310).

[0157] As described above, the semiconductor chip (1300) can be arranged to overlap vertically with the hole (1140) of the circuit board (20). The semiconductor chip (1300) can be arranged to overlap vertically with the metal part (1150).

[0158] The lower surface of the semiconductor chip (1300) is supported by the upper surface of the metal part (1150), and accordingly, heat generated by the operation of the semiconductor chip (1300) can be dissipated through the metal part (1150).

[0159] Meanwhile, the semiconductor chips (1300) may be provided in multiple numbers and placed on the circuit board (20). In this case, as shown in FIG. 18, the circuit board (20) may be provided with multiple holes (1140) and metal parts (1150) corresponding to the number of semiconductor chips (1300).

[0160] The semiconductor package may include a molding portion (1400) disposed on a circuit board (20). A semiconductor chip (1300) including a wire (1310) may be embedded within the molding portion (1400). The molding portion (1400) may be disposed on the surface of a build-up structure (1100). Accordingly, the bonding state of the semiconductor chip (1300) on the circuit board (20) can be firmly maintained.

[0161] FIG. 19 is a cross-sectional view of a circuit board according to a third embodiment of the present invention.

[0162] In this embodiment, other parts are identical to the second embodiment, except for the difference in the shape of the metal part. Therefore, below, only the characteristic parts of this embodiment will be described, and for the remaining parts, the description according to the second embodiment will be used.

[0163] Referring to FIG. 19, the circuit board (30) according to the present embodiment may include a metal part (1550). The metal part (1550) may include a first part (1510, 1520) and a second part (1570, 1580) disposed on one side and the other side of the first part (1510, 1520).

[0164] The second part (1570, 1580) may include a second-1 part (1570) disposed on the upper surface of the build-up structure (1100) and a second-2 part (1580) disposed on the lower surface of the build-up structure (1100). The second-1 part (1570) may include a first surface (1572) that contacts the upper surface of the build-up structure (1100), and the second-2 part (1580) may include a second surface (1582) that contacts the lower surface of the build-up structure (1100).

[0165] The metal part (1550) includes a first surface (1572) located on the same plane as the upper surface of the build-up structure (1100) and a second surface (1582) located on the same plane as the lower surface of the build-up structure (1100), and the first surface (1572) and the second surface (1582) may have a shape that is asymmetric in the vertical direction. That is, with respect to the horizontal center axis (L) of the first surface (1572), the horizontal length of the second surface (1582) may be different from the horizontal length of the first surface (1572). The second-1 part (1570) and the second-2 part (1580) may have a shape that is asymmetric in the vertical direction. The horizontal length of the second-1 part (1570) may be different from the horizontal length of the second-2 part (1580). The horizontal length of Part 2-1 (1570) may be shorter than the horizontal length of Part 2-2 (1580). The horizontal length of the first surface (1572) may be shorter than the horizontal length of the second surface (1582).

[0166] According to the above structure, the horizontal length of the second-1 part (1570) forming the placement surface of the semiconductor chip is formed to be relatively short to support the semiconductor chip, and at the same time, the size of the heat dissipation area where heat is conducted is formed to be relatively large to improve heat dissipation efficiency.

[0167] In addition, compared to a structure in which the same heat transfer occurs in a high-density area and a low-density area for impedance matching, according to the present embodiment, a heat dissipation structure that takes into account the circuit density for impedance matching can be implemented through an asymmetric structure between the first surface (1572) and the second surface (1582), thereby having the advantage of improving the reliability of the circuit board (30). That is, as it is implemented so that an area with a relatively low circuit density is placed on the first surface (1572) and an area with a relatively high circuit density is placed on the second surface (1582), there is an advantage in that the shape of the metal part (1550) for improving heat dissipation efficiency by area can be adjusted in various ways.

[0168] However, the semiconductor chip is not limited to being placed in the 2-1 section (1570). If the cross-sectional area of ​​the semiconductor chip is large, the semiconductor chip may be placed on the surface of the 2-2 section (1580) and heat dissipation may occur in the direction of the 2-1 section (1570). In this case, there is an advantage that the amount of plating required to form the heat dissipation area can be reduced, and at the same time, heat dissipation of a semiconductor chip with a larger area can be achieved.

[0169] Meanwhile, the first part (1510, 1520) may include a first-1 part (1520) connected to the second-1 part (1570) and a first-2 part (1510) connected to the second-2 part (1580), based on the plating part (1160). The first-1 part (1520) may be arranged to penetrate the fourth to sixth insulating layers (1104, 1105, 1106), and the first-2 part (1510) may be arranged to penetrate the first to third insulating layers (1101, 1102, 1103).

[0170] Part 1-1 (1520) and Part 1-2 (1510) may have an asymmetrical shape in the vertical direction. The horizontal length of Part 1-1 (1520) may differ from the horizontal length of Part 1-2 (1510). The horizontal length of Part 1-1 (1520) may be longer than the horizontal length of Part 1-2 (1510). Accordingly, the horizontal length of Part 1-2 (1510), which is connected to Part 2-2 (1580), which has a relatively long horizontal length, is formed longer, thereby making the plating process of Part 2-2 (1580) easier. Additionally, the horizontal length of Part 1-1 (1520), which is connected to Part 2-1 (1570), which has a relatively short horizontal length, is formed shorter, thereby securing a wider space for forming wiring and via portions in the bonding area of ​​the semiconductor chip.

[0171] FIG. 20 is a cross-sectional view of a circuit board according to the fourth embodiment of the present invention.

[0172] In this embodiment, other parts are identical to the second embodiment, except for the difference in the shape of the metal part. Therefore, below, only the characteristic parts of this embodiment will be described, and for the remaining parts, the description according to the second embodiment will be used.

[0173] Referring to FIG. 20, the circuit board according to the present embodiment may include a metal part (1650). The metal part (1650) may include a first part (1610, 1620) and a second part (1670, 1680) disposed on one side and the other side of the first part (1610, 1620).

[0174] The first part (1610, 1620) may include a first-1 part (1610) disposed on the upper surface of the plating part (1160) and a first-2 part (1620) disposed on the lower surface of the plating part (1160). The first-1 part (1610) and the first-2 part (1620) may have an asymmetrical shape in the vertical direction. The first-1 part (1610) may include a first region (1612) and a second region (1614) that are spaced apart in the horizontal direction. The first region (1612) and the second region (1614) are each disposed to penetrate the fourth to sixth insulating layers (1104, 1105, 1106) and may be spaced apart in the horizontal direction. Between the first region (1612) and the second region (1614), one region of the fourth to sixth insulating layers (1104, 1105, 1106) may be disposed. The horizontal width of each of the first region (1612) and the second region (1614) may be shorter than the horizontal width of the first-second part (1620). The horizontal width of each of the first region (1612) and the second region (1614) may be shorter than half the horizontal width of the first-second part (1620).

[0175] Accordingly, heat generated from the semiconductor chip can be dispersed through multiple paths, thereby improving heat dissipation efficiency. Additionally, by forming a vertical support structure of multiple regions (1612, 1614) through the first and second parts (1620), the metal part (1150) within the build-up structure (1100) can be firmly supported.

[0176] Meanwhile, although not illustrated, the 2-1 part (1670) and the 2-2 part (1680) constituting the 2-2 part (1670, 1680) may have different horizontal lengths from each other, and for example, the horizontal length of the 2-1 part (1670) may be shorter than the horizontal length of the 2-2 part (1680).

[0177] In the foregoing, although all components constituting an embodiment of the present invention have been described as being combined or operating in combination, the present invention is not necessarily limited to such embodiments. That is, within the scope of the purpose of the present invention, all components may be selectively combined in one or more ways to operate. Furthermore, terms such as "include," "constitute," or "have" described above, unless specifically stated otherwise, mean that the relevant component may be inherent; thus, they should be interpreted as allowing for the inclusion of additional components rather than excluding other components. All terms, including technical or scientific terms, have the same meaning as generally understood by those skilled in the art to which the present invention pertains, unless otherwise defined. Terms commonly used, such as those defined in advance, should be interpreted in accordance with their meaning in the context of the relevant technology and should not be interpreted in an ideal or overly formal sense unless explicitly defined in the present invention.

[0178] The foregoing description is merely an illustrative explanation of the technical concept of the present invention, and those skilled in the art to which the present invention pertains will be able to make various modifications and variations within the scope of the essential characteristics of the present invention. Accordingly, the embodiments disclosed in the present invention are intended to explain, not limit, the technical concept of the present invention, and the scope of the technical concept of the present invention is not limited by such embodiments. The scope of protection of the present invention shall be interpreted by the claims below, and all technical concepts within an equivalent scope shall be interpreted as being included within the scope of rights of the present invention.

[0179] Meanwhile, when a circuit board having the features of the invention described above is used in IT devices or home appliances such as smartphones, server computers, and TVs, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the features of the invention performs a semiconductor package function, it can safely protect the semiconductor chip from external moisture or contaminants, and can resolve issues such as leakage current, electrical short circuits between terminals, or electrical open circuits of terminals supplying power to the semiconductor chip. In addition, when it is responsible for signal transmission, it can resolve noise issues. Through this, the circuit board having the features of the invention described above enables the stable operation of IT devices or home appliances, thereby allowing the entire product and the circuit board to which the invention is applied to achieve functional integration or technical interoperability.

[0180] When a circuit board having the features of the invention described above is used in a transportation device such as a vehicle, it can resolve the problem of signal distortion transmitted to the transportation device, or safely protect a semiconductor chip controlling the transportation device from the outside, and further improve the stability of the transportation device by resolving problems such as leakage current, electrical short circuits between terminals, or electrical open circuits of terminals supplying power to the semiconductor chip. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

Claims

1. A build-up layer including a plurality of insulating layers stacked along a vertical direction; and It includes a metal layer penetrating at least a portion of the above-mentioned build-up layer, and The metal layer comprises a first part and a second part disposed on one side and the other side of the first part, and A circuit board in which the size of the crystal grains in at least one region of the first part is smaller than the size of the crystal grains in the second part.

2. In Paragraph 1, The above build-up layer includes a hole in which the metal layer is disposed, and The first part above is a circuit board positioned to penetrate the inner wall of the hole.

3. In Paragraph 1, The second part above is a circuit board protruding from the surface of the build-up structure.

4. In Paragraph 1, The above-mentioned first part includes a first-1 part arranged in a vertical direction and a first-2 part, and At least one region of the above-mentioned first part is the first-1 part, and A circuit board in which the size of the crystal grains in the above 1-1 part is smaller than the size of the crystal grains in the above 1-2 part.

5. In Paragraph 4, A circuit board in which the vertical thickness of the above 1-1 part is smaller than the vertical thickness of the above 1-2 part.

6. In Paragraph 1, It includes a plurality of power wiring portions disposed respectively on the plurality of insulating layers, and a plurality of power via portions penetrating at least a portion of the plurality of insulating layers to electrically connect the plurality of power wiring portions. The plurality of power wiring sections and the plurality of power via sections are circuit boards connected to the first section.

7. In Paragraph 6, The metal layer comprises an upper portion disposed on the upper surface of the build-up layer and a lower portion disposed on the lower surface of the build-up layer, and The above upper portion and the above lower portion are each circuit boards connected to the plurality of power wiring portions disposed on the surface of the build-up layer.

8. In Paragraph 7, A circuit board in which the horizontal length of the upper portion and the lower portion is longer than the horizontal length of the central portion connecting the upper portion and the lower portion.

9. In Paragraph 4, A circuit board having a vertical thickness of 1 µm to 2 µm in the above 1-1 part.

10. A build-up layer including a plurality of insulating layers stacked along the vertical direction; A metal layer penetrating at least a portion of the above-mentioned build-up layer; and It includes a semiconductor chip disposed on the metal layer above, The metal layer comprises a first part and a second part disposed on one side and the other side of the first part, and A semiconductor package in which the size of the crystal grains in at least one region of the first part is smaller than the size of the crystal grains in the second part.

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