Circuit board and semiconductor package

Abstract

This circuit board includes: a core layer including an upper surface and a lower surface; a first build-up layer disposed on the upper surface of the core layer; and a second build-up layer disposed on the lower surface of the core layer, wherein at least one of the first build-up layer and the second build-up layer includes a protrusion part extending through at least a part of the core layer.

Description

Circuit boards and semiconductor packages

[0001] The present embodiment relates to a circuit board and a semiconductor package.

[0002]

[0003] Recently, technology related to electronic products has been progressing toward multifunctionality and high speed, and to respond to this trend, semiconductor chip manufacturing technology is also developing rapidly.

[0004] In particular, the thickness of circuit boards used for the miniaturization of finished electronic products is also being reduced, and technologies related to multilayer circuit boards, which comprise more circuit layers within a circuit board of the same thickness, are being actively researched.

[0005] A circuit board is formed by printing circuit line patterns using a conductive material, such as copper, onto an electrically insulating substrate; it is a general term for a board immediately before electronic components are mounted. To densely mount many different types of electronic components on a flat surface, the mounting positions of each component are determined, and circuit patterns connecting the components are printed on the surface of the flat plate to secure them.

[0006] The circuit board includes a plurality of insulating layers arranged in a vertical direction. The plurality of insulating layers can be electrically connected by wiring layers arranged on each surface and via electrodes that connect different wiring layers in a vertical direction.

[0007] According to the above structure, there are problems such as reduced yield due to increased height and signal loss due to increased signal transmission length.

[0008]

[0009] The present invention addresses the problem that recent circuit boards, which are trending toward high multilayer and large area, have problems such as low productivity and reduced yield when arranging via electrodes in the core layer as the thickness of the core layer increases to prevent warping. The present invention provides a circuit board and a semiconductor package that increase productivity and yield while maintaining the thickness of the core layer of the circuit board.

[0010]

[0011] A circuit board according to the present embodiment comprises a core layer including an upper surface and a lower surface; a first build-up layer disposed on the upper surface of the core layer; and a second build-up layer disposed on the lower surface of the core layer, wherein at least one of the first build-up layer and the second build-up layer comprises a protrusion penetrating at least a portion of the core layer.

[0012] The first build-up layer and the second build-up layer each include at least one insulating layer, and the protrusion may be made of the same material as the insulating layer.

[0013] The core layer may include a through hole penetrating from the upper surface to the lower surface, the first build-up layer may include a first protrusion in which at least a portion is disposed within the through hole, and the second build-up layer may include a second protrusion in which at least a portion is disposed within the through hole.

[0014] The core layer includes a coupling groove with a concave shape from the upper surface, and the first build-up layer may include a first protrusion coupled within the coupling groove.

[0015] The vertical length of the first protrusion may be less than or equal to half the vertical thickness of the core layer.

[0016] The vertical length of the first protrusion may be at least 1 / 2 of the vertical thickness of the core layer.

[0017] The core layer includes a coupling groove with a concave shape from the lower surface, and the second build-up layer may include a second protrusion coupled within the coupling groove.

[0018] The above insulating layer may be ABF (Ajinomoto Build-up Film).

[0019] The via portion is a metallic material disposed within a via hole penetrating at least a portion of the core layer, and the protrusion may overlap at least a portion of the via portion in a horizontal direction.

[0020] A semiconductor package according to the present embodiment comprises: a core layer including an upper surface and a lower surface; a first build-up layer disposed on the upper surface of the core layer; a second build-up layer disposed on the lower surface of the core layer; and a semiconductor chip disposed on the surface of the first build-up layer or the second build-up layer, wherein at least one of the first build-up layer and the second build-up layer includes a protrusion penetrating at least a portion of the core layer.

[0021]

[0022] In this embodiment, there is a structure in which a plurality of insulating layers are arranged in a vertical direction through a coupling structure between a core layer and a first build-up layer and between a core layer and a second build-up layer, and there is an advantage that the bending phenomenon of the circuit board can be minimized as the bonding strength between the insulating layer and the core layer increases.

[0023]

[0024] FIG. 1 is a cross-sectional view of a circuit board according to an embodiment of the present invention.

[0025] FIGS. 2 to 7 are drawings illustrating various shapes of a protrusion and a coupling groove according to an embodiment of the present invention.

[0026] FIG. 8 is a drawing illustrating a semiconductor package according to an embodiment of the present invention.

[0027]

[0028] The present invention is susceptible to various modifications and may have various embodiments, and specific embodiments are illustrated and described in the drawings. However, this does not specify the present invention.

[0029] It should be understood that the embodiments are not intended to be limited and include all modifications, equivalents, and substitutions that fall within the spirit and scope of the invention.

[0030] However, the technical concept of the present invention is not limited to some of the described embodiments but can be implemented in various different forms, and within the scope of the technical concept of the present invention, one or more of the components among the embodiments may be selectively combined or substituted.

[0031] In addition, terms used in the embodiments of the present invention (including technical and scientific terms) shall be interpreted in a meaning generally understood by those skilled in the art to which the present invention pertains, unless explicitly and specifically defined otherwise. Commonly used terms, such as those defined in a dictionary, shall be interpreted in consideration of their contextual meaning as described in the present invention. If a commonly used term defined in a dictionary does not match the meaning it has in the context of the description of the present invention, it shall be interpreted in accordance with the meaning it has in the context of the description of the present invention. Furthermore, even if not explicitly defined in this application, it shall not be interpreted in an ideal or overly formal sense based on the description of the present invention.

[0032] Furthermore, the terms used in the embodiments of the present invention are for describing the embodiments and are not intended to limit the present invention. In this specification, the singular form may include the plural form unless specifically stated otherwise in the text.

[0033] Terms containing ordinal numbers, such as "first," "second," etc., may be used to describe various components, but the meaning of the components is not limited by the ordinal numbers. Terms containing ordinal numbers are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the second component may be named the first component, and similarly, the first component may be named the second component. Furthermore, if the meaning of the component does not depart from the scope of the present invention even without ordinal numbers such as "first" and "second," the component may be referred to by excluding the ordinal number.

[0034] The term "and / or" includes a combination of multiple related listed items or any of the multiple related listed items. Such a term is used merely to distinguish a component from other components and is not limited by the nature, order, sequence, etc. of the component.

[0035] In this application, terms such as “comprising,” “provided,” and “having” are intended to specify the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not excluding in advance the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0036] When referring to directions, vertical and horizontal directions are used for convenience of explanation. Additionally, the horizontal direction may include a first horizontal direction perpendicular to the vertical direction, and a second horizontal direction perpendicular to the first horizontal direction and the vertical direction. Furthermore, if the vertical and horizontal directions follow a Cartesian coordinate system, they may correspond to the first horizontal direction (X-axis), the second horizontal direction (Y-axis), and the vertical direction (Z-axis), respectively; if they follow a cylindrical coordinate system, the first horizontal direction may refer to the azimuth (Φ) direction (or circumferential direction), and the second horizontal direction may refer to the radius (ρ) direction (or centrifugal direction) separated from a specific configuration; and if they follow a spherical coordinate system, the first horizontal direction may refer to the azimuth (Φ) direction (or circumferential direction), and the second horizontal direction may refer to the radius (r) direction (or centrifugal direction) separated from a specific configuration. In particular, the vertical direction may refer to the polar angle (θ) direction formed by the second horizontal direction and the Z-axis. For convenience of explanation, the first horizontal direction, the second horizontal direction, and the vertical direction may be used by combining the Cartesian coordinate system, the cylindrical coordinate system, and the spherical coordinate system described above. However, unless otherwise specified, the vertical direction refers to the Z-axis according to the Cartesian coordinate system, and the horizontal direction refers to any direction that can be defined on the XY plane; when referring to the first horizontal direction and the second horizontal direction perpendicular to the first horizontal direction, the first horizontal direction refers to the X-axis and the second horizontal direction refers to the Y-axis.

[0037] Furthermore, when described as being formed or placed "above or below" each component, "above" or "below" includes not only cases where two components are in direct contact with each other, but also cases where one or more other components are formed or placed between the two components. Additionally, when expressed as "above or below," it may include the meaning of a downward direction as well as an upward direction relative to a single component.

[0038] Furthermore, the meaning that Configuration A is positioned between Configuration B and Configuration C may include the meaning that Configuration A is positioned such that at least a portion of it overlaps with Configurations B and C in the horizontal and / or vertical directions. Unless otherwise noted, even if Configuration C is located between a virtual line extending vertically and / or horizontally from Configuration A and a virtual line extending vertically and / or horizontally from Configuration B, the meaning may include that Configuration C is positioned between Configuration A and Configuration B.

[0039] Furthermore, the statement that Configuration A is exposed from Configuration B should be understood as meaning that Configuration A is exposed from Configuration B, not that Configuration A is exposed from the entire product; and unless there are special circumstances, it should not be understood as meaning that the entirety of Configuration A is covered by Configuration B. In other words, when Configuration A is stated to be exposed from Configuration B, it should be understood to mean that Configuration C, in addition to Configurations A and B, covers Configuration A exposed from Configuration B.

[0040] Additionally, where it is stated that a component is 'connected,' 'combined,' 'connected,' or 'contacted' with another component, this may include not only cases where the component is directly connected, combined, or connected to the other component, but also cases where it is 'connected,' 'combined,' or 'connected' due to another component located between the component and the other component. Accordingly, if component A is to be understood only as being directly 'connected,' 'combined,' 'connected,' or 'contacted' with component B, it is described as being 'directly connected,' 'directly combined,' 'directly connected,' or 'directly contacted.'

[0041] In addition, when it is stated that configuration A is 'fixed' to configuration B, it should be understood that configuration A is indirectly fixed to configuration B through configuration C and / or configuration D, etc., unless otherwise specifically mentioned, considering the function and purpose to be solved, and in cases where configuration A is to be understood only as being 'directly fixed' to configuration B, it is stated as being 'directly fixed'.

[0042] In addition, when described as “flat” or “located on the same plane,” it should not be interpreted according to the dictionary definition, but rather understood by a person with ordinary knowledge in the relevant technical field to the extent that process deviations are taken into account.

[0043] FIG. 1 is a cross-sectional view of a circuit board according to an embodiment of the present invention.

[0044] Referring to FIG. 1, a circuit board (10) according to an embodiment of the present invention may include a core layer (100), a first build-up layer (200), a second build-up layer (300), a plurality of wiring portions, a plurality of via portions, and a protection layer.

[0045] A circuit board (10) may include a core layer (100). The core layer (100) may be a component forming the basis of the circuit board (10). Based on the vertical direction of the circuit board (10), the core layer (100) may be positioned in the center. The material of the core layer (100) may include at least one selected from the group consisting of glass, resin, plastic, and metal. The core layer (100) may be a prepreg (PPG) in which glass fibers are embedded. The core layer (100) may be a single-layer structure having a predetermined thickness in the vertical direction, but alternatively, the core layer (100) may include a plurality of insulating layers stacked in the vertical direction. When the core layer (100) is implemented with multiple insulating layers, compared to a structure in which the core layer is implemented with a single layer, via holes in each insulating layer constituting the core layer (100) can be formed using a laser as well as a mechanical drill, thereby lowering the manufacturing cost and making it easy to fill the entire interior of the via holes of the core layer (100) with metal. In addition, according to the structure in which multiple insulating layers are stacked vertically, the degree of design freedom regarding the formation of pads and via electrodes is increased, and accordingly, there is an advantage that production efficiency can be improved.

[0046] The core layer (100) may have a vertical thickness greater than the thickness of each of the plurality of insulating layers constituting the first build-up layer (200) and the second build-up layer (300) to be described later. Accordingly, warpage of the circuit board (10) through the core layer (100) can be minimized.

[0047] The first build-up layer (200) may be disposed on one side of the core layer (100). The first build-up layer (200) may be disposed on the upper surface of the core layer (100). The second build-up layer (300) may be disposed on the other side of the core layer (100). The second build-up layer (300) may be disposed on the lower surface of the core layer (100). The first build-up layer (100) and the second build-up layer (300) may be disposed facing each other with respect to the core layer (100). The first build-up layer (200) and the second build-up layer (300) may each include a plurality of insulating layers disposed in a vertical direction. The number of insulating layers of the first build-up layer (200) and the number of insulating layers of the second build-up layer (300) may be the same. Accordingly, the occurrence of bending of the circuit board (10) based on the core layer (100) can be minimized. However, this is not limited to the number of insulating layers in the first build-up layer (200) and the number of insulating layers in the second build-up layer (300) may differ from each other.

[0048] The first build-up (200) may include a first insulating layer (210), a second insulating layer (220), a third insulating layer (230), a fourth insulating layer (240), and a fifth insulating layer (250) arranged in a vertical direction. The first insulating layer (210) may be placed on the upper surface of the core layer (100). The second insulating layer (220) may be placed on the upper surface of the first insulating layer (210). The third insulating layer (230) may be placed on the upper surface of the second insulating layer (220). The fourth insulating layer (240) may be placed on the upper surface of the third insulating layer (230). The fifth insulating layer (250) may be placed on the upper surface of the fourth insulating layer (240).

[0049] The second build-up layer (300) may include a sixth insulating layer (310), a seventh insulating layer (320), an eighth insulating layer (330), a ninth insulating layer (340), and a tenth insulating layer (350) arranged in a vertical direction. The sixth insulating layer (310) may be placed on the lower surface of the core layer (100). The seventh insulating layer (320) may be placed on the lower surface of the sixth insulating layer (310). The eighth insulating layer (330) may be placed on the lower surface of the seventh insulating layer (320). The ninth insulating layer (340) may be placed on the lower surface of the eighth insulating layer (330). The tenth insulating layer (350) may be placed on the lower surface of the ninth insulating layer (340).

[0050] The first to tenth insulating layers (210, 220, 230, 240, 250, 310, 320, 330, 340, 350) may each be any insulating material, such as photocurable and / or thermosetting materials. As thermosetting insulating materials, insulating materials in which inorganic and / or organic fillers are dispersed within a resin, such as ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Corporation, may be used, and prepregs (PPG) containing glass fibers within a resin may be used. In addition, the resins described above may be, for example, epoxy resin, bismaleimide triazine resin (BT resin), phenolic resin, etc., and the inorganic and / or organic fillers may be provided with materials such as silica or plastic. When an insulating resin is used as a core, it may include a reinforcing material provided with glass fibers or aramid fibers. When the first to tenth insulating layers (210, 220, 230, 240, 250, 310, 320, 330, 340, 350) are photocurable insulators, the first to tenth insulating layers (210, 220, 230, 240, 250, 310, 320, 330, 340, 350) may each be a PID (Photo Imageable Dielectric).

[0051] The vertical thickness of each of the first to tenth insulating layers (210, 220, 230, 240, 250, 310, 320, 330, 340, 350) may be thinner than the vertical thickness of the core layer (100).

[0052] The circuit board (10) may include a protective layer. The protective layer may include a first protective layer (510) disposed on the surface of the first build-up layer (200) and a second protective layer (520) disposed on the surface of the second build-up layer (200). When a semiconductor device is disposed on the surface of the circuit board (10) using a material such as solder, the first protective layer (510) and the second protective layer (520) can perform the function of preventing short circuits between solders due to low wettability with the solder, and can prevent problems where external contaminants penetrate into the build-up structure and reduce reliability. The first protective layer (510) and the second protective layer (520) may each utilize a photocurable insulating material. For example, the first protective layer (510) and the second protective layer (520) may be a solder resist or a PID (Photo Imageable Dielectric).

[0053] The first protective layer (510) may include a hole (512) for exposing the seventh wiring section (417), which will be described later, to the upper side of the circuit board (10). The second protective layer (520), which will be described later, may include a hole (522) for exposing the twelfth wiring section (422), which will be described later, to the lower side of the circuit board (10).

[0054] The circuit board (10) may include a circuit pattern for transmitting electrical signals and / or power to an electronic device such as a semiconductor chip. The circuit pattern may include a plurality of wiring portions and a plurality of via portions.

[0055] Multiple wiring sections may be disposed on the surfaces of multiple insulating layers. Here, being disposed on the surface may also imply that at least a portion of each wiring section is embedded within each of the multiple insulating layers or protective layers and exposed to the outside from the surface. A wiring section may also be referred to as a metal layer. Furthermore, the surfaces of the multiple insulating layers each include a first surface, a second surface, and a side surface between the first surface and the second surface. Here, the first surface of the insulating layer may be understood as the upper surface, and the second surface of the insulating layer may be understood as the lower surface. Additionally, the upper and lower surfaces of the insulating layer are for convenience of explanation and do not limit the absolute location of the components.

[0056] The meaning that the wiring portion is disposed on the surface means that it is disposed on at least one of the one side, the other side, or the side of the plurality of insulating layers. The structure may have wiring portions disposed on one side and the other side of some of the insulating layers, respectively, and wiring portions disposed on only one side or the other side of other parts of the plurality of insulating layers.

[0057] A plurality of wiring sections include a first wiring section (411) disposed on the upper surface of the core layer (100), a second wiring section (412) disposed on the lower surface of the core layer (100), a third wiring section (413) disposed on the upper surface of the first insulating layer (210), a fourth wiring section (414) disposed on the upper surface of the second insulating layer (220), a fifth wiring section (415) disposed on the upper surface of the third insulating layer (230), a sixth wiring section (416) disposed on the upper surface of the fourth insulating layer (240), a seventh wiring section (417) disposed on the upper surface of the fifth insulating layer (250), an eighth wiring section (418) disposed on the lower surface of the sixth insulating layer (310), and a ninth wiring section (419) disposed on the lower surface of the seventh insulating layer (320). It may include a 10th wiring section (420) disposed on the lower surface of the 8th insulating layer (330), an 11th wiring section (430) disposed on the lower surface of the 9th insulating layer (340), and a 12th wiring section (422) disposed on the lower surface of the 10th insulating layer (350). Here, the 7th wiring section (417) and the 12th wiring section (422), which are covered by at least a portion of the protective layer (510, 520), may be named the 1st pad section and the 2nd pad section, respectively. Additionally, the wiring section may include a pad section for connecting to a via section.

[0058] The via portion may be a metallic material disposed in a via hole formed in each of a plurality of insulating layers to connect a plurality of wiring portions facing each other in a vertical direction. Here, the via hole penetrates at least a portion of each of the plurality of insulating layers in a vertical direction, and a via portion may be disposed within the via hole.

[0059] The via section comprises a first via section (430) penetrating at least a portion of the core layer (100), a second via section (471) penetrating at least a portion of the first insulating layer (210), a third via section (472) penetrating at least a portion of the second insulating layer (220), a fourth via section (473) penetrating at least a portion of the third insulating layer (230), a fifth via section (474) penetrating at least a portion of the fourth insulating layer (240), a sixth via section (475) penetrating at least a portion of the fifth insulating layer (250), a seventh via section (476) penetrating at least a portion of the sixth insulating layer (310), an eighth via section (477) penetrating at least a portion of the seventh insulating layer (320), a ninth via section (478) penetrating at least a portion of the eighth insulating layer (330), and at least a portion of the ninth insulating layer (340). It may include a 10th via (479) penetrating a portion and an 11th via (4480) penetrating at least a portion of the 10th insulating layer (350).

[0060] The first via section (430) can electrically connect the first wiring section (411) and the second wiring section (412). A filling member (460) may be disposed within the via hole where the first via section (430) is formed within the core layer (100). The first via section (430) is disposed along the wall of the via hole of the core layer (100), and the filling member (460) is filled into the space formed inside the first via section (430) to bury the via hole of the core layer (100).

[0061] The second via (471) can electrically connect the first wiring section (411) and the third wiring section (413). The third via (472) can electrically connect the third wiring section (413) and the fourth wiring section (414). The fourth via (473) can electrically connect the fourth wiring section (414) and the fifth wiring section (415). The fifth via (474) can electrically connect the fifth wiring section (415) and the sixth wiring section (416). The sixth via (475) can electrically connect the sixth wiring section (416) and the seventh wiring section (417). The seventh via (476) can electrically connect the second wiring section (412) and the eighth wiring section (418). The 8th via (477) can electrically connect the 8th wiring section (418) and the 9th wiring section (419). The 9th via (478) can electrically connect the 9th wiring section (419) and the 10th wiring section (420). The 10th via (479) can electrically connect the 10th wiring section (420) and the 11th wiring section (421). The 11th via (480) can electrically connect the 11th wiring section (421) and the 12th wiring section (422).

[0062] The second to sixth vias (471, 472, 473, 474, 475) may each have a shape in which the horizontal width gradually decreases as it approaches the core layer (100). The seventh to eleventh vias (476, 477, 478, 479, 480) may each have a shape in which the horizontal width gradually decreases as it approaches the core layer (100).

[0063] At least one of the first build-up layer (200) and / or the second build-up layer (300) may include a protrusion (270, 370) that penetrates at least a portion of the core layer (100). The protrusion (270, 370) may have a shape in which a portion of the insulating layer constituting the first build-up layer (200) or the second build-up layer (300) protrudes from the surface and penetrates one side and / or the other side of the core layer (100). Specifically, the first build-up layer (200) may include a protrusion that protrudes toward the other side of the core layer (100) to penetrate at least a portion of the core layer (100), and the second build-up layer (300) may include a protrusion that protrudes toward one side of the core layer (100) to penetrate at least a portion of the core layer (100). The protrusions (270, 370) may be made of the same material as the insulating layer constituting the first build-up layer (200) or the insulating layer constituting the second build-up layer (300).

[0064] The protrusions (270, 370) may include a first protrusion (270) that protrudes from the surface of the first insulating layer (210) and penetrates one side of the core layer (100), and a second protrusion (370) that protrudes from the surface of the sixth insulating layer (310) and penetrates the other side of the core layer (100).

[0065] The protrusions (270, 370) may be arranged so that at least a portion overlaps horizontally with the first via (430) penetrating the core layer (100). Additionally, as shown in FIG. 4, the first protrusion (270) may be arranged so that it is offset from the second protrusion (370) along the vertical direction, or so that it overlaps with the second protrusion along the vertical direction.

[0066] A coupling groove (130) to which a protrusion (270, 370) is coupled may be formed on at least one surface of the core layer (100) on which the first build-up layer (100) is disposed or on the other surface of the core layer (100) on which the second build-up layer (200) is disposed. For example, a first coupling groove with a concave shape from the surface may be disposed on one surface of the core layer (100) to which the first protrusion (270) is coupled. A second coupling groove with a concave shape from the surface may be disposed on the other surface of the core layer (100) to which the second protrusion (370) is coupled.

[0067] Meanwhile, when a first protrusion (270) and a second protrusion (370) are formed on each of the first build-up layer (200) and the second build-up layer (300), the first protrusion (270) and the second protrusion (370) can be connected in a vertical direction. In this case, the first coupling groove and the second coupling groove may have a hole shape that communicates in a vertical direction. Accordingly, since the other side is penetrated from one side of the core layer (100), the first coupling groove and the second coupling groove can be named a through hole by combination. The through hole may have a shape with a constant width in the vertical direction.

[0068] A via electrode (450) that electrically connects the first wiring section (411) and the second wiring section (412) may also be disposed in the through hole of the core layer (100). In this case, the via electrode (450) may be disposed along the inner wall surface of the through hole. Accordingly, the circuit board (10) can improve signal transmission efficiency through a connection structure between multiple wiring sections via the via electrode (450) in addition to the first via section (430) of the core layer (100). Accordingly, the via electrode (450) may be part of the first via section (430).

[0069] According to the above structure, in a structure in which a plurality of insulating layers are arranged in a vertical direction through a coupling structure between the core layer (100) and the first build-up layer (200) and between the core layer (100) and the second build-up layer (300), the bending phenomenon of the circuit board (10) can be minimized and the twisting of the core layer (100) can be prevented as the coupling force between the insulating layer and the core layer (100) increases.

[0070] Meanwhile, although not illustrated, the horizontal width of the coupling groove (130) to which the protrusions (270, 370) are coupled may be less than or equal to the horizontal width of the via hole in which the first via (430) is placed. Accordingly, the horizontal pitch between adjacent first via (430) can be secured by the protrusions (270, 370), thereby increasing the degree of freedom in the design.

[0071] Additionally, the first via portion (430) may be provided in plurality and arranged along the horizontal direction within the core layer (100), in which case the coupling structure of the protrusion (270, 370) and the coupling groove (130) may be arranged between the plurality of first via portions (430).

[0072] As a variation, the horizontal width of the coupling groove (130) to which the protrusions (270, 370) are coupled may be smaller than the horizontal width of the via hole to which the first via portion (430) is placed. In this case, there is an advantage that the placement area of ​​the first via portion (430) to which electrical connection is made can be secured more widely in the core layer (100).

[0073] FIGS. 2 to 7 are drawings illustrating various shapes of a protrusion and a coupling groove according to an embodiment of the present invention.

[0074] Referring to FIG. 2, the second protrusion (370) may be omitted. In this case, the core layer (100) may be combined through the first build-up layer (200) and the first protrusion (270). A coupling groove (130) to which the first protrusion (270) is coupled may be disposed on one side of the core layer (100). The vertical length (H2) of the first protrusion (270) and the coupling groove (130) may be less than or equal to half the vertical thickness (H1) of the core layer (100). Accordingly, the area for forming the internal coupling groove (130) of the core layer (100) is formed relatively short, thus providing the advantage of easy productivity.

[0075] However, the vertical length of the first protrusion (270) and the coupling groove (130) may be more than half the vertical thickness of the core layer (100), in which case the coupling area between the core layer (100) and the first build-up layer (200) through the first protrusion (270) may be secured more widely.

[0076] Referring to FIG. 3, the first protrusion (270) may be omitted. In this case, the core layer (100) may be combined through the second build-up layer (300) and the second protrusion (370). A coupling groove (130) to which the second protrusion (370) is coupled may be disposed on the other side of the core layer (100). The vertical length (H3) of the second protrusion (370) and the coupling groove (130) may be less than or equal to half the vertical thickness (H1) of the core layer (100). Accordingly, the area for forming the internal coupling groove (130) of the core layer (100) is formed relatively short, thus providing the advantage of easy productivity.

[0077] However, the vertical length of the second protrusion (370) and the coupling groove (130) may be more than half the vertical thickness of the core layer (100), and in this case, the coupling area between the core layer (100) and the second build-up layer (300) through the second protrusion (370) may be secured more widely.

[0078] As illustrated in FIGS. 2 and 3, the combined structure of the first build-up layer (200) or the second build-up layer (300) through the core layer (100) and the protrusions (270, 370) can be implemented in correspondence with the placement area of ​​the semiconductor chip (1000, see FIG. 8).

[0079] For example, when a semiconductor chip (1000) is placed on a first build-up layer (200), the core layer (100) and the first build-up layer (200) can form a bonding structure through a first protrusion (270) and a bonding groove (130) by means of a load from the semiconductor chip (1000) to the second build-up layer (300), as shown in FIG. 2.

[0080] When the semiconductor chip (1000) is placed on the second build-up layer (300), the core layer (100) and the second build-up layer (300) can form a bonding structure through the second protrusion (370) and the bonding groove (130) by the load from the semiconductor chip (1000) to the first build-up layer (200), as shown in FIG. 3.

[0081] Referring to FIG. 5, the first via section (430) may include a first region (432) and a second region (434) arranged in a vertical direction. The first region (432) may have a shape in which the horizontal width decreases as it faces the second build-up layer (300). The second region (434) is arranged below the first region (432) and may have a shape in which the horizontal width decreases as it faces the first build-up layer (200). The via hole of the core layer (100) in which the first via section (430) is arranged may also have a first region (122) in which the horizontal width decreases as it faces the second build-up layer (300) and a second region (124) in which the horizontal width decreases as it faces the first build-up layer (200), corresponding to the shapes of the first region (432) and the second region (434).

[0082] Additionally, the first protrusion (280) and the second protrusion (380) may be arranged so as to be perpendicularly offset from each other and may be arranged to overlap along the horizontal direction with the via (430). That is, the above-described embodiment can prevent problems such as twisting or bending of the core layer (100) by arranging the first protrusion (280) and / or the second protrusion (380) so that the stress applied to the core layer (100) can be relieved.

[0083] The core layer (100) may include a through hole (140) in which a first protrusion (280) and a second protrusion (380) are arranged. The through hole (140) may have a shape that penetrates from one side of the core layer (100) to the other side. The through hole (140) may include a third region (142) in which the horizontal width decreases as it extends from one side of the core layer (100) toward the second build-up layer (300), and a fourth region (144) in which the horizontal width decreases as it extends from the other side of the core layer (100) toward the first build-up layer (200).

[0084] The first build-up layer (200) and the second build-up layer (300) may include protrusions (280, 380) that are coupled to the through hole (140). The first build-up layer (200) may include a first protrusion (280) that protrudes from one surface facing the core layer (100) and is positioned in a third region (142). The second build-up layer (300) may include a second protrusion (380) that protrudes from one surface facing the core layer (100) and is positioned in a fourth region (144).

[0085] In this embodiment, the first protrusion (280) and the second protrusion (380) may each have an hourglass-shaped cross-section corresponding to the shape of the through hole (140). Accordingly, the bonding strength with the core layer (100) can be increased by reversing the expansion direction of the first protrusion (280) and the second protrusion (380) within the through hole (140).

[0086] Referring to FIG. 6, in the embodiment described in FIG. 5, the second protrusion (380) may be omitted. In this case, the core layer (100) may be combined through the first build-up layer (200) and the first protrusion (280). A coupling groove (142) to which the first protrusion (280) is coupled may be disposed on one side of the core layer (100). The coupling groove (142) may have a shape in which the horizontal width decreases as it moves from one side of the core layer (100) toward the second build-up layer (300).

[0087] Referring to FIG. 7, in the embodiment described in FIG. 5, the first protrusion (280) may be omitted. In this case, the core layer (100) may be combined with the second build-up layer (300) through the second protrusion (380). A coupling groove (142) to which the second protrusion (380) is coupled may be disposed on the other side of the core layer (100). The coupling groove (142) may have a shape in which the horizontal width decreases as it moves toward the first build-up layer (200) from the other side of the core layer (100).

[0088] FIG. 8 is a drawing illustrating a semiconductor package according to an embodiment of the present invention.

[0089] Referring to FIG. 8, a semiconductor package according to an embodiment of the present invention may include a semiconductor chip (1000) disposed on the aforementioned circuit board (10). For example, the semiconductor chip (1000) may be disposed on a first build-up layer (200) and may be electrically connected to a seventh wiring portion (417) disposed on the first build-up layer (200) through a connecting member.

[0090] In the foregoing, although all components constituting an embodiment of the present invention have been described as being combined or operating in combination, the present invention is not necessarily limited to such embodiments. That is, within the scope of the purpose of the present invention, all components may be selectively combined in one or more ways to operate. Furthermore, terms such as "include," "constitute," or "have" described above, unless specifically stated otherwise, mean that the relevant component may be inherent; thus, they should be interpreted as allowing for the inclusion of additional components rather than excluding other components. All terms, including technical or scientific terms, have the same meaning as generally understood by those skilled in the art to which the present invention pertains, unless otherwise defined. Terms commonly used, such as those defined in advance, should be interpreted in accordance with their meaning in the context of the relevant technology and should not be interpreted in an ideal or overly formal sense unless explicitly defined in the present invention.

[0091] The foregoing description is merely an illustrative explanation of the technical concept of the present invention, and those skilled in the art to which the present invention pertains will be able to make various modifications and variations within the scope of the essential characteristics of the present invention. Accordingly, the embodiments disclosed in the present invention are intended to explain, not limit, the technical concept of the present invention, and the scope of the technical concept of the present invention is not limited by such embodiments. The scope of protection of the present invention shall be interpreted by the claims below, and all technical concepts within an equivalent scope shall be interpreted as being included within the scope of rights of the present invention.

[0092] Meanwhile, when a circuit board having the features of the invention described above is used in IT devices or home appliances such as smartphones, server computers, and TVs, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the features of the invention performs a semiconductor package function, it can safely protect the semiconductor chip from external moisture or contaminants, and can resolve issues such as leakage current, electrical short circuits between terminals, or electrical open circuits of terminals supplying power to the semiconductor chip. In addition, when it is responsible for signal transmission, it can resolve noise issues. Through this, the circuit board having the features of the invention described above enables the stable operation of IT devices or home appliances, thereby allowing the entire product and the circuit board to which the invention is applied to achieve functional integration or technical interoperability.

[0093] When a circuit board having the features of the invention described above is used in a transportation device such as a vehicle, it can resolve the problem of signal distortion transmitted to the transportation device, or safely protect a semiconductor chip controlling the transportation device from the outside, and further improve the stability of the transportation device by resolving problems such as leakage current, electrical short circuits between terminals, or electrical open circuits of terminals supplying power to the semiconductor chip. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

Claims

1. Core layer including an upper surface and a lower surface; A first build-up layer disposed on the upper surface of the core layer; and It includes a second build-up layer disposed on the lower surface of the core layer, and At least one of the first build-up layer and the second build-up layer is a circuit board including a protrusion penetrating at least a portion of the core layer.

2. In Paragraph 1, The first build-up layer and the second build-up layer each include at least one insulating layer, and The above protrusion is a circuit board made of the same material as the above insulating layer.

3. In Paragraph 1, The above core layer includes a through hole penetrating from the upper surface to the lower surface, and The first build-up layer includes a first protrusion in which at least a portion is disposed within the through hole, and The above second build-up layer is a circuit board comprising a second protrusion in which at least a portion is disposed within the through hole.

4. In Paragraph 1, The above core layer includes a concave coupling groove from the upper surface, and The above first build-up layer is a circuit board including a first protrusion coupled within the coupling groove.

5. In Paragraph 4, A circuit board in which the vertical length of the first protrusion is less than or equal to 1 / 2 of the vertical thickness of the core layer.

6. In Paragraph 1, A circuit board in which the vertical length of the first protrusion is at least 1 / 2 of the vertical thickness of the core layer.

7. In Paragraph 1, The above core layer includes a concave coupling groove from the lower surface, and The above second build-up layer is a circuit board including a second protrusion that is coupled within the coupling groove.

8. In Paragraph 2, A circuit board in which the insulating layer is ABF (Ajinomoto Build-up Film).

9. In Paragraph 1, It includes a via portion which is a metallic material disposed within a via hole penetrating at least a portion of the core layer, and A circuit board in which at least a portion of the above-mentioned protrusion overlaps horizontally with the above-mentioned via portion.

10. Core layer including an upper surface and a lower surface; A first build-up layer disposed on the upper surface of the core layer; A second build-up layer disposed on the lower surface of the core layer; and A semiconductor chip disposed on the surface of the first build-up layer or the second build-up layer, and A semiconductor package in which at least one of the first build-up layer and the second build-up layer includes a protrusion penetrating at least a portion of the core layer.

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