Floating body effect remediation for extended drain mosfet

Abstract

NEDMOS FETs capable of withstanding high drain voltages while attaining high device reliability, and which remediate the floating body effect using one of several novel architectures. Each architecture provides a P or P+ pathway between the body of a NEDMOS device and a device-wide P+ body tie. The P / P+ pathway enables collection and conveyance of holes over to the device-wide body ties, resulting in elimination or substantial mitigation of the floating body effect. Use of a body tie spanning the width of the gate conductive layer (e.g., polysilicon) provides a number of benefits without reducing the effective width of the gate structure or increasing the gate capacitance CGG. Thus, one aspect of the present invention encompasses a MOSFET including a pathway between a body of the MOSFET and a device-wide body tie, wherein the pathway enables collection and conveyance of holes from the body over to the device-wide body tie.

Description

FLOATING BODY EFFECT REMEDIATION FOR EXTENDED DRAIN MOSFET CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] The present application claims priority to U.S. Provisional Application No. 63 / 712,260, filed on October 25, 2024, entitled “FLOATING BODY EFFECT REMEDIATION FOR EXTENDED DRAIN MOSFET”, the contents of which are incorporated herein by reference in their entirety.TECHNICAL FIELD

[0002] This invention relates to electronic integrated circuits, and more particularly to electronic integrated circuits that include metal-oxide-semiconductor field-effect transistors (MOSFETs).BACKGROUND

[0003] Virtually all modern electronic products - including laptop computers, mobile telephones, and electric cars - utilize MOSFET-based integrated circuits (ICs). A number of architectural variations exist for MOSFETs. The most common type of MOSFETs are N-type MOSFETs (NFETs), which have N+ doped source and drain regions abutting opposite sides of a channel region, which, for an enhancement-mode device, may be doped with P-type material. NFETs have been adapted to withstand relatively high drain voltages. For example, N-type Extended Drain MOS (NEDMOS) FETs fabricated using silicon-on-insulator (SOI) processes and Laterally-Diffused MOS (LDMOS) FETs fabricated using bulk silicon are common transistor devices capable of handling relatively high drain voltages.

[0004] FIG. 1 is a stylized cross-sectional view of an SOI IC structure for a prior art NEDMOS FET 100. The SOI structure includes a substrate 102, an insulating buried-oxide (BOX) layer 104, and an active layer 106 (note that the dimensions for the elements of the SOI IC structure are not to scale; some dimensions have been exaggerated for clarity or emphasis). The substrate 102 is typically a semiconductor material such as silicon (Si), but may be other materials such as glass orsapphire. The BOX layer 104 is a dielectric and is often SiO2 formed as a “top” surface of the substrate 102; for some substrates (e.g., glass or sapphire, a BOX layer 104 optionally may be omitted. Some embodiments may include a trap-rich Si layer (not shown) between the BOX layer 104 and the substrate 102. A trap-rich Si layer mitigates parasitic surface conduction and improves device performance at high frequencies.

[0005] The active layer 106 may include some combination of implants and / or layers that include dopants, dielectrics, polysilicon, conductors, passivation, and other materials to form active and / or passive electronic components and / or mechanical structures. For example, the NEDMOS FET 100 of FIG. 1 has an active layer 106 that includes an N+ source 110, a P-type body region or “P-well” 112 in which an electrically conductive channel can be formed, an N- Si drift region 114, and an N+ drain 116, all bounded by isolation structures 118, such as a shallow trench isolation (STI) structure. The designation “N- means a lesser concentration of N-type dopant (e.g., arsenic or phosphorous) than the designation “N+”

[0006] The active layer 106 may include a halo region 122 to increase a sub-surface electric field to reduce so-called punch-through, or short channel, conduction between the source 110 and the drain 116, thus increasing the channel breakdown voltage. For an N-type MOSFET, a halo region is typically dopes with P or P+ material. Some embodiments may include an N-type lightly-doped drain (LDD) region (not shown; “LDD” being somewhat of a misnomer, since an LDD region would generally only be on the source-side of a NEDMOS FET). An LDD region extends the source 110 underneath a gate structure 130 and modulates the threshold voltage VTH, transconductance Gm, and leakage current of the device.

[0007] The gate structure 130 is formed in contact with a surface of the active layer 106, positioned with respect to the P-well 112 so as to be able to control current flow through the P-well 112 between the source 110 and the drain 116. The gate structure 130 includes a conductive layer 132, such as N+ doped polysilicon, in contact with an insulating gate oxide (GOX) layer 134, the thickness of which may be varied for different applications. In the illustrated example, the gate structure 130 is surrounded by insulating spacers 136. In some applications, the dielectric spacer may be formed from multiple dielectric layers. Part of the gate structure 130 and the N- drift region 114 may be coated with a dielectric 138, such as SiCE, SiaN^ etc., which in turn may beoverlaid with a salicide block (SAB) layer 140, such as silicon nitride (SiN), to prevent subsequent formation of self-aligned silicides (also known as “salicides”) on those structures / regions.

[0008] A conductive source contact 142, a conductive gate contact 144, and a conductive drain contact 146, which may be salicides, are respectively formed in contact with the source 110, the conductive layer 132 of the gate structure 130, and the drain 116. Stylized electrical terminals S, G, and D are shown coupled to the corresponding source contact 142, gate contact 144, and drain contact 146.

[0009] The gate structure 130, the BOX layer 104, and the active layer 106 (which may include multiple FETs) may be collectively referred to as a “device region” or “substructure” for convenience (noting that other structures or regions may intrude into the substructure in particular IC designs). A superstructure (not shown) of various elements, regions, and structures may be fabricated on or above the substructure in order to implement particular functionality. The superstructure may include, for example, conductive interconnections from the illustrated NEDMOS FET 100 to other components (including other FETs on the same IC die) and / or external contacts, passivation layers, and protective coatings.

[0010] One of the purposes of the N- drift region 114 is to reduce the electrical field (“E-field”) that would otherwise occur at and near the junction of the P-well 112 and an abutting drain (near the region 150 marked with a dotted-line oval) when a sufficiently high drain voltage VDD is applied to the device. A high E-field generates “hot” (z.e., energetic) electrons, which may cause impact ionization which can result in avalanche breakdown. In addition, hot electrons with higher energy than the GOX layer 134 can be trapped at the junction interface in and around region 150, which causes increased resistance in the channel of the device, thus reducing the device drain-to-source current IDS. The N- drift region 114, by having a lower doping concentration than the drain 116, reduces the electric field and impact ionization on the drain side of the gate structure 130. This increases the gate dielectric breakdown voltage, which improves the reliability of an NEDMOS FET.

[0011] The illustrated NEDMOS FET 100 includes doped regions having different dopant concentrations. For example, the NEDMOS FET 100 may include heavily doped (x+), intermediately doped (x), and lightly doped (x-) regions, where x is the polarity type and can beP-type (“P”) or N-type (“N”). A lightly doped region may have a dopant concentration of about 1015 / cm3, an intermediately doped region may have a dopant concentration of about 1018 / cm3, and a heavily doped region may have a dopant concentration of about 1021 / cm3. Providing other dopant concentrations for the different doped regions may also be useful. For example, the doping concentrations for the different types of doped regions may be relative and depend on a selected fabrication process. P-type dopants may include boron (B), aluminum (Al), and / or indium (In), while N-type dopants may include phosphorous (P), arsenic (As), and / or antimony (Sb).

[0012] Due to the insulating BOX layer 104, impact ionization and tunneling occurring at high electric field strengths cause holes to accumulate within the P-well 112, resulting in the well-known floating body effect. The floating body effect significantly degrades the output conductance (gDs) and the safe operating area (SOA) of the device (the SOA is defined by a set of voltage, current, and temperature values within which a MOSFET device operates reliably). Typically, for an N-type FET, a P+ body tie along with a polysilicon body tie extension is implemented to reduce the floating body effect. However, too many body ties of this type cause the gate capacitance CGG to increase and moderately reduces the effective gate width. A striped body tie design without a polysilicon extension may be used, but each body tie stripe overlapping the gate reduces the effective gate width.

[0013] The present invention is directed to novel NEDMOS FETs capable of withstanding higher drain voltages than conventional NEDMOS devices while attaining high device reliability, and which remediate the floating body effect using one of several novel architectures.SUMMARY

[0014] The present invention encompasses novel NEDMOS FETs capable of withstanding higher drain voltages than conventional NEDMOS devices while attaining high device reliability, and which remediate the floating body effect using one of several novel architectures. Each architecture provides a P or P+ pathway between the body of a NEDMOS device and a devicewide P+ body tie. The P / P+ pathway enables collection and conveyance of holes over to the devicewide body ties, resulting in elimination or substantial mitigation of the floating body effect. Use of a body tie that spans the width of the gate conductive layer (e.g., polysilicon) provides a number of benefits, noted below, without reducing the effective width of the gate structure or increasing the gate capacitance CGG. The invention further encompasses LDMOS FETs having a comparable construction.

[0015] One aspect of the present invention encompasses a MOSFET including a pathway between a body of the MOSFET and a device-wide body tie, wherein the pathway enables collection and conveyance of holes from the body over to the device-wide body tie. In particular, the present invention encompasses a MOSFET including an active layer, a body region fabricated within the active layer and doped to have a first semiconductor characteristic, a gate structure formed above the body region, a shallow source region fabricated within the active layer adjacent to a second side of the body region and doped to have a second semiconductor characteristic, a device-wide body tie region fabricated within the active layer adjacent to the shallow source region and doped to have a third semiconductor characteristic, and a pathway between the body region and the device-wide body tie region, wherein the pathway enables collection and conveyance of holes from the body over to the device-wide body tie. Another aspect of the invention includes methods for making such a MOSFET.

[0016] The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention should be apparent from the description and drawings, and from the claims.DE SCRIPTION OF THE DRAWINGS

[0017] FIG. l is a stylized cross-sectional view of an SOI IC structure for a prior art NEDMOS FET.

[0018] FIG. 2A is a stylized cross-sectional view of a first SOI IC structure for an improved NEDMOS FET in accordance with the present invention.

[0019] FIG. 2B is a stylized top plan view of the SOI IC structure of FIG. 2A.

[0020] FIG. 3 is a stylized cross-sectional view of a second SOI IC structure for an improved NEDMOS FET in accordance with the present invention.

[0021] FIG. 4 is a stylized cross-sectional view of a third SOI IC structure for an improved NEDMOS FET in accordance with the present invention.

[0022] FIG. 5 is a process flowchart showing another representation of an example fabrication process for an improved NEDMOS FET that is suitable for some contemporary IC front-end-of-line (FEOL) foundries.

[0023] FIG. 6 is a top plan view of a substrate that may be, for example, a printed circuit board or chip module substrate (e.g., a thin-film tile).

[0024] Like reference numbers and designations in the various drawings indicate like elements unless the context requires otherwise.DETATLED DESCRIPTION

[0025] The present invention encompasses novel NEDMOS FETs capable of withstanding higher drain voltages than conventional NEDMOS devices while attaining high device reliability, and which remediate the floating body effect using one of several novel architectures. Each architecture provides a P or P+ pathway between the body of a NEDMOS device and a devicewide P+ body tie. The P / P+ pathway enables collection and conveyance of holes over to the devicewide body ties, resulting in elimination or substantial mitigation of the floating body effect. Use of a body tie that spans the width of the gate conductive layer (e.g., polysilicon) provides a number of benefits, noted below, without reducing the effective width of the gate structure or increasing the gate capacitance CGG. The invention further encompasses LDMOS FETs having a comparable construction.

[0026] FIG. 2A is a stylized cross-sectional view of a first SOI IC structure for an improved NEDMOS FET 200 in accordance with the present invention. The cross-sectional structure is similar in many aspects to the conventional NEDMOS FET 100 of FIG. 1, and corresponding elements are numbered the same. However, significant and novel differences exist. In particular, on the source-side of the gate structure 130, the illustrated embodiment includes a shallow N+ source 202, a buried P+ body contact region 204, and a device-wide P+ body tie 206. The shallow N+ source 202 also serves as a lightly-doped drain (LDD) region to modulate the threshold voltage VTH, transconductance Gm, and leakage current of the device.

[0027] FIG. 2B is a stylized top plan view of the SOI IC structure of FIG. 2A. As can be seen, the device-wide body tie 206 has essentially the same length (in the Y dimension) as the shallow N+ source 202, the gate conductive layer 132 (e.g., N+ polysilicon; overlying dielectric and gate contacts are omitted for clarity), the N- drift region 114, and the N+ drain 116.

[0028] The buried P+ body contact region 204 beneath the shallow N+ source 202 can significantly improve the SOA of the NEDMOS FET 200 by serving as a pathway 212 (indicated by a dotted line on FIG. 2A) for collecting holes (represented as “+” symbols in dashed oval 210) that may be formed within the P-well 112 near the drain-side of the gate structure 130 over to the device-wide body tie 206.

[0029] The use of a body tie 206 is of a special importance - the body tie 206 eliminates or substantially mitigates the floating body effect; mitigates turn-on of the parasitic bipolar devices inherent in a MOSFET; improves the breakdown voltage of the FET; improves electro-static discharge (ESD) protection for the FET; improves device and circuitry performance and capability, and in particular improves circuit linearity, reliability, and power consumption in analog and digital circuitry, especially for such devices as radio frequency (RF) and mmWave switches, low-noise amplifiers (LNAs), and power amplifiers (PAs). Further, the use of a body tie 206 that spans the width of the gate conductive layer 132 provides all of these benefits without reducing the effective width of the gate structure 130 or increasing the gate capacitance CGG. In some embodiments, the body tie 206 may be tied (electrically coupled) to the source 110, and thus the device will have equal potential between the body and the source. In some embodiments, the body tie 206 may be separately biased in order to manipulate the body potential independently of the source.

[0030] To avoid the cost of implementing the buried P+ body contact region 204 using an extra mask, the buried P+ body contact region 204 is preferably fabricated by ion implantation of dopant using the same mask used for implantation of halo region 122 and the shallow N+ source 202. For example, as the NEDMOS FET 200 is fabricated, a mask is formed to define the region adjacent to the gate structure 130 that is to become the source 202. With that source mask in place, ion implantation of P or P+ dopant at a first selected tilt angle (e.g, about 30° with respect to vertical) may be performed to create the halo region 122. Similarly, ion implantation of P+ dopant at a second selected angle (e.g, about 0° to about 45° with respect to vertical, with 0° being typical) may be performed to create the buried P+ body contact region 204. Thereafter, again using the same source mask, implantation of N+ dopant may be performed to create the shallow N+ source 202. Note that the order of implantation of the halo region 122 and the buried P+ body contact region 204 may be reversed.

[0031] FIG. 2A shows the buried P+ body contact region 204 as a uniformly doped region that does not reach all of the way to the BOX layer 104. However, the buried P+ body contact region 204 may extend all of the way to the BOX layer 104, and / or may be fabricated with a stepped or continuous vertical (along the Z dimension) doping gradient. For example, a continuous vertical doping gradient may be achieved simply by implanting a dopant at a fixed energy level, resultingin higher level of doping closer to the top of the buried P+ body contact region 204 and a lower level of doping closer to the bottom of the buried P+ body contact region 204. A stepped doping gradient for the buried P+ body contact region 204 may be created by varying the energy of ion implantation and the duration of implantation at particular energy levels. For example, P+ dopant may be implanted at about lOkeV for a first duration, and then at about 5keV for a second duration, to create a buried P+ body contact region 204 having two vertically-stepped doping concentrations.

[0032] FIG. 3 is a stylized cross-sectional view of a second SOI IC structure for an improved NEDMOS FET 300 in accordance with the present invention. The cross-sectional structure is similar in many aspects to the NEDMOS FET 200 of FIG. 2A, and corresponding elements are numbered the same. However, on the source-side of the gate structure 130, the illustrated embodiment includes a shallow N+ source 202 and a device-wide P+ body tie 206, but omits the buried P+ body contact region 204 of FIG. 2A. Instead, the shallowness of the N+ source 202 results in an L-shaped P-well 112 that contacts the device-wide body tie 206, thereby creating a pathway 212 that enables collection and conveyance of holes (represented as “+” symbols in dashed oval 210) over to the device-wide body tie 206. As in FIG. 2A, the shallow N+ source 202 also serves as a lightly-doped drain (LDD) region to modulate the threshold voltage VTH, transconductance Gm, and leakage current of the device. An advantage of the embodiment shown in FIG. 3 is that the extra P+ implantation step is avoided compared to the process for forming the buried P+ body contact region 204 of FIG. 2A.

[0033] FIG. 4 is a stylized cross-sectional view of a third SOI IC structure for an improved NEDMOS FET 400 in accordance with the present invention. The cross-sectional structure is similar in many aspects to the NEDMOS FET 200 of FIG. 2A, and corresponding elements are numbered the same. However, on the source-side of the gate structure 130, the illustrated embodiment includes a shallow N+ source 202 and a device-wide P+ body tie 206, but omits the buried P+ body contact region 204 of FIG. 2A. In addition, an expanded halo region 402 is formed by implanting P+ dopant for a duration and tilt angle sufficient to encompass the later-formed shallow N+ source 202. Thus, as illustrated, a portion of the expanded halo region 402 extends below the shallow N+ source 202 and provides a P+ pathway 212 for collection and conveyance of holes (represented as “+” symbols in dashed oval 210) over to the device-wide body tie 206. Anadvantage of the embodiment shown in FIG. 4 is that the extra P+ implantation step is avoided compared to the process for forming the distinct buried P+ body contact region 204 of FIG. 2A.

[0034] A number of different processes may be used to fabricate the improved FET devices described in this disclosure, including NEDMOS and LDMOS versions.

[0035] FIG. 5 is a process flowchart 500 showing another representation of an example fabrication process for an improved NEDMOS FET that is suitable for some contemporary IC front-end-of-line (FEOL) foundries. Note that some conventional steps, such as planarization, passivation, details of masking and etching, and superstructure formation have been omitted as known to those of ordinary skill in the art. The illustrated process includes:• Forming shallow trench isolation (STI) regions (Step 502).• Forming a P-type well (Step 504).• Performing gate oxidation (Step 506).• Depositing gate material (e.g, P+ poly-Si), patterning (e.g, masking and etching) to define a gate structure, and forming gate structure spacers (Step 508).• Patterning a drain-side drift region and angle implanting N- dopant (Step 510).• Masking the region in which the shallow N+ source 202 is to be formed (Step 512).• Implanting a P or P+ source-side halo region, normal size or expanded size (Step 514).• If including a buried P+ body contact region, then implanting a P+ dopant that will be positioned below a shallow N+ source region (Step 516).• Implanting a shallow N+ source region, then patterning and implanting an N+ drain region (Step 518).• Depositing a salicide block layer and patterning to define contact regions (Step 520).Depositing salicide (e.g, NiSi) in the defined contact regions and annealing (Step 522).

[0036] Note that not all steps that may be performed during the manufacture of a novel FET device as part of an IC are shown or described in this disclosure. Such steps may vary between IC foundries and may include (but are not limited to) substrate thinning, planarization, special implantations, annealing, formation of ohmic contacts, and formation of additional temporary or permanent structures (e.g., drift regions, substrate contacts, passivation layers, salicide blocks, replacement metal gate (RMG)), etc. After formation of a basic MOSFET structure, back-end-of-line (BEOL) processes may be applied, such as fabrication of electrical contacts (pads), vias, insulating layers (dielectrics), metallization layers, and bonding sites for die-to-package connections.

[0037] As should be appreciated, other “recipes” that include additive and / or subtractive process steps may be used to fabricate essentially the same improved NEDMOS FET device structures of the types described in this disclosure. Further, the fabrications steps may be performed in any feasible order. For example, as described above, a buried P+ body contact region may be implanted before the halo region. As another example, the buried P+ body contact region and shallow source region may be formed before the drain-side drift region. LDMOS FETs may be fabricated using essentially the same processes. The same concepts and processes may be applied to fabricating MOSFETs in bulk silicon, high-resistivity silicon, SOI without a non-trap rich layer, etc.

[0038] Circuits and devices in accordance with the present invention may be used alone or in combination with other components, circuits, and devices. Embodiments of the present invention may be fabricated as integrated circuits (ICs), which may be encased in IC packages and / or in modules for ease of handling, manufacture, and / or improved performance. In particular, IC embodiments of this invention are often used in modules in which one or more of such ICs are combined with other circuit components or blocks (e.g., fdters, amplifiers, passive components, and possibly additional ICs) into one package. The ICs and / or modules are then typically combined with other components, often on a printed circuit board, to form part of an end-product such as a cellular telephone, laptop computer, or electronic tablet, or to form a higher-level module which may be used in a wide variety of products, such as vehicles, test equipment, medical devices, etc. Through various configurations of modules and assemblies, such ICs typically enable a mode of communication, often wireless communication.

[0039] As one example of further integration of embodiments of the present invention with other components, FIG. 6 is a top plan view of a substrate 600 that may be, for example, a printed circuit board or chip module substrate (e.g., a thin-film tile). In the illustrated example, the substrate 600 includes multiple ICs 602a-602d having terminal pads 604 which would be interconnected by conductive vias and / or traces on and / or within the substrate 600 or on the opposite (back) surface of the substrate 600 (to avoid clutter, the surface conductive traces are not shown and not all terminal pads are labelled). The ICs 602a-602d may embody, for example, signal switches, active and / or passive fdters, amplifiers (including one or more low-noise amplifiers), and other circuitry. For example, IC 602b may incorporate one or more instances of a NEDMOS FET like the devices shown in FIGS. 2A, 3, and / or 4.

[0040] The substrate 600 may also include one or more passive devices 606 embedded in, formed on, and / or affixed to the substrate 600. While shown as generic rectangles, the passive devices 606 may be, for example, filters, capacitors, inductors, transmission lines, resistors, antennae elements, transducers (including, for example, MEMS-based transducers, such as accelerometers, gyroscopes, microphones, pressure sensors, e / c.), batteries, etc., interconnected by conductive traces on or in the substrate 600 to other passive devices 606 and / or the individual ICs 602a-602d.

[0041] The front or back surface of the substrate 600 may be used as a location for the formation of other structures. For example, one or more antennae may be formed on or affixed to the front orback surface of the substrate 600; one example of a front-surface antenna 608 is shown, coupled to an IC die 602b, which may include RF front-end circuitry. Thus, by including one or more antennae on the substrate 600, a complete radio may be created.

[0042] Embodiments of the present invention are useful in a wide variety of larger radio frequency (RF) circuits and systems for performing a range of functions, including (but not limited to) impedance matching circuits, RF power amplifiers, RF low-noise amplifiers (LNAs), phase shifters, attenuators, antenna beam-steering systems, charge pump devices, RF switches, high performance envelope tracking circuits, high performance average power tracking circuits, etc. Such functions are useful in a variety of applications, such as radar systems (including phasedarray and automotive radar systems), radio systems (including cellular radio systems), and test equipment.

[0043] Radio system usage includes wireless RF systems (including base stations, relay stations, and hand-held transceivers) that use various technologies and protocols, including various types of orthogonal frequency-division multiplexing (“OFDM”), quadrature amplitude modulation (“QAM”), Code-Division Multiple Access (“CDMA”), Time-Division Multiple Access (“TDMA”), Wide Band Code Division Multiple Access (“W-CDMA”), Global System for Mobile Communications (“GSM”), Long Term Evolution (“LTE”), 5G, 6G, and WiFi (e.g., 802.1 la, b, g, ac, ax, be) protocols, as well as other radio communication standards and protocols.

[0044] The term “MOSFET”, as used in this disclosure, includes any field effect transistor (FET) having an insulated gate whose voltage or charge level determines the conductivity of the transistor, and encompasses insulated gates having a metal or metal-like, insulator, and / or semiconductor structure. The terms “metal” or “metal-like” include at least one electrically conductive material (such as aluminum, copper, or other metal, or highly doped polysilicon, graphene, or other electrical conductor), “insulator” includes at least one insulating material (such as silicon oxide or other dielectric material), and “semiconductor” includes at least one semiconductor material.

[0045] As used in this disclosure, the term “radio frequency” (RF) refers to a rate of oscillation in the range of about 3 kHz to about 300 GHz. This term also includes the frequencies used in wireless communication systems. An RF frequency may be the frequency of an electromagnetic wave or of an alternating voltage or current in a circuit.

[0046] With respect to the figures referenced in this disclosure, the dimensions for the various elements are not to scale; some dimensions may be greatly exaggerated vertically and / or horizontally for clarity or emphasis. In addition, references to orientations and directions (e.g., “top”, “bottom”, “above”, “below”, “lateral”, “vertical”, “horizontal”, etc.) are relative to the example drawings, and not necessarily absolute orientations or directions.

[0047] Various embodiments of the invention can be implemented to meet a wide variety of specifications. Unless otherwise noted above, selection of suitable component values is a matterof design choice. Various embodiments of the invention may be implemented in any suitable integrated circuit (IC) technology (including but not limited to MOSFET structures), or in hybrid or discrete circuit forms. Integrated circuit embodiments may be fabricated using any suitable substrates and processes, including but not limited to standard bulk silicon, high-resistivity bulk CMOS, silicon-on-insulator (SOI), and silicon-on-sapphire (SOS). Unless otherwise noted above, embodiments of the invention may be implemented in other transistor technologies, such as BiCMOS, LDMOS, BCD, FinFET, GAAFET, and SiC-based device technologies, using 2-D, 2.5-D, and 3-D structures. However, embodiments of the invention are particularly useful when fabricated using an SOI or SOS based process, or when fabricated with processes having similar characteristics. Fabrication in CMOS using SOI or SOS processes enables circuits with low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity, and high frequency operation (Ze., radio frequencies up to and exceeding 300 GHz). Monolithic IC implementation is particularly useful since parasitic capacitances generally can be kept low (or at a minimum, kept uniform across all units, permitting them to be compensated) by careful design.

[0048] A number of embodiments of the invention have been described. It is to be understood that various modifications may be made without departing from the spirit and scope of the invention. For example, some of the steps described above may be order independent, and thus can be performed in an order different from that described. Further, some of the steps described above may be optional. Various activities described with respect to the methods identified above can be executed in repetitive, serial, and / or parallel fashion.

[0049] It is to be understood that the foregoing description is intended to illustrate and not to limit the scope of the invention, which is defined by the scope of the following claims, and that other embodiments are within the scope of the claims. In particular, the scope of the invention includes any and all feasible combinations of one or more of the processes, machines, manufactures, or compositions of matter set forth in the claims below. (Note that the parenthetical labels for claim elements are for ease of referring to such elements, and do not in themselves indicate a particular required ordering or enumeration of elements; further, such labels may be reused in dependent claims as references to additional elements without being regarded as starting a conflicting labeling sequence).

Claims

CLATMSWHAT IS CLAIMED IS:

1. AMOSFET including a pathway between a body region of the MOSFET and a device-wide body tie region, wherein the pathway enables collection and conveyance of holes from the body region over to the device-wide body tie region.

2. The MOSFET of claim 1, wherein the pathway comprises a buried body contact region fabricated within an active layer of the MOSFET below a shallow source region of the MOSFET and in contact with the body region and the device-wide body tie region.

3. The MOSFET of claim 1, wherein the pathway comprises an extension of the body region below a shallow source region of the MOSFET and in contact with the device-wide body tie region.

4. The MOSFET of claim I, wherein the pathway comprises an expanded halo region fabricated within an active layer of the MOSFET below a shallow source region of the MOSFET and in contact with the body region and the device-wide body tie region.

5. AMOSFET including:(a) an active layer;(b) a body region fabricated within the active layer and doped to have a first semiconductor characteristic;(c) a gate structure formed above the body region;(d) a shallow source region fabricated within the active layer adjacent to a side of the body region and doped to have a second semiconductor characteristic;(e) a device-wide body tie region fabricated within the active layer adjacent to the shallow source region and doped to have a third semiconductor characteristic; and(fj a pathway between the body region and the device-wide body tie region, wherein the pathway enables collection and conveyance of holes from the body over to the devicewide body tie.

6. The MOSFET of claim 5, wherein the pathway comprises a buried body contact region fabricated within the active layer below the shallow source region and in contact with the body region and the device-wide body tie region and doped to have a fourth semiconductor characteristic.

7. The MOSFET of claim 5, wherein the pathway comprises an extension of the body region below the shallow source region in contact with the device-wide body tie region.

8. The MOSFET of claim 5, wherein the pathway comprises an expanded halo region fabricated within the active layer below the shallow source region and in contact with the body region and the device- wide body tie region and doped to have a fourth semiconductor characteristic.

9. The MOSFET of claim 5, wherein the active layer is formed on an insulating layer supported by a substrate.

10. The MOSFET of claim 5, wherein the first semiconductor characteristic is P-type, the second semiconductor characteristic is N+ type, and the third semiconductor characteristic is P+ type.

11. The MOSFET of claim 5, wherein the device-wide body tie region is electrically coupled to the shallow source region.

12. The MOSFET of claim 5, wherein the device-wide body tie region is electrically biased independently of the shallow source region.

13. A MOSFET including:(a) an active layer;(b) a body region fabricated within the active layer and doped to have a first semiconductor characteristic;(c) a gate structure formed above the body region;(d) a shallow source region fabricated within the active layer adjacent to a second side of the body region and doped to have a second semiconductor characteristic;(e) a device-wide body tie region fabricated within the active layer adjacent to the shallow source region and doped to have a third semiconductor characteristic; and(f) a buried body contact region fabricated within the active layer below the shallow source region and in contact with the body region and the device-wide body tie region and doped to have a fourth semiconductor characteristic.

14. The MOSFET of claim 13, wherein the active layer is formed on an insulating layer supported by a substrate.

15. The MOSFET of claim 13, wherein the first semiconductor characteristic is P-type, the second semiconductor characteristic is N+ type, the third semiconductor characteristic is P+ type, and the fourth semiconductor characteristic is P+ type.

16. The MOSFET of claim 13, wherein the device-wide body tie region is electrically coupled to the shallow source region.

17. The MOSFET of claim 13, wherein the device-wide body tie region is electrically biased independently of the shallow source region.

18. A MOSFET including:(a) an active layer;(b) a body region fabricated within the active layer and doped to have a first semiconductor characteristic;(c) a gate structure formed above the body region;(d) a shallow source region fabricated within the active layer proximate to a side of the body region and doped to have a second semiconductor characteristic; and(e) a device-wide body tie region fabricated within the active layer adjacent to the shallow source region and doped to have a third semiconductor characteristic;wherein the body region extends below the shallow source region to be in contact with the device-wide body tie region.

19. The MOSFET of claim 18, wherein the active layer is formed on an insulating layer supported by a substrate.

20. The MOSFET of claim 18, wherein the first semiconductor characteristic is P-type, the second semiconductor characteristic is N+ type, and the third semiconductor characteristic is P+ type.

21. The MOSFET of claim 18, wherein the device-wide body tie region is electrically coupled to the shallow source region.

22. The MOSFET of claim 18, wherein the device-wide body tie region is electrically biased independently of the shallow source region.

23. A MOSFET including:(a) an active layer;(b) a body region fabricated within the active layer and doped to have a first semiconductor characteristic;(c) a gate structure formed above the body region;(d) a shallow source region fabricated within the active layer proximate to a second side of the body region and doped to have a second semiconductor characteristic;(e) a device-wide body tie region fabricated within the active layer adjacent to the shallow source region and doped to have a third semiconductor characteristic; and(f) an expanded halo region fabricated within the active layer below the shallow source region and in contact with the body region and the device-wide body tie region and doped to have a fourth semiconductor characteristic.

24. The MOSFET of claim 23, wherein the active layer is formed on an insulating layer supported by a substrate.

25. The MOSFET of claim 23, wherein the first semiconductor characteristic is P-type, the second semiconductor characteristic is N+ type, the third semiconductor characteristic is P+ type, and the fourth semiconductor characteristic is P or P+ type.

26. The MOSFET of claim 23, wherein the device-wide body tie region is electrically coupled to the shallow source region.

27. The MOSFET of claim 23, wherein the device-wide body tie region is electrically biased independently of the shallow source region.

28. A MOSFET including:(a) an active layer;(b) a body region fabricated within the active layer and doped to have a first semiconductor characteristic;(c) a gate structure formed above the body region;(d) a drift region fabricated within the active layer adjacent to a first side of the body region and doped to have a second semiconductor characteristic;(e) a drain region fabricated within the active layer adjacent to the drift region and doped to have a third semiconductor characteristic;(f) a shallow source region fabricated within the active layer adjacent to a second side of the body region and doped to have a fourth semiconductor characteristic;(g) a device-wide body tie region fabricated within the active layer adjacent to the shallow source region and doped to have a fifth semiconductor characteristic; and(h) a buried body contact region fabricated within the active layer below the shallow source region and in contact with the body region and the device-wide body tie region and doped to have a sixth semiconductor characteristic.

29. The MOSFET of claim 28, wherein the active layer is formed on an insulating layer supported by a substrate.

30. The MOSFET of claim 28, wherein the first semiconductor characteristic is P-type, the second semiconductor characteristic is N- type, the third semiconductor characteristic is N+ type, the fourth semiconductor characteristic is N+ type, the fifth semiconductor characteristic is P+ type, and the sixth semiconductor characteristic is P+ type.

31. The MOSFET of claim 28, wherein the device-wide body tie region is electrically coupled to the shallow source region.

32. The MOSFET of claim 28, wherein the device-wide body tie region is electrically biased independently of the shallow source region.

33. A MOSFET including:(a) an active layer;(b) a body region fabricated within the active layer and doped to have a first semiconductor characteristic;(c) a gate structure formed above the body region;(d) a drift region fabricated within the active layer adjacent to a first side of the body region and doped to have a second semiconductor characteristic;(e) a drain region fabricated within the active layer adjacent to the drift region and doped to have a third semiconductor characteristic;(f) a shallow source region fabricated within the active layer proximate to a second side of the body region and doped to have a fourth semiconductor characteristic; and(g) a device-wide body tie region fabricated within the active layer adjacent to the shallow source region and doped to have a fifth semiconductor characteristic;wherein the body region extends below the shallow source region to be in contact with the device-wide body tie region.

34. The MOSFET of claim 33, wherein the active layer is formed on an insulating layer supported by a substrate.

35. The MOSFET of claim 33, wherein the first semiconductor characteristic is P-type, the second semiconductor characteristic is N- type, the third semiconductor characteristic is N+ type, the fourth semiconductor characteristic is N+ type, and the fifth semiconductor characteristic is P+ type.

36. The MOSFET of claim 33, wherein the device-wide body tie region is electrically coupled to the shallow source region.

37. The MOSFET of claim 33, wherein the device-wide body tie region is electrically biased independently of the shallow source region.

38. AMOSFET including:(a) an active layer;(b) a body region fabricated within the active layer and doped to have a first semiconductor characteristic;(c) a gate structure formed above the body region;(d) a drift region fabricated within the active layer adjacent to a first side of the body region and doped to have a second semiconductor characteristic;(e) a drain region fabricated within the active layer adjacent to the drift region and doped to have a third semiconductor characteristic;(f) a shallow source region fabricated within the active layer proximate to a second side of the body region and doped to have a fourth semiconductor characteristic;(g) a device-wide body tie region fabricated within the active layer adjacent to the shallow source region and doped to have a fifth semiconductor characteristic; and(h) an expanded halo region fabricated within the active layer below the shallow source region and in contact with the body region and the device- wide body tie region and doped to have a sixth semiconductor characteristic.

39. The MOSFET of claim 38, wherein the active layer is formed on an insulating layer supported by a substrate.

40. The MOSFET of claim 38, wherein the first semiconductor characteristic is P-type, the second semiconductor characteristic is N- type, the third semiconductor characteristic is N+ type, the fourth semiconductor characteristic is N+ type, the fifth semiconductor characteristic is P+ type, and the sixth semiconductor characteristic is P or P+ type.

41. The MOSFET of claim 38, wherein the device-wide body tie region is electrically coupled to the shallow source region.

42. The MOSFET of claim 38, wherein the device- wide body tie region is electrically biased independently of the shallow source region.

43. A method of fabricating an integrated circuit on a substrate and including:(a) fabricating a body region within an active layer of the integrated circuit, the body region doped to have a first semiconductor characteristic;(b) fabricating a gate structure above the body region;(c) fabricating a shallow source region within the active layer adjacent to a side of the body region and doped to have a second semiconductor characteristic;(d) fabricating a device-wide body tie region within the active layer adjacent to the shallow source region and doped to have a third semiconductor characteristic; and(e) fabricating a pathway between the body region and the device-wide body tie region, wherein the pathway enables collection and conveyance of holes from the body over to the device- wide body tie.

44. The method of claim 43, wherein the pathway comprises a buried body contact region fabricated within the active layer below the shallow source region and in contact with the body region and the device-wide body tie region and doped to have a fourth semiconductor characteristic.

45. The method of claim 43, wherein the pathway comprises an extension of the body region below the shallow source region in contact with the device-wide body tie region.

46. The method of claim 43, wherein the pathway comprises an expanded halo region fabricated within the active layer below the shallow source region and in contact with the body region and the device-wide body tie region and doped to have a fourth semiconductor characteristic.

47. The method of claim 43, further including electrically coupling the device-wide body tie region to the shallow source region.

48. The method of claim 43, further including electrically biasing the device-wide body tie region independently of the shallow source region.

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