Display substrate and manufacturing method therefor, and display device

Abstract

A display substrate and a manufacturing method therefor, and a display device. The display substrate comprises a pixel driving circuit; the pixel driving circuit comprises a driving transistor, a capacitor, and a second transfer electrode (32); the driving transistor comprises a first active layer (11); the capacitor comprises a first plate (21) disposed on the side of the first active layer (11) away from the base (101), a second plate (42) disposed on the side of the first plate (21) away from the base (101), and a third plate (43) disposed on the side of the second plate (42) away from the base (101); and the second transfer electrode (32) is disposed on the side of the third plate (43) away from the base (101), is connected to the third plate (43) by means of a third via hole (V3), and is connected to the first plate (21) by means of a fourth via hole (V4).

Description

Display substrate and its preparation method, display device Technical Field

[0001] This article relates to, but is not limited to, the field of display technology, specifically to a display substrate and its preparation method, and a display device. Background Technology

[0002] Virtual reality (VR) display devices are devices that use visual and auditory input to block out a person's sense of the outside world, creating a feeling of being in a virtual environment. The display principle involves displaying images for the left and right eyes separately on the left and right screens, simulating the visual difference between the two eyes. Through technological means, each eye receives a corresponding image, and the two eyes, after receiving these different images, create a sense of depth in the mind.

[0003] Active matrix organic light-emitting diode (AMOLED) panels, due to their self-emissive properties, have high contrast, good viewing angles, and fast response times, making them very suitable for VR display devices.

[0004] Summary of the Invention

[0005] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0006] On one hand, this disclosure provides a display substrate, including a driving circuit layer disposed on a substrate. The driving circuit layer includes at least a plurality of circuit units, at least one of which includes a pixel driving circuit. The pixel driving circuit includes a driving transistor, a capacitor, and a second transition electrode. The driving transistor includes a first active layer. The capacitor includes a first electrode plate disposed on the side of the first active layer away from the substrate, a second electrode plate disposed on the side of the first electrode plate away from the substrate, and a third electrode plate disposed on the side of the second electrode plate away from the substrate. The second transition electrode is disposed on the side of the third electrode plate away from the substrate. A third via is disposed between the second transition electrode and the third electrode plate. A fourth via is disposed between the second transition electrode and the first electrode plate. The second transition electrode is connected to the third electrode plate through the third via and to the first electrode plate through the fourth via.

[0007] In an exemplary embodiment, the driving transistor further includes a first gate disposed on the side of the first active layer away from the substrate, and the first gate serves as the first plate of the capacitor.

[0008] In an exemplary embodiment, a fifth insulating layer is disposed between the second adapter electrode and the third electrode plate. The third via extends through the fifth insulating layer from the surface of the fifth insulating layer away from the substrate, exposing the surface of the third electrode plate away from the substrate. A fifth insulating layer, a fourth insulating layer, and a third insulating layer are disposed between the second adapter electrode and the first electrode plate. The fifth insulating layer, the fourth insulating layer, and the third insulating layer are arranged sequentially along the direction close to the substrate. The fourth via extends through the fifth insulating layer from the surface of the fifth insulating layer away from the substrate, sequentially extending through the fifth insulating layer, the fourth insulating layer, and the third insulating layer, exposing the surface of the first electrode plate away from the substrate.

[0009] In an exemplary embodiment, a second via is provided between the second electrode plate and the second end of the first active layer, and the second electrode plate is connected to the second end of the first active layer through the second via.

[0010] In an exemplary embodiment, the pixel driving circuit further includes a first adapter electrode and a first power line. The first adapter electrode is disposed on the side of the first active layer away from the substrate, and the first power line is disposed on the side of the first adapter electrode away from the substrate. A first via is disposed between the first adapter electrode and a first end of the first active layer, and the first adapter electrode is connected to the first end of the first active layer through the first via. A fifth via is disposed between the first power line and the first adapter electrode, and the first power line is connected to the first adapter electrode through the fifth via.

[0011] In an exemplary embodiment, the first adapter electrode and the second electrode plate are located in the same film layer and use the same semiconductor material; the first power line and the second adapter electrode are located in the same film layer and use the same semiconductor material.

[0012] In an exemplary embodiment, the first active layer is low-temperature polycrystalline silicon.

[0013] In an exemplary embodiment, the pixel driving circuit further includes a first switching transistor, the first switching transistor including a second active layer and a second gate disposed on the side of the second active layer away from the substrate.

[0014] In an exemplary embodiment, the second active layer and the first active layer are located in the same film layer and are made of the same semiconductor material.

[0015] In an exemplary embodiment, the second gate and the first electrode are located in the same film layer and are made of the same semiconductor material.

[0016] In an exemplary embodiment, the pixel driving circuit further includes a data signal line disposed on the side of the third electrode plate away from the substrate. A sixth via is provided between the data signal line and the first end of the second active layer, and the data signal line is connected to the first end of the second active layer through the sixth via.

[0017] In an exemplary embodiment, the pixel driving circuit further includes a fourth transition electrode, which is disposed on the side of the data signal line away from the substrate. A ninth via is provided between the fourth transition electrode and the second end of the second active layer, and the fourth transition electrode is connected to the second end of the second active layer through the ninth via. An eighth via is provided between the fourth transition electrode and the third electrode plate, and the fourth transition electrode is connected to the third electrode plate through the eighth via.

[0018] In an exemplary embodiment, the pixel driving circuit further includes a first light-emitting control transistor, the first light-emitting control transistor including a fourth active layer, the fourth active layer being disposed on the side of the third electrode away from the substrate, and at least a portion of the orthographic projection of the fourth active layer on the substrate overlapping the orthographic projection of the first active layer on the substrate.

[0019] In an exemplary embodiment, the pixel driving circuit further includes a third transition electrode and a fifth transition electrode. The third transition electrode is disposed between the third electrode plate and the fourth active layer. The fifth transition electrode is disposed on the side of the fourth active layer away from the substrate. A seventh via is disposed between the third transition electrode and the second electrode plate, and the third transition electrode is connected to the second electrode plate through the seventh via. A tenth via is disposed between the fifth transition electrode and the third transition electrode, and the fifth transition electrode is connected to the third transition electrode through the tenth via. An eleventh via is disposed between the fifth transition electrode and the first end of the fourth active layer, and the fifth transition electrode is connected to the first end of the fourth active layer through the eleventh via.

[0020] In an exemplary embodiment, the pixel driving circuit further includes a sixth transition electrode and a light-emitting device. The sixth transition electrode is disposed on the side of the fourth active layer away from the substrate, and the light-emitting device is disposed on the side of the sixth transition electrode away from the substrate. A twelfth via is provided between the sixth transition electrode and the second end of the fourth active layer. The sixth transition electrode is connected to the second end of the fourth active layer through the twelfth via, and the light-emitting device is connected to the sixth transition electrode.

[0021] In an exemplary embodiment, the pixel driving circuit further includes a second switching transistor, the second switching transistor including a third active layer, the third active layer being integrally connected with the fourth active layer and comprising the same material.

[0022] In an exemplary embodiment, the first light-emitting control transistor further includes a fifth gate and a sixth gate, the fifth gate being disposed on the side of the fourth active layer near the substrate, and the sixth gate being disposed on the side of the fourth active layer away from the substrate; the second switching transistor further includes a third gate and a fourth gate, the third gate being disposed on the side of the third active layer near the substrate, and the fourth gate being disposed on the side of the third active layer away from the substrate; the fifth gate and the third gate are located in the same film layer, and the sixth gate and the fourth gate are located in the same film layer.

[0023] In an exemplary embodiment, the pixel driving circuit further includes a seventh transition electrode and a reference signal line. The seventh transition electrode is disposed on the side of the third active layer away from the substrate, and the reference signal line is disposed on the side of the seventh transition electrode away from the substrate. A thirteenth via is disposed between the seventh transition electrode and the third active layer. The seventh transition electrode is connected to a first end of the third active layer through the thirteenth via, and the reference signal line is connected to the seventh transition electrode.

[0024] On the other hand, this disclosure also provides a display device including the aforementioned display substrate.

[0025] On the other hand, this disclosure also provides a method for preparing a display substrate, comprising:

[0026] A driving circuit layer is formed on a substrate. The driving circuit layer includes at least a plurality of circuit units, at least one of which includes a pixel driving circuit. The pixel driving circuit includes a driving transistor, a capacitor, and a second transition electrode. The driving transistor includes a first active layer. The capacitor includes a first electrode plate disposed on the side of the first active layer away from the substrate, a second electrode plate disposed on the side of the first electrode plate away from the substrate, and a third electrode plate disposed on the side of the second electrode plate away from the substrate. The second transition electrode is disposed on the side of the third electrode plate away from the substrate. A third via is disposed between the second transition electrode and the third electrode plate. A fourth via is disposed between the second transition electrode and the first electrode plate. The second transition electrode is connected to the third electrode plate through the third via and to the first electrode plate through the fourth via.

[0027] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0028] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0029] Figure 1 is a schematic diagram of the structure of a display device;

[0030] Figure 2 is a schematic diagram of a planar structure of a display substrate;

[0031] Figure 3 is a schematic cross-sectional view of a display substrate;

[0032] Figure 4 is an equivalent circuit diagram of a pixel driving circuit of a display substrate according to an exemplary embodiment of the present disclosure;

[0033] Figure 5 is a schematic diagram of a display substrate after the formation of the first semiconductor layer pattern according to the present disclosure;

[0034] Figure 6 is a schematic diagram of a display substrate after the formation of the first conductive layer pattern according to the present disclosure;

[0035] Figure 7 is a schematic diagram of a display substrate after the formation of a third insulating layer pattern according to the present disclosure;

[0036] Figure 8 is a schematic diagram of a display substrate after the formation of the second conductive layer pattern according to the present disclosure;

[0037] Figure 9 is a schematic diagram of a display substrate after the formation of a third conductive layer pattern according to the present disclosure;

[0038] Figure 10 is a schematic diagram of a display substrate after the formation of the fifth insulating layer pattern according to the present disclosure;

[0039] Figure 11 is a schematic diagram of a display substrate after the formation of the fourth conductive layer pattern according to the present disclosure;

[0040] Figure 12 is a schematic diagram of a display substrate after the formation of the sixth insulating layer pattern according to the present disclosure;

[0041] Figure 13 is a schematic diagram of a display substrate after the formation of the fifth conductive layer pattern according to the present disclosure;

[0042] Figure 14 is a schematic diagram of a display substrate after the formation of the sixth conductive layer pattern according to the present disclosure;

[0043] Figure 15 is a schematic diagram of a display substrate after the formation of a second semiconductor layer pattern according to the present disclosure;

[0044] Figure 16 is a schematic diagram of a display substrate after the formation of the seventh conductive layer pattern according to the present disclosure;

[0045] Figure 17 is a schematic diagram of a display substrate after the formation of the tenth insulating layer pattern according to the present disclosure;

[0046] Figure 18 is a schematic diagram of a display substrate after the formation of the eighth conductive layer pattern according to the present disclosure. Detailed Implementation

[0047] To make the objectives, technical solutions, and advantages of this disclosure clearer, embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be varied in various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0048] The scale of the figures in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The figures described in this disclosure are only schematic diagrams of the structure, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0049] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0050] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0051] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0052] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0053] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged, and the "source terminal" and "drain terminal" can be interchanged.

[0054] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0055] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0056] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0057] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0058] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0059] The inventors of this publication have discovered that VR display devices, due to the close proximity of the screen to the human eye, require a high pixel density (PPI) to ensure clear display content and eliminate the "screen door effect," for example, a pixel density of 1200 PPI or 1500 PPI. However, the pixel driving circuitry of AMOLED backplanes is complex, with a large number of thin-film transistors (TFTs), and the high pixel density significantly reduces the space available for the pixel driving circuitry.

[0060] Related display substrates compress the space for pixel driving circuits by stacking thin-film transistors. For example, in an LTPO backplane, oxide semiconductor thin-film transistors are placed above low-temperature polycrystalline silicon thin-film transistors. However, the fabrication process of such backplanes involves many steps, making manufacturing difficult and costly.

[0061] Figure 1 is a schematic diagram of a display device. As shown in Figure 1, the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is connected to the data driver, the scan driver, and the light-emitting driver. The data driver is connected to multiple data signal lines (D1 to Dn), the scan driver is connected to multiple scan signal lines (S1 to Sm), and the light-emitting driver is connected to multiple light-emitting signal lines (E1 to Eo). The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit, which is connected to the scan signal lines, the light-emitting signal lines, and the data signal lines. The light-emitting unit may include a light-emitting device, which is connected to the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller can provide grayscale values ​​and control signals of specifications suitable for the data driver to the data driver, provide clock signals, scan start signals, etc. of specifications suitable for the scan driver to the scan driver, and provide clock signals, transmit stop signals, etc. of specifications suitable for the light-emitting driver to the light-emitting driver. The data driver can use grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data signal lines D1, D2, D3, ..., Dn. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn in pixel rows, where n can be a natural number. The scan driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ..., Sm by receiving clock signals, scan start signals, etc., from the timing controller. For example, the scan driver can sequentially provide scan signals with on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals in the form of on-level pulses to the next stage circuit under the control of a clock signal, where m can be a natural number. The light-emitting driver can generate transmit signals to be provided to light-emitting signal lines E1, E2, E3, ..., Eo by receiving clock signals, transmit stop signals, etc., from the timing controller. For example, the light-emitting driver can sequentially provide transmit signals with cutoff level pulses to the light-emitting signal lines E1 to Eo. For example, the light-emitting driver can be configured as a shift register and can generate transmit signals by sequentially transmitting transmit stop signals in the form of cutoff level pulses to the next stage circuit under the control of a clock signal, where o can be a natural number. In an exemplary embodiment, a pixel array can be disposed on a display substrate.

[0062] Figure 2 is a schematic diagram of a planar structure of a display substrate. In an exemplary embodiment, the display substrate may include a display area and a border area surrounding the display area. As shown in Figure 2, the display area of ​​the display substrate may include a plurality of pixel units P arranged in a matrix. At least one pixel unit P may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. Each sub-pixel may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit, which is connected to a scan signal line, a data signal line, and a light-emitting signal line, respectively. The pixel driving circuit is configured to receive the data voltage transmitted by the data signal line and output a corresponding current to the light-emitting device under the control of the scan signal line and the light-emitting signal line. The light-emitting unit may include at least a light-emitting device, which is connected to the pixel driving circuit of the sub-pixel and is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel.

[0063] In an exemplary embodiment, the first sub-pixel P1 can be a red sub-pixel (R) that emits red light, the second sub-pixel P2 can be a blue sub-pixel (B) that emits blue light, and the third sub-pixel P3 can be a green sub-pixel (G) that emits green light. In an exemplary embodiment, the shape of the sub-pixels can be rectangular, rhomboid, pentagonal, or hexagonal, and the three sub-pixels can be arranged in a horizontal, vertical, or triangular manner, etc., which is not limited herein.

[0064] In an exemplary embodiment, a pixel unit may include four sub-pixels, which may be arranged in a horizontal, vertical, or square manner, etc., and this disclosure does not limit the arrangement.

[0065] Figure 3 is a schematic cross-sectional view of a display substrate. As shown in Figure 3, on a plane perpendicular to the display substrate, the display area of ​​the display substrate may include a driving circuit layer 102 disposed on a substrate 101, a light-emitting structure layer 103 disposed on the side of the driving circuit layer 102 away from the substrate 101, and an encapsulation structure layer 104 disposed on the side of the light-emitting structure layer 103 away from the substrate 101. In some possible implementations, the display substrate may include other film layers, such as a touch structure layer, etc., which are not limited herein.

[0066] In an exemplary embodiment, the substrate 101 can be a flexible substrate or a rigid substrate. The driving circuit layer 102 can include multiple circuit units, each of which can include at least a pixel driving circuit, and the pixel driving circuit can include multiple transistors and storage capacitors. The light-emitting structure layer 103 can include multiple light-emitting units, each of which can include at least a light-emitting device. The light-emitting device can include an anode, a light-emitting functional layer, and a cathode. The anode is connected to the pixel driving circuit, the light-emitting functional layer is connected to the anode, and the cathode is connected to the light-emitting functional layer. The light-emitting functional layer emits light of a corresponding color under the driving of the anode and cathode. The encapsulation structure layer 104 can include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers can be made of inorganic materials, and the second encapsulation layer can be made of organic materials. The second encapsulation layer is disposed between the first and third encapsulation layers, forming an inorganic / organic / inorganic material stacked structure, which can ensure that external moisture cannot enter the light-emitting structure layer 103.

[0067] In an exemplary embodiment, the light-emitting functional layer may include a light-emitting layer (EML) and any one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL).

[0068] The display substrate of this disclosure will be illustrated by some exemplary embodiments below.

[0069] Figure 4 is an equivalent circuit diagram of a pixel driving circuit for a display substrate according to an exemplary embodiment of the present disclosure. In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, 8T1C, or 9T2C structure. As shown in Figure 4, the pixel driving circuit of the exemplary embodiment of the present disclosure may be a 4T1C structure, which may include four transistors (first transistor T1 to fourth transistor T4) and one storage capacitor C. The pixel driving circuit is connected to the reference signal line REF, the data signal line DATA, the first power supply line VDD, the second power supply line VSS, the scan signal line SCAN, and the light emission signal line EM, respectively.

[0070] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, a fourth node N4, and a fifth node N5. The first node N1 is connected to the second terminal of the second transistor T2, the gate of the first transistor T1, and the first terminal of the storage capacitor C. The second node N2 is connected to the second terminal of the third transistor T3, the second terminal of the storage capacitor C, the second terminal of the first transistor T1, and the first terminal of the fourth transistor T4. The fourth node N4 is connected to the data signal line DATA and the first terminal of the second transistor T2. The fifth node N5 is connected to the reference signal line REF and the first terminal of the third transistor T3.

[0071] In an exemplary embodiment, the first end (first plate) of the storage capacitor C is connected to the first node N1, and the second end (second plate) of the storage capacitor C is connected to the second node N2.

[0072] In an exemplary embodiment, the first transistor T1 is a driving transistor; the second transistor T2 is a first switching transistor for writing data signals; the third transistor T3 is a second switching transistor for extracting threshold voltage or current; and the fourth transistor T4 is a first light-emitting control transistor.

[0073] In an exemplary embodiment, the gate electrode of the first transistor T1 is connected to the first node N1, and through the first node N1, it is connected to the second terminal of the second transistor and the first terminal of the storage capacitor C. The first terminal of the first transistor T1 is connected to the first power supply line VDD, and the second terminal of the first transistor T1 is connected to the second node N2. Through the second node N2, it is connected to the second terminal of the third transistor, the second terminal of the storage capacitor C, and the first terminal of the fourth transistor T4. The first transistor T1 is used to generate a corresponding current at its second terminal under the control of the data signal received at its gate electrode, thereby controlling the light-emitting device EL to emit light. The gate electrode of the second transistor T2 is connected to the scan signal line SCAN, and the first terminal of the second transistor T2 is connected to the data signal line DATA through the fourth node N4. The second terminal of the second transistor T2 is connected to the first node N1, and through the first node N1, it is connected to the first terminal of the capacitor C and the gate of the first transistor T1. The second transistor T2 is used to receive the data signal transmitted by the data signal line DATA under the control of the scan signal line SCAN. The gate electrode of the third transistor T3 is connected to the scan signal line SCAN. The first terminal of the third transistor T3 is connected to the reference signal line REF through the fifth node N5. The second terminal of the third transistor T3 is connected to the second node N2, and through the second node N2, it is connected to the second terminal of capacitor C, the second terminal of the first transistor T1, and the first terminal of the fourth transistor T4. The third transistor T3 is used to extract the threshold voltage Vth and mobility of the third transistor T3 in response to the compensation timing, so as to compensate for the threshold voltage Vth. The gate electrode of the fourth transistor T4 is connected to the first light-emitting signal line EM. The first terminal of the fourth transistor T4 is connected to the second node N2, and the second terminal of the fourth transistor T4 is connected to the first terminal of the light-emitting device EL.

[0074] In an exemplary embodiment, the first terminal of the light-emitting device EL is connected to the second terminal of the fourth transistor T4, and the second terminal of the light-emitting device EL is connected to the second power line VSS. The signal of the second power line VSS is a continuously supplied low-level signal, and the signal of the first power line VDD is a continuously supplied high-level signal.

[0075] In an exemplary embodiment, the light-emitting device EL can be an OLED, including a stacked first electrode (anode), a light-emitting functional layer, and a second electrode (cathode); the light-emitting device EL can be a QLED, including a stacked first electrode (anode), a quantum dot light-emitting layer, and a second electrode (cathode); or, the light-emitting device EL can be an LED.

[0076] In an exemplary embodiment, the first transistor T1 and the second transistor T2 can be low-temperature polysilicon (LTPS) thin-film transistors (TFTs), and the third transistor T3 and the fourth transistor T4 can be oxide (O4) thin-film transistors (TFTs). The active layer of the LTPS TFT is made of low-temperature polysilicon (LTPS), while the active layer of the O4 TFT is made of oxide semiconductor. LTPS TFTs have advantages such as high mobility and fast charging, while O4 TFTs have advantages such as low leakage current. Integrating LTPS TFTs and O4 TFTs onto a single display substrate, i.e., an LTPS+Oxide (LTPO) display substrate, leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0077] This disclosure provides a display substrate including a driving circuit layer disposed on a substrate. The driving circuit layer includes at least a plurality of circuit units, at least one of which includes a pixel driving circuit. The pixel driving circuit includes a driving transistor, a capacitor, and a second transition electrode. The driving transistor includes a first active layer. The capacitor includes a first electrode plate disposed on the side of the first active layer away from the substrate, a second electrode plate disposed on the side of the first electrode plate away from the substrate, and a third electrode plate disposed on the side of the second electrode plate away from the substrate. The second transition electrode is disposed on the side of the third electrode plate away from the substrate. A third via is disposed between the second transition electrode and the third electrode plate, and a fourth via is disposed between the second transition electrode and the first electrode plate. The second transition electrode is connected to the third electrode plate through the third via and to the first electrode plate through the fourth via.

[0078] In an exemplary embodiment, the driving transistor further includes a first gate disposed on the side of the first active layer away from the substrate, and the first gate serves as the first plate of the capacitor.

[0079] In an exemplary embodiment, a fifth insulating layer is disposed between the second adapter electrode and the third electrode plate. The third via extends through the fifth insulating layer from the surface of the fifth insulating layer away from the substrate, exposing the surface of the third electrode plate away from the substrate. A fifth insulating layer, a fourth insulating layer, and a third insulating layer are disposed between the second adapter electrode and the first electrode plate. The fifth insulating layer, the fourth insulating layer, and the third insulating layer are arranged sequentially along the direction close to the substrate. The fourth via extends through the fifth insulating layer from the surface of the fifth insulating layer away from the substrate, sequentially extending through the fifth insulating layer, the fourth insulating layer, and the third insulating layer, exposing the surface of the first electrode plate away from the substrate.

[0080] The following description uses the fabrication process of a display substrate as an example. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film made of a certain material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0081] In an exemplary embodiment, the circuit unit referred to in this disclosure refers to a region divided according to the pixel driving circuit, and the light-emitting unit referred to in this disclosure refers to a region divided according to the light-emitting device.

[0082] In an exemplary embodiment, the position of the light-emitting unit projected onto the substrate may correspond to the position of the circuit unit projected onto the substrate, or the position of the light-emitting unit projected onto the substrate may not correspond to the position of the circuit unit projected onto the substrate.

[0083] The fabrication process of the display substrate in this embodiment may include the following operations.

[0084] (101) Forming a first semiconductor layer pattern. In an exemplary embodiment, forming a first semiconductor layer pattern may include: sequentially depositing a first insulating film and a first semiconductor film on a substrate, patterning the first semiconductor film through a patterning process to form a first insulating layer 201 covering the substrate 101, and forming a first semiconductor layer pattern disposed on the first insulating layer 201, as shown in FIG5.

[0085] In an exemplary embodiment, the first semiconductor layer pattern may include a first active layer 11 and a second active layer 12, wherein the orthographic projection of the first active layer 11 onto the substrate 101 and the orthographic projection of the second active layer 12 onto the substrate 101 do not overlap. Both the first active layer 11 and the second active layer 12 may be low-temperature polycrystalline silicon.

[0086] In an exemplary embodiment, the first insulating layer 201 may be a silicon oxide compound. The first insulating layer 201 may be referred to as the first buffer layer (Buffer1).

[0087] (102) Forming a first conductive layer pattern. In an exemplary embodiment, forming a first conductive layer pattern may include: depositing a second insulating film and a first conductive film sequentially on a substrate on which the aforementioned pattern is formed; patterning the first conductive film using a patterning process; forming a second insulating layer 202 covering the first semiconductor layer pattern on the second insulating film; and forming a first conductive layer pattern disposed on the second insulating layer 202 on the first conductive film, as shown in FIG6.

[0088] In an exemplary embodiment, the first conductive layer pattern may include a first gate 21 and a second gate 22. The orthographic projection of the first gate 21 on the substrate 101 does not overlap with the orthographic projection of the second gate 22 on the substrate 101. The orthographic projection of the first gate 21 on the substrate 101 overlaps with the orthographic projection of the first active layer 11 on the substrate 101; the orthographic projection of the second gate 22 on the substrate 101 overlaps with the orthographic projection of the second active layer 12 on the substrate 101. The first gate 21 and the first active layer 11 form a first transistor; the second gate 22 and the second active layer 12 form a second transistor.

[0089] In an exemplary embodiment, both the first gate 21 and the second gate 22 can be single-layer structures, such as copper or molybdenum; or, both the first gate 21 and the second gate 22 can be multi-layer structures, such as titanium / aluminum / titanium stacked structures.

[0090] In an exemplary embodiment, the second insulating layer 202 may be a silicon nitride compound or a silicon oxide compound. The second insulating layer 202 may be referred to as the first gate insulating layer (GI1).

[0091] (103) Forming a third insulating layer pattern. In an exemplary embodiment, forming a third insulating layer pattern may include: depositing a third insulating film on a substrate on which the aforementioned pattern is formed, and patterning the third insulating film using a patterning process to form a third insulating layer 203 covering the first conductive layer pattern, wherein the third insulating layer 203 in each circuit unit is provided with a plurality of vias, as shown in FIG7.

[0092] In an exemplary embodiment, the plurality of vias in the third insulating layer 203 of each circuit unit include a first via V1 and a second via V2. The orthographic projection of the first via V1 onto the substrate lies within the orthographic projection of the first end of the first active layer 11 onto the substrate. The third insulating layer 203 and the second insulating layer 202 within the first via V1 are etched away, exposing the surface of the first end of the first active layer 11. The first via V1 is configured to allow a subsequently formed first transition electrode to connect to the first end of the first active layer 11 through the via. The orthographic projection of the second via V2 onto the substrate lies within the orthographic projection of the second end of the first active layer 11 onto the substrate. The third insulating layer 203 and the second insulating layer 202 within the second via V2 are etched away, exposing the surface of the second end of the first active layer 11. The second via V2 is configured to allow a subsequently formed second electrode plate to connect to the second end of the first active layer 11 through the via.

[0093] In an exemplary embodiment, the third insulating layer 203 may be a silicon nitride compound or a silicon oxide compound. The third insulating layer 203 may be referred to as the second gate insulating layer (GI2).

[0094] (104) Forming a second conductive layer pattern. In an exemplary embodiment, forming a second conductive layer pattern may include: depositing a second conductive film on a substrate on which the aforementioned pattern is formed, and patterning the second conductive film using a patterning process to form a second conductive layer pattern disposed on the third insulating layer 203, as shown in FIG8.

[0095] In an exemplary embodiment, the second conductive layer pattern may include a first transition electrode 31 and a second electrode plate 42. The first transition electrode 31 is connected to a first end of the first active layer 11 through a first via V1.

[0096] In an exemplary embodiment, the orthographic projection of the first portion of the second electrode plate 42 onto the substrate overlaps with the orthographic projection of the first gate 21 onto the substrate, forming a capacitor C. The first gate 21 serves as the first electrode plate of the capacitor C. The orthographic projection of the second portion of the second electrode plate 42 onto the substrate does not overlap with the orthographic projection of the first gate 21 onto the substrate, and the second portion of the second electrode plate 42 is connected to the second end of the first active layer 11 through a second via V2.

[0097] In an exemplary embodiment, both the first transfer electrode 31 and the second electrode plate 42 can be single-layer structures, such as copper or molybdenum; or, both the first transfer electrode 31 and the second electrode plate 42 can be multi-layer structures, such as titanium / aluminum / titanium stacked structures.

[0098] (105) Forming a third conductive layer pattern. In an exemplary embodiment, forming a third conductive layer pattern may include: depositing a fourth insulating film and a third conductive film sequentially on a substrate on which the aforementioned pattern is formed; patterning the third conductive film using a patterning process to form a fourth insulating layer 204 covering the second conductive layer pattern; and forming a third conductive layer pattern disposed on the fourth insulating layer 204, as shown in FIG9.

[0099] In an exemplary embodiment, the third conductive layer pattern may include a third electrode 43, the orthographic projection of the first portion of the third electrode 43 on the substrate overlapping the orthographic projection of the second portion of the second electrode 42 on the substrate, the first portion of the third electrode 43 serving as one electrode of capacitor C. The orthographic projection of the second portion of the third electrode 43 on the substrate does not overlap with the orthographic projection of the second electrode 42 on the substrate, and the second portion of the third electrode 43 is configured to connect to a subsequently formed second transition electrode.

[0100] In an exemplary embodiment, the third electrode 43, the second electrode 42, and the first electrode 43 form a capacitor, and the third electrode 43 and the first electrode are connected in a subsequent process via a second transfer electrode.

[0101] In an exemplary embodiment, the third electrode plate 43 can be a single-layer structure, such as copper or molybdenum; or, the third electrode plate 43 can be a multi-layer structure, such as a titanium / aluminum / titanium laminate structure.

[0102] In an exemplary embodiment, the fourth insulating layer 204 may be a silicon nitride compound or a silicon oxide compound. The fourth insulating layer 204 may be referred to as the third gate insulating layer (GI3).

[0103] (106) Forming a fifth insulating layer pattern. In an exemplary embodiment, forming a fifth insulating layer pattern may include: depositing a fifth insulating film on a substrate on which the aforementioned pattern is formed, and patterning the fifth insulating film using a patterning process to form a fifth insulating layer 205 covering the third conductive layer pattern, wherein the fifth insulating layer 205 in each circuit unit is provided with a plurality of vias, as shown in FIG10.

[0104] In an exemplary embodiment, the plurality of vias in the fifth insulating layer 205 of each circuit unit include a third via V3, a fourth via V4, a fifth via V5, and a sixth via V6. The orthographic projection of the third via V3 onto the substrate lies within the orthographic projection of the second portion of the third electrode plate 43 onto the substrate. The fifth insulating layer 205 within the third via V3 is etched away, exposing the surface of the second portion of the third electrode plate 43. The third via V3 is configured to allow a subsequently formed second transition electrode to connect to the second portion of the third electrode plate 43 through this via.

[0105] In an exemplary embodiment, the orthographic projection of the fourth via V4 on the substrate is located within the orthographic projection of the first gate 21 on the substrate. The fifth insulating layer 205, the fourth insulating layer 204, and the third insulating layer 203 within the fourth via V4 are etched away, exposing the surface of the first gate 21. The fourth via V4 is configured to allow the subsequently formed second transition electrode to be connected to the first gate 21 through the via.

[0106] In an exemplary embodiment, the orthographic projection of the fifth via V5 on the substrate lies within the orthographic projection of the first adapter electrode 31 on the substrate. The fifth insulating layer 205 and the fourth insulating layer 204 within the fifth via V5 are etched away, exposing the surface of the first adapter electrode 31. The fifth via V5 is configured to allow the subsequently formed first power line (VDD) to be connected to the first adapter electrode 31 through the via.

[0107] In an exemplary embodiment, the orthographic projection of the sixth via V6 on the substrate lies within the orthographic projection of the second active layer 12 on the substrate. The fifth insulating layer 205, the fourth insulating layer 204, the third insulating layer 203, and the second insulating layer 202 within the sixth via V6 are etched away, exposing the surface of the first end of the second active layer 12. The sixth via V6 is configured to allow a subsequently formed data signal line (DATA) to be connected to the first end of the second active layer 12 through the via.

[0108] In an exemplary embodiment, the fifth insulating layer 205 may be a silicon nitride compound or a silicon oxide compound. The fifth insulating layer 205 may be referred to as the fourth gate insulating layer (GI4).

[0109] (107) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming a fourth conductive layer pattern may include: depositing a fourth conductive film on a substrate on which the aforementioned pattern is formed, and patterning the fourth conductive film by a patterning process to form a fourth conductive layer pattern disposed on the fifth insulating layer 205, as shown in FIG11.

[0110] In an exemplary embodiment, the fourth conductive layer pattern may include a second transition electrode 32, a first power line (VDD), and a data signal line (DATA). The second transition electrode 32 is connected to the second part of the third electrode plate 43 through a third via V3, and is connected to the first gate 21 through a fourth via V4. The first power line (VDD) is connected to the first transition electrode 31 through a fifth via V5. The data signal line (DATA) is connected to the first end of the second active layer 12 through a sixth via V6.

[0111] In an exemplary embodiment, the second transfer electrode 32, the first power line (VDD), and the data signal line (DATA) can all be single-layer structures, such as copper or molybdenum; or, the second transfer electrode 32, the first power line (VDD), and the data signal line (DATA) can all be multi-layer structures, such as titanium / aluminum / titanium stacked structures.

[0112] (108) Forming a sixth insulating layer pattern. In an exemplary embodiment, forming a sixth insulating layer pattern may include: depositing a sixth insulating film on a substrate on which the aforementioned pattern is formed, and patterning the sixth insulating film using a patterning process to form a sixth insulating layer 206 covering the fourth conductive layer pattern, wherein the sixth insulating layer 206 in each circuit unit is provided with a plurality of vias, as shown in FIG12.

[0113] In an exemplary embodiment, the plurality of vias in the sixth insulating layer of each circuit unit include a seventh via V7, an eighth via V8, and a ninth via V9. The orthographic projection of the seventh via V7 on the substrate is located within the orthographic projection of the second electrode plate 42 on the substrate. The sixth insulating layer 206, the fifth insulating layer 205, and the fourth insulating layer 204 within the seventh via V7 are etched away, exposing a portion of the surface of the second electrode plate 42. The seventh via V7 is configured to allow a subsequently formed third transition electrode to be connected to the second electrode plate 42 through the via.

[0114] In an exemplary embodiment, the orthographic projection of the eighth via V8 on the substrate is located within the orthographic projection of the third electrode plate 43 on the substrate. The sixth insulating layer 206 and the fifth insulating layer 205 within the eighth via V8 are etched away, exposing a portion of the surface of the third electrode plate 43. The eighth via V8 is configured to allow the subsequently formed fourth transition electrode to be connected to the third electrode plate 43 through the via.

[0115] In an exemplary embodiment, the orthographic projection of the ninth via V9 on the substrate is located within the orthographic projection of the second end of the second active layer 12 on the substrate. The sixth insulating layer 206, the fifth insulating layer 205, the fourth insulating layer 204, the third insulating layer 203, and the second insulating layer 202 within the ninth via V9 are etched away, exposing a portion of the surface of the second end of the second active layer 12. The ninth via V9 is configured to allow the subsequently formed fourth transition electrode to connect to the second end of the second active layer 12 through the via.

[0116] In an exemplary embodiment, the sixth insulating layer 206 may be a silicon nitride compound or a silicon oxide compound. The sixth insulating layer 206 may be referred to as the first interlayer dielectric layer (ILD1).

[0117] (109) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming a fifth conductive layer pattern may include: depositing a fifth conductive film on a substrate on which the aforementioned pattern is formed, and patterning the fifth conductive film by a patterning process to form a fifth conductive layer pattern disposed on the sixth insulating layer 206, as shown in FIG13.

[0118] In an exemplary embodiment, the fifth conductive layer pattern includes a third transition electrode 33 and a fourth transition electrode 34. The third transition electrode 33 is connected to the second electrode plate 42 through a seventh via V7. The fourth transition electrode 34 is connected to the third electrode plate 43 through an eighth via V8, and is connected to the second end of the second active layer 12 through a ninth via V9.

[0119] In an exemplary embodiment, both the third transfer electrode 33 and the fourth transfer electrode 34 can be single-layer structures, such as copper or molybdenum; or, both the third transfer electrode 33 and the fourth transfer electrode 34 can be multi-layer structures, such as titanium / aluminum / titanium stacked structures.

[0120] (110) Forming a sixth conductive layer pattern. In an exemplary embodiment, forming a sixth conductive layer pattern may include: sequentially depositing a first organic thin film, a seventh insulating thin film, and a sixth conductive thin film on a substrate on which the aforementioned pattern is formed; patterning the sixth conductive thin film using a patterning process, such that the first organic thin film forms a first organic dielectric layer 301 covering the fifth conductive layer pattern; the seventh insulating thin film forms a seventh insulating layer 207 disposed on the first organic dielectric layer 301; and the sixth conductive thin film forms a sixth conductive layer pattern disposed on the seventh insulating layer 207. The sixth conductive layer pattern includes a third gate 23 and a fifth gate 31, as shown in FIG14. The third gate 23 may serve as the bottom gate of a subsequently formed third transistor, and the fifth gate 31 may serve as the bottom gate of a subsequently formed fourth transistor.

[0121] In an exemplary embodiment, the first organic dielectric layer 301 may be made of an organic material, such as resin, and may be referred to as a first planarization layer. The seventh insulating layer 207 may be a silicon nitride compound or a silicon oxide compound. The seventh insulating layer 207 may be referred to as a second buffer layer (Buffer2). The third gate 23 may be a single-layer structure, such as copper or molybdenum; or, the third gate 23 may be a multi-layer structure, such as a titanium / aluminum / titanium stacked structure.

[0122] (111) Forming a second semiconductor layer pattern. In an exemplary embodiment, forming a second semiconductor layer pattern may include: sequentially depositing an eighth insulating film and a second semiconductor film on a substrate, patterning the second semiconductor film through a patterning process to form an eighth insulating layer 208 covering the sixth conductive layer pattern, and forming a second semiconductor layer pattern disposed on the eighth insulating layer 208, as shown in FIG15.

[0123] In an exemplary embodiment, the second semiconductor layer pattern may include a third active layer 13 and a fourth active layer 14. The orthographic projection of the third active layer 13 onto the substrate 101 includes the orthographic projection of the third gate 23 onto the substrate 101, and the orthographic projection of the fourth active layer 14 onto the substrate 101 includes the orthographic projection of the fifth gate 31 onto the substrate 101. The third active layer 13 and the fourth active layer 14 may be connected as a single unit, and both the third active layer 13 and the fourth active layer 14 may be oxide semiconductors. The third active layer 13 may serve as the active layer of a subsequently formed third transistor, and the fourth active layer 14 may serve as the active layer of a subsequently formed fourth transistor.

[0124] In an exemplary embodiment, the orthographic projection of the third active layer 13 on the substrate 101 overlaps with the orthographic projection of the second active layer 12 on the substrate 101. The orthographic projection of the fourth active layer 14 on the substrate 101 overlaps with the orthographic projection of the first active layer 11 on the substrate 101.

[0125] In an exemplary embodiment, the eighth insulating layer 208 may be a silicon nitride compound or a silicon oxide compound. The eighth insulating layer 208 may be referred to as the fifth gate insulating layer (GI5).

[0126] (112) Forming a seventh conductive layer pattern. In an exemplary embodiment, forming a seventh conductive layer pattern may include: depositing a ninth insulating film and a seventh conductive film sequentially on a substrate on which the aforementioned pattern is formed, patterning the seventh conductive film by a patterning process, so that the ninth insulating film forms a ninth insulating layer 209 covering the third active layer 13, and forming a seventh conductive layer pattern disposed on the ninth insulating layer 209, as shown in FIG16.

[0127] (113) In an exemplary embodiment, the seventh conductive layer pattern includes a fourth gate 24 and a sixth gate 32. The orthographic projection of the fourth gate 24 onto the substrate lies within the orthographic projection of the third active layer 13 onto the substrate, and the orthographic projection of the sixth gate 32 onto the substrate lies within the orthographic projection of the fourth active layer 14 onto the substrate. The fourth gate 24 can serve as the top gate of a subsequently formed third transistor, and the sixth gate 32 can serve as the top gate of a subsequently formed fourth transistor. The third gate 23, the third active layer 13, and the fourth gate 24 form a third transistor, which is a dual-gate structure. The fifth gate 31, the fourth active layer 14, and the sixth gate 32 form a fourth transistor, which is also a dual-gate structure.

[0128] In an exemplary embodiment, the ninth insulating layer 209 may be a silicon nitride compound or a silicon oxide compound. The ninth insulating layer 209 may be referred to as the sixth gate insulating layer (GI6).

[0129] (114) Forming a tenth insulating layer pattern. In an exemplary embodiment, forming a tenth insulating layer pattern may include: depositing a tenth insulating film on a substrate on which the aforementioned pattern is formed, and patterning the tenth insulating film using a patterning process to form a tenth insulating layer 210 covering the pattern of the seventh conductive layer, wherein the tenth insulating layer 210 in each circuit unit is provided with a plurality of vias, as shown in FIG17.

[0130] In an exemplary embodiment, the plurality of vias in the tenth insulating layer 210 of each circuit unit include a tenth via V10, an eleventh via V11, a twelfth via V12, and a thirteenth via V13. The orthographic projection of the tenth via V10 onto the substrate lies within the orthographic projection of the third transition electrode 33 onto the substrate. The tenth insulating layer 210, the ninth insulating layer 209, the eighth insulating layer 208, the seventh insulating layer 207, and the first organic dielectric layer 301 within the tenth via V10 are etched away, exposing a portion of the surface of the third transition electrode 33. The tenth via V10 is configured to allow a subsequently formed fifth transition electrode to connect to the third transition electrode 33 through this via.

[0131] In an exemplary embodiment, the orthographic projection of the eleventh via V11 onto the substrate lies within the orthographic projection of the first end of the fourth active layer 14 onto the substrate. The tenth insulating layer 210 and the ninth insulating layer 209 within the eleventh via V11 are etched away, exposing a portion of the surface of the first end of the fourth active layer 14. The eleventh via V11 is configured to allow the subsequently formed fifth transition electrode to connect to the first end of the fourth active layer 14 through the via.

[0132] In an exemplary embodiment, the orthographic projection of the twelfth via V12 on the substrate is located within the orthographic projection of the second end of the fourth active layer 14 on the substrate. The tenth insulating layer 210 and the ninth insulating layer 209 within the twelfth via V12 are etched away, exposing a portion of the surface of the second end of the fourth active layer 14. The twelfth via V12 is configured to allow the subsequently formed sixth transition electrode to connect to the second end of the fourth active layer 14 through the via.

[0133] In an exemplary embodiment, the orthographic projection of the thirteenth via V13 onto the substrate is located within the orthographic projection of the first end of the third active layer 13 onto the substrate. The tenth insulating layer 210 and the ninth insulating layer 209 within the thirteenth via V13 are etched away, exposing a portion of the surface of the first end of the third active layer 13. The thirteenth via V13 is configured to allow the subsequently formed seventh transition electrode to connect to the first end of the third active layer 13 through the via.

[0134] In an exemplary embodiment, the tenth insulating layer 210 may be a silicon nitride compound or a silicon oxide compound. The tenth insulating layer 210 may be referred to as the second interlayer dielectric layer (ILD2).

[0135] (115) Forming an eighth conductive layer pattern. In an exemplary embodiment, forming an eighth conductive layer pattern may include: depositing an eighth conductive film on a substrate on which the aforementioned pattern is formed, and patterning the eighth conductive film by a patterning process to form an eighth conductive layer pattern disposed on the tenth insulating layer 210, as shown in FIG18.

[0136] In an exemplary embodiment, the eighth conductive layer pattern includes a fifth transition electrode 35, a sixth transition electrode 36, and a seventh transition electrode 37. The fifth transition electrode 35 is connected to the third transition electrode 33 via a tenth via V10, and to the first end of the fourth active layer 14 via an eleventh via V11. The first end of the fourth active layer 14 is electrically connected to the second electrode plate 42 via the fifth transition electrode 35 and the third transition electrode 33. The sixth transition electrode 36 is connected to the second end of the fourth active layer 14 via a twelfth via V12, and is also configured to connect to the first electrode (anode) of a subsequently formed light-emitting device. The seventh transition electrode 37 is connected to the first end of the third active layer 13 via a thirteenth via V13, and is also configured to connect to the subsequently formed reference signal line REF.

[0137] In an exemplary embodiment, the fifth transition electrode 35, the sixth transition electrode 36, and the seventh transition electrode 37 can all be single-layer structures, such as copper or molybdenum; or, the fifth transition electrode 35, the sixth transition electrode 36, and the seventh transition electrode 37 can all be multi-layer structures, such as titanium / aluminum / titanium stacked structures.

[0138] At this point, the driving circuit layer of this embodiment is fabricated on the substrate. Subsequent fabrication processes may include forming a reference signal line REF and a light-emitting structure layer disposed on the side of the reference signal line REF away from the substrate, which will not be described in detail here. The light-emitting structure layer includes a light-emitting device, which comprises a first electrode, a light-emitting functional layer, and a second electrode sequentially disposed along the direction away from the substrate. The reference signal line REF can be connected to the seventh transition electrode 37 through a via, and the first electrode of the light-emitting structure layer can be connected to the sixth transition electrode 36 through a via.

[0139] The present disclosure shows the substrate fabrication process, in which the third electrode plate 43 and the first gate electrode 21 (first electrode plate) are electrically connected through the second transfer electrode 32, which simplifies the process and reduces production costs.

[0140] The present disclosure shows the substrate fabrication process, in which the second transfer electrode 32, the first power line VDD, and the data signal line DATA are formed using the same material and the same fabrication process, which simplifies the process and reduces production costs.

[0141] The present invention discloses a substrate fabrication process in which a third via V3 exposing the third electrode plate 43 and a fourth via V4 exposing the first gate 21 (first electrode plate) are formed using the same masking process. The second transfer electrode 32 is connected to the third electrode plate 43 through the third via V3 and to the first gate 21 (first electrode plate) through the fourth via V4, thereby achieving an electrical connection between the first gate 21 (first electrode plate) and the third electrode plate 43. This simplifies the process and reduces production costs.

[0142] The present disclosure discloses the substrate fabrication process, in which the first gate 21 (first electrode plate) and the third electrode plate 43 are electrically connected, so that the orthographic projections of the first gate 21 (first electrode plate) and the third electrode plate 43 on the substrate overlap with the orthographic projections of the second electrode plate 42 on the substrate, thereby increasing the capacitance and improving the storage performance of the capacitor.

[0143] The present disclosure shows the substrate fabrication process. By having the orthographic projection of the third active layer 13 on the substrate 101 overlap with the orthographic projection of the second active layer 12 on the substrate 101, the space utilization of the driving pixel circuit is improved, and the channel length of the second active layer 12 can be increased.

[0144] The present disclosure shows the substrate fabrication process. By having the orthographic projection of the fourth active layer 14 on the substrate 101 overlap with the orthographic projection of the first active layer 11 on the substrate 101, the space utilization of the driving pixel circuit is improved, and the channel length of the first active layer 11 can be increased.

[0145] In some embodiments of this disclosure, the display substrate further includes a second light-emitting signal line and a fifth transistor. The gate of the fifth transistor is connected to the second light-emitting signal line. The fifth transistor is disposed between the first power signal line and the first transistor. The first terminal of the fifth transistor is connected to the first power signal line, and the second terminal of the fifth transistor is connected to the first terminal of the first transistor. The fifth transistor is a second light-emitting control transistor. The fifth transistor includes a fifth active layer and a seventh gate. The fifth active layer is disposed in the same layer as the first active layer of the first transistor and is fabricated using the same material and the same fabrication process. The seventh gate is disposed in the same layer as the first gate of the first transistor and is fabricated using the same material and the same fabrication process. Further details are omitted here.

[0146] This disclosure also provides a method for preparing a display substrate to prepare the display substrate provided in the above embodiments.

[0147] In an exemplary embodiment, the method for fabricating a display substrate may include:

[0148] A driving circuit layer is formed on a substrate. The driving circuit layer includes at least a plurality of circuit units, at least one of which includes a pixel driving circuit. The pixel driving circuit includes a driving transistor, a capacitor, and a second transition electrode. The driving transistor includes a first active layer. The capacitor includes a first electrode plate disposed on the side of the first active layer away from the substrate, a second electrode plate disposed on the side of the first electrode plate away from the substrate, and a third electrode plate disposed on the side of the second electrode plate away from the substrate. The second transition electrode is disposed on the side of the third electrode plate away from the substrate. A third via is disposed between the second transition electrode and the third electrode plate. A fourth via is disposed between the second transition electrode and the first electrode plate. The second transition electrode is connected to the third electrode plate through the third via and to the first electrode plate through the fourth via.

[0149] This disclosure also provides a display device, which includes the aforementioned display substrate. The display device can be any product or component with display function, such as a virtual reality (VR) display device, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator, and the embodiments of the present invention are not limited thereto.

[0150] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit the invention. Any person skilled in the art may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope of this disclosure; however, the patent protection scope of this invention shall still be determined by the scope defined in the appended claims.

Claims

1. A display substrate, comprising a driving circuit layer disposed on a substrate, the driving circuit layer comprising at least a plurality of circuit units, at least one circuit unit comprising a pixel driving circuit, the pixel driving circuit comprising a driving transistor, a capacitor, and a second transition electrode, the driving transistor comprising a first active layer, the capacitor comprising a first electrode plate disposed on a side of the first active layer away from the substrate, a second electrode plate disposed on a side of the first electrode plate away from the substrate, and a third electrode plate disposed on a side of the second electrode plate away from the substrate, the second transition electrode being disposed on a side of the third electrode plate away from the substrate, a third via being disposed between the second transition electrode and the third electrode plate, a fourth via being disposed between the second transition electrode and the first electrode plate, the second transition electrode being connected to the third electrode plate through the third via, and the second transition electrode being connected to the first electrode plate through the fourth via.

2. The display substrate as claimed in claim 1, wherein, The driving transistor further includes a first gate, which is disposed on the side of the first active layer away from the substrate, and the first gate serves as the first plate of the capacitor.

3. The display substrate as described in claim 1, wherein, A fifth insulating layer is provided between the second transfer electrode and the third electrode plate. The third via extends through the fifth insulating layer from the surface of the fifth insulating layer away from the substrate, exposing the surface of the third electrode plate away from the substrate. A fifth insulating layer, a fourth insulating layer, and a third insulating layer are disposed between the second adapter electrode and the first electrode plate. The fifth insulating layer, the fourth insulating layer, and the third insulating layer are disposed sequentially along the direction close to the substrate. The fourth via extends from the surface of the fifth insulating layer away from the substrate, through the fifth insulating layer, the fourth insulating layer, and the third insulating layer in sequence, exposing the surface of the first electrode plate away from the substrate.

4. The display substrate as described in any one of claims 1 to 3, wherein, A second via is provided between the second electrode plate and the second end of the first active layer, and the second electrode plate is connected to the second end of the first active layer through the second via.

5. The display substrate as described in any one of claims 1 to 3, wherein, The pixel driving circuit further includes a first adapter electrode and a first power line. The first adapter electrode is disposed on the side of the first active layer away from the substrate, and the first power line is disposed on the side of the first adapter electrode away from the substrate. A first via is disposed between the first adapter electrode and a first end of the first active layer, and the first adapter electrode is connected to the first end of the first active layer through the first via. A fifth via is disposed between the first power line and the first adapter electrode, and the first power line is connected to the first adapter electrode through the fifth via.

6. The display substrate as claimed in claim 5, wherein, The first adapter electrode and the second electrode are located on the same film layer and use the same semiconductor material; the first power line and the second adapter electrode are located on the same film layer and use the same semiconductor material.

7. The display substrate as described in any one of claims 1 to 3, wherein, The first active layer is low-temperature polycrystalline silicon.

8. The display substrate as described in any one of claims 1 to 3, wherein, The pixel driving circuit further includes a first switching transistor, the first switching transistor including a second active layer and a second gate disposed on the side of the second active layer away from the substrate.

9. The display substrate as claimed in claim 8, wherein, The second active layer and the first active layer are located in the same film layer and use the same semiconductor material.

10. The display substrate as claimed in claim 8, wherein, The second gate and the first electrode are located in the same film layer and use the same semiconductor material.

11. The display substrate as claimed in claim 8, wherein, The pixel driving circuit further includes a data signal line, which is disposed on the side of the third electrode plate away from the substrate. A sixth via is provided between the data signal line and the first end of the second active layer, and the data signal line is connected to the first end of the second active layer through the sixth via.

12. The display substrate as claimed in claim 11, wherein, The pixel driving circuit further includes a fourth adapter electrode, which is disposed on the side of the data signal line away from the substrate. A ninth via is provided between the fourth adapter electrode and the second end of the second active layer. The fourth adapter electrode is connected to the second end of the second active layer through the ninth via. An eighth via is provided between the fourth adapter electrode and the third electrode plate. The fourth adapter electrode is connected to the third electrode plate through the eighth via.

13. The display substrate as described in any one of claims 1 to 3, wherein, The pixel driving circuit further includes a first light-emitting control transistor, which includes a fourth active layer. The fourth active layer is disposed on the side of the third electrode away from the substrate, and at least a portion of the orthographic projection of the fourth active layer on the substrate overlaps with the orthographic projection of the first active layer on the substrate.

14. The display substrate as claimed in claim 13, wherein, The pixel driving circuit further includes a third transition electrode and a fifth transition electrode. The third transition electrode is disposed between the third electrode plate and the fourth active layer. The fifth transition electrode is disposed on the side of the fourth active layer away from the substrate. A seventh via is disposed between the third transition electrode and the second electrode plate, and the third transition electrode is connected to the second electrode plate through the seventh via. A tenth via is disposed between the fifth transition electrode and the third transition electrode, and the fifth transition electrode is connected to the third transition electrode through the tenth via. An eleventh via is disposed between the fifth transition electrode and the first end of the fourth active layer, and the fifth transition electrode is connected to the first end of the fourth active layer through the eleventh via.

15. The display substrate as claimed in claim 13, wherein, The pixel driving circuit further includes a sixth adapter electrode and a light-emitting device. The sixth adapter electrode is disposed on the side of the fourth active layer away from the substrate, and the light-emitting device is disposed on the side of the sixth adapter electrode away from the substrate. A twelfth via is provided between the sixth adapter electrode and the second end of the fourth active layer. The sixth adapter electrode is connected to the second end of the fourth active layer through the twelfth via, and the light-emitting device is connected to the sixth adapter electrode.

16. The display substrate as claimed in claim 13, wherein, The pixel driving circuit further includes a second switching transistor, which includes a third active layer. The third active layer and the fourth active layer are connected as a single unit and contain the same material.

17. The display substrate as claimed in claim 16, wherein, The first light-emitting control transistor further includes a fifth gate and a sixth gate, wherein the fifth gate is disposed on the side of the fourth active layer near the substrate, and the sixth gate is disposed on the side of the fourth active layer away from the substrate; the second switching transistor further includes a third gate and a fourth gate, wherein the third gate is disposed on the side of the third active layer near the substrate, and the fourth gate is disposed on the side of the third active layer away from the substrate; the fifth gate and the third gate are located in the same film layer, and the sixth gate and the fourth gate are located in the same film layer.

18. The display substrate as claimed in claim 16, wherein, The pixel driving circuit further includes a seventh transition electrode and a reference signal line. The seventh transition electrode is disposed on the side of the third active layer away from the substrate, and the reference signal line is disposed on the side of the seventh transition electrode away from the substrate. A thirteenth via is disposed between the seventh transition electrode and the third active layer. The seventh transition electrode is connected to the first end of the third active layer through the thirteenth via, and the reference signal line is connected to the seventh transition electrode.

19. A display device comprising a display substrate as described in any one of claims 1 to 18.

20. A method for preparing a display substrate, comprising: A driving circuit layer is formed on a substrate. The driving circuit layer includes at least a plurality of circuit units, at least one of which includes a pixel driving circuit. The pixel driving circuit includes a driving transistor, a capacitor, and a second transition electrode. The driving transistor includes a first active layer. The capacitor includes a first electrode plate disposed on the side of the first active layer away from the substrate, a second electrode plate disposed on the side of the first electrode plate away from the substrate, and a electrode plate disposed on the side of the second electrode plate away from the substrate. The third electrode plate is located on one side of the substrate. The second adapter electrode is disposed on the side of the third electrode plate away from the substrate. A third through hole is provided between the second adapter electrode and the third electrode plate. A fourth through hole is provided between the second adapter electrode and the first electrode plate. The second adapter electrode is connected to the third electrode plate through the third through hole and to the first electrode plate through the fourth through hole.

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