Display substrate and display device

Abstract

A display substrate and a display device. The display substrate comprises: a plurality of pixel driving circuits and a plurality of first signal lines arranged on a substrate. At least one pixel driving circuit comprises: a plurality of transistors. A control electrode of at least one transistor in at least one pixel driving circuit is electrically connected to at least one signal line among the plurality of first signal lines. The pixel driving circuit further comprises: a capacitor. The capacitor comprises: a first electrode plate (C1). The plurality of transistors include: a driving transistor and a compensation transistor. A first electrode of the compensation transistor and the first electrode plate of the capacitor are separately electrically connected to the control electrode of the driving transistor. There is no overlapping area between the orthographic projection of at least one structure among the first electrode of the compensation transistor, the first electrode plate (C1) of the capacitor, and the control electrode of the driving transistor in at least one pixel driving circuit on the substrate and the orthographic projection of at least one signal line among the plurality of first signal lines on the substrate.

Description

Display substrate and display device Technical Field

[0001] This disclosure relates to, but is not limited to, the display field, and specifically to a display substrate and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field.

[0003] Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0005] This disclosure provides a display substrate and a display device.

[0006] In a first aspect, this disclosure provides a display substrate, including: a substrate and a plurality of pixel driving circuits and a plurality of first signal lines disposed on the substrate, wherein at least one pixel driving circuit includes: a plurality of transistors, and at least one transistor includes: a control electrode, a first electrode and a second electrode, wherein the control electrode of at least one transistor in at least one pixel driving circuit is electrically connected to at least one of the plurality of first signal lines.

[0007] The pixel driving circuit further includes a capacitor, the capacitor including a first electrode plate, and the plurality of transistors including a driving transistor and a compensation transistor, wherein the first electrode of the compensation transistor and the first electrode plate of the capacitor are respectively electrically connected to the control electrode of the driving transistor.

[0008] The orthographic projection of at least one of the structures of the first electrode of the compensation transistor, the first plate of the capacitor, and the control electrode of the driving transistor in at least one pixel driving circuit onto the substrate does not overlap with the orthographic projection of at least one of the plurality of first signal lines onto the substrate.

[0009] In an exemplary embodiment, the plurality of transistors further includes: a first initial transistor, the first signal line including: a first scan signal line, the control electrode of the first initial transistor in at least one pixel driving circuit being electrically connected to at least one of the plurality of first scan signal lines, the first scan signal line extending at least partially along a first direction;

[0010] For at least one pixel driving circuit, the orthographic projection of at least one of the structures of the first electrode of the compensation transistor, the first plate of the capacitor, and the control electrode of the driving transistor on the substrate does not overlap with the orthographic projection of the first scan signal line connected to the pixel driving circuit on the substrate.

[0011] In an exemplary embodiment, the compensation transistor is an N-type transistor, and the first signal line includes a second scan signal line. The control electrode of the compensation transistor in at least one pixel driving circuit is electrically connected to at least one of the multiple second scan signal lines, and the second scan signal line extends at least partially along a first direction.

[0012] For at least one pixel driving circuit, the orthographic projection of at least one of the structures of the first electrode of the compensation transistor, the first plate of the capacitor, and the control electrode of the driving transistor on the substrate does not overlap with the orthographic projection of the second scan signal line connected to the pixel driving circuit on the substrate.

[0013] In an exemplary embodiment, the second scan signal line includes: a first scan line and a second scan line that are interconnected; at least one of the first scan line and the second scan line extends at least partially along a first direction;

[0014] For at least one second scan signal line, the orthographic projection of the first scan line on the substrate at least partially overlaps with the orthographic projection of the second scan line on the substrate, and the orthographic projection of at least one of the first scan line and the second scan line on the substrate is located on the side of the first scan signal line away from the substrate.

[0015] In an exemplary embodiment, for at least one pixel driving circuit, the second scan signal line connected to the pixel driving circuit is located between the orthographic projection of at least one of the structures of the first electrode of the compensation transistor, the first plate of the capacitor, and the control electrode of the driving transistor on the substrate and the orthographic projection of the first scan signal line connected to the pixel driving circuit on the substrate.

[0016] In an exemplary embodiment, the second terminal of the driving transistor is electrically connected to the second terminal of the first initial transistor and the second terminal of the compensation transistor, respectively;

[0017] For at least one pixel driving circuit, the orthographic projection of at least one of the structures of the second pole of the driving transistor, the second pole of the first initial transistor, and the second pole of the compensation transistor on the substrate at least partially overlaps with the orthographic projection of at least one of the first scan signal lines and the second scan signal lines connected to the pixel driving circuit on the substrate.

[0018] In an exemplary embodiment, the first signal line further includes: a first reset signal line, wherein the control electrode of the first initial transistor of at least one pixel driving circuit is electrically connected to at least one of the plurality of first reset signal lines, and the first reset signal line extends at least partially along a first direction;

[0019] For at least one pixel driving circuit, the orthographic projection of at least one of the structures of the first electrode of the compensation transistor, the first plate of the capacitor, and the control electrode of the driving transistor on the substrate does not overlap with the orthographic projection of the first reset signal line connected to the pixel driving circuit on the substrate, and the orthographic projection of the first reset signal line connected to the pixel driving circuit on the substrate is located on the side of the first scan signal line connected to the pixel driving circuit that is far away from the second scan signal line connected to the pixel driving circuit.

[0020] In an exemplary embodiment, the system further includes: a plurality of light-emitting devices disposed on a substrate; at least one pixel driving circuit electrically connected to at least one light-emitting device; the at least one light-emitting device includes: a first electrode; the first signal line further includes: a second reset signal line; the plurality of transistors further includes: a second initial transistor and a third initial transistor; for at least one pixel driving circuit, the control electrode of at least one of the second initial transistors and the third initial transistor is electrically connected to at least one of the plurality of second reset signal lines; the second electrode of the second initial transistor is electrically connected to the first electrode of the light-emitting device connected to the pixel driving circuit; the second electrode of the third initial transistor is electrically connected to the first electrode of the driving transistor; and the second reset signal line extends at least partially along a first direction.

[0021] For at least one pixel driving circuit, the orthographic projection of at least one of the structures of the first electrode of the compensation transistor, the first plate of the capacitor, and the control electrode of the driving transistor on the substrate does not overlap with the orthographic projection of the second reset signal line connected to the pixel driving circuit on the substrate, and the orthographic projection of the second reset signal line connected to the pixel driving circuit on the substrate is located on the side of at least one of the structures of the first electrode of the compensation transistor, the first plate of the capacitor, and the control electrode of the driving transistor in the pixel driving circuit that is away from the second scan signal line connected to the pixel driving circuit.

[0022] In an exemplary embodiment, the first signal line further includes: a light-emitting signal line, and at least one pixel driving circuit includes: a first light-emitting transistor and a second light-emitting transistor, wherein the control electrode of at least one of the first light-emitting transistor and the second light-emitting transistor is electrically connected to the light-emitting signal line, the second electrode of the first light-emitting transistor is electrically connected to the first electrode of the driving transistor, the first electrode of the second light-emitting transistor is electrically connected to the second electrode of the driving transistor, and the light-emitting signal line extends along a first direction;

[0023] For at least one pixel driving circuit, the orthographic projection of at least one of the structures of the first electrode of the compensation transistor, the first plate of the capacitor, and the control electrode of the driving transistor on the substrate does not overlap with the orthographic projection of the light-emitting signal line connected to the pixel driving circuit on the substrate, and the light-emitting signal line connected to the pixel driving circuit is located between the orthographic projection of at least one of the structures of the first electrode of the compensation transistor, the first plate of the capacitor, and the control electrode of the driving transistor in the pixel driving circuit and the second reset signal line connected to the pixel driving circuit on the substrate.

[0024] In an exemplary embodiment, the first signal line further includes: a first initial signal line, wherein the first electrode of the first initial transistor in at least one pixel driving circuit is electrically connected to at least one of the plurality of first initial signal lines, and the first initial signal line extends along a first direction;

[0025] For at least one pixel driving circuit, the orthographic projection of at least one of the structures of the first electrode of the compensation transistor, the first plate of the capacitor, and the control electrode of the driving transistor on the substrate does not overlap with the orthographic projection of the first initial signal line connected to the pixel driving circuit on the substrate, and the orthographic projection of the first initial signal line connected to the pixel driving circuit on the substrate is located on the side of the first scan signal line connected to the pixel driving circuit that is far away from the second scan signal line connected to the pixel driving circuit.

[0026] In an exemplary embodiment, the first signal line further includes: a second initial signal line, wherein the first electrode of the second initial transistor in at least one pixel driving circuit is electrically connected to at least one of the plurality of second initial signal lines, and the second initial signal line extends along a first direction;

[0027] For at least one pixel driving circuit, the orthographic projection of at least one of the structures of the first electrode of the compensation transistor, the first plate of the capacitor, and the control electrode of the driving transistor on the substrate does not overlap with the orthographic projection of the second initial signal line connected to the pixel driving circuit on the substrate, and the orthographic projection of the second initial signal line connected to the pixel driving circuit on the substrate is located on the side of the second reset signal line connected to the pixel driving circuit that is far away from the first scan signal line connected to the pixel driving circuit.

[0028] In an exemplary embodiment, for at least one pixel driving circuit, the orthographic projection of the second initial signal line connected to the pixel driving circuit on the substrate at least partially overlaps with the orthographic projection of at least one of the first reset signal line and the first initial signal line connected to the next row of pixel driving circuits on the substrate.

[0029] In an exemplary embodiment, the first signal line further includes: a third initial signal line, wherein the first electrode of a third initial transistor in at least one pixel driving circuit is electrically connected to at least one of a plurality of third initial signal lines, and the third initial signal line extends along a first direction;

[0030] For at least one pixel driving circuit, the orthographic projection of at least one of the structures of the first electrode of the compensation transistor, the first plate of the capacitor, and the control electrode of the driving transistor on the substrate does not overlap with the orthographic projection of the third initial signal line connected to the pixel driving circuit on the substrate, and the orthographic projection of the third initial signal line connected to the pixel driving circuit on the substrate at least partially overlaps with the orthographic projection of the second reset signal line connected to the pixel driving circuit on the substrate.

[0031] In an exemplary embodiment, the third initial signal line connected to the pixel driving circuit and the light emission signal line connected to the pixel driving circuit do not overlap in their orthogonal projections on the substrate.

[0032] In an exemplary embodiment, the circuit structures of at least two adjacent pixel driving circuits located in the same row are symmetrically arranged to intersect with respect to a virtual straight line extending along a second direction.

[0033] In an exemplary embodiment, the first signal line includes: a first scan signal line, a second scan signal line, a first reset signal line, a second reset signal line, a first initial signal line, a second initial signal line, and a third initial signal line; the second reset signal line includes: a first scan line and a second scan line; the plurality of transistors includes: at least one P-type transistor and at least one N-type transistor; at least one of the plurality of transistors further includes: an active pattern; the capacitor further includes: a second electrode plate; the display substrate further includes: a circuit structure layer; the circuit structure layer includes: a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, and a fourth conductive layer sequentially stacked on the substrate;

[0034] The first semiconductor layer includes: an active pattern of at least one P-type transistor located in at least one pixel driving circuit;

[0035] The first conductive layer includes: a first scan signal line, a light emission signal line, a first reset signal line, a second reset signal line, and a control electrode of at least one P-type transistor located in at least one pixel driving circuit and a first electrode of a capacitor;

[0036] The second conductive layer includes: a first scan line of at least one of the second scan signal lines, a first initial signal line, and a second plate of a capacitor located in at least one pixel driving circuit;

[0037] The second semiconductor layer includes: an active pattern of at least one P-type transistor located in at least one pixel driving circuit;

[0038] The third conductive layer includes: a second scan line, a second initial signal line, and a third initial signal line, all of which are second scan signal lines;

[0039] The fourth conductive layer includes: a first electrode and a second electrode of at least one transistor located in at least one pixel driving circuit.

[0040] Secondly, this disclosure also provides a display device, including: the aforementioned display substrate.

[0041] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood.

[0042] Overview of the attached figures

[0043] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0044] Figure 1 is a schematic diagram of a display device;

[0045] Figure 2A is a schematic diagram of a planar structure of a display substrate;

[0046] Figure 2B is a schematic diagram of a planar structure of a display substrate;

[0047] Figure 2C is a schematic diagram of a planar structure of a display substrate;

[0048] Figure 3A is a schematic diagram of the equivalent circuit of the pixel driving circuit;

[0049] Figure 3B is a schematic diagram of the equivalent circuit of the pixel driving circuit.

[0050] Figure 4 is a timing diagram of the pixel driving circuit in Figure 3A;

[0051] Figure 5 is a top view of the display substrate provided in an embodiment of this disclosure;

[0052] Figure 6 is a schematic diagram of the pattern of the first semiconductor layer in Figure 5;

[0053] Figure 7 is a schematic diagram of the pattern of the first conductive layer in Figure 5;

[0054] Figure 8 is a schematic diagram after the first conductive layer pattern in Figure 5 is formed;

[0055] Figure 9 is a schematic diagram of the second conductive layer pattern in Figure 5;

[0056] Figure 10 is a schematic diagram after the second conductive layer pattern is formed in Figure 5;

[0057] Figure 11 is a schematic diagram of the pattern of the second semiconductor layer in Figure 5;

[0058] Figure 12 is a schematic diagram after the second semiconductor layer pattern is formed in Figure 5;

[0059] Figure 13 is a schematic diagram of the third conductive layer pattern in Figure 5;

[0060] Figure 14 is a schematic diagram after the formation of the third conductive layer pattern in Figure 5;

[0061] Figure 15 is a schematic diagram after the fifth insulating layer pattern is formed in Figure 5;

[0062] Figure 16 is a schematic diagram of the fourth conductive layer pattern in Figure 5;

[0063] Figure 17 is a schematic diagram of the fourth conductive layer pattern formed in Figure 5.

[0064] Detailed Explanation

[0065] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components have been omitted. The accompanying drawings of the embodiments of this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to with reference to general designs.

[0066] The scale of the figures in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The figures described in this disclosure are only schematic diagrams of the structure, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0067] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0068] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0069] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0070] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0071] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0072] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0073] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0074] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0075] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures through the same patterning process, and their materials may be the same or different. For example, the precursors forming multiple structures in a same-layer arrangement may be made of the same material, while the final materials may be the same or different.

[0076] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0077] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0078] Figure 1 is a schematic diagram of a display device. As shown in Figure 1, the display device may include a display substrate, which may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is connected to the data driver, the scan driver, and the light-emitting driver.

[0079] In an exemplary embodiment, the data driver is connected to multiple data signal lines (D1 to Dn), the scan driver is connected to multiple scan signal lines (S1 to Sm), and the light-emitting driver is connected to multiple light-emitting signal lines (E1 to Eo). The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting device connected to the circuit unit. The circuit unit may include a pixel driving circuit, which may be connected to the scan signal lines, light-emitting signal lines, and data signal lines, respectively.

[0080] In an exemplary embodiment, the timing controller can provide grayscale values ​​and control signals of specifications suitable for the data driver to the data driver, provide clock signals, scan start signals, etc. of specifications suitable for the scan driver to the scan driver, and provide clock signals, transmit stop signals, etc. of specifications suitable for the light-emitting driver to the light-emitting driver.

[0081] In an exemplary embodiment, the data driver may use grayscale values ​​and control signals received from a timing controller to generate data voltages that will be provided to data signal lines D1, D2, D3, ..., Dn. For example, the data driver may use a clock signal to sample grayscale values ​​and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn on a pixel-row basis, where n can be a natural number.

[0082] In an exemplary embodiment, the scan driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ..., Sm by receiving a clock signal, a scan start signal, etc., from a timing controller. For example, the scan driver can sequentially provide scan signals with on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can generate scan signals by sequentially transmitting the scan start signal, provided in the form of on-level pulses, to the next stage circuit under the control of a clock signal, where m can be a natural number.

[0083] In an exemplary embodiment, the LED driver can generate transmit signals to be provided to LED signal lines E1, E2, E3, ..., Eo by receiving clock signals, transmit stop signals, etc., from a timing controller. For example, the LED driver can sequentially provide transmit signals with cutoff level pulses to LED signal lines E1 through Eo. For example, the LED driver can be configured as a shift register and can generate transmit signals by sequentially transmitting transmit stop signals in the form of cutoff level pulses to the next stage circuit under the control of a clock signal, where o can be a natural number.

[0084] Figure 2A is a schematic diagram of a planar structure of a display substrate (Figure 1), Figure 2B is a schematic diagram of a planar structure of a display substrate (Figure 22), and Figure 2C is a schematic diagram of a planar structure of a display substrate (Figure 23). As shown in Figures 2A to 2C, the display substrate may include multiple pixel units P arranged in a matrix. At least one of the multiple pixel units P includes a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. Each of the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 includes a pixel driving circuit and a light-emitting device. The pixel driving circuits in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are respectively connected to a scan signal line, a data signal line, and a light-emitting signal line. The pixel driving circuits are configured to receive the data voltage transmitted by the data signal line and output a corresponding current to the light-emitting device under the control of the scan signal line and the light-emitting signal line. The light-emitting devices in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are respectively connected to the pixel driving circuit of their respective sub-pixels. The light-emitting devices are configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of their respective sub-pixels.

[0085] In an exemplary embodiment, the first sub-pixel P1 may be a red sub-pixel (R) that emits red light, the second sub-pixel P2 may be a blue sub-pixel (B) that emits blue light, and the third sub-pixel P3 may be a green sub-pixel (G) that emits green light.

[0086] In an exemplary embodiment, the shape of the sub-pixel can be rectangular, rhomboid, pentagonal or hexagonal, and the three sub-pixels can be arranged horizontally side by side, vertically side by side or in a triangular pattern, which is not limited in this disclosure.

[0087] In an exemplary embodiment, a pixel unit may include three sub-pixels. The three sub-pixels may be arranged horizontally side by side, vertically side by side, or in a triangular arrangement, etc., and this disclosure does not limit the arrangement. Figure 2A illustrates an example of three sub-pixels arranged horizontally side by side. Figure 2B illustrates an example of three sub-pixels arranged in a triangular arrangement.

[0088] In other exemplary embodiments, a pixel unit may include four sub-pixels, which may be arranged horizontally side-by-side, vertically side-by-side, or in a square, etc., and this disclosure does not limit the arrangement. Figure 2C is illustrated using an example of four sub-pixels arranged in a square.

[0089] In an exemplary embodiment, the pixel driving circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. Here, T refers to a transistor in the pixel driving circuit, C refers to a capacitor in the pixel driving circuit, the number before T refers to the number of transistors in the pixel driving circuit, and the number before C refers to the number of capacitors in the pixel driving circuit.

[0090] Figure 3A is a schematic diagram of the equivalent circuit of the pixel driving circuit, and Figure 3B is a schematic diagram of the equivalent circuit of the pixel driving circuit. As shown in Figures 3A and 3B, the pixel driving circuit may include 8 transistors (first transistor T1 to eighth transistor T8), 1 capacitor C, and the pixel driving circuit may be connected to 10 signal lines (data signal line Data, first scan signal line Gate1, second scan signal line Gate2, first reset signal line Reset1, second reset signal line Reset2, light emission signal line EM, first initial signal line INIT1, second initial signal line INIT2, third initial signal line INIT3, and first power supply line VDD).

[0091] In an exemplary embodiment, the first end of capacitor C is connected to the first power line VDD, and the second end of capacitor C is connected to the first node N1, that is, the second end of capacitor C is connected to the control electrode of the third transistor T3.

[0092] In an exemplary embodiment, the control electrode of the first transistor T1 is connected to the first reset signal line Reset1, the first electrode of the first transistor T1 is connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is connected to either the first node N1 or the third node N3. Figure 3A illustrates the example of the second electrode of the first transistor T1 being connected to the third node N3, and Figure 3B illustrates the example of the second electrode of the first transistor T1 being connected to the first node N1. The first transistor T1 can be referred to as the first initial transistor. When a conduction level scan signal is applied to the first reset signal line Reset1, the first transistor T1 transmits the initial signal of the first initial signal line INIT1 to the first node N1 or the third node N3 to initialize the charge of the first node N1 or the third node N3.

[0093] In an exemplary embodiment, the control electrode of the second transistor T2 is connected to the second scan signal line Gate2, the first electrode of the second transistor T2 is connected to the first node N1, and the second electrode of the second transistor T2 is connected to the third node N3. The second transistor T2 can be referred to as a compensation transistor. When a conduction-level scan signal is applied to the second scan signal line Gate2, the second transistor T2 causes the control electrode of the third transistor T3 to connect to its second electrode.

[0094] In an exemplary embodiment, the control electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be referred to as a driving transistor, and the third transistor T3 determines the magnitude of the driving current flowing between the first power line VDD and the second power line VSS based on the potential difference between its control electrode and its first electrode.

[0095] In an exemplary embodiment, the control electrode of the fourth transistor T4 is connected to the first scan signal line Gate1, the first electrode of the fourth transistor T4 is connected to the data signal line Data, and the second electrode of the fourth transistor T4 is connected to the second node N2. The fourth transistor T4 can be referred to as a switching transistor, a write transistor, etc. When a conduction-level scan signal is applied to the first scan signal line Gate1, the fourth transistor T4 causes the data voltage of the data signal line Data to be input to the pixel driving circuit.

[0096] In an exemplary embodiment, the control electrode of the fifth transistor T5 is connected to the light-emitting signal line EM, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the second node N2. The control electrode of the sixth transistor T6 is connected to the light-emitting signal line EM, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the fourth node N4 (which is also the first electrode of the light-emitting device L). The fifth transistor T5 and the sixth transistor T6 can be referred to as light-emitting transistors. When a conduction-level light-emitting signal is applied to the light-emitting signal line EM, the fifth transistor T5 and the sixth transistor T6 cause the light-emitting device to emit light by forming a drive current path between the first power supply line VDD and the second power supply line VSS.

[0097] In an exemplary embodiment, the control electrode of the seventh transistor T7 is connected to the second reset signal line Reset2, the first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is connected to the fourth node N4. The seventh transistor T7 can be referred to as the second initial transistor. When a conduction level scan signal is applied to the second reset signal line Reset2, the seventh transistor T7 transmits the initial signal of the second initial signal line INIT2 to the fourth node N4 (which is also the first electrode of the light-emitting device L), so as to initialize or release the accumulated charge in the first electrode of the light-emitting device.

[0098] In an exemplary embodiment, the control electrode of the eighth transistor T8 is connected to the second reset signal line Reset2, the first electrode of the eighth transistor T8 is connected to the third initial signal line INIT3, and the second electrode of the eighth transistor T8 is connected to the second node N2. The eighth transistor T8 can be referred to as the third initial transistor. When a conduction level scan signal is applied to the second reset signal line Reset2, the eighth transistor T8 transmits the initial signal of the third initial signal line INIT3 to the second node N2, biasing the third transistor T3.

[0099] In an exemplary embodiment, the light-emitting device L may include a current-driven device, such as a current-driven light-emitting diode, like a micro light-emitting diode (Micro LED), a mini light-emitting diode (Mini LED), an organic light-emitting diode (OLED), or a quantum light-emitting diode (QLED). The typical size (e.g., length) of a Micro LED can be less than 100 μm, for example, 10 μm to 50 μm. The typical size (e.g., length) of a Mini LED can be approximately 100 μm to 300 μm, for example, 120 μm to 260 μm.

[0100] In an exemplary embodiment, the organic light-emitting layer may include stacked hole injection layer (HIL), hole transport layer (HTL), electron block layer (EBL), emitting layer (EML), hole block layer (HBL), electron transport layer (ETL), and electron injection layer (EIL). In this exemplary embodiment, the hole injection layers of all sub-pixels may be a common layer connected together, the electron injection layers of all sub-pixels may be a common layer connected together, the hole transport layers of all sub-pixels may be a common layer connected together, the hole block layers of all sub-pixels may be a common layer connected together, and the emitting layers of adjacent sub-pixels may have a small overlap or may be isolated. Similarly, the electron block layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0101] In an exemplary embodiment, the light-emitting device L may include a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode). Exemplarily, the first electrode of the light-emitting device is electrically connected to a fourth node N4 in a pixel driving circuit, and the second electrode of the light-emitting device is electrically connected to a second power line VSS.

[0102] In an exemplary embodiment, the voltage value of at least one of the first initial signal line INIT1, the second initial signal line INIT2, and the third initial signal line INIT3 is constant, and it is a DC signal. In an exemplary embodiment, the DC signal can be one in which neither the magnitude nor the direction of the signal changes with time.

[0103] In an exemplary embodiment, the first power line VDD continuously provides a high-level signal, and the second power line VSS continuously provides a low-level signal.

[0104] Based on their characteristics, transistors can be classified into N-type transistors and P-type transistors. When a transistor is P-type, its turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage), and its turn-off voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage). When a transistor is N-type, its turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage), and its turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage).

[0105] In an exemplary embodiment, the N-type transistor can be an oxide thin-film transistor, the active layer of which is made of oxide semiconductor. Oxide thin-film transistors have advantages such as low leakage current.

[0106] In an exemplary embodiment, the P-type transistor can be a low-temperature polycrystalline silicon (LTPS) thin-film transistor. The active layer of the LTPS thin-film transistor is made of low-temperature polycrystalline silicon, which has advantages such as high mobility and fast charging.

[0107] In an exemplary embodiment, the first transistor T1 to the eighth transistor T8 can be either P-type transistors or N-type transistors. Using the same type of transistor in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first transistor T1 to the eighth transistor T8 may include both P-type and N-type transistors.

[0108] In an exemplary embodiment, in the pixel driving circuit provided in FIG3A, the second transistor T2 can be an N-type transistor, and the first transistor T1, the third transistor T3 to the eighth transistor T8 can be P-type transistors. The fact that the second transistor T2 is an N-type transistor can reduce the leakage current of the first node N1 and ensure the stability of the signal at the first node N1.

[0109] In an exemplary embodiment, in the pixel driving circuit provided in FIG3B, the first transistor T1 and the second transistor T2 can be N-type transistors, and the third transistor T3 to the eighth transistor T8 can be P-type transistors. The fact that the first transistor T1 and the second transistor T2 are N-type transistors can reduce the leakage current of the first node N1 and ensure the stability of the signal at the first node N1.

[0110] In an exemplary embodiment, the second transistor T2 in this disclosure can be an N-type transistor, and the first transistor T1, the third transistor T3 to the eighth transistor T8 can be P-type transistors. Integrating low-temperature polycrystalline silicon thin-film transistors and oxide thin-film transistors on a single display substrate forms a low-temperature polycrystalline oxide (LTPO) display substrate. This allows for the utilization of the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0111] Figure 4 is a timing diagram of the pixel driving circuit provided in Figure 3A. The following describes an exemplary embodiment of this disclosure through the operation of the pixel driving circuit exemplified in Figure 3A. The pixel driving circuit in Figure 3A includes eight transistors (first transistor T1 to eighth transistor T8) and one capacitor (capacitor C). The first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are P-type transistors, and the second transistor T2 is an N-type transistor.

[0112] In an exemplary embodiment, the operation of the pixel driving circuit may include:

[0113] In the first stage, P1, also known as the initialization stage, the signals of the first scan signal line Gate1, the second scan signal line Gate2, the first reset signal line Reset1, and the light emission signal line EM are high-level signals, while the signal of the second reset signal line Reset2 is low-level. The second transistor T2, the seventh transistor T7, and the eighth transistor T8 are turned on, while the first transistor T1, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are turned off.

[0114] When the second transistor T2 is turned on, the first node N1 and the third node N3 are also turned on. The seventh transistor T7 is also turned on. The initial signal of the second initial signal line INIT2 is written to the fourth node N4 (which is also the anode of the light-emitting device L) through the turned-on seventh transistor T7, initializing (resetting) the fourth node N4 (also the anode of the light-emitting device L) and clearing its internal pre-stored voltage, thus completing the initialization. When the eighth transistor T8 is turned on, the initial signal of the third initial signal line INIT3 is written to the second node N2, initializing (resetting) the second node N2 and clearing its internal pre-stored voltage, thus completing the initialization.

[0115] In the second stage P2, the signals of the first scan signal line Gate1, the second scan signal line Gate2, the second reset signal line Reset2, and the light emission signal line EM are high-level signals, while the signal of the first reset signal line Reset1 is low-level. The first transistor T1 and the second transistor T2 are turned on, while the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0116] When the first transistor T1 is turned on, the signal of the first initial signal line INIT1 is written to the third node N3, clearing the pre-stored voltage inside and initializing the third node N3. When the second transistor T2 is turned on, the signal of the third node N3 is written to the first node N1, clearing the pre-stored voltage inside and initializing the first node N1.

[0117] In the third stage (P3), the threshold compensation and data writing stage, the signals of the second scan signal line Gate2, the first reset signal line Reset1, the second reset signal line Reset2, and the light emission signal line EM are high-level signals, while the signal of the first scan signal line Gate1 is low-level. The data signal line Data outputs the data signal. The second transistor T2 and the fourth transistor T4 are turned on, while the first transistor T1, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0118] The second transistor T2 and the fourth transistor T4 are turned on. The data signal on the data signal line Data charges the first node N1 through the turned-on fourth transistor T4, the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2 until the voltage value of the signal at the first node N1 is Vdata + Vth, where Vdata is the voltage value of the data signal and Vth is the threshold voltage of the third transistor T3.

[0119] In the fourth stage, P4, the bias stage, the signals of the first scan signal line Gate1, the first reset signal line Reset1, and the light emission signal line EM are high-level signals, while the signals of the second scan signal line Gate2 and the second reset signal line Reset2 are low-level signals. The seventh transistor T7 and the eighth transistor T8 are turned on, while the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are turned off.

[0120] When the seventh transistor T7 is turned on, the initial signal of the second initial signal line INIT2 is written to the fourth node N4 (which is also the anode of the light-emitting device L) through the turned-on seventh transistor T7, re-initializing (resetting) the fourth node N4 (which is also the anode of the light-emitting device L), clearing its internal pre-stored voltage, and completing the initialization. When the eighth transistor T8 is turned on, the initial signal of the third initial signal line INIT3 is written to the second node N2, causing the third transistor T3 to be in a bias state.

[0121] In the fifth stage (P5), the light-emitting stage, the signals of the first scan signal line Gate1, the first reset signal line Reset1, and the second reset signal line Reset2 are high-level signals, while the signals of the second scan signal line Gate2 and the light-emitting signal line EM are low-level signals. The fifth transistor T5 and the sixth transistor T6 are turned on, while the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off.

[0122] The fifth transistor T5 and the sixth transistor T6 are turned on. The power signal output from the first power line VDD provides a driving voltage to the fourth node N4 (which is also the first electrode of the light-emitting device L) through the turned-on fifth transistor T5, the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on sixth transistor T6, driving the light-emitting device L to emit light. During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (the driving transistor) is determined by the voltage difference between its gate electrode and its first electrode. Since the voltage of the first node N1 is Vdata + Vth, and the voltage value of the signal at the second node N2 is Vdd, where Vdd is the voltage value of the signal from the first power line, the driving current of the third transistor T3 is:

[0123] I = K * (Vgs - Vth) 2 =K*(Vdata+Vth-Vdd-Vth) 2 =K*(Vdata-Vdd) 2

[0124] Where I is the driving current flowing through the third transistor T3, which is the driving current driving the light-emitting device L, K is a constant, and Vgs is the voltage difference between the control electrode and the first electrode of the third transistor T3.

[0125] As can be seen from the derivation of the above current formula, during the light-emitting stage, the driving current of the third transistor T3 is no longer affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current. This ensures uniform display brightness of the display product and improves the overall display effect of the display product.

[0126] The operation of the pixel driving circuit in Figure 3B is similar to that in Figure 3A, and will not be described again here.

[0127] The structural layout of a pixel driving circuit in a display substrate causes signal instability in some structures of the pixel driving circuit, thereby affecting the display effect of the display substrate.

[0128] Therefore, this disclosure provides a display substrate.

[0129] Figure 5 is a top view of a display substrate provided in an embodiment of this disclosure. As shown in Figure 5, the display substrate provided in this embodiment includes: a substrate and a plurality of pixel driving circuits P and a plurality of first signal lines disposed on the substrate. The control electrode of at least one transistor in at least one pixel driving circuit is electrically connected to at least one of the plurality of first signal lines. At least one pixel driving circuit includes: a plurality of transistors and a capacitor, and at least one transistor includes: an active pattern. The control electrode, the first electrode, and the second electrode are included, and the capacitor includes: a first electrode plate C1 and a second electrode plate. The pixel driving circuit can be the pixel driving circuit provided in Figure 3A. Figure 5 illustrates two pixel driving circuits in the m-th row of pixel driving circuits as an example. Wherein, Gate1(m) refers to the first scan signal line connected to the m-th row pixel driving circuit, Gate2(m) refers to the second scan signal line connected to the m-th row pixel driving circuit, Reset1(m) refers to the first reset signal line connected to the m-th row pixel driving circuit, Reset2(m) refers to the second reset signal line connected to the m-th row pixel driving circuit, INIT1(m) refers to the first initial signal line connected to the m-th row pixel driving circuit, INIT2(m) refers to the second initial signal line connected to the m-th row pixel driving circuit, and INI3(m) refers to the third initial signal line connected to the m-th row pixel driving circuit.

[0130] In an exemplary embodiment, the plurality of transistors includes a driving transistor (also the third transistor T3) and a compensation transistor. The first electrode 23 of the compensation transistor (also the second transistor T2) and the first plate C1 of the capacitor are electrically connected to the control electrode 32 of the driving transistor. The orthographic projection of at least one structure of the first electrode 23 of the compensation transistor, the first plate C1 of the capacitor, and the control electrode 32 of the driving transistor in at least one pixel driving circuit onto the substrate does not overlap with the orthographic projection of at least one of the plurality of first signal lines onto the substrate. The first plate C1 of the capacitor and the control electrode 32 of the driving transistor in at least one pixel driving circuit can be an integral structure.

[0131] In this disclosure, at least one of the structures of the first electrode of the compensation transistor, the first plate of the capacitor, and the control electrode of the driving transistor in at least one pixel driving circuit represents a first node in the pixel driving circuit. The fact that the orthographic projection of at least one of the structures of the first electrode of the compensation transistor, the first plate of the capacitor, and the control electrode of the driving transistor in at least one pixel driving circuit onto the substrate does not overlap with the orthographic projection of at least one of the multiple first signal lines onto the substrate means that the first node in the pixel driving circuit does not overlap with at least one of the multiple first signal lines. This can avoid the instability of the signal of the first node in the pixel driving circuit, avoid interference from the signal of at least one of the multiple first signal lines, improve the reliability of the pixel driving circuit, and improve the display effect of the display substrate.

[0132] In an exemplary embodiment, as shown in FIG5, the first signal line includes: a first scan signal line Gate1, the control electrode of a first initial transistor in at least one pixel driving circuit is electrically connected to at least one of the plurality of first scan signal lines Gate1, and the first scan signal line Gate1 extends at least partially along a first direction D1.

[0133] As shown in Figure 5, for at least one pixel driving circuit, the orthographic projection of at least one of the structures of the first electrode 23 of the compensation transistor, the first plate C1 of the capacitor, and the control electrode 32 of the driving transistor on the substrate does not overlap with the orthographic projection of the first scan signal line Gate1 connected to the pixel driving circuit on the substrate. For example, the orthographic projection of at least one of the structures of the first electrode 23 of the compensation transistor, the first plate C1 of the capacitor, and the control electrode 32 of the driving transistor in the m-th row pixel driving circuit on the substrate does not overlap with the orthographic projection of the first scan signal line Gate1(m) connected to the m-th row pixel driving circuit on the substrate.

[0134] In an exemplary embodiment, as shown in FIG5, the first signal line includes: a second scan signal line Gate2, wherein the control electrode of the compensation transistor in at least one pixel driving circuit is electrically connected to at least one of the multiple second scan signal lines Gate2, and the second scan signal line Gate2 extends at least partially along the first direction D1.

[0135] As shown in Figure 5, for at least one pixel driving circuit, the orthographic projection of at least one of the structures of the first electrode 23 of the compensation transistor, the first plate C1 of the capacitor, and the control electrode 32 of the driving transistor on the substrate does not overlap with the orthographic projection of the second scan signal line Gate2 connected to the pixel driving circuit on the substrate. For example, the orthographic projection of at least one of the structures of the first electrode 23 of the compensation transistor, the first plate C1 of the capacitor, and the control electrode 32 of the driving transistor in the m-th row pixel driving circuit on the substrate does not overlap with the orthographic projection of the second scan signal line Gate2(m) connected to the m-th row pixel driving circuit on the substrate.

[0136] In an exemplary embodiment, as shown in FIG5, the second scan signal line Gate2 includes: a first scan line Gate2A and a second scan line Gate2B connected to each other; at least one of the first scan line Gate2A and the second scan line Gate2B extends at least partially along a first direction D1.

[0137] In an exemplary embodiment, as shown in FIG5, for at least one second scan signal line Gate2, the orthographic projection of the first scan line Gate2A on the substrate and the orthographic projection of the second scan line Gate2B on the substrate at least partially overlap, and the orthographic projection of at least one of the first scan line Gate2A and the second scan line Gate2B in the at least one second scan signal line Gate2 on the substrate is located on the side of the first scan signal line Gate1 away from the substrate.

[0138] In an exemplary embodiment, as shown in FIG5, for at least one pixel driving circuit, the second scan signal line Gate2 connected to the pixel driving circuit is located between the orthographic projection of at least one of the structures of the first electrode 23 of the compensation transistor, the first plate C1 of the capacitor, and the control electrode 32 of the driving transistor on the substrate and the orthographic projection of the first scan signal line Gate1 connected to the pixel driving circuit on the substrate. The second scan signal line Gate2(m) connected to the m-th row pixel driving circuit is located between the orthographic projection of at least one of the structures of the first electrode 23 of the compensation transistor, the first plate C1 of the capacitor, and the control electrode 32 of the driving transistor on the substrate and the orthographic projection of the first scan signal line Gate1(m) connected to the m-th row pixel driving circuit on the substrate.

[0139] In an exemplary embodiment, as shown in FIG5, for at least one pixel driving circuit, the orthographic projection of at least one of the structures of the second terminal 24 of the driving transistor, the second terminal 14 of the first initial transistor (also a first transistor), and the second terminal 24 of the compensation transistor (also a second transistor T2) onto the substrate at least partially overlaps with the orthographic projection of at least one of the first scan signal lines Gate1 and Gate2 connected to the pixel driving circuit onto the substrate. The second terminal 24 of the driving transistor, the second terminal 14 of the first initial transistor (also a first transistor), and the second terminal 24 of the compensation transistor (also a second transistor T2) in the at least one pixel driving circuit are an integral structure.

[0140] In an exemplary embodiment, as shown in FIG5, the first signal line further includes: a first reset signal line Reset1, wherein the control electrode of the first initial transistor of at least one pixel driving circuit is electrically connected to at least one of the plurality of first reset signal lines Reset1, and the first reset signal line Reset1 extends at least partially along the first direction D1.

[0141] In an exemplary embodiment, as shown in FIG5, for at least one pixel driving circuit, the orthographic projection of at least one of the structures of the first electrode 23 of the compensation transistor, the first plate C1 of the capacitor, and the control electrode 32 of the driving transistor on the substrate does not overlap with the orthographic projection of the first reset signal line Reset1 connected to the pixel driving circuit on the substrate, and the orthographic projection of the first reset signal line Reset1 connected to the pixel driving circuit on the substrate is located on the side of the first scan signal line Gate1 connected to the pixel driving circuit away from the second scan signal line Gate2 connected to the pixel driving circuit. The orthographic projection of at least one of the following structures in the m-th row pixel driving circuit—the first electrode 23 of the compensation transistor, the first plate C1 of the capacitor, and the control electrode 32 of the driving transistor—on the substrate does not overlap with the orthographic projection of the first reset signal line Reset1(m) connected to the m-th row pixel driving circuit on the substrate, and the orthographic projection of the first reset signal line Reset1(m) connected to the m-th row pixel driving circuit on the substrate is located on the side of the first scan signal line Gate1(m) connected to the m-th row pixel driving circuit that is far away from the orthographic projection of the second scan signal line Gate2(m) connected to the m-th row pixel driving circuit on the substrate.

[0142] In an exemplary embodiment, as shown in FIG5, the first signal line further includes a second reset signal line Reset2. For at least one pixel driving circuit, the control electrode of at least one of the second initial transistors and the third initial transistor is electrically connected to at least one of the multiple second reset signal lines. The second electrode of the second initial transistor is electrically connected to the first electrode of the light-emitting device connected to the pixel driving circuit. The second electrode of the third initial transistor is electrically connected to the first electrode of the driving transistor. The second reset signal line Reset2 extends at least partially along the first direction D1.

[0143] In an exemplary embodiment, as shown in FIG5, for at least one pixel driving circuit, the orthographic projection of at least one of the structures of the first electrode 23 of the compensation transistor, the first plate C1 of the capacitor, and the control electrode 32 of the driving transistor on the substrate does not overlap with the orthographic projection of the second reset signal line Reset2 connected to the pixel driving circuit on the substrate, and the orthographic projection of the second reset signal line Reset2 connected to the pixel driving circuit on the substrate is located on the side away from the second scan signal line Gate2 connected to the pixel driving circuit. For example, the orthographic projection of at least one of the structures of the first electrode 23 of the compensation transistor, the first plate C1 of the capacitor, and the control electrode 32 of the driving transistor in the m-th row pixel driving circuit onto the substrate does not overlap with the orthographic projection of the second reset signal line Reset2(m) connected to the m-th row pixel driving circuit onto the substrate, and the orthographic projection of the second reset signal line Reset2(m) connected to the m-th row pixel driving circuit onto the substrate is located on the side away from the second scan signal line Gate2(m) connected to the m-th row pixel driving circuit.

[0144] In an exemplary embodiment, as shown in FIG5, the first signal line further includes: a light-emitting signal line EM, the control electrode of at least one of the first light-emitting transistor and the second light-emitting transistor is electrically connected to the light-emitting signal line EM, the second electrode of the first light-emitting transistor is electrically connected to the first electrode of the driving transistor, the first electrode of the second light-emitting transistor is electrically connected to the second electrode of the driving transistor, and the light-emitting signal line EM extends along the first direction D1.

[0145] In an exemplary embodiment, as shown in FIG5, for at least one pixel driving circuit, the orthographic projection of at least one of the structures of the first electrode 23 of the compensation transistor, the first plate C1 of the capacitor, and the control electrode 32 of the driving transistor on the substrate does not overlap with the orthographic projection of the light-emitting signal line EM connected to the pixel driving circuit on the substrate, and the light-emitting signal line EM connected to the pixel driving circuit is located between the orthographic projection of at least one of the structures of the first electrode 23 of the compensation transistor, the first plate C1 of the capacitor, and the control electrode 32 of the driving transistor in the pixel driving circuit and the second reset signal line Reset2 connected to the pixel driving circuit on the substrate. For example, the orthographic projection of at least one of the structures of the first electrode 23 of the compensation transistor, the first plate C1 of the capacitor, and the control electrode 32 of the driving transistor in the m-th row pixel driving circuit onto the substrate does not overlap with the orthographic projection of the light-emitting signal line EM(m) connected to the m-th row pixel driving circuit onto the substrate, and the light-emitting signal line EM(m) connected to the m-th row pixel driving circuit is located between the orthographic projection of at least one of the structures of the first electrode 23 of the compensation transistor, the first plate C1 of the capacitor, and the control electrode 32 of the driving transistor in the pixel driving circuit and the second reset signal line Reset2(m) connected to the m-th row pixel driving circuit onto the substrate.

[0146] In an exemplary embodiment, as shown in FIG5, the first signal line further includes: a first initial signal line INIT1, wherein the first pole of the first initial transistor in at least one pixel driving circuit is electrically connected to at least one of the plurality of first initial signal lines INIT1, and the first initial signal line INIT1 extends along a first direction D1.

[0147] In an exemplary embodiment, as shown in FIG5, for at least one pixel driving circuit, the orthographic projection of at least one of the structures of the first electrode 23 of the compensation transistor, the first plate C1 of the capacitor, and the control electrode 32 of the driving transistor on the substrate does not overlap with the orthographic projection of the first initial signal line INIT1 connected to the pixel driving circuit on the substrate, and the orthographic projection of the first initial signal line INIT1 connected to the pixel driving circuit on the substrate is located on the side of the first scan signal line Gate1 connected to the pixel driving circuit away from the second scan signal line Gate2 connected to the pixel driving circuit on the substrate. For example, the orthographic projection of at least one of the structures of the first electrode 23 of the compensation transistor, the first plate C1 of the capacitor, and the control electrode 32 of the driving transistor in the m-th row pixel driving circuit on the substrate does not overlap with the orthographic projection of the first initial signal line INIT1(m) connected to the m-th row pixel driving circuit on the substrate, and the orthographic projection of the first initial signal line INIT1(m) connected to the m-th row pixel driving circuit on the substrate is located on the side of the first scan signal line Gate1(m) connected to the m-th row pixel driving circuit that is far away from the second scan signal line Gate2(m) connected to the m-th row pixel driving circuit.

[0148] In an exemplary embodiment, as shown in FIG5, the first signal line further includes: a second initial signal line INIT2, wherein the first terminal of the second initial transistor in at least one pixel driving circuit is electrically connected to at least one of the plurality of second initial signal lines INIT2, and the second initial signal line INIT2 extends along the first direction D1;

[0149] In an exemplary embodiment, as shown in FIG5, for at least one pixel driving circuit, the orthographic projection of at least one of the structures of the first electrode 23 of the compensation transistor, the first electrode C1 of the capacitor, and the control electrode 32 of the driving transistor on the substrate does not overlap with the orthographic projection of the second initial signal line INIT2 connected to the pixel driving circuit on the substrate, and the orthographic projection of the second initial signal line INIT2 connected to the pixel driving circuit on the substrate is located on the side of the second reset signal line Reset2 connected to the pixel driving circuit away from the first scan signal line Gate1 connected to the pixel driving circuit on the substrate. For example, the orthographic projection of at least one of the structures of the first electrode 23 of the compensation transistor, the first plate C1 of the capacitor, and the control electrode 32 of the driving transistor in the m-th row pixel driving circuit on the substrate does not overlap with the orthographic projection of the second initial signal line INIT2(m) connected to the m-th row pixel driving circuit on the substrate, and the orthographic projection of the second initial signal line INIT2(m) connected to the m-th row pixel driving circuit on the substrate is located on the side of the second reset signal line Reset2(m) connected to the m-th row pixel driving circuit that is far away from the first scan signal line Gate1(m) connected to the m-th row pixel driving circuit.

[0150] In an exemplary embodiment, as shown in FIG5, for at least one pixel driving circuit, the orthographic projection of the second initial signal line INIT2 connected to the pixel driving circuit on the substrate at least partially overlaps with the orthographic projection of at least one of the first reset signal line Reset1 and the first initial signal line INIT1 connected to the next row pixel driving circuit on the substrate. For example, the orthographic projection of the second initial signal line INIT2(m-1) connected to the (m-1)th row pixel driving circuit on the substrate at least partially overlaps with the orthographic projection of at least one of the first reset signal line Reset1(m) and the first initial signal line INIT1(m) connected to the m-th row pixel driving circuit on the substrate.

[0151] In an exemplary embodiment, as shown in FIG5, the first signal line further includes a third initial signal line INIT3, wherein the first terminal of the third initial transistor in at least one pixel driving circuit is electrically connected to at least one of the plurality of third initial signal lines INIT3, and the third initial signal line INIT3 extends along the first direction D1.

[0152] In an exemplary embodiment, as shown in FIG5, for at least one pixel driving circuit, the orthographic projection of at least one of the structures of the first electrode 23 of the compensation transistor, the first plate C1 of the capacitor, and the control electrode 32 of the driving transistor on the substrate does not overlap with the orthographic projection of the third initial signal line INIT3 connected to the pixel driving circuit on the substrate, and the orthographic projection of the third initial signal line INIT3 connected to the pixel driving circuit on the substrate at least partially overlaps with the orthographic projection of the second reset signal line Reset2 connected to the pixel driving circuit on the substrate. Exemplarily, the orthographic projection of at least one of the structures of the first electrode 23 of the compensation transistor, the first plate C1 of the capacitor, and the control electrode 32 of the driving transistor in the m-th row pixel driving circuit on the substrate does not overlap with the orthographic projection of the third initial signal line INIT3(m) connected to the m-th row pixel driving circuit on the substrate, and the orthographic projection of the third initial signal line INIT3(m) connected to the m-th row pixel driving circuit on the substrate at least partially overlaps with the orthographic projection of the second reset signal line Reset2(m) connected to the m-th row pixel driving circuit on the substrate.

[0153] In an exemplary embodiment, as shown in FIG5, the orthographic projections of the third initial signal line INIT3 connected to the pixel driving circuit and the light-emitting signal line EM connected to the pixel driving circuit on the substrate do not overlap. This lack of overlap prevents the third initial signal line INIT3 from being interfered with by the pulse signal of the light-emitting signal line EM, thereby improving the reliability of the display substrate.

[0154] In an exemplary embodiment, as shown in FIG5, the circuit structures of at least two adjacent pixel driving circuits located in the same row are symmetrically arranged to intersect with respect to a virtual straight line extending along the second direction.

[0155] In an exemplary embodiment, the display substrate may further include: a plurality of second signal lines, at least one of which extends along a second direction, and the first direction intersects the second direction. The intersection of the first and second directions includes the first direction being perpendicular to the second direction. The second signal lines include: a first power line, a data signal line, and an initial connection line. At least one initial connection line is electrically connected to at least one third initial signal line. The plurality of initial connection lines and the plurality of third initial signal lines form a mesh structure, which can ensure the uniformity of biasing the driving transistors by multiple pixel driving circuits during display, thereby improving the reliability of the display substrate.

[0156] In an exemplary embodiment, the plurality of transistors includes at least one P-type transistor and at least one N-type transistor.

[0157] In an exemplary embodiment, the display substrate further includes a circuit structure layer, which includes a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, and a fourth conductive layer sequentially stacked on the substrate.

[0158] In an exemplary embodiment, the first semiconductor layer includes an active pattern of at least one P-type transistor located in at least one pixel driving circuit.

[0159] In an exemplary embodiment, the first conductive layer includes: a first scan signal line, a light emission signal line, a first reset signal line, a second reset signal line, and the control electrode of at least one P-type transistor and the first plate of a capacitor located in at least one pixel driving circuit.

[0160] In an exemplary embodiment, the second conductive layer includes: a first scan line of at least one of the second scan signal lines, a first initial signal line, and a second plate of a capacitor located in at least one pixel driving circuit.

[0161] In an exemplary embodiment, the second semiconductor layer includes an active pattern of at least one P-type transistor located in at least one pixel driving circuit.

[0162] In an exemplary embodiment, the third conductive layer includes: a second scan line, a second initial signal line, and a third initial signal line, at least one of the second scan signal lines.

[0163] In an exemplary embodiment, the fourth conductive layer includes: a first electrode and a second electrode of at least one transistor located in at least one pixel driving circuit.

[0164] In an exemplary embodiment, the circuit structure layer may further include a fifth conductive layer located on the side of the fourth conductive layer away from the substrate. The fifth conductive layer includes at least a first power line, a data signal line, and an initial connection line.

[0165] In an exemplary embodiment, the circuit structure layer may further include a light-shielding layer located on the side of the first semiconductor layer near the substrate. The light-shielding layer includes at least one light-shielding structure, wherein the orthographic projection of the at least one light-shielding structure on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least one transistor of at least one pixel driving circuit on the substrate.

[0166] In an exemplary embodiment, when the pixel driving circuit of the display substrate is the pixel driving circuit provided in FIG3B, the second pole of the first transistor in at least one pixel driving circuit can be electrically connected to the first node through a conductive connection line. The conductive connection line can be located in the fourth conductive layer or the light-shielding layer, as long as the conductive connection line is not short-circuited with any of the multiple signal lines connected to the pixel driving circuit.

[0167] The following description uses the fabrication process of a display substrate as an example. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film made of a certain material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0168] Figures 6 to 17 are schematic diagrams illustrating the fabrication process of a display substrate provided in an exemplary embodiment. Figures 6 to 17 are illustrated using a one-row, two-column pixel driving circuit as an example.

[0169] The fabrication process of the display substrate provided in this disclosure may include, as shown in Figures 6 to 17:

[0170] (1) Forming a first semiconductor layer pattern. In an exemplary embodiment, forming a first semiconductor layer pattern may include: depositing a first semiconductor thin film on a substrate, and patterning the first semiconductor thin film by a patterning process to form a first semiconductor layer pattern, as shown in FIG6, FIG6 being a schematic diagram of the first semiconductor layer pattern in FIG5.

[0171] In an exemplary embodiment, as shown in FIG6, the first semiconductor layer pattern may include at least an active pattern of at least one P-type transistor located in at least one pixel driving circuit. FIG6 is illustrated using an example where the active pattern of at least one P-type transistor includes: an active pattern 11 of a first transistor, an active pattern 31 of a third transistor, an active pattern 41 of a fourth transistor, an active pattern 51 of a fifth transistor, an active pattern 61 of a sixth transistor, an active pattern 71 of a seventh transistor, and an active pattern 81 of an eighth transistor.

[0172] In an exemplary embodiment, for at least one pixel driving circuit, the active pattern 31 of the third transistor, the active pattern 41 of the fourth transistor, the active pattern 51 of the fifth transistor, the active pattern 61 of the sixth transistor, and the active pattern 71 of the seventh transistor are integrally formed. The active pattern 11 of the first transistor and the active pattern 81 of the eighth transistor are separately configured.

[0173] In an exemplary embodiment, in the first direction D1, the active patterns 41 of the fourth transistor and 51 of the fifth transistor of at least one column of pixel driving circuits are located on the side of the active pattern 31 of the third transistor of the same column of pixel driving circuits near the previous column of pixel driving circuits, and the active patterns 11 of the first transistor and 61 of the sixth transistor of at least one column of pixel driving circuits are located on the side of the active pattern 31 of the third transistor of the same column of pixel driving circuits near the next column of pixel driving circuits. In the second direction D2, the active patterns 11 of the first transistor and 41 of the fourth transistor of at least one row of pixel driving circuits are located on the side of the active pattern 31 of the third transistor of the same row of pixel driving circuits near the previous row of pixel driving circuits, and the active patterns 51 of the fifth transistor, 61 of the sixth transistor, 71 of the seventh transistor, and 81 of the eighth transistor of at least one row of pixel driving circuits are near the side of the next row of pixel driving circuits.

[0174] In an exemplary embodiment, the active pattern 31 of the third transistor may be in the shape of an inverted “Ω”.

[0175] In an exemplary embodiment, the active pattern 11 of the first transistor, the active pattern 41 of the fourth transistor, the active pattern 51 of the fifth transistor, and the active pattern 71 of the seventh transistor can be in the shape of an "I".

[0176] In an exemplary embodiment, the active pattern 61 of the sixth transistor may be in the shape of a horizontally flipped "L".

[0177] In an exemplary embodiment, the active pattern of each transistor may include a first region, a second region, and a channel region located between the first and second regions. In an exemplary embodiment, for at least one pixel driving circuit, the first region 31-1 of the active pattern 31 of the third transistor may simultaneously serve as the second region 41-2 of the active pattern 41 of the fourth transistor and the second region 51-2 of the active pattern 51 of the fifth transistor. The second region 31-2 of the active pattern 31 of the third transistor may simultaneously serve as the first region 61-1 of the active pattern 61 of the sixth transistor. The first region 11-1 and the second region 11-2 of the active pattern 11 of the first transistor, the first region 41-1 of the active pattern 41 of the fourth transistor, the first region 51-1 of the active pattern 51 of the fifth transistor, the first region 71-1 of the active pattern 71 of the seventh transistor, and the first region 81-1 and the second region 81-2 of the active pattern 81 of the eighth transistor may be configured individually.

[0178] (2) Forming a first conductive layer pattern. In an exemplary embodiment, forming a first conductive layer pattern may include: sequentially depositing a first insulating film and a first conductive film on a substrate on which the aforementioned pattern is formed; patterning the first insulating film and the first conductive film using a patterning process to form a first insulating layer pattern and a first conductive layer pattern located on the first insulating layer, as shown in Figures 7 and 8. Figure 7 is a schematic diagram of the first conductive layer pattern in Figure 5, and Figure 8 is a schematic diagram of Figure 5 after the first conductive layer pattern has been formed. In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0179] In an exemplary embodiment, as shown in Figures 7 and 8, the first conductive layer pattern may include: a first scan signal line Gate1, a first reset signal line Reset1, a second reset signal line Reset2, a light emission signal line EM, and the control electrode of at least one P-type transistor located in at least one pixel driving circuit, and the first electrode C1 of a capacitor. Figure 7 illustrates an example where the control electrodes of at least one P-type transistor include: the control electrode 12 of the first transistor, the control electrode 32 of the third transistor, the control electrode 42 of the fourth transistor, the control electrode 52 of the fifth transistor, the control electrode 62 of the sixth transistor, the control electrode 72 of the seventh transistor, and the control electrode 82 of the eighth transistor.

[0180] In an exemplary embodiment, for at least one row of sub-pixels, the first reset signal line Reset1, the first scan signal line Gate1, the light emission signal line EM, and the second reset signal line Reset2 connected to the pixel driving circuit are arranged sequentially along the second direction D2.

[0181] In an exemplary embodiment, the first reset signal line Reset1 and the first scan signal line Gate1 connected to at least one row of pixel driving circuits are located on the side of the first plate C1 of the capacitor of the pixel driving circuit closer to the previous row of pixel driving circuits, and the first reset signal line Reset1 connected to at least one row of pixel driving circuits is located on the side of the first scan signal line Gate1 connected to at least one row of pixel driving circuits away from the first plate C1 of the capacitor of the pixel driving circuit.

[0182] In an exemplary embodiment, the light-emitting signal line EM and the second reset signal line Reset2 connected to at least one row of pixel driving circuits are located on the side of the first plate C1 of the capacitor of the pixel driving circuit closer to the next row of pixel driving circuits, and the second reset signal line Reset2 connected to at least one row of pixel driving circuits is located on the side of the light-emitting signal line EM connected to at least one row of pixel driving circuits away from the first plate C1 of the capacitor of the pixel driving circuit.

[0183] In an exemplary embodiment, the shape of the first reset signal line Reset1 can be a line shape in which the main body extends along the first direction D1. The area where the first reset signal line Reset1, to which at least one pixel driving circuit is connected, overlaps with the active pattern of the first transistor can be the control electrode 12 of the first transistor.

[0184] In an exemplary embodiment, the shape of the first scan signal line Gate1 can be a line shape in which the main body extends along the first direction D1. The area where the first scan signal line Gate1, to which at least one pixel driving circuit is connected, overlaps with the active pattern of the fourth transistor can be the control electrode 42 of the fourth transistor.

[0185] In an exemplary embodiment, the shape of the light-emitting signal line EM can be a line shape extending along the first direction D1 of the main body portion. The area where the light-emitting signal line EM connected to at least one pixel driving circuit overlaps with the active pattern of the fifth transistor can be the control electrode 52 of the fifth transistor, and the area where the light-emitting signal line EM connected to at least one pixel driving circuit overlaps with the active pattern of the sixth transistor can be the control electrode 62 of the sixth transistor.

[0186] In an exemplary embodiment, the shape of the second reset signal line Reset2 can be a line shape in which the main body extends along the first direction D1. The area where the second reset signal line Reset2, connected to at least one pixel driving circuit, overlaps with the active pattern of the seventh transistor can be the control electrode 72 of the seventh transistor, and the area where the second reset signal line Reset2, connected to at least one pixel driving circuit, overlaps with the active pattern of the eighth transistor can be the control electrode 82 of the eighth transistor.

[0187] In an exemplary embodiment, the first plate C1 of the capacitor in at least one pixel driving circuit can be rectangular in shape, and the corners of the rectangle can be chamfered. Exemplarily, the first plate C1 of the capacitor can serve as the control electrode 32 of the third transistor.

[0188] In an exemplary embodiment, the first scan signal line Gate1, the first reset signal line Reset1, the second reset signal line Reset2, and the light emission signal line EM can be designed with equal width or with non-equal width, and can be straight lines or broken lines. This not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the signal lines. This disclosure does not limit the scope of the invention.

[0189] In an exemplary embodiment, after the first conductive layer pattern is formed, the first conductive layer can be used as a shield to conduct the first semiconductor layer. The first semiconductor layer in the area shielded by the first conductive layer forms the channel regions of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor. The first semiconductor layer in the area not shielded by the first conductive layer is conducted.

[0190] In an exemplary embodiment, the control electrode of the first transistor is disposed across the active pattern of the first transistor, the control electrode of the third transistor is disposed across the active pattern of the third transistor, the control electrode of the fourth transistor is disposed across the active pattern of the fourth transistor, the control electrode of the fifth transistor is disposed across the active pattern of the fifth transistor, the control electrode of the sixth transistor is disposed across the active pattern of the sixth transistor, the control electrode of the seventh transistor is disposed across the active pattern of the seventh transistor, and the control electrode of the eighth transistor is disposed across the active pattern of the eighth transistor. That is, the extension direction of the control electrode of at least one transistor is perpendicular to the extension direction of the active pattern.

[0191] (3) Forming a second conductive layer pattern. In an exemplary embodiment, forming a second conductive layer pattern may include: sequentially depositing a second insulating film and a second conductive film on a substrate on which the aforementioned pattern is formed; patterning the second insulating film and the second conductive film using a patterning process to form a second insulating layer pattern and a second conductive layer pattern located on the second insulating layer, as shown in Figures 9 and 10. Figure 9 is a schematic diagram of the second conductive layer pattern in Figure 5, and Figure 10 is a schematic diagram of the second conductive layer pattern after it has been formed in Figure 5. In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0192] In an exemplary embodiment, as shown in Figures 9 and 10, the second conductive layer pattern may include: a first initial signal line INIT1, a first scan line Gate2A of a second scan signal line Gate2, a second plate C2 of a capacitor located in at least one pixel driving circuit, and a first control electrode of at least one N-type transistor. The first control electrode of at least one N-type transistor may include: a first control electrode 22A of a second transistor.

[0193] In an exemplary embodiment, the first scan line Gate2A, which is connected to at least one row of pixel driving circuits, is arranged sequentially along the second direction D2.

[0194] In an exemplary embodiment, the orthographic projection of the first initial signal line INIT1 connected to the pixel driving circuit on the substrate is located on the side where the orthographic projection of the first reset signal line connected to the pixel driving circuit on the substrate is far from the orthographic projection of the first scan signal line connected to the pixel driving circuit on the substrate.

[0195] In an exemplary embodiment, the orthographic projection of the first scan line Gate2A of the second scan signal line Gate2 connected to the pixel driving circuit on the substrate is located between the orthographic projection of the first scan signal line Gate1 connected to the pixel driving circuit on the substrate and the orthographic projection of at least one of the first and second plates of the capacitor located in the pixel driving circuit on the substrate.

[0196] In an exemplary embodiment, the shape of the first initial signal line INIT1 can be a line shape in which the main body extends along the first direction D1.

[0197] In an exemplary embodiment, the shape of the first scan line Gate2A of the second scan signal line Gate2 can be a line shape in which the main body extends along the first direction D1. The area where the first scan line Gate2A of the second scan signal line Gate2, to which at least one pixel driving circuit is connected, overlaps with the active pattern of the second transistor can be the first control electrode 22A of the second transistor.

[0198] In an exemplary embodiment, the first scan line Gate2A of the first initial signal line INIT1 and the second scan signal line Gate2 can be designed with equal width or with non-equal width, and can be a straight line or a broken line. This not only facilitates the layout of the pixel structure, but also reduces the parasitic capacitance between signal lines. This disclosure does not limit the scope of the invention.

[0199] In an exemplary embodiment, the main outline of the second electrode C2 of the capacitor can be rectangular, and the corners of the rectangle can be chamfered. The orthographic projection of the main body of the second electrode C2 on the substrate at least partially overlaps with the orthographic projection of the first electrode of the capacitor on the substrate. The second electrode C2 of the capacitor is provided with an opening V, which can be rectangular in shape and located in the middle of the second electrode C2, so that the second electrode C2 of the capacitor forms a ring structure. The opening V exposes the second insulating layer covering the first electrode of the capacitor, and the orthographic projection of the first electrode of the capacitor on the substrate covers the orthographic projection of the opening V on the substrate. In the exemplary embodiment, the opening V exposes the first electrode of the capacitor, so that the first electrode of the subsequently formed second transistor is connected to the first electrode of the capacitor.

[0200] In an exemplary embodiment, the second plate C2 of the capacitors of adjacent pixel driving circuits located in the same row is electrically connected.

[0201] (4) Forming a second semiconductor layer pattern. In an exemplary embodiment, forming a second semiconductor layer pattern may include: on the substrate on which the aforementioned pattern is formed, including: sequentially depositing a third insulating film and a second semiconductor film on the substrate, and patterning the third insulating film and the second semiconductor film by a patterning process to form a third insulating layer pattern and a second semiconductor layer pattern located on the third insulating layer, as shown in Figures 11 and 12. Figure 11 is a schematic diagram of the second semiconductor layer pattern in Figure 5, and Figure 12 is a schematic diagram of the second semiconductor layer pattern after it is formed in Figure 5.

[0202] In an exemplary embodiment, as shown in Figures 11 and 12, the second semiconductor layer pattern may include an active pattern of at least one N-type transistor located in at least one pixel driving circuit. The active pattern of the at least one N-type transistor includes an active pattern 21 of the second transistor.

[0203] In an exemplary embodiment, as shown in Figures 11 and 12, the active pattern 21 of the second transistor is configured separately.

[0204] In an exemplary embodiment, the active pattern 21 of the second transistor is in the shape of an "I".

[0205] In an exemplary embodiment, the active pattern of each transistor may include a first region, a second region, and a channel region located between the first and second regions. In an exemplary embodiment, for at least one pixel driving circuit, the active pattern 21 of the second transistor includes a first region 21-1 and a second region 21-2.

[0206] In an exemplary embodiment, the active pattern 21 of the second transistor is disposed across the first control electrode of the second transistor.

[0207] (5) Forming a third conductive layer pattern. In an exemplary embodiment, forming a second semiconductor layer pattern may include: sequentially depositing a fourth insulating film and a third conductive film on a substrate on which the aforementioned pattern is formed; patterning the fourth insulating film and the third conductive film using a patterning process to form a fourth insulating layer pattern and a third conductive layer pattern located on the fourth insulating layer, as shown in Figures 13 and 14. Figure 13 is a schematic diagram of the third conductive layer pattern in Figure 5, and Figure 14 is a schematic diagram of the third conductive layer pattern after it has been formed in Figure 5. In an exemplary embodiment, the third conductive layer may be referred to as a third gate metal (GATE3) layer.

[0208] In an exemplary embodiment, as shown in Figures 13 and 14, the third conductive layer pattern may include: a second scan line Gate2B of the second scan signal line Gate2, a second initial signal line INIT2, a third initial signal line INIT3, and a second control electrode of at least one N-type transistor located in at least one pixel driving circuit. The first control electrode of at least one N-type transistor may include: a second control electrode 22B of the second transistor. In Figure 13, the second initial signal line INIT2(m-1) refers to the second initial signal line connected to the (m-1)th row pixel driving circuit, Gate2B(m) refers to the second scan line of the second scan signal line connected to the mth row pixel driving circuit, the second initial signal line INIT2(m) refers to the second initial signal line connected to the mth row pixel driving circuit, and the third initial signal line INIT3(m) refers to the third initial signal line connected to the mth row pixel driving circuit.

[0209] In an exemplary embodiment, the second scan line Gate2B, the third initial signal line INIT3, and the second initial signal line INIT2 connected to at least one pixel driving circuit are arranged sequentially along the second direction D2.

[0210] In an exemplary embodiment, the shape of the second scan line Gate2B of the second scan signal line Gate2 connected to at least one pixel driving circuit can be a line shape in which the main part extends along the first direction D1. The orthographic projection of the second scan line Gate2B of the second scan signal line Gate2 connected to at least one pixel driving circuit on the substrate at least partially overlaps with the orthographic projection of the first scan line of the second scan signal line Gate2 connected to at least one pixel driving circuit on the substrate. The area where the second scan line Gate2B of the second scan signal line Gate2 connected to at least one pixel driving circuit overlaps with the active pattern of the second transistor can serve as the second control electrode 22B of the second transistor.

[0211] In an exemplary embodiment, the shape of the third initial signal line INIT3 can be a line shape in which the main body extends along the first direction D1. The orthographic projection of the third initial signal line INIT3 connected to at least one pixel driving circuit on the substrate at least partially overlaps with the orthographic projection of the second reset signal line on the substrate, and there is no overlap with the orthographic projection of the light emission signal line on the substrate.

[0212] In an exemplary embodiment, the shape of the second initial signal line INIT2 can be a line shape in which the main body extends along the first direction D1. The orthographic projection of the second initial signal line INIT2 connected to at least one pixel driving circuit on the substrate is located on the side of the orthographic projection of the third scan signal line connected to at least one pixel driving circuit on the substrate that is far from the side of the orthographic projection of the light emission signal line connected to at least one pixel driving circuit on the substrate that is far from the substrate.

[0213] In an exemplary embodiment, the orthographic projection of the second initial signal line INIT2(m-1) connected to the pixel driving circuit of the (m-1)th row on the substrate at least partially overlaps with the orthographic projections of the first reset signal line and the first initial signal line connected to the pixel driving circuit of the (m-1)th row on the substrate.

[0214] In an exemplary embodiment, the second scan line Gate2B, the second initial signal line INIT2, and the third initial signal line INIT3 of the second scan signal line Gate2 can be designed with equal width or with non-equal width, and can be straight lines or broken lines. This not only facilitates the layout of the pixel structure, but also reduces the parasitic capacitance between signal lines. This disclosure does not limit the scope of the invention.

[0215] (6) Forming a fifth insulating layer pattern includes: depositing a fifth insulating film on a substrate on which the aforementioned pattern has been formed, and patterning the fifth insulating film by a patterning process to form a fifth insulating layer pattern covering the aforementioned pattern. The fifth insulating layer has multiple via patterns, as shown in Figure 15. Figure 15 is a schematic diagram of the fifth insulating layer pattern formed in Figure 5.

[0216] In an exemplary embodiment, as shown in FIG15, the plurality of vias in the fifth insulating layer pattern include at least: a first via V1 to a nineteenth via V19 located in at least one pixel driving circuit.

[0217] In an exemplary embodiment, the orthographic projection of the first via V1 onto the substrate is within the orthographic projection range of the first region of the active pattern of the first transistor onto the substrate. The fourth insulating layer, the third insulating layer, the second insulating layer, and the first insulating layer within the first via V1 are etched away, exposing the surface of the first region of the active layer of the first transistor. The first via V1 is configured to allow the first electrode of the subsequently formed first transistor to be connected to the first region of the active layer of the first transistor through the via.

[0218] In an exemplary embodiment, the orthographic projection of the second via V2 onto the substrate is within the orthographic projection of the second region of the active pattern of the first transistor onto the substrate. The fourth insulating layer, the third insulating layer, the second insulating layer, and the first insulating layer within the second via V2 are etched away, exposing the surface of the second region of the active pattern of the first transistor. The second via V2 is configured to allow the second terminal of the subsequently formed first transistor (which is also the second terminal of the second transistor, the second terminal of the third transistor, and the first terminal of the sixth transistor) to be connected to the second region of the active pattern of the first transistor through the via.

[0219] In an exemplary embodiment, the orthographic projection of the third via V3 onto the substrate lies within the range of the orthographic projection of the first region of the active pattern of the third transistor (which is also the second region of the active pattern of the fourth transistor and the second region of the active pattern of the fifth transistor) onto the substrate. The fourth insulating layer, the third insulating layer, the second insulating layer, and the first insulating layer within the third via V3 are etched away, exposing the surface of the first region of the active pattern of the third transistor (which is also the second region of the active pattern of the fourth transistor and the second region of the active pattern of the fifth transistor). The third via V3 is configured to allow the first electrode of the subsequently formed third transistor (which is also the second electrode of the fourth transistor, the second electrode of the fifth transistor, and the second electrode of the eighth transistor) to be connected to the first region of the active pattern of the third transistor (which is also the second region of the active pattern of the fourth transistor and the second region of the active pattern of the fifth transistor) through the via.

[0220] In an exemplary embodiment, the orthographic projection of the fourth via V4 onto the substrate lies within the orthographic projection of the second region of the active pattern of the third transistor (which is also the first region of the active pattern of the sixth transistor) onto the substrate. The fourth insulating layer, the third insulating layer, the second insulating layer, and the first insulating layer within the fourth via V4 are etched away, exposing the surface of the second region of the active pattern of the third transistor (which is also the second region of the active pattern of the sixth transistor). The fourth via V4 is configured to allow the second electrode of the subsequently formed first transistor (which is also the second electrode of the second transistor, the second electrode of the third transistor, and the first electrode of the sixth transistor) to be connected to the second region of the active pattern of the third transistor (which is also the second region of the active pattern of the sixth transistor) through the via.

[0221] In an exemplary embodiment, the orthographic projection of the fifth via V5 onto the substrate is within the orthographic projection of the first region of the active pattern of the fourth transistor onto the substrate. The fourth insulating layer, the third insulating layer, the second insulating layer, and the first insulating layer within the fifth via V5 are etched away, exposing the surface of the first region of the active pattern of the fourth transistor. The fifth via V5 is configured to allow the first electrode of the subsequently formed fourth transistor to be connected to the first region of the active pattern of the fourth transistor through the via.

[0222] In an exemplary embodiment, the orthographic projection of the sixth via V6 onto the substrate is within the orthographic projection of the first region of the active pattern of the fifth transistor onto the substrate. The fourth, third, second, and first insulating layers within the sixth via V6 are etched away, exposing the surface of the first region of the active pattern of the fifth transistor. The sixth via V6 is configured to allow the first electrode of the subsequently formed fifth transistor to be connected to the first region of the active pattern of the fifth transistor through the via.

[0223] In an exemplary embodiment, the orthographic projection of the seventh via V7 onto the substrate lies within the orthographic projection of the second region of the active pattern of the sixth transistor (which is also the second region of the active pattern of the seventh transistor) onto the substrate. The fourth, third, second, and first insulating layers within the seventh via V7 are etched away, exposing the surface of the second region of the active pattern of the sixth transistor (which is also the second region of the active pattern of the seventh transistor). The seventh via V7 is configured to allow the second electrode of the subsequently formed sixth transistor (which is also the second electrode of the seventh transistor) to be connected to the second region of the active pattern of the sixth transistor (which is also the second region of the active pattern of the seventh transistor) through the via.

[0224] In an exemplary embodiment, the orthographic projection of the eighth via V8 onto the substrate is within the orthographic projection of the first region of the active pattern of the seventh transistor onto the substrate. The fourth, third, second, and first insulating layers within the eighth via V8 are etched away, exposing the surface of the first region of the active pattern of the seventh transistor. The eighth via V8 is configured to allow the first electrode of the subsequently formed seventh transistor to be connected to the first region of the active pattern of the seventh transistor through the via.

[0225] In an exemplary embodiment, the orthographic projection of the ninth via V9 onto the substrate is within the orthographic projection of the first region of the active pattern of the eighth transistor onto the substrate. The fourth, third, second, and first insulating layers within the ninth via V9 are etched away, exposing the surface of the first region of the active pattern of the eighth transistor. The ninth via V9 is configured to allow the first electrode of the subsequently formed eighth transistor to be connected to the first region of the active pattern of the eighth transistor through the via.

[0226] In an exemplary embodiment, the orthographic projection of the tenth via V10 onto the substrate lies within the orthographic projection of the second region of the active pattern of the eighth transistor onto the substrate. The fourth, third, second, and first insulating layers within the tenth via V10 are etched away, exposing the surface of the first region of the active pattern of the eighth transistor. The tenth via V10 is configured to allow the first terminal of the subsequently formed third transistor (which is also the second terminal of the fourth, fifth, and eighth transistors) to be connected to the second region of the active pattern of the eighth transistor through the via.

[0227] In an exemplary embodiment, the orthogonal projection of the eleventh via V11 onto the substrate is located within the orthogonal projection of the first electrode of the capacitor (which is also the second electrode of the third transistor) onto the substrate. The fourth, third, and second insulating layers within the eleventh via V11 are etched away, exposing the surface of the first electrode of the capacitor (which is also the second electrode of the third transistor). The eleventh via V11 is configured to allow the first electrode of the subsequently formed second transistor to be connected to the first electrode of the capacitor (which is also the second electrode of the third transistor) through the via.

[0228] In an exemplary embodiment, the orthographic projection of the twelfth via V12 on the substrate is located within the range of the orthographic projection of the second plate of the capacitor on the substrate. The fourth and third insulating layers within the twelfth via V12 are etched away, exposing the surface of the second plate of the capacitor. The twelfth via V12 is configured to allow the first electrode of the subsequently formed fifth transistor to be connected to the second plate of the capacitor through the via.

[0229] In an exemplary embodiment, the orthographic projection of the thirteenth via V13 onto the substrate is within the range of the orthographic projection of the first initial signal line onto the substrate. The fourth and third insulating layers within the thirteenth via V13 are etched away, exposing the surface of the first initial signal line. The thirteenth via V13 is configured to allow the first electrode of the subsequently formed first transistor to be connected to the first initial signal line through the via.

[0230] In an exemplary embodiment, the orthographic projection of the fourteenth via V14 onto the substrate is within the orthographic projection range of the first region of the active pattern of the second transistor onto the substrate. The fourth insulating layer within the fourteenth via V14 is etched away, exposing the surface of the first region of the active pattern of the second transistor. The fourteenth via V14 is configured to allow the first electrode of the subsequently formed second transistor to be connected to the first region of the active pattern of the second transistor through the via.

[0231] In an exemplary embodiment, the orthographic projection of the fifteenth via V15 onto the substrate lies within the orthographic projection of the second region of the active pattern of the second transistor onto the substrate. The fourth insulating layer within the fifteenth via V15 is etched away, exposing the surface of the second region of the active pattern of the second transistor. The fifteenth via V15 is configured to allow the second terminal of the subsequently formed first transistor (which is also the second terminal of the second transistor, the second terminal of the third transistor, and the third terminal of the sixth transistor) to be connected to the second region of the active pattern of the second transistor through the via.

[0232] In an exemplary embodiment, the orthographic projection of the sixteenth via V16 on the substrate is within the range of the orthographic projection of the second initial signal line on the substrate. The sixteenth via V16 exposes the surface of the second initial signal line. The sixteenth via V16 is configured to allow the first electrode of the subsequently formed seventh transistor to be connected to the second initial signal line through the via.

[0233] In an exemplary embodiment, the orthographic projection of the seventeenth via V17 onto the substrate is within the range of the orthographic projection of the third initial signal line onto the substrate. The seventeenth via V17 exposes the surface of the third initial signal line. The seventeenth via V17 is configured to allow the first electrode of the subsequently formed eighth transistor to be connected to the third initial signal line through the via.

[0234] (7) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming a fourth conductive layer pattern may include: depositing a fourth conductive thin film on the substrate on which the aforementioned pattern is formed, and patterning the fourth conductive thin film using a patterning process to form a fourth conductive layer pattern, as shown in Figures 16 and 17. Figure 16 is a schematic diagram of the fourth conductive layer pattern in Figure 5, and Figure 17 is a schematic diagram of the fourth conductive layer pattern after it has been formed in Figure 5. In an exemplary embodiment, the fourth conductive layer may be referred to as a first source / drain metal (SD1) layer.

[0235] In an exemplary embodiment, as shown in Figures 16 and 17, the fourth conductive layer pattern may include: the first pole 13 and the second pole 14 of the first transistor of at least one pixel driving circuit to the first pole 83 and the second pole 84 of the eighth transistor.

[0236] In an exemplary embodiment, the first electrodes of the first transistors in at least two adjacent pixel driving circuits located in the same row are the same electrode. Exemplarily, the first electrode of the first transistor in at least one pixel driving circuit in the same row is the same electrode as the first electrode of the first transistor in one of the adjacent pixel driving circuits.

[0237] In an exemplary embodiment, in at least one pixel driving circuit, the first electrode 13 of the first transistor is separately disposed and is strip-shaped, extending at least partially along the first direction D1. The first electrode 13 of the first transistor is connected to the first region of the active pattern of the first transistor through a first via and is electrically connected to the first initial signal line through a thirteenth via.

[0238] In an exemplary embodiment, the second electrode 14 of the first transistor, the second electrode 24 of the second transistor, the second electrode 34 of the third transistor, and the first electrode 63 of the sixth transistor are integrally formed and are shaped like a horizontally flipped "7". The second electrode 14 of the first transistor (which is also the second electrode 24 of the second transistor, the second electrode 34 of the third transistor, and the first electrode 63 of the sixth transistor) is connected to the second region of the active pattern of the first transistor through a second via, connected to the second region of the active pattern of the third transistor (which is also the second region of the active pattern of the sixth transistor) through a fourth via V4, and connected to the second region of the active pattern of the second transistor through a fifteenth via.

[0239] In an exemplary embodiment, the first electrode 23 of the second transistor is provided separately. The first electrode 23 of the second transistor may be in the shape of a broken line. The first electrode 23 of the second transistor is connected to the first plate of the capacitor (which is also the second electrode of the third transistor) through the eleventh via V11, and is connected to the first region of the active pattern of the second transistor through the fourteenth via.

[0240] In an exemplary embodiment, the orthographic projection of the first electrode 23 of the second transistor onto the substrate does not overlap with the orthographic projection of at least one of the first and second scan signal lines onto the substrate.

[0241] In an exemplary embodiment, the first electrode 33 of the third transistor, the second electrode 44 of the fourth transistor, the second electrode 54 of the fifth transistor, and the second electrode 84 of the eighth transistor are an integral structure in the shape of an "I". The first electrode 33 of the third transistor (which is also the second electrode 44 of the fourth transistor, the second electrode 54 of the fifth transistor, and the second electrode 84 of the eighth transistor) is connected to the first region of the active pattern of the third transistor (which is also the second region of the active pattern of the fourth transistor and the second region of the active pattern of the fifth transistor) through a third via, and is connected to the second region of the active pattern of the eighth transistor through a tenth via.

[0242] In an exemplary embodiment, the first electrode 43 of the fourth transistor is separately disposed and is block-shaped. The first electrode 43 of the fourth transistor is connected to the first region of the active layer of the fourth transistor through a fifth via.

[0243] In an exemplary embodiment, the first electrode 53 of the fifth transistor is separately disposed and is shaped as a strip extending at least partially along the second direction D2. The first electrode 53 of the fifth transistor is connected to the first region of the active pattern of the fifth transistor through a sixth via and to the second plate of the capacitor through a twelfth via.

[0244] In an exemplary embodiment, the second electrode 64 of the sixth transistor (which is also the second electrode 74 of the seventh transistor) is block-shaped, and the second electrode 64 of the sixth transistor (which is also the second electrode 74 of the seventh transistor) is connected to the second region of the active pattern of the sixth transistor (which is also the second region of the active pattern of the seventh transistor) through a seventh via.

[0245] In an exemplary embodiment, the first electrode 73 of the seventh transistor is separately provided and is in the shape of a strip extending at least partially along the first direction D1. The first electrode 73 of the seventh transistor is connected to the first region of the active pattern of the seventh transistor through an eighth via and is connected to the second initial signal line through a sixteenth via.

[0246] In an exemplary embodiment, the first electrode 83 of the eighth transistor is separately provided and is in the shape of a strip extending at least partially along the first direction D1. The first electrode 83 of the eighth transistor is connected to the first region of the active pattern of the eighth transistor through a ninth via and to the third initial signal line through a seventeenth via.

[0247] (8) Forming a planarization layer pattern. In an exemplary embodiment, forming a planarization layer pattern may include: depositing a sixth insulating film on a substrate on which the aforementioned pattern is formed, patterning the sixth insulating film using a patterning process to form a sixth insulating layer, coating a planarization film on the sixth insulating layer, and patterning the planarization film using a patterning process to form a planarization layer pattern covering the aforementioned pattern, wherein the planarization layer has a plurality of via patterns.

[0248] In an exemplary embodiment, the plurality of via patterns on the planarization layer pattern include: eighteenth via to twentieth via.

[0249] In an exemplary embodiment, the orthographic projection of the eighteenth via on the substrate is within the range of the orthographic projection of the first electrode of the fourth transistor on the substrate. The sixth insulating layer in the eighteenth via is etched away, exposing the surface of the first electrode of the fourth transistor. The eighteenth via is configured to allow subsequently formed data signal lines to be connected to the first electrode of the fourth transistor through the via.

[0250] In an exemplary embodiment, the orthogonal projection of the nineteenth via onto the substrate is within the range of the orthogonal projection of the first electrode of the fifth transistor onto the substrate. The sixth insulating layer within the nineteenth via is etched away, exposing the surface of the first electrode of the fifth transistor. The nineteenth via is configured to allow a subsequently formed first power line to be connected to the first electrode of the fifth transistor through the via.

[0251] In an exemplary embodiment, the orthogonal projection of the twentieth via onto the substrate is located within the orthogonal projection of the second electrode of the sixth transistor (which is also the second electrode of the seventh transistor) onto the substrate. The sixth insulating layer within the twentieth via is etched away, exposing the surface of the second electrode of the sixth transistor (which is also the second electrode of the seventh transistor). The twentieth via is configured to allow a subsequently formed anode connection electrode to be connected to the second electrode of the sixth transistor (which is also the second electrode of the seventh transistor) through the via.

[0252] In an exemplary embodiment, the orthographic projection of the 21st via on the substrate is within the range of the orthographic projection of the third initial signal line on the substrate. The sixth insulating layer within the 21st via is etched away, exposing the surface of the third initial signal line. The 21st via is configured to allow subsequently formed initial connection lines to be connected to the third initial signal line through the via.

[0253] (9) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming a fifth conductive layer pattern may include: depositing a fifth conductive film on a substrate on which the aforementioned pattern is formed, and patterning the fifth conductive film using a patterning process to form a fifth conductive layer pattern.

[0254] In an exemplary embodiment, the fifth conductive layer pattern may include at least: a data signal line, a first power line, an initial connection line, and an anode connection electrode located in at least one pixel driving circuit.

[0255] In an exemplary embodiment, the data signal line may be a line shape in which the main body extends along the second direction, and is electrically connected to the first electrode of the fourth transistor through the eighteenth via.

[0256] In an exemplary embodiment, the data signal line can be a line shape in which the main body extends along a second direction. The data signal line is electrically connected to the first electrode of the fifth transistor through a nineteenth via.

[0257] In an exemplary embodiment, the anode connection electrode is electrically connected to the second electrode of the sixth transistor (which is also the second electrode of the seventh transistor) through the twentieth via.

[0258] In an exemplary embodiment, the initial connection line may be a line shape extending along the second direction of the main body portion, and is electrically connected to the third initial signal line through the twenty-first via.

[0259] At this point, the circuit structure layer is fabricated on the substrate. In a plane parallel to the display substrate, the circuit structure layer may include multiple pixel driving circuits and multiple signal lines connected to the pixel driving circuits. In a plane perpendicular to the display substrate, the circuit structure layer may be disposed on the substrate. The pixel driving circuit for at least one sub-pixel includes at least one P-type transistor, at least one N-type transistor, and at least one capacitor, the capacitor including a first electrode and a second electrode.

[0260] The pixel driving circuit layer may include a first semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a second semiconductor layer, a fourth insulating layer, a third conductive layer, a fifth insulating layer, a fourth conductive layer, a sixth insulating layer, a first planarization layer, and a fifth conductive layer, which are sequentially disposed on the substrate.

[0261] In an exemplary embodiment, the first semiconductor layer may be an amorphous silicon layer or a polycrystalline silicon layer.

[0262] In an exemplary embodiment, the second semiconductor layer may be a metal oxide layer. The metal oxide layer may be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium, and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium, and tin, an oxide containing indium and zinc, an oxide containing silicon and indium and tin, or an oxide containing indium or gallium and zinc. The metal oxide layer may be a single layer, a double layer, or a multilayer.

[0263] In an exemplary embodiment, at least one of the first to fifth conductive layers may be a metallic material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or a conductive alloy material, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It may be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. For example, the material used to fabricate the first conductive layer may include molybdenum.

[0264] In an exemplary embodiment, the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer, and the sixth insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer.

[0265] In an exemplary embodiment, the planarization layer may be made of organic materials.

[0266] In an exemplary embodiment, after the circuit structure layer is fabricated, a light-emitting structure layer is fabricated on the circuit structure layer. The fabrication process of the light-emitting structure layer may include the following operations.

[0267] On the substrate with the aforementioned pattern, an anodic conductive film is deposited, and the anodic conductive film is patterned using a patterning process to form an anodic conductive layer pattern disposed on a second planarization layer. On the substrate with the aforementioned pattern, a pixel definition film is deposited, and the pixel definition film is patterned using a patterning process to form a pixel definition layer pattern that exposes the anodic conductive layer pattern. On the substrate with the pixel definition layer pattern, an organic light-emitting material is coated, and the organic light-emitting material is patterned using a patterning process to form an organic structure layer pattern. On the substrate with the organic material layer pattern, a cathode conductive film is deposited, and the cathode conductive film is patterned using a patterning process to form a cathode conductive layer.

[0268] At this point, the luminescent structure layer has been successfully fabricated on the substrate.

[0269] In an exemplary embodiment, the anode conductive layer includes at least the anodes of a plurality of light-emitting devices.

[0270] In an exemplary embodiment, the anode conductive layer adopts a single-layer structure, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or it can adopt a multi-layer composite structure, such as ITO / Ag / ITO.

[0271] In an exemplary embodiment, the organic structure layer may include at least an organic light-emitting layer of a light-emitting device.

[0272] In an exemplary embodiment, the cathode conductive layer may include at least the cathodes of a plurality of light-emitting devices.

[0273] In an exemplary embodiment, the cathode layer can be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or the aforementioned conductive alloy materials, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It can be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. Exemplarily, the fourth conductive layer can be a three-layer stacked structure formed of titanium, aluminum, and titanium.

[0274] In an exemplary embodiment, the subsequent preparation process may include: forming an encapsulation structure layer on the cathode conductive layer. The encapsulation structure layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer is disposed between the first and third encapsulation layers to ensure that external moisture cannot enter the light-emitting structure layer.

[0275] The display substrate described in this embodiment can be used in display products of any resolution.

[0276] In an exemplary embodiment, the display device can be any product or component with display function, such as electronic paper, OLED panel, active-matrix organic light emitting diode (AMOLED) panel, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, etc.

[0277] The accompanying drawings in this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in general design.

[0278] For clarity, the thickness and dimensions of layers or microstructures are enlarged in the accompanying drawings used to describe embodiments of this disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “below” another element, the element may be located “directly” on or “below” the other element, or there may be intermediate elements present.

[0279] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this disclosure shall still be determined by the scope defined in the appended claims.

Claims

A display substrate, comprising: The substrate and a plurality of pixel driving circuits and a plurality of first signal lines disposed on the substrate, wherein at least one pixel driving circuit includes a plurality of transistors, and at least one transistor includes a control electrode, a first electrode and a second electrode, wherein the control electrode of at least one transistor in at least one pixel driving circuit is electrically connected to at least one of the plurality of first signal lines. The pixel driving circuit further includes a capacitor, the capacitor including a first electrode plate, and the plurality of transistors including a driving transistor and a compensation transistor, wherein the first electrode of the compensation transistor and the first electrode plate of the capacitor are respectively electrically connected to the control electrode of the driving transistor. The orthographic projection of at least one of the structures of the first electrode of the compensation transistor, the first plate of the capacitor, and the control electrode of the driving transistor in at least one pixel driving circuit onto the substrate does not overlap with the orthographic projection of at least one of the plurality of first signal lines onto the substrate. The display substrate according to claim 1, wherein, The plurality of transistors further includes: a first initial transistor, the first signal line includes: a first scan signal line, the control electrode of the first initial transistor in at least one pixel driving circuit is electrically connected to at least one of the plurality of first scan signal lines, and the first scan signal line extends at least partially along a first direction; For at least one pixel driving circuit, the orthographic projection of at least one of the structures of the first electrode of the compensation transistor, the first plate of the capacitor, and the control electrode of the driving transistor on the substrate does not overlap with the orthographic projection of the first scan signal line connected to the pixel driving circuit on the substrate. The display substrate according to claim 2, wherein, The compensation transistor is an N-type transistor, and the first signal line includes: a second scan signal line. The control electrode of the compensation transistor in at least one pixel driving circuit is electrically connected to at least one of the multiple second scan signal lines. The second scan signal line extends at least partially along a first direction. For at least one pixel driving circuit, the orthographic projection of at least one of the structures of the first electrode of the compensation transistor, the first plate of the capacitor, and the control electrode of the driving transistor on the substrate does not overlap with the orthographic projection of the second scan signal line connected to the pixel driving circuit on the substrate. The display substrate according to claim 3, wherein, The second scan signal line includes: a first scan line and a second scan line that are interconnected; at least one of the first scan line and the second scan line extends at least partially along a first direction; For at least one second scan signal line, the orthographic projection of the first scan line on the substrate at least partially overlaps with the orthographic projection of the second scan line on the substrate, and the orthographic projection of at least one of the first scan line and the second scan line on the substrate is located on the side of the first scan signal line away from the substrate. The display substrate according to claim 3, wherein, For at least one pixel driving circuit, the second scan signal line connected to the pixel driving circuit is located between the orthographic projection of at least one of the structures of the first electrode of the compensation transistor, the first plate of the capacitor, and the control electrode of the driving transistor on the substrate and the orthographic projection of the first scan signal line connected to the pixel driving circuit on the substrate. The display substrate according to claim 3, wherein, The second terminal of the driving transistor is electrically connected to the second terminal of the first initial transistor and the second terminal of the compensation transistor, respectively. For at least one pixel driving circuit, the orthographic projection of at least one of the structures of the second terminal of the driving transistor, the second terminal of the first initial transistor, and the second terminal of the compensation transistor onto the substrate is at least equal to the orthographic projection of at least one of the first and second scan signal lines connected to the pixel driving circuit onto the substrate. Partial overlap. The display substrate according to claim 3, wherein, The first signal line further includes: a first reset signal line, wherein the control electrode of the first initial transistor of at least one pixel driving circuit is electrically connected to at least one of the plurality of first reset signal lines, and the first reset signal line extends at least partially along a first direction; For at least one pixel driving circuit, the orthographic projection of at least one of the structures of the first electrode of the compensation transistor, the first plate of the capacitor, and the control electrode of the driving transistor on the substrate does not overlap with the orthographic projection of the first reset signal line connected to the pixel driving circuit on the substrate, and the orthographic projection of the first reset signal line connected to the pixel driving circuit on the substrate is located on the side of the first scan signal line connected to the pixel driving circuit that is far away from the second scan signal line connected to the pixel driving circuit. The display substrate according to claim 3 further includes: A plurality of light-emitting devices disposed on a substrate, at least one pixel driving circuit electrically connected to at least one light-emitting device, the at least one light-emitting device comprising: a first electrode, the first signal line further comprising: a second reset signal line, the plurality of transistors further comprising: a second initial transistor and a third initial transistor, for at least one pixel driving circuit, the control electrode of at least one of the second initial transistors and the third initial transistor is electrically connected to at least one of the plurality of second reset signal lines, the second electrode of the second initial transistor is electrically connected to the first electrode of the light-emitting device connected to the pixel driving circuit, the second electrode of the third initial transistor is electrically connected to the first electrode of the driving transistor, and the second reset signal line extends at least partially along a first direction; For at least one pixel driving circuit, the orthographic projection of at least one of the structures of the first electrode of the compensation transistor, the first plate of the capacitor, and the control electrode of the driving transistor on the substrate does not overlap with the orthographic projection of the second reset signal line connected to the pixel driving circuit on the substrate, and the orthographic projection of the second reset signal line connected to the pixel driving circuit on the substrate is located on the side of at least one of the structures of the first electrode of the compensation transistor, the first plate of the capacitor, and the control electrode of the driving transistor in the pixel driving circuit that is away from the second scan signal line connected to the pixel driving circuit. The display substrate according to claim 8, wherein, The first signal line further includes: a light-emitting signal line; at least one pixel driving circuit includes: a first light-emitting transistor and a second light-emitting transistor; the control electrode of at least one of the first and second light-emitting transistors is electrically connected to the light-emitting signal line; the second electrode of the first light-emitting transistor is electrically connected to the first electrode of the driving transistor; the first electrode of the second light-emitting transistor is electrically connected to the second electrode of the driving transistor; and the light-emitting signal line extends along a first direction. For at least one pixel driving circuit, the orthographic projection of at least one of the structures of the first electrode of the compensation transistor, the first plate of the capacitor, and the control electrode of the driving transistor on the substrate does not overlap with the orthographic projection of the light-emitting signal line connected to the pixel driving circuit on the substrate, and the light-emitting signal line connected to the pixel driving circuit is located between the orthographic projection of at least one of the structures of the first electrode of the compensation transistor, the first plate of the capacitor, and the control electrode of the driving transistor in the pixel driving circuit and the second reset signal line connected to the pixel driving circuit on the substrate. The display substrate according to claim 9, wherein, The first signal line further includes: a first initial signal line, wherein the first electrode of the first initial transistor in at least one pixel driving circuit is electrically connected to at least one of the plurality of first initial signal lines, and the first initial signal line extends along a first direction; For at least one pixel driving circuit, the orthographic projection of at least one of the structures of the first electrode of the compensation transistor, the first plate of the capacitor, and the control electrode of the driving transistor on the substrate does not overlap with the orthographic projection of the first initial signal line connected to the pixel driving circuit on the substrate, and the orthographic projection of the first initial signal line connected to the pixel driving circuit on the substrate is located on the side of the first scan signal line connected to the pixel driving circuit that is far away from the second scan signal line connected to the pixel driving circuit. The display substrate according to claim 9, wherein, The first signal line further includes: a second initial signal The first terminal of the second initial transistor in at least one pixel driving circuit is electrically connected to at least one of a plurality of second initial signal lines, the second initial signal lines extending along a first direction; For at least one pixel driving circuit, the orthographic projection of at least one of the structures of the first electrode of the compensation transistor, the first plate of the capacitor, and the control electrode of the driving transistor on the substrate does not overlap with the orthographic projection of the second initial signal line connected to the pixel driving circuit on the substrate, and the orthographic projection of the second initial signal line connected to the pixel driving circuit on the substrate is located on the side of the second reset signal line connected to the pixel driving circuit that is far away from the first scan signal line connected to the pixel driving circuit. The display substrate according to claim 11, wherein, For at least one pixel driving circuit, the orthographic projection of the second initial signal line connected to the pixel driving circuit on the substrate at least partially overlaps with the orthographic projection of at least one of the first reset signal line and the first initial signal line connected to the next row pixel driving circuit on the substrate. The display substrate according to claim 9, wherein, The first signal line further includes: a third initial signal line, wherein the first electrode of the third initial transistor in at least one pixel driving circuit is electrically connected to at least one of the plurality of third initial signal lines, and the third initial signal line extends along a first direction; For at least one pixel driving circuit, the orthographic projection of at least one of the structures of the first electrode of the compensation transistor, the first plate of the capacitor, and the control electrode of the driving transistor on the substrate does not overlap with the orthographic projection of the third initial signal line connected to the pixel driving circuit on the substrate, and the orthographic projection of the third initial signal line connected to the pixel driving circuit on the substrate at least partially overlaps with the orthographic projection of the second reset signal line connected to the pixel driving circuit on the substrate. The display substrate according to claim 13, wherein, The third initial signal line connected to the pixel driving circuit and the light emission signal line connected to the pixel driving circuit do not overlap in their orthogonal projections on the substrate. The display substrate according to claim 1, wherein, The circuit structures of at least two adjacent pixel driving circuits located in the same row are symmetrically arranged to intersect with respect to a virtual straight line extending along the second direction. The display substrate according to claim 1, wherein, The first signal line includes: a first scan signal line, a second scan signal line, a first reset signal line, a second reset signal line, a first initial signal line, a second initial signal line, and a third initial signal line. The second reset signal line includes: a first scan line and a second scan line. The plurality of transistors includes: at least one P-type transistor and at least one N-type transistor. At least one of the plurality of transistors further includes: an active pattern. The capacitor further includes: a second electrode plate. The display substrate further includes: a circuit structure layer. The circuit structure layer includes: a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, and a fourth conductive layer sequentially stacked on the substrate. The first semiconductor layer includes: an active pattern of at least one P-type transistor located in at least one pixel driving circuit; The first conductive layer includes: a first scan signal line, a light emission signal line, a first reset signal line, a second reset signal line, and a control electrode of at least one P-type transistor located in at least one pixel driving circuit and a first electrode of a capacitor; The second conductive layer includes: a first scan line of at least one of the second scan signal lines, a first initial signal line, and a second plate of a capacitor located in at least one pixel driving circuit; The second semiconductor layer includes: an active pattern of at least one P-type transistor located in at least one pixel driving circuit; The third conductive layer includes: a second scan line, a second initial signal line, and a third initial signal line, all of which are second scan signal lines; The fourth conductive layer includes: a first electrode and a second electrode of at least one transistor located in at least one pixel driving circuit. A display device, comprising: The display substrate as described in any one of claims 1 to 16.

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