Display panel and display apparatus

Abstract

A display panel (100) and a display apparatus. A gate driving unit (200a) of the display panel (100) comprises an output circuit (222), a receiving circuit (221) and a storage capacitor that are connected to each other, wherein the output circuit (222) and the receiving circuit (221) each comprise a gate transistor, with an active portion of the gate transistor being located in a first active layer (123); one electrode plate of the storage capacitor is located in a second active layer (127), and a gate of the gate transistor and the other electrode plate of the storage capacitor are located in a first gate layer (125); and the first gate layer (125), the first active layer (123) and the second active layer (127) are all arranged in different layers.

Description

Display panel and display device Technical Field

[0001] This application relates to the field of displays, and in particular to a display panel and display device. Background Technology

[0002] Current OLED (Organic Light-Emitting Diode) display devices face increasingly stringent requirements for power consumption and screen-to-body ratio. To reduce power consumption and increase screen-to-body ratio, Low Temperature Polysilicon Oxide (LTPO) technology is employed. LTPO technology utilizes both low-temperature polysilicon thin-film transistors (LTPS) and oxide thin-film transistors (OTCs), allowing the driving circuit to combine the advantages of both technologies, thereby reducing power consumption and leakage current.

[0003] Currently, display devices using LTPO technology have a large number of film layers, which in turn requires a large number of photomasks, resulting in a more complex process and higher costs. Summary of the Invention

[0004] This application provides a display panel and display device to solve the technical problem of complex manufacturing processes in existing display devices using LTPO technology.

[0005] To address the above issues, the technical solution provided in this application is as follows:

[0006] This application proposes a display panel including a plurality of gate driving units. Each gate driving unit includes an output circuit, a receiving circuit, and a storage capacitor connected to each other. The output circuit includes a first output transistor and a second output transistor connected to each other. The drain of the first output transistor is connected to a clock line, and the drain of the second output transistor is connected to a high potential line. The area of ​​the first output transistor is larger than the area of ​​the second output transistor.

[0007] The output circuit and the receiving circuit both include a gate transistor. The active portion of the gate transistor is located in the first active layer. One plate of the storage capacitor is located in the second active layer. The gate of the gate transistor and the other plate of the storage capacitor are located in the first gate layer. The first gate layer, the first active layer, and the second active layer are all disposed in different layers. Attached Figure Description

[0008] Figure 1 is a simplified diagram of the first structure of the display panel of this application.

[0009] Figure 2 is an equivalent circuit diagram of the pixel driving circuit in the display panel of this application.

[0010] Figure 3 is a simplified diagram of the second structure of the display panel of this application.

[0011] Figure 4 is a simplified diagram of the third structure of the display panel of this application.

[0012] Figure 5 is an equivalent circuit diagram of the gate driving circuit in the display panel of this application.

[0013] Figure 6 is a schematic diagram of the film layer in the display panel of this application.

[0014] Figure 7 is a film layer diagram of the first gate layer in the display panel of this application.

[0015] Figure 8 is a film diagram of the first active layer in the display panel of this application.

[0016] Figure 9 is a stacked diagram of the first active layer and the first gate layer in the display panel of this application.

[0017] Figure 10 is a film diagram of the second active layer in the display panel of this application.

[0018] Figure 11 is a stacked diagram of the first active layer, the second active layer, and the first gate layer in the display panel of this application.

[0019] Figure 12 is a film layer diagram of the second gate layer in the display panel of this application.

[0020] Figure 13 is a stacked diagram of the first active layer, the second active layer, the first gate layer and the second gate layer in the display panel of this application.

[0021] Figure 14 is a film diagram of the first source and drain layer in the display panel of this application.

[0022] Figure 15 is a stacked diagram of the first active layer, second active layer, first gate layer, second gate layer and first source / drain layer in the display panel of this application.

[0023] Figure 16 is a film diagram of the second source and drain layer in the display panel of this application.

[0024] Figure 17 is a stacked diagram of the first active layer, second active layer, first gate layer, second gate layer, first source-drain layer and second source-drain layer in the display panel of this application.

[0025] Figure 18 is a connection diagram of four consecutive gate driving units and clock lines in the display panel of this application. Embodiments of the present invention

[0026] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application. Furthermore, it should be understood that the specific embodiments described herein are only for illustration and explanation of this application and are not intended to limit this application.

[0027] In the description of this application, it should be understood that the terms "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0028] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, features defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, and "at least one" can mean one, two, or more, unless otherwise explicitly specified.

[0029] Please refer to Figures 1 to 17. This application provides a display panel 100, which includes a display area AA and a non-display area NA disposed on one side of the display area AA.

[0030] In this embodiment, the display area AA includes a pixel driving circuit 300 having multiple pixel transistors, the multiple pixel transistors including silicon semiconductor transistors and oxide semiconductor transistors, the active portion of the silicon semiconductor transistor is located in the first active layer 123, and the active portion of the oxide semiconductor transistor is located in the second active layer 127.

[0031] In this embodiment, the non-display area NA is located on one side of the display area AA. The non-display area NA includes a gate driving circuit 200 having multiple cascaded gate driving units 200a. Each gate driving unit 200a includes multiple gate transistors and a storage capacitor connected to the gate transistors.

[0032] In this embodiment, the active portion of the gate transistor is located in the first active layer 123, and one plate of the storage capacitor is located in the second active layer 127.

[0033] In some embodiments of this application, the storage capacitor of the gate driving unit 200a is usually composed of two layers of metal material, which results in a large number of film layers in the display panel 100, thereby increasing the number of photomasks, leading to a more complex process and higher cost. However, this application uses the material of the first active layer 123 to set the active part of the gate transistor and the material of the second active layer 127 to set one electrode of the storage capacitor, so that the one electrode of the storage capacitor is replaced by an active layer material instead of a metal material, removing the metal layer used to prepare the one electrode of the storage capacitor, reducing the number of film layers in the display panel 100, and simplifying the manufacturing process of the display panel 100.

[0034] In this embodiment, the gate driving unit 200a further includes an output circuit 222 and a receiving circuit 221 connected to each other. The area of ​​the gate transistor in the output circuit 222 is larger than the area of ​​the gate transistor in the receiving circuit 221. Since the output circuit 222 is used to transmit control signals to the display area AA, and the receiving circuit 221 is used to transmit signals in the gate driving unit 200a at this level, the load of the gate transistor in the output circuit 222 is greater than the load of the gate transistor in the receiving circuit 221. In order to ensure the output load of the output circuit 222, this application makes the area of ​​the gate transistor in the output circuit 222 larger than the area of ​​the gate transistor in the receiving circuit 221, thereby improving the transmission capability of the output circuit 222.

[0035] It should be noted that the silicon semiconductor transistor in this application is a P-type transistor, and the oxide semiconductor transistor is an N-type transistor.

[0036] It should be noted that the pixel transistor in this application is the transistor constituting the pixel driving circuit 300, and the gate transistor is the transistor constituting the gate driving circuit 200.

[0037] The technical solution of this application will now be described in conjunction with specific embodiments.

[0038] Referring to Figure 1, the display panel 100 includes a display area AA and a non-display area NA adjacent to the display area AA. The display area AA is located within the display area AA. Optionally, the non-display area NA surrounds the display area AA, so that the display area AA is enclosed by the non-display area NA. The display area AA is the area within the display panel 100 used for display functions, and it contains multiple display units that perform these functions. The non-display area NA may be a border area of ​​the display panel 100, and it may contain functional components that assist the display units within the display area AA in performing their display functions.

[0039] Please refer to Figure 1. A bonding terminal 400 is provided on the lower side of the display area AA. The bonding terminal 400 can be connected to an external circuit. The bonding terminal 400 transmits the signals input from the external circuit to the data traces, thereby driving the display panel 100 to display the image. For example, the bonding terminal 400 can be bonded to a chip or a flip-chip film to provide power and drive signals to the display panel 100.

[0040] In this embodiment, multiple light-emitting devices (LEDs) and pixel driving circuits 300 for driving the LEDs can be arrayed in the display area AA. The pixel driving circuit 300 can be a 7T1C, 7T2C, 8T2C, 8T3C, 8T4C, etc. This application does not impose specific limitations. The following description uses an 8T2C pixel driving circuit 300 as an example.

[0041] Referring to Figure 2, the pixel driving circuit 300 may include a switching transistor T2A, a driving transistor T1A, a compensation transistor T3A, a first reset transistor T4A, a second reset transistor T7A, a third reset transistor T8A, a first light-emitting transistor T5A, a second light-emitting transistor T6A, a boost capacitor Cboost, and a control capacitor Cst2.

[0042] Referring to Figure 2, the first electrode of switching transistor T2A is connected to the data signal line Data, the second electrode of switching transistor T2A is connected to control node A1, and the gate of switching transistor T2A receives the switching control signal Pscan1; the first electrode of driving transistor T1A is connected to control node A1, the second electrode of driving transistor T1A is connected to control node B1, and the gate of driving transistor T1A is connected to control node Q1; the first electrode of compensation transistor T3A is connected to control node Q1, the second electrode of compensation transistor T3A is connected to control node B1, and the gate of compensation transistor T3A receives the compensation control signal Nscan1; the first electrode of the first reset transistor T4A receives the first reset signal Vi1, the second electrode of the first reset transistor T4A is connected to control node Q1, and the gate of the first reset transistor T4A receives the first reset control signal Nscan2; the first electrode of the second reset transistor T7A is connected to the second reset signal Vi2, and the second electrode of the second reset transistor T7A is connected to the anode of the light-emitting device. The gate of transistor 7A receives the second reset control signal Pscan2; the first electrode of the third reset transistor T8A receives the third reset signal Vi3, the second electrode of the third reset transistor T8A is connected to control node A1, and the gate of the third reset transistor T8A receives the third reset control signal Vi3; the first electrode of the first light-emitting transistor T5A is connected to the high-level source VDD, the second electrode of the first light-emitting transistor T5A is connected to control node A1, and the gate of the first light-emitting transistor T5A receives the light-emitting control signal EM; the first electrode of the second light-emitting transistor T6A is connected to the second node B1, the second electrode of the second light-emitting transistor T6A is connected to the anode of the light-emitting device, and the gate of the second light-emitting transistor T6A receives the light-emitting control signal EM; one end of the boost capacitor Cboost is connected to control node Q1, and the other end of the boost capacitor Cboost is connected to the gate of the switching transistor T2A; one end of the control capacitor Cst2 is connected to control node Q1, and the other end of the control capacitor Cst2 is connected to the high-level source VDD; the cathode of the light-emitting device is connected to the low-level source VSS.

[0043] In this embodiment, the high-level source VDD is used to provide a constant high voltage to the pixel driving circuit 300, and the low-level source VSS is used to provide a constant low voltage to the pixel driving circuit 300.

[0044] In this embodiment, the switching transistor T2A, driving transistor T1A, second reset transistor T7A, third reset transistor T8A, first light-emitting transistor T5A, and second light-emitting transistor T6A can be either P-type transistors or N-type transistors, and the compensation transistor T3A and first reset transistor T4A can be either P-type transistors or N-type transistors. This application uses the example of switching transistor T2A, driving transistor T1A, second reset transistor T7A, third reset transistor T8A, first light-emitting transistor T5A, and second light-emitting transistor T6A being P-type transistors, and compensation transistor T3A and first reset transistor T4A being N-type transistors for illustration.

[0045] In this embodiment, the capacitance of the boost capacitor Cboost is smaller than that of the control capacitor Cst2. In this embodiment, the control capacitor Cst2 is mainly used to maintain the stability of the potential of the third node Q1; therefore, the capacitance of the control capacitor Cst2 is relatively large, for example, the capacitance value of the control capacitor Cst2 can range from 45fF to 55fF, and the capacitance value of the boost capacitor Cboost can range from 5fF to 15fF.

[0046] In this embodiment, the first electrode can be either the source or the drain, and the second electrode can be either the source or the drain.

[0047] Please refer to Figures 3 and 4. The gate driving circuit 200 is disposed in the non-display area NA, and the gate driving circuit 200 can be disposed on both sides of the display area AA. The gate driving circuit 200 can include N cascaded gate driving units 200a. The N gate driving units 200a can be arranged along the first direction X. The structure of the gate driving unit 200a can be various. For example, in the structure of Figure 3, the non-display area NA can include a plurality of first gate circuits 210 arranged and cascaded along the first direction X, a plurality of second gate circuits 220 arranged and cascaded along the first direction X, a plurality of third gate circuits 230 arranged and cascaded along the first direction X, a plurality of fourth gate circuits 240 arranged and cascaded along the first direction X, and a plurality of fifth gate circuits 250 arranged and cascaded along the first direction X.

[0048] In this embodiment, the second direction Y is parallel to the scan line of the display panel 100, and the angle between the first direction X and the second direction Y is greater than 0° and less than or equal to 90°. The scan line can be a gate signal transmission line, such as at least one of a compensation control line, a first reset control line, a switch control line, a second reset control line, or a light emission control line.

[0049] Please refer to Figures 3 and 4. The first gate circuit 210 is located on both sides of the display area AA. The first gate circuit 210 is used to transmit the compensation control signal Nscan1. The first gate circuit 210 is connected to two compensation control lines. That is, the first gate circuit 210 is used to output the compensation control signal Nscan1 to the two-row pixel driving circuit 300. In other words, the two-row pixel driving circuit 300 requires a first gate circuit 210.

[0050] Please refer to Figures 3 and 4. The second gate circuit 220 is disposed on both sides of the display area AA. The second gate circuit 220 and the first gate circuit 210 can be arranged along the second direction Y or the first direction X. The second gate circuit 220 is used to transmit the first reset control signal Nscan2. One second gate circuit 220 is connected to two first reset control lines. At the same time, the first-level second gate circuit 220 of this application is used to output the first reset control signal Nscan2 to the two-row pixel driving circuit 300, that is, the two-row pixel driving circuit 300 requires a first-level second gate circuit 220.

[0051] It should be noted that the second gate circuit 220 and the first gate circuit 210 in Figures 3 and 4 are illustrated by alternating arrangement along the first direction X. In actual cases, they can be adjusted according to the wiring space of the display panel. For example, the first gate circuit 210 can be arranged in a single column along the first direction X, and the second gate circuit 220 can be arranged in a single column along the first direction X.

[0052] Please refer to Figures 3 and 4. The fifth gate circuit 250 is located on both sides of the display area AA, and between the display area AA and the first gate circuit 210, and between the display area AA and the second gate circuit 220. The fifth gate circuit 250 is used to transmit the switch control signal Pscan1. The fifth gate circuit 250 is connected to two switch control lines. At the same time, the first-level fifth gate circuit 250 of this application is used to output the switch control signal Pscan1 to the row pixel driving circuit 300, that is, the row pixel driving circuit 300 requires a first-level fifth gate circuit 250.

[0053] It should be noted that, as shown in Figures 3 and 4, each display area AA is provided with a first gate circuit 210, a second gate circuit 220 and a fifth gate circuit 250 on both sides, that is, the first gate circuit 210, the second gate circuit 220 and the fifth gate circuit 250 of this application are driven simultaneously on both sides.

[0054] Please refer to Figures 3 and 4. The third gate circuit 230 is located on the first side of the display area AA, and the third gate circuit 230 is located on the side of the first gate circuit 210 away from the display area AA. The third gate circuit 230 is used to transmit the second reset control signal Pscan2. The third gate circuit 230 is connected to two second reset control lines. At the same time, the first-level fourth gate circuit 240 of this application is used to output the compensation control signal Nscan1 to the two-row pixel driving circuit 300, that is, the two-row pixel driving circuit 300 requires a first-level third gate circuit 230.

[0055] Please refer to Figures 3 and 4. The fourth gate circuit 240 is located on the second side of the display area AA, and the fourth gate circuit 240 is located on the side of the first gate circuit 210 away from the display area AA. The fourth gate circuit 240 is used to transmit the light emission control signal EM. The fourth gate circuit 240 is connected to two light emission control lines. At the same time, the first-level fourth gate circuit 240 of this application is used to output the compensation control signal Nscan1 to the two-row pixel driving circuit 300, that is, the two-row pixel driving circuit 300 requires a first-level fourth gate circuit 240.

[0056] It should be noted that, in this application, only the third gate circuit 230 is provided on one side of the display area AA, and only the fourth gate circuit 240 is provided on the other side of the display area AA, that is, the third gate circuit 230 and the fourth gate circuit 240 are driven on one side only.

[0057] It should be noted that since the first reset signal Vi1, the second reset signal Vi2 and the third reset signal Vi3 are all constant voltages, they do not require the corresponding gate drive circuit 200 to control them, and can be directly connected to the corresponding constant voltage source.

[0058] In this embodiment, the first gate circuit 210, the second gate circuit 220, the third gate circuit 230, the fourth gate circuit 240, and the fifth gate circuit 250 of this application can be mTnC gate circuits. In the following embodiment, the structure of the gate driving unit 200a of this application will be described using the fifth gate circuit 250 as an example of 8T2C.

[0059] It should be noted that the difference between Figure 3 and Figure 4 is that the display panel in Figure 4 is equipped with an under-display camera area (CUP), while the display panel in Figure 3 is not equipped with an under-display camera area (CUP).

[0060] Referring to Figure 5, the gate drive unit 200a may include a receiving circuit 221 and an output circuit 222. The receiving circuit 221 and the output circuit 222 are arranged along the second direction Y. The receiving circuit 221 is used to receive the stage transmission signal generated by the upper gate drive circuit 200. The output circuit 222 is electrically connected to the receiving circuit 221 through the second node Q2 and the first node P2, and is used to output the control signal of this stage and the stage transmission signal of the next stage according to the signal of the second node Q2 and the signal of the first node P2.

[0061] Please refer to Figure 5. The output circuit 222 includes a second output transistor T7 and a first output transistor T6. The gate of the second output transistor T7 is electrically connected to the second node Q2, the drain of the second output transistor T7 is electrically connected to the high potential line VGH, and the source of the second output transistor T7 is electrically connected to the output terminal OUT in the gate drive circuit 200. The gate of the first output transistor T6 is electrically connected to the first node P2, the drain of the first output transistor T6 is electrically connected to the second type clock line CK, and the source of the first output transistor T6 is electrically connected to the output terminal OUT.

[0062] Please refer to Figure 5. The receiving circuit 221 includes a first node control module 221a and a second node control module 221b. The first output transistor T6 and the first node control module 221a are connected to the first node P2, and the second output transistor T7 and the second node control module 221b are connected to the second node Q2.

[0063] Please refer to Figure 5. The storage capacitor includes a first capacitor C1 and a second capacitor C2. The first capacitor C1 includes a first plate C1a and a second plate C1b. The first plate C1a is connected to the output terminal OUT in the gate drive circuit 200, and the second plate C1b is connected to the first node P2. The second capacitor C2 includes a third plate C2a and a fourth plate C2b. The third plate C2a is connected to the high potential line VGH, and the fourth plate C2b is connected to the second node Q2.

[0064] Please refer to Figure 5. The receiving circuit 221 includes a first transistor T1. The gate of the first transistor T1 is connected to the first type clock line XCK, the drain of the first transistor T1 is connected to the low potential line VGL, and the source of the first transistor T1 is connected to the second node Q2.

[0065] Please refer to Figure 5. The receiving circuit 221 includes a second transistor T2. The gate of the second transistor T2 is loaded with a first type clock line XCK. The drain of the second transistor T3 is connected to the initial signal line STV or the output terminal OUT of the previous stage gate driving unit 200a. The source of the second transistor T3 is connected to the third node N2.

[0066] Please refer to Figure 5. The receiving circuit 221 includes a third transistor T3. The gate of the third transistor T3 is connected to the third node N2, the drain of the third transistor T3 is connected to the first type clock line XCK, and the source of the third transistor T3 is connected to the second node Q2.

[0067] Please refer to Figure 5. The receiving circuit 221 includes a fourth transistor T4. The gate of the fourth transistor T4 is connected to the second type clock line CK. The drain of the fourth transistor T4 is connected to the source of the fifth transistor T5. The source of the fourth transistor T4 is connected to the third node N2.

[0068] Please refer to Figure 5. The receiving circuit 221 includes a fifth transistor T5. The gate of the fifth transistor T5 is connected to the second node Q2, and the drain of the fifth transistor T5 is connected to the high potential line VGH.

[0069] Please refer to Figure 5. The receiving circuit 221 includes an eighth transistor T8. The gate of the eighth transistor T8 is connected to the low potential line VGH, the drain of the eighth transistor T8 is connected to the third node N2, and the source of the eighth transistor T8 is connected to the first node P2.

[0070] It should be noted that the drain of the second transistor T2 is only connected to the initial signal line STV in the first stage. In the gate drive unit 200a after the second stage, the drain of the third transistor T3 is electrically connected to the output terminal OUT of the gate drive unit 200a of the previous stage.

[0071] It should be noted that the source and drain in the transistor described in this application are only different in name. As long as one is the output terminal and the other is the input terminal, it is sufficient. In this application, the source is described as the output terminal of the transistor and the drain is described as the input terminal of the transistor.

[0072] It should be noted that all transistors in the gate drive circuit 200 of this application can be N-type transistors or P-type transistors. In this embodiment, all transistors in the gate drive circuit 200 are described using P-type transistors as an example.

[0073] It should be noted that the first node control module 221a of this application may include the fourth transistor T4, the fifth transistor T5, and the eighth transistor T8, and the second node control module 221b may include the first transistor T1 and the third transistor T3; secondly, the second transistor T2 may also belong to the first node control module 221a.

[0074] It should be noted that since the first output transistor T6 is used to output the low level of the switch control signal Pscan1, the output load of the first output transistor T6 is greater than the output load of the second output transistor T7. In order to increase the output load of the first output transistor T6, this application can make the area of ​​the first output transistor T6 larger than the area of ​​the second output transistor T7, thereby improving the output load capacity of the first output transistor T6.

[0075] Referring to Figure 6, the display area AA and the non-display area NA of the display panel 100 may be provided with a substrate 110 and an array driving layer 120 disposed on the substrate 110. Within the display area AA, the display panel 100 may also be provided with a pixel definition layer (not shown) disposed on the array driving layer 120, a light-emitting device layer (not shown) disposed on the same layer as the pixel definition layer, and an encapsulation layer (not shown) disposed on the pixel definition layer. The following description mainly focuses on the film layer structure within the non-display area NA and the display area AA.

[0076] In this embodiment, the substrate 110 supports various layers disposed on the substrate 110. When the display panel 100 is a bottom-emitting light-emitting display device or a double-sided light-emitting display device, a transparent substrate is used. When the display panel 100 is a top-emitting light-emitting display device, a semi-transparent or opaque substrate, as well as a transparent substrate, can be used.

[0077] In this embodiment, the substrate 110 is used to support the various film layers disposed on the substrate 110. The substrate 110 may be made of an insulating material such as glass, quartz, or polymer resin. The substrate 110 may be a rigid substrate or a flexible substrate that can be bent, folded, rolled, etc. Examples of flexible materials used for flexible substrates include, but are not limited to, polyimide (PI).

[0078] In this embodiment, the substrate 110 may include a first flexible substrate 111, a first barrier layer 112, a second flexible substrate 113, and a second barrier layer 114 stacked together. The first flexible substrate 111 and the second flexible substrate 113 may be formed of the same material, such as polyimide, and the first barrier layer 112 and the second barrier layer 114 may be formed of an inorganic material, for example, including at least one of SiOx and SiNx.

[0079] Please refer to Figure 6. The array driving layer 120 may include multiple thin-film transistors. The thin-film transistors may be etch-block type, back-channel etch type, or classified into bottom-gate thin-film transistors, top-gate thin-film transistors, etc., according to the position of the gate and the active layer, or classified into N-type thin-film transistors and P-type thin-film transistors according to their performance. For example, the gate transistor in the non-display area AA may be a P-type thin-film transistor, and the pixel transistor in the display area AA may be an N-type thin-film transistor or a P-type thin-film transistor. Secondly, the thin-film transistors in Figure 6 do not represent the structural diagram of any transistor in Figure 2, but are only schematic diagrams of each film layer of the display panel 100 of this application.

[0080] Referring to Figure 6, the array driving layer 120 may include a barrier insulating layer BF disposed on the substrate 110, a light-shielding layer 121 embedded in the barrier insulating layer BF, a buffer layer 122 disposed on the barrier insulating layer BF, a first active layer 123 disposed on the buffer layer 122, a first insulating layer 124 disposed on the first active layer 123, a first gate layer 125 disposed on the first insulating layer 124, a second insulating layer 126 disposed on the first gate layer 125, and a second insulating layer 126 disposed on the second insulating layer 124. The second active layer 127 on the 26, the third insulating layer 128 disposed on the second active layer 127, the second gate layer 129 disposed on the third insulating layer 128, the fourth insulating layer 130 disposed on the second gate layer 129, the first source-drain layer 131 disposed on the fourth insulating layer 130, the first planarization layer 132 disposed on the first source-drain layer 131, the second source-drain layer 133 disposed on the first planarization layer 132, and the second planarization layer 134 disposed on the second source-drain layer 133.

[0081] Please refer to Figure 6. The light-shielding layer 121 is disposed on the second barrier layer 114. The light-shielding layer 121 is used to block external light from entering the thin film transistor from the bottom. The material of the light-shielding layer 121 can be made of black light-shielding material, such as black light-shielding metal or black organic material. In this application, the light-shielding layer 121 can be disposed only in the display area AA.

[0082] Please refer to Figure 6. The buffer layer 122 is disposed on the light-shielding layer 121. The buffer layer 122 is used to isolate the light-shielding layer 121 from the upper metal material. The material of the buffer layer 122 may be composed of a compound consisting of nitrogen, silicon and oxygen elements, such as a single layer of silicon oxide film or a stacked structure of silicon oxide and silicon nitride.

[0083] Please refer to Figure 6. The first active layer 123 is disposed on the buffer layer 122, and the second active layer 127 is disposed on the second insulating layer 126. In this application, the material of the first active layer 123 can be silicon semiconductor, such as low-temperature polycrystalline silicon, and the material of the second active layer 127 can be oxide semiconductor, such as metal oxide. Since the transistors in the gate driving unit 200a are all P-type transistors, metal oxide semiconductors are not disposed in the non-display area AA of this application. However, the pixel driving circuit 300 has N-type transistors and P-type transistors. Therefore, metal oxide semiconductors and low-temperature polycrystalline silicon semiconductors are disposed in the display area AA of this application.

[0084] Please refer to Figure 6. The first insulating layer 124, the second insulating layer 126, the third insulating layer 128, and the fourth insulating layer 130 are respectively disposed on the corresponding metal layer or semiconductor layer, and are disposed separately as different metal layers or semiconductor layers. The materials of the first insulating layer 124, the second insulating layer 126, the third insulating layer 128, and the fourth insulating layer 130 can be inorganic materials composed of at least two elements in silicon oxynitride or organic materials with planarity.

[0085] Please refer to Figure 6. The first gate layer 125 and the second gate layer 129 are respectively disposed on the corresponding insulating layers. The materials of the first gate layer 125 and the second gate layer 129 can be copper, molybdenum, or molybdenum-titanium alloy, etc.

[0086] Please refer to Figure 6. The first source-drain layer 131 is disposed on the fourth insulating layer 130, and the second source-drain layer 133 is disposed on the first planarization layer 132. The materials of the first source-drain layer 131 and the second source-drain layer 133 can be copper or molybdenum-titanium alloy, copper or titanium, etc.

[0087] Please refer to Figure 6. The first planarization layer 132 and the second planarization layer 134 are laid in a whole layer to ensure the flatness of the film layer of the array driving layer 120. The materials of the first planarization layer 132 and the second planarization layer 134 can be inorganic materials composed of silicon oxynitride or organic materials with flatness.

[0088] As shown in Figure 6, the two plates of the storage capacitor in the non-display area AA of this application are respectively made of the material of the first gate layer 125 and the material of the second active layer 127. For example, the first plate C1a and the third plate C2a are located in the second active layer 127, and the second plate C1b and the fourth plate C2b are located in the first gate layer 125. The metal layer and an insulating layer between the original second active layer 127 and the first gate layer 125 are removed, reducing the number of film layers in the display panel 100, simplifying the manufacturing process of the display panel 100, and reducing the cost of the display panel 100.

[0089] It should be noted that when all transistors in the gate drive circuit 200 of this embodiment are N-type transistors, the active portions of all transistors in the gate drive circuit 200 can be set using the second active layer 127, and the materials of the first active layer 123 and the first gate layer 125 can be used to form the two plates of the storage capacitor.

[0090] The structure of each film layer in the gate driving unit 200a is described below based on the stack-up diagram. In Figures 7 to 17, each figure shows the structure of the corresponding film layer in the two-stage gate driving unit 200a. The following embodiment uses the film layer of the first-stage gate driving unit 200a in the figure as an example for illustration.

[0091] Please refer to Figure 7, which is a film layer diagram of the first gate layer 125 in the display panel 100 of this application.

[0092] In this embodiment, the first gate layer 125 includes a first gate T6G of the first output transistor T6 and a second gate T7G of the second output transistor T7, and the first gate T6G and the second gate T7G are arranged in the first direction X.

[0093] In this embodiment, the first gate T6G includes a first main gate T6Ga and at least two first branch gates T6Gb connected to the first main gate T6Ga. The first main gate T6Ga extends along a first direction X, and the at least two first branch gates T6Gb extend along a second direction Y. The at least two first branch gates T6Gb are spaced apart in the first direction X. The first main gate T6Ga and part of the first branch gates T6Gb are multiplexed as the second electrode C1b. For example, in the structure of FIG7, the first gate T6G includes one first main gate T6Ga and two first branch gates T6Gb. The first main gate T6Ga is located on the side of the first branch gates T6Gb close to the display area AA.

[0094] In this embodiment, the second gate T7G includes a second main gate T7Ga and a second branch gate T7Gb connected to the second main gate T7Ga. The second branch gate T7Gb extends along the second direction Y. The second main gate T7Ga and at most a portion of the second branch gate T7Gb are multiplexed as the fourth electrode plate C2b. For example, in the structure of FIG7, the second gate T7G includes one second main gate T7Ga and one second branch gate T7Gb. The second main gate T7Ga is disposed on the side of the second branch gate T7Gb close to the display area AA.

[0095] In this embodiment, the length and number of the strip-shaped branch gates in the second direction Y are positively correlated with the output load of the output transistor. Therefore, in order to improve the driving capability of the first output transistor T6 and the second output transistor T7, this application sets the first output transistor T6 and the second output transistor T7 as separately arranged strip-shaped branch gates. Each strip-shaped branch gate bears the load of the corresponding transistor. The strip-shaped branch electrode corresponds to the channel of the active part in the corresponding transistor. The two adjacent strip-shaped branch gates correspond to the source and drain of the upper layer. The composite electric field formed by multiple separately arranged strip-shaped branch gates can improve the driving capability of the transistor.

[0096] In this embodiment, in the first direction X, the spacing between two adjacent first branch gates T6Gb can be equal to the spacing between adjacent first branch gates T6Gb and second branch gates T7Gb.

[0097] In this embodiment, since the output load of the second output transistor T7 is less than the output load of the first output transistor T6, the area of ​​the first gate T6G can be larger than the area of ​​the second gate T7G to improve the driving capability of the gate in the first output transistor T6.

[0098] Please refer to Figure 7. The first gate layer 125 also includes the gate T1G of the first transistor T1, the gate T2G of the second transistor T2, the gate T3G of the third transistor T3, the gate T4G of the fourth transistor T4, the gate T5G of the fifth transistor T5, and the gate T8G of the eighth transistor T8.

[0099] Please refer to Figure 7. The gates T1G of the first transistor T1, T2G of the second transistor T2, T3G of the third transistor T3, T4G of the fourth transistor T4, T5G of the fifth transistor T5, and T8G of the eighth transistor T8 can all be elongated structures extending along the second direction Y.

[0100] Please refer to Figure 7. The gate T1G of the first transistor T1 is connected to the gate T2G of the second transistor T2. The gate of the fifth transistor T5 and the end of the second gate T7G away from the display area AA are connected. The gate T1G of the first transistor T1 is located away from the display area AA. The gate T2G of the second transistor T2 is located between the gate T1G and the second gate T2G of the first transistor T1.

[0101] Please refer to Figure 7. The gate T4G of the fourth transistor T4 is located at the end of the first gate T6G that is away from the display area AA. The gate T3G of the third transistor T3 and the gate T8G of the eighth transistor T8 are arranged in the first direction X. The gate T3G of the third transistor T3 is located close to the gate T1G of the first transistor T1, and the gate T8G of the eighth transistor T8 is located away from the gate T2G of the second transistor T2.

[0102] Referring to Figure 7, the first gate layer 125 also includes a first connection line L1 and a second connection line L2. One end of the first connection line L1 is disposed near the gate T1G of the first transistor T1 and away from the gate T2G of the second transistor T2. The other end of the first connection line L1 overlaps with the first type clock line XCK and is electrically connected to the first type clock line XCK through a via. One end of the second connection line L2 is connected to the gate T4G of the fourth transistor T4 and away from the first output transistor T6. The other end of the second connection line L2 overlaps with the second type clock line CK and is connected to the second type clock line CK through a via.

[0103] Please refer to Figures 8 and 9. Figure 8 is a film layer diagram of the first active layer 123 in the display panel 100 of this application, and Figure 9 is a film layer stack diagram of the first active layer 123 and the first gate layer 125 in the display panel 100 of this application.

[0104] In this embodiment, the first active layer 123 includes a first active portion T6A of the first output transistor T6 and a second active portion T7A of the second output transistor T7. Both the first active portion T6A and the second active portion T7A extend along the first direction X and are connected to each other. The first active portion T6A and the first branch gate T6Gb partially overlap, and the second active portion T7A and the second branch gate T7Gb partially overlap. The overlapping portion of the first active portion T6A and the first branch gate T6Gb forms the channel of the first output transistor T6, and the overlapping portion of the second active portion T7A and the second branch gate T7Gb forms the channel of the second output transistor T7.

[0105] Since the first output transistor T6 is used to control the low-level output to quickly turn on the pixel transistors in the display area AA, the first output transistor T6 needs to have a stronger output capability. Referring to Figures 8 and 9, in the second direction Y, the width of the first active part T6A is greater than the width of the second active part T7A. The increase in the width of the first active part T6A increases the channel width of the first active part T6A, thereby improving the driving capability of the first output transistor T6.

[0106] It should be noted that both the first active part T6A and the second active part T7A include two separately disposed sub-parts. The separate disposal of the two sub-parts can reduce the size of the first active part T6A and the second active part T7A in the second direction Y, thus avoiding the technical problem of electrostatic concentration in the active part.

[0107] In this embodiment, the first active layer 123 further includes an active portion T1A of the first transistor T1, an active portion T2A of the second transistor T2, an active portion T3A of the third transistor T3, an active portion T4A of the fourth transistor T4, an active portion T5A of the fifth transistor T5, and an active portion T8A of the eighth transistor T8. All of the above active portions can be elongated structures extending along the first direction X.

[0108] In this embodiment, the first active layer 123 further includes a third connecting line L3 and a fourth connecting line L4. Both the third connecting line L3 and the fourth connecting line L4 are elongated structures extending along the second direction Y. The active portion T5A of the fifth transistor T5 is connected to the end of the second active portion T7A away from the first active portion T6A through the third connecting line L3. One end of the fourth connecting line L4 is connected to the end of the active portion T5A of the fifth transistor T5 away from the third connecting line L3, and one end of the fourth connecting line L4 is connected to the active portion T4A of the fourth transistor T4.

[0109] It should be noted that, in order to improve the wiring space of this application, the conductor portions located in the first active layer 123 and on both sides of the channel in some transistors of this application are reused as the source or drain of the corresponding transistor, without the need to separately set the source or drain of the corresponding transistor in the first source-drain layer 131, as detailed below.

[0110] Please refer to Figure 9. The overlapping portion of the active part T1A and the gate T1G of the first transistor T1 is the channel of the first transistor T1, and the two sides of the channel of the first transistor T1 are multiplexed as the source T1S and the drain T1D of the first transistor T1.

[0111] Referring to Figure 9, the overlapping portion of the active portion T2A and the gate T2G of the second transistor T2 forms the channel of the second transistor T2, and the two sides of the channel of the second transistor T2 are multiplexed as the source T2S and drain T2D of the second transistor T2. Furthermore, the active portion T2A of the second transistor T2 includes at least two connected active branches T2Aa, which are arranged side-by-side along the second direction Y. The gate T2G of the second transistor T2 overlaps with both of the at least two active branches T2Aa. Therefore, the second transistor T2 has two spaced-apart channel portions, meaning that the second transistor T2 can be composed of two transistors connected in series. The arrangement of the two active branches T2Aa increases the width of the channel portion and reduces the leakage current of the second transistor T2.

[0112] Please refer to Figure 9. The overlapping portion of the active part T3A and the gate T3G of the third transistor T3 is the channel of the third transistor T3, and the two sides of the channel of the third transistor T3 are multiplexed as the source T3S and the drain T3D of the third transistor T3.

[0113] Please refer to Figure 9. The overlapping portion of the active part T4A and the gate T4G of the fourth transistor T4 is the channel of the fourth transistor T4, and the two sides of the channel of the fourth transistor T4 are multiplexed as the source T4S and the drain T4D of the fourth transistor T4.

[0114] Please refer to Figure 9. The overlapping portion of the active part T5A and the fifth gate T5G of the fifth transistor T5 is the channel of the fifth transistor T5, and the two sides of the channel of the fifth transistor T5 are multiplexed as the source T5S and drain T5D of the fifth transistor T5. At the same time, since the fifth gate T5G of this application has two fifth branch gates T5Gb, the fifth transistor T5 has two spaced channel portions, that is, the fifth transistor T5 can be composed of two transistors connected in series. The provision of two fifth branch gates T5Gb increases the width of the channel portion and reduces the leakage current of the fifth transistor T5.

[0115] Please refer to Figure 9. The overlapping portion of the active part T8A and the gate T8G of the eighth transistor T8 is the channel of the eighth transistor T8, and the two sides of the channel of the eighth transistor T8 are multiplexed as the source T8S and the drain T8D of the eighth transistor T8.

[0116] It should be noted that the source T4S and source T5S share the same structure.

[0117] In this embodiment, since the second transistor T2 and the eighth transistor T8 are used to control the potential of the first node P2, in order to improve the accuracy of the potential of the first node P2, the width of the active portion T8A of the eighth transistor T8 and the active portion T2A of the second transistor T2 can be increased. For example, the width of the active portion T8A of the eighth transistor T8 and the active portion T2A of the second transistor T2 can both be greater than the width of the active portion T1A of the first transistor T1, the active portion T3A of the third transistor T3, the active portion T4A of the fourth transistor T4, and the active portion T5A of the fifth transistor T5, which are also included in the first active layer 123.

[0118] Please refer to Figures 10 and 11. Figure 10 is a film layer diagram of the second active layer 127 in the display panel 100 of this application, and Figure 11 is a film layer stack diagram of the first active layer 123, the second active layer 127 and the first gate layer 125 in the display panel 100 of this application.

[0119] In this embodiment, the second active layer 127 includes a first electrode C1a of the first capacitor C1 and a third electrode C2a of the second capacitor C2. The first electrode C1a and the second electrode C1b are at least partially overlapped, and the third electrode C2a and the fourth electrode C2b are at least partially overlapped.

[0120] Please refer to Figure 11. In order to increase the capacitance of the storage capacitor, this application makes a portion of the outer contour of the first plate C1a expand relative to the outer contour of the second plate C1b, and a portion of the outer contour of the third plate C2a expand relative to the outer contour of the fourth plate C2b, which is equivalent to increasing the area of ​​the first plate C1a and the third plate C2a as much as possible.

[0121] In this embodiment, since the stability of the potential of the first node P2 is related to the stability of the low level output by the first output transistor T6, in order to ensure the output load of the first output transistor T6, this application makes the capacitance of the first capacitor C1 greater than the capacitance of the second capacitor C2, that is, the overlapping area of ​​the first plate C1a and the second plate C1b is smaller than the overlapping area of ​​the third plate C2a and the fourth plate C2b.

[0122] In this embodiment, in order to increase the overlap area of ​​the first electrode C1a and the second electrode C1b, the first electrode C1a may include a first main electrode C1aa and at least two first branch electrodes C1ab connected to the first main electrode C1aa. The first main electrode C1aa extends along a first direction, and the at least two first branch electrodes C1ab extend along a second direction, and the multiple first branch electrodes C1ab are spaced apart in the first direction X. At the same time, the first main electrode C1aa at least partially overlaps with the first main gate T6Ga, and the first branch electrodes C1ab at least partially overlaps with the corresponding first branch gate T6Gb. The length of the first branch electrode C1ab is less than the length of the first branch gate T6Gb.

[0123] Please refer to Figures 12 and 13. Figure 12 is a film layer diagram of the second gate layer 129 in the display panel 100 of this application, and Figure 13 is a film layer stack diagram of the first active layer 123, the second active layer 127, the first gate layer 125 and the second gate layer 129 in the display panel 100 of this application.

[0124] In this embodiment, the second gate layer 129 includes a fifth connection line L5, which is a zigzag segment. One end of the fifth connection line L5 is connected to the drain T1D of the first transistor T1, and the other end of the fifth connection line L5 is connected to the gate T5G of the fifth transistor T5.

[0125] It should be noted that the structure of the fifth connecting line L5 in the attached figure is only one embodiment of this application, and it can be adaptively adjusted according to the corresponding wiring space.

[0126] Please refer to Figures 14 and 15. Figure 14 is a film layer diagram of the first source-drain layer 131 in the display panel 100 of this application, and Figure 15 is a film layer stack diagram of the first active layer 123, the second active layer 127, the first gate layer 125, the second gate layer 129 and the first source-drain layer 131 in the display panel 100 of this application.

[0127] In this embodiment, the display panel 100 further includes a first source-drain layer 131 disposed on the side of the second active layer 127 away from the first active layer 123. The first source-drain layer 131 includes a first source T6S and a first drain T6D of the first output transistor T6, and a second source T7S and a second drain T7D of the second output transistor T7.

[0128] In this embodiment, the first drain T6D includes a first branch drain T6Db, which extends along the second direction Y; for example, in the structures of FIG14 and FIG15, the first drain T6D includes one first branch drain T6Db.

[0129] In this embodiment, the first source T6S includes a first branch source T6Sb, which extends along the second direction Y. For example, in the structures of FIG14 and FIG15, the first source T6S includes two first branch sources T6Sb, and the two first branch sources T6Sb are disposed between one first branch drain T6Db.

[0130] Please refer to Figure 14. Two first branch sources T6Sb and one first branch drain T6Db are spaced apart in the first direction X, and two first branch gates T6Gb are disposed between corresponding adjacent first branch sources T6Sb and first branch drains T6Db.

[0131] In this embodiment, the second drain T7D includes a second branch drain T7Db, which extends along the second direction Y; for example, in the structures of FIG14 and FIG15, the second drain T7D includes one second branch drain T7Db.

[0132] In this embodiment, the second source T7S includes a second branch source T7Sb, which extends along the second direction Y; for example, in the structures of FIG14 and FIG15, the second source T7S includes one second branch source T7Sb.

[0133] Please refer to Figure 14. The second branch source T7Sb and the second branch drain T7Db are spaced apart in the first direction X, and a second branch gate T7Gb is disposed between the second branch source T7Sb and the second branch drain T7Db.

[0134] Please refer to Figures 14 and 15. Among the two first branch sources T6Sb, the first branch source T6Sb closest to the second output transistor T7 can be reused as the second branch source T7Sb.

[0135] Please refer to Figures 14 and 15. The first source-drain layer 131 also includes a source trunk 131a extending along the first direction X. Both first branch sources are connected to the source trunk 131a, and at least part of the source trunk 131a overlaps with the first capacitor C1. For example, the orthogonal projection of the source trunk 131a on the first capacitor C1 in the figures is located inside the first capacitor C1.

[0136] Please refer to Figure 15. The display panel 100 includes a plurality of first contact holes HL1 and a plurality of second contact holes HL2 disposed in the area where the first output transistor T6 is located. The first drain T6D passes through the plurality of first contact holes HL1 and is connected to the first active part T6A. The first source T6S passes through the plurality of second contact holes HL2 and is connected to the first active part T6A.

[0137] Please refer to Figure 15. The display panel 100 includes a plurality of third contact holes HL3 and a plurality of fourth contact holes HL4 disposed in the area where the second output transistor T7 is located. The second drain T7D is connected to the second active part T7A through the plurality of third contact holes HL3. The second source T7S is connected to the first active part T6A through the plurality of fourth contact holes HL4. Since the second source T7S is multiplexed as the first source T6S, the fourth contact hole HL4 in the area where the second source T7S is located can also be the second contact hole HL2.

[0138] In this embodiment, the first contact hole HL1, the second contact hole HL2, the third contact hole HL3, and the sixth contact hole HL5 penetrate the second insulating layer 126, the third insulating layer 128, the fourth insulating layer 130, and a portion of the first insulating layer 124.

[0139] Please refer to Figures 14 and 15. The first source-drain layer 131 includes a first transmission segment TS1. One end of the first transmission segment TS1 passes through a via and is connected to the low potential line VGL. The other end of the first transmission segment TS1 passes through a via and is connected to one end of the active portion T1A of the first transistor T1.

[0140] Please refer to Figures 14 and 15. The first source-drain layer 131 includes a second transmission segment TS2. One end of the second transmission segment TS2 passes through a via and is connected to the other end of the active portion T1A of the first transistor T1. The other end of the second transmission segment TS2 passes through a via and is connected to the end of the fifth connection line L5 away from the output circuit 222. The middle region of the second transmission segment TS2 has an extension towards the output circuit 222. This extension passes through a via and is connected to one end of the active portion T3A of the third transistor T3.

[0141] Please refer to Figures 14 and 15. The first source-drain layer 131 includes a third transmission segment TS3. One end of the third transmission segment TS3 passes through a via and is connected to the active portion T3A of the third transistor T3. The other end of the third transmission segment TS3 passes through a via and is connected to the gate T1G of the first transistor T1.

[0142] Please refer to Figures 14 and 15. The first source-drain layer 131 includes a fourth transmission segment TS4. One end of the fourth transmission segment TS4 passes through a via and is connected to the end of the gate T1G of the first transistor T1 away from the gate T2G of the second transistor T2. The other end of the fourth transmission segment TS4 passes through a via and is connected to the first connection line L1.

[0143] Please refer to Figures 14 and 15. The first source-drain layer 131 includes a fifth transmission segment TS5. One end of the fifth transmission segment TS5 passes through a via and is connected to the low potential line VGL. The other end of the fifth transmission segment TS5 passes through a via and is connected to the end of the gate T8G of the eighth transistor T8 away from the output circuit 222.

[0144] Please refer to Figures 14 and 15. The first source-drain layer 131 includes a sixth transmission segment TS6. One end of the sixth transmission segment TS6 passes through a via and is connected to the end of the gate T5G of the fifth transistor T5 away from the output circuit 222. The other end of the sixth transmission segment TS6 passes through a via and is connected to the other end of the fifth connection line L5.

[0145] Please refer to Figures 14 and 15. The first source-drain layer 131 includes a seventh transmission segment TS7. One end of the seventh transmission segment TS7 passes through a via and is connected to the end of the first drain T6D away from the display area AA. The other end of the seventh transmission segment TS7 passes through a via and is connected to the end of the gate T4G of the fourth transistor T4 near the output circuit 222.

[0146] Please refer to Figures 14 and 15. The first source-drain layer 131 includes an eighth transmission segment TS8. One end of the eighth transmission segment TS8 passes through a via and is connected to one end of an active branch T2Aa of the second transistor T2. The other end of the eighth transmission segment TS8 passes through a via and is connected to one end of the active portion T4A of the fourth transistor T4 away from the active portion T5A of the fifth transistor T5. The middle region of the eighth transmission segment TS8 has a vertical segment and a horizontal segment. The vertical segment passes through a via and is connected to the gate T3G of the third transistor T3. The horizontal segment passes through a via and is connected to one end of the active portion T8A of the eighth transistor T8.

[0147] Please refer to Figures 14 and 15. The first source-drain layer 131 includes a ninth transmission segment TS9. One end of the ninth transmission segment TS9 passes through a via and is connected to the other end of the active portion T8A of the eighth transistor T8. The other end of the ninth transmission segment TS9 passes through a via and is connected to the end of the first branch gate T6Gb of the first output transistor T6 away from the output circuit 222.

[0148] Referring to Figures 14 and 15, the first source-drain layer 131 includes a tenth transmission segment TS10 and an eleventh transmission segment T11. In one gate driving unit 200a, the tenth transmission segment TS10 connects the second connection line L2 and a clock line, and the eleventh transmission segment T11 connects the first connection line L1 and another clock line. In another gate driving unit 200a, the tenth transmission segment TS10 connects the first connection line L1 and a clock line, and the eleventh transmission segment T11 connects the second connection line L2 and another clock line. Therefore, the positions of the tenth transmission segment TS10 and the eleventh transmission segment T11 differ in different gate driving units 200a.

[0149] Please refer to Figures 14 and 15. The first source-drain layer 131 includes a twelfth transmission segment TS12. One end of the twelfth transmission segment TS12 passes through a via and is connected to the end of the source T6Sb of the previous first branch away from the display area AA. The other end of the twelfth transmission segment TS12 passes through a via and is connected to one end of another active branch T2Aa of the second transistor T2.

[0150] Please refer to Figures 14 and 15. The first source-drain layer 131 includes a thirteenth transmission segment TS13, which extends along the first direction Y. One end of the thirteenth transmission segment TS13 is connected to the second drain T7D, and the other end of the thirteenth transmission segment TS13 is connected to the high potential line VGH.

[0151] Please refer to Figures 16 to 18. Figure 16 is a film layer diagram of the second source-drain layer 133 in the display panel 100 of this application. Figure 17 is a film layer stack diagram of the first active layer 123, the second active layer 127, the first gate layer 125, the second gate layer 129, the first source-drain layer 131, and the second source-drain layer 133 in the display panel 100 of this application. Figure 18 is a connection diagram of the four consecutive gate driving units 200a and the clock line in the display panel 100 of this application.

[0152] Please refer to Figures 16 to 18. The display panel 100 also includes a second source-drain layer 133 disposed on the side of the first source-drain layer 131 away from the second active layer 127. The second source-drain layer 133 includes a low-potential line VGL and a high-potential line VGH. The low-potential line VGL and the high-potential line VGH extend along the first direction X and are arranged along the second direction Y. The high-potential line VGH has an overlapping portion with the output circuit 222, and the low-potential line VGL has an overlapping portion with the receiving circuit 221. For example, the high-potential line VGH passes through a via and is connected to the thirteenth transmission segment TS13, and the low-potential line VGL passes through a via and is connected to the first transmission segment TS1.

[0153] In this embodiment, in the second direction Y, the width of the high potential line VGH can be greater than the width of the low potential line VGL.

[0154] Please refer to Figures 16 to 18. The second source-drain layer 133 also includes multiple clock lines disposed between the low potential line VGL and the high potential line VGH. The multiple clock lines extend along the first direction X and are arranged along the second direction Y. Some of the multiple clock lines overlap with the output circuit 222, and some of the multiple clock lines overlap with the receiving circuit 221.

[0155] Please refer to Figures 16 to 18. The multiple clock lines include a first clock line CK1, a second clock line CK2, a third clock line CK3, and a fourth clock line CK4, which are spaced apart. The first clock line CK1 overlaps with the output circuit 222, and the second clock line CK2, the third clock line CK3, and the fourth clock line CK4 overlap with the receiving circuit 221.

[0156] In this embodiment, each gate driving unit 200a is connected to two different clock lines among the first clock line CK1, the second clock line CK2, the third clock line CK3, and the fourth clock line CK4. That is, the first type of clock line XCK and the second type of clock line CK are two different ones among the above four lines.

[0157] For example, referring to Figure 18, the gate T4G of the fourth transistor T4 of the first gate driving unit 200a is connected to the first clock line CK1, and the gate T1G of the first transistor T1 is connected to the second clock line CK2; the gate T4G of the fourth transistor T4 of the second gate driving unit 200a is connected to the fourth clock line CK4, and the gate T1G of the first transistor T1 is connected to the first clock line CK1; the gate T4G of the fourth transistor T4 of the third gate driving unit 200a is connected to the third clock line CK3, and the gate T1G of the first transistor T1 is connected to the fourth clock line CK4; the gate T4G of the fourth transistor T4 of the fourth gate driving unit 200a is connected to the second clock line CK2, and the gate T1G of the first transistor T1 is connected to the third clock line CK3.

[0158] It should be noted that the two gate driving units 200a in Figure 17 of this application are the first gate driving unit 200a and the second gate driving unit 200a, respectively.

[0159] In this embodiment, in the second direction Y, the width of one clock line is greater than the width of the low potential line VGL, and the width of one clock line is less than the width of the high potential line VGH; at the same time, the width of each clock line can be equal.

[0160] In this embodiment, the second source-drain layer 133 further includes an initial signal line STV, which is located between the high potential line VGH and the first clock line CK1.

[0161] It should be noted that the initial signal line STV is only connected to the active part T2A of the second transistor T2 in the first-stage gate drive unit 200a. The active part T2A of the second transistor T2 in the second-stage and above gate drive units 200a is connected to the output terminal OUT of the previous stage gate drive unit 200a through the twelfth transmission segment TS12.

[0162] It should be noted that the signal line for transmitting signals in this application extends along the first direction X or the second direction Y, which only indicates that the signal line extends in that direction and does not represent that the signal line is a straight line in that direction. It can be an oblique line or multiple straight lines, etc.

[0163] This application also provides a display device, which includes the aforementioned display panel. The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0164] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0165] The technical solutions provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions in the embodiments of this application.

Claims

1. A display panel comprising a plurality of gate driving units, each gate driving unit comprising an output circuit, a receiving circuit, and a storage capacitor connected thereto, the output circuit comprising a first output transistor and a second output transistor connected thereto, the drain of the first output transistor being connected to a clock line, the drain of the second output transistor being connected to a high potential line, and the area of ​​the first output transistor being larger than the area of ​​the second output transistor. in, Both the output circuit and the receiving circuit include a gate transistor. The active portion of the gate transistor is located in the first active layer. One plate of the storage capacitor is located in the second active layer. The gate of the gate transistor and the other plate of the storage capacitor are located in the first gate layer. The first gate layer, the first active layer, and the second active layer are all disposed in different layers.

2. The display panel according to claim 1, wherein, The receiving circuit includes a first node control module, and the first output transistor and the first node control module are connected to the first node. The storage capacitor includes a first capacitor, which includes a first plate and a second plate. The first plate is connected to the source of the first output transistor, and the second plate is connected to the first node. The first plate is located in the second active layer, and the second plate is located in the first gate layer.

3. The display panel according to claim 2, wherein, The receiving circuit includes a second node control module, and the second output transistor and the second node control module are connected to the second node; The storage capacitor includes a second capacitor, which includes a third plate and a fourth plate. The third plate is connected to the high-potential line, and the fourth plate is connected to the second node. The third plate is located in the second active layer, and the fourth plate is located in the first gate layer.

4. The display panel according to claim 3, wherein, The overlapping area of ​​the first electrode plate and the second electrode plate is greater than the overlapping area of ​​the third electrode plate and the fourth electrode plate.

5. The display panel according to claim 3, wherein, The first gate layer includes a first gate of the first output transistor and a second gate of the second output transistor, wherein the first gate and the second gate are arranged in a first direction; The area of ​​the first gate is larger than the area of ​​the second gate.

6. The display panel according to claim 5, wherein, The first gate includes a first main gate and at least two first branch gates connected to the first main gate. The first main gate extends along the first direction, the first branch gates extend along the second direction, and the at least two first branch gates are spaced apart in the first direction. The second gate includes a second main gate and a second branch gate connected to the second main gate. The second main gate and the second branch gate extend along the second direction, and the first branch gate and the second branch gate are spaced apart in the first direction. The first main gate and the second branch gate are also spaced apart in the first direction. Wherein, the first main gate and a portion of the first branch gate are multiplexed as the second electrode plate, the second main gate and at most a portion of the second branch gate are multiplexed as the fourth electrode plate, the second direction is parallel to the scan line of the display panel, and the angle between the first direction and the second direction is greater than 0° and less than or equal to 90°.

7. The display panel according to claim 6, wherein, The first active layer includes a first active portion of the first output transistor and a second active portion of the second output transistor. Both the first active portion and the second active portion extend along the first direction and are connected to each other. The first active portion overlaps with multiple first branch gates, and the second active portion overlaps with multiple second branch gates.

8. The display panel according to claim 7, wherein, In the second direction, the width of the first active part is greater than the width of the second active part.

9. The display panel according to claim 6, wherein, The second active layer includes the first electrode plate of the first capacitor and the third electrode plate of the second capacitor; Wherein, at least a portion of the outer contour of the first electrode plate is wider than the outer contour of the second electrode plate, and at least a portion of the outer contour of the third electrode plate is wider than the outer contour of the fourth electrode plate.

10. The display panel according to claim 9, wherein, The second electrode plate includes a first main electrode plate and at least two first branch electrode plates connected to the first main electrode plate. The first main electrode plate extends along the first direction, and the at least two first branch electrode plates extend along the second direction. The plurality of first branch electrode plates are spaced apart in the first direction. Wherein, the first main plate overlaps at least partially with the first main gate, the first branch plate overlaps at least partially with the corresponding first branch gate, and the length of the first branch plate is less than the length of the first branch gate.

11. The display panel according to claim 6, wherein, The display panel further includes a first source / drain layer disposed on the side of the second active layer away from the first active layer, the first source / drain layer comprising: The first output transistor has a first source and a first drain, wherein the first drain includes a first branch drain and the first source includes a first branch source; The second output transistor has a second source and a second drain, the second drain includes a second branch drain, and the second source includes a second branch source. The first branch drain, the first branch source, the second branch drain, and the second branch drain all extend along the second direction and are arranged at intervals along the first direction. The first branch gate has a first branch drain and a first branch source on both sides of the second direction, and the second branch gate has a second branch drain and a second branch source on both sides of the second direction, and the second branch source near the first output transistor is multiplexed as the first branch source.

12. The display panel according to claim 11, wherein, in, The first source-drain layer further includes a source trunk extending along the first direction, the first branch source being connected to the source trunk, and at least a portion of the source trunk overlapping the first capacitor.

13. The display panel according to claim 11, wherein, The display panel further includes a second source-drain layer disposed on the side of the first source-drain layer away from the first active layer. The second source-drain layer includes a low-potential line and a high-potential line, which extend along the first direction and are arranged along the second direction. The high-potential line overlaps with the output circuit, and the low-potential line overlaps with the receiving circuit.

14. The display panel according to claim 13, wherein, In the second direction, the width of the high-potential line is greater than the width of the low-potential line.

15. The display panel according to claim 13, wherein, The second source-drain layer also includes a plurality of clock lines disposed between the low potential line and the high potential line, wherein the plurality of clock lines extend along the first direction and are arranged along the second direction; Some of the multiple clock lines overlap with the output circuit, and some of the multiple clock lines overlap with the receiving circuit.

16. The display panel according to claim 15, wherein, The multiple clock lines include a first clock line, a second clock line, a third clock line, and a fourth clock line arranged at intervals. The first clock line overlaps with the output circuit, and the second, third, and fourth clock lines overlap with the receiving circuit. Each of the gate driving units is connected to two different clock lines among the first, second, third, and fourth clock lines.

17. The display panel according to claim 15, wherein, In the second direction, the width of one of the clock lines is greater than the width of the low-potential line, and the width of one of the clock lines is less than the width of the high-potential line.

18. The display panel according to any one of claims 1 to 17, wherein, The receiving circuit includes: The first transistor has its gate connected to a first type of clock line, its drain connected to a low potential line, and its source connected to a second node. The second transistor has its gate connected to a first type of clock line, its drain connected to an initial signal line or the output of the gate driving unit of the previous stage, and its source connected to a third node. The third transistor has its gate connected to a third node, its drain connected to a first type of clock line, and its source connected to a second node. The fourth transistor has its gate connected to a second type of clock line, its drain connected to the source of a fifth transistor, and its source connected to a third node. The fifth transistor has its gate connected to the second node and its drain connected to the high potential line. The eighth transistor has its gate connected to a low potential line, its drain connected to a third node, and its source connected to a first node. The drain of the first output transistor is connected to the second type of clock line.

19. The display panel according to claim 18, wherein, The first gate layer of the display panel includes the gate of the second transistor, the first active layer of the display panel includes the active portion of the second transistor, and the gate of the second transistor extends along a second direction; The active portion of the second transistor includes at least two connected active branches, which are arranged side by side along the second direction, and the gate of the second transistor overlaps with both of the at least two active branches.

20. A display device, wherein, The display device includes a display panel as described in any one of claims 1 to 19.

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