Display panel

Abstract

Disclosed in the present application is a display panel. A gate driving unit of the display panel comprises an output circuit, a receiving circuit and a storage capacitor, which are connected to one another, wherein the output circuit and the receiving circuit each comprise a gate transistor, an active portion of at least one gate transistor is located in a first active layer, one electrode plate of the storage capacitor is located in a second active layer, a gate electrode of the gate transistor and the other electrode plate of the storage capacitor are located in a first gate layer, and the first gate layer, the first active layer and the second active layer are all arranged in different layers.

Description

Display panel Technical Field

[0001] This application relates to the field of displays, and more particularly to a display panel. Background Technology

[0002] Current OLED (Organic Light-Emitting Diode) display devices face increasingly stringent requirements for power consumption and screen-to-body ratio. To reduce power consumption and increase screen-to-body ratio, Low Temperature Polysilicon Oxide (LTPO) technology is employed. LTPO technology utilizes both low-temperature polysilicon thin-film transistors (LTPS) and oxide thin-film transistors (OTCs), allowing the driving circuit to combine the advantages of both technologies, thereby reducing power consumption and leakage current.

[0003] Currently, display devices using LTPO technology have a large number of film layers, which in turn requires a large number of photomasks, resulting in a more complex process and higher costs. Summary of the Invention

[0004] This application provides a display panel to solve the technical problem of complex manufacturing processes in existing display devices using LTPO technology.

[0005] To address the above issues, the technical solution provided in this application is as follows:

[0006] This application proposes a display panel including a plurality of gate driving units; each gate driving unit includes an output circuit, a receiving circuit and a storage capacitor connected to each other, both the output circuit and the receiving circuit include gate transistors, and the area of ​​the gate transistor in the output circuit is larger than the area of ​​the gate transistor in the receiving circuit.

[0007] In this configuration, the active portion of at least one of the gate transistors is located in the first active layer, one plate of the storage capacitor is located in the second active layer, the gate of the gate transistor and the other plate of the storage capacitor are located in the first gate layer, the first gate layer is disposed between the first active layer and the second active layer, and the materials of the first active layer and the second active layer are different. Attached Figure Description

[0008] Figure 1 is a simplified diagram of the first structure of the display panel of this application;

[0009] Figure 2 is an equivalent circuit diagram of the pixel driving circuit in the display panel of this application;

[0010] Figure 3 is a simplified diagram of the second structure of the display panel of this application;

[0011] Figure 4 is a simplified diagram of the third structure of the display panel of this application;

[0012] Figure 5 is an equivalent circuit diagram of the gate driving circuit in the display panel of this application;

[0013] Figure 6 is a schematic diagram of the film layer in the display panel of this application;

[0014] Figure 7 is a film layer diagram of the first gate layer in the display panel of this application.

[0015] Figure 8 is a film layer diagram of the first active layer in the display panel of this application.

[0016] Figure 9 is a stacked diagram of the first active layer and the first gate layer in the display panel of this application.

[0017] Figure 10 is a film diagram of the second active layer in the display panel of this application.

[0018] Figure 11 is a stacked diagram of the first active layer, the second active layer, and the first gate layer in the display panel of this application.

[0019] Figure 12 is a film layer diagram of the second gate layer in the display panel of this application.

[0020] Figure 13 is a stacked diagram of the first active layer, the second active layer, the first gate layer and the second gate layer in the display panel of this application.

[0021] Figure 14 is a film diagram of the first source and drain layer in the display panel of this application.

[0022] Figure 15 is a stacked diagram of the first active layer, second active layer, first gate layer, second gate layer and first source / drain layer in the display panel of this application.

[0023] Figure 16 is a film diagram of the second source / drain layer in the display panel of this application.

[0024] Figure 17 is a stacked diagram of the first active layer, second active layer, first gate layer, second gate layer, first source-drain layer and second source-drain layer in the display panel of this application. Embodiments of the present invention

[0025] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application. Furthermore, it should be understood that the specific embodiments described herein are only for illustration and explanation of this application and are not intended to limit this application.

[0026] In the description of this application, it should be understood that the terms "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0027] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, features defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, and "at least one" can mean one, two, or more, unless otherwise explicitly specified.

[0028] Please refer to Figures 1 to 17. This application provides a display panel 100, which includes a display area AA and a non-display area NA disposed on one side of the display area AA.

[0029] In this embodiment, the display area AA includes a pixel driving circuit 300 having multiple pixel transistors, the multiple pixel transistors including silicon semiconductor transistors and oxide semiconductor transistors, the active portion of the silicon semiconductor transistor is located in the first active layer 123, and the active portion of the oxide semiconductor transistor is located in the second active layer 127.

[0030] In this embodiment, the non-display area NA is located on one side of the display area AA. The non-display area NA includes a gate driving circuit 200 having multiple cascaded gate driving units 200a. Each gate driving unit 200a includes multiple gate transistors and a storage capacitor connected to the gate transistors.

[0031] In this embodiment, the active portion of the gate transistor is located in the first active layer 123, and one plate of the storage capacitor is located in the second active layer 127.

[0032] In some embodiments of this application, the storage capacitor of the gate driving unit 200a is usually composed of two layers of metal material, which results in a large number of film layers in the display panel 100, thereby increasing the number of photomasks, leading to a more complex process and higher cost. However, this application uses the material of the first active layer 123 to set the active part of the gate transistor and the material of the second active layer 127 to set one electrode of the storage capacitor, so that the one electrode of the storage capacitor is replaced by an active layer material instead of a metal material, removing the metal layer used to prepare the one electrode of the storage capacitor, reducing the number of film layers in the display panel 100, and simplifying the manufacturing process of the display panel 100.

[0033] In this embodiment, the gate driving unit 200a further includes an output circuit 222 and a receiving circuit 221 connected to each other. The area of ​​the gate transistor in the output circuit 222 is larger than the area of ​​the gate transistor in the receiving circuit 221. Since the output circuit 222 is used to transmit control signals to the display area AA, and the receiving circuit 221 is used to transmit signals in the gate driving unit 200a at this level, the load of the gate transistor in the output circuit 222 is greater than the load of the gate transistor in the receiving circuit 221. In order to ensure the output load of the output circuit 222, this application makes the area of ​​the gate transistor in the output circuit 222 larger than the area of ​​the gate transistor in the receiving circuit 221, thereby improving the transmission capability of the output circuit 222.

[0034] It should be noted that the silicon semiconductor transistor in this application is a P-type transistor, and the oxide semiconductor transistor is an N-type transistor.

[0035] It should be noted that the pixel transistor in this application is the transistor constituting the pixel driving circuit 300, and the gate transistor is the transistor constituting the gate driving circuit 200.

[0036] The technical solution of this application will now be described in conjunction with specific embodiments.

[0037] Referring to Figure 1, the display panel 100 includes a display area AA and a non-display area NA adjacent to the display area AA. The display area AA is located within the display area AA. Optionally, the non-display area NA surrounds the display area AA, so that the display area AA is enclosed by the non-display area NA. The display area AA is the area within the display panel 100 used for display functions, and it contains multiple display units that perform these functions. The non-display area NA may be a border area of ​​the display panel 100, and it may contain functional components that assist the display units within the display area AA in performing their display functions.

[0038] Please refer to Figure 1. A bonding terminal 400 is provided on the lower side of the display area AA. The bonding terminal 400 can be connected to an external circuit. The bonding terminal 400 transmits the signals input from the external circuit to the data traces, thereby driving the display panel 100 to display the image. For example, the bonding terminal 400 can be bonded to a chip or a flip-chip film to provide power and drive signals to the display panel 100.

[0039] In this embodiment, multiple light-emitting devices (LEDs) and pixel driving circuits 300 for driving the LEDs can be arrayed in the display area AA. The pixel driving circuit 300 can be a 7T1C, 7T2C, 8T2C, 8T3C, 8T4C, etc. This application does not impose specific limitations. The following description uses an 8T2C pixel driving circuit 300 as an example.

[0040] Referring to Figure 2, the pixel driving circuit 300 may include a switching transistor T2A, a driving transistor T1A, a compensation transistor T3A, a first reset transistor T4A, a second reset transistor T7A, a third reset transistor T8A, a first light-emitting transistor T5A, a second light-emitting transistor T6A, a boost capacitor Cboost, and a control capacitor Cst2.

[0041] Referring to Figure 2, the first electrode of switching transistor T2A is connected to the data signal line Data, the second electrode of switching transistor T2A is connected to control node A1, and the gate of switching transistor T2A receives the switching control signal Pscan1; the first electrode of driving transistor T1A is connected to control node A1, the second electrode of driving transistor T1A is connected to control node B1, and the gate of driving transistor T1A is connected to control node Q1; the first electrode of compensation transistor T3A is connected to control node Q1, the second electrode of compensation transistor T3A is connected to control node B1, and the gate of compensation transistor T3A receives the compensation control signal Nscan1; the first electrode of the first reset transistor T4A receives the first reset signal Vi1, the second electrode of the first reset transistor T4A is connected to control node Q1, and the gate of the first reset transistor T4A receives the first reset control signal Nscan2; the first electrode of the second reset transistor T7A is connected to the second reset signal Vi2, and the second electrode of the second reset transistor T7A is connected to the anode of the light-emitting device. The gate of transistor 7A receives the second reset control signal Pscan2; the first electrode of the third reset transistor T8A receives the third reset signal Vi3, the second electrode of the third reset transistor T8A is connected to control node A1, and the gate of the third reset transistor T8A receives the third reset control signal Vi3; the first electrode of the first light-emitting transistor T5A is connected to the high-level source VDD, the second electrode of the first light-emitting transistor T5A is connected to control node A1, and the gate of the first light-emitting transistor T5A receives the light-emitting control signal EM; the first electrode of the second light-emitting transistor T6A is connected to the second node B1, the second electrode of the second light-emitting transistor T6A is connected to the anode of the light-emitting device, and the gate of the second light-emitting transistor T6A receives the light-emitting control signal EM; one end of the boost capacitor Cboost is connected to control node Q1, and the other end of the boost capacitor Cboost is connected to the gate of the switching transistor T2A; one end of the control capacitor Cst2 is connected to control node Q1, and the other end of the control capacitor Cst2 is connected to the high-level source VDD; the cathode of the light-emitting device is connected to the low-level source VSS.

[0042] In this embodiment, the high-level source VDD is used to provide a constant high voltage to the pixel driving circuit 300, and the low-level source VSS is used to provide a constant low voltage to the pixel driving circuit 300.

[0043] In this embodiment, the switching transistor T2A, driving transistor T1A, second reset transistor T7A, third reset transistor T8A, first light-emitting transistor T5A, and second light-emitting transistor T6A can be either P-type transistors or N-type transistors, and the compensation transistor T3A and first reset transistor T4A can be either P-type transistors or N-type transistors. This application uses the example of switching transistor T2A, driving transistor T1A, second reset transistor T7A, third reset transistor T8A, first light-emitting transistor T5A, and second light-emitting transistor T6A being P-type transistors, and compensation transistor T3A and first reset transistor T4A being N-type transistors for illustration.

[0044] In this embodiment, the capacitance of the boost capacitor Cboost is smaller than that of the control capacitor Cst2. In this embodiment, the control capacitor Cst2 is mainly used to maintain the stability of the potential of the third node Q1; therefore, the capacitance of the control capacitor Cst2 is relatively large, for example, the capacitance value of the control capacitor Cst2 can range from 45fF to 55fF, and the capacitance value of the boost capacitor Cboost can range from 5fF to 15fF.

[0045] In this embodiment, the first electrode can be either the source or the drain, and the second electrode can be either the source or the drain.

[0046] Please refer to Figures 3 and 4. The gate driving circuit 200 is disposed in the non-display area NA, and the gate driving circuit 200 can be disposed on both sides of the display area AA. The gate driving circuit 200 can include N cascaded gate driving units 200a. The N gate driving units 200a can be arranged along the first direction X. The structure of the gate driving unit 200a can be various. For example, in the structure of Figure 3, the non-display area NA can include a plurality of first gate circuits 210 arranged and cascaded along the first direction X, a plurality of second gate circuits 220 arranged and cascaded along the first direction X, a plurality of third gate circuits 230 arranged and cascaded along the first direction X, a plurality of fourth gate circuits 240 arranged and cascaded along the first direction X, and a plurality of fifth gate circuits 250 arranged and cascaded along the first direction X.

[0047] In this embodiment, the second direction Y is parallel to the scan line of the display panel 100, and the angle between the first direction X and the second direction Y is greater than 0° and less than or equal to 90°. The scan line can be a gate signal transmission line, such as at least one of a compensation control line, a first reset control line, a switch control line, a second reset control line, or a light emission control line.

[0048] Please refer to Figures 3 and 4. The first gate circuit 210 is located on both sides of the display area AA. The first gate circuit 210 is used to transmit the compensation control signal Nscan1. The first gate circuit 210 is connected to two compensation control lines. That is, the first gate circuit 210 is used to output the compensation control signal Nscan1 to the two-row pixel driving circuit 300. In other words, the two-row pixel driving circuit 300 requires a first gate circuit 210.

[0049] Please refer to Figures 3 and 4. The second gate circuit 220 is disposed on both sides of the display area AA. The second gate circuit 220 and the first gate circuit 210 can be arranged along the second direction Y or the first direction X. The second gate circuit 220 is used to transmit the first reset control signal Nscan2. One second gate circuit 220 is connected to two first reset control lines. At the same time, the first-level second gate circuit 220 of this application is used to output the first reset control signal Nscan2 to the two-row pixel driving circuit 300, that is, the two-row pixel driving circuit 300 requires a first-level second gate circuit 220.

[0050] It should be noted that the second gate circuit 220 and the first gate circuit 210 in Figures 3 and 4 are illustrated by alternating arrangement along the first direction X. In actual cases, they can be adjusted according to the wiring space of the display panel. For example, the first gate circuit 210 can be arranged in a single column along the first direction X, and the second gate circuit 220 can be arranged in a single column along the first direction X.

[0051] Please refer to Figures 3 and 4. The fifth gate circuit 250 is located on both sides of the display area AA, and between the display area AA and the first gate circuit 210, and between the display area AA and the second gate circuit 220. The fifth gate circuit 250 is used to transmit the switch control signal Pscan1. The fifth gate circuit 250 is connected to two switch control lines. At the same time, the first-level fifth gate circuit 250 of this application is used to output the switch control signal Pscan1 to the row pixel driving circuit 300, that is, the row pixel driving circuit 300 requires a first-level fifth gate circuit 250.

[0052] It should be noted that, as shown in Figures 3 and 4, each display area AA is provided with a first gate circuit 210, a second gate circuit 220 and a fifth gate circuit 250 on both sides, that is, the first gate circuit 210, the second gate circuit 220 and the fifth gate circuit 250 of this application are driven simultaneously on both sides.

[0053] Please refer to Figures 3 and 4. The third gate circuit 230 is located on the first side of the display area AA, and the third gate circuit 230 is located on the side of the first gate circuit 210 away from the display area AA. The third gate circuit 230 is used to transmit the second reset control signal Pscan2. The third gate circuit 230 is connected to two second reset control lines. At the same time, the first-level fourth gate circuit 240 of this application is used to output the compensation control signal Nscan1 to the two-row pixel driving circuit 300, that is, the two-row pixel driving circuit 300 requires a first-level third gate circuit 230.

[0054] Please refer to Figures 3 and 4. The fourth gate circuit 240 is located on the second side of the display area AA, and the fourth gate circuit 240 is located on the side of the first gate circuit 210 away from the display area AA. The fourth gate circuit 240 is used to transmit the light emission control signal EM. The fourth gate circuit 240 is connected to two light emission control lines. At the same time, the first-level fourth gate circuit 240 of this application is used to output the compensation control signal Nscan1 to the two-row pixel driving circuit 300, that is, the two-row pixel driving circuit 300 requires a first-level fourth gate circuit 240.

[0055] It should be noted that, in this application, only the third gate circuit 230 is provided on one side of the display area AA, and only the fourth gate circuit 240 is provided on the other side of the display area AA, that is, the third gate circuit 230 and the fourth gate circuit 240 are driven on one side only.

[0056] It should be noted that since the first reset signal Vi1, the second reset signal Vi2 and the third reset signal Vi3 are all constant voltages, they do not require the corresponding gate drive circuit 200 to control them, and can be directly connected to the corresponding constant voltage source.

[0057] In this embodiment, the first gate circuit 210, the second gate circuit 220, the third gate circuit 230, the fourth gate circuit 240, and the fifth gate circuit 250 of this application can be gate circuits of mTnC. In the following embodiment, the structure of the gate driving unit 200a of this application will be described using the third gate circuit 230 and the fourth gate circuit 240 as 13T3C as an example.

[0058] It should be noted that the difference between Figure 3 and Figure 4 is that the display panel in Figure 4 is equipped with an under-display camera area (CUP), while the display panel in Figure 3 is not equipped with an under-display camera area (CUP).

[0059] Referring to Figure 5, the gate drive unit 200a may include a receiving circuit 221 and an output circuit 222. The receiving circuit 221 and the output circuit 222 are arranged along the second direction Y. The receiving circuit 221 is used to receive the stage transmission signal generated by the upper gate drive circuit 200. The output circuit 222 is electrically connected to the receiving circuit 221 through the second node Q2 and the first node P2, and is used to output the control signal of this stage and the stage transmission signal of the next stage according to the signal of the second node Q2 and the signal of the first node P2.

[0060] Please refer to Figure 5. The output circuit 222 includes a second output transistor T10 and a first output transistor T9. The gate of the second output transistor T10 is electrically connected to the second node Q2, the drain of the second output transistor T10 is electrically connected to the high potential line VGH, and the source of the second output transistor T10 is electrically connected to the output terminal OUT in the gate drive circuit 200. The gate of the first output transistor T9 is electrically connected to the first node P2, the drain of the first output transistor T9 is electrically connected to the low potential line VGL, and the source of the first output transistor T9 is electrically connected to the output terminal OUT.

[0061] Please refer to Figure 5. The receiving circuit 221 includes a first node control module 221a and a second node control module 221b. The first output transistor T9 and the first node control module 221a are connected to the first node P2, and the second output transistor T10 and the second node control module 221b are connected to the second node Q2.

[0062] Please refer to Figure 5. The storage capacitors include a first capacitor C1, a second capacitor C2, and a third capacitor C3. The first capacitor C1 includes a first plate C1a and a second plate C1b, which are respectively connected to different internal nodes in the first node control module 221a. The second capacitor C2 includes a third plate C2a and a fourth plate C2b, which are respectively connected to different internal nodes in the second node control module 221b. The third capacitor C3 includes a fifth plate C3a and a sixth plate C3b, where the fifth plate C3a is connected to the second node Q2, and the sixth plate C3b is connected to the drain of the second output transistor T10.

[0063] Please refer to Figure 5. The receiving circuit 221 includes a third transistor T3. The gate of the third transistor T3 is loaded with the first clock line XCK. The drain of the third transistor T3 is connected to the initial signal line STV. The source of the third transistor T3 is connected to the control node N3.

[0064] Please refer to Figure 5. The receiving circuit 221 includes a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7. The gate of the fifth transistor T5 is electrically connected to the control node N3. The source of the fifth transistor T5 is loaded with the first clock line XCK. The gate of the fourth transistor T4 is loaded with the first clock line XCK. The drain of the fourth transistor T4 is loaded with the low potential line VGL. The source of the fourth transistor T4 is electrically connected to the control node N2. The source of the fifth transistor T5 is electrically connected to the control node N2. The gate of the sixth transistor T6 is electrically connected to the control node N1. The source of the sixth transistor T6 is electrically connected to the drain of the seventh transistor T7. The drain of the sixth transistor T6 and the gate of the seventh transistor T7 are both loaded with the second clock line CK. The source of the seventh transistor T7 is electrically connected to the second node Q2.

[0065] Please refer to Figure 5. The receiving circuit 221 includes a thirteenth transistor T13, a first capacitor C1, a first transistor T1, and a second transistor T2. The gate of the thirteenth transistor T13 is electrically connected to the control line Control to load a control signal. The drain of the thirteenth transistor T13 is loaded with a high potential line VGH. The source of the thirteenth transistor T13 is electrically connected to the control node N3. The gate of the first transistor T1 is electrically connected to the control node N2. The drain of the first transistor T1 is loaded with a high potential line VGH. The source of the first transistor T1 is electrically connected to the source of the second transistor T2. The drain of the second transistor T2 is loaded with a second clock line CK. The gate of the second transistor T2 is electrically connected to the first node P2. The first capacitor C1 is electrically connected between the gate and source of the second transistor T2, and the gate of the second transistor T2 is connected to the first node P2.

[0066] Please refer to Figure 5. The receiving circuit 221 includes an eleventh transistor T11, a second capacitor C2, and a twelfth transistor T12. The output circuit 222 may also include a third capacitor C3 electrically connected between the gate and drain of the tenth transistor T10. The gates of the eleventh transistor T11 and the twelfth transistor T12 can both be connected to the low potential line VGL. The drain and source of the eleventh transistor T11 are electrically connected to control node N2 and control node N1, respectively. The second capacitor C2 is electrically connected between the gate and source of the sixth transistor T6. The drain and source of the twelfth transistor T12 are electrically connected to control node N3 and first node P2, respectively.

[0067] Please refer to Figure 5. The receiving circuit 221 includes an eighth transistor T8. The gate of the eighth transistor T8 is connected to the control node N3, the drain of the eighth transistor T8 is connected to the high potential line VGH, and the source of the eighth transistor T8 is connected to the second node Q2.

[0068] It should be noted that the drain of the third transistor T3 is only connected to the initial signal line STV in the first stage. In the gate drive unit 200a after the second stage, the drain of the third transistor T3 is electrically connected to the output terminal OUT of the gate drive unit 200a of the previous stage.

[0069] It should be noted that the source and drain in the transistor described in this application are only different in name. As long as one is the output terminal and the other is the input terminal, it is sufficient. In this application, the source is described as the output terminal of the transistor and the drain is described as the input terminal of the transistor.

[0070] It should be noted that all transistors in the gate drive circuit 200 of this application can be N-type transistors or P-type transistors. In this embodiment, all transistors in the gate drive circuit 200 are described using P-type transistors as an example.

[0071] It should be noted that the first node control module 221a of this application may include a first transistor T1 and a second transistor T2, and the second node control module 221b may include a sixth transistor T6 and a seventh transistor T7; or, the first node control module 221a of this application may include a first transistor T1, a second transistor T2 and a twelfth transistor T12, and the second node control module 221b may include a sixth transistor T6, a seventh transistor T7 and an eleventh transistor T11.

[0072] Referring to Figure 6, the display area AA and the non-display area NA of the display panel 100 may be provided with a substrate 110 and an array driving layer 120 disposed on the substrate 110. Within the display area AA, the display panel 100 may also be provided with a pixel definition layer (not shown) disposed on the array driving layer 120, a light-emitting device layer (not shown) disposed on the same layer as the pixel definition layer, and an encapsulation layer (not shown) disposed on the pixel definition layer. The following description mainly focuses on the film layer structure within the non-display area NA and the display area AA.

[0073] In this embodiment, the substrate 110 supports various layers disposed on the substrate 110. When the display panel 100 is a bottom-emitting light-emitting display device or a double-sided light-emitting display device, a transparent substrate is used. When the display panel 100 is a top-emitting light-emitting display device, a semi-transparent or opaque substrate, as well as a transparent substrate, can be used.

[0074] In this embodiment, the substrate 110 is used to support the various film layers disposed on the substrate 110. The substrate 110 may be made of an insulating material such as glass, quartz, or polymer resin. The substrate 110 may be a rigid substrate or a flexible substrate that can be bent, folded, rolled, etc. Examples of flexible materials used for flexible substrates include, but are not limited to, polyimide (PI).

[0075] In this embodiment, the substrate 110 may include a first flexible substrate 111, a first barrier layer 112, a second flexible substrate 113, and a second barrier layer 114 stacked together. The first flexible substrate 111 and the second flexible substrate 113 may be formed of the same material, such as polyimide, and the first barrier layer 112 and the second barrier layer 114 may be formed of an inorganic material, for example, including at least one of SiOx and SiNx.

[0076] Please refer to Figure 6. The array driving layer 120 may include multiple thin-film transistors. The thin-film transistors may be etch-block type, back-channel etch type, or classified into bottom-gate thin-film transistors, top-gate thin-film transistors, etc., according to the position of the gate and the active layer, or classified into N-type thin-film transistors and P-type thin-film transistors according to their performance. For example, the gate transistor in the non-display area AA may be a P-type thin-film transistor, and the pixel transistor in the display area AA may be an N-type thin-film transistor or a P-type thin-film transistor. Secondly, the thin-film transistors in Figure 6 do not represent the structural diagram of any transistor in Figure 2, but are only schematic diagrams of each film layer of the display panel 100 of this application.

[0077] Referring to Figure 6, the array driving layer 120 may include a barrier insulating layer BF disposed on the substrate 110, a light-shielding layer 121 embedded in the barrier insulating layer BF, a buffer layer 122 disposed on the barrier insulating layer BF, a first active layer 123 disposed on the buffer layer 122, a first insulating layer 124 disposed on the first active layer 123, a first gate layer 125 disposed on the first insulating layer 124, a second insulating layer 126 disposed on the first gate layer 125, and a second insulating layer 126 disposed on the second insulating layer 124. The second active layer 127 on the 6, the third insulating layer 128 disposed on the second active layer 127, the second gate layer 129 disposed on the third insulating layer 128, the fourth insulating layer 130 disposed on the second gate layer 129, the first source-drain layer 131 disposed on the fourth insulating layer 130, the first planarization layer 132 disposed on the first source-drain layer 131, the second source-drain layer 133 disposed on the first planarization layer 132, and the second planarization layer 134 disposed on the second source-drain layer 133.

[0078] Please refer to Figure 6. The light-shielding layer 121 is disposed on the second barrier layer 114. The light-shielding layer 121 is used to block external light from entering the thin film transistor from the bottom. The material of the light-shielding layer 121 can be made of black light-shielding material, such as black light-shielding metal or black organic material. In this application, the light-shielding layer 121 can be disposed only in the display area AA.

[0079] Please refer to Figure 6. The buffer layer 122 is disposed on the light-shielding layer 121. The buffer layer 122 is used to isolate the light-shielding layer 121 from the upper metal material. The material of the buffer layer 122 may be composed of a compound consisting of nitrogen, silicon and oxygen elements, such as a single layer of silicon oxide film or a stacked structure of silicon oxide and silicon nitride.

[0080] Please refer to Figure 6. The first active layer 123 is disposed on the buffer layer 122, and the second active layer 127 is disposed on the second insulating layer 126. In this application, the material of the first active layer 123 can be silicon semiconductor, such as low-temperature polycrystalline silicon, and the material of the second active layer 127 can be oxide semiconductor, such as metal oxide. Since the transistors in the gate driving unit 200a are all P-type transistors, metal oxide semiconductors are not disposed in the non-display area AA of this application. However, the pixel driving circuit 300 has N-type transistors and P-type transistors. Therefore, metal oxide semiconductors and low-temperature polycrystalline silicon semiconductors are disposed in the display area AA of this application.

[0081] Please refer to Figure 6. The first insulating layer 124, the second insulating layer 126, the third insulating layer 128, and the fourth insulating layer 130 are respectively disposed on the corresponding metal layer or semiconductor layer, and are disposed separately as different metal layers or semiconductor layers. The materials of the first insulating layer 124, the second insulating layer 126, the third insulating layer 128, and the fourth insulating layer 130 can be inorganic materials composed of at least two elements in silicon oxynitride or organic materials with planarity.

[0082] Please refer to Figure 6. The first gate layer 125 and the second gate layer 129 are respectively disposed on the corresponding insulating layers. The materials of the first gate layer 125 and the second gate layer 129 can be copper, molybdenum, or molybdenum-titanium alloy, etc.

[0083] Please refer to Figure 6. The first source-drain layer 131 is disposed on the fourth insulating layer 130, and the second source-drain layer 133 is disposed on the first planarization layer 132. The materials of the first source-drain layer 131 and the second source-drain layer 133 can be copper or molybdenum-titanium alloy, copper or titanium, etc.

[0084] Please refer to Figure 6. The first planarization layer 132 and the second planarization layer 134 are laid in a whole layer to ensure the flatness of the film layer of the array driving layer 120. The materials of the first planarization layer 132 and the second planarization layer 134 can be inorganic materials composed of silicon oxynitride or organic materials with flatness.

[0085] As shown in Figure 6, the two plates of the storage capacitor in the non-display area AA of this application are respectively made of the material of the first gate layer 125 and the material of the second active layer 127. For example, the first plate C1a, the third plate C2a, and the fifth plate C3a are located in the second active layer 127, and the second plate C1b, the fourth plate C2b, and the sixth plate C3b are located in the first gate layer 125. The metal layer and an insulating layer between the original second active layer 127 and the first gate layer 125 are removed, reducing the number of film layers in the display panel 100, simplifying the manufacturing process of the display panel 100, and reducing the cost of the display panel 100.

[0086] It should be noted that when all transistors in the gate drive circuit 200 of this embodiment are N-type transistors, the active portions of all transistors in the gate drive circuit 200 can be set using the second active layer 127, and the materials of the first active layer 123 and the first gate layer 125 can be used to form the two plates of the storage capacitor.

[0087] The structure of each film layer in the gate drive unit 200a is described below based on the stack-up diagram.

[0088] Please refer to Figure 7, which is a film layer diagram of the first gate layer 125 in the display panel 100 of this application.

[0089] In this embodiment, the first gate layer 125 includes a first gate T9G of the first output transistor T9 and a second gate T10G of the second output transistor T10, and the first gate T9G and the second gate T10G are arranged in the first direction X.

[0090] In this embodiment, the first gate T9G includes a first main gate T9Ga and a plurality of first branch gates T9Gb connected to the first main gate T9Ga. The first main gate T9Ga extends along a first direction X, and the plurality of first branch gates T9Gb extends along a second direction Y, and the plurality of first branch gates T9Gb are spaced apart in the first direction X. For example, in the structure of FIG7, the first gate T9G includes one first main gate T9Ga and five first branch gates T9Gb, and the first main gate T9Ga is located on the side of the first branch gates T9Gb away from the display area AA.

[0091] In this embodiment, the second gate T10G includes a second main gate T10Ga and a plurality of second branch gates T10Gb connected to the second main gate T10Ga. The second main gate T10Ga extends along a first direction X, and the plurality of second branch gates T10Gb extends along a second direction Y. The plurality of second branch gates T10Gb are spaced apart in the first direction X. The second main gate T10Ga and part of the second branch gates T10Gb are multiplexed as the sixth electrode plate C3b. For example, in the structure of FIG7, the second gate T10G includes one second main gate T10Ga and five second branch gates T10Gb. The second main gate T10Ga is located on the side of the second branch gates T10Gb away from the display area AA.

[0092] In this embodiment, the length and number of the strip-shaped branch gates in the second direction Y are positively correlated with the output load of the output transistor. Therefore, in order to improve the driving capability of the first output transistor T9 and the second output transistor T10, this application sets the first output transistor T9 and the second output transistor T10 as multiple separately arranged strip-shaped branch gates. Each strip-shaped branch gate bears the load of the corresponding transistor. The strip-shaped branch electrode corresponds to the channel of the active part in the corresponding transistor. The two adjacent strip-shaped branch gates correspond to the source and drain of the upper layer. The composite electric field formed by the multiple separately arranged strip-shaped branch gates can improve the driving capability of the transistor.

[0093] In this embodiment, in the first direction X, the spacing between two adjacent first branch gates T9Gb can be equal, and the spacing between two adjacent second branch gates T10Gb can be equal.

[0094] In this embodiment, in the first direction X, the spacing between two adjacent first branch gates T9Gb and the spacing between two adjacent second branch gates T10Gb can be equal.

[0095] In this embodiment, since the output load of the second output transistor T10 is greater than the output load of the first output transistor T9, the area of ​​the first gate T9G can be smaller than the area of ​​the second gate T10G to improve the driving capability of the gate in the second output transistor T10.

[0096] Meanwhile, since a third capacitor C3 is provided in the area where the second output transistor T10 is located, and no capacitor is provided in the area where the first output transistor T9 is located, and the main driving structure in the first output transistor T9 and the second output transistor T10 is the branch gate, and since the second main gate T10Ga and part of the second branch gate T10Gb are multiplexed as the sixth plate C3b, in order to increase the capacitance value of the third capacitor C3, this application can make the linewidth of the first main gate T9Ga smaller than the linewidth of the second main gate T10Ga in the second direction Y, which is equivalent to increasing the linewidth of the second main gate T10Ga, thereby increasing the overlap area of ​​the two plates in the third capacitor C3 and increasing the capacitance value of the third capacitor C3.

[0097] It should be noted that since the potential of the first gate T9G of the first output transistor T9 is a pulse voltage, setting a corresponding capacitor in this area will affect the high and low level transition of the pulse voltage. However, the potential of the second gate T10G of the second output transistor is not a pulse voltage, so a storage capacitor with voltage regulation function can be set.

[0098] Referring to Figure 7, the first gate layer 125 also includes the second electrode C1b of the first capacitor C1 and the fourth electrode C2b of the second capacitor C2. The second electrode C1b and the fourth electrode C2b are arranged along the first direction X, and the fourth electrode C2b and the sixth electrode C3b are arranged along the second direction Y. The second electrode C1b extends along the second direction YX and is connected to the first main gate T9Ga.

[0099] In this embodiment, the area of ​​the second electrode plate C1b can be larger than the area of ​​the fourth electrode plate C2b.

[0100] Referring to Figure 7, the first gate layer 125 also includes the gate T1G of the first transistor T1, the gate T2G of the second transistor T2, the gate T3G of the third transistor T3, the gate T4G of the fourth transistor T4, the gate T5G of the fifth transistor T5, the gate T6G of the sixth transistor T6, the gate T7G of the seventh transistor T7, the gate T8G of the eighth transistor T8, the gate T11G of the eleventh transistor T11, the gate T12G of the twelfth transistor T12, and the gate T13G of the thirteenth transistor T13.

[0101] Please refer to Figure 7. The gates T2G of the second transistor T2, T6G of the sixth transistor T6, and T13G of the thirteenth transistor T13 all extend along the first direction X. The gates T1G of the first transistor T1, T3G of the third transistor T3, T4G of the fourth transistor T4, T7G of the seventh transistor T7, T8G of the eighth transistor T8, T11G of the eleventh transistor T11, and T12G of the twelfth transistor T12 extend along the second direction Y.

[0102] Please refer to Figure 7. The gate T2G of the second transistor T2 is connected to the second plate C1b, and the gate T6G of the sixth transistor T6 is connected to the fourth plate C2b. The gate T2G of the second transistor T2 is located on the side of the second plate C1b close to the fourth plate C2b, and the gate T6G of the sixth transistor T6 is located on the side of the fourth plate C2b close to the second plate C1b.

[0103] Please refer to Figure 7. The gate T11G of the eleventh transistor T11 and the gate T12G of the twelfth transistor T12 are connected in the second direction Y. The gate T8G of the eighth transistor T8 and the gate T5G of the fifth transistor T5 are connected. The gate T3G of the third transistor T3, the gate T4G of the fourth transistor T4 and the gate T12G of the twelfth transistor T12 are arranged at intervals in the first direction X.

[0104] Please refer to Figure 7. The gate T1G of the first transistor T1 is located close to the first gate T9G, and the gate T1G of the first transistor T1 is located between the gate T2G of the second transistor T2 and the gate T13G of the thirteenth transistor T13. The gate T8G of the eighth transistor T8 is located between the gate T13G of the thirteenth transistor T13 and the gate T6G of the sixth transistor T6. The gate T7G of the seventh transistor T7 is located between the fourth plate C2b and the second main gate T10Ga.

[0105] Please refer to Figure 7. The first gate layer 125 also includes a first connection line L1, a second connection line L2, a third connection line L3, a fourth connection line L4, and a first extension segment ET1. The first connection line L1 includes a first lateral segment L1a and a first vertical segment L1b connected to each other. The first lateral segment L1a is located on the side of the fourth electrode plate C2b away from the gate T6G of the sixth transistor T6. The first vertical segment L1b is located between the fourth electrode plate C2b and the second main gate T10Ga. The first vertical segment L1b is connected to the gate T7G of the seventh transistor T7.

[0106] Please refer to Figure 7. The second connection line L2 extends along the second direction Y, and the second connection line L2 is located on the side of the second gate T10 away from the first gate T9.

[0107] Please refer to Figure 7. The third connecting line L3 includes a third horizontal segment L3a and a third oblique segment L3b connected together. The gate T8G of the eighth transistor T8 and the gate T5G of the fifth transistor T5 are both connected to the third horizontal segment L3a. The third oblique segment L3b extends between the gate T4G of the fourth transistor T4 and the gate T12G of the twelfth transistor T12. The fourth connecting line L4 includes a fourth horizontal segment L4a and a fourth oblique segment L4b connected together. The fourth horizontal segment L4a is located between the gate T2G of the second transistor T2 and the gate T13G of the thirteenth transistor T13. The end of the fourth oblique segment L4b away from the fourth horizontal segment L4a extends between the third horizontal segment L3a and the gate T12G of the twelfth transistor T12.

[0108] Please refer to Figure 7. The first extension segment ET1 is connected to the second main gate T10Ga and extends to the side of the second main gate T10Ga away from the second branch gate T10Gb. The first extension segment ET1 is located between the gate T7G of the seventh transistor T7 and the gate T8G of the eighth transistor T8.

[0109] Referring to Figure 7, the gate T5G of the fifth transistor T5 includes a fifth main gate T5Ga extending along the first direction X and at least two fifth branch gates T5Gb connected to the fifth main gate T5Ga. The fifth branch gates T5Gb extend along the second direction Y and are connected to the third lateral segment L3a. Meanwhile, the lengths of the two fifth branch gates T5Gb in the second direction Y are not equal. For example, the length of the fifth branch gate T5Gb farther away from the third lateral segment L3a can be greater than the length of the fifth branch gate T5Gb closer to the third lateral segment L3a.

[0110] It should be noted that since the fifth transistor T5 is used to control the potential of the control node N2, if the leakage current of the fifth transistor is large, it will affect the potential of the control node N2, thereby affecting the stability of the high-level output of the output terminal OUT. Therefore, this application sets the fifth transistor T5 as two transistors connected in series to reduce the leakage current of the fifth transistor T5 and improve the stability of the high-level output of the output terminal OUT.

[0111] Please refer to Figures 8 and 9. Figure 8 is a film layer diagram of the first active layer 123 in the display panel 100 of this application, and Figure 9 is a film layer stack diagram of the first active layer 123 and the first gate layer 125 in the display panel 100 of this application.

[0112] In this embodiment, the first active layer 123 includes a first active portion T9A of the first output transistor T9 and a second active portion T10A of the second output transistor T10. Both the first active portion T9A and the second active portion T10A extend along the first direction X and are connected to each other. The first active portion T9A partially overlaps with multiple first branch gates T9Gb, and the second active portion T10A partially overlaps with multiple second branch gates T10Gb. The overlapping portion of the first active portion T9A and the multiple first branch gates T9Gb forms the channel of the first output transistor T9, and the overlapping portion of the second active portion T10A and the multiple second branch gates T10Gb forms the channel of the second output transistor T10.

[0113] Since the second output transistor T10 is used to control the low-level output to quickly turn off the pixel transistors in the display area AA, the second output transistor T10 needs to have a stronger output capability. Referring to Figures 8 and 9, in the second direction Y, the width of the first active portion T9A is smaller than the width of the second active portion T10A. The increase in the width of the second active portion T10A increases the channel width of the second active portion T10A, thereby improving the driving capability of the second output transistor T10.

[0114] In this embodiment, the first active layer 123 further includes the active portion T1A of the first transistor T1, the active portion T2A of the second transistor T2, the active portion T3A of the third transistor T3, the active portion T4A of the fourth transistor T4, the active portion T5A of the fifth transistor T5, the active portion T6A of the sixth transistor T6, the active portion T7A of the seventh transistor T7, the active portion T8A of the eighth transistor T8, the active portion T11A of the eleventh transistor T11, the active portion T12A of the twelfth transistor T12, and the active portion T13A of the thirteenth transistor T13.

[0115] In this embodiment, the active portion T2A of the second transistor T2, the active portion T3A of the thirteenth transistor T13, and the active portion T6A of the sixth transistor T6 all extend along the second direction Y, while the active portions of the remaining transistors all extend along the first direction X.

[0116] In this embodiment, the active portion T1A of the first transistor T1, the active portion T2A of the second transistor T2, the active portion T8A of the eighth transistor T8, and the active portion T13A of the thirteenth transistor T13 are connected together, while the active portions of the remaining transistors are separated from each other.

[0117] In this embodiment, the linewidths of the active portion T3A of the third transistor T3, the active portion T11A of the eleventh transistor T11, and the active portion T12A of the twelfth transistor T12 in the second direction Y can be equal, and the linewidths of the active portion T4A of the fourth transistor T4, the active portion T5A of the fifth transistor T5, and the active portion T6A of the sixth transistor T6 in the first direction X can be equal, and the linewidth of the active portion T3A of the third transistor T3 is greater than the linewidth of the active portion T4A of the fourth transistor T4.

[0118] It should be noted that, in order to improve the wiring space of this application, the conductor portions located in the first active layer 123 and on both sides of the channel in some transistors of this application are reused as the source or drain of the corresponding transistor, without the need to separately set the source or drain of the corresponding transistor in the first source-drain layer 131, as detailed below.

[0119] Please refer to Figure 9. The overlapping portion of the active part T1A and the gate T1G of the first transistor T1 is the channel of the first transistor T1, and the two sides of the channel of the first transistor T1 are multiplexed as the source T1S and the drain T1D of the first transistor T1.

[0120] Please refer to Figure 9. The overlapping portion of the active part T2A and the gate T2G of the second transistor T2 is the channel of the second transistor T2, and the two sides of the channel of the second transistor T2 are multiplexed as the source T2S and the drain T2D of the second transistor T2.

[0121] Please refer to Figure 9. The overlapping portion of the active part T3A and the gate T3G of the third transistor T3 is the channel of the third transistor T3, and the two sides of the channel of the third transistor T3 are multiplexed as the source T3S and the drain T3D of the third transistor T3.

[0122] Please refer to Figure 9. The overlapping portion of the active part T4A and the gate T4G of the fourth transistor T4 is the channel of the fourth transistor T4, and the two sides of the channel of the fourth transistor T4 are multiplexed as the source T4S and the drain T4D of the fourth transistor T4.

[0123] Please refer to Figure 9. The overlapping portion of the active part T5A and the fifth gate T5G of the fifth transistor T5 is the channel of the fifth transistor T5, and the two sides of the channel of the fifth transistor T5 are multiplexed as the source T5S and drain T5D of the fifth transistor T5. At the same time, since the fifth gate T5G of this application has two fifth branch gates T5Gb, the fifth transistor T5 has two spaced channel portions, that is, the fifth transistor T5 can be composed of two transistors connected in series. The provision of two fifth branch gates T5Gb increases the width of the channel portion and reduces the leakage current of the fifth transistor T5.

[0124] Please refer to Figure 9. The overlapping portion of the active part T6A and the gate T6G of the sixth transistor T6 is the channel of the sixth transistor T6, and the two sides of the channel of the sixth transistor T6 are multiplexed as the source T6S and the drain T6D of the sixth transistor T6.

[0125] Please refer to Figure 9. The overlapping portion of the active part T7A and the gate T7G of the seventh transistor T7 is the channel of the seventh transistor T7, and the two sides of the channel of the seventh transistor T7 are multiplexed as the source T7S and the drain T7D of the seventh transistor T7.

[0126] Please refer to Figure 9. The overlapping portion of the active part T8A and the gate T8G of the eighth transistor T8 is the channel of the eighth transistor T8, and the two sides of the channel of the eighth transistor T8 are multiplexed as the source T8S and the drain T8D of the eighth transistor T8.

[0127] Please refer to Figure 9. The overlapping portion of the active part T11A and the gate T11G of the eleventh transistor T11 is the channel of the eleventh transistor T11, and the two sides of the channel of the eleventh transistor T11 are multiplexed as the source T11S and the drain T11D of the eleventh transistor T11.

[0128] Please refer to Figure 10. The overlapping portion of the active part T12A and the gate T12G of the twelfth transistor T12 is the channel of the twelfth transistor T12, and the two sides of the channel of the twelfth transistor T12 are multiplexed as the source T12S and the drain T12D of the twelfth transistor T12.

[0129] Please refer to Figure 9. The overlapping portion of the active part T13A and the gate T13G of the thirteenth transistor T13 is the channel of the thirteenth transistor T13, and the two sides of the channel of the thirteenth transistor T13 are multiplexed to form the source T13S and the drain T13D of the thirteenth transistor T13.

[0130] It should be noted that drain T1D, drain T8D and drain T13D share a common structure, and source T1S and source T2S share a common structure.

[0131] Please refer to Figures 10 and 11. Figure 10 is a film layer diagram of the second active layer 127 in the display panel 100 of this application, and Figure 11 is a film layer stack diagram of the first active layer 123, the second active layer 127 and the first gate layer 125 in the display panel 100 of this application.

[0132] In this embodiment, the second active layer 127 includes a first electrode C1a of the first capacitor C1, a third electrode C2a of the second capacitor C2, and a fifth electrode C3a of the third capacitor C3. The first electrode C1a and the second electrode C1b are at least partially overlapped, the third electrode C2a and the fourth electrode C2b are at least partially overlapped, and the fifth electrode C3a and the sixth electrode C3b are at least partially overlapped.

[0133] Please refer to Figure 11. In order to increase the capacitance of the storage capacitor, this application makes a portion of the outer contour of the first plate C1a expand relative to the outer contour of the second plate C1b, a portion of the outer contour of the third plate C2a expand relative to the outer contour of the fourth plate C2b, and a portion of the outer contour of the fifth plate C3a expand relative to the outer contour of the sixth plate C3b, which is equivalent to increasing the area of ​​the first plate C1a, the third plate C2a, and the fifth plate C3a as much as possible.

[0134] In this embodiment, since the first capacitor C1 is a bootstrap capacitor and the second capacitor C2 and the third capacitor C3 are both voltage-stabilizing capacitors, the capacitance of the first capacitor C1 is greater than the capacitance of the second capacitor C2, and the capacitance of the first capacitor C1 is greater than the capacitance of the third capacitor C3. That is, the overlapping area of ​​the first plate C1a and the second plate C1b is greater than the overlapping area of ​​the third plate C2a and the fourth plate C2b, and the overlapping area of ​​the first plate C1a and the second plate C1b is greater than the overlapping area of ​​the fifth plate C3a and the sixth plate C3b.

[0135] In this embodiment, since at least a portion of the second main gate T10Ga and a portion of the second branch gate T10Gb are reused as the sixth electrode plate C3b, the fifth electrode plate C3a of this application can cover a portion of the second branch gate T10Gb and a portion of the second main gate T10Ga.

[0136] Please refer to Figures 12 and 13. Figure 12 is a film layer diagram of the second gate layer 129 in the display panel 100 of this application, and Figure 13 is a film layer stack diagram of the first active layer 123, the second active layer 127, the first gate layer 125 and the second gate layer 129 in the display panel 100 of this application.

[0137] In this embodiment, the second gate layer 129 includes an output trace OT, which includes a lateral output segment OT1 and a vertical output segment OT2. The lateral output segment OT1 overlaps with multiple first branch gates T9Gb and multiple second branch gates T10Gb. For example, in the structure of FIG13, the lateral output segment OT1 overlaps with 6 first branch gates T9Gb and 4 second branch gates T10Gb.

[0138] Please refer to Figures 14 and 15. Figure 14 is a film layer diagram of the first source-drain layer 131 in the display panel 100 of this application, and Figure 15 is a film layer stack diagram of the first active layer 123, the second active layer 127, the first gate layer 125, the second gate layer 129 and the first source-drain layer 131 in the display panel 100 of this application.

[0139] In this embodiment, the display panel 100 further includes a first source-drain layer 131 disposed on the side of the second active layer 127 away from the first active layer 123. The first source-drain layer 131 includes a first source T9S and a first drain T9D of the first output transistor T9, and a second source T10S and a second drain T10D of the second output transistor T10.

[0140] In this embodiment, the first drain T9D includes a plurality of first branch drains T9Db, which extend along the second direction Y; for example, in the structures of FIG14 and FIG15, the first drain T9D includes three first branch drains T9Db spaced apart along the first direction X.

[0141] In this embodiment, the first source T9S includes a plurality of first branch source T9Sb, which extend along the second direction Y; for example, in the structures of FIG14 and FIG15, the first source T9S includes 3 first branch source T9Sb.

[0142] Please refer to Figure 14. Multiple first branch source electrodes T9Sb are spaced apart in the first direction X, multiple first branch source electrodes T9Sb and multiple first branch drain electrodes T9Db are spaced apart in the first direction X, and a first branch gate electrode T9Gb is disposed between adjacent first branch source electrodes T9Sb and first branch drain electrodes T9Db.

[0143] In this embodiment, the second drain T10D includes a plurality of second branch drains T10Db, which extend along the second direction Y; for example, in the structures of FIG14 and FIG15, the second drain T10D includes three second branch drains T10Db.

[0144] In this embodiment, the second source T10S includes a plurality of second branch sources T10Sb, which extend along the second direction Y; for example, in the structures of FIG14 and FIG15, the second source T10S includes 3 second branch sources T10Sb.

[0145] Please refer to Figure 14. Multiple second branch sources T10Sb are spaced apart in the first direction X. Multiple second branch sources T10Sb and multiple second branch drains T10Db are spaced apart and staggered in the first direction X. A second branch gate T10Gb is disposed between adjacent second branch sources T10Sb and second branch drains T10Db.

[0146] Please refer to Figures 14 and 15. The second branch drain T10Db, which is closer to the first output transistor T9, is shared with the first branch drain T9Db, which is closer to the second output transistor T10.

[0147] Please refer to Figures 14 and 15. The first source-drain layer 131 also includes a drain main stem 131a extending along the first direction X. The drain main stem 131a extends from the region where the first output transistor T9 is located to the region where the second output transistor T10 is located. Multiple second branch drains T10Db are connected to the drain main stem 131a. Multiple second branch sources T10Sb, multiple first branch drains T9Db, and multiple first branch sources T9Sb are all separated from the drain main stem 131a.

[0148] In this embodiment, the ends of multiple first branch sources T9Sb and multiple second branch sources T10Sb that are away from the receiving circuit 221 pass through vias and are electrically connected to the output trace OT. That is, the first branch source T9Sb serves as the output terminal of the first output transistor T9, and the second branch source T10Sb serves as the output terminal of the second output transistor T10. The end of the first branch source T9Sb that is away from the drain main trunk 131a passes through the first contact hole HL1 and is connected to the vertical output segment OT2. The end of the second branch source T10Sb that is away from the drain main trunk 131a passes through the second contact hole HL2 and is connected to the vertical output segment OT2. That is, both of them pass through vias and are electrically connected to the vertical output segment OT2 of the output trace OT.

[0149] In this embodiment, both the first contact hole HL1 and the second contact hole HL2 penetrate the fourth insulating layer 130.

[0150] In this embodiment, the ends of the multiple second branch drains T10Db near the receiving circuit 221 are connected to the drain trunk 131a, and the ends of the multiple second branch drains T10Db away from the receiving circuit 221 are separated from the output trace OT. For example, in the structure of FIG15, the second drain includes three second branch drains T10Db, and all three second branch drains T10Db are separated from the output trace OT. Since the output trace OT is only connected to the second branch source T10Sb in the second output transistor T10, the longitudinal output segment OT2 of the output trace OT does not extend to the second branch drain T10Db that is far from the first output transistor T9 among the three second branch drains T10Db. Therefore, the length of the second branch drain T10Db that is far from the first output transistor T9 in the second direction Y can be greater than the length of the remaining second branch drains T10Db in the second direction Y.

[0151] Please refer to Figure 15. The display panel 100 includes a plurality of third contact holes HL3 and a plurality of fourth contact holes HL4 disposed in the area where the first output transistor T9 is located. The first drain T9D passes through the plurality of third contact holes HL3 and is connected to the first active part T9A. The first source T9S passes through the plurality of fourth contact holes HL4 and is connected to the first active part T9A.

[0152] Please refer to Figure 15. The display panel 100 includes a plurality of fifth contact holes HL5 and a plurality of sixth contact holes HL6 located in the area where the second output transistor T10 is located. The second drain T10D passes through the plurality of fifth contact holes HL5 and is connected to the first active part T9A. The second source T10S passes through the plurality of sixth contact holes HL6 and is connected to the first active part T9A.

[0153] In this embodiment, the third contact hole HL3, the fourth contact hole HL4, the fifth contact hole HL5, and the sixth contact hole HL5 penetrate the second insulating layer 126, the third insulating layer 128, the fourth insulating layer 130, and a portion of the first insulating layer 124.

[0154] Please refer to Figures 14 and 15. The first source-drain layer 131 also includes a first low potential line VGL1, a first clock line XCK, and a second clock line CK connected to the output circuit 222. The first low potential line VGL1, the first clock line XCK, and the second clock line CK are located at the end of the receiving circuit 221 away from the output circuit 222. The first low potential line VGL1, the first clock line XCK, and the second clock line CK all extend along the first direction X and are arranged along the second direction Y.

[0155] In this embodiment, the first low potential line VGL1 is located close to the receiving circuit 221, the second clock line CK is located away from the receiving circuit 221, and the first clock line XCK is located between the first low potential line VGL1 and the second clock line CK.

[0156] Please refer to Figure 15. The end of the first horizontal segment L1a away from the first vertical segment L1b passes through a via and is connected to the second clock line CK. The end of the gate T3G of the third transistor T3 away from the output circuit 222 passes through a via and is connected to the first clock line XCK. The end of the gate T4G of the fourth transistor T4 away from the output circuit 222 passes through a via and is connected to the first clock line XCK. The end of the gate T12G of the twelfth transistor T2 away from the output circuit 222 passes through a via and is connected to the first low potential line VGL1.

[0157] Please refer to Figures 14 and 15. The first source-drain layer 131 includes a first transmission segment TS1. One end of the first transmission segment TS1 passes through a via and is connected to the end of the second connection line L2 near the receiving circuit 221. The other end of the first transmission segment TS1 passes through a via and is connected to one end of the active part T3A of the third transistor T3.

[0158] The first source-drain layer 131 includes a second transmission segment TS2 extending along the first direction X. One end of the second transmission segment TS2 passes through a via and is connected to the other end of the active portion T3A of the third transistor T3. The other end of the second transmission segment TS2 passes through a via and is connected to at least one fifth branch gate T5Gb of the fifth transistor T5.

[0159] The first source-drain layer 131 includes a third transmission segment TS3 extending along the second direction Y. One end of the third transmission segment TS3 passes through a via and is connected to the end of the gate T3G of the third transistor T3 away from the first clock line XCK. The other end of the second transmission segment TS2 passes through a via and is connected to one end of the active portion T5A of the fifth transistor T5.

[0160] The first source-drain layer 131 includes a fourth transmission segment TS4 extending along the first direction X. One end of the fourth transmission segment TS4 passes through a via and is connected to the other end of the active portion T5A of the fifth transistor T5. The other end of the fourth transmission segment TS4 passes through a via and is connected to one end of the active portion T11A of the eleventh transistor T11.

[0161] The first source-drain layer 131 includes a fifth transmission segment TS5 extending along the second direction Y. One end of the fifth transmission segment TS5 is connected to the fourth transmission segment TS4, and the other end of the fifth transmission segment TS5 passes through a via and is connected to one end of the active portion T4A of the fourth transistor T4.

[0162] The first source-drain layer 131 includes a sixth transmission segment TS6 extending along the first direction X. One end of the sixth transmission segment TS6 passes through a via and is connected to the other end of the active portion T11A of the eleventh transistor T11. The other end of the sixth transmission segment TS6 passes through a via and is connected to the end of the gate T6G of the sixth transistor T6 away from the second capacitor.

[0163] The first source-drain layer 131 includes a seventh transmission segment TS7 extending along the first direction X. One end of the seventh transmission segment TS7 passes through a via and is connected to one end of the third oblique segment L3b. The other end of the seventh transmission segment TS7 passes through a via and is connected to one end of the active portion T12A of the twelfth transistor T12.

[0164] The first source-drain layer 131 includes an eighth transmission segment TS8 extending along the first direction X. One end of the eighth transmission segment TS8 passes through a via and is connected to the other end of the active portion T12A of the twelfth transistor T12. The other end of the eighth transmission segment TS8 passes through a via and is connected to the end of the first plate C1a away from the first output transistor T9.

[0165] The first source-drain layer 131 includes a ninth transmission segment TS9. One end of the ninth transmission segment TS9 passes through a via and is connected to one end of the active portion T7A of the seventh transistor T7. The other end of the ninth transmission segment TS9 passes through a via and is connected to one end of the active portion T6A of the sixth transistor T6.

[0166] The first source-drain layer 131 includes a tenth transmission segment TS10 extending along the first direction X. One end of the tenth transmission segment TS10 passes through a via and is connected to the connection point of the gate T7G of the seventh transistor T7 and the first vertical segment L1b. The other end of the tenth transmission segment TS10 passes through a via and is connected to one end of the active portion T2A of the second transistor T2. The middle segment of the tenth transmission segment TS10 passes through a via and is connected to the other end of the active portion T6A of the sixth transistor T6.

[0167] The first source-drain layer 131 includes an eleventh transmission segment TS11. One end of the eleventh transmission segment TS11 passes through a via and is connected to the other end of the active portion T7A of the seventh transistor T7. The other end of the eleventh transmission segment TS11 passes through a via and is connected to one end of the active portion T8A of the eighth transistor T8. The middle section of the eleventh transmission segment TS11 passes through a via and is connected to the first extension segment ET1.

[0168] The first source-drain layer 131 includes a twelfth transmission segment TS12 extending along the first direction X. One end of the twelfth transmission segment TS12 passes through a via and is connected to the third lateral segment L3a. The other end of the twelfth transmission segment TS12 passes through a via and is connected to one end of the active portion T3A of the thirteenth transistor T13. The other end of the active portion of the thirteenth transistor T13 passes through a via and is connected to the drain main body 131a.

[0169] The first source-drain layer 131 includes a thirteenth transmission segment TS13. One end of the thirteenth transmission segment TS13 passes through a via and is connected to the other end of the active part T2A of the second transistor T2. The other end of the thirteenth transmission segment TS13 passes through a via and is connected to the second electrode plate C1a.

[0170] The first source-drain layer 131 includes a fourteenth transmission segment TS14 and a fifteenth transmission segment TS15. One end of the fourteenth transmission segment TS14 passes through a via and is connected to the second connection line L2. The other end of the fourteenth transmission segment TS14 passes through a via and is connected to the lateral output segment OT2 of the previous stage. The fifteenth transmission segment TS15 is connected to the fourteenth transmission segment TS14 of the next stage.

[0171] The first source-drain layer 131 includes a second extension segment ET2 extending along the second direction Y. One end of the second extension segment ET2 is connected to the first low potential line VGL1, and the other end of the second extension segment ET2 passes through a via and is connected to the other end of the active portion T4A of the fourth transistor T4.

[0172] The first source-drain layer 131 also includes a control line Control extending along the first direction X and a third extension segment ET3 connected to the control line Control. The end of the third extension segment ET3 away from the control line Control is connected to the gate T3G of the thirteenth transistor T13.

[0173] Please refer to Figures 16 and 17. Figure 16 is a film layer diagram of the second source / drain layer 133 in the display panel 100 of this application, and Figure 17 is a film layer stack diagram of the first active layer 123, the second active layer 127, the first gate layer 125, the second gate layer 129, the first source / drain layer 131, and the second source / drain layer 133 in the display panel 100 of this application.

[0174] In this embodiment, the display panel 100 further includes a second source-drain layer 133 disposed on the side of the first source-drain layer 131 away from the second active layer 127. The second source-drain layer 133 includes a first high potential line VGH1 and a second low potential line VGL2. The first high potential line VGH1 and the second low potential line VGL2 extend along the first direction X and are arranged along the second direction Y. The second low potential line VGL2 is disposed close to the display area AA.

[0175] In this embodiment, the second low potential line VGL2 overlaps with multiple first branch gates T9Gb and multiple second branch gates T10Gb, and the second low potential line VGL2 passes through the first connection hole HL7 and is connected to multiple first branch drains T9Db; the first high potential line VGH1 overlaps with the drain trunk 131a and part of the receiving circuit 221, and the first high potential line VGH1 passes through the second connection hole HL8 and is connected to the drain trunk 131a.

[0176] In the structure of Figure 16, the second source-drain layer 133 includes a first high potential line VGH1 and a second low potential line VGL2. The second low potential line VGL2 passes through the first connection hole HL7 and is connected to the first branch drain T9Db of the first output transistor T9. The first high potential line VGH1 passes through the second connection hole HL8 and is connected to the drain trunk 131a.

[0177] In this embodiment, the first connecting hole HL7 and the second connecting hole HL8 penetrate the first planarization layer 132.

[0178] In this embodiment, the number of first connecting holes HL7 can be less than or equal to the number of second connecting holes HL8; for example, in the structure of Figure 17, the number of first connecting holes HL7 is 3, and the number of second connecting holes HL8 is 1. Meanwhile, in order to reduce the contact impedance between the first high-potential line VGH1 and the drain trunk 131a, this application makes the aperture of the first connecting hole HL7 smaller than the aperture of the second connecting hole HL8, which is equivalent to reducing the number of second connecting holes HL8 and increasing the aperture of the second connecting holes HL8. This reduces the contact impedance of the second connecting holes HL8 while ensuring that the contact areas of the first connecting holes HL7 and the second connecting holes HL8 are comparable to those of the corresponding potential lines.

[0179] In this embodiment, in the second direction Y, the width of the first low potential line VGL1 is smaller than the width of the second low potential line VGL2, and the width of the first high potential line VGH1 is larger than the width of the second low potential line VGL2.

[0180] In this embodiment, the second source-drain layer 133 further includes an initial signal line STV, which is located on the side of the second low potential line VGL2 near the display area AA.

[0181] In this embodiment, the first high-potential line VGH1 may overlap with at least a portion of the first capacitor C1, and the first high-potential line VGH1 may overlap with at least a portion of the second capacitor C2.

[0182] In this embodiment, since the gate T11G of the eleventh transistor T11 and the gate T12G of the twelfth transistor T12 are both connected to the first low potential line VGL1, the first high potential line VGH1 is spaced apart from the gate T11G of the eleventh transistor T11 and the gate T12G of the twelfth transistor T12 in order to avoid the influence of the first high potential line VGH1 on the gate T11G of the eleventh transistor T11 and the gate T12G of the twelfth transistor T12.

[0183] It should be noted that the initial signal line STV is only connected to the end of the second connection line L2 in the first-stage gate driving unit 200a that is away from the receiving circuit 221. The end of the second connection line L2 in the second-stage and above gate driving units 200a that is away from the receiving circuit 221 is connected to the lateral output segment OT1 of the output trace OT of the previous stage gate driving unit 200a.

[0184] It should be noted that the signal line for transmitting signals in this application extends along the first direction X or the second direction Y, which only indicates that the signal line extends in that direction and does not represent that the signal line is a straight line in that direction. It can be an oblique line or multiple straight lines, etc.

[0185] This application also provides a display device, which includes the aforementioned display panel. The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0186] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0187] The technical solutions provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions in the embodiments of this application.

Claims

1. A display panel comprising a plurality of gate driving units, each of the gate driving units comprising an output circuit, a receiving circuit and a storage capacitor connected in series, each of the output circuit and the receiving circuit comprising a gate transistor, and an area of the gate transistor in the output circuit being greater than an area of the gate transistor in the receiving circuit; wherein an active part of at least one of the gate transistors being located in a first active layer, one plate of the storage capacitor being located in a second active layer, a gate of the gate transistor and another plate of the storage capacitor being located in a first gate layer, the first gate layer, the first active layer and the second active layer being arranged in different layers.

2. The display panel of claim 1, wherein, the output circuit comprising a first output transistor, the receiving circuit comprising a first node control module, the first output transistor and the first node control module being connected to a first node; wherein the storage capacitor comprises a first capacitor, the first capacitor comprising a first plate and a second plate, the first plate and the second plate being connected to different internal nodes in the first node control module respectively, the first plate being located in the second active layer, and the second plate being located in the first gate layer.

3. The display panel of claim 2, wherein, the output circuit comprising a second output transistor connected to the first output transistor, the receiving circuit comprising a second node control module, the second output transistor and the second node control module being connected to a second node; wherein the storage capacitor comprises a second capacitor, the second capacitor comprising a third plate and a fourth plate, the third plate and the fourth plate being connected to different internal nodes in the second node control module respectively, the third plate being located in the second active layer, and the fourth plate being located in the first gate layer.

4. The display panel of claim 3, wherein, an overlapping area of the first plate and the second plate being greater than an overlapping area of the third plate and the fourth plate.

5. The display panel of claim 3, wherein, the storage capacitor further comprising a third capacitor, the third capacitor comprising a fifth plate and a sixth plate, the fifth plate being located in the second active layer, and the sixth plate being located in the first gate layer; wherein the sixth plate is connected to a source of the second output transistor, and the fifth plate is connected to the second node.

6. The display panel of claim 5, wherein, the first gate layer comprising a first gate of the first output transistor and a second gate of the second output transistor, the first gate and the second gate being arranged in a first direction; wherein an area of the first gate is less than an area of the second gate.

7. The display panel of claim 6, wherein, the first gate comprising a first trunk gate and a plurality of first branch gates connected to the first trunk gate, the first trunk gate extending along the first direction, the plurality of first branch gates extending along a second direction, and the plurality of first branch gates being arranged in the first direction with intervals; the second gate comprising a second trunk gate and a plurality of second branch gates connected to the second trunk gate, the second trunk gate extending along the first direction, the plurality of second branch gates extending along the second direction, and the plurality of second branch gates being arranged in the first direction with intervals; The second main trunk gate and part of the second branch gate are multiplexed as the sixth plate, the second direction is parallel to a scan line of the display panel, and an included angle between the first direction and the second direction is greater than 0° and less than or equal to 90°.

8. The display panel of claim 7, wherein, In the second direction, a line width of the first main trunk gate is less than a line width of the second main trunk gate.

9. The display panel of claim 7, wherein, In the second direction, a length of the first branch gate is less than a length of the second branch gate.

10. The display panel of claim 7, wherein, The first gate layer further includes a second plate of the first capacitor and a fourth plate of the second capacitor, the second plate and the fourth plate are arranged along the first direction, and the fourth plate and the sixth plate are arranged along the second direction. The second plate extends along the second direction and is connected to the first main trunk gate.

11. The display panel of claim 10, wherein, The second active layer includes a first plate of the first capacitor, a third plate of the second capacitor and a fifth plate of the third capacitor. Part of the outer contour of the first plate is outwardly expanded relative to an outer contour of the second plate, part of the outer contour of the third plate is outwardly expanded relative to an outer contour of the fourth plate, and part of the outer contour of the fifth plate is outwardly expanded relative to an outer contour of the sixth plate.

12. The display panel of claim 7, wherein, The display panel further includes a first source-drain layer arranged on a side of the second active layer away from the first active layer, and the first source-drain layer includes a first source and a first drain of the first output transistor. The first drain includes a plurality of first branch drains, and the first source includes a plurality of first branch sources, the plurality of first branch drains and the plurality of first branch sources extend along the second direction, and the plurality of first branch drains and the plurality of first branch sources are arranged at intervals along the first direction. Each first branch gate is provided with a first branch drain and a first branch source on both sides of the first direction.

13. The display panel of claim 12, wherein, The first source-drain layer further includes a second source and a second drain of the second output transistor. The second drain includes a plurality of second branch drains, and the second source includes a plurality of second branch sources, the plurality of second branch drains and the plurality of second branch sources extend along the second direction, and the plurality of second branch drains and the plurality of second branch sources are arranged at intervals along the first direction, and each second branch gate is provided with a second branch drain and a second branch source on both sides of the first direction. The first source-drain layer further includes a drain trunk extending along the first direction, the plurality of second branch drains are connected to the drain trunk, and the plurality of second branch sources, the plurality of first branch drains and the plurality of first branch sources are arranged separately from the drain trunk.

14. The display panel of claim 13, wherein, The display panel further includes a second gate layer arranged between the second active layer and the first source-drain layer, and the second gate layer includes output traces extending along the first direction. An end of the plurality of first branch sources and the plurality of second branch sources away from the receiving circuit passes through a via and is electrically connected to the output traces.

15. The display panel of claim 14, wherein, The second branch drain electrodes and the second branch source electrodes are arranged in a staggered manner along the first direction, and the second branch drain electrodes close to one end of the receiving circuit are connected to the drain stem, and the second branch drain electrodes away from the other end of the receiving circuit are arranged separately from the output wire.

16. The display panel of claim 13, wherein, The first source-drain layer further comprises a first low potential line, a first clock line and a second clock line connected to the output circuit, the first low potential line, the first clock line and the second clock line are arranged at the end of the receiving circuit away from the output circuit, and the first low potential line, the first clock line and the second clock line all extend along the first direction and are arranged along the second direction. The first low potential line is arranged close to the receiving circuit, the second clock line is arranged away from the receiving circuit, and the first clock line is arranged between the first low potential line and the second clock line.

17. The display panel of claim 13, wherein, The display panel further comprises a second source-drain layer arranged on the side of the first source-drain layer away from the first active layer, the second source-drain layer comprises a second low potential line and a first high potential line, and the second low potential line and the first high potential line all extend along the first direction and are arranged along the second direction. The second low potential line overlaps the first branch gate electrodes and the second branch gate electrodes, and the second low potential line passes through the first connection hole to connect the first branch drain electrodes. The first high potential line overlaps the drain stem and part of the receiving circuit, and the first high potential line passes through the second connection hole to connect the drain stem.

18. The display panel of claim 17, wherein, In the second direction, the width of the first low potential line is smaller than the width of the second low potential line.

19. The display panel of claim 17, wherein, In the second direction, the width of the first high potential line is greater than the width of the second low potential line.

20. The display panel of claim 17, wherein, The aperture of the first connection hole is smaller than the aperture of the second connection hole.

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