Test module and test apparatus

Abstract

A test module (100) and a test apparatus. The test module (100) comprises a capacitor assembly (10), a switch assembly (20), and a frame assembly (30). The capacitor assembly (10) and the switch assembly (20) are both located inside the frame assembly (30), and the capacitor assembly (10) and the switch assembly (20) are connected to a semiconductor device under test. The switch assembly (20) comprises a protective switch, and the protective switch is connected to the capacitor assembly (10).

Description

A test module and a test device

[0001] Cross-references to related applications

[0002] This application is based on and claims priority to Chinese Patent Application No. 202411541402.2, filed on October 31, 2024, entitled “A Multi-Test Module and Test Device”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of semiconductor device testing technology, and in particular to a test module and a test apparatus. Background Technology

[0004] In recent years, wide-bandgap semiconductor devices, represented by silicon carbide (SiC), have attracted widespread attention. SiC material has a bandgap three times that of silicon, a critical breakdown electric field strength ten times that of silicon, and a thermal conductivity three times that of silicon. Therefore, SiC semiconductor devices are suitable for high-frequency, high-voltage, and high-temperature applications, and contribute to improving the efficiency and power density of power electronic systems. They have enormous application prospects in high-voltage power transmission and transformation, new energy vehicles, aerospace, shipbuilding, and marine industries. Therefore, it is necessary to test the characteristics of these semiconductor devices.

[0005] The test modules provided by related technologies can test the frequent switching conditions of the semiconductor device under test (SDT) through DC power supplies, DC pulse capacitors, protective fuses, load inductors, the SDT itself, accompanying SDT devices, and protection branches to determine the operating frequency of the SDT and thus test its characteristics. However, because DC pulse capacitors discharge within microseconds while protective fuses operate in milliseconds, the fuses may not be able to trip during the DC pulse capacitor discharge, and the discharged energy can damage both the SDT and the test module. In other words, the test modules provided by these technologies have low reliability. Summary of the Invention

[0006] To address the low reliability issue in existing technologies, this application provides a test module for semiconductor devices, which may include a capacitor assembly, a switch assembly, and a frame assembly. Both the capacitor assembly and the switch assembly are located inside the frame assembly and are connected to the semiconductor device under test. The switch assembly includes a protection switch, which is connected to the capacitor assembly.

[0007] In some embodiments, the capacitor assembly may include multiple capacitor banks and a busbar. The multiple capacitor banks are connected in parallel via the busbar. Each capacitor bank includes multiple parallel-connected DC pulse capacitors.

[0008] In some embodiments, the busbar includes a first insulating layer, a negative electrode plate, a second insulating layer, a positive electrode plate, and a third insulating layer stacked sequentially along a first direction.

[0009] In some embodiments, the positive electrode plate is provided with a first sealed mounting hole. The first sealed mounting hole penetrates the negative electrode plate and is insulated from it. The positive electrode plate is connected to the positive terminal of the capacitor bank through the first sealed mounting hole. The insulation voltage between the first sealed mounting hole and the negative electrode plate is greater than or equal to 1.5 times the terminal voltage of the DC pulse capacitor.

[0010] The negative plate has a second sealed mounting hole. The second sealed mounting hole penetrates the positive plate and is insulated from it. The negative plate is connected to the negative terminal of the capacitor bank through the second sealed mounting hole. The insulation voltage between the second sealed mounting hole and the positive plate is greater than or equal to 1.5 times the voltage at the terminal of the DC pulse capacitor.

[0011] In some embodiments, the switching assembly further includes a changeover switch, a protective fuse, a snubber capacitor, a voltage equalization branch, and a switch busbar. The voltage equalization branch includes a voltage equalization capacitor and a voltage equalization resistor connected in parallel.

[0012] The changeover switch and protection switch are fixed on one side of the switch busbar, while the protection fuse, absorption capacitor, and equalizing branch are fixed on the other side of the switch busbar. The protection switch is connected to the protection fuse, capacitor assembly, absorption capacitor, changeover switch, and equalizing branch through the switch busbar. The protection fuse is connected to the changeover switch and absorption capacitor through the switch busbar. The changeover switch is connected to the equalizing branch through the switch busbar.

[0013] In some embodiments, the switch busbar includes a fourth insulating layer, a negative terminal busbar, a fifth insulating layer, a positive terminal busbar, a sixth insulating layer, a switching busbar, and a seventh insulating layer stacked along a first direction.

[0014] In some embodiments, the positive input busbar includes a plurality of first terminals, second terminals and third terminals.

[0015] Multiple first terminals are led out in parallel along a first direction, and second and third terminals are led out in opposite directions along a second direction, with the first direction perpendicular to the second direction.

[0016] Each terminal is connected to the first end of the protective fuse, the second terminal is connected to the cathode of the first diode in the protective switch, and the third terminal is connected to the positive plate.

[0017] In some embodiments, the negative input busbar includes a plurality of fourth terminals, a plurality of fifth terminals, a sixth terminal, a seventh terminal, and an eighth terminal.

[0018] Each of the plurality of fifth terminals and the sixth terminal are led out in parallel along a first direction, and each of the plurality of fourth terminals, the seventh terminal and the eighth terminal are led out in the opposite direction along a second direction, with the first direction being perpendicular to the second direction.

[0019] The fourth terminal is connected to the anode of the second diode in the switching switch, the fifth terminal is connected to the absorption capacitor, the sixth terminal is connected to the second end of the equalizing branch, the seventh terminal is connected to the second electrode of the first fully controlled semiconductor device in the protection switch, and the eighth terminal is connected to the negative electrode plate.

[0020] In some embodiments, the switching busbar includes a plurality of positive busbars and a negative busbar.

[0021] Each of the multiple positive busbars has an L-shaped structure. The negative busbar includes a ninth terminal, a tenth terminal, and an eleventh terminal. The ninth terminal is led out along a third direction, the tenth terminal is led out along a first direction, and the eleventh terminal is led out along a second direction. The first direction, the second direction, and the third direction are perpendicular to each other.

[0022] Each positive busbar is connected to the second terminal of the protective fuse and the first terminal of the second fully controlled semiconductor device in the switching switch. The ninth terminal is connected to the second terminal of the second fully controlled semiconductor device. The tenth terminal is connected to the first terminal of the equalizing branch. The eleventh terminal is connected to the semiconductor device under test.

[0023] In some embodiments, the frame assembly includes a housing shell, a cover plate, a support plate, and a heat sink.

[0024] The capacitor assembly is fixed to the side wall of the enclosure, the support plate is fixed inside the enclosure, the heat sink is fixed to the support plate, the switch assembly is fixed to the heat sink, and the enclosure and cover plate form a sealed structure.

[0025] In some embodiments, the side walls of the enclosure are provided with ventilation holes. The enclosure and cover are made of metal, and the support plate is made of insulating material.

[0026] Furthermore, this application also provides a testing apparatus, including multiple test modules as described above. These test modules are cascaded and connected to the semiconductor device under test.

[0027] Compared with the prior art, the beneficial effects of this application are as follows:

[0028] In the test module provided in this application, both the capacitor assembly and the switch assembly are located inside the frame assembly and are connected to the semiconductor device under test (DUT). The switch assembly includes a protection switch, which is connected to the capacitor assembly. During DC pulse capacitor discharge, the protection switch provides overvoltage protection to the capacitor bank, preventing damage to the DUT and the test module. In other words, the test module provided in this application has high reliability.

[0029] Based on the device connection method and layout, the switch busbar has a short loop distance, low parasitic inductance due to repeated trips, and low stray inductance, effectively solving the problem of voltage and current overshoot caused by parasitic inductance under high current change rate conditions. This allows the switch busbar to not only meet the required withstand voltage, insulation, and heat dissipation requirements, but also effectively improve problems such as turn-off voltage spikes and voltage and current waveform distortion, reducing voltage stress on the tested semiconductor devices.

[0030] In this application, multiple capacitor banks are connected in parallel via a busbar, resulting in good current sharing and preventing individual capacitor banks from overheating.

[0031] The busbars and switch busbars are designed with low inductance, and the current inlet and outlet circuits are closely stacked together, so the distributed inductance cancels each other out. At the same time, the first sealed mounting hole on the positive plate and the second sealed mounting hole on the negative plate can increase the creepage distance. The low parasitic inductance and associated capacitance can effectively reduce the induced high voltage when the switching switch and protection switch are turned on and off, thereby protecting the switching switch and protection switch.

[0032] In the busbar, the different insulation layers, positive plates, and negative plates are completely bonded together without air gaps. This results in low partial discharge rate under high voltage, high electrical safety, low electromagnetic radiation, and low conducted heat generation. Furthermore, the busbar is resistant to harsh environments such as pollution and vibration.

[0033] The switch busbar features seamless bonding between different insulation layers and between the negative and positive input busbars, resulting in low partial discharge rate under high voltage, high electrical safety, low electromagnetic radiation, and minimal conducted heat generation. Furthermore, the switch busbar is resistant to harsh environments such as pollution and vibration.

[0034] The test module provided in this application can be used to test the switching characteristics, reverse recovery, dynamic resistance, gate charge, and other characteristics of the semiconductor device under test.

[0035] The test module provided in this application has a compact structure and high space utilization. A certain number of test modules can be cascaded to form a test device, which can meet the testing requirements of higher voltage levels and help expand the test capacity.

[0036] The test module provided in this application has a housing, suitable for different structural combinations, and easy to cascade to form test devices of different voltage levels. Each cascaded test module can be used independently or in combination, allowing for more flexible control. Furthermore, it saves overall space in the test device, has high integration, and is convenient for installation and maintenance.

[0037] In the test apparatus provided in this application, multiple test modules are connected and led out to the semiconductor device under test using cascaded busbars. The cascaded busbar structure is designed according to the principle of positive and negative parallelism, reverse direction, and minimum safe distance to avoid unnecessary connection transitions and low parasitic stray inductance. Attached Figure Description

[0038] Figure 1a is an isometric side view of the test module in an embodiment of this application;

[0039] Figure 1b is an exploded view of the test module in an embodiment of this application;

[0040] Figure 2 is the electrical schematic diagram of the test module in the embodiment of this application;

[0041] Figure 3a is an isometric side view of the capacitor assembly in an embodiment of this application;

[0042] Figure 3b is an exploded view of the capacitor assembly in an embodiment of this application;

[0043] Figure 4 is a schematic structural diagram of the busbar in an embodiment of this application;

[0044] Figure 5a is an isometric side view of the switch assembly in an embodiment of this application;

[0045] Figure 5b is an exploded view of the switch assembly in an embodiment of this application;

[0046] Figure 6a is an isometric side view of the switch busbar in an embodiment of this application;

[0047] Figure 6b is an exploded view of the switch busbar in an embodiment of this application;

[0048] Figure 7 is a schematic structural diagram of a positive electrode incoming busbar in an embodiment of this application;

[0049] Figure 8 is a schematic structural diagram of a negative terminal incoming busbar in an embodiment of this application;

[0050] Figure 9 is a schematic structural diagram of a switching busbar in an embodiment of this application;

[0051] Figure 10a is an isometric side view of the frame component in an embodiment of this application;

[0052] Figure 10b is an exploded view of the frame components in an embodiment of this application;

[0053] Figure 11 is a schematic structural diagram of a test device in an embodiment of this application;

[0054] Figure 12 is an electrical structure diagram of the test device in the embodiment of this application. Detailed Implementation

[0055] The technical solutions in this application will now be described with reference to the accompanying drawings.

[0056] The terms "first," "second," etc., used in the specification, embodiments, claims, and drawings of this application are for distinguishing purposes only and should not be construed as indicating or implying relative importance or order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, such as including a series of steps or units. A method, system, product, or apparatus is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or apparatuses.

[0057] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0058] This application provides a test module for semiconductor devices (using an Insulated Gate Bipolar Transistor (IGBT) as an example). As shown in Figures 1a and 1b, the test module 100 includes a capacitor assembly 10, a switch assembly 20, and a frame assembly 30. Both the capacitor assembly 10 and the switch assembly 20 are located inside the frame assembly 30 and are connected to the semiconductor device under test (i.e., the IGBT, not shown in Figures 1a and 1b). The switch assembly 20 includes a protection switch (not shown in Figures 1a and 1b, but described below), which is connected to the capacitor assembly 10.

[0059] The electrical schematic diagram corresponding to test module 100 can be found in Figure 2. In Figure 2, DUT1 represents the IGBT under test, DUT2 represents the accompanying semiconductor device (which can be a diode or a device containing an IGBT anti-parallel diode), L represents the load inductance, U represents the power supply, C1 represents the capacitor bank in capacitor assembly 10, and the protection switch includes IGBT1 (i.e., the first fully controlled semiconductor device), diode D1 (i.e., the first diode), and resistor R1. C2 represents the absorption capacitor in switch assembly 20, and F represents the protection fuse in switch assembly 20. The switching switch in switch assembly 20 includes IGBT2 (i.e., the second fully controlled semiconductor device) and diode D2 (i.e., the second diode). The voltage equalization branch in switch assembly 20 includes voltage equalization resistor R2 and voltage equalization capacitor C3.

[0060] In some embodiments, as shown in Figures 3a and 3b, the capacitor assembly 10 may include multiple capacitor groups 11 and a busbar 12. The multiple capacitor groups 11 are connected in parallel via the busbar 12. Each capacitor group 11 includes multiple parallel-connected DC pulse capacitors. In this embodiment, 3000V / 500μF DC pulse capacitors are used, with a self-inductance ≤50nH, an equivalent series resistance ≤1mΩ, and an allowable voltage drop range of ≤5% under test conditions. The structural layout is a double-row, five-column configuration.

[0061] For example, as shown in FIG4, the busbar 12 includes a first insulating layer 121, a negative electrode plate 122, a second insulating layer 123, a positive electrode plate 124 and a third insulating layer 125 stacked sequentially along a first direction (which may be the Z direction in FIG4).

[0062] For example, the positive electrode plate 124 is provided with a first sealed mounting hole. The first sealed mounting hole penetrates the negative electrode plate 122 and is insulated from the negative electrode plate 122. The positive electrode plate 124 is connected to the positive terminal of the capacitor bank 11 through the first sealed mounting hole. The insulation voltage between the first sealed mounting hole and the negative electrode plate 122 is greater than or equal to 1.5 times the voltage at the terminal of the DC pulse capacitor.

[0063] The negative plate 122 is provided with a second sealed mounting hole. The second sealed mounting hole penetrates the positive plate 124 and is insulated from the positive plate 124. The negative plate 122 is connected to the negative terminal of the capacitor bank 11 through the second sealed mounting hole. The insulation voltage between the second sealed mounting hole and the positive plate 124 is greater than or equal to 1.5 times the terminal voltage of the DC pulse capacitor.

[0064] The self-inductance of the busbar 12 is the superposition of the self-inductance of the positive plate 124, the self-inductance of the negative plate 122, and the mutual inductance coupling between the positive plate 124 and the negative plate 122. Its self-inductance is mainly related to the length of the current path; the shorter the current path, the smaller the self-inductance. The mutual inductance between the positive plate 124 and the negative plate 122 is related to the degree of mutual coupling. Except for the lead-out terminals and mounting holes, the structures of the positive plate 124 and the negative plate 122 are basically symmetrical, resulting in a symmetrical and oppositely overlapping current path. The self-inductance and mutual inductance of the positive plate 124 and the negative plate 122 cancel each other out, thus reducing the self-inductance of the busbar 12. The three insulating layers—the first insulating layer 121, the second insulating layer 123, and the third insulating layer 125—meet the insulation requirements between the positive plate 124 and the negative plate 122.

[0065] In some embodiments, the setting function of the switching assembly 20 is as follows: during the initial test state, each capacitor bank is charged until it is charged to the set voltage. During the test, the capacitor bank 11 is turned on and off according to the control timing to output DC pulses, thereby testing the turn-on and turn-off capabilities of the IGBT under test; in addition, it has overvoltage and overcurrent protection functions.

[0066] In some embodiments, as shown in Figures 5a and 5b, the switching assembly 20 includes a switching switch 21, a protective switch 22, a protective fuse 23, an absorption capacitor 24, a voltage equalization branch 25, and a switch busbar 26. The voltage equalization branch 25 includes a voltage equalization capacitor 251 and a voltage equalization resistor 252 connected in parallel.

[0067] The changeover switch 21 and the protection switch 22 are fixed on one side of the switch busbar 26, and the protection fuse 23, the absorption capacitor 24, and the equalizing branch 25 are fixed on the other side of the switch busbar 26. The protection switch 22 is connected to the protection fuse 23, the capacitor assembly 10, the absorption capacitor 24, the changeover switch 21, and the equalizing branch 25 through the switch busbar 26. The protection fuse 23 is connected to the changeover switch 21 and the absorption capacitor 24 through the switch busbar 26. The changeover switch 21 is connected to the equalizing branch 25 through the switch busbar 26.

[0068] The switching switch 21 and the protection switch 22 are configured according to the electrical parameters of the test system. In this embodiment, a 3300V / 1000A switching switch and a 3300V / 400A IGBT protection switch are used. The switching switch 21 is used to control the output of the capacitor bank 11 and provide current limiting protection. The protection switch 22 is used to provide overvoltage protection for the capacitor bank 11. The protection fuse 23 is used to provide overcurrent protection for the main test circuit.

[0069] The absorption capacitor 24 is used to control the surge voltage interruption and the surge voltage recovery of the freewheeling diode. In this embodiment, a 3000V / 3.3μF absorption capacitor is used.

[0070] The voltage equalization branch 25 is used to ensure that the voltage of each test module is basically consistent in the initial state of the test when multiple test modules are used in combination, and to suppress overvoltage surges. The voltage equalization resistor 252 is used for current limiting and absorption. In this embodiment, a 3000V / 1μF voltage equalization capacitor 251 and a 2MΩ / 10W resistor 252 are selected.

[0071] In some embodiments, as shown in Figures 6a and 6b, the switch busbar 26 includes a fourth insulating layer 261, a negative terminal busbar 262, a fifth insulating layer 263, a positive terminal busbar 264, a sixth insulating layer 265, a switching busbar 266, and a seventh insulating layer 267 stacked along a first direction (Z direction in Figure 6b).

[0072] For example, as shown in FIG7, the positive terminal busbar 264 includes a plurality of first terminals P1, second terminals P2 and third terminals P3.

[0073] Multiple first terminals P1 are led out in parallel along a first direction (Z direction in Figure 7), and second terminals P2 and third terminals P3 are led out in opposite directions along a second direction (X direction in Figure 7). The first direction is perpendicular to the second direction.

[0074] Each first terminal P1 is connected to the first end of the protective fuse 23, the second terminal P2 is connected to the negative terminal of the first diode (diode D1 in Figure 2) in the protective switch 22, and the third terminal P3 is connected to the positive plate 124.

[0075] For example, as shown in FIG8, the negative terminal busbar 262 includes a plurality of fourth terminals P4, a plurality of fifth terminals P5, a sixth terminal P6, a seventh terminal P7 and an eighth terminal P8.

[0076] Each of the multiple fifth terminals P5 and the sixth terminal P6 are led out in parallel along the first direction (the X direction in Figure 8), and each of the multiple fourth terminals P4, the seventh terminal P7 and the eighth terminal P8 are led out in the opposite direction along the second direction (the X direction in Figure 8). The first direction is perpendicular to the second direction.

[0077] The fourth terminal P4 is connected to the anode of the second diode (i.e., diode D2 in Figure 2) in the switching switch 21, the fifth terminal P5 is connected to the absorption capacitor 24, the sixth terminal P6 is connected to the second end of the voltage equalization branch 25, the seventh terminal P7 is connected to the second electrode (which can be the emitter) of the first fully controllable semiconductor device (i.e., IGBT1 in Figure 2) in the protection switch 22, and the eighth terminal P8 is connected to the negative plate 122.

[0078] For example, as shown in FIG9, the switching busbar 266 includes a plurality of positive busbars 2661 and negative busbars 2662.

[0079] Each of the multiple positive busbars 2661 has an L-shaped structure. The negative busbar 2662 includes a ninth terminal P9, a tenth terminal P10, and an eleventh terminal P11. The ninth terminal P9 is led out along a third direction (the opposite direction of the Y direction in Figure 9), the tenth terminal P10 is led out along a first direction (the Z direction in Figure 9), and the eleventh terminal P11 is led out along a second direction (the X direction in Figure 9), wherein the first direction, the second direction, and the third direction are perpendicular to each other.

[0080] Each positive busbar 2661 connects to the second terminal of the protective fuse 23 and the first terminal (which can be the collector) of the second fully controllable semiconductor device (i.e., IGBT2 in Figure 2) in the switching switch 21. The ninth terminal P9 connects to the second terminal (which can be the emitter) of the second fully controllable semiconductor device (i.e., IGBT2 in Figure 2). The tenth terminal P10 connects to the first terminal of the equalizing branch 25, and the eleventh terminal P11 connects to the semiconductor device under test (i.e., DUT1 in Figure 2). In the case of multiple test modules cascaded, the eleventh terminal P11 can be used to connect to the next level test module.

[0081] In some embodiments, as shown in Figures 10a and 10b, the frame assembly 30 includes a housing 31, a cover plate 32, a support plate 33, and a heat sink 34.

[0082] The capacitor assembly 10 (not shown in Figures 1a and 10b) is fixed to the side wall of the housing 31, the support plate 33 is fixed inside the housing 31, the heat sink 34 is fixed to the support plate 33, and the switch assembly 20 (not shown in Figures 1a and 10b) is fixed to the heat sink 34. The housing 31 and the cover plate 32 form a sealed structure.

[0083] In some embodiments, the sidewalls of the housing 31 are provided with heat dissipation holes. The housing 31 and the cover plate 32 are made of metal, and the support plate 33 may be made of insulating material. In this embodiment, the housing 31 and the cover plate 32 are made of aluminum-zinc coated steel.

[0084] It is understood that, in addition to the above-mentioned components or parts, the capacitor parameters and quantities of the test module 10 can be adjusted and optimized according to actual test needs, and other functional structures can be added as needed. This application embodiment does not limit this.

[0085] Furthermore, this application also provides a testing device, as shown in FIG11. The testing device 100 includes multiple test modules 10 as described above. The multiple test modules 10 are cascaded and connected to the semiconductor device under test (not shown in FIG11). In the embodiment of this application, the testing device 100 is provided with four test modules 10. The four test modules 10 are cascaded to form a 12kV testing device. The four test modules 10 are connected and led out to the semiconductor device under test using a cascaded busbar C. The cascaded busbar C structure is designed according to the principle of positive and negative parallelism, reverse polarity, and minimum safe distance to avoid unnecessary connection transitions and to reduce parasitic stray inductance.

[0086] The electrical structure diagram corresponding to the test device 100 can be found in Figure 12. In Figure 12, the test device 100 includes four test modules 10. The four test modules 10 are cascaded and connected to the DUT1 (i.e., the IGBT under test).

[0087] The above are merely embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application shall be included within the scope of the claims of this application pending approval. Industrial applicability

[0088] This application relates to a test module and test apparatus, including a capacitor assembly, a switch assembly, and a frame assembly. Both the capacitor assembly and the switch assembly are located inside the frame assembly and are connected to the semiconductor device under test (DUT). The switch assembly includes a protection switch connected to the capacitor assembly. During DC pulse capacitor discharge, the protection switch provides overvoltage protection to the capacitor bank, preventing damage to the DUT and the test module. In other words, the test module provided in this application has high reliability. The switch busbar, designed according to the device connection method and layout, has a short loop distance, low parasitic inductance due to repeated connections, and low stray inductance, effectively solving the problem of voltage and current overshoot caused by parasitic inductance under high current change rate conditions. This ensures that the switch busbar not only meets the required withstand voltage, insulation, and heat dissipation requirements but also effectively improves issues such as turn-off voltage spikes and voltage / current waveform distortion, reducing voltage stress on the DUT.

Claims

1. A test module, the test module comprising: A capacitor assembly, a switch assembly, and a frame assembly are provided; both the capacitor assembly and the switch assembly are located inside the frame assembly and are connected to the semiconductor device under test; wherein the switch assembly includes a protection switch, which is connected to the capacitor assembly.

2. The test module according to claim 1, wherein, The capacitor assembly includes multiple capacitor banks and a busbar; the multiple capacitor banks are connected in parallel through the busbar. The capacitor bank includes multiple DC pulse capacitors connected in parallel.

3. The test module according to claim 2, wherein, The busbar includes a first insulating layer, a negative electrode plate, a second insulating layer, a positive electrode plate, and a third insulating layer stacked sequentially along a first direction.

4. The test module according to claim 3, wherein, The positive electrode plate is provided with a first sealed mounting hole; the first sealed mounting hole penetrates the negative electrode plate and is insulated from the negative electrode plate, and the positive electrode plate is connected to the positive terminal of the capacitor bank through the first sealed mounting hole; the insulation voltage between the first sealed mounting hole and the negative electrode plate is greater than or equal to 1.5 times the terminal voltage of the DC pulse capacitor. The negative electrode plate is provided with a second sealed mounting hole; the second sealed mounting hole penetrates the positive electrode plate and is insulated from the positive electrode plate, and the negative electrode plate is connected to the negative terminal of the capacitor bank through the second sealed mounting hole; the insulation voltage between the second sealed mounting hole and the positive electrode plate is greater than or equal to 1.5 times the terminal voltage of the DC pulse capacitor.

5. The test module according to any one of claims 1 to 4, wherein, The switching assembly further includes a changeover switch, a protective fuse, an absorption capacitor, a voltage equalization branch, and a switch busbar; wherein, the voltage equalization branch includes a voltage equalization capacitor and a voltage equalization resistor connected in parallel; The switching switch and the protection switch are fixed on one side of the switch busbar, and the protection fuse, the absorption capacitor and the voltage equalization branch are fixed on the other side of the switch busbar. The protection switch is connected to the protection fuse, the capacitor assembly, the absorption capacitor, the switching switch and the voltage equalization branch through the switch busbar. The protection fuse is connected to the switching switch and the absorption capacitor through the switch busbar. The switching switch is connected to the voltage equalization branch through the switch busbar.

6. The test module according to claim 5, wherein, The switch busbar includes a fourth insulating layer, a negative terminal busbar, a fifth insulating layer, a positive terminal busbar, a sixth insulating layer, a switching busbar, and a seventh insulating layer stacked along a first direction.

7. The test module according to claim 6, wherein, The positive terminal busbar includes multiple first terminals, second terminals, and third terminals; The plurality of first terminals are led out in parallel along a first direction, and the second terminal and the third terminal are led out in opposite directions along a second direction, wherein the first direction is perpendicular to the second direction; Each first terminal is connected to the first end of the protective fuse, the second terminal is connected to the cathode of the first diode in the protective switch, and the third terminal is connected to the positive plate.

8. The test module according to claim 6, wherein, The negative terminal busbar includes multiple fourth terminals, multiple fifth terminals, a sixth terminal, a seventh terminal, and an eighth terminal; Each of the plurality of fifth terminals and the sixth terminal are led out in parallel along a first direction, and each of the plurality of fourth terminals, the seventh terminal and the eighth terminal are led out in the opposite direction along a second direction, wherein the first direction is perpendicular to the second direction; The fourth terminal is connected to the anode of the second diode in the switching switch, the fifth terminal is connected to the absorption capacitor, the sixth terminal is connected to the second end of the equalizing branch, the seventh terminal is connected to the second electrode of the first fully controllable semiconductor device in the protection switch, and the eighth terminal is connected to the negative electrode plate.

9. The test module according to claim 6, wherein, The switching busbar includes multiple positive busbars and negative busbars; Each of the plurality of positive busbars is an L-shaped structure. The negative busbar includes a ninth terminal, a tenth terminal, and an eleventh terminal. The ninth terminal is led out along a third direction, the tenth terminal is led out along a first direction, and the eleventh terminal is led out along a second direction. The first direction, the second direction, and the third direction are perpendicular to each other. Each positive busbar is connected to the second terminal of the protective fuse and the first terminal of the second fully controllable semiconductor device in the switching switch. The ninth terminal is connected to the second terminal of the second fully controllable semiconductor device. The tenth terminal is connected to the first terminal of the equalizing branch. The eleventh terminal is connected to the semiconductor device under test.

10. The test module according to any one of claims 1 to 4, wherein, The frame assembly includes a housing shell, a cover plate, a support plate, and a heat sink; The capacitor assembly is fixed to the side wall of the housing shell, the support plate is fixed inside the housing shell, the heat sink is fixed to the support plate, the switch assembly is fixed to the heat sink, and the housing shell and the cover plate form a sealed structure.

Images