Test circuit, test method and chip stack structure

Abstract

Provided in the present disclosure are a test circuit, a test method and a chip stack structure. The test circuit is applied to a logic chip, and comprises a first register module, which is electrically connected to a first path and a first through silicon via of the logic chip, wherein when a first test enable signal is at a first level, the first register module is configured as a linear feedback shift register, and receives a first test signal at a first speed by means of the first path; and when the first test enable signal is at a second level, the first register module is configured as an ordinary shift register, and serially outputs values in the first register module on the basis of a serial test protocol, so as to obtain a first test result signal. The present disclosure at least facilitates a speed test of a logic chip before stacking, thereby saving on test costs.

Description

Test circuit, test method and chip stacking structure

[0001] This application claims priority to Chinese Patent Application No. 202411533604.2, filed on October 31, 2024, entitled “Test Circuit, Test Method and Chip Stacking Structure”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to the field of semiconductor technology, and in particular to a test circuit, a test method, and a chip stacking structure. Background Technology

[0003] With the development of integrated circuit technology, the manufacturing process of semiconductor devices has made significant progress. However, in recent years, the development of two-dimensional semiconductor technology has encountered various challenges: physical limits, limitations of existing development techniques, and limits of stored electron density. Against this backdrop, to address the difficulties encountered in two-dimensional semiconductor devices and to pursue lower production costs per unit memory cell, bonding processes (e.g., hybrid bonding, bumping, wire bonding) can be used to stack multiple chips to form three-dimensional semiconductor devices. Testing three-dimensional semiconductor devices, such as high-bandwidth memory (HBM), is characterized by long and complex processes, leading to high testing costs. Summary of the Invention

[0004] This disclosure provides a test circuit, test method, and chip stacking structure, which at least facilitates speed testing of logic chips before stacking and saves test costs.

[0005] In a first aspect, embodiments of this disclosure provide a test circuit applied to a logic chip, comprising:

[0006] The first register module is electrically connected to the first path and the first through-silicon via of the logic chip. When the first test enable signal is at the first level, it is configured as a linear feedback shift register to receive the first test signal at the first speed through the first path. When the first test enable signal is at the second level, it is configured as a normal shift register to serially output the values ​​in the first register module according to the serial test protocol to obtain the first test result signal.

[0007] In some embodiments, the test circuit further includes:

[0008] The second register module is electrically connected to the second path and the second through-silicon via of the logic chip. In the write path test mode of the second path, when the second test enable signal is at the first level, it is configured as a linear feedback shift register to receive the second test signal at the first speed through the write path of the second path. When the second test enable signal is at the second level, it is configured as a normal shift register to serially output the values ​​in the second register module according to the serial test protocol to obtain the second test result signal. In the read path test mode of the second path, when the second test enable signal is at the second level, it is configured as a normal shift register to write the initial value to the second register module according to the serial test protocol. When the second test enable signal is at the first level, it is configured as a linear feedback shift register to generate pseudo-random data and output the pseudo-random data at the first speed through the read path of the second path.

[0009] In some embodiments, the first path is a command address path for transmitting the command address signal of the logic chip, and the second path is a data path for transmitting the data signal of the logic chip.

[0010] In some embodiments, the first path includes a first receiver, a command decoder, and a first sampling circuit, wherein the first receiver is electrically connected to the command address port of the logic chip; the write path in the second path includes a second receiver, a first serial-to-parallel conversion circuit, and a first transmitter, wherein the second receiver is electrically connected to the data port of the logic chip, and the first transmitter is electrically connected to the second through-silicon via; the read path in the second path includes a third receiver, a second serial-to-parallel conversion circuit, and a second transmitter, wherein the third receiver is electrically connected to the second through-silicon via, and the second transmitter is electrically connected to the data port.

[0011] In some embodiments, the first test signal is sent by the host and transmitted to the first register module via the command address port of the logic chip and the first path; the second test signal is sent by the host and transmitted to the second register module via the data port of the logic chip and the write path in the second path; the pseudo-random data is transmitted to the host via the first transmitter, the read path in the second path and the data port.

[0012] In some embodiments, the first test signal is sent by the test interface circuit of the logic chip and transmitted to the first register module via a third transmitter electrically connected to the command address port and the first path; the second test signal is sent by the test interface circuit of the logic chip and transmitted to the second register module via the second serial-to-parallel conversion circuit, the second transmitter, and the write path in the second path; the pseudo-random data is transmitted to the multi-input shift register of the logic chip via the first transmitter, the third receiver, and the second serial-to-parallel conversion circuit.

[0013] In some embodiments, the first register module includes:

[0014] The first input selection unit is configured such that a first input terminal receives the first test signal, a second input terminal receives test data written according to a serial test protocol, a control terminal receives the first test enable signal, and when the first test enable signal is at a first level, the output terminal outputs the signal received by the first input terminal, and when the first test enable signal is at a second level, the output terminal outputs the signal received by the second input terminal.

[0015] The first clock selection unit is configured to receive a first clock signal at a first input terminal and a second clock signal at a second input terminal. When the first test enable signal is at a first level, it outputs the signal received at the first input terminal; when the first test enable signal is at a second level, it outputs the signal received at the second input terminal. The first clock signal is used to sample the command address signal of the logic chip, and the second clock signal is a clock signal under a serial test protocol.

[0016] The first register unit includes a first AND gate, a second AND gate, a first XOR gate, a second XOR gate, and M single-edge flip-flops. The first input of the first AND gate receives the first test enable signal, and its second input is electrically connected to the output of the Mth single-edge flip-flop. The first input of the first XOR gate is electrically connected to the output of the first AND gate, and its second input is electrically connected to the output of the first input selection unit. The first input of the second AND gate receives the first test enable signal, and its second input is electrically connected to the output of the Mth single-edge flip-flop. The first input of the second XOR gate is electrically connected to the output of the second AND gate, and its second input is electrically connected to the output of the Nth single-edge flip-flop. The outputs of the single-edge flip-flops are electrically connected; the input of the first single-edge flip-flop is electrically connected to the output of the first XOR gate, the input of the i-th single-edge flip-flop is electrically connected to the output of the (i-1)-th single-edge flip-flop, the input of the (N+1)-th single-edge flip-flop is electrically connected to the output of the second XOR gate, the input of the j-th single-edge flip-flop is electrically connected to the output of the (j-1)-th single-edge flip-flop, and the output of the M-th single-edge flip-flop outputs the first test result signal. The clock terminals of the M single-edge flip-flops are all electrically connected to the output of the first clock selection unit; where M, N, i, and j are all positive integers, M>N, 2≤i≤N, and (N+1)-th single-edge flip-flops output the first test result signal. <j≤M。

[0017] In some embodiments, M = 5 and N = 2.

[0018] In some embodiments, the second register module includes:

[0019] The second input selection unit is configured such that the first input terminal receives the second test signal, the second input terminal receives test data written according to the serial test protocol, the control terminal receives the second test enable signal, and when the second test enable signal is at a first level, the output terminal outputs the signal received by the first input terminal, and when the second test enable signal is at a second level, the output terminal outputs the signal received by the second input terminal.

[0020] The second clock selection unit is configured such that its first input terminal receives a third clock signal, its second input terminal receives a fourth clock signal, and its third input terminal receives a fifth clock signal. When the second test enable signal is at a second level, its first output terminal outputs the signal received by the first input terminal. When the second test enable signal is at a first level, and in the mode of testing the write path in the second path, its first output terminal outputs the signal received by the second input terminal. When the second test enable signal is at a first level, and in the mode of testing the read path in the second path, its first output terminal outputs the signal received by the third input terminal. The signal output by the first output terminal is denoted as the sixth clock signal, and the signal output by the second output terminal is denoted as the seventh clock signal, the seventh clock signal being out of phase with the sixth clock signal. The third clock signal is a clock signal under a serial test protocol, the fourth clock signal is a clock signal used in the write path of the second path, and the fifth clock signal is a clock signal used in the read path of the second path.

[0021] The second register unit includes a third AND gate, a fourth AND gate, a third XOR gate, a fourth XOR gate, and A dual-edge flip-flops. The first input of the third AND gate receives the second test enable signal, and its second input is electrically connected to the output of the A dual-edge flip-flop. The first input of the third XOR gate is electrically connected to the output of the third AND gate, and its second input is electrically connected to the output of the second input selection unit. The first input of the fourth AND gate receives the second test enable signal, and its second input is electrically connected to the output of the A dual-edge flip-flop. The first input of the fourth XOR gate is electrically connected to the output of the fourth AND gate, and its second input is electrically connected to the output of the B dual-edge flip-flop. The connections are as follows: the input of the first dual-edge flip-flop is electrically connected to the output of the third XOR gate; the input of the x-th dual-edge flip-flop is electrically connected to the output of the (x-1)-th dual-edge flip-flop; the input of the (B+1)-th dual-edge flip-flop is electrically connected to the output of the fourth XOR gate; the input of the y-th dual-edge flip-flop is electrically connected to the output of the (y-1)-th dual-edge flip-flop; the output of the A-th dual-edge flip-flop outputs the second test result signal or the pseudo-random data; the first clock terminals of the A dual-edge flip-flops all receive the sixth clock signal, and the second clock terminals all receive the seventh clock signal; wherein A, B, x, and y are all positive integers, A>B, 2≤x≤B, and (B+1)-th dual-edge flip-flops... <y≤A。

[0022] In some embodiments, A = 5 and B = 2.

[0023] In some embodiments, the dual-edge flip-flop samples in response to the rising edge of the clock signal received at the first clock terminal when the second test enable signal is at the second level, and samples in response to the rising and falling edges of the clock signal received at the first clock terminal when the second test enable signal is at the first level.

[0024] In some embodiments, the dual-edge trigger includes:

[0025] The first gated inverter is configured such that its input terminal is electrically connected to the input terminal of the dual-edge flip-flop, and its control terminal is electrically connected to the second clock terminal of the dual-edge flip-flop.

[0026] The first inverter is configured such that its input is electrically connected to the reset terminal of the dual-edge flip-flop;

[0027] The first NOR gate is configured such that its first input is electrically connected to the output of the first gated inverter, and its second input is electrically connected to the output of the first inverter.

[0028] The second gated inverter is configured such that its input is electrically connected to the output of the first NOR gate, and its control is electrically connected to the first clock terminal of the dual-edge flip-flop.

[0029] The third gated inverter is configured such that its input is electrically connected to the output of the first NOR gate, its control terminal is electrically connected to the first clock terminal of the dual-edge flip-flop, and its output is electrically connected to the first input of the first NOR gate.

[0030] The second inverter is configured such that its input is electrically connected to the output of the second gated inverter, and its output is electrically connected to the output of the dual-edge flip-flop.

[0031] The fourth gated inverter is configured such that its input terminal is electrically connected to the input terminal of the dual-edge flip-flop, and its control terminal is electrically connected to the first clock terminal of the dual-edge flip-flop.

[0032] The fifth AND gate is configured such that its first input is electrically connected to the second test enable signal, its second input is electrically connected to the output of the fourth gated inverter, and its output is electrically connected to the second input of the second NOR gate.

[0033] The second NOR gate is configured such that its first input is electrically connected to the output of the first NAND gate;

[0034] The fifth gated inverter is configured such that its input is electrically connected to the output of the second NOR gate, its control terminal is electrically connected to the second clock terminal of the dual-edge flip-flop, and its output is electrically connected to the input of the second inverter.

[0035] The sixth gated inverter is configured such that its input is electrically connected to the output of the second NOR gate, its control terminal is electrically connected to the second clock terminal of the dual-edge flip-flop, and its output is electrically connected to the second input of the fifth AND gate.

[0036] The first OR gate is configured such that its first input is electrically connected to the second test enable signal, and its second input is electrically connected to the output of the dual-edge flip-flop.

[0037] The first NAND gate is configured such that its first input is electrically connected to the reset terminal of the dual-edge flip-flop, and its second input is electrically connected to the output terminal of the first OR gate.

[0038] In some embodiments, the serial test protocol is the IEEE 1500 test protocol.

[0039] Secondly, embodiments of this disclosure provide a testing method applied to a logic chip, comprising:

[0040] A first test signal is written to the first register module of the logic chip through the first path of the logic chip at a first speed;

[0041] Control the first register module to operate in linear feedback shift register mode;

[0042] The first register module is controlled to operate in the mode of a normal shift register. According to the serial test protocol, the values ​​in the first register module are serially output to obtain the first test result signal.

[0043] The first test result signal is compared with the expected value to determine whether the first path of the logic chip can work normally at the first speed;

[0044] The first register module is electrically connected to the first through-silicon via of the logic chip.

[0045] In some embodiments, the testing method further includes:

[0046] A second test signal is written to the second register module of the logic chip at a first speed via the write path in the second path of the logic chip.

[0047] Control the second register module to operate in linear feedback shift register mode;

[0048] The second register module is controlled to operate in the mode of a normal shift register. According to the serial test protocol, the values ​​in the second register module are serially output to obtain the second test result signal.

[0049] The second test result signal is compared with the expected value to determine whether the write path in the second path of the logic chip can work normally at the first speed;

[0050] The second register module is electrically connected to the second through-silicon via of the logic chip.

[0051] In some embodiments, the testing method further includes:

[0052] Control the second register module to operate in normal shift register mode, and write initial values ​​to the second register module according to the serial test protocol;

[0053] The second register module is controlled to operate in linear feedback shift register mode to generate pseudo-random data;

[0054] The pseudo-random data is output at a first speed via the read path in the second path;

[0055] The pseudo-random data is compared with the expected value to determine whether the read path in the second path of the logic chip can work normally at the first speed.

[0056] Thirdly, embodiments of this disclosure provide a chip stacking structure, including a logic chip and at least one stacking unit, wherein the logic chip and at least one stacking unit are stacked sequentially along a first direction; each stacking unit includes a plurality of memory chips stacked sequentially along the first direction, wherein the first direction is perpendicular to the top surface of each memory chip;

[0057] The logic chip includes the test circuit as described in the first aspect.

[0058] The technical solutions provided in this disclosure have at least the following advantages:

[0059] By designing a test circuit, speed tests are performed on the logic chips, allowing some testing of the HBM device to be moved forward. That is, the logic chips are tested before stacking, and logic chips that meet the speed requirements are selected and then stacked with memory chips. This can greatly reduce testing and stacking costs. Attached Figure Description

[0060] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings represent similar elements. Unless otherwise stated, the figures in the drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0061] Figure 1 is a schematic diagram of a test circuit and logic chip provided in an embodiment of this disclosure;

[0062] Figure 2 is a schematic diagram of another test circuit and logic chip provided in an embodiment of this disclosure;

[0063] Figure 3 is a schematic diagram of a specific test circuit and logic chip provided in an embodiment of this disclosure;

[0064] Figure 4 is a schematic diagram of another specific test circuit and logic chip provided in an embodiment of this disclosure;

[0065] Figure 5 is a circuit diagram of a first register module provided in an embodiment of this disclosure;

[0066] Figure 6a is an equivalent circuit diagram of the first register unit in one case;

[0067] Figure 6b shows the equivalent circuit diagram of the first register unit in another case;

[0068] Figure 7 is a circuit diagram of a second register module provided in an embodiment of this disclosure;

[0069] Figure 8 shows the equivalent circuit diagram of the second register unit in one case;

[0070] Figure 9 is a circuit diagram of a dual-edge flip-flop provided in an embodiment of this disclosure;

[0071] Figure 10 is a flowchart of a testing method provided in an embodiment of this disclosure;

[0072] Figure 11 is a flowchart of another testing method provided in an embodiment of this disclosure;

[0073] Figure 12 is a flowchart of another testing method provided in an embodiment of this disclosure;

[0074] Figure 13 is a schematic diagram of a chip stacking structure provided in an embodiment of this disclosure. Detailed Implementation

[0075] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It is understood that the specific embodiments described herein are merely for explaining the relevant applications and not for limiting the applications. It should also be noted that, for ease of description, only the parts related to the relevant applications are shown in the accompanying drawings. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to limit this disclosure. In the following description, references to "some embodiments" describe a subset of all possible embodiments; however, it is understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with each other without conflict. It should be noted that the terms "first, second, third" involved in the embodiments of this disclosure are only used to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0076] Dynamic Random Access Memory (DRAM)

[0077] Synchronous Dynamic Random Access Memory (SDRAM)

[0078] Double Data Rate SDRAM (DDR)

[0079] Low-power DDR (LPDDR)

[0080] High-bandwidth memory (HBM)

[0081] Through Silicon Via (TSV)

[0082] Command (CMD)

[0083] Linear Feedback Shift Register (LFSR)

[0084] Multi-input Shift Register (MISR)

[0085] HBM devices consist of stacked logic and memory chips, and testing HBM devices is characterized by a long and complex process. Speed-related testing of HBM devices mainly focuses on the stacked logic and memory chips. Even if some devices are found to be slow, the stacked logic and memory chips must be discarded, resulting in high testing costs.

[0086] Based on this, this disclosure provides a test circuit applied to a logic chip, comprising: a first register module electrically connected to a first path and a first through-silicon via (TSV) of the logic chip; configured as a linear feedback shift register when the first test enable signal is at a first level, receiving a first test signal at a first speed through the first path; and configured as a general-purpose shift register when the first test enable signal is at a second level, serially outputting the values ​​in the first register module according to a serial test protocol to obtain a first test result signal. Thus, by designing the test circuit, speed testing of the logic chip is performed, allowing some testing of the HBM device to be moved forward, i.e., the logic chip is tested before stacking, screening out logic chips with acceptable speeds before stacking with memory chips. This significantly reduces testing and stacking costs.

[0087] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0088] In one embodiment of this disclosure, referring to FIG1, a schematic diagram of the structure of a logic chip 40 provided in this embodiment of the disclosure is shown. The logic chip 40 includes a test circuit 10. As shown in FIG1, the test circuit 10 includes:

[0089] The first register module 11 is electrically connected to the first path 20 and the first through-silicon via 30 of the logic chip 40. When the first test enable signal is at the first level, it is configured as a linear feedback shift register (LFSR) to receive the first test signal at the first speed through the first path 20. When the first test enable signal is at the second level, it is configured as a general shift register to serially output the values ​​in the first register module 11 according to the serial test protocol to obtain the first test result signal.

[0090] When performing a speed test on the first path 20 of logic chip 40, logic chip 40 can be set to run at a first speed, and a first test signal can be written to the first register module 11 at the first speed through the first path 20. At this time, by setting the first test enable signal to a first level, the first register module 11 is configured as an LFSR. The working principle of the LFSR is that it generates different output data in different clock cycles according to the input signal and the structure of the LFSR. The working principle of the LFSR is to perform a polynomial division. The structure of the LFSR represents an intrinsic polynomial, that is, the divisor. The input signal of the LFSR represents the exponent of the dividend in the polynomial division, and the output data represents the exponent of the remainder in the polynomial division. The number of bits of the output data is the same as the number of flip-flops (DFFs) in the LFSR structure. For example, if the LFSR includes 5 DFFs, then the LFSR output data will be 5 bits. If the first test signal includes 16 bits of data, the LFSR will receive all 16 bits of data within 16 clock cycles. After the 16th clock cycle, the data output by each DFF in the LFSR is related to the exponent of the remainder after polynomial division. At this time, the first test enable signal is set to the second level, the first register module 11 is configured as a general-purpose shift register, and the value in the first register module 11 is serially output according to the serial test protocol, that is, the result of each DFF in the original LFSR is serially output to obtain the first test result signal. If the first test result signal is consistent with the expected value, it means that the first test signal was transmitted from the first path 20 to the first register module 11 without error at the first speed, which means that the first path 20 of the logic chip 40 can operate normally at the first speed, that is, it has passed the test at the first speed. It is understandable that different first speeds can be set, and the value of the first speed can be continuously increased to test the maximum speed at which the logic chip 40 can operate normally. Logic chips that pass the speed test are then stacked with memory chips, which can greatly reduce testing costs and stacking costs.

[0091] The logic chip includes multiple through-silicon vias (TSVs), each with its corresponding first register module for speed testing. In a test mode based on a serial test protocol, each TSV can be connected in series, meaning the first test result signal output from the first register module corresponding to each TSV is serially output. The overall serially output data is compared with the expected value to determine if the logic chip can operate normally at that first speed. When writing the first test signal, the first mode register module 11 is set to an LFSR, primarily for data compression to improve test efficiency. To improve test accuracy and reliability, a large amount of data needs to be written to the first path 20. Without data compression, the output test data would be extremely large, and given the numerous TSVs in the logic chip, test efficiency would be very low. Using an LFSR, regardless of the number of bits in the first test signal data, the number of output bits is fixed, as mentioned earlier, determined by the LFSR structure. For example, if the LFSR includes 5 DFFs, then the LFSR output data will be 5 bits. Regardless of the amount of data in the first test signal, the output data of the first register module 11 corresponding to the first through-silicon via (TSV) will be 5 bits. Multiplying this by the number of TSVs in the logic chip 40 gives the total number of bits of test data output according to the serial test protocol test mode. In this way, using the LFSR can greatly compress the amount of data that needs to be tested and improve test efficiency.

[0092] In some embodiments, the serial test protocol is the IEEE 1500 test protocol.

[0093] In some embodiments, as shown in FIG2, the test circuit 10 further includes:

[0094] The second register module 12 is electrically connected to the second path 60 and the second through-silicon via 50 of the logic chip 40. In the write path 61 mode of the second test path, when the second test enable signal is at the first level, it is configured as a linear feedback shift register and receives the second test signal at the first speed through the write path 61 of the second path. When the second test enable signal is at the second level, it is configured as a normal shift register and serially outputs the values ​​in the second register module 12 according to the serial test protocol to obtain the second test result signal. In the read path 62 mode of the second test path, when the second test enable signal is at the second level, it is configured as a normal shift register and writes the initial value to the second register module 12 according to the serial test protocol. When the second test enable signal is at the first level, it is configured as a linear feedback shift register and generates pseudo-random data, which is output at the first speed through the read path 62 of the second path.

[0095] In some embodiments, the first path 20 is a command address path used to transmit the command address signal of the logic chip 40, and the second path 60 is a data path used to transmit the data signal of the logic chip 40.

[0096] In the test mode of write path 61 in the second path 60, the test method is similar to that of the first path 20. When performing a speed test on write path 61 in the second path 60 of the logic chip 40, the logic chip 40 can be set to run at a first speed, and a second test signal is written to the second register module 12 at the first speed through write path 61 in the second path 60. At this time, the second register module 12 is configured as an LFSR by setting the second test enable signal to the first level. After all the second test signals have been received, the second test enable signal is set to the second level, and the second register module 12 is configured as a general shift register. According to the serial test protocol, the values ​​in the second register module 12 are serially output, that is, the results of each DFF in the original LFSR are serially output to obtain the second test result signal. If the second test result signal is consistent with the expected value, it means that the second test signal was transmitted from write path 61 in the second path 60 to the second register module 12 at the first speed without error, which means that write path 61 in the second path 60 of the logic chip 40 can run normally at the first speed, that is, it has passed the test at the first speed.

[0097] In the read path 62 mode of the second test path, when the second test enable signal is at the second level, the second register module 12 is configured as a general-purpose shift register, and an initial value is written to the second register module 12 according to the serial test protocol. The initial value is a non-all-zero seed value, meaning the initial value cannot be all zeros. After the initial value is written, the second test enable signal is set to the first level, and the second register module 12 is configured as an LFSR, allowing the LFSR to... n The system transitions between -1 states to generate pseudo-random data, where n is the number of DFFs in the LFSR. The pseudo-random data is output at the first speed via read path 62 in the second path 60 and compared with the expected value. If the output pseudo-random data matches the expected value, it indicates that the data output process from read path 62 in the second path 60 has not encountered any errors, meaning that read path 62 in the second path 60 of the logic chip 40 can operate normally at the first speed, thus passing the test at the first speed.

[0098] By designing the test circuit 10, the first path 20 and the second path 60 of the logic chip 40, i.e., the command address path and the data path, are tested at various speeds. Only when both the first path 20 and the second path 60 pass the speed test can it be said that the logic chip 40 can operate normally at that speed. In this way, logic chips that meet the speed requirements can be selected and then stacked with memory chips, which can greatly reduce testing and stacking costs.

[0099] In some embodiments, as shown in Figures 3 and 4, the first path 20 includes a first receiver 21, a command decoder 22, and a first sampling circuit 23, wherein the first receiver 21 is electrically connected to the command address port CA of the logic chip 40; the write path 61 in the second path 60 includes a second receiver 611, a first serial-to-parallel conversion circuit 612, and a first transmitter 613, wherein the second receiver 611 is electrically connected to the data port DQ of the logic chip 40, and the first transmitter 613 is electrically connected to the second through-silicon via 50; the read path 62 in the second path 60 includes a third receiver 623, a second serial-to-parallel conversion circuit 622, and a second transmitter 621, wherein the third receiver 623 is electrically connected to the second through-silicon via 50, and the second transmitter 621 is electrically connected to the data port DQ.

[0100] In the first path 20, the first receiver 21 is electrically connected to the command address port CA of the logic chip 40 to receive command address signals. The command decoder 22 decodes the command address signals to obtain the corresponding command or specific address. The first sampling circuit 23 samples the decoded command or address, synchronizes it with the clock, and simultaneously sends the sampled command and address to the first through-silicon via 30. In the second path 60, the second receiver 611 is electrically connected to the data port DQ of the logic chip 40 to receive data signals. The first serial-to-parallel conversion circuit 612 converts the data in the write path 61 from serial to parallel. The first transmitter 613 is electrically connected to the second through-silicon via 50 to drive the output data. In the read path 62, the third receiver 623 is electrically connected to the second through-silicon via 50 to receive data from the second through-silicon via 50. The second serial-to-parallel conversion circuit 622 converts the data in the read path 62 from parallel to serial. The second transmitter 621 is electrically connected to the data port DQ to drive the data.

[0101] In some embodiments, as shown in FIG3, a first test signal is sent by the host 70 and transmitted to the first register module 11 via the command address port CA of the logic chip 40 and the first path 20; a second test signal is sent by the host 70 and transmitted to the second register module 12 via the data port DQ of the logic chip 40 and the write path 61 in the second path 60; pseudo-random data is transmitted to the host 70 via the first transmitter 613, the read path 62 in the second path 60, and the data port DQ. Because the first transmitter 613 is electrically connected to the second register module 12, it can receive pseudo-random data. The output terminal of the first transmitter 613 is electrically connected to the second through-silicon via 50, and the input terminal of the third receiver 623 is also electrically connected to the second through-silicon via 50, so pseudo-random data can be sent to the read path 62 in the second path 60 through the first transmitter 613.

[0102] In some embodiments, as shown in FIG4, the first test signal is sent by the test interface circuit 80 of the logic chip 40 and transmitted to the first register module 11 via the third transmitter 41 electrically connected to the command address port CA and the first path 20; the second test signal is sent by the test interface circuit 80 of the logic chip 40 and transmitted to the second register module 12 via the second serial-to-parallel conversion circuit 622, the second transmitter 621, and the write path 61 in the second path 60; pseudo-random data is transmitted to the multi-input shift register 63 of the logic chip 40 via the first transmitter 613, the third receiver 623, and the second serial-to-parallel conversion circuit 622.

[0103] To avoid connecting too many circuits to the command address port CA and data port DQ, which would increase capacitive load and affect the quality of the received signal, the test interface circuit 80 on the logic chip 40 does not directly send test signals to the command address port CA and data port DQ. Since the output of the third transmitter 41 is electrically connected to the command address port CA, and the input of the first receiver 21 is also electrically connected to the command address port CA, the output of the third transmitter 41 and the input of the first receiver 21 can be electrically connected. The first test signal can then be sent to the first path 20 and transmitted to the first register module 11 via the third transmitter 41. Because the second test signal sent by the test interface circuit 80 is parallel data, it is first converted from parallel to serial via the second serial-to-parallel conversion circuit 622. Since the output of the second transmitter 621 and the input of the second receiver 611 are both electrically connected to the data port DQ, the second test signal can be sent to the write path 61 in the second path via the second transmitter 621, and then transmitted to the second register module 12. The pseudo-random data is transmitted to the multi-input shift register 63 of the logic chip 40 via the first transmitter 613, the third receiver 623, and the second serial-to-parallel conversion circuit 622, where it is compared with the expected value.

[0104] In some embodiments, as shown in FIG5, the first register module 11 includes:

[0105] The first input selection unit 111 is configured such that the first input terminal receives a first test signal, the second input terminal receives test data written according to a serial test protocol, the control terminal receives a first test enable signal, and when the first test enable signal is at a first level, the output terminal outputs the signal received by the first input terminal, and when the first test enable signal is at a second level, the output terminal outputs the signal received by the second input terminal.

[0106] The first clock selection unit 112 is configured to receive a first clock signal at its first input terminal and a second clock signal at its second input terminal. When the first test enable signal is at a first level, it outputs the signal received at the first input terminal; when the first test enable signal is at a second level, it outputs the signal received at the second input terminal. The first clock signal is used to sample the command address signal of the logic chip, and the second clock signal is a clock signal under a serial test protocol.

[0107] The first register unit 113 includes a first AND gate AND1, a second AND gate AND2, a first XOR gate XOR1, a second XOR gate XOR2, and M single-edge flip-flops (1131, 1132, 1133, 1134, and 1135 are shown as examples in the figure); the first input terminal of the first AND gate AND1 receives a first test enable signal, and the second input terminal is electrically connected to the output terminal of the Mth single-edge flip-flop; the first input terminal of the first XOR gate XOR1 is electrically connected to the output terminal of the first AND gate AND1, and the second input terminal is electrically connected to the output terminal of the first input selection unit; the first input terminal of the second AND gate AND2 receives the first test enable signal, and the second input terminal is electrically connected to the output terminal of the Mth single-edge flip-flop; the first input terminal of the second XOR gate XOR ... One input terminal is electrically connected to the output terminal of the second AND gate AND2, and the second input terminal is electrically connected to the output terminal of the Nth single-edge flip-flop; the input terminal of the 1st single-edge flip-flop is electrically connected to the output terminal of the first XOR gate XOR1, the input terminal of the i-th single-edge flip-flop is electrically connected to the output terminal of the (i-1)-th single-edge flip-flop, the input terminal of the (N+1)-th single-edge flip-flop is electrically connected to the output terminal of the second XOR gate XOR2, the input terminal of the j-th single-edge flip-flop is electrically connected to the output terminal of the (j-1)-th single-edge flip-flop, and the output terminal of the M-th single-edge flip-flop outputs the first test result signal. The clock terminals of the M single-edge flip-flops are all electrically connected to the output terminal of the first clock selection unit; where M, N, i, and j are all positive integers, M>N, 2≤i≤N, and (N+1)-th single-edge flip-flops output the first test result signal. <j≤M。

[0108] Understandably, when the first test enable signal is at the first level, the first register module 11 is configured as an LFSR (LForientation Register), requiring the reception of the first test signal. Therefore, the first input selection unit 111 outputs the first test signal to the first register unit 113, and the first clock selection unit 112 outputs the first clock signal to the first register unit 113. The first clock signal is used to sample the command address signal of the logic chip. Since the first path is the command address path, used to transmit the command address signal of the logic chip, when the first path transmits the first test signal during testing, the first clock signal also samples the first test signal, and the first register unit 113 also uses the first clock signal, which is beneficial for the smooth reception of the first test signal. When the first test enable signal is at the second level, the first register module 11 is configured as a general-purpose shift register, requiring the serial output of the value in the first register unit 113 according to the serial test protocol to obtain the first test result signal. Therefore, the first clock selection unit 112 outputs the second clock signal, which is the clock signal under the serial test protocol. The first input selection unit 111 outputs the test data written according to the serial test protocol. However, in this case, according to the serial test protocol, the value in the first register unit 113 needs to be serially output. Therefore, the test data written is empty, that is, no test data is written, or a fixed value that does not affect the serial output of the value in the first register unit 113 is written.

[0109] In some embodiments, M = 5 and N = 2. Referring to Figure 5, the first register unit 113 is shown as an example with M = 5 and N = 2. The M single-edge flip-flops can be composed of D flip-flops, wherein the reset terminal of the D flip-flops can be connected to the reset signal of the logic chip, or a reset signal indicating the end of the test, etc., which are not specifically shown in the figure.

[0110] Taking a high level as the first level and a low level as the second level, when the first test enable signal is at the first level, the first register unit 113 is configured as an LFSR, and its equivalent circuit is shown in Figure 6a. The first test signal enters the LFSR from the second input terminal Datain of the first XOR gate XOR1. Taking M=5 and N=2 as an example, the eigenpolynomial of this LFSR is P(x)=x 5 +x 2+1. As mentioned earlier, the LFSR works by performing a polynomial division. The structure of the LFSR represents an eigenpolynomial, i.e., the divisor. The input signal of the LFSR represents the exponent of the dividend in the polynomial division, and the output data represents the exponent of the remainder. The number of bits in the output data is the same as the number of flip-flops (DFFs) in the LFSR structure. Table 1 below shows a specific example. Datain represents one bit of data in the first test signal received in each step, i.e., each clock cycle, and Q... <1> …Q <5> This represents the output of each single-edge flip-flop in the LFSR. In the example in Table 1, the first test signal consists of 16 bits of data 0110101100111010, which enters the LFSR over 16 clock cycles. After the 16th clock cycle, the data Q output by each DFF in the LFSR is... <1> To Q <5> They are 11100 respectively.

[0111] Table 1

[0112] When the first test enable signal is at the second level, the first register unit 113 is configured as a general-purpose shift register, and its equivalent circuit is shown in Figure 6b. According to the serial test protocol, the value in the first register unit 113 is serially output, which is the data Q originally output by each DFF in the LFSR. <1> To Q <5> The first test result signal is obtained by serial output.

[0113] It should be noted that in Figures 6a and 6b, the connection of the clock terminal of each flip-flop is not specifically drawn, mainly to show the equivalent circuit of the first register unit 113 under different conditions. In fact, the clock terminal of each flip-flop is still connected to the output terminal of the first clock selection unit 112.

[0114] In some embodiments, as shown in FIG7, the second register module 12 includes:

[0115] The second input selection unit 121 is configured such that the first input terminal receives a second test signal, the second input terminal receives test data written according to the serial test protocol, the control terminal receives a second test enable signal, and when the second test enable signal is at a first level, the output terminal outputs the signal received by the first input terminal, and when the second test enable signal is at a second level, the output terminal outputs the signal received by the second input terminal.

[0116] The second clock selection unit 122 is configured such that its first input terminal receives a third clock signal, its second input terminal receives a fourth clock signal, and its third input terminal receives a fifth clock signal. When the second test enable signal is at a second level, its first output terminal outputs the signal received by the first input terminal. When the second test enable signal is at a first level, and in the mode of writing path 61 in the second test path 60, its first output terminal outputs the signal received by the second input terminal. When the second test enable signal is at a first level, and in the mode of reading path 62 in the second test path 60, its first output terminal outputs the signal received by the third input terminal. The signal output by the first output terminal is denoted as the sixth clock signal, and the signal output by the second output terminal is denoted as the seventh clock signal. The seventh clock signal is out of phase with the sixth clock signal. The third clock signal is the clock signal under the serial test protocol, the fourth clock signal is the clock signal used in the writing path 61 in the second path 60, and the fifth clock signal is the clock signal used in the reading path 62 in the second path 60.

[0117] The second register unit 123 includes a third AND gate AND3, a fourth AND gate AND4, a third XOR gate XOR3, a fourth XOR gate XOR4, and A dual-edge flip-flops (1231, 1232, 1233, 1234, and 1235 are shown as examples in the figure); the first input of the third AND gate AND3 receives the second test enable signal, and the second input is electrically connected to the output of the A dual-edge flip-flops; the first input of the third XOR gate XOR3 is electrically connected to the output of the third AND gate AND3, and the second input is electrically connected to the output of the second input selection unit; the first input of the fourth AND gate AND4 receives the second test enable signal, and the second input is electrically connected to the output of the A dual-edge flip-flops; the first input of the fourth XOR gate XOR4 is electrically connected to the output of the fourth AND gate AND4; the first input of the fourth AND gate XOR4 is electrically connected to the output of the fourth AND gate AND4; the first input of the fourth AND gate XOR4 is electrically connected to the output of the second ... The output of gate AND4 is electrically connected, and its second input is electrically connected to the output of the B-th dual-edge flip-flop; the input of the 1st dual-edge flip-flop is electrically connected to the output of the third XOR gate XOR3; the input of the x-th dual-edge flip-flop is electrically connected to the output of the (x-1)-th dual-edge flip-flop; the input of the (B+1)-th dual-edge flip-flop is electrically connected to the output of the fourth XOR gate XOR4; the input of the y-th dual-edge flip-flop is electrically connected to the output of the (y-1)-th dual-edge flip-flop; the output of the A-th dual-edge flip-flop outputs the second test result signal or pseudo-random data; the first clock input of each of the A dual-edge flip-flops receives the sixth clock signal, and the second clock input receives the seventh clock signal; where A, B, x, and y are all positive integers, A>B, 2≤x≤B, and (B+1) <y≤A。

[0118] In some embodiments, A = 5 and B = 2. Referring to Figure 7, the second register unit 123 is shown as an example with A = 5 and B = 2.

[0119] In the mode of writing path 61 in the second path 60 test, when the second test enable signal is at the first level, the second register module 12 is configured as an LFSR and needs to receive the second test signal. Therefore, the second input selection unit 121 outputs the second test signal to the second register unit 123, and the second clock selection unit 122 outputs the fourth clock signal to the second register unit 123. The fourth clock signal is the clock signal used in the write path 61 of the second path 60. In this way, the second register unit 123 uses the same clock as the write path 61, which is beneficial to the smooth reception of the second test signal. At this time, the second register unit 123 is configured as an LFSR, and its equivalent circuit diagram is shown in Figure 6a. Its working principle is similar to that of the first register unit 113 mentioned above, and will not be described again here. In the mode of writing path 61 in the second path 60 test, when the second test enable signal is at the second level, the second clock selection unit 122 outputs the third clock signal, which is the clock signal under the serial test protocol. The second input selection unit 121 outputs the test data written according to the serial test protocol. However, in this case, according to the serial test protocol, the value in the second register unit 123 needs to be serially output, so the written test data is empty, that is, no test data is written, or a fixed value that does not affect the serial output of the value in the second register unit 123 is written. The second register unit 123 is configured as a general shift register, and its equivalent circuit diagram is shown in Figure 6b. According to the serial test protocol, the value in the second register unit 123 is serially output to obtain the second test result signal. It can be understood that in the mode of writing path 61 in the second path 60, the working principle of the second register module 12 is similar to the working principle of the first register module 11 when testing the first path 20.

[0120] In the mode of reading path 62 in the second path 60, when the second test enable signal is at the second level, the second input selection unit 121 outputs the test data written according to the serial test protocol, and the second clock selection unit 122 outputs the third clock signal, which is the clock signal under the serial test protocol. The second register unit 123 is configured as a general-purpose shift register, and its equivalent circuit diagram is shown in Figure 6b. According to the serial test protocol, the initial value is written to the second register unit 123 through the second input selection unit 121. After the initial value is written, the second test enable signal is set to the first level, and the second input selection unit 121 outputs the second test signal to the second register unit 123. Since the read path is being tested at this time, the second test signal is empty or a fixed value that does not affect the operation of the LFSR at this time, such as 0. The second clock selection unit 122 outputs the fifth clock signal to the second register unit 123. The fifth clock signal is the clock signal used in the read path 62 in the second path 60. In this way, the second register unit 123 uses the same clock as the read path 62, which is beneficial for the second register unit to output data smoothly. At this point, the second register unit 123 is configured as an LFSR to generate pseudo-random data, and its equivalent circuit diagram is shown in Figure 8. In this example, the LFSR includes 5 flip-flops, so the LFSR can jump between 31 states to generate pseudo-random data. Table 2 below shows a specific example. In step 0, the initial value 10000 is written, and the output Q of each flip-flop in steps 1 to 30... <1> To Q <5> As shown in the table. In Step 31, Q <1> To Q <5> The value returns to 10000, and the process restarts, adjusting between 31 states. The pseudo-random data output by the LFSR is the output Q of the last trigger. <5> .

[0121] Table 2

[0122] It should be noted that in Figure 8, the clock connection is not shown primarily to illustrate the equivalent circuit of the second register unit 123. In reality, the first clock input of each dual-edge flip-flop receives the sixth clock signal, and the second clock input receives the seventh clock signal; the sixth and seventh clock signals are out of phase. Dual-edge flip-flops can also have a reset input, which is not shown in Figures 7 and 8. This reset input can be connected to the reset signal of the logic chip, or a reset signal indicating the end of a test, etc.

[0123] In some embodiments, the dual-edge flip-flop samples in response to the rising edge of the clock signal received at the first clock terminal when the second test enable signal is at the second level, and samples in response to both the rising and falling edges of the clock signal received at the first clock terminal when the second test enable signal is at the first level. Because the reception of the second test signal or the output of pseudo-random data is in high-speed mode in the write path 61 or read path 62 mode of the second test path 60, the dual-edge flip-flop needs to sample on both the rising and falling edges of the clock. However, in the test mode according to the serial test protocol, neither the serial output of the second test result signal nor the writing of the initial value requires very high speed, so the dual-edge flip-flop can sample only on the rising edge of the clock, saving power consumption.

[0124] In some embodiments, as shown in FIG9, the dual-edge trigger includes:

[0125] The first gated inverter G1 is configured such that its input terminal is electrically connected to the input terminal D of a dual-edge flip-flop, and its control terminal is electrically connected to the second clock terminal Clkb of the dual-edge flip-flop.

[0126] The first inverter N1 is configured such that its input is electrically connected to the reset terminal Rst of a dual-edge flip-flop;

[0127] The first NOR gate Nor1 is configured such that its first input is electrically connected to the output of the first gated inverter G1, and its second input is electrically connected to the output of the first inverter N1.

[0128] The second gated inverter G2 is configured such that its input is electrically connected to the output of the first NOR gate Nor1, and its control is electrically connected to the first clock terminal Clk of the dual-edge flip-flop.

[0129] The third gated inverter G3 is configured such that its input is electrically connected to the output of the first NOR gate Nor1, its control terminal is electrically connected to the first clock terminal Clk of the dual-edge flip-flop, and its output is electrically connected to the first input of the first NOR gate Nor1.

[0130] The second inverter N2 is configured such that its input is electrically connected to the output of the second gated inverter G2, and its output is electrically connected to the output Q of the dual-edge flip-flop.

[0131] The fourth gated inverter G4 is configured such that its input is electrically connected to the input D of a dual-edge flip-flop, and its control is electrically connected to the first clock terminal Clk of the dual-edge flip-flop.

[0132] The fifth AND gate, And5, is configured such that its first input is electrically connected to the second test enable signal Test, its second input is electrically connected to the output of the fourth gated inverter G4, and its output is electrically connected to the second input of the second NOR gate Nor2.

[0133] The second NOR gate Nor2 is configured such that its first input is electrically connected to the output of the first NAND gate Nand1.

[0134] The fifth gated inverter G5 is configured such that its input is electrically connected to the output of the second NOR gate Nor2, its control terminal is electrically connected to the second clock terminal Clkb of the dual-edge flip-flop, and its output is electrically connected to the input of the second inverter N2.

[0135] The sixth gate inverter G6 is configured such that its input is electrically connected to the output of the second NOR gate Nor2, its control terminal is electrically connected to the second clock terminal Clkb of the dual-edge flip-flop, and its output is electrically connected to the second input of the fifth AND gate And5.

[0136] The first OR gate OR1 is configured such that its first input is electrically connected to the second test enable signal Test, and its second input is electrically connected to the output Q of a dual-edge flip-flop.

[0137] The first NAND gate, Nand1, is configured such that its first input is electrically connected to the reset terminal Rst of a dual-edge flip-flop, and its second input is electrically connected to the output of the first OR gate, OR1.

[0138] When the second test enable signal Test is high, OR1 outputs a high level. The output of Nand1 depends on the signal at the reset terminal Rst, and the first input of And5 receives a high level. When the reset terminal receives a high level and no reset is performed, the flip-flop composed of G1, Nor1, G3, and G2 samples at the rising edge of the first clock terminal Clk, and the flip-flop composed of G4, And5, Nor2, G6, and G5 samples at the falling edge of the first clock terminal Clk, thus forming a dual-edge sampling function. When the second test enable signal Test is low, And5 outputs a low level, and the output of G4 cannot be transmitted backward. Therefore, it cannot sample at the falling edge of the first clock terminal Clk. Only the flip-flop composed of G1, Nor1, G3, and G2 samples at the rising edge of the first clock terminal Clk. Nor2, G5, N2, OR1, and Nand1 form a latch structure, which is beneficial for maintaining the output.

[0139] In summary, the test circuit provided in this disclosure, by designing a corresponding register module before the through-silicon via (TSV), can perform speed tests on both the command address path and the read / write path in the data path of the logic chip. This allows some testing of the HBM device to be moved forward, i.e., the logic chip is tested before stacking, and logic chips that meet the speed requirements are selected before being stacked with memory chips. This can greatly reduce testing and stacking costs.

[0140] In another embodiment of this disclosure, referring to Figure 10, a flowchart of a testing method is shown. As shown in Figure 10, the method is applied to a logic chip and includes:

[0141] S101. Write the first test signal to the first register module of the logic chip through the first path of the logic chip at the first speed;

[0142] S102, Control the first register module to operate in the mode of a linear feedback shift register;

[0143] S103. Control the first register module to operate in the mode of a normal shift register, and output the values ​​in the first register module serially according to the serial test protocol to obtain the first test result signal;

[0144] S104. Compare the first test result signal with the expected value to determine whether the first path of the logic chip can work normally at the first speed.

[0145] The first register module is electrically connected to the first through-silicon via of the logic chip.

[0146] If the first test result signal matches the expected value, it indicates that the first test signal transmitted from the first path to the first register module without error at the first speed. This means the first path of the logic chip can operate normally at the first speed, thus passing the test at the first speed. Understandably, different first speeds can be set, and by continuously increasing the value of the first speed, the maximum speed at which the logic chip can operate normally can be tested. Logic chips that pass the speed test are then stacked with memory chips, which can significantly reduce testing and stacking costs.

[0147] The logic chip includes multiple through-silicon vias (TSVs), each with its corresponding first register module for speed testing. In a test mode based on a serial test protocol, each TSV can be connected in series, meaning the first test result signal output from the first register module corresponding to each TSV is sequentially output serially. The overall serially output data is compared with the expected value to determine whether the logic chip can operate normally at that first speed.

[0148] In some embodiments, referring to Figure 11, the test method further includes:

[0149] S201. Write the second test signal to the second register module of the logic chip at a first speed through the write path in the second path of the logic chip.

[0150] S202, Control the second register module to operate in linear feedback shift register mode;

[0151] S203. Control the second register module to operate in the mode of a normal shift register, and output the values ​​in the second register module serially according to the serial test protocol to obtain the second test result signal;

[0152] S204. Compare the second test result signal with the expected value to determine whether the write path in the second path of the logic chip can work normally at the first speed.

[0153] The second register module is electrically connected to the second through-silicon via of the logic chip.

[0154] If the second test result signal is consistent with the expected value, it means that the second test signal did not have any errors in the process of being transmitted from the write path in the second path to the second register module at the first speed. This means that the write path in the second path of the logic chip can run normally at the first speed, i.e., it has passed the test at the first speed.

[0155] In some embodiments, referring to Figure 12, the test method further includes:

[0156] S301. Control the second register module to operate in ordinary shift register mode, and write initial values ​​to the second register module according to the serial test protocol;

[0157] S302, Control the second register module to operate in linear feedback shift register mode to generate pseudo-random data;

[0158] S303. Output pseudo-random data at the first speed through the read path in the second path;

[0159] S304. Compare the pseudo-random data with the expected value to determine whether the read path in the second path of the logic chip can work normally at the first speed.

[0160] If the output pseudo-random data is consistent with the expected value, it means that there is no error in the process of outputting data from the read path in the second path, which means that the read path in the second path of the logic chip can run normally at the first speed, that is, it has passed the test at the first speed.

[0161] In some embodiments, the first path is a command address path used to transmit command address signals of the logic chip, and the second path is a data path used to transmit data signals of the logic chip.

[0162] This testing method can perform the aforementioned tests on the first and second paths of a logic chip, namely the command address path and the data path, at various speeds. Only when both the first and second paths pass the speed test can it be said that the logic chip can operate normally at that speed. In this way, qualified logic chips can be selected and then stacked with memory chips, which can greatly reduce testing and stacking costs.

[0163] In another embodiment of this disclosure, see Figure 13, which shows a schematic diagram of a chip stacking structure.

[0164] As shown in Figure 13, the chip stacking structure includes a logic chip 40 and at least one stacking unit 90, and the logic chip 40 and at least one stacking unit 90 are stacked sequentially along a first direction; each stacking unit includes a plurality of memory chips 91 stacked sequentially along the first direction, the first direction being perpendicular to the top surface of each memory chip 91; the logic chip 40 includes the test circuit in the aforementioned embodiment.

[0165] The logic chips 40 included in this chip stacking structure can undergo the aforementioned speed test using their included test circuitry before stacking. Only logic chips that pass the speed test are stacked with memory chips. This ensures the quality and yield of the chip stacking structure while reducing testing and stacking costs.

[0166] The above are merely preferred embodiments of this disclosure and are not intended to limit the scope of protection of this disclosure. It should be noted that in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. The sequence numbers of the embodiments in this disclosure are merely descriptive and do not represent the superiority or inferiority of the embodiments. The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined to obtain new method embodiments without conflict. The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined to obtain new product embodiments without conflict. The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined to obtain new method or device embodiments without conflict. The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A test circuit, characterized in that, Applied to logic chips (40), including: The first register module (11) is electrically connected to the first path (20) and the first through-silicon via (30) of the logic chip. When the first test enable signal is at the first level, it is configured as a linear feedback shift register and receives the first test signal at the first speed through the first path. When the first test enable signal is at the second level, it is configured as a normal shift register and outputs the value in the first register module serially according to the serial test protocol to obtain the first test result signal.

2. The test circuit according to claim 1, characterized in that, Also includes: The second register module (12) is electrically connected to the second path (60) and the second through-silicon via (50) of the logic chip. In the mode of testing the write path in the second path, when the second test enable signal is at the first level, it is configured as a linear feedback shift register and receives the second test signal at the first speed through the write path of the second path. When the second test enable signal is at the second level, it is configured as a normal shift register and outputs the value in the second register module serially according to the serial test protocol to obtain the second test result signal. In the mode of testing the read path in the second path, when the second test enable signal is at the second level, it is configured as a normal shift register and writes an initial value to the second register module according to the serial test protocol. When the second test enable signal is at the first level, it is configured as a linear feedback shift register to generate pseudo-random data and output the pseudo-random data at the first speed through the read path in the second path.

3. The test circuit according to claim 2, characterized in that, The first path is a command address path, used to transmit the command address signal of the logic chip, and the second path is a data path, used to transmit the data signal of the logic chip.

4. The test circuit according to claim 3, characterized in that, The first path includes a first receiver (21), a command decoder (22), and a first sampling circuit (23), wherein the first receiver is electrically connected to the command address port of the logic chip; the write path in the second path includes a second receiver, a first serial-to-parallel conversion circuit, and a first transmitter, wherein the second receiver is electrically connected to the data port of the logic chip, and the first transmitter is electrically connected to the second through-silicon via; the read path in the second path includes a third receiver, a second serial-to-parallel conversion circuit, and a second transmitter, wherein the third receiver is electrically connected to the second through-silicon via, and the second transmitter is electrically connected to the data port.

5. The test circuit according to claim 4, characterized in that, The first test signal is sent by the host and transmitted to the first register module via the command address port of the logic chip and the first path; the second test signal is sent by the host and transmitted to the second register module via the data port of the logic chip and the write path in the second path; the pseudo-random data is transmitted to the host via the first transmitter, the read path in the second path and the data port.

6. The test circuit according to claim 4, characterized in that, The first test signal is sent by the test interface circuit of the logic chip and transmitted to the first register module via the third transmitter electrically connected to the command address port and the first path; the second test signal is sent by the test interface circuit of the logic chip and transmitted to the second register module via the second serial-to-parallel conversion circuit, the second transmitter and the write path in the second path; the pseudo-random data is transmitted to the multi-input shift register of the logic chip via the first transmitter, the third receiver and the second serial-to-parallel conversion circuit.

7. The test circuit according to claim 1, characterized in that, The first register module includes: The first input selection unit (111) is configured such that a first input terminal receives the first test signal, a second input terminal receives test data written according to the serial test protocol, a control terminal receives the first test enable signal, and when the first test enable signal is at a first level, the output terminal outputs the signal received by the first input terminal, and when the first test enable signal is at a second level, the output terminal outputs the signal received by the second input terminal. The first clock selection unit (112) is configured to receive a first clock signal at a first input terminal and a second clock signal at a second input terminal. When the first test enable signal is at a first level, it outputs the signal received at the first input terminal; when the first test enable signal is at a second level, it outputs the signal received at the second input terminal. The first clock signal is used to sample the command address signal of the logic chip, and the second clock signal is the clock signal under the serial test protocol. The first register unit (113) includes a first AND gate, a second AND gate, a first XOR gate, a second XOR gate, and M single-edge flip-flops; the first input of the first AND gate receives the first test enable signal, and the second input is electrically connected to the output of the Mth single-edge flip-flop; the first input of the first XOR gate is electrically connected to the output of the first AND gate, and the second input is electrically connected to the output of the first input selection unit; the first input of the second AND gate receives the first test enable signal, and the second input is electrically connected to the output of the Mth single-edge flip-flop; the first input of the second XOR gate is electrically connected to the output of the second AND gate, and the second input is electrically connected to the output of the first input selection unit; the first input of the second AND gate receives the first test enable signal, and the second input is electrically connected to the output of the Mth single-edge flip-flop; the first input of the second XOR gate is electrically connected to the output of the second AND gate, and the second input is electrically connected to the output of the first input selection unit. The output of the Nth single-edge flip-flop is electrically connected; the input of the 1st single-edge flip-flop is electrically connected to the output of the first XOR gate; the input of the i-th single-edge flip-flop is electrically connected to the output of the (i-1)-th single-edge flip-flop; the input of the (N+1)-th single-edge flip-flop is electrically connected to the output of the second XOR gate; the input of the j-th single-edge flip-flop is electrically connected to the output of the (j-1)-th single-edge flip-flop; the output of the M-th single-edge flip-flop outputs the first test result signal; the clock terminals of the M single-edge flip-flops are all electrically connected to the output of the first clock selection unit; where M, N, i, and j are all positive integers, M>N, 2≤i≤N, (N+1) <j≤M。 8. The test circuit according to claim 7, characterized in that, M=5, N=2.

9. The test circuit according to claim 2, characterized in that, The second register module includes: The second input selection unit (121) is configured such that the first input terminal receives the second test signal, the second input terminal receives test data written according to the serial test protocol, the control terminal receives the second test enable signal, and when the second test enable signal is at a first level, the output terminal outputs the signal received by the first input terminal, and when the second test enable signal is at a second level, the output terminal outputs the signal received by the second input terminal. The second clock selection unit (122) is configured such that its first input terminal receives a third clock signal, its second input terminal receives a fourth clock signal, and its third input terminal receives a fifth clock signal. When the second test enable signal is at a second level, its first output terminal outputs the signal received by the first input terminal. When the second test enable signal is at a first level and in the mode of testing the write path in the second path, its first output terminal outputs the signal received by the second input terminal. When the second test enable signal is at a first level and in the mode of testing the read path in the second path, its first output terminal outputs the signal received by the third input terminal. The signal output by the first output terminal is denoted as the sixth clock signal, and the signal output by the second output terminal is denoted as the seventh clock signal. The seventh clock signal is out of phase with the sixth clock signal. The third clock signal is the clock signal under the serial test protocol, the fourth clock signal is the clock signal used in the write path in the second path, and the fifth clock signal is the clock signal used in the read path in the second path. The second register unit (123) includes a third AND gate, a fourth AND gate, a third XOR gate, a fourth XOR gate, and A dual-edge flip-flops; the first input of the third AND gate receives the second test enable signal, and the second input is electrically connected to the output of the A dual-edge flip-flop; the first input of the third XOR gate is electrically connected to the output of the third AND gate, and the second input is electrically connected to the output of the second input selection unit; the first input of the fourth AND gate receives the second test enable signal, and the second input is electrically connected to the output of the A dual-edge flip-flop; the first input of the fourth XOR gate is electrically connected to the output of the fourth AND gate, and the second input is electrically connected to the output of the B dual-edge flip-flop. The output terminals are electrically connected; the input terminal of the first dual-edge flip-flop is electrically connected to the output terminal of the third XOR gate, the input terminal of the x-th dual-edge flip-flop is electrically connected to the output terminal of the (x-1)-th dual-edge flip-flop, the input terminal of the (B+1)-th dual-edge flip-flop is electrically connected to the output terminal of the fourth XOR gate, the input terminal of the y-th dual-edge flip-flop is electrically connected to the output terminal of the (y-1)-th dual-edge flip-flop, and the output terminal of the A-th dual-edge flip-flop outputs the second test result signal or the pseudo-random data. The first clock terminals of the A dual-edge flip-flops all receive the sixth clock signal, and the second clock terminals all receive the seventh clock signal; wherein A, B, x, and y are all positive integers, A>B, 2≤x≤B, and (B+1) <y≤A。 10. The test circuit according to claim 9, characterized in that, A = 5, B = 2.

11. The test circuit according to claim 9, characterized in that, When the second test enable signal is at the second level, the dual-edge flip-flop samples in response to the rising edge of the clock signal received at the first clock terminal; when the second test enable signal is at the first level, it samples in response to the rising and falling edges of the clock signal received at the first clock terminal.

12. The test circuit according to claim 11, characterized in that, The dual-edge trigger includes: The first gated inverter is configured such that its input terminal is electrically connected to the input terminal of the dual-edge flip-flop, and its control terminal is electrically connected to the second clock terminal of the dual-edge flip-flop. The first inverter is configured such that its input is electrically connected to the reset terminal of the dual-edge flip-flop; The first NOR gate is configured such that its first input is electrically connected to the output of the first gated inverter, and its second input is electrically connected to the output of the first inverter. The second gated inverter is configured such that its input is electrically connected to the output of the first NOR gate, and its control is electrically connected to the first clock terminal of the dual-edge flip-flop. The third gated inverter is configured such that its input is electrically connected to the output of the first NOR gate, its control terminal is electrically connected to the first clock terminal of the dual-edge flip-flop, and its output is electrically connected to the first input of the first NOR gate. The second inverter is configured such that its input is electrically connected to the output of the second gated inverter, and its output is electrically connected to the output of the dual-edge flip-flop. The fourth gated inverter is configured such that its input terminal is electrically connected to the input terminal of the dual-edge flip-flop, and its control terminal is electrically connected to the first clock terminal of the dual-edge flip-flop. The fifth AND gate is configured such that its first input is electrically connected to the second test enable signal, its second input is electrically connected to the output of the fourth gated inverter, and its output is electrically connected to the second input of the second NOR gate. The second NOR gate is configured such that its first input is electrically connected to the output of the first NAND gate; The fifth gated inverter is configured such that its input is electrically connected to the output of the second NOR gate, its control terminal is electrically connected to the second clock terminal of the dual-edge flip-flop, and its output is electrically connected to the input of the second inverter. The sixth gated inverter is configured such that its input is electrically connected to the output of the second NOR gate, its control terminal is electrically connected to the second clock terminal of the dual-edge flip-flop, and its output is electrically connected to the second input of the fifth AND gate. The first OR gate is configured such that its first input is electrically connected to the second test enable signal, and its second input is electrically connected to the output of the dual-edge flip-flop. The first NAND gate is configured such that its first input is electrically connected to the reset terminal of the dual-edge flip-flop, and its second input is electrically connected to the output terminal of the first OR gate.

13. The test circuit according to claim 1, characterized in that, The serial test protocol is the IEEE 1500 test protocol.

14. A testing method, characterized in that, Applied to logic chips, including: A first test signal is written to the first register module of the logic chip through the first path of the logic chip at a first speed; Control the first register module to operate in linear feedback shift register mode; The first register module is controlled to operate in the mode of a normal shift register. According to the serial test protocol, the values ​​in the first register module are serially output to obtain the first test result signal. The first test result signal is compared with the expected value to determine whether the first path of the logic chip can work normally at the first speed; The first register module is electrically connected to the first through-silicon via of the logic chip.

15. The test method according to claim 14, characterized in that, Also includes: A second test signal is written to the second register module of the logic chip at a first speed via the write path in the second path of the logic chip. Control the second register module to operate in linear feedback shift register mode; The second register module is controlled to operate in the mode of a normal shift register, and the values ​​in the second register module are serially output according to the serial test protocol to obtain the second test result signal; The second test result signal is compared with the expected value to determine whether the write path in the second path of the logic chip can work normally at the first speed; The second register module is electrically connected to the second through-silicon via of the logic chip.

16. The test method according to claim 15, characterized in that, Also includes: The second register module is controlled to operate in normal shift register mode, and an initial value is written to the second register module according to the serial test protocol; The second register module is controlled to operate in linear feedback shift register mode to generate pseudo-random data; The pseudo-random data is output at a first speed via the read path in the second path; The pseudo-random data is compared with the expected value to determine whether the read path in the second path of the logic chip can work normally at the first speed.

17. A chip stacking structure, characterized in that, It includes a logic chip and at least one stacking unit, wherein the logic chip and at least one stacking unit are stacked sequentially along a first direction; each stacking unit includes a plurality of memory chips stacked sequentially along the first direction, wherein the first direction is perpendicular to the top surface of each memory chip; The logic chip includes the test circuit as described in any one of claims 1-13.

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