Semiconductor device and manufacturing method therefor, chip, and electronic device

Abstract

Embodiments of the present application relate to the technical field of semiconductors, and provide a semiconductor device and a manufacturing method therefor, a chip, and an electronic device. The semiconductor device comprises: a substrate, a first groove being formed on the substrate; a first dielectric layer, the first dielectric layer being arranged on the substrate, wherein a second groove is formed on the side of the first dielectric layer away from the substrate, and the second groove is arranged corresponding to the first groove; an alignment mark, the alignment mark being located in the second groove; a through-silicon via, the through-silicon via penetrating through the first dielectric layer and extending into the substrate; and a conductive structure, the conductive structure filling the through-silicon via, and the alignment mark and at least a portion of the conductive structure being made of the same material and arranged in the same layer. In the embodiments of the present application, the alignment mark located in the second groove has higher contrast, facilitating alignment identification during exposure.

Description

Semiconductor devices and their fabrication methods, chips, electronic devices

[0001] This application claims priority to Chinese Patent Application No. 202411563102.4, filed on November 4, 2024, entitled "Semiconductor Device and Preparation Method Thereof, Chip, Electronic Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of semiconductor technology, and in particular to a semiconductor device, its fabrication method, a chip, and an electronic device. Background Technology

[0003] In the chip manufacturing industry, alignment is required during photolithography to ensure that the overlay deviation between subsequent exposure layers and previous layers meets design standards. When exposing the first pattern layer, no alignment is performed because there are no alignment marks. Subsequent layers are aligned using the alignment marks from the previous one or several layers. The quality of the alignment marks themselves not only affects whether the lithography machine can correctly identify the marked patterns but also affects the accuracy of the overlay deviation. Summary of the Invention

[0004] Embodiments of this application provide a semiconductor device and its fabrication method, chip, and electronic device for improving the clarity of alignment marks and increasing alignment accuracy.

[0005] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0006] In a first aspect, a semiconductor device is provided, comprising: a substrate having a first groove thereon; a first dielectric layer disposed on the substrate, wherein the first dielectric layer has a second groove on a side away from the substrate, the second groove corresponding to the first groove; an alignment mark located within the second groove; a through-silicon via penetrating the first dielectric layer and extending into the substrate; and a conductive structure filling the through-silicon via, wherein the alignment mark and at least a portion of the conductive structure are made of the same material and disposed in the same layer.

[0007] The semiconductor device provided in this application includes a first groove formed on a substrate and a second groove formed on a first dielectric layer for conformal purposes. During the formation of the conductive structure, an alignment mark is simultaneously formed within the second groove. This alignment mark has higher contrast, making alignment identification during exposure easier and reducing the risk of alignment failure. Furthermore, it utilizes only the process of forming the conductive structure itself, without any other additional processes, and has broad application prospects.

[0008] In one possible implementation, the conductive structure includes conductive pillars filling through-silicon vias, and alignment marks are made of the same material as the conductive pillars and are disposed in the same layer.

[0009] In one possible implementation, the conductive structure includes a barrier layer and conductive pillars, the conductive pillars filling a through-silicon via (TSV); the barrier layer is disposed between the conductive pillars and the TSV; and alignment marks are made of the same material as at least one of the conductive pillars and the barrier layer and are disposed in the same layer.

[0010] In one possible implementation, the conductive structure includes a barrier layer, a seed layer, and conductive pillars, with the conductive pillars filling a through-silicon via (TSV); the seed layer is disposed between the conductive pillars and the TSV; the barrier layer is disposed between the seed layer and the TSV; and alignment marks are made of the same material as at least one of the conductive pillars, the seed layer, and the barrier layer and are disposed in the same layer.

[0011] In one possible implementation, the barrier layer is made of at least one or more of the following materials: titanium, tantalum, titanium nitride, and tantalum nitride. This barrier layer prevents the diffusion of metallic materials into silicon or other materials during high-temperature processing or fabrication, maintaining the stability and integrity of the circuit. Furthermore, the barrier layer material has high contrast, facilitating alignment identification during exposure.

[0012] In one possible implementation, the alignment mark is flush with the side surface away from the substrate and the side surface of the first dielectric layer away from the substrate.

[0013] In one possible implementation, the semiconductor device further includes an insulating layer disposed between the through-silicon via (TSV) and the conductive structure, and covering the sidewalls and bottom wall of the TSV.

[0014] In one possible implementation, the semiconductor device further includes a second dielectric layer that covers the first dielectric layer, alignment marks, and conductive structures.

[0015] In a second aspect, a method for fabricating a semiconductor device is provided, the method comprising: forming a first groove on a substrate; forming a first dielectric layer on the substrate, wherein a second groove is formed on a side of the first dielectric layer away from the substrate, the second groove being formed corresponding to the first groove; forming a through-silicon via (TSV) penetrating the first dielectric layer and extending into the substrate; forming an alignment mark and a conductive structure, wherein the alignment mark is located within the second groove, the conductive structure is filled within the TSV, and at least a portion of the alignment mark and the conductive structure are made of the same material and disposed in the same layer.

[0016] In one possible implementation, forming a conductive structure and alignment marks includes: forming a conductive layer that covers a first dielectric layer and a portion of the conductive layer further fills a through-silicon via (TSV) and a second groove; planarizing the conductive layer while retaining the portion of the conductive layer filled in the TSV to obtain a conductive structure, and retaining the portion of the conductive layer filled in the second groove to obtain alignment marks.

[0017] In one possible implementation, forming a conductive structure and alignment marks includes: forming a barrier layer that covers a first dielectric layer and a portion of the barrier layer further fills a through-silicon via and a second groove; forming a conductive layer that covers the barrier layer; planarizing the barrier layer and the conductive layer, retaining portions of the conductive layer and the barrier layer filled within the through-silicon via to obtain a conductive structure, and retaining at least the portion of the barrier layer located within the second groove to obtain alignment marks.

[0018] In one possible implementation, forming a conductive structure and alignment marks includes: forming a barrier layer covering a first dielectric layer, and a portion of the barrier layer further filling a through-silicon via (TSV) and a second groove; forming a seed layer covering the barrier layer; forming a conductive layer covering the seed layer; planarizing the barrier layer, seed layer, and conductive layer, retaining portions of the conductive layer, seed layer, and barrier layer filled within the TSV, to obtain a conductive structure, and retaining at least the portion of the barrier layer located within the second groove, to obtain alignment marks.

[0019] Thirdly, a chip is provided, the chip including a substrate and a semiconductor device in the first aspect and any possible embodiment thereof; the semiconductor device and the substrate are electrically connected.

[0020] Fourthly, an electronic device is provided, the electronic device including a printed circuit board and a chip; the chip and the printed circuit board are electrically connected.

[0021] The technical effects of any of the possible implementations of the second to fourth aspects can be found in the technical effects of the different implementations of the first aspect described above, and will not be repeated here. Attached Figure Description

[0022] Figure 1 is a schematic diagram of the structure of the semiconductor device provided in an embodiment of this application;

[0023] Figure 2 is a schematic diagram of the structure of a semiconductor device provided in another embodiment of this application;

[0024] Figure 3 is a schematic diagram of the structure of a semiconductor device provided in another embodiment of this application;

[0025] Figure 4 is a schematic flowchart of the semiconductor device fabrication method provided in the embodiments of this application;

[0026] Figures 5-9 are schematic diagrams of the structure of a semiconductor device provided in an embodiment of this application at various stages of the fabrication process;

[0027] Figures 10-12 are schematic diagrams of the structure of a semiconductor device provided in another embodiment of this application at various stages of the fabrication process;

[0028] Figures 13-18 are schematic diagrams of the structure of a semiconductor device provided in another embodiment of this application at various stages of the fabrication process;

[0029] Figure 19 is a schematic diagram of the structure of a semiconductor device provided in another embodiment of this application;

[0030] Figure 20 is a schematic diagram of the structure of a semiconductor device provided in another embodiment of this application;

[0031] Figure 21 is a schematic diagram of the structure of a semiconductor device provided in another embodiment of this application;

[0032] Figure 22 is a schematic diagram of the structure of a semiconductor device provided in another embodiment of this application;

[0033] Figure 23 is a schematic diagram of the structure of a chip provided in an embodiment of this application;

[0034] Figure 24 is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0035] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0036] In the following description, the terms "first," "second," etc., are used for descriptive convenience only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0037] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0038] In chip fabrication, alignment is crucial during photolithography to ensure that the overlay between subsequent layers meets design standards. Generally, there are two types of alignment marks: one is a periodic structure that diffracts under an alignment laser, offering high alignment accuracy and commonly used in front-end processes; the other is an alignment mark based on a comparison standard pattern (golden image), offering slightly lower alignment accuracy and commonly used in back-end processes, though sometimes in front-end processes. Alignment marks are typically added to the exposure pattern of each layer, forming alignment marks during subsequent dielectric or metal layer deposition for use in aligning subsequent layers. When the first layer is exposed, no alignment is performed because there are no alignment marks; subsequent layers are aligned using the alignment marks from the previous layer or layers. The quality of the alignment marks themselves not only affects whether the lithography machine can correctly identify the marked pattern but also influences the overlay accuracy.

[0039] Advanced packaging processes typically include through-silicon via (TSV) technology. TSVs allow vertical interconnects to penetrate silicon wafers or chips. TSV technology can be used to achieve 3D integrated circuit packaging; for example, it can be used to stack multiple chips to achieve chip or circuit interconnection. Due to the deep depth of the TSVs formed and the limitations of the etching process, it is not suitable to add alignment marks within the TSVs. Therefore, a zero mark is first created as an alignment marker. Then, the metal layer formed during TSV fabrication and the subsequent top metal layer are aligned according to the zero mark to ensure that the overlay deviation between the top metal layer and the TSV is within a preset range. When forming the film layer after the top metal layer, a new alignment mark can be created for alignment, or the initial zero mark can be used as the alignment marker for exposure.

[0040] The following embodiment provides a method for fabricating alignment marks, as shown in Figures 1 and 2. In Figure 1, a first groove 11 is first etched into a substrate 10, and then a first dielectric layer 20 is deposited. Due to conformal requirements, a second groove 21 is formed on the first dielectric layer 20. During the processing of the first dielectric layer 20, the first groove 11 and the second groove 21 in Figure 1 are used as alignment marks for alignment exposure. In Figure 2, after the first dielectric layer 20 is processed, a through-silicon via (TSV) 30 is formed, and conductive material is deposited in the TSV 30. After the conductive material deposition, a planarization process is required to remove any residual conductive material from the surface of the first dielectric layer 20. Generally, the planarization process involves a certain degree of over-polishing of the first dielectric layer 20 to ensure that no conductive material residue remains on the surface. As shown in Figure 2, after the planarization process, the second groove 21 is removed, and then a top metal layer 25 is deposited.

[0041] However, during the process of removing residual conductive material from the surface, there may be insufficient grinding. That is, although all the residual metal on the surface of the first dielectric layer 20 has been ground off, the second groove 21 may be partially retained. This will cause the subsequent alignment marks to be affected by the pattern of the partially retained second groove 21, resulting in the failure of the top metal layer 25 to be aligned.

[0042] To facilitate the removal of the second groove 21, the etching depth of the first groove 11 can be further reduced. However, this results in an unclear pattern boundary between the first groove 11 and the first dielectric layer 20 filling it, potentially leading to a low alignment score during the formation of the top metal layer 25. In subsequent processes, as other film layers are gradually deposited, the boundary between the first groove 11 and the first dielectric layer 20 gradually becomes blurred, and the marking quality gradually decreases. This may result in alignment failures and excessively low recognition scores, making it difficult to use as an alignment mark for subsequent film layers.

[0043] Therefore, this application also provides a semiconductor device, as shown in FIG3, which includes: a substrate 10, a first dielectric layer 20, an alignment mark 22, a through-silicon via 30, and a conductive structure 71. A first groove 11 is provided on the substrate 10; the first dielectric layer 20 is disposed on the substrate 10, and a second groove 21 is provided on the side of the first dielectric layer 20 away from the substrate 10, the second groove 21 corresponding to the first groove 11; the alignment mark 22 is located within the second groove 21; the through-silicon via 30 penetrates the first dielectric layer 20 and extends into the substrate 10; the conductive structure 71 fills the through-silicon via 30, and at least a portion of the alignment mark 22 and the conductive structure 71 are made of the same material and disposed in the same layer.

[0044] In one specific embodiment, as shown in FIG4, the semiconductor device fabrication steps shown in FIG3 specifically include: S10-S40.

[0045] S10: A first groove 11 is formed on the substrate 10.

[0046] S20: A first dielectric layer 20 is formed on the substrate 10. A second groove 21 is formed on the side of the first dielectric layer 20 away from the substrate 10. The second groove 21 is formed corresponding to the first groove 11.

[0047] S30: Forming a through-silicon via 30 that penetrates the first dielectric layer 20 and extends into the substrate 10.

[0048] S40: Form alignment mark 22 and conductive structure 71. Alignment mark 22 is located in second groove 21 and conductive structure 71 is filled in silicon via 30. Alignment mark 22 and conductive structure 71 are made of the same material and are disposed in the same layer.

[0049] The alignment mark 22 being made of the same material as at least a portion of the conductive structure 71 and being disposed in the same layer can be understood as follows: when the conductive structure 71 includes only one film layer, the alignment mark 22 is made of the same material as that film layer and is disposed in the same layer; or, when the conductive structure 71 includes multiple film layers, the alignment mark 22 may be made of the same material as one or more of these multiple film layers and be disposed in the same layer.

[0050] In this application, "same layer" refers to a layer structure formed using the same film deposition process to create a specific pattern, and then using the same photomask through a single patterning process. Depending on the specific pattern, the single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses.

[0051] In other words, alignment mark 22 can be patterned with at least a portion of conductive structure 71 in the same patterning process for the same film layer.

[0052] The semiconductor device provided in this application includes a first groove 11 formed on a substrate 10, and a second groove 21 formed on a first dielectric layer 20 for conformal purposes. Simultaneously, during the formation of the conductive structure 71, an alignment mark 22 is formed within the second groove 21. Because the material of the conductive structure 71 has higher contrast, and the alignment mark 22 is made of at least a portion of the same material as the conductive structure 71, the alignment mark 22 also has higher contrast, making alignment identification during exposure easier and reducing the risk of alignment failure. Furthermore, this application embodiment utilizes the process of forming the conductive structure 71 to simultaneously form the alignment mark 22, requiring no other additional processes, and has broad application prospects.

[0053] The following, with reference to the accompanying drawings, provides a schematic description of steps S10-S40 in the semiconductor device fabrication method.

[0054] S10: A first groove 11 is formed in the substrate 10.

[0055] In this embodiment, the substrate 10 may be a semiconductor substrate. Exemplarily, the material of the substrate 10 includes at least one or a combination of the following: silicon (Si), germanium silicide (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), p-type doped Si, n-type doped Si, and other semiconductor or suitable substrate 10 materials. In some embodiments, the substrate 10 may contain, for example, but not limited to, group III elements, group IV elements, group V elements, or combinations thereof (e.g., III-V compounds).

[0056] As shown in Figure 5, a first groove 11 can be formed in the substrate 10 through a patterning process, including etching processes such as photolithography and dry etching. The photolithography process includes photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, and drying (e.g., hard baking). The dry etching process involves using etching gases such as carbon tetrafluoride (CF4), argon (Ar), nitrogen trifluoride (NF3), chlorine (Cl2), helium (He), hydrogen bromide (HBr), oxygen (O2), nitrogen (N2), fluoromethane (CH3F), methane (CH4), difluoromethane (CH2F2), or combinations thereof.

[0057] S20: A first dielectric layer 20 is formed on the substrate 10. A second groove 21 is formed on the side of the first dielectric layer 20 away from the substrate 10. The second groove 21 is formed corresponding to the first groove 11.

[0058] For example, as shown in Figure 6, a first dielectric layer 20 is formed on the substrate 10 using a deposition process based on Figure 5. For conformal purposes, a second groove 21 is formed on the side of the first dielectric layer 20 away from the substrate 10, and the second groove 21 corresponds to the first groove 11. The deposition process can be, for example, chemical vapor deposition (CVD), high-density plasma chemical vapor deposition (HDPCVD), spin coating, sputtering, or other suitable processes. The first dielectric layer 20 can be a single-layer structure or a multilayer structure, and the material of the first dielectric layer 20 can be various dielectric materials, such as SiO2, Si3N4, SiON, and NDC.

[0059] It is understood that in this embodiment, the etching depth of the first groove 11 can be adjusted according to the actual application to adjust the depth of the second groove 21 in the thickness direction of the substrate 10, thereby controlling the outline of the alignment mark 22 formed in subsequent steps.

[0060] S30: Forming a through-silicon via 30 that penetrates the first dielectric layer 20 and extends into the substrate 10.

[0061] In some alternative examples, the through silicon via 30 (TSV) can be formed using TSV technology. For example, as shown in Figure 7, a through-hole is formed on the first dielectric layer 20 based on Figure 6, extending into the substrate 10. The TSV can be formed on the substrate 10 and the first dielectric layer 20 in a single etching process, or the first dielectric layer 20 can be etched first to form the through-hole, and then the substrate 10 can be etched to form blind vias, i.e., the bottom of each blind via is a certain distance from the surface of the substrate 10 away from the first dielectric layer 20. The through-hole communicates with the blind via to form the TSV 30, and the depth of the TSV 30 is greater than the thickness of the first dielectric layer 20, but less than the sum of the thickness of the substrate 10 and the thickness of the first dielectric layer 20.

[0062] S40: Form alignment mark 22 and conductive structure 71. Alignment mark 22 is located in second groove 21. Conductive structure 71 is filled in silicon via 30. Alignment mark 22 and conductive structure 71 are made of the same material and are disposed in the same layer.

[0063] In this embodiment, in the same deposition process, alignment marks 22 are formed in the second groove 21, and conductive structures 71 are formed in the through-silicon vias 30. In some specific examples, the material of the conductive structure 71 includes copper, aluminum, tungsten, titanium, cobalt, chromium, and combinations thereof, or other metals and their metal compounds.

[0064] Because the metal and its metal compounds in the conductive structure 71 have high contrast, the alignment mark 22, which is made of the same material as the conductive structure 71, also has higher contrast. Even after multiple film layers are deposited subsequently, it will not affect the identification during photolithography, making alignment easier. Furthermore, subsequent multilayer exposure processes can align with the alignment mark in this layer, improving the overlay process. Moreover, in this embodiment, the alignment mark 22 can be formed simultaneously using the process for forming the conductive structure 71, without any additional processes, thus having broad application prospects.

[0065] The conductive structure 71 can be configured in various ways, and correspondingly, the alignment mark 22 can also be configured in various ways, which will be described below with reference to the accompanying drawings.

[0066] In some embodiments, in the above-described S40, alignment marks 22 and conductive structures 71 are formed, including S41a-S42a.

[0067] S41a: A conductive layer 70 is formed, which covers the first dielectric layer 20, and a portion of the conductive layer 70 is also filled in the through-silicon via 30 and the second groove 21.

[0068] As shown in Figure 8, based on Figure 7, a conductive material is deposited on the first dielectric layer 20 by a deposition process. The conductive material fills the second groove 21 and the through-silicon via 30 to form a conductive layer 70. For example, the material of the conductive layer 70 includes copper, aluminum, tungsten, titanium, cobalt, chromium and combinations thereof.

[0069] S42a: The conductive layer 70 is planarized, and the portion of the conductive layer 70 filled in the through-silicon via 30 is retained to obtain the conductive structure 71. The portion of the conductive layer 70 filled in the second groove 21 is retained to obtain the alignment mark 22.

[0070] In this embodiment, as shown in FIG9, the structure described above is ground using a chemical mechanical polishing (CMP) process based on FIG8. The conductive layer 70 retained in the through-silicon via 30 after grinding becomes a conductive pillar 72. This conductive pillar 72 serves as a conductive structure 71, providing a vertical signal channel for semiconductor devices to transmit and receive electrical signals between semiconductor devices.

[0071] The conductive layer retained in the second groove after grinding becomes an alignment mark, and therefore the alignment mark 22 contains a metal element with high contrast. Using a high-contrast alignment mark 22 ensures that identification during photolithography is not affected even after multiple film layers are deposited, making alignment easier. Furthermore, subsequent multi-layer exposures and photolithography processes can align with this layer's alignment mark, improving the overlay process. Moreover, in this embodiment, the alignment mark 22 can be formed simultaneously using the process of forming the conductive structure 71, without any additional processes, thus having broad application prospects. In other embodiments, in step S40 above, forming the alignment mark 22 and the conductive structure 71 includes the following steps S41b-S43b.

[0072] S41b: A barrier layer 50 is formed, which covers the first dielectric layer 20, and a portion of the barrier layer 50 also fills the through-silicon via 30 and the second groove 21.

[0073] In this embodiment, as shown in FIG10, based on FIG7, the barrier layer 50 covers the sidewalls and bottom wall of the second groove 21 and the sidewalls and bottom wall of the through-silicon via 30. In some specific examples, the material of the barrier layer 50 may or may not completely fill the second groove 21, leaving some space in the second groove 21. In some specific examples, the material of the barrier layer 50 does not completely fill the through-silicon via 30 to facilitate the subsequent deposition of conductive material in the through-silicon via 30.

[0074] The barrier layer 50 can be a single-layer or multi-layer structure. The material of the barrier layer 50 can be one or more of titanium (Ti), tantalum (Ta), titanium nitride (TiN), and tantalum nitride (TaN), or other metals or dielectrics. This barrier layer 50 prevents the diffusion of metal materials from the subsequently formed conductive structure into the substrate during high-temperature processing or fabrication, maintaining the stability and integrity of the circuit. It also effectively blocks the migration of harmful substances, avoiding negative impacts on the performance of semiconductor devices. Especially in multilayer structures, it protects the lower-layer circuitry from the influence of the upper-layer metal.

[0075] S42b: Forming a conductive layer 70, which covers the barrier layer 50.

[0076] As shown in Figure 11, based on Figure 10, a conductive material is deposited on the barrier layer 50 using a deposition process. This conductive material at least fills the through-silicon via 30 to form a conductive layer 70. In some specific examples, when the material of the barrier layer does not completely fill the second groove 21 in step S41b above, the conductive material can also fill the second groove 21. Exemplarily, the material of the conductive layer 70 includes copper, aluminum, tungsten, titanium, cobalt, chromium, and combinations thereof.

[0077] S43b: Planarize the barrier layer 50 and the conductive layer 70, retain the portion of the conductive layer 70 and the barrier layer 50 that fills the through-silicon via 30, to obtain a conductive structure 71, and retain at least the portion of the barrier layer 50 located in the second groove 21, to obtain an alignment mark 22.

[0078] In this embodiment, as shown in FIG12, the structure described above is ground using a chemical mechanical polishing (CMP) process based on FIG11. After grinding, the conductive layer 70 retained in the through-silicon via 30 becomes a conductive pillar 72. The conductive pillar 72 and the barrier layer 50 retained inside the through-silicon via 30 together constitute a conductive structure 71. The conductive structure 71 provides a vertical signal channel for semiconductor devices, used for transmitting and receiving electrical signals between semiconductor devices.

[0079] The film layer retained in the second groove 21 after grinding becomes the alignment mark. In some embodiments, when the material of the barrier layer 50 fills the second groove 21 in step S41b, the alignment mark 22 is composed of the barrier layer 50 retained in the second groove 21. In other embodiments, when the material of the barrier layer 50 does not fill the second groove 21 in step S41b, some of the conductive layer 70 is also deposited in the second groove 21. The alignment mark 22 may be composed of the barrier layer 50 and the conductive layer 70 retained in the second groove 21. Alternatively, in other embodiments, even if the material of the barrier layer 50 and the conductive material together fill the second groove 21 in steps S41b and S42b, the conductive material in the second groove 21 is removed due to the long CMP process time and deep grinding. Therefore, the alignment mark 22 is composed of the barrier layer 50 retained in the second groove 21.

[0080] Both the barrier layer 50 and the conductive layer 70 contain metal elements, therefore the alignment mark 22 also contains metal elements with high contrast. Using a high-contrast alignment mark 22 ensures that identification during photolithography is not affected even after multiple film layers are deposited, making alignment easier. Furthermore, subsequent multilayer exposures and photolithography processes can align with this layer's alignment mark, improving the overlay process. In this embodiment, the alignment mark 22 is formed simultaneously with the process of forming the conductive structure 71, requiring no additional processes, thus demonstrating broad application prospects.

[0081] In some optional embodiments, the preparation method further includes the following step S50 before step S40 described above.

[0082] S50: Form an insulating layer 40.

[0083] As shown in Figure 13, an insulating layer 40 is formed on the first dielectric layer 20 using a deposition process based on Figure 7. Specifically, the insulating layer 40 covers the surface of the first dielectric layer 20 away from the substrate 10, the sidewalls and bottom wall of the second groove 21, and the sidewalls and bottom wall of the through-silicon via 30, thereby preventing electrical signal interference between different circuits. Alternatively, in some optional embodiments, the insulating layer 40 may only cover the sidewalls and bottom wall of the through-silicon via 30.

[0084] The insulating layer 40 is formed of a dielectric material that has good insulating properties and can effectively prevent current leakage. The insulating layer 40 can be a single layer structure of the same dielectric material or a multilayer structure of different materials. The dielectric material is, for example, one or a combination of two or more materials selected from silicon oxynitride, silicone, and polyimide, or any other dielectric material in the art used to constitute the insulating layer 40.

[0085] In this embodiment, the materials of the insulating layer 40 and the first dielectric layer 20 are not limited. When the materials of the insulating layer 40 and the first dielectric layer 20 are the same, the boundary line between the insulating layer 40 and the first dielectric layer 20 can be blurred or disappear, that is, the insulating layer 40 and the first dielectric layer 20 are the same material layer.

[0086] Accordingly, in step S40 above, alignment mark 22 and conductive structure 71 are formed, including S41c-S44c.

[0087] S41c: Forms a barrier layer 50.

[0088] As shown in Figure 14, a barrier layer 50 covering the insulating layer 40 is formed through a deposition process based on Figure 13. Specifically, the barrier layer 50 is also provided in the second groove 21 and the through-silicon via 30, but these areas are not completely filled. Therefore, the barrier layer 50 can prevent the diffusion of metal materials in the subsequently formed conductive structure into the substrate during high-temperature processing or fabrication, maintaining the stability and integrity of the circuit. Simultaneously, it can effectively block the migration of harmful substances, avoiding negative impacts on the performance of semiconductor devices. Especially in multilayer structures, it can protect the lower-layer circuit from the influence of the upper-layer metal. The barrier layer 50 can be a single-layer structure or a multilayer structure. The material of the barrier layer 50 can be one or more of titanium (Ti), tantalum (Ta), titanium nitride (TiN), and tantalum nitride (TaN), or other metals or dielectrics.

[0089] S42c: Formation of seed layer 60.

[0090] In this embodiment, as shown in FIG15, a seed layer 60 is formed on the surface of the barrier layer 50 based on FIG14. That is, a seed layer 60 is also provided in the second groove 21 and the through-silicon via 30, and the second groove 21 and the through-silicon via 30 are not completely filled. The seed layer 60 can provide a good adhesion surface, promote the uniform deposition of subsequent metals, and ensure the formation of a stable conductive path in the through-silicon via 30.

[0091] In some examples, the seed layer 60 can be formed by deposition processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), metal-organic chemical vapor deposition (MOCVD), or plasma-enhanced chemical vapor deposition (PECVD).

[0092] S43c: Formation of conductive layer 70.

[0093] In this embodiment, as shown in FIG16, based on FIG15, a conductive layer 70 is formed on the surface of the seed layer 60, thereby filling the second groove 21 and the through-silicon via 30. The material of the conductive layer 70 includes copper, aluminum, tungsten, titanium, cobalt, chromium, and combinations thereof.

[0094] S44c: The conductive layer 70, seed layer 60 and barrier layer 50 are planarized to obtain conductive structure 71 and alignment mark 22.

[0095] In this embodiment, as shown in FIG17, the above structure is polished by chemical mechanical polishing (CMP) based on FIG16. The film layer remaining in the through silicon via 30 after polishing, excluding the insulating layer 40, constitutes the conductive structure 71. The film layer remaining in the second groove 21 after polishing, excluding the insulating layer 40, constitutes the alignment mark 22.

[0096] In a specific example, the conductive layer 70 retained within the through-silicon via 30 is formed as a conductive pillar 72. The conductive pillar 72, together with the seed layer 60 and the barrier layer 50 retained within the through-silicon via 30, constitute a conductive structure 71. This conductive structure 71 provides a vertical signal path for semiconductor devices, used for transmitting and receiving electrical signals between semiconductor devices. An insulating layer 40 disposed between the conductive structure 71 and the through-silicon via 30 prevents electrical signal interference between the conductive structure 71 and other circuits.

[0097] In a specific example, in the polished semiconductor device, the barrier layer 50 and seed layer 60 retained in the second groove 21 form the alignment mark 22. During subsequent photolithography alignment exposure operations, such as when forming the semiconductor device shown in FIG18, a second dielectric layer 75 needs to be formed on the first dielectric layer 20. The second dielectric layer 75 covers the first dielectric layer 20, the alignment mark 22, and the conductive structure 71. The second dielectric layer 75 can be a single-layer structure or a stacked structure, and the material of the second dielectric layer 75 can be one or more of SiO2, Si3N4, SiON, and NDC.

[0098] When depositing the second dielectric layer 75, alignment exposure can be performed using the alignment marks (the barrier layer 50 and the seed layer 60 retained in the second groove 21) set in the second groove 21 as a reference. Since the alignment marks containing metallic elements have high contrast, they do not affect the identification during photolithography even after multiple film layers are deposited subsequently, making alignment easier. Furthermore, subsequent multilayer exposure processes can align with these alignment marks, improving the overlay process. Simultaneously, the process of forming these alignment marks utilizes the original process of filling the through-silicon via 30, requiring no additional processes, and has broad application prospects.

[0099] In one specific embodiment, after planarization, the alignment mark 22 is flush with the side surface of the substrate 10 away from the first dielectric layer 20 away from the substrate 10.

[0100] In one optional example, the seed layer 60 has a retention thickness of 100nm-200nm after polishing, for example, a retention thickness of 110nm after polishing; or, a retention thickness of 125nm after polishing; or, a retention thickness of 155nm after polishing; or, a retention thickness of 160nm after polishing; or, a retention thickness of 190nm after polishing, or other depths.

[0101] In some specific embodiments, considering that the first groove 11 needs to have a certain etching depth to ensure that the second groove 21 can still be retained after subsequent grinding, the etching depth of the first groove 11 should meet the following conditions:

[0102] The etching depth of the first groove 11 = the thickness of the barrier layer 50 + the remaining thickness of the seed layer 60 after grinding + the thickness loss of the insulating layer 40 and the first dielectric layer 20 during grinding.

[0103] This ensures that the alignment marks are clear, improves the accuracy of identification, and reduces the risk of alignment failure.

[0104] In another specific example, due to the deeper etching depth of the first groove 11, or less grinding during the aforementioned polishing process, the alignment mark 22 in the second groove 21 also includes the conductive layer 70. As shown in Figure 19, in the polished semiconductor device, the second groove 21 retains the insulating layer 40, the remaining portion of the barrier layer 50 (excluding the via 30), the remaining portion of the seed layer 60 (excluding the via 30), and the remaining portion of the conductive layer 70 (excluding the via 30). Thus, the remaining portions of the barrier layer 50, the seed layer 60, and the conductive layer 70 constitute the alignment mark 22. During subsequent photolithography alignment exposure of the film layer, the alignment mark 22 in the second groove 21 can be used as a reference. Since the alignment mark 22 includes metal elements, which have high contrast, alignment is easier. Moreover, the process of forming the alignment mark 22 utilizes the original process of forming the conductive structure 71 in the via 30, requiring no additional processes and showing broad application prospects.

[0105] In some alternative embodiments, as shown in FIG20, when the insulating layer 40 is thicker, it can also cover the surface of the first dielectric layer 20 away from the substrate 10, that is, the first dielectric layer 20 is completely covered by the insulating layer 40. Using a thicker insulating layer 40 can further prevent current leakage.

[0106] In another specific example, due to the shallow etching depth of the first groove 11, or excessive grinding during the aforementioned polishing process, the alignment mark in the second groove 21 is composed only of a portion of the barrier layer 50. As shown in Figure 21, in the polished semiconductor device, the second groove 21 retains the remaining portion of the insulating layer 40 and the barrier layer 50, excluding those within the through-silicon via 30; thus, the remaining portion of the barrier layer 50 constitutes the alignment mark 22. During subsequent photolithography alignment exposure of the film layer, the alignment mark 22 formed in the second groove 21 can be used as a reference. Because the alignment mark 22 contains metal elements, it has high contrast and is easier to align successfully. Moreover, the process of forming the alignment mark 22 utilizes the original process of forming the conductive structure 71 in the through-silicon via 30, requiring no other additional processes, and has broad application prospects.

[0107] The semiconductor device proposed in this application is not limited to the specific structure formed by the fabrication method provided in the above embodiments. In some other embodiments, the insulating layer 40 may not be formed before the conductive structure 71 and the alignment mark 22 are formed, that is, in Figures 13-21, the insulating layer 40 is not provided. For example, in the schematic diagram of the semiconductor device shown in Figure 22, the barrier layer 50 is directly formed on the first dielectric layer 20, and then the seed layer and the conductive layer are formed sequentially. The film layer retained in the through-silicon via 30 constitutes the conductive structure 71, and the film layer retained in the second groove 21 constitutes the alignment mark 22.

[0108] In this embodiment, the method for fabricating the semiconductor device and the structure of the fabricated semiconductor device are the same as or similar to steps S41c-S44c described above. Specific details can be found in the descriptions of S41c-S44c, and will not be repeated here. The above examples are merely illustrative examples provided to better understand the technical solutions of the embodiments of this application and are not intended as the sole limitation on the embodiments of this application. The embodiments of this application are not limited to forming alignment marks simultaneously with the TSV process; alignment marks can be formed simultaneously in fabrication processes employing other conductive structures. Correspondingly, when using other fabrication processes, the structure in the alignment marks can change with the change in the conductive structure.

[0109] The alignment mark 22 provided in this application embodiment is not only applicable to the scenario of photolithography of film layers provided in the above embodiment, but also applicable to other scenarios that require alignment of any film layer. For example, before mixing and bonding two film layers, the structure of the alignment mark 22 and the corresponding preparation method provided in this application embodiment can be referred to to form alignment marks on both film layers. Then, alignment is performed based on the alignment marks on the two film layers, and bonding is then performed.

[0110] This application also provides a chip 200. As shown in FIG23, the chip includes a semiconductor device 100 and a substrate 110, wherein the semiconductor device 100 and the substrate 110 are electrically connected.

[0111] In some embodiments, the chip 200 may further include microbumps 101. When the substrate is a packaging substrate, multiple microbumps 101 can electrically connect the packaging substrate to the semiconductor device 100. Additionally, in some embodiments, as shown in FIG23, the electronic device may also include a connector 130; the substrate 110 in the chip is connected to other electronic devices, such as a printed circuit board, via the connector 130. This enables communication between the semiconductor device 100 and other electronic devices. Here, the connector 130 may be a solder ball or a microbump.

[0112] The chip provided in the above embodiments of this application can be an unpackaged bare chip. An unpackaged bare chip can include one integrated circuit block (which can be referred to as a two-dimensional (2D) bare chip), or it can include multiple integrated circuit blocks (which can be referred to as a three-dimensional (3D) bare chip). The chip provided in the above embodiments can also be a packaged chip, which can include one bare chip or multiple bare chips.

[0113] The chips according to embodiments of this application can be applied to various electronic devices. For example, by integrating multiple such chips and other devices (e.g., other forms of transistors, etc.), and electrically connecting them to a printed circuit board, an electronic device can be constructed. Therefore, embodiments of this application also provide an electronic device, as shown in FIG24, which may include the chip 200 and printed circuit board (PCB) 300 provided in the above embodiments. This electronic device may include facilities such as base stations and servers, and may also include CMOS image sensors, NAND flash memory, high-bandwidth memory, mobile phones, tablets, televisions, smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, and other electronic products. Embodiments of this application do not impose special limitations on the specific form of the above electronic device.

[0114] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A semiconductor device, characterized in that, include: A substrate having a first groove provided thereon; A first dielectric layer is disposed on the substrate, wherein the first dielectric layer has a second groove on the side away from the substrate, and the second groove is disposed corresponding to the first groove; Alignment mark, the alignment mark being located within the second groove; A through-silicon via (TSV) that penetrates the first dielectric layer and extends into the substrate; A conductive structure, wherein the conductive structure fills the through-silicon via, and the alignment mark is made of the same material as at least a portion of the conductive structure and is disposed in the same layer.

2. The semiconductor device according to claim 1, characterized in that, The conductive structure includes conductive pillars that fill the through-silicon vias, and the alignment marks are made of the same material as the conductive pillars and are disposed in the same layer.

3. The semiconductor device according to claim 1, characterized in that, The conductive structure includes a barrier layer and conductive pillars. The conductive pillars fill the through-silicon vias; The barrier layer is disposed between the conductive pillar and the through-silicon via; The alignment mark is made of the same material as at least one of the conductive pillars and the barrier layer and is disposed in the same layer.

4. The semiconductor device according to claim 1, characterized in that, The conductive structure includes a barrier layer, a seed layer, and conductive pillars. The conductive pillars fill the through-silicon vias; The seed layer is disposed between the conductive pillar and the through-silicon via; The barrier layer is disposed between the seed layer and the through-silicon via; The alignment mark is made of the same material as at least one of the conductive pillar, seed layer and barrier layer and is disposed in the same layer.

5. The semiconductor device according to claim 3 or 4, characterized in that, The material of the barrier layer includes at least one or more of the following combinations: titanium, tantalum, titanium nitride, and tantalum nitride.

6. The semiconductor device according to any one of claims 1-5, characterized in that, The alignment mark is flush with the side surface away from the substrate and the side surface of the first dielectric layer away from the substrate.

7. The semiconductor device according to any one of claims 1-6, characterized in that, The semiconductor device also includes an insulating layer. The insulating layer is disposed between the through-silicon via and the conductive structure, and covers the sidewalls and bottom wall of the through-silicon via.

8. The semiconductor device according to any one of claims 1-7, characterized in that, The semiconductor device further includes a second dielectric layer. The second dielectric layer covers the first dielectric layer, the alignment mark, and the conductive structure.

9. A method for fabricating a semiconductor device, characterized in that, include: A first groove is formed on the substrate; A first dielectric layer is formed on the substrate, and a second groove is formed on the side of the first dielectric layer away from the substrate, the second groove being formed corresponding to the first groove; Forming a through-silicon via that penetrates the first dielectric layer and extends into the substrate; A conductive structure and an alignment mark are formed, the alignment mark being located within the second groove, the conductive structure filling the through-silicon via, and the alignment mark being made of the same material as at least a portion of the conductive structure and disposed in the same layer.

10. The method according to claim 9, characterized in that, The formation of the conductive structure and alignment marks includes: A conductive layer is formed, the conductive layer covering the first dielectric layer, and a portion of the conductive layer also fills the through-silicon via and the second groove; The conductive layer is planarized, retaining the portion of the conductive layer that fills the through-silicon via to obtain the conductive structure, and retaining the portion of the conductive layer that fills the second groove to obtain the alignment mark.

11. The method according to claim 9, characterized in that, The formation of the conductive structure and alignment marks includes: A barrier layer is formed, the barrier layer covering the first dielectric layer, and a portion of the barrier layer also filling the through-silicon via and the second groove; A conductive layer is formed, which covers the barrier layer; The barrier layer and the conductive layer are planarized, retaining the portions of the conductive layer and the barrier layer that fill the through-silicon vias to obtain the conductive structure, and at least retaining the portion of the barrier layer located in the second groove to obtain the alignment mark.

12. The method according to claim 9, characterized in that, The formation of the conductive structure and alignment marks includes: A barrier layer is formed, the barrier layer covering the first dielectric layer, and a portion of the barrier layer also filling the through-silicon via and the second groove; A seed layer is formed, which covers the barrier layer; A conductive layer is formed, which covers the seed layer; The barrier layer, the seed layer, and the conductive layer are planarized, and the portions of the conductive layer, the seed layer, and the barrier layer that fill the through-silicon vias are retained to obtain the conductive structure. At least the portion of the barrier layer located in the second groove is retained to obtain the alignment mark.

13. A chip, characterized in that, It includes a substrate and a semiconductor device as described in any one of claims 1-8; the semiconductor device and the substrate are electrically connected.

14. An electronic device, characterized in that, It includes a printed circuit board and the chip as described in claim 13; the chip and the printed circuit board are electrically connected.

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