Memory cell, semiconductor device, and manufacturing method therefor

Abstract

Embodiments of the present disclosure provide a memory cell, a semiconductor device, and a manufacturing method therefor. The semiconductor device comprises: a substrate, the substrate comprising a base and a stack structure disposed on the base, and the stack structure comprising first insulating layers and second insulating layers which are alternately arranged; several first hole structures and second hole structures penetrating through the stack structure and arranged in a first direction, the first direction being parallel to the base; and a memory cell, the memory cell comprising first sub-structures disposed in the first hole structures and second sub-structures disposed in the second hole structures, the first sub-structures being located in the first insulating layers or the second insulating layers, the second sub-structures being located in the first insulating layers or the second insulating layers, each first sub-structure comprising a read transistor and a capacitor, and each second sub-structure comprising a first transistor and a second transistor.

Description

Memory cells, semiconductor devices and their fabrication methods

[0001] Cross-references to related applications

[0002] This application is based on and claims priority to Chinese Patent Application No. 202411554712.8, filed on November 1, 2024, entitled "Semiconductor Device and Preparation Method Thereof, Storage Unit, Read / Write Method and Memory Thereof", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of semiconductor technology, and in particular to a memory cell, a semiconductor device, and a method for fabricating the same. Background Technology

[0004] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and number of devices contained in a single chip are increasing, which means that small differences in the manufacturing process may affect the performance of the devices.

[0005] To minimize product costs, the goal is to fabricate as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands.

[0006] Application content

[0007] In view of this, the present disclosure provides a memory cell, a semiconductor device, and a method for fabricating the same.

[0008] To achieve the above objectives, the technical solution disclosed herein is implemented as follows:

[0009] This disclosure provides a semiconductor device, comprising: a substrate, the substrate including a base and a stacked structure disposed on the base, the stacked structure including alternating first insulating layers and second insulating layers; a plurality of first hole structures and second hole structures penetrating the stacked structure and disposed along a first direction, the first direction being parallel to the base; a memory cell, the memory cell including a first substructure disposed in the first hole structure and a second substructure disposed in the second hole structure; the first substructure including a read transistor and a capacitor, the first substructure being located in the first insulating layer or the second insulating layer; the second substructure including a first transistor and a second transistor, the second substructure being located in the first insulating layer or the second insulating layer.

[0010] In some embodiments, the first hole structure includes a read word line that extends through the stacked structure, and the first substructure includes a capacitor surrounding the read word line and a read transistor that partially surrounds the capacitor.

[0011] In some embodiments, the first substructure includes a first dielectric layer and a first conductive layer surrounding the word lines, and a first gate dielectric layer and a first semiconductor layer partially surrounding the first conductive layer.

[0012] In some embodiments, the second hole structure includes a write line that penetrates the stacked structure, the first transistor and the second transistor are integral structures, and the integral structure surrounds the write line.

[0013] In some embodiments, the integral structure includes a second gate dielectric layer and a second semiconductor layer surrounding the writing lines.

[0014] In some embodiments, the second semiconductor layer is in contact with the first conductive layer.

[0015] In some embodiments, a bit line structure extending along a first direction is further included, and a plurality of memory cells arranged along the first direction are connected to the same bit line structure; the bit line structure includes a first bit line disposed on a first side of the memory cell and a second bit line disposed on a second side of the memory cell, the first side and the second side being opposite sides of the memory cell in a second direction; the second direction intersects the first direction and is parallel to the substrate.

[0016] In some embodiments, the first bit line is connected to the first semiconductor layer and the second semiconductor layer in the memory cell, and the second bit line is connected to the first semiconductor layer and the second semiconductor layer in the memory cell.

[0017] In some embodiments, a second medium layer is included between two adjacent memory cells along a first direction.

[0018] In some embodiments, the material of the second semiconductor layer includes a metal oxide semiconductor, wherein the metal oxide semiconductor includes at least one element selected from indium, gallium, zinc, tin, and tungsten.

[0019] In some embodiments, the material of the first semiconductor layer includes a single-crystal semiconductor, a polycrystalline semiconductor, or a metal oxide semiconductor.

[0020] In some embodiments, the outer peripheral shape of the first semiconductor layer is the same as the inner peripheral shape of the first semiconductor layer.

[0021] In some embodiments, when the first substructure is located in the first insulating layer, the size of the reading line in the first insulating layer is larger than the size of the reading line in the second insulating layer; when the first substructure is located in the second insulating layer, the size of the reading line in the second insulating layer is larger than the size of the reading line in the first insulating layer.

[0022] This disclosure provides a method for fabricating a semiconductor device, comprising: providing a substrate, the substrate including a substrate and a stacked structure formed on the substrate, the stacked structure including alternating first insulating layers and second insulating layers; forming a plurality of first hole structures and second hole structures penetrating the stacked structure and disposed along a first direction, the first direction being parallel to the substrate; the first hole structure including a first substructure disposed in the first insulating layer or the second insulating layer, each first substructure including a read transistor and a capacitor; the second hole structure including a second substructure disposed in the first insulating layer or the second insulating layer, each second substructure including a first transistor and a second transistor, the first substructure and the second substructure constituting a memory cell.

[0023] In some embodiments, forming a first hole structure includes: forming a first hole through a stacked structure; when the first substructure is located in a first insulating layer, the size of the first hole in the first insulating layer is larger than the size of the first hole in the second insulating layer; when the first substructure is located in a second insulating layer, the size of the first hole in the second insulating layer is larger than the size of the first hole in the first insulating layer; the first hole structure is formed through the first hole, and the first hole structure also includes a read line through the stacked structure, with a capacitor surrounding the read line.

[0024] In some embodiments, forming a first hole through the stacked structure includes: forming a first initial hole through the stacked structure, and laterally etching a first insulating layer or a second insulating layer through the first initial hole to form a first lateral groove surrounding the first initial hole, wherein the first initial hole and the first lateral groove constitute the first hole.

[0025] In some embodiments, forming a first hole structure through a first hole includes: sequentially forming a read transistor and a capacitor covering the bottom of a first lateral groove; and depositing conductive material through a first initial hole to form a read line filling the first initial hole.

[0026] In some embodiments, forming a first hole structure through a first hole includes: sequentially forming a read transistor and a capacitor covering the bottom and sidewalls of a first lateral groove; depositing conductive material through a first initial hole to form a read line filling the first lateral groove and the first initial hole; when the first substructure is located in a first insulating layer, the size of the read line in the first insulating layer is larger than the size of the read line in the second insulating layer; when the first substructure is located in a second insulating layer, the size of the read line in the second insulating layer is larger than the size of the read line in the first insulating layer.

[0027] In some embodiments, forming a second hole structure includes: forming a second hole through the stacked structure; when the second substructure is located in the first insulating layer, the size of the second hole in the first insulating layer is larger than the size of the second hole in the second insulating layer; when the second substructure is located in the second insulating layer, the size of the second hole in the second insulating layer is larger than the size of the second hole in the first insulating layer; forming the second hole structure through the second hole, the second hole structure also includes a write line through the stacked structure, the first transistor and the second transistor are an integral structure, and the integral structure surrounds the write line.

[0028] In some embodiments, forming a second hole through the stacked structure includes: forming a second initial hole through the stacked structure, wherein the projection of the second initial hole on the substrate does not overlap with the projection of the first hole structure on the substrate; and laterally etching a first insulating layer or a second insulating layer and a read transistor through the second initial hole to expose a portion of the capacitor, thereby forming a second lateral groove surrounding the second initial hole, wherein the second initial hole and the second lateral groove constitute the second hole.

[0029] In some embodiments, forming a second hole structure through a second hole includes: forming a first transistor and a second transistor in a second lateral groove; and depositing conductive material through a second initial hole to form a writing line that fills the second hole.

[0030] In some embodiments, the channel material of the first transistor and the channel material of the second transistor include a metal oxide semiconductor, wherein the metal oxide semiconductor includes at least one element selected from indium, gallium, zinc, tin and tungsten.

[0031] In some embodiments, before forming the second hole structure, the fabrication method further includes: forming a bit line structure extending along a first direction, wherein a plurality of memory cells arranged along the first direction are connected to the same bit line structure; the bit line structure includes a first bit line located on a first side of the memory cell and a second bit line located on a second side of the memory cell, wherein the first side and the second side are opposite sides of the memory cell in a second direction; the second direction intersects the first direction and is parallel to the substrate.

[0032] This disclosure provides a memory cell, including: an address line structure comprising a first address line and a second address line; a read transistor comprising a first electrode connected to the first address line, a second electrode connected to the second address line, and a first gate connected to a memory node; a write transistor comprising a first transistor and a second transistor connected in parallel; wherein the first transistor comprises a third electrode connected to the address line structure, a fourth electrode connected to the memory node, and a second gate connected to a write word line; the second transistor comprises a fifth electrode connected to the address line structure, a sixth electrode connected to the memory node, and a third gate connected to the write word line; the second gate and the third gate serve as connection terminals of the write word line to connect multiple write transistors in series; and a capacitor coupled to the memory node.

[0033] In some embodiments, the capacitor includes a first plate connected to the storage node and a second plate grounded; a third electrode and a fifth electrode are connected to a first address line.

[0034] In some embodiments, the capacitor includes a first plate connected to the storage node and a second plate connected to the read line; the second plate serves as the connection end of the read line to connect multiple capacitors in series.

[0035] In some embodiments, the third electrode and the fifth electrode are connected to the first address line.

[0036] In some embodiments, the third electrode is connected to the first address line, and the fifth electrode is connected to the second address line.

[0037] In some embodiments, the channel material of the write transistor includes a metal oxide semiconductor, wherein the metal oxide semiconductor includes at least one element selected from indium, gallium, zinc, tin, and tungsten.

[0038] In some embodiments, the channel material of the read transistor includes a single-crystal semiconductor, a polycrystalline semiconductor, or a metal-oxide-semiconductor.

[0039] In some embodiments, the memory cell includes a first substructure and a second substructure disposed along a first direction parallel to the substrate; the first substructure includes a read transistor and a capacitor, and the second substructure includes a first transistor and a second transistor.

[0040] In some embodiments, during the write phase, a first level is applied to the write word line to turn on the first and second transistors, and a storage signal is input to the third and fifth electrodes to write the storage signal into the storage node as stored data; during the read phase, a second level is applied to the end of the capacitor opposite to the storage node, and the stored data is read by sensing whether the read transistor is turned on.

[0041] In some embodiments, during the read phase, if the read transistor is turned on, the stored data is first data; if the read transistor is not turned on, the stored data is second data, and the first data and the second data are different. Attached Figure Description

[0042] Figure 1 is a schematic diagram of the steps of a semiconductor device fabrication method provided in an embodiment of this disclosure;

[0043] Figure 2 is a schematic diagram of the structure of the substrate provided in an embodiment of this disclosure;

[0044] Figure 3(a) is a top perspective view of the structure obtained after forming the first hole in an embodiment of the present disclosure, located in the first insulating layer; and Figure 3(b) is a cross-sectional schematic diagram of the structure shown in Figure (a) along line AA'.

[0045] Figure 4(a) is a top perspective view of the structure obtained after forming the first hole structure in an embodiment of the present disclosure, located in the first insulating layer; and Figure 4(b) is a cross-sectional schematic diagram of the structure shown in Figure (a) along line AA'.

[0046] Figure 5(a) is a top perspective view of the structure obtained after forming the first hole structure in another embodiment of the present disclosure, located in the first insulating layer; and Figure 5(b) is a cross-sectional schematic diagram of the structure shown in Figure (a) along line AA'.

[0047] Figure 6(a) is a top perspective view of the structure obtained after forming the isolation gap in an embodiment of the present disclosure, located in the first insulating layer; and Figure 6(b) is a cross-sectional schematic diagram of the structure shown in Figure (a) along line AA'.

[0048] Figure 7(a) is a top perspective view of the structure obtained after forming the first and second wire gaps in an embodiment of the present disclosure, located in the first insulating layer; and (b) is a cross-sectional schematic diagram of the structure shown in (a) along line AA'.

[0049] Figure 8(a) is a top perspective view of the structure obtained after forming the first bit line, the second bit line and the isolation structure in an embodiment of the present disclosure, located in the first insulating layer; and Figure 8(b) is a cross-sectional schematic diagram of the structure shown in Figure (a) along line AA'.

[0050] Figure 9(a) is a top perspective view of the structure obtained after forming the second initial hole in an embodiment of the present disclosure, located in the first insulating layer; (b) is a cross-sectional schematic diagram of the structure shown in (a) along line BB'; and (c) is a cross-sectional schematic diagram of the structure shown in (a) along line CC'.

[0051] Figure 10(a) is a top perspective view of the structure obtained after forming the second transverse groove in an embodiment of the present disclosure, located in the first insulating layer; (b) is a cross-sectional schematic diagram of the structure shown in (a) along line BB'; and (c) is a cross-sectional schematic diagram of the structure shown in (a) along line CC'.

[0052] Figure 11(a) is a top perspective view of the structure obtained after forming the second dielectric layer in an embodiment of the present disclosure, located on the first insulating layer; (b) is a cross-sectional schematic diagram of the structure shown in (a) along line BB'; and (c) is a cross-sectional schematic diagram of the structure shown in (a) along line CC'.

[0053] Figure 12(a) is a top perspective view of the structure obtained after forming the second hole structure in an embodiment of the present disclosure, located in the first insulating layer; (b) is a cross-sectional schematic diagram of the structure shown in (a) along line AA'; (c) is a cross-sectional schematic diagram of the structure shown in (a) along line BB'; and (d) is a cross-sectional schematic diagram of the structure shown in (a) along line CC'.

[0054] Figure 13(a) is a logic circuit diagram of a memory cell provided in an embodiment of the present disclosure, and (b) is a structural schematic diagram of the memory cell shown in (a).

[0055] Figure 14(a) is a logic circuit diagram of a memory cell provided in an embodiment of the present disclosure, and (b) is a structural schematic diagram of the memory cell shown in (a).

[0056] Figure 15(a) is a logic circuit diagram of a memory cell provided in an embodiment of the present disclosure, and (b) is a structural schematic diagram of the memory cell shown in (a).

[0057] Figure 16(a) is a logic circuit diagram of a storage unit provided in an embodiment of the present disclosure, and Figure 16(b) is a structural schematic diagram of the storage unit shown in Figure (a). Detailed Implementation

[0058] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0059] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0060] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0061] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0062] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0063] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0064] To fully understand this disclosure, detailed steps and structures will be set forth in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0065] This disclosure provides a method for fabricating a semiconductor device, comprising: providing a substrate, the substrate including a substrate and a stacked structure formed on the substrate, the stacked structure including alternating first insulating layers and second insulating layers; forming a plurality of first hole structures and second hole structures penetrating the stacked structure and disposed along a first direction, the first direction being parallel to the substrate; the first hole structure including a first substructure disposed in the first insulating layer or the second insulating layer, each first substructure including a read transistor and a capacitor; the second hole structure including a second substructure disposed in the first insulating layer or the second insulating layer, each second substructure including a first transistor and a second transistor, the first substructure and the second substructure constituting a memory cell.

[0066] The semiconductor device fabrication method provided in this disclosure forms a semiconductor device with a three-transistor-capacitor (3T1C) memory cell. Specifically, it includes two write transistors (a first transistor and a second transistor, respectively), one read transistor, and a capacitor. The two write transistors not only provide redundancy but also enable higher data transfer rates. Furthermore, during the write phase, the parallel-connected first and second transistors can shunt the write current, thereby reducing the performance requirements on the write transistors. In addition, the memory cells in this semiconductor device can be stacked not only perpendicular to the substrate but also arranged in an array in a plane parallel to the substrate, which is beneficial for increasing the integration density of the memory cells.

[0067] Figure 1 is a schematic diagram of the steps in a method for fabricating a semiconductor device according to an embodiment of this disclosure. As shown in Figure 1, the fabrication method includes the following steps:

[0068] Step S10: Provide a substrate, the substrate including a substrate and a stacked structure formed on the substrate, the stacked structure including an alternately arranged first insulating layer and a second insulating layer.

[0069] Step S20: Form a plurality of through-stacking structures and first and second hole structures disposed along a first direction, the first direction being parallel to the substrate.

[0070] It should be understood that the steps shown in Figure 1 are not exclusive, and other steps may be performed before, after, or between any of the steps shown in the operation.

[0071] Figures 2 to 4 and Figures 6 to 12 are schematic diagrams of the semiconductor device structure at various stages in the fabrication method of the semiconductor device provided in the embodiments of this disclosure. It should be noted that Figures 2 to 4 and Figures 6 to 12 are schematic diagrams reflecting a complete implementation process of the semiconductor device fabrication method, and parts not marked in some figures can be shared. The fabrication method of the semiconductor device provided in the embodiments of this disclosure will be described in detail below with reference to Figures 1, 2 to 4, and 6 to 12. It should be noted that Figures 2 to 4 and Figures 6 to 12 are illustrated using the example of the first substructure and the second substructure located in the first insulating layer.

[0072] It should be noted that, for ease of description, the various directions that may be used in the following description are defined first. In a plane parallel to the substrate, the first intersecting direction (Y direction) and the second direction (X direction) are defined, and in a plane perpendicular to the substrate, the Z direction is defined. The X, Y, and Z directions can be mutually perpendicular.

[0073] The deposition processes involved in the embodiments of this disclosure include, but are not limited to: chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), sputtering, metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), and combinations thereof.

[0074] The etching processes involved in the embodiments of this disclosure include, but are not limited to, dry etching, wet etching, and combinations thereof.

[0075] The "patterning process" involved in the embodiments of this disclosure includes processes such as depositing a film layer, coating photoresist, mask exposure, development, etching, and photoresist stripping, which are mature manufacturing processes in related technologies. Deposition can be performed using known processes such as sputtering, evaporation, and chemical vapor deposition; coating can be performed using known coating processes; and etching can be performed using known methods. No specific limitations are made here.

[0076] The semiconductor structure disclosed herein is at least a portion of the structure that will be used in subsequent processes to form the final device structure. Here, the final device may be a memory, such as DRAM (Dynamic Random Access Memory), or other memory chips or processing chips that contain DRAM memory cells.

[0077] Figure 2 is a schematic diagram of the structure of the substrate provided in an embodiment of this disclosure. Referring to Figure 2, a substrate 1 is provided, and a first insulating layer 21 and a second insulating layer 22 are alternately stacked on the substrate 1 by a deposition process to form a stacked structure 2.

[0078] In some embodiments, after forming the stacked structure 2 on the substrate 1, a protective layer 23 can be deposited on the top surface of the stacked structure 2 away from the substrate 1 by a deposition process. The protective layer 23 is used to physically protect the semiconductor device. Exemplarily, the protective layer 23 may include at least one insulating film layer.

[0079] In some embodiments, to avoid electrical connections between multiple rows of memory cells via the substrate 1, at least one insulating layer 24 may be included between the substrate 1 and the stacked structure 2. The material of the insulating layer 24 is an insulating material. Exemplarily, the insulating layer 24 between the substrate 1 and the stacked structure 2 may be a second insulating layer. It should be noted that, in the embodiments of this disclosure, identical structures located in the same layer (or in the same stacked layer) and arranged along the Y direction are called rows, and identical structures arranged along the Z direction are called columns. For example, memory cells arranged along the Y direction and located in the same first insulating layer 21 are called a row of memory cells or a row of memory cells, and memory cells arranged along the Z direction are called a column of memory cells or a column of memory cells.

[0080] For example, the first insulating layer 21 and the second insulating layer 22 may have the same thickness or different thicknesses, and neither of them may be zero. The first insulating layer 21 may be formed of silicon nitride, and the second insulating layer 22 may be formed of silicon oxide, such that the stacked structure 2 is a nitride-oxide (NO) stack. It should be noted that the number of layers of the first insulating layer 21 and the second insulating layer 22 in the stacked structure 2 shown in FIG2 is only an example, and the specific number of layers of the first insulating layer 21 and the second insulating layer 22 in this disclosure is not limited to the number of layers shown.

[0081] This disclosure does not specifically limit the constituent materials of substrate 1. As an example, substrate 1 can be composed of semiconductor materials, insulating materials, conductive materials, or any combination thereof. The substrate can be a single-layer structure or a multi-layer structure. For example, the substrate can be a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V or II / VI semiconductor substrates. Alternatively, the substrate can be a layered substrate comprising, for example, a stack of Si and SiGe, a stack of Si and SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator.

[0082] The insulating and dielectric materials involved in this disclosure can all be insulating materials with high dielectric constant (High-K, HK), such as dielectric materials with a dielectric constant K greater than or equal to 3.9. These include, but are not limited to, HK materials such as hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), and zirconium oxide (ZrO2); the conductive materials can be materials containing metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; the semiconductor materials can be at least one of monocrystalline silicon, amorphous silicon, polycrystalline silicon, or doped polycrystalline silicon, and the semiconductor materials can also be metal oxide semiconductors.

[0083] The material of the gate dielectric layer (first gate dielectric layer or second gate dielectric layer) involved in this disclosure can be selected from any one or more of silicon oxide (e.g., SiO2), hafnium oxide (e.g., HfO2), zirconium oxide (e.g., ZrO), and aluminum oxide (e.g., Al2O3). The gate dielectric layer can be a single-layer structure or a multi-layer structure. For example, it can include a two-layer structure formed of silicon oxide and hafnium oxide, wherein the silicon oxide layer contacts the channel region and the hafnium oxide layer contacts the gate. The thickness of the gate dielectric layer can be set according to actual electrical requirements, for example, it can be 2 nm to 5 nm.

[0084] It should be noted that the first hole structure and the second hole structure are in one-to-one correspondence. In other words, each column of memory cells includes a first hole structure and a second hole structure, and the device structures in the first hole structure and the second hole structure are coupled.

[0085] In some embodiments, forming a first hole structure includes: forming a first hole through a stacked structure; when the first substructure is located in a first insulating layer, the size of the first hole in the first insulating layer is larger than the size of the first hole in the second insulating layer; when the first substructure is located in a second insulating layer, the size of the first hole in the second insulating layer is larger than the size of the first hole in the first insulating layer.

[0086] Figure 3(a) is a top perspective view of the structure obtained after forming the first hole in one embodiment of the present disclosure, located in the first insulating layer; and Figure 3(b) is a cross-sectional schematic diagram of the structure shown in Figure (a) along line AA'. Referring to Figure 3, forming the first hole structure includes forming a first hole 3 that penetrates the stacked structure 2. It should be noted that the number of first holes shown in Figure 3 is only an example, and the present disclosure does not limit the number of first holes.

[0087] In some embodiments, forming a first hole through the stacked structure includes: forming a first initial hole through the stacked structure, and laterally etching a first insulating layer or a second insulating layer through the first initial hole to form a first lateral groove surrounding the first initial hole, wherein the first initial hole and the first lateral groove constitute the first hole.

[0088] In some embodiments, forming a first hole 3 through the stacked structure 2 includes the following steps:

[0089] The first initial hole 31 is formed through the stacked structure 2 by patterning the stacked structure 2 using a patterning process.

[0090] The first insulating layer 21 is laterally etched through the first initial hole 31 to form a first lateral groove 32 surrounding the first initial hole 31.

[0091] Referring to Figure 3, the size of the first hole 3 in the first insulating layer 21 is larger than the size of the first hole 3 in the second insulating layer 22. It can be understood that, on the XOY plane, the orthographic projection of the first hole 3 located in the second insulating layer 22 falls within the orthographic projection of the first hole 3 located in the first insulating layer 21, as shown in Figure 3(b), where the cross-section of the first hole 3 is sawtooth-shaped. It should be noted that the trench formed by lateral etching of the first insulating layer 21 through the first initial hole 31 is a single unit, wherein the first initial hole 31 and the first lateral groove 32 are different parts of this trench. Each first hole 3 has a certain distance between it and other adjacent first holes 3.

[0092] In some embodiments, the second insulating layer can be laterally etched through the first initial hole to form a first lateral groove surrounding the first initial hole, wherein the size of the first hole in the second insulating layer is larger than the size of the first hole in the first insulating layer.

[0093] In some embodiments, the first holes 3 are arranged in an array in the stacked structure 2, specifically including a plurality of first holes 3 arranged along the X direction and a plurality of first holes 3 arranged along the Y direction. It should be noted that the number of first holes 3 shown in FIG3 is only an example, and the number of first holes in this disclosure is not limited to the number shown in FIG3.

[0094] In some embodiments, a first hole structure is formed through a first hole, and the first hole structure further includes a reading line that runs through the stacked structure, with a capacitor surrounding the reading line.

[0095] Figure 4(a) is a top perspective view of the structure obtained after forming the first hole structure in an embodiment of the present disclosure, located in the first insulating layer; and Figure 4(b) is a cross-sectional schematic diagram of the structure shown in Figure (a) along line AA'. Referring to Figure 4, forming the first hole structure further includes forming a first hole structure 4 through the first hole 3, wherein the first hole structure 4 includes a first substructure 40 formed in the first insulating layer 21.

[0096] In some embodiments, when the first lateral groove is located in the second insulating layer, the first hole structure includes a first substructure formed in the second insulating layer. It should be noted that the first substructure and the first lateral groove are located in the same layer.

[0097] In some embodiments, forming a first hole structure through a first hole includes: sequentially forming a read transistor and a capacitor covering the bottom of a first lateral groove; and depositing conductive material through a first initial hole to form a read line filling the first initial hole.

[0098] Referring to Figure 4, the first hole structure 4 is formed through the first hole 3, including the following steps:

[0099] A read transistor Tr is formed covering the bottom of the first lateral groove 32;

[0100] A capacitor C (Capacitor) is formed to cover the read transistor Tr;

[0101] This forms a Read Word Line (RWL) that fills the first initial hole 31.

[0102] For example, the fabrication process of the read transistor Tr includes: forming a first semiconductor layer 41 covering the bottom of the first lateral groove 32 by a deposition process; then forming a first gate dielectric layer 42 that at least covers the surfaces of the first semiconductor layer 41 and the second insulating layer 22 exposed in the first hole 3; and then forming a first conductive layer 43 filling the first lateral groove 32. The portion of the first semiconductor layer 41 that contacts the first gate dielectric layer 42 serves as the channel of the read transistor Tr, and the portion of the first conductive layer 43 that contacts the first gate dielectric layer 42 serves as the gate of the read transistor Tr. The first gate dielectric layer 42 may be a thin film covering the inner wall of the first hole 3. The material of the first semiconductor layer 41 may be a semiconductor material, the material of the first gate dielectric layer 42 may be a dielectric material, and the material of the first conductive layer 43 may be a conductive material. It should be noted that the bottom of the first lateral groove 32 refers to the bottom of the first lateral groove 32 in the X direction that exposes the first insulating layer, and the sidewalls of the first lateral groove 32 refer to the two opposite sides of the first lateral groove 32 in the Z direction.

[0103] The fabrication process of capacitor C and read line RWL includes: forming a first dielectric layer 44 covering the surfaces of the first gate dielectric layer 42 and the first conductive layer 43 exposed by the first hole 3 through a deposition process; and then depositing conductive material into the first initial hole 31 through a deposition process to form the read line RWL. The first conductive layer 43, the first dielectric layer 44, and a portion of the read line RWL (the portion of the read line RWL corresponding to the first conductive layer 43) located in the same first insulating layer 21 can constitute a capacitor C surrounding the read line RWL. It should be noted that the first dielectric layer 44 covers the surfaces of the first gate dielectric layer 42 and the first conductive layer 43 exposed by the first hole 3 after the read transistor Tr is formed, and the material of the first dielectric layer 44 can be a dielectric material.

[0104] Understandably, the read transistor Tr and capacitor C are formed in the same layer, and the read word line RWL runs through the stacked structure 2, thereby connecting the first substructure 40, which is stacked vertically along the Z direction, in series.

[0105] In some embodiments, forming a first hole structure through a first hole includes: sequentially forming a read transistor and a capacitor covering the bottom and sidewalls of a first lateral groove; depositing conductive material through a first initial hole to form a read line filling the first lateral groove and the first initial hole; when the first substructure is located in a first insulating layer, the size of the read line in the first insulating layer is larger than the size of the read line in the second insulating layer; when the first substructure is located in a second insulating layer, the size of the read line in the second insulating layer is larger than the size of the read line in the first insulating layer.

[0106] Figure 5(a) is a top perspective view of the structure obtained after forming the first hole structure in another embodiment of this disclosure, located in the first insulating layer; and Figure 5(b) is a cross-sectional schematic diagram of the structure shown in Figure (a) along line AA'. Referring to Figure 5, forming the first hole structure 4' through the first hole 3 may further include the following steps:

[0107] A read transistor Tr' is formed covering the bottom and sidewalls of the first lateral groove 32;

[0108] A capacitor C' is formed to cover the read transistor Tr';

[0109] A reading line RWL' is formed that fills the first transverse groove 32 and the first initial hole 31.

[0110] Exemplarily, the fabrication process of the read transistor Tr' includes: forming a first semiconductor layer 41' covering the bottom of the first lateral groove 32 by a deposition process; then forming a first gate dielectric layer 42' that at least covers the surfaces of the first semiconductor layer 41' and the second insulating layer 22 exposed in the first hole 3; and then forming a first conductive layer 43' covering the first gate dielectric layer 42'. The portion of the first semiconductor layer 41' that contacts the first gate dielectric layer 42' serves as the channel of the read transistor Tr', and the portion of the first conductive layer 43' that contacts the first gate dielectric layer 42' serves as the gate of the read transistor Tr'. The first gate dielectric layer 42' may be a thin film covering the inner wall of the first hole 3. The material of the first semiconductor layer 41' may be a semiconductor material, the material of the first gate dielectric layer 42' may be a dielectric material, and the material of the first conductive layer 43' may be a conductive material.

[0111] The fabrication process of capacitor C' and read line RWL' includes: forming a first dielectric layer 44' covering the surfaces of the first gate dielectric layer 42' and the first conductive layer 43' exposed by the first hole 3 through a deposition process; and then depositing conductive material into the first hole 3 through a deposition process to form the read line RWL'. The first conductive layer 43', the first dielectric layer 44', and a portion of the read line RWL' (the portion of the read line RWL' corresponding to the first conductive layer 43') located in the same first insulating layer 21 can constitute a capacitor C' surrounding the read line RWL'. It should be noted that the first dielectric layer 44' covers the surfaces of the first gate dielectric layer 42' and the first conductive layer 43' exposed by the first hole 3 after the formation of the read transistor Tr', and the material of the first dielectric layer 44' can be a dielectric material.

[0112] It is understandable that the read transistor Tr' and capacitor C' are formed in the same layer, and the read word line RWL' runs through the stacked structure 2, thereby connecting the first substructure 40' stacked vertically along the Z direction in series.

[0113] Since the first conductive layer 43' can serve as one of the plates of capacitor C', the first conductive layer 43' can cover the bottom and sidewalls of the first transverse groove 32 (specifically, the inner wall of the first gate dielectric layer 42' located in the first transverse groove 32) to increase the plate size of capacitor C'. This can increase the capacity of capacitor C' and effectively improve the data storage capacity, data retention time, and stability of the storage unit.

[0114] In some embodiments, before forming the second hole structure, the fabrication method further includes: forming a bit line structure extending along a first direction, wherein a plurality of memory cells arranged along the first direction are connected to the same bit line structure; the bit line structure includes a first bit line located on a first side of the memory cell and a second bit line located on a second side of the memory cell, wherein the first side and the second side are opposite sides of the memory cell in a second direction; the second direction intersects the first direction and is parallel to the substrate.

[0115] In some embodiments, forming a bitline structure extending along a first direction includes the following steps:

[0116] The stacked structure 2 is patterned using a design process to form an isolation gap that runs through the stacked structure 2;

[0117] The first insulating layer 21 is laterally etched through the isolation gap to form the first wire gap and the second wire gap;

[0118] Conductive material is deposited in the first and second line gaps through a deposition process to form the first and second lines, and insulating material is filled in the isolation gaps through a deposition process to form an isolation structure.

[0119] In other embodiments, when the first substructure is formed in the second insulating layer, forming a bit line structure extending along the first direction includes: forming an isolation gap that penetrates the stacked structure; laterally etching the second insulating layer through the isolation gap to form a first bit line gap and a second bit line gap; depositing conductive material in the first bit line gap and the second bit line gap through a deposition process to form a first bit line and a second bit line; and filling the isolation gap with insulating material through a deposition process to form an isolation structure.

[0120] In other embodiments, when the first substructure and the second substructure in the same memory cell are formed in different layers, such as when the first substructure is formed in the first insulating layer and the second substructure is formed in the second insulating layer, the bit line structure along the Z direction can be located in adjacent first and second insulating layers and the bit line structure does not penetrate adjacent first and second insulating layers. This allows the bit line structure to bridge the first substructure formed in the first insulating layer and the second substructure formed in the second insulating layer in the same memory cell.

[0121] Figure 6(a) is a top perspective view of the structure obtained after forming the isolation gap in an embodiment of this disclosure, located in the first insulating layer; and Figure 6(b) is a cross-sectional schematic diagram of the structure shown in Figure (a) along line AA'. Referring to Figure 6, the isolation gap 51 is located between two adjacent rows of first substructures 40 along the X direction, and there is a certain distance between the isolation gap 51 and the two adjacent rows of first substructures 40 in the X direction.

[0122] Figure 7(a) is a top perspective view of the structure obtained after forming the first and second line slots in an embodiment of this disclosure, located on the first insulating layer. Figure (b) is a cross-sectional schematic diagram of the structure shown in Figure (a) along line AA'. Referring to Figure 7, the first insulating layer 21 is laterally etched through the isolation slot 51 to expose the first semiconductor layer 41, thereby forming the first line slot 52 and the second line slot 53. The first line slot 52 is located on the first side of a row of first substructures 40, and the second line slot is located on the second side of a row of first substructures 40. It should be noted that the trench formed after laterally etching the first insulating layer 21 through the isolation slot 51 is a whole, wherein the isolation slot 51, the first line slot 52, and the second line slot 53 are different parts of the trench.

[0123] Figure 8(a) is a top perspective view of the structure obtained after forming the first bit line, the second bit line, and the isolation structure in one embodiment of the present disclosure, located in the first insulating layer; and Figure 8(b) is a cross-sectional schematic diagram of the structure shown in Figure (a) along line AA'. Referring to Figure 8, the first bit line 54 is formed in the first bit line gap 52, the second bit line 55 is formed in the second bit line gap 53, and the isolation structure 56 is formed in the isolation gap 51. In some embodiments, before forming the isolation structure 56, the conductive material remaining in the isolation gap 51 (the conductive material remaining when forming the bit line structure 5) can be etched to prevent the bit line structures 5 located in different first insulating layers 21 from connecting together. The first bit line 54 is located on the first side of the first substructure 40 in a row and is connected to the first semiconductor layer 41 (the channel of the read transistor Tr). The second bit line 55 in the same bit line structure 5 is located on the second side of the first substructure 40 in the same row and is connected to the first semiconductor layer 41 (the channel of the read transistor Tr). The first bit line 54 and the second bit line 55, which are located on both sides of the first substructure 40 in the same row, constitute the bit line structure 5. The isolation structure 56 is used to isolate two adjacent rows of read transistors Tr (that is, to isolate two adjacent bit line structures 5). The part of the first bit line 54 that contacts the first substructure 40 serves as one terminal (source or drain) of the read transistor Tr, and the part of the second bit line 55 that contacts the same first substructure 40 serves as the other terminal (drain or source) of the read transistor Tr. The bit line structure 5 can connect the first hole structures 4 in the same row in series. The first bit line 54 and the second bit line 55 extend along the Y direction.

[0124] In some embodiments, forming a second hole structure includes: forming a second hole through a stacked structure, wherein when the second substructure is located in a first insulating layer, the size of the second hole in the first insulating layer is larger than the size of the second hole in the second insulating layer; and when the second substructure is located in a second insulating layer, the size of the second hole in the second insulating layer is larger than the size of the second hole in the first insulating layer.

[0125] Figure 9(a) is a top perspective view of the structure obtained after forming the second initial hole in an embodiment of the present disclosure, located in the first insulating layer; (b) is a cross-sectional schematic diagram of the structure shown in (a) along line BB'; and (c) is a cross-sectional schematic diagram of the structure shown in (a) along line CC'. Figure 10(a) is a top perspective view of the structure obtained after forming the second transverse groove in an embodiment of the present disclosure, located in the first insulating layer; (b) is a cross-sectional schematic diagram of the structure shown in (a) along line BB'; and (c) is a cross-sectional schematic diagram of the structure shown in (a) along line CC'. Referring to Figures 9 and 10, forming the second hole structure includes: forming a second hole 6 through the stacked structure 2.

[0126] In some embodiments, forming a second hole through the stacked structure includes: forming a second initial hole through the stacked structure, wherein the projection of the second initial hole on the substrate does not overlap with the projection of the first hole structure on the substrate; and laterally etching the first insulating layer or the second insulating layer and the first transistor through the second initial hole to expose a portion of the capacitor, thereby forming a second lateral groove surrounding the second initial hole, wherein the second initial hole and the second lateral groove constitute the second hole.

[0127] In some embodiments, forming a second hole 6 through the stacked structure 2 includes the following steps:

[0128] The stacked structure 2 is patterned using a patterning process to form a second initial hole 61 that penetrates the stacked structure 2.

[0129] Laterally etch the first insulating layer 21 and the first semiconductor layer 41 and the first gate dielectric layer 42 in the read transistor Tr through the second initial hole 61 to expose a portion of the capacitor C, thereby forming a second lateral groove 62 surrounding the second initial hole 61.

[0130] In some embodiments, when the first substructure and the second substructure in the same memory cell are formed in different layers, such as when the first substructure is formed in the first insulating layer and the second substructure is formed in the second insulating layer, the step of forming the second hole includes: forming a through hole through the stacked structure; laterally etching the first insulating layer and the first semiconductor layer and the first gate dielectric layer in the read transistor through the through hole to expose a portion of the capacitor to form a second initial hole; laterally etching the second insulating layer through the second initial hole to expose the bit line structure and etching the first gate dielectric layer (the portion of the first gate dielectric layer that contacts the second insulating layer) that partially covers the first conductive layer to form a second lateral groove surrounding the second initial hole. In this case, the projection of the first semiconductor layer onto the XOY plane is a ring with a notch.

[0131] Referring to Figure 9, along the Y direction, a second initial hole 61 is disposed between two first hole structures 4. The distance between the second initial hole 61 and the first hole structure 4 (specifically, the first semiconductor layer 41) in the same memory cell column is essentially zero or greater than zero. The distance between the second initial hole 61 and the first hole structure 4 in adjacent memory cell columns is greater than zero, and the distance between the second initial hole 61 and the first hole structure 4 in the same memory cell column is less than the distance between the second initial hole 61 and the first hole structure 4 in adjacent memory cell columns. Along the X direction, the second initial hole 61 is disposed between the first bit line 54 and the second bit line 55. There is a certain spacing between the second initial hole 61 and the first bit line 54, and there is a certain spacing between the second initial hole 61 and the second bit line 55.

[0132] Referring to Figure 10, the second lateral groove 62 surrounds the second initial hole 61. Along the Y direction, the second lateral groove 62 is positioned between the two first hole structures 4, and the distance between the second lateral groove 62 and the first hole structure 4 in the same memory cell column (specifically, the portion of the first conductive layer 43 exposed by the second lateral groove 62) is zero. The distance between the second lateral groove 62 and the first hole structure 4 in adjacent memory cell columns is greater than zero, ensuring physical isolation between two adjacent memory cell columns along the Y direction. Along the X direction, the second lateral groove 62 exposes the first bit line 54 and the second bit line 55. It should be noted that the trench formed by lateral etching of the first insulating layer 21 and the first semiconductor layer 41 and the first gate dielectric layer 42 in the read transistor Tr through the second initial hole 61 is a single unit, wherein the second initial hole 61 and the second lateral groove 62 are different parts of this trench.

[0133] The size of the second hole 6 in the first insulating layer 21 is larger than that in the second insulating layer 22. It can be understood that, on the XOY plane, the orthographic projection of the second hole 6 located in the second insulating layer 22 falls within the orthographic projection of the second hole 6 located in the first insulating layer 21, as shown in Figures (b) and (c) of Figure 10, the cross-section of the second hole 6 is sawtooth-shaped.

[0134] In other embodiments, when the second substructure described below is formed in the second insulating layer, the size of the second hole in the second insulating layer is larger than the size of the second hole in the first insulating layer.

[0135] In some embodiments, the different etching rates of the first semiconductor layer 41, the first gate dielectric layer 42, and the first insulating layer 21 in the Y direction may result in the first insulating layer 21 between the second lateral recess 62 and the first substructure 40 in adjacent memory cell columns being completely etched or having a thickness that is insufficient to isolate two adjacent memory cell columns in the Y direction. Therefore, forming the second via 6 through the stacked structure 2 may further include the following steps:

[0136] Deposit medium material into the second hole 6;

[0137] The dielectric material in the second hole 6 is etched to expose the first conductive layer 43, the first bit line 54, and the second bit line 55. The remaining dielectric material serves as the second dielectric layer.

[0138] Figure 11(a) is a top perspective view of the structure obtained after forming the second dielectric layer in an embodiment of the present disclosure, located on the first insulating layer; (b) is a cross-sectional schematic diagram of the structure shown in (a) along line BB'; and (c) is a cross-sectional schematic diagram of the structure shown in (a) along line CC'. Referring to Figure 10, the size of the second lateral groove 62 in the direction near the first conductive layer 43 is smaller than the size of the second lateral groove 62 in the direction near the first insulating layer 21. After depositing dielectric material in the second hole 6 shown in Figure 10, since the dielectric material is etched at the same rate in the Y direction, after the etching of the dielectric material stops, the size of the second lateral groove 62 in the direction near the first conductive layer 43 shown in Figure 11 is basically the same as the size of the second lateral groove 62 in the direction near the second dielectric layer 63. There is a dielectric material (second dielectric layer 63) of a certain thickness between the second lateral groove 62 and the first substructure 40 in the adjacent other memory cell column. The second dielectric layer 63 and the first insulating layer 21 between the second lateral groove 62 and the first substructure 40 in the adjacent other memory cell column along the Y direction can better isolate the two adjacent memory cell columns along the Y direction.

[0139] In some embodiments, a second hole structure is formed through a second hole, the second hole structure further including a write line through the stacked structure, the first transistor and the second transistor being an integral structure, and the integral structure surrounding the write line.

[0140] Figure 12(a) is a top perspective view of the structure obtained after forming the second hole structure in one embodiment of the present disclosure, located in the first insulating layer; (b) is a cross-sectional schematic diagram of the structure shown in (a) along line AA'; (c) is a cross-sectional schematic diagram of the structure shown in (a) along line BB'; and (d) is a cross-sectional schematic diagram of the structure shown in (a) along line CC'. Referring to Figure 12, forming the second hole structure further includes: forming a second hole structure 7 through the second hole 6, wherein the second hole structure 7 includes a second substructure 70 formed in the first insulating layer 21.

[0141] In some embodiments, forming a second hole structure through a second hole includes: forming a first transistor and a second transistor in a second lateral groove; and depositing conductive material through a second initial hole to form a writing line that fills the second hole.

[0142] Referring to Figure 12, the second hole structure 7 is formed through the second hole 6, including the following steps:

[0143] A first transistor T1 and a second transistor T2 are formed in the second transverse groove 62;

[0144] This forms a Write Word Line (WWL) that fills the second hole 6.

[0145] For example, the fabrication process of the second hole structure 7 includes: forming a second semiconductor layer 71 and a second gate dielectric layer 72 covering the bottom and sidewalls of the second lateral groove 62 by a deposition process, and then depositing conductive material into the second hole 6 by a deposition process to form a write line WWL. The second gate dielectric layer 72 can be a thin film covering the inner wall of the second hole 6. The second semiconductor layer 71 is connected to the first conductive layer 43 in the Y direction, and its first side is connected to the first bit line 54 in the X direction. Its second side is connected to the second bit line 55. The bit line structure 5 connects memory cells arranged along the Y direction to form a row of memory cells. The material of the second semiconductor layer 71 can be a semiconductor material, and the material of the second gate dielectric layer 72 can be a dielectric material. It should be noted that the bottom of the second lateral groove 62 refers to the bottom of the second lateral groove 62 in the Y direction that exposes the first conductive layer 43 and the first insulating layer 21, and in the X direction that exposes the bit line structure 5. The sidewalls of the second lateral groove 62 refer to the two opposite sides of the second lateral groove 62 in the Z direction.

[0146] In this configuration, the write line WWL located in the first insulating layer 21 serves as the common gate of the first transistor T1 and the second transistor T2. The portion of the first conductive layer 43 that contacts the second substructure 70 serves as the common electrode (common source or common drain) of the first transistor T1 and the second transistor T2. The portion of the first bit line 54 that contacts the second substructure 70 serves as one electrode (drain or source) of the first transistor T1. The portion of the second bit line 55 that contacts the second substructure 70 serves as one electrode (drain or source) of the second transistor T2. The portion of the second semiconductor layer 71 connected to the first bit line 54 and the first conductive layer 43 serves as the channel of the first transistor T1, and the portion of the second semiconductor layer 71 connected to the second bit line 55 and the first conductive layer 43 serves as the channel of the second transistor T2. It is understood that the first transistor T1 and the second transistor T2 are a single integrated structure, comprising the portion of the write line WWL located in the first insulating layer 21 and in contact with the second gate dielectric layer 72, the second gate dielectric layer 72, and the second semiconductor layer 71.

[0147] It is understandable that the first transistor T1 and the second transistor T2 are disposed in the first insulating layer 21, and the write line WWL passes through the stacked structure 2, thereby connecting the integral structure stacked vertically along the Z direction in series.

[0148] As shown in Figure 12, the number of memory cells in the memory cell column of this semiconductor device is the same as the number of first insulating layers 21 in the stacked structure 2. It should be noted that the number of memory cell columns shown in Figure 12 is only an example, and this disclosure does not limit the number of memory cell columns.

[0149] As shown in Figure 12, the outer peripheral shape of the first semiconductor layer 41 is the same as the inner peripheral shape of the first semiconductor layer 41. Since the first semiconductor layer 41 is a thin film formed in the first transverse groove 32, the outer peripheral shape of the first semiconductor layer 41 is the same as the inner peripheral shape of the first semiconductor layer 41, and the outer peripheral dimension of the first semiconductor layer 41 is larger than the inner peripheral dimension of the first semiconductor layer 41. It should be noted that the outer peripheral of the first semiconductor layer 41 refers to the projection of the outer peripheral wall of the first semiconductor layer 41 away from the first gate dielectric layer 42 on the XOY plane, and the inner peripheral of the first semiconductor layer 41 refers to the projection of the inner peripheral wall of the first semiconductor layer 41 in contact with the first gate dielectric layer 42 on the XOY plane.

[0150] Specifically, since a portion of the first semiconductor layer 41 is removed, the projection of the first semiconductor layer 41 (the channel of the read transistor Tr) onto the XOY plane is a notched ring. It can be understood that the read transistor Tr partially surrounds the capacitor C. Furthermore, the inner peripheral wall of the first semiconductor layer 41 matches the bottom of the first lateral groove 32 (the outer peripheral wall of the first gate dielectric layer 42). Therefore, when the projection of the bottom of the first lateral groove 32 onto the XOY plane is circular, the outer and inner peripheries of the first semiconductor layer 41 are notched circles; when the projection of the bottom of the first lateral groove 32 onto the XOY plane is rectangular, the outer and inner peripheries of the first semiconductor layer 41 are notched rectangles. This disclosure does not impose any other limitations on the shape of the outer and inner peripheries of the first semiconductor layer 41.

[0151] The outer periphery of the second semiconductor layer 71 has the same shape as its inner periphery. Since the second semiconductor layer 71 is a thin film formed in the second lateral groove 62, its outer periphery has the same shape as its inner periphery, and the outer periphery dimension is larger than the inner periphery dimension. The inner peripheral wall of the second semiconductor layer 71 fits into the bottom of the second lateral groove 62. Therefore, when the projection of the bottom of the second lateral groove 62 onto the XOY plane is circular, the outer and inner peripheries of the second semiconductor layer 71 are circular; when the projection of the bottom of the second lateral groove 62 onto the XOY plane is rectangular, the outer and inner peripheries of the second semiconductor layer 71 are rectangular. Furthermore, the shape of the outer periphery of the second semiconductor layer 71 is also related to the degree of etching of the first insulating layer 21 when forming the second lateral groove 62. If the first insulating layer 21 is etched to expose the first substructure 40 when forming the second lateral groove 62, then the side of the outer periphery of the second semiconductor layer 71 near the first conductive layer 43 has an arc-shaped depression. If the first insulating layer 21 is etched to just expose the first substructure 40 when forming the second lateral groove 62, then the outer periphery of the first conductive layer 43 is tangent to the outer periphery of the second semiconductor layer 71, and the side of the outer periphery of the second semiconductor layer 71 near the first conductive layer 43 can be a straight line. It should be noted that the outer periphery of the second semiconductor layer 71 refers to the projection of the outer peripheral wall of the second semiconductor layer 71 away from the second gate dielectric layer 72 on the XOY plane, the inner periphery of the second semiconductor layer 71 refers to the projection of the inner peripheral wall of the second semiconductor layer 71 in contact with the second gate dielectric layer 72 on the XOY plane, and the outer periphery of the first conductive layer 43 refers to the projection of the outer peripheral wall of the first conductive layer 43 away from the first dielectric layer 44 on the XOY plane.

[0152] In some embodiments, the channel material of the first transistor and the channel material of the second transistor include a metal oxide semiconductor, wherein the metal oxide semiconductor includes at least one element selected from indium, gallium, zinc, tin and tungsten.

[0153] The channel materials of the first transistor and the second transistor include metal-oxide-semiconductor (MODS). For example, MODS include at least one of indium, gallium, zinc, tin, and tungsten; compounds containing other elements, such as nitrogen (N) and silicon (Si), are also possible; small amounts of other doping elements are also possible. Furthermore, compared to other semiconductor materials, using MODS to form the channels of the first and second transistors (second semiconductor layer 71) allows for better control of semiconductor device manufacturing costs.

[0154] In some embodiments, the metal oxide semiconductor material can be indium gallium zinc oxide (IGZO). When the metal oxide material is IGZO, the leakage current of the transistor is small (less than or equal to 10-15A), thereby ensuring a low refresh rate of the memory cell.It should be noted that the metal oxide material can also be ITO or InSnOx (Indium Tin Oxide), IWO or InWO (Indium Tungsten Oxide), ZnOx (Zinc Oxide), InOx (Indium Oxide), In2O3 (Indium Oxide), SnO2 (Tin Dioxide), TiOx (Tin Dioxide), ZnxOyNz (Zinc Nitride Oxide), MgxZnyOz (Magnesium Zinc Oxide), InxZnyOz (Indium Zinc Oxide), InxGayZnzOa (Indium Gallium Zinc Oxide), ZrxInyZnzOa (Zirconium Indium Zinc Oxide), HfxInyZnzOa (Hafnium Indium Zinc Oxide). Indium Zinc Oxide, SnxInyZnzOa (Tin Indium Zinc Oxide), AlxSnyInzZnaOd (Aluminum Tin Indium Zinc Oxide), SixInyZnzOa (Silicon Indium Zinc Oxide), ZnxSnyOz (Zinc Tin Oxide), AlxZnySnzOa (Aluminum Indium Tin Oxide), GaxZnySnzOa (Gallium Indium Tin Oxide), ZrxZnySnzOa (Zirconium Indium Tin Oxide), InGaSiO (Indium Gallium Silicon Oxide), IAZO (Indium Aluminum Zinc Oxide), IGO (Indium Gallium Oxide). Materials such as indium gallium oxide (IGAO), indium zinc oxide (IZO), and indium zinc oxide (IZOx) are acceptable, as long as the leakage current of the transistor meets the requirements. The specific requirements can be adjusted according to the actual situation.

[0155] This disclosure also provides a semiconductor device, which will be described below with reference to FIG12.

[0156] This disclosure provides a semiconductor device, comprising: a substrate, the substrate including a base and a stacked structure disposed on the base, the stacked structure including alternating first insulating layers and second insulating layers; a plurality of first hole structures and second hole structures penetrating the stacked structure and disposed along a first direction parallel to the base; a memory cell, the memory cell including a first substructure disposed in the second hole structure and a second substructure disposed in the second hole structure; the first substructure including a read transistor and a capacitor, the first substructure being located in the first insulating layer or the second insulating layer; the second substructure including a first transistor and a second transistor, the second substructure being located in the first insulating layer or the second insulating layer.

[0157] This disclosure provides a semiconductor device with a 3T1C memory cell, specifically including two write transistors (a first transistor and a second transistor, respectively), one read transistor, and a capacitor. The two write transistors not only provide redundancy but also enable higher data transfer rates. Furthermore, during the write phase, the parallel-connected first and second transistors can shunt the write current, thereby reducing the performance requirements on the write transistors. Additionally, the memory cells in this semiconductor device can be stacked not only perpendicular to the substrate but also arranged in an array in a plane parallel to the substrate, which is beneficial for increasing the integration density of the memory cells.

[0158] Referring to Figure 12, the substrate includes a substrate 1 and a stacked structure 2. The stacked structure 2 includes an alternately arranged first insulating layer 21 and a second insulating layer 22. The top surface of the stacked structure 2 away from the substrate 1 may include a protective layer 23 for physically protecting the semiconductor device. Exemplarily, the protective layer 23 may include at least one insulating film layer.

[0159] In some embodiments, to avoid electrical connection between multiple rows of memory cells through the substrate 1, at least one isolation layer 24 may be included between the substrate 1 and the stacked structure 2. The material of the isolation layer 24 is an insulating material. For example, the isolation layer 24 between the substrate 1 and the stacked structure 2 may be a second insulating layer.

[0160] The first hole structure 4 and the second hole structure 7 both penetrate the stacked structure 2, and the first substructure 40 and the second substructure 70 are disposed in the first insulating layer 21.

[0161] In some embodiments, a first substructure is disposed in a first insulating layer or a second insulating layer, and a second substructure is disposed in a first insulating layer or a second insulating layer.

[0162] In some embodiments, when the first substructure and the second substructure in the same storage cell are disposed in different layers, for example, when the first substructure is disposed in the first insulating layer and the second substructure is disposed in the second insulating layer, the projection of the first substructure on the XOY plane overlaps with the projection of the second substructure on the XOY plane, that is, the first substructure and the second substructure are coupled.

[0163] In some embodiments, the first hole structure includes a read word line that extends through the stacked structure, and the first substructure includes a capacitor surrounding the read word line and a read transistor that partially surrounds the capacitor.

[0164] In some embodiments, the first hole structure 4 includes a read word line RWL that passes through the stacked structure 2, and the first substructure 40 includes a capacitor C surrounding the read word line RWL and a read transistor Tr that partially surrounds the capacitor C. The read word line RWL can connect the first substructures 40 stacked vertically along the Z direction in series to form the first hole structure 4.

[0165] In some embodiments, the first substructure includes a first dielectric layer and a first conductive layer surrounding the word lines, and a first gate dielectric layer and a first semiconductor layer partially surrounding the first conductive layer.

[0166] In some embodiments, on the XOY plane, the first substructure 40 along the direction away from the read word line RWL includes a first dielectric layer 44 and a first conductive layer 43 surrounding the read word line RWL, and a first gate dielectric layer 42 and a first semiconductor layer 41 partially surrounding the first conductive layer 43, wherein the first gate dielectric layer 42 partially surrounds the first conductive layer 43, and the first semiconductor layer 41 surrounds the first gate dielectric layer 42. The first dielectric layer 44 may be a film layer covering the sidewalls and bottom of the read word line RWL, and the first gate dielectric layer 42 may also cover the sidewalls of the first dielectric layer 44 located in the second insulating layer 22. It is understood that the first dielectric layer 44 and the first gate dielectric layer 42 can extend from the top to the bottom of the stacked structure 2.

[0167] The first conductive layer 43, the first dielectric layer 44, and a portion of the read word line RWL (the portion of the read word line RWL corresponding to the first conductive layer 43) located in the same first insulating layer 21 can form a capacitor C surrounding the read word line RWL. The portion of the first semiconductor layer 41 that contacts the first gate dielectric layer 42 serves as the channel of the read transistor Tr, and the portion of the first conductive layer 43 that contacts the first gate dielectric layer 42 serves as the gate of the read transistor Tr.

[0168] In some embodiments, when the first substructure is located in the first insulating layer, the size of the reading line in the first insulating layer is larger than the size of the reading line in the second insulating layer; when the first substructure is located in the second insulating layer, the size of the reading line in the second insulating layer is larger than the size of the reading line in the first insulating layer.

[0169] In some embodiments, when the first substructure 40 is located in the first insulating layer 21, the size of the read line RWL in the first insulating layer 21 is larger than the size of the read line RWL in the second insulating layer 22. It is understood that the cross-section of the read line RWL in the plane perpendicular to the substrate 1 is serrated. The first conductive layer 43 and the first gate dielectric layer 42 can be formed as film layers that sequentially cover the sidewalls of the portion of the read line RWL located in the first insulating layer 21 to increase the size of the capacitor plates. This can increase the capacitance of the capacitor and effectively improve the data storage capacity, data retention time and stability of the storage cell.

[0170] In other embodiments, when the first substructure is located in the second insulating layer, the size of the read line RWL in the second insulating layer is larger than the size of the read line RWL in the first insulating layer.

[0171] In some embodiments, the second hole structure includes a write line that penetrates the stacked structure, the first transistor and the second transistor are integral structures, and the integral structure surrounds the write line.

[0172] In some embodiments, the second hole structure 7 includes a write line WWL penetrating the stacked structure 2, with an integral structure surrounding the write line WWL. It is understood that, within the same first insulating layer 21, a first transistor T1 surrounds a portion of the sidewall of the write line WWL, and a second transistor T2 surrounds a portion of the sidewall of the write line WWL. The write line WWL can be connected in series with integral structures stacked perpendicularly along the Z direction to form the second hole structure 7.

[0173] In some embodiments, the integral structure includes a second gate dielectric layer and a second semiconductor layer surrounding the writing lines.

[0174] In some embodiments, on the XOY plane, the second substructure 70 along the direction away from the write line WWL includes a second gate dielectric layer 72 and a second semiconductor layer 71 surrounding the write line WWL. The second gate dielectric layer 72 may be a film layer covering the sidewalls and bottom of the write line WWL. It is understood that the first transistor T1 and the second transistor T2 are an integral structure, which includes the portion of the write line WWL located in the first insulating layer 21 and in contact with the second gate dielectric layer 72, the second gate dielectric layer 72, and the second semiconductor layer 71.

[0175] In this configuration, the portion of the write line WWL located in the first insulating layer 21 serves as the common gate of the first transistor T1 and the second transistor T2, a portion of the second semiconductor layer 71 serves as the channel of the first transistor T1, and a portion of the second semiconductor layer 71 serves as the channel of the second transistor T2.

[0176] In some embodiments, the second semiconductor layer is in contact with the first conductive layer.

[0177] In some embodiments, the portion of the first conductive layer 43 not covered by the first gate dielectric layer 42 and the first semiconductor layer 41 contacts the second semiconductor layer 71, and the portion of the first conductive layer 43 that contacts the second semiconductor layer 71 can serve as the common electrode (common source or common drain) of the first transistor T1 and the second transistor T2.

[0178] In some embodiments, when the first substructure and the second substructure in the same memory cell are disposed in different layers, for example, when the first substructure is disposed in the first insulating layer and the second substructure is disposed in the second insulating layer, the projection of the first conductive layer in the first substructure onto the XOY plane overlaps with the projection of the second semiconductor layer in the second substructure onto the XOY plane, and the first gate dielectric layer does not cover the portion where the projection of the first conductive layer onto the XOY plane overlaps with the projection of the second semiconductor layer onto the XOY plane, that is, the first conductive layer in the first substructure is in contact with the second semiconductor layer in the second substructure.

[0179] In some embodiments, the semiconductor device further includes a bit line structure extending along a first direction, wherein a plurality of memory cells arranged along the first direction are connected to the same bit line structure; the bit line structure includes a first bit line disposed on a first side of the memory cell and a second bit line disposed on a second side of the memory cell, wherein the first side and the second side are opposite sides of the memory cell in a second direction; the second direction intersects the first direction and is parallel to the substrate.

[0180] In some embodiments, the semiconductor device further includes a bit line structure 5 extending along the Y direction, with a row of memory cells connected to the same bit line structure 5. The bit line structure 5 includes a first bit line 54 disposed on a first side of the memory cell and a second bit line 55 disposed on a second side of the memory cell, that is, the bit line structure 5 can connect memory cells located in the same first insulating layer 21 and arranged along the Y direction to form a row of memory cells.

[0181] In some embodiments, when the first substructure and the second substructure in the same memory cell are disposed in different layers, for example, when the first substructure is disposed in the first insulating layer and the second substructure is disposed in the second insulating layer, the bit line structure along the Z direction can be located in adjacent first and second insulating layers and the bit line structure does not penetrate adjacent first and second insulating layers. This allows the bit line structure to bridge the first substructure disposed in the first insulating layer and the second substructure disposed in the second insulating layer in the same memory cell.

[0182] In some embodiments, the first bit line is connected to the first semiconductor layer and the second semiconductor layer in the memory cell, and the second bit line is connected to the first semiconductor layer and the second semiconductor layer in the memory cell.

[0183] In some embodiments, along the X direction, the first substructure 40 and the second substructure 70 are substantially the same size, so the first bit line 54 can be connected to the first semiconductor layer 41 and the second semiconductor layer 71 in a row of memory cells, and the second bit line 55 can be connected to the first semiconductor layer 41 and the second semiconductor layer 71 in the same row of memory cells.

[0184] The portion of the first bit line 54 that contacts the first semiconductor layer 41 in the first substructure 40 serves as one pole (source or drain) of the read transistor Tr, and the portion of the second bit line 55 that contacts the first semiconductor layer 41 in the same first substructure 40 serves as the other pole (drain or source) of the read transistor Tr.

[0185] The portion of the first bit line 54 that contacts the second semiconductor layer 71 in the second substructure 70 serves as one electrode (drain or source) of the first transistor T1, and the portion of the second bit line 55 that contacts the second semiconductor layer 71 in the second substructure 70 serves as one electrode (drain or source) of the second transistor T2. The portion of the second semiconductor layer 71 connected to the first bit line 54 and the first conductive layer 43 serves as the channel of the first transistor T1, and the portion of the second semiconductor layer 71 connected to the second bit line 55 and the first conductive layer 43 serves as the channel of the second transistor T2.

[0186] In some embodiments, a second medium layer is included between two adjacent memory cells along a first direction.

[0187] In some embodiments, along the Y direction, at least a second medium layer 63 is included between two adjacent memory cells, the second medium layer 63 being used to isolate two adjacent memory cells in the Y direction.

[0188] In some embodiments, along the Y direction, at least a first insulating layer 21 is included between two adjacent memory cells. In other embodiments, along the Y direction, a second dielectric layer 63 and a first insulating layer 21 are included between two adjacent memory cells.

[0189] In some embodiments, the semiconductor device may further include an isolation structure 56 extending through the stacked structure 2, the isolation structure 56 extending along the Y direction and disposed between two adjacent rows of memory cell columns to isolate two adjacent rows of memory cell columns along the X direction (that is, to isolate two adjacent bit line structures 5).

[0190] In some embodiments, the material of the second semiconductor layer includes a metal oxide semiconductor, wherein the metal oxide semiconductor includes at least one element selected from indium, gallium, zinc, tin, and tungsten.

[0191] In some embodiments, the material of the second semiconductor layer 71 includes a metal oxide semiconductor. For example, the metal oxide semiconductor includes at least one of indium, gallium, zinc, tin, and tungsten; compounds containing other elements, such as nitrogen (N) and silicon (Si), are also excluded; the presence of other small amounts of doping elements is also not excluded. The metal oxide semiconductor material can be indium gallium zinc oxide (IGZO). When the metal oxide material is IGZO, the leakage current of the transistor is relatively small (leakage current less than or equal to 10⁻¹⁵ A), thereby ensuring a low refresh rate for the memory cell. Furthermore, compared to other semiconductor materials, using a metal oxide semiconductor as the channel (second semiconductor layer) for both the first and second transistors allows for better control of the manufacturing cost of the memory cell.

[0192] In some embodiments, the material of the first semiconductor layer includes a single-crystal semiconductor, a polycrystalline semiconductor, or a metal oxide semiconductor.

[0193] In some embodiments, the material of the first semiconductor layer 41 includes a single-crystal semiconductor, a polycrystalline semiconductor, or a metal oxide semiconductor. For example, the material of the first semiconductor layer can be at least one of single-crystal silicon, polycrystalline silicon, or doped polycrystalline silicon, and the material of the first semiconductor layer 41 can also be a metal oxide semiconductor.

[0194] In some embodiments, the outer peripheral shape of the first semiconductor layer is different from the inner peripheral shape of the first semiconductor layer.

[0195] As shown in Figure 12, the projection of the first semiconductor layer 41 onto the XOY plane is a ring with a notch. The inner peripheral wall of the first semiconductor layer 41 matches the outer peripheral wall of the first gate dielectric layer 42. Therefore, when the projection of the outer peripheral wall of the first gate dielectric layer 42 onto the XOY plane is a circle with a notch, the outer and inner peripheral edges of the first semiconductor layer 41 are circles with notches; when the projection of the outer peripheral wall of the first gate dielectric layer 42 onto the XOY plane is a rectangle with a notch, the outer and inner peripheral edges of the first semiconductor layer 41 are rectangles with notches.

[0196] The outer periphery shape of the second semiconductor layer 71 is the same as the inner periphery shape of the second semiconductor layer 71, and the outer periphery size of the second semiconductor layer 71 is larger than the inner periphery size of the second semiconductor layer 71.

[0197] Here, the specific structure and other details of the semiconductor device are similar to those of the semiconductor device obtained by the aforementioned preparation method. For any parts not mentioned, please refer to the above preparation method embodiments, which will not be repeated here.

[0198] This disclosure provides a memory cell, including: an address line structure comprising a first address line and a second address line; a read transistor comprising a first electrode connected to the first address line, a second electrode connected to the second address line, and a first gate connected to a memory node; a write transistor comprising a first transistor and a second transistor connected in parallel; wherein the first transistor comprises a third electrode connected to the address line structure, a fourth electrode connected to the memory node, and a second gate connected to a write word line; the second transistor comprises a fifth electrode connected to the address line structure, a sixth electrode connected to the memory node, and a third gate connected to the write word line; the second gate and the third gate serve as connection terminals of the write word line to connect multiple write transistors in series; and a capacitor coupled to the memory node.

[0199] Figure 13(a) is a logic circuit diagram of a memory cell provided in an embodiment of this disclosure, and Figure (b) is a structural schematic diagram of the memory cell shown in Figure (a). Referring to Figure 13, the read transistor Tr1 includes a first electrode P11 connected to the first address line A1, a second electrode P21 connected to the second address line A2, and a first gate G11 connected to the storage node SN; the write transistor includes a first transistor T11 and a second transistor T21. The first transistor T11 includes a third electrode P31 connected to the address line structure, a fourth electrode P41 connected to the storage node SN, and a second gate G21 connected to the write word line WWL; the second transistor T21 includes a fifth electrode P51 connected to the address line structure, a sixth electrode P61 connected to the storage node SN, and a third gate G31 connected to the write word line WWL, as well as a capacitor coupled to the storage node SN. The capacitor may be a parasitic capacitance of the read transistor Tr1.

[0200] In some embodiments, the third electrode and the fifth electrode are connected to the first address line.

[0201] Referring to Figure 13, the third electrode P31 and the fifth electrode P51 are connected to the first address line A1.

[0202] The memory cell includes a first substructure and a second substructure arranged along the Y direction. The first substructure includes a read transistor Tr1 and a capacitor, and the second substructure includes a write transistor. The first substructure includes an insulating structure 131 extending along the Z direction, a first conductive layer 132 surrounding the insulating structure 131, a first gate dielectric layer 133 partially surrounding the first conductive layer 132, and a first semiconductor layer 134. The second substructure includes a write word line WWL extending along the Z direction, a second gate dielectric layer 135 surrounding the write word line WWL, and a second semiconductor layer 136. The portion of the first conductive layer 132 not covered by the first gate dielectric layer 133 and the first semiconductor layer 134 is connected to the second semiconductor layer 136. The insulating structure 131, the first gate dielectric layer 133, and the second gate dielectric layer 135 are made of dielectric material; the first conductive layer 132, the first address line A1, the second address line A2, and the write word line WWL are made of conductive material; and the first semiconductor layer 134 and the second semiconductor layer 136 are made of semiconductor material.

[0203] The memory cell also includes an address line structure, which includes a first address line A1 extending along the Y direction and a second address line A2 extending along the Z direction. The first address line A1 and the second address line A2 are respectively disposed on both sides of the memory cell along the X direction. Specifically, the first address line A1 is connected to the first semiconductor layer 134 and the second semiconductor layer 136, and the second address line A2 is connected to the first semiconductor layer 134.

[0204] In this configuration, the first conductive layer 132 serves as the storage node SN, the portion of the first address line A1 that contacts the first semiconductor layer 134 serves as the first electrode P11, the portion of the second address line A2 that contacts the first semiconductor layer 134 serves as the second electrode P21, the portion of the first semiconductor layer 134 that contacts the first gate dielectric layer 133 serves as the channel of the read transistor Tr1, and the portion of the first conductive layer 132 that contacts the first gate dielectric layer 133 serves as the first gate G11.

[0205] The portion of the first address line A1 that contacts the second semiconductor layer 136 serves as the third electrode P31 and the fifth electrode P51; the portion of the first conductive layer 132 that contacts the second semiconductor layer 136 serves as the fourth electrode P41 and the sixth electrode P61; the portion of the write line WWL that corresponds to the second semiconductor layer 136 serves as the second gate G21 and the third gate G31; the portion of the second semiconductor layer 136 that contacts the first conductive layer 132 and the first address line A1 serves as the two locations where the channels of the first transistor T11 and the second transistor T21 are connected end to end to form a loop.

[0206] The first conductive layer 132, the first gate dielectric layer 133, and the first semiconductor layer 134 constitute a capacitor coupled to the storage node SN.

[0207] The second address line A2 connects the read transistor Tr1 into a column along the Z direction, and the write word line WWL connects the write transistor into a column along the Z direction. That is, the second address line A2 and the write word line WWL connect the memory cells along the Z direction to form a column of memory cells. The first address line A1 connects the memory cells arranged along the Y direction into a row of memory cells. In addition, adjacent memory cells in the memory cells arranged along the X direction are isolated from each other.

[0208] The memory cell provided in this embodiment includes two write transistors (a first transistor and a second transistor, respectively), one read transistor, and a capacitor. The two write transistors not only provide redundancy but also enable higher data transfer rates. Furthermore, during the write phase, the parallel connection of the first and second transistors can shunt the write current, thereby reducing the performance requirements on the write transistors. In addition, the memory cell can be stacked not only along the Z-axis but also arranged in an array in the XOY plane, which is beneficial for improving the integration density of the memory cell.

[0209] In some embodiments, the size of the insulating structure located in the first substructure is larger than the size of the insulating structure located between two adjacent first substructures disposed along a direction perpendicular to the substrate. It is understood that the cross-section of the insulating structure in the plane perpendicular to the substrate is serrated. The first conductive layer and the first gate dielectric layer can be formed as film layers that sequentially cover the sidewalls of the portion of the insulating structure located in the first substructure to increase the size of the capacitor plates. This can increase the capacitance of the capacitor and effectively improve the data storage capacity, data retention time and stability of the storage cell.

[0210] Here, the specific structure and other details of the first conductive layer, the first gate dielectric layer, the first semiconductor layer and the second substructure in the memory cell in Figure 13 are similar to those in the aforementioned semiconductor device and its fabrication method. For parts not mentioned, please refer to the above-mentioned embodiments of the semiconductor device and its fabrication method, which will not be repeated here.

[0211] In some embodiments, the capacitor includes a first plate connected to the storage node and a second plate grounded; a third electrode and a fifth electrode are connected to a first address line.

[0212] Figure 14(a) is a logic circuit diagram of a memory cell provided in an embodiment of this disclosure, and Figure (b) is a structural schematic diagram of the memory cell shown in Figure (a). Referring to Figure 14, the read transistor Tr2 includes a first electrode P12 connected to the first address line A1, a second electrode P22 connected to the second address line A2, and a first gate G12 connected to the memory node SN; the write transistor includes a first transistor T12 and a second transistor T22. The first transistor T12 includes a third electrode P32 connected to the first address line A1, a fourth electrode P42 connected to the memory node SN, and a second gate G22 connected to the write word line WWL; the second transistor T22 includes a fifth electrode P52 connected to the first address line A1, a sixth electrode P62 connected to the memory node SN, and a third gate G32 connected to the write word line WWL; the capacitor C2 includes a first plate E12 connected to the memory node SN and a grounded second plate E22.

[0213] Referring to Figure 14, the memory cell includes a first substructure and a second substructure arranged along the Y direction. The first substructure includes a read transistor Tr2 and a capacitor C2, and the second substructure includes a write transistor. The first substructure includes a conductive structure 140 extending along the Z direction, a first dielectric layer 141 and a first conductive layer 142 sequentially surrounding the conductive structure 140, a first gate dielectric layer 143 partially surrounding the first conductive layer 142, and a first semiconductor layer 144, wherein the conductive structure 140 is grounded. The second substructure includes a write word line WWL extending along the Z direction, a second gate dielectric layer 145 surrounding the write word line WWL, and a second semiconductor layer 146. The portion of the first conductive layer 142 not covered by the first gate dielectric layer 143 and the first semiconductor layer 144 is connected to the second semiconductor layer 146. The materials of the first dielectric layer 141, the first gate dielectric layer 143, and the second gate dielectric layer 145 include dielectric materials; the materials of the conductive structure 140, the first conductive layer 142, the first address line A1, the second address line A2, and the write word line WWL include conductive materials; and the materials of the first semiconductor layer 144 and the second semiconductor layer 146 include semiconductor materials.

[0214] The memory cell also includes an address line structure, which includes a first address line A1 extending along the Y direction and a second address line A2 extending along the Z direction. The first address line A1 and the second address line A2 are respectively disposed on both sides of the memory cell along the X direction. Specifically, the first address line A1 is connected to the first semiconductor layer 144 and the second semiconductor layer 146, and the second address line A2 is connected to the first semiconductor layer 144.

[0215] In this configuration, the first conductive layer 142 serves as the storage node SN, the portion of the first address line A1 that contacts the first semiconductor layer 144 serves as the first electrode P12, the portion of the second address line A2 that contacts the first semiconductor layer 144 serves as the second electrode P22, the portion of the first semiconductor layer 144 that contacts the first gate dielectric layer 143 serves as the channel of the read transistor Tr2, and the portion of the first conductive layer 142 that contacts the first gate dielectric layer 143 serves as the first gate G12.

[0216] The portion of the first address line A1 that contacts the second semiconductor layer 146 serves as the third electrode P32 and the fifth electrode P52; the portion of the first conductive layer 142 that contacts the second semiconductor layer 146 serves as the fourth electrode P42 and the sixth electrode P62; the portion of the write line WWL that corresponds to the second semiconductor layer 146 serves as the second gate G22 and the third gate G32; the portion of the second semiconductor layer 146 that contacts the first conductive layer 142 and the first address line A1 serves as the two locations where the channels of the first transistor T12 and the second transistor T22 are connected. It can be understood that the channels of the first transistor T12 and the second transistor T22 are connected end to end to form a loop.

[0217] The portion of the first conductive layer 142 that contacts the first dielectric layer 141 serves as the first electrode plate E12, and the portion of the conductive structure 140 that corresponds to the first conductive layer 142 serves as the second electrode plate E22, thus forming a capacitor C2.

[0218] Conductive structure 140 connects capacitor C2 in a column along the Z direction, second address line A2 connects read transistor Tr2 in a column along the Z direction, and write word line WWL connects write transistor in a column along the Z direction. That is, conductive structure 140, second address line A2 and write word line WWL connect memory cells in a column along the Z direction to form a column of memory cells, and first address line A1 connects memory cells arranged along the Y direction to form a row of memory cells.

[0219] In some embodiments, the size of the conductive structure located in the first substructure is larger than the size of the conductive structure located between two adjacent first substructures disposed along a direction perpendicular to the substrate. It is understood that the cross-section of the conductive structure in the plane perpendicular to the substrate is serrated. The first dielectric layer and the first conductive layer can be formed as film layers that sequentially cover the sidewalls of the portion of the conductive structure located in the first substructure to increase the size of the capacitor plates. This can increase the capacitance of the capacitor and effectively improve the data storage capacity, data retention time and stability of the storage cell.

[0220] Here, the specific structure and other details of the first dielectric layer, first conductive layer, first gate dielectric layer, first semiconductor layer and second substructure in the memory cell of Figure 14 are similar to those in the aforementioned semiconductor device and its fabrication method. For parts not mentioned, please refer to the above-mentioned embodiments of semiconductor device and its fabrication method, which will not be repeated here.

[0221] In some embodiments, the capacitor includes a first plate connected to the storage node and a second plate connected to the read line; the second plate serves as the connection end of the read line to connect multiple capacitors in series.

[0222] Figure 15(a) is a logic circuit diagram of a memory cell provided in an embodiment of this disclosure, and Figure (b) is a structural schematic diagram of the memory cell shown in Figure (a). Referring to Figure 15, the read transistor Tr3 includes a first electrode P13 connected to the first address line A1, a second electrode P23 connected to the second address line A2, and a first gate G13 connected to the memory node SN; the write transistor includes a first transistor T13 and a second transistor T23. The first transistor T13 includes a third electrode P33 connected to the first address line A1, a fourth electrode P43 connected to the memory node SN, and a second gate G23 connected to the write word line WWL; the second transistor T23 includes a fifth electrode P53 connected to the first address line A1, a sixth electrode P63 connected to the memory node SN, and a third gate G33 connected to the write word line WWL; the capacitor C3 includes a first plate E13 connected to the memory node SN and a second plate E23 connected to the read word line RWL.

[0223] Referring to Figure 15, the memory cell includes a first substructure and a second substructure arranged along the Y direction. The first substructure includes a read transistor Tr3 and a capacitor C3, and the second substructure includes a write transistor. The first substructure includes a read word line RWL extending along the Z direction, a first dielectric layer 151 and a first conductive layer 152 sequentially surrounding the read word line RWL, a first gate dielectric layer 153 partially surrounding the first conductive layer 152, and a first semiconductor layer 154. The second substructure includes a write word line WWL extending along the Z direction, a second gate dielectric layer 155 surrounding the write word line WWL, and a second semiconductor layer 156. The portion of the first conductive layer 152 not covered by the first gate dielectric layer 153 and the first semiconductor layer 154 is connected to the second semiconductor layer 156. The materials of the first dielectric layer 151, the first gate dielectric layer 153, and the second gate dielectric layer 155 include dielectric materials; the materials of the first conductive layer 152, the first address line A1, the second address line A2, the read word line RWL, and the write word line WWL include conductive materials; and the materials of the first semiconductor layer 154 and the second semiconductor layer 156 include semiconductor materials.

[0224] The memory cell also includes an address line structure, which includes a first address line A1 extending along the Y direction and a second address line A2 extending along the Y direction. The first address line A1 and the second address line A2 are respectively disposed on both sides of the memory cell along the X direction. Specifically, the first address line A1 is connected to the first semiconductor layer 154 and the second semiconductor layer 156, and the second address line A2 is connected to the first semiconductor layer 154. It can be understood that the second address line A2 is not in contact with the write transistor.

[0225] In this configuration, the first conductive layer 152 serves as the storage node SN, the portion of the first address line A1 that contacts the first semiconductor layer 154 serves as the first electrode P13, the portion of the second address line A2 that contacts the first semiconductor layer 154 serves as the second electrode P23, the portion of the first semiconductor layer 154 that contacts the first gate dielectric layer 153 serves as the channel of the read transistor Tr3, and the portion of the first conductive layer 152 that contacts the first gate dielectric layer 153 serves as the first gate G13.

[0226] The portion of the first address line A1 that contacts the second semiconductor layer 156 serves as the third electrode P33 and the fifth electrode P53; the portion of the first conductive layer 152 that contacts the second semiconductor layer 156 serves as the fourth electrode P43 and the sixth electrode P63; the portion of the write line WWL that corresponds to the second semiconductor layer 156 serves as the second gate G23 and the third gate G33; the portion of the second semiconductor layer 156 that contacts the first conductive layer 152 and the first address line A1 serves as the two locations where the channels of the first transistor T13 and the second transistor T23 are connected. It can be understood that the channels of the first transistor T13 and the second transistor T23 are connected end to end to form a loop.

[0227] The portion of the first conductive layer 152 that contacts the first dielectric layer 151 serves as the first electrode plate E13, and the portion of the read line RWL that corresponds to the first conductive layer 152 serves as the second electrode plate E23, thus forming a capacitor C3.

[0228] The read word line RWL connects capacitor C3 and read transistor Tr3 in a column along the Z direction, and the write word line WWL connects write transistors in a column along the Z direction. That is, the read word line RWL and the write word line WWL connect the memory cells in the Z direction to form a column of memory cells. The first address line A1 and the second address line A2 connect the memory cells arranged in the Y direction to form a row of memory cells.

[0229] In some embodiments, the second address line A2 in the memory cell shown in FIG15 can be connected to a reference voltage.

[0230] In some embodiments, the size of the read line located in the first substructure is larger than the size of the read line located between two adjacent first substructures disposed along a direction perpendicular to the substrate. It is understood that the cross-section of the read line in the plane perpendicular to the substrate is sawtooth-shaped. The first dielectric layer and the first conductive layer can be formed as film layers that sequentially cover the sidewalls of the portion of the read line located in the first substructure to increase the size of the capacitor plates. This can increase the capacitance of the capacitor and effectively improve the data storage capacity, data retention time and stability of the storage cell.

[0231] Here, the specific structure and other details of the first and second substructures in the memory cell in Figure 15 are similar to those in the aforementioned semiconductor devices and their fabrication methods. For any parts not mentioned, please refer to the above-mentioned embodiments of semiconductor devices and their fabrication methods. They will not be repeated here.

[0232] In some embodiments, the third electrode is connected to the first address line, and the fifth electrode is connected to the second address line.

[0233] Figure 16(a) is a logic circuit diagram of a memory cell provided in an embodiment of this disclosure, and Figure (b) is a structural schematic diagram of the memory cell shown in Figure (a). Referring to Figure 16, the read transistor Tr4 includes a first electrode P14 connected to the first address line A1, a second electrode P24 connected to the second address line A2, and a first gate G14 connected to the memory node SN; the write transistor includes a first transistor T14 and a second transistor T24. The first transistor T14 includes a third electrode P34 connected to the first address line A1, a fourth electrode P44 connected to the memory node SN, and a second gate G24 connected to the write word line WWL; the second transistor T24 includes a fifth electrode P54 connected to the second address line A2, a sixth electrode P64 connected to the memory node SN, and a third gate G34 connected to the write word line WWL; the capacitor C4 includes a first plate E14 connected to the memory node SN and a second plate E24 connected to the read word line RWL.

[0234] Referring to Figure 16, the memory cell includes a first substructure and a second substructure arranged along the Y direction. The first substructure includes a read transistor Tr4 and a capacitor C4, and the second substructure includes a write transistor. The first substructure includes a read word line RWL extending along the Z direction, a first dielectric layer 161 and a first conductive layer 162 sequentially surrounding the read word line RWL, a first gate dielectric layer 163 partially surrounding the first conductive layer 162, and a first semiconductor layer 164. The second substructure includes a write word line WWL extending along the Z direction, a second gate dielectric layer 165 surrounding the write word line WWL, and a second semiconductor layer 166. The portion of the first conductive layer 162 not covered by the first gate dielectric layer 163 and the first semiconductor layer 164 is connected to the second semiconductor layer 166. The materials of the first dielectric layer 161, the first gate dielectric layer 163, and the second gate dielectric layer 165 include dielectric materials; the materials of the first conductive layer 162, the first address line A1, the second address line A2, the read word line RWL, and the write word line WWL include conductive materials; and the materials of the first semiconductor layer 164 and the second semiconductor layer 166 include semiconductor materials.

[0235] The memory cell also includes an address line structure, which includes a first address line A1 extending along the Y direction and a second address line A2 extending along the Y direction. The first address line A1 and the second address line A2 are respectively disposed on both sides of the memory cell along the X direction. Specifically, the first address line A1 is connected to the first semiconductor layer 164 and the second semiconductor layer 166, and the second address line A2 is connected to the first semiconductor layer 164 and the second semiconductor layer 166.

[0236] In this configuration, the first conductive layer 162 serves as the storage node SN, the portion of the first address line A1 that contacts the first semiconductor layer 164 serves as the first electrode P14, the portion of the second address line A2 that contacts the first semiconductor layer 164 serves as the second electrode P24, the portion of the first semiconductor layer 164 that contacts the first gate dielectric layer 163 serves as the channel of the read transistor Tr4, and the portion of the first conductive layer 162 that contacts the first gate dielectric layer 163 serves as the first gate G14.

[0237] The portion of the first address line A1 that contacts the second semiconductor layer 166 serves as the third electrode P34; the portion of the second address line A2 that contacts the second semiconductor layer 166 serves as the fifth electrode P54; the portion of the first conductive layer 162 that contacts the second semiconductor layer 166 serves as the fourth electrode P44 and the sixth electrode P64; the portion of the write line WWL that corresponds to the second semiconductor layer 166 serves as the second gate G24 and the third gate G34; the portion of the second semiconductor layer 166 that contacts the first conductive layer 162 serves as the location where the channel of the first transistor T14 connects to the channel of the second transistor T24; the second semiconductor layer 166 located between the location where the second semiconductor layer 166 contacts the first address line A1 and the location where the second semiconductor layer 166 contacts the first conductive layer 162 serves as the channel of the first transistor T14; the second semiconductor layer 166 located between the location where the second address line A2 contacts the second address line A2 and the location where the second semiconductor layer 166 contacts the first conductive layer 162 serves as the channel of the second transistor T24. In the memory cell shown in Figure 16, the channel length of the first transistor T14 is basically the same as that of the second transistor T24, which allows the first transistor T14 and the second transistor T24 to have similar performance. Here, performance refers to threshold voltage, maximum current carrying capacity, and other properties.

[0238] The portion of the first conductive layer 162 that contacts the first dielectric layer 161 serves as the first electrode plate E14, and the portion of the read line RWL that corresponds to the first conductive layer 162 serves as the second electrode plate E24, thus forming a capacitor C4.

[0239] The read word line RWL connects capacitor C4 and read transistor Tr4 in a column along the Z direction, and the write word line WWL connects write transistors in a column along the Z direction. That is, the read word line RWL and the write word line WWL connect the memory cells in the Z direction to form a column of memory cells. The first address line A1 and the second address line A2 connect the memory cells arranged in the Y direction to form a row of memory cells.

[0240] In some embodiments, the channel material of the write transistor includes a metal oxide semiconductor, wherein the metal oxide semiconductor includes at least one element selected from indium, gallium, zinc, tin, and tungsten.

[0241] In some embodiments, the channel material of the write transistor includes a metal-oxide-semiconductor (MODS). For example, the MODS includes at least one of indium, gallium, zinc, tin, and tungsten; compounds containing other elements, such as nitrogen (N) and silicon (Si), are also possible; the presence of other small amounts of doping elements is also possible. The MODS material can be indium gallium zinc oxide (IGZO). When the MODS material is IGZO, the transistor has a low leakage current (less than or equal to 10⁻¹⁵ A), thereby ensuring a low refresh rate for the memory cell. Furthermore, compared to other semiconductor materials, using a MODS as the channel (second semiconductor layer) of the write transistor allows for better control of the memory cell manufacturing cost.

[0242] In some embodiments, the channel material of the read transistor includes a single-crystal semiconductor, a polycrystalline semiconductor, or a metal-oxide-semiconductor.

[0243] In some embodiments, the channel material of the read transistor may include at least one of monocrystalline silicon, polycrystalline silicon, doped polycrystalline silicon, amorphous silicon, and IGZO.

[0244] Here, the specific structure and other details of the first and second substructures in the memory cell in Figure 16 are similar to those in the aforementioned semiconductor devices and their fabrication methods. For parts not mentioned, please refer to the above-mentioned embodiments of semiconductor devices and their fabrication methods, which will not be repeated here.

[0245] This disclosure provides a memory including a plurality of memory cells arranged in an array. Each memory cell includes a first substructure and a second substructure disposed along a first direction parallel to a substrate. The first substructure includes a read transistor and a capacitor, and the second substructure includes a first transistor and a second transistor.

[0246] In some embodiments, the memory further includes read word lines extending in a direction perpendicular to the substrate, with first substructures surrounding the read word lines. The read word lines connect the first substructures in a column along a direction perpendicular to the substrate.

[0247] In some embodiments, the first substructure further includes a capacitor surrounding the read word line and a read transistor partially surrounding the capacitor.

[0248] In some embodiments, the first substructure includes a first dielectric layer and a first conductive layer sequentially surrounding the read word line, and a first gate dielectric layer and a first semiconductor layer partially surrounding the first conductive layer. The portion of the first conductive layer not covered by the first gate dielectric layer and the first semiconductor layer is connected to the second substructure. The portion of the first semiconductor layer that contacts the first gate dielectric layer serves as the channel of the read transistor, and the portion of the first conductive layer that contacts the first gate dielectric layer serves as the gate of the read transistor. The portion of the first conductive layer that contacts the first dielectric layer serves as the first plate of a capacitor, and the portion of the read word line corresponding to the first conductive layer serves as the second plate of the capacitor, thus forming a capacitor.

[0249] In some embodiments, the size of the read line located in the first substructure is larger than the size of the read line located between two adjacent first substructures disposed along a direction perpendicular to the substrate. It is understood that the cross-section of the read line in the plane perpendicular to the substrate is sawtooth-shaped. The first dielectric layer and the first conductive layer can be formed as film layers that sequentially cover the sidewalls of the portion of the read line located in the first substructure to increase the size of the capacitor plates. This can increase the capacitance of the capacitor and effectively improve the data storage capacity, data retention time and stability of the storage cell.

[0250] In some embodiments, the memory further includes write word lines extending in a direction perpendicular to the substrate. The first transistor and the second transistor are integral structures, and the integral structure surrounds the write word lines. A second substructure is connected to the portion of the capacitor not surrounded by the read transistor; specifically, the second substructure is connected to the portion of the first conductive layer not covered by the first gate dielectric layer and the first semiconductor layer. The write word lines connect the integral structures in a column along a direction perpendicular to the substrate.

[0251] In some embodiments, in the Z direction, the first substructure and the second substructure in the same memory cell are staggered, and the projection of the first substructure in the same memory cell onto the XOY plane overlaps with the projection of the second substructure onto the XOY plane. The first gate dielectric layer does not cover the portion where the projection of the first conductive layer onto the XOY plane overlaps with the projection of the second semiconductor layer onto the XOY plane, that is, the first conductive layer in the first substructure is in contact with the second semiconductor layer in the second substructure.

[0252] In some embodiments, the integrated structure includes a second gate dielectric layer and a second semiconductor layer sequentially surrounding the write line. It is understood that the integrated structure includes a portion where the write line contacts the second gate dielectric layer, the second gate dielectric layer, and the second semiconductor layer. The second semiconductor layer serves as the channel for the first transistor and the second transistor, and the portion of the write line corresponding to the second semiconductor layer serves as the gate for the first transistor and the second transistor.

[0253] In some embodiments, the channel materials of the first transistor and the second transistor comprise metal-oxide-semiconductor (MODS), wherein the MODS comprises at least one element selected from indium, gallium, zinc, tin, and tungsten. For example, the MODS material can be indium gallium zinc oxide (IGZO). When the MODS material is IGZO, the transistor has a low leakage current (less than or equal to 10⁻¹⁵ A), thereby ensuring a low refresh rate for the memory. Furthermore, compared to other semiconductor materials, using MODS as the channel for both the first and second transistors (the second semiconductor layer) allows for better control over the memory cells and the manufacturing cost of the memory.

[0254] In some embodiments, the memory further includes a bit line structure extending along a first direction; the bit line structure includes a first bit line and a second bit line located on both sides of the memory cell along a second direction, the first bit line and the second bit line being coupled to the memory cell, the second direction intersecting the first direction, and the second direction being parallel to the substrate.

[0255] In some embodiments, the first bit line and the second bit line are located on opposite sides of the first substructure in the same row and connected to the first semiconductor layer (the channel of the read transistor). The first bit line and the second bit line disposed on opposite sides of the first substructure in the same row constitute a bit line structure. The portion of the first bit line that contacts the first substructure serves as one electrode (source or drain) of the read transistor, and the portion of the second bit line that contacts the same first substructure serves as the other electrode (drain or source) of the read transistor. The bit line structure can connect memory cells in the same row in series.

[0256] In some embodiments, the first bit line and the second bit line are connected to the second semiconductor layer.

[0257] In this configuration, the portion of the first conductive layer that contacts the second substructure (second semiconductor layer) serves as the common electrode (common source or common drain) of the first transistor and the second transistor; the portion of the first bit line that contacts the second substructure (second semiconductor layer) serves as one electrode (drain or source) of the first transistor; the portion of the second bit line that contacts the second substructure (second semiconductor layer) serves as one electrode (drain or source) of the second transistor; the portion of the second semiconductor layer connected to the first bit line and the first conductive layer serves as the channel of the first transistor; and the portion of the second semiconductor layer connected to the second bit line and the first conductive layer serves as the channel of the second transistor.

[0258] In some embodiments, a second medium layer may be included between two adjacent storage cells in a row of storage cells to isolate adjacent storage cells along a first direction.

[0259] In some embodiments, the memory may further include an isolation structure that extends through the stacked structure, the isolation structure extending along a first direction and disposed between two adjacent rows of memory cells to isolate two adjacent rows of memory cells along a second direction (that is, to isolate two adjacent bit line structures).

[0260] Here, the specific structures and other details of the first and second substructures in the semiconductor structure are similar to those in the aforementioned semiconductor devices and their fabrication methods. For any parts not mentioned, please refer to the above-mentioned embodiments of semiconductor devices and their fabrication methods, which will not be repeated here.

[0261] This disclosure provides a read / write method for reading and writing data to a storage cell in any of the above embodiments. The read / write method includes: during the write phase, applying a first level to the write word line to turn on the first transistor and the second transistor, and inputting a storage signal to the third electrode and the fifth electrode to write the storage signal into the storage node and use it as stored data; during the read phase, applying a second level to the end of the capacitor opposite to the storage node, and reading the stored data by sensing whether the read transistor is turned on.

[0262] In some embodiments, during the write phase, a first level is applied to the second and third gates via the write word line to turn on the first and second transistors, and a storage signal is input to the third and fifth electrodes to write the storage signal into the storage node as stored data. It is understood that the larger of the levels on the third and fifth electrodes is used as the storage signal written into the storage node. After the storage signal is written into the storage node, the first level can be disengaged from the first and second transistors via the write word line, and the storage signal is no longer input to the third and fifth electrodes.

[0263] In some embodiments, during the read phase, a second level is applied to the end of the capacitor opposite to the storage node, and a third level and a fourth level are applied to the first bit line and the second bit line, respectively. The third level and the fourth level are different, and one of them is a reference level. The read transistor is turned on by sensing the current change on the first bit line or the second bit line, thus enabling the reading of stored data.

[0264] The two write transistors (the first transistor and the second transistor) not only provide redundancy but also enable a higher data transfer rate. Furthermore, since the first transistor and the second transistor are connected in parallel, the current can be shunted during data writing, thereby reducing the performance requirements of the write transistors.

[0265] In some embodiments, during the read phase, if the read transistor is turned on, the stored data is first data; if the read transistor is not turned on, the stored data is second data, and the first data and the second data are different.

[0266] In some embodiments, during the read phase, if the read transistor is turned on, the stored data is a first data "0"; if the read transistor is not turned on, the stored data is a second data "1"; or, during the read phase, if the read transistor is turned on, the stored data is a first data "1"; if the read transistor is not turned on, the stored data is a second data "0".

[0267] It should be noted that the descriptions of the semiconductor devices, memory cells, read / write methods, and memories above are similar to the descriptions of the semiconductor device fabrication method embodiments above, and have similar beneficial effects. For technical details not disclosed in the semiconductor device, memory cell, read / write method, and memory embodiments of this disclosure, please refer to the descriptions of the semiconductor device fabrication method embodiments of this disclosure for understanding.

[0268] This disclosure provides a memory cell, a semiconductor device, and a method for fabricating the same. The semiconductor device includes: a substrate, comprising a base and a stacked structure disposed on the substrate, the stacked structure including alternating first and second insulating layers; a plurality of first and second via structures penetrating the stacked structure and disposed along a first direction parallel to the substrate; a memory cell, comprising a first substructure disposed in the first via structure and a second substructure disposed in the second via structure; the first substructure including a read transistor and a capacitor, the first substructure being located within the first or second insulating layer; the second substructure including a first transistor and a second transistor, the second substructure being located within the first or second insulating layer. This disclosure provides a semiconductor device with a 3T1C memory cell, specifically including two write transistors (a first transistor and a second transistor, respectively), one read transistor, and a capacitor. The two write transistors not only provide redundancy but also enable higher data transfer rates. Furthermore, during the write phase, the parallel first and second transistors can shunt the write current, thereby reducing the performance requirements of the write transistors. In addition, the memory cells in this semiconductor device can be stacked not only in a direction perpendicular to the substrate, but also arranged in an array in a plane parallel to the substrate, which is beneficial to improving the integration density of the memory cells.

[0269] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0270] The above description is only a preferred embodiment of this disclosure and does not limit the patent scope of this disclosure. All equivalent structural transformations made using the contents of this specification and drawings under the inventive concept of this disclosure, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this disclosure. Industrial applicability

[0271] This disclosure provides a memory cell, a semiconductor device, and a method for fabricating the same. The semiconductor device includes: a substrate, comprising a base and a stacked structure disposed on the substrate, the stacked structure including alternating first and second insulating layers; a plurality of first and second via structures penetrating the stacked structure and disposed along a first direction parallel to the substrate; a memory cell, comprising a first substructure disposed in the first via structure and a second substructure disposed in the second via structure; the first substructure including a read transistor and a capacitor, the first substructure being located within the first or second insulating layer; the second substructure including a first transistor and a second transistor, the second substructure being located within the first or second insulating layer. This disclosure also provides a semiconductor device with a three-transistor single-capacitor memory cell, specifically including two write transistors (a first transistor and a second transistor, respectively), one read transistor, and a capacitor. The two write transistors not only provide redundancy but also enable higher data transfer rates. Furthermore, during the write phase, the parallel first and second transistors can shunt the write current, thereby reducing the performance requirements of the write transistors. In addition, the memory cells in this semiconductor device can be stacked not only in a direction perpendicular to the substrate, but also arranged in an array in a plane parallel to the substrate, which is beneficial to improving the integration density of the memory cells.

Claims

1. A semiconductor device, comprising: The substrate includes a substrate (1) and a stacked structure (2) disposed on the substrate (1), the stacked structure (2) including an alternately disposed first insulating layer (21) and a second insulating layer (22); A plurality of first hole structures (4) and second hole structures (7) are provided through the stacked structure (2) and along a first direction, the first direction being parallel to the substrate (1); The storage unit includes a first substructure (40) disposed in the first hole structure (4) and a second substructure (70) disposed in the second hole structure (7); The first substructure (40) includes a read transistor and a capacitor, and the first substructure (40) is located in the first insulating layer (21) or the second insulating layer (22); The second substructure (70) includes a first transistor and a second transistor, and the second substructure (70) is located in the first insulating layer (21) or the second insulating layer (22).

2. The semiconductor device according to claim 1, wherein, The first hole structure (4) includes a read word line through the stacked structure (2), and the first substructure (40) includes a capacitor surrounding the read word line and a read transistor partially surrounding the capacitor.

3. The semiconductor device according to claim 2, wherein, The first substructure (40) includes a first dielectric layer (44) and a first conductive layer (43) surrounding the word line, and a first gate dielectric layer (42) and a first semiconductor layer (41) partially surrounding the first conductive layer (43).

4. The semiconductor device according to claim 3, wherein, The second hole structure (7) includes a writing line through the stacked structure (2), the first transistor and the second transistor are an integral structure, and the integral structure surrounds the writing line.

5. The semiconductor device according to claim 4, wherein, The integrated structure includes a second gate dielectric layer (72) and a second semiconductor layer (71) surrounding the writing line.

6. The semiconductor device according to claim 5, wherein, The second semiconductor layer (71) is in contact with the first conductive layer (43).

7. The semiconductor device according to claim 5 or 6, wherein, It also includes a bit line structure (5) extending along the first direction, and a plurality of the memory cells arranged along the first direction are connected to the same bit line structure (5); The bit line structure (5) includes a first bit line (54) disposed on the first side of the memory cell and a second bit line (55) disposed on the second side of the memory cell. The first side and the second side are opposite sides of the memory cell in a second direction. The second direction intersects the first direction and is parallel to the substrate (1).

8. The semiconductor device according to claim 7, wherein, The first bit line (54) is connected to the first semiconductor layer (41) and the second semiconductor layer (71) in the memory cell, and the second bit line (55) is connected to the first semiconductor layer (41) and the second semiconductor layer (71) in the memory cell.

9. The semiconductor device according to any one of claims 5 to 8, wherein, The material of the second semiconductor layer (71) includes a metal oxide semiconductor, wherein the metal oxide semiconductor includes at least one element selected from indium, gallium, zinc, tin and tungsten.

10. The semiconductor device according to any one of claims 3 to 9, wherein, The material of the first semiconductor layer (41) includes single-crystal semiconductor, polycrystalline semiconductor or metal oxide semiconductor.

11. The semiconductor device according to any one of claims 3 to 10, wherein, The outer periphery shape of the first semiconductor layer (41) is the same as the inner periphery shape of the first semiconductor layer (41).

12. The semiconductor device according to any one of claims 2 to 11, wherein, When the first substructure (40) is located in the first insulating layer (21), the size of the reading line in the first insulating layer (21) is larger than the size of the reading line in the second insulating layer (22); When the first substructure (40) is located in the second insulating layer (22), the size of the reading line in the second insulating layer (22) is larger than the size of the reading line in the first insulating layer (21).

13. The semiconductor device according to any one of claims 1 to 12, wherein, Along the first direction, a second medium layer (63) is included between two adjacent storage cells.

14. A method for fabricating a semiconductor device, comprising: A substrate is provided, the substrate including a substrate (1) and a stacked structure (2) formed on the substrate (1), the stacked structure (2) including an alternating first insulating layer (21) and a second insulating layer (22); A plurality of first hole structures (4) and second hole structures (7) are formed through the stacked structure (2) and disposed along a first direction, wherein the first direction is parallel to the substrate (1); The first hole structure (4) includes a first substructure (40) disposed in the first insulating layer (21) or the second insulating layer (22), each of the first substructures (40) including a read transistor and a capacitor; The second hole structure (7) includes a second substructure (70) disposed in the first insulating layer (21) or the second insulating layer (22), each second substructure (70) including a first transistor and a second transistor, the first substructure (40) and the second substructure (70) constituting a memory cell.

15. The preparation method according to claim 14, wherein, Forming the first hole structure (4) includes: A first hole (3) is formed through the stacked structure (2); when the first substructure (40) is located in the first insulating layer (21), the size of the first hole (3) in the first insulating layer (21) is larger than the size of the first hole (3) in the second insulating layer (22); when the first substructure (40) is located in the second insulating layer (22), the size of the first hole (3) in the second insulating layer (22) is larger than the size of the first hole (3) in the first insulating layer (21); The first hole structure (4) is formed through the first hole (3), and the first hole structure (4) also includes a reading line that passes through the stacked structure (2), and the capacitor surrounds the reading line.

16. The preparation method according to claim 15, wherein, The formation of the first hole (3) through the stacked structure (2) includes: A first initial hole (31) is formed through the stacked structure (2), and the first insulating layer (21) or the second insulating layer (22) is laterally etched through the first initial hole (31) to form a first lateral groove (32) surrounding the first initial hole (31). The first initial hole (31) and the first lateral groove (32) constitute the first hole (3).

17. The preparation method according to claim 16, wherein, The process of forming the first hole structure (4) through the first hole (3) includes: A read transistor and the capacitor are sequentially formed to cover the bottom of the first transverse groove (32); Conductive material is deposited through the first initial hole (31) to form the reading line that fills the first initial hole (31).

18. The preparation method according to claim 16, wherein, The process of forming the first hole structure (4) through the first hole (3) includes: The read transistor and the capacitor are sequentially formed to cover the bottom and sidewall of the first transverse groove (32); Conductive material is deposited through the first initial hole (31) to form the reading line that fills the first transverse groove (32) and the first initial hole (31); When the first substructure (40) is located on the first insulating layer (21), the size of the reading line on the first insulating layer (21) is greater than the size of the reading line on the second insulating layer (22); when the first substructure (40) is located on the second insulating layer (22), the size of the reading line on the second insulating layer (22) is greater than the size of the reading line on the first insulating layer (21).

19. The preparation method according to any one of claims 14 to 18, wherein, Forming the second hole structure (7) includes: A second hole (6) is formed through the stacked structure (2); when the second substructure (70) is located in the first insulating layer (21), the size of the second hole (6) in the first insulating layer (21) is larger than the size of the second hole (6) in the second insulating layer (22); when the second substructure (70) is located in the second insulating layer (22), the size of the second hole (6) in the second insulating layer (22) is larger than the size of the second hole (6) in the first insulating layer (21); The second hole structure (7) is formed through the second hole (6). The second hole structure (7) also includes a writing line that passes through the stacked structure (2). The first transistor and the second transistor are an integral structure, and the integral structure surrounds the writing line.

20. The preparation method according to claim 19, wherein, The formation of the second hole (6) through the stacked structure (2) includes: A second initial hole (61) is formed through the stacked structure (2), and the projection of the second initial hole (61) on the substrate (1) does not overlap with the projection of the first hole structure (4) on the substrate (1); The first insulating layer (21) or the second insulating layer (22) and the read transistor are laterally etched through the second initial hole (61) to expose a portion of the capacitor, thereby forming a second lateral groove (62) surrounding the second initial hole (61), the second initial hole (61) and the second lateral groove (62) constituting the second hole (6).

21. The preparation method according to claim 20, wherein, The process of forming the second hole structure (7) through the second hole includes: The first transistor and the second transistor are formed in the second lateral groove (62); Conductive material is deposited through the second initial hole (61) to form the writing line that fills the second hole (6).

22. The preparation method according to any one of claims 14 to 21, wherein, The channel material of the first transistor and the channel material of the second transistor both comprise metal oxide semiconductors, wherein the metal oxide semiconductor comprises at least one element selected from indium, gallium, zinc, tin, and tungsten.

23. The preparation method according to any one of claims 14 to 22, wherein, Before forming the second pore structure (7), the preparation method further includes: A bit line structure (5) extending along the first direction is formed, and a plurality of memory cells arranged along the first direction are connected to the same bit line structure (5). The bit line structure (5) includes a first bit line (54) located on the first side of the memory cell and a second bit line (55) located on the second side of the memory cell. The first side and the second side are opposite sides of the memory cell in a second direction. The second direction intersects the first direction and is parallel to the substrate (1).

24. A storage unit, comprising: The address line structure includes a first address line and a second address line. The read transistor includes a first electrode connected to the first address line, a second electrode connected to the second address line, and a first gate connected to the memory node; A write transistor includes a first transistor and a second transistor connected in parallel; wherein the first transistor includes a third electrode connected to the address line structure, a fourth electrode connected to the memory node, and a second gate connected to the write word line; the second transistor includes a fifth electrode connected to the address line structure, a sixth electrode connected to the memory node, and a third gate connected to the write word line; the second gate and the third gate serve as connection terminals of the write word line to connect multiple write transistors in series. And capacitors coupled to the storage node.

25. The storage unit according to claim 24, wherein, The capacitor includes a first plate connected to the storage node and a second plate grounded. The third electrode and the fifth electrode are connected to the first address line.

26. The storage unit according to claim 24, wherein, The capacitor includes a first plate connected to the storage node and a second plate connected to the read line; the second plate serves as the connection end of the read line to connect multiple capacitors in series.

27. The storage unit according to claim 26, wherein, The third electrode and the fifth electrode are connected to the first address line.

28. The storage unit according to claim 26, wherein, The third electrode is connected to the first address line, and the fifth electrode is connected to the second address line.

29. The storage unit according to any one of claims 24 to 28, wherein, The channel material of the write transistor includes a metal oxide semiconductor, wherein the metal oxide semiconductor includes at least one element selected from indium, gallium, zinc, tin and tungsten.

30. The storage unit according to any one of claims 24 to 29, wherein, The channel material of the read transistor includes single-crystal semiconductor, polycrystalline semiconductor, or metal oxide semiconductor.

31. The storage unit according to any one of claims 24 to 30, wherein, The storage cell includes a first substructure and a second substructure disposed along a first direction, the first direction being parallel to the substrate; The first substructure includes the read transistor and the capacitor, and the second substructure includes the first transistor and the second transistor.

32. The storage unit according to any one of claims 24 to 31, wherein, During the writing phase, a first level is applied to the write word line to turn on the first transistor and the second transistor, and a storage signal is input to the third electrode and the fifth electrode to write the storage signal into the storage node as stored data; During the read phase, a second voltage level is applied to the end of the capacitor opposite to the storage node, and the stored data is read by sensing whether the read transistor is turned on.

33. The storage unit according to claim 32, wherein, During the reading phase, when the read transistor is turned on, the stored data is the first data; If the read transistor is not turned on, the stored data is the second data, and the first data is different from the second data.

Images