Memory cell, semiconductor device and manufacturing method therefor

Abstract

Provided in the embodiments of the present disclosure are a memory cell, a semiconductor device and a manufacturing method therefor. The semiconductor device comprises: a substrate and a stacked structure provided on the substrate, the stacked structure comprising first semiconductor layers and insulating layers that are alternately arranged; a plurality of first hole structures and second hole structures which penetrate the stacked structure and are arranged in a first direction, the first direction being parallel to the substrate; and a memory cell, the memory cell comprising first sub-structures provided in the first hole structures and second sub-structures provided in the second hole structures. The first sub-structures and the second sub-structures are located in the first semiconductor layers, each first sub-structure comprising a first gate structure of a read transistor and a capacitor, and each second sub-structure comprising a first transistor and a second transistor.

Description

Memory cells, semiconductor devices and their fabrication methods

[0001] Cross-references to related applications

[0002] This disclosure is based on and claims priority to Chinese Patent Application No. 202411554729.3, filed on November 1, 2024, entitled Semiconductor Device and Method for Fabrication Thereof, Storage Unit, Read / Write Method and Memory Thereof, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of semiconductor technology, and in particular to a memory cell, a semiconductor device, and a method for fabricating the same. Background Technology

[0004] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and number of devices contained in a single chip are increasing, which means that small differences in the manufacturing process may affect the performance of the devices.

[0005] To minimize product costs, the goal is to fabricate as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands.

[0006] Application content

[0007] In view of this, the present disclosure provides a memory cell, a semiconductor device, and a method for fabricating the same.

[0008] To achieve the above objectives, the technical solution disclosed herein is implemented as follows:

[0009] This disclosure provides a semiconductor device, including: a substrate and a stacked structure disposed on the substrate, the stacked structure including alternating first semiconductor layers and insulating layers; a plurality of first hole structures and second hole structures penetrating the stacked structure and disposed along a first direction parallel to the substrate; a memory cell, the memory cell including a first substructure disposed in the first hole structure and a second substructure disposed in the second hole structure; the first substructure including a first gate structure of a read transistor and a capacitor, the first substructure being located in the first semiconductor layer; the second substructure including a first transistor and a second transistor, the second substructure being located in the first semiconductor layer.

[0010] In some embodiments, the first hole structure includes a read line that penetrates the stacked structure, and the first substructure includes a capacitor surrounding the read line and a first gate structure that partially surrounds the capacitor.

[0011] In some embodiments, the first substructure includes a first dielectric layer and a first conductive layer surrounding a read word line, and a first gate dielectric layer partially surrounding the first conductive layer; wherein the first conductive layer and the first gate dielectric layer constitute a first gate structure, and the first gate structure and the first semiconductor layer constitute a read transistor.

[0012] In some embodiments, the second hole structure includes a writing line that penetrates the stacked structure, the first transistor and the second transistor are integral structures, and the integral structure surrounds the writing line.

[0013] In some embodiments, the integral structure includes a second gate dielectric layer and a second semiconductor layer surrounding the writing lines.

[0014] In some embodiments, the second semiconductor layer is in contact with the first conductive layer.

[0015] In some embodiments, a bit line structure extending along a first direction is further included, and a plurality of memory cells arranged along the first direction are connected to the same bit line structure; the bit line structure includes a first bit line disposed on a first side of the memory cell and a second bit line disposed on a second side of the memory cell, the first side and the second side being opposite sides of the memory cell in a second direction; the second direction intersects the first direction and is parallel to the substrate.

[0016] In some embodiments, the first bit line is connected to the first semiconductor layer and the second semiconductor layer in the memory cell, and the second bit line is connected to the first semiconductor layer and the second semiconductor layer in the memory cell.

[0017] In some embodiments, a media structure is included between two adjacent storage cells along a first direction.

[0018] In some embodiments, the material of the second semiconductor layer includes a metal oxide semiconductor, wherein the metal oxide semiconductor includes at least one element selected from indium, gallium, zinc, tin, and tungsten.

[0019] In some embodiments, the material of the first semiconductor layer includes a single-crystal semiconductor.

[0020] In some embodiments, the outer peripheral shape of the first semiconductor layer is different from the inner peripheral shape of the first semiconductor layer.

[0021] In some embodiments, the size of the read line in the first semiconductor layer is larger than the size of the read line in the insulating layer.

[0022] This disclosure provides a method for fabricating a semiconductor device, comprising: providing a substrate, the substrate including a substrate and a stacked structure formed on the substrate, the stacked structure including alternating first semiconductor layers and sacrificial layers; forming a plurality of first hole structures and second hole structures that penetrate the stacked structure and are disposed along a first direction, the first direction being parallel to the substrate; the first hole structure including a first substructure disposed in the first semiconductor layer, each first substructure including a first gate structure of a read transistor and a capacitor; the second hole structure including a second substructure disposed in the first semiconductor layer, each second substructure including a first transistor and a second transistor, the first substructure and the second substructure located in the same first semiconductor layer constituting a memory cell.

[0023] In some embodiments, forming a first hole structure includes: forming a first insulating layer and a first hole through the stacked structure, wherein the size of the first hole in the first semiconductor layer is larger than the size of the first hole in the sacrificial layer, the first insulating layer is located in the sacrificial layer and surrounds the first hole; forming the first hole structure through the first hole, the first hole structure also includes a read line through the stacked structure, and a capacitor surrounds the read line.

[0024] In some embodiments, forming a first insulating layer and a first via through the stacked structure includes: forming a first initial via through the stacked structure; replacing a portion of the sacrificial layer with an insulating material through the first initial via to form a first insulating layer; and laterally etching a first semiconductor layer through the first initial via to form a first lateral groove surrounding the first initial via, wherein the first initial via and the first lateral groove constitute the first via.

[0025] In some embodiments, forming a first hole structure through a first hole includes: sequentially forming a first gate structure and a capacitor covering the bottom of a first lateral groove; and depositing conductive material through a first initial hole to form a read line filling the first initial hole.

[0026] In some embodiments, forming a first hole structure through a first hole includes: sequentially forming a first gate structure and a capacitor covering the bottom and sidewalls of a first lateral groove; depositing conductive material through a first initial hole to form a read line filling the first lateral groove and the first initial hole, wherein the size of the read line in the first semiconductor layer is larger than the size of the read line in the sacrificial layer.

[0027] In some embodiments, forming a second hole structure includes: forming a second hole through the stacked structure, the size of the second hole in the first semiconductor layer being larger than the size of the second hole in the sacrificial layer; forming a second hole structure through the second hole, the second hole structure also including a write line through the stacked structure, the first transistor and the second transistor being an integral structure, and the integral structure surrounding the write line.

[0028] In some embodiments, forming a second hole through the stacked structure includes: forming a second initial hole through the stacked structure, wherein the projection of the second initial hole on the substrate does not overlap with the projection of the first hole structure on the substrate; and laterally etching the first semiconductor layer and the first gate structure through the second initial hole to expose a portion of the capacitor, thereby forming a second lateral groove surrounding the second initial hole, wherein the second initial hole and the second lateral groove constitute the second hole.

[0029] In some embodiments, forming a second hole structure through a second hole includes: forming a first transistor and a second transistor in a second lateral groove; and depositing conductive material through a second initial hole to form a writing line that fills the second hole.

[0030] In some embodiments, the channel material of the read transistor includes a single-crystal semiconductor.

[0031] In some embodiments, the channel material of the first transistor and the channel material of the second transistor include a metal oxide semiconductor, wherein the metal oxide semiconductor includes at least one element selected from indium, gallium, zinc, tin and tungsten.

[0032] In some embodiments, before forming the second hole structure, the fabrication method further includes: forming a bit line structure extending along a first direction in a first semiconductor layer, wherein a plurality of memory cells arranged along the first direction are connected to the same bit line structure; the bit line structure includes a first bit line located on a first side of the memory cell and a second bit line located on a second side of the memory cell, wherein the first side and the second side are opposite sides of the memory cell in a second direction; the second direction intersects the first direction and is parallel to the substrate.

[0033] In some embodiments, before forming the second hole structure, the preparation method further includes: forming a medium structure between two memory cells disposed along a first direction through the second hole.

[0034] This disclosure provides a memory cell, including: an address line structure comprising a first address line and a second address line; a read transistor comprising a first electrode connected to the first address line, a second electrode connected to the second address line, and a first gate connected to a memory node, wherein the channel material of the read transistor comprises a single-crystal semiconductor; a write transistor comprising a first transistor and a second transistor connected in parallel; wherein the first transistor comprises a third electrode connected to the address line structure, a fourth electrode connected to the memory node, and a second gate connected to a write word line; the second transistor comprises a fifth electrode connected to the address line structure, a sixth electrode connected to the memory node, and a third gate connected to the write word line; the second gate and the third gate serve as connection terminals of the write word line to connect multiple write transistors in series; and a capacitor coupled to the memory node.

[0035] In some embodiments, the capacitor includes a first plate connected to the storage node and a second plate grounded; a third electrode and a fifth electrode are connected to a first address line.

[0036] In some embodiments, the capacitor includes a first plate connected to the storage node and a second plate connected to the read line; the second plate serves as the connection end of the read line to connect multiple capacitors in series.

[0037] In some embodiments, the third electrode and the fifth electrode are connected to the first address line.

[0038] In some embodiments, the third electrode is connected to the first address line, and the fifth electrode is connected to the second address line.

[0039] In some embodiments, the channel material of the write transistor includes a metal oxide semiconductor, wherein the metal oxide semiconductor includes at least one element selected from indium, gallium, zinc, tin, and tungsten.

[0040] In some embodiments, each memory cell includes a first structure and a second substructure disposed along a first direction parallel to the substrate; the first structure includes a read transistor and a capacitor, and the second substructure includes a first transistor and a second transistor.

[0041] In some embodiments, during the write phase, a first level is applied to the write word line to turn on the first and second transistors, and a storage signal is input to the third and fifth electrodes to write the storage signal into the storage node as stored data; during the read phase, a second level is applied to the end of the capacitor opposite to the storage node, and the stored data is read by sensing whether the read transistor is turned on. Attached Figure Description

[0042] Figure 1 is a schematic diagram of the steps of a semiconductor device fabrication method provided in an embodiment of this disclosure;

[0043] Figure 2 is a schematic diagram of the structure of the substrate provided in an embodiment of this disclosure;

[0044] Figure 3(a) is a top perspective view of the structure obtained after forming the first filling hole in an embodiment of the present disclosure, located in the sacrificial layer; and Figure 3(b) is a cross-sectional schematic diagram of the structure shown in Figure (a) along line AA'.

[0045] Figure 4(a) is a top perspective view of the structure obtained after forming the first insulating layer and the first initial hole in an embodiment of the present disclosure, located in the sacrificial layer; and Figure 4(b) is a cross-sectional schematic diagram of the structure shown in Figure (a) along line AA'.

[0046] Figure 5(a) is a top perspective view of the structure obtained after forming the first transverse groove in an embodiment of the present disclosure, located in the first semiconductor layer; and Figure 5(b) is a cross-sectional schematic diagram of the structure shown in Figure (a) along line AA'.

[0047] Figure 6(a) is a top perspective view of the structure obtained after forming the first hole structure in an embodiment of the present disclosure, located in the first semiconductor layer; and Figure 6(b) is a cross-sectional schematic diagram of the structure shown in Figure (a) along line AA'.

[0048] Figure 7(a) is a top perspective view of the structure obtained after forming the first hole structure in another embodiment of the present disclosure, located in the first semiconductor layer; and Figure 7(b) is a cross-sectional schematic diagram of the structure shown in Figure (a) along line AA'.

[0049] Figure 8(a) is a top perspective view of the structure obtained after forming the isolation gap in an embodiment of the present disclosure, located in the sacrificial layer; (b) is a cross-sectional schematic diagram of the structure shown in (a) along line AA'; and (c) is a cross-sectional schematic diagram of the structure shown in (a) along line BB'.

[0050] Figure 9(a) is a top perspective view of the structure obtained after forming the second insulating layer in an embodiment of the present disclosure, (b) is a cross-sectional schematic diagram of the structure shown in (a) along line AA', and (c) is a cross-sectional schematic diagram of the structure shown in (a) along line BB'.

[0051] Figure 10(a) is a top perspective view of the structure obtained after forming the first and second line slots in an embodiment of the present disclosure, located in the first semiconductor layer; and (b) is a cross-sectional schematic diagram of the structure shown in (a) along line AA'.

[0052] Figure 11(a) is a top perspective view of the structure obtained after forming the first bit line, the second bit line and the isolation structure in an embodiment of the present disclosure, located in the first semiconductor layer; and (b) is a cross-sectional schematic diagram of the structure shown in (a) along line AA'.

[0053] Figure 12(a) is a top perspective view of the structure obtained after forming the second initial hole in an embodiment of the present disclosure located in the first semiconductor layer, (b) is a cross-sectional schematic diagram of the structure shown in (a) along line BB', and (c) is a cross-sectional schematic diagram of the structure shown in (a) along line CC'.

[0054] Figure 13(a) is a top perspective view of the structure obtained after forming the second initial transverse groove in an embodiment of the present disclosure, located in the first semiconductor layer; (b) is a cross-sectional schematic diagram of the structure shown in (a) along line BB'; and (c) is a cross-sectional schematic diagram of the structure shown in (a) along line CC'.

[0055] Figure 14(a) is a top view of the structure obtained after forming the medium structure and the second hole in one embodiment of the present disclosure, (b) is a cross-sectional view of the structure shown in (a) along line BB', and (c) is a cross-sectional view of the structure shown in (a) along line CC'.

[0056] Figure 15(a) is a top perspective view of the structure obtained after forming the second hole structure in an embodiment of the present disclosure located in the first semiconductor layer, (b) is a cross-sectional schematic diagram of the structure shown in (a) along line AA', (c) is a cross-sectional schematic diagram of the structure shown in (a) along line BB', and (d) is a cross-sectional schematic diagram of the structure shown in (a) along line CC'.

[0057] Figure 16(a) is a logic circuit diagram of a memory cell provided in an embodiment of the present disclosure, and (b) is a structural schematic diagram of the memory cell shown in (a).

[0058] Figure 17(a) is a logic circuit diagram of a memory cell provided in an embodiment of the present disclosure, and (b) is a structural schematic diagram of the memory cell shown in (a).

[0059] Figure 18(a) is a logic circuit diagram of a memory cell provided in an embodiment of the present disclosure, and (b) is a structural schematic diagram of the memory cell shown in (a).

[0060] Figure 19(a) is a logic circuit diagram of a storage unit provided in an embodiment of this disclosure, and Figure 19(b) is a structural schematic diagram of the storage unit shown in Figure (a). Detailed Implementation

[0061] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0062] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0063] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0064] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or part from another element, component, area, layer, or part. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or part discussed below may be referred to as a second element, component, area, layer, or part. And the discussion of a second element, component, area, layer, or part does not imply that the first element, component, area, layer, or part necessarily exists in this disclosure.

[0065] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0066] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0067] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0068] This disclosure provides a method for fabricating a semiconductor device, comprising: providing a substrate, the substrate including a substrate and a stacked structure formed on the substrate, the stacked structure including alternating first semiconductor layers and sacrificial layers; forming a plurality of first hole structures and second hole structures that penetrate the stacked structure and are disposed along a first direction, the first direction being parallel to the substrate; the first hole structure including a first substructure disposed in the first semiconductor layer, each first substructure including a first gate structure of a read transistor and a capacitor; the second hole structure including a second substructure disposed in the first semiconductor layer, each second substructure including a first transistor and a second transistor, the first substructure and the second substructure located in the same first semiconductor layer constituting a memory cell.

[0069] The semiconductor device fabrication method provided in this disclosure forms a semiconductor device with a three-transistor-capacitor (3T1C) memory cell, specifically including two write transistors (a first transistor and a second transistor, respectively), a read transistor, and a capacitor. A first gate structure and a first semiconductor layer constitute the read transistor. The two write transistors not only provide redundancy but also enable higher data transfer rates. Furthermore, during the write phase, the parallel-connected first and second transistors can shunt the write current, thereby reducing the performance requirements on the write transistors. In addition, the memory cells in this semiconductor device can be stacked not only perpendicular to the substrate but also arranged in an array in a plane parallel to the substrate, which is beneficial for increasing the integration density of the memory cells.

[0070] In some embodiments, a first substructure and at least a first semiconductor layer surrounding a portion of the first substructure constitute a first structure, the first structure including a read transistor and a capacitor.

[0071] Figure 1 is a schematic diagram of the steps in a method for fabricating a semiconductor device according to an embodiment of this disclosure. As shown in the figure, the fabrication method includes the following steps:

[0072] Step S10: Provide a substrate, the substrate including a substrate and a stacked structure formed on the substrate, the stacked structure including alternating first semiconductor layers and sacrificial layers.

[0073] Step S20: Form a plurality of through-stacking structures and first and second hole structures disposed along a first direction, the first direction being parallel to the substrate.

[0074] It should be understood that the steps shown in Figure 1 are not exclusive, and other steps may be performed before, after, or between any of the steps shown in the operation.

[0075] Figures 2 to 6 and Figures 8 to 15 are schematic diagrams of the semiconductor device structure at various stages in the fabrication method of the semiconductor device provided in the embodiments of this disclosure. It should be noted that Figures 2 to 6 and Figures 8 to 15 are schematic diagrams reflecting a complete implementation process of the semiconductor device fabrication method, and parts not marked in some figures can be shared with each other. The fabrication method of the semiconductor device provided in the embodiments of this disclosure will be described in detail below with reference to Figures 1, 2 to 6, and 8 to 15.

[0076] It should be noted that, for ease of description, the various directions that may be used in the following description are defined first. In a plane parallel to the substrate, the first intersecting direction (Y direction) and the second direction (X direction) are defined, and in a plane perpendicular to the substrate, the Z direction is defined. The X, Y, and Z directions can be mutually perpendicular.

[0077] The deposition processes involved in the embodiments of this disclosure include, but are not limited to: chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), sputtering, metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), and combinations thereof.

[0078] The etching processes involved in the embodiments of this disclosure include, but are not limited to, dry etching, wet etching, and combinations thereof.

[0079] The "patterning process" involved in the embodiments of this disclosure includes processes such as depositing a film layer, coating photoresist, mask exposure, development, etching, and photoresist stripping, which are mature manufacturing processes in related technologies. Deposition can be performed using known processes such as sputtering, evaporation, and chemical vapor deposition; coating can be performed using known coating processes; and etching can be performed using known methods. No specific limitations are made here.

[0080] The semiconductor structure disclosed herein is at least a portion of the structure that will be used in subsequent processes to form the final device structure. Here, the final device may be a memory, such as DRAM (Dynamic Random Access Memory), or other memory chips or processing chips that contain DRAM memory cells.

[0081] Figure 2 is a schematic diagram of the structure of the substrate provided in an embodiment of this disclosure. Referring to Figure 2, a substrate 1 is provided, and a first semiconductor layer 21 and a sacrificial layer 22 are alternately stacked on the substrate 1 by a deposition process to form a stacked structure 2.

[0082] In some embodiments, the first semiconductor layer 21 may be formed of silicon, and the sacrificial layer 22 may be formed of silicon-germanium, such that the stacked structure 2 is a silicon-silicon-germanium (Si-SiGe) stack. Specifically, the stacked structure 2 can be deposited onto the substrate 1 using a heteroepitaxial process. Due to the good lattice matching between silicon and silicon-germanium, interface defects and stress problems during the stacking process are reduced, and the interface quality of each layer in the formed stacked structure 2 can be better guaranteed.

[0083] In some embodiments, after forming the stacked structure 2 on the substrate 1, a protective layer 23 can be deposited on the top surface of the stacked structure 2 away from the substrate 1 by a deposition process. The protective layer 23 is used to physically protect the semiconductor device. Exemplarily, the protective layer 23 may include at least one insulating film layer.

[0084] In some embodiments, to prevent multiple rows of memory cells from being electrically connected through the substrate 1, at least one isolation layer may be included between the substrate 1 and the stacked structure 2. The isolation layer is made of an insulating material. In other embodiments, at least one replacement layer 24 may be included between the substrate 1 and the stacked structure 2. The replacement layer 24 will be replaced with an insulating material in subsequent processes. In one example, the replacement layer 24 between the substrate 1 and the stacked structure 2 may be a sacrificial layer, which will be replaced with an insulating material in subsequent processes. In another example, the replacement layer 24 may be a first semiconductor layer, and at least the portion of the replacement layer 24 in contact with the rows of memory cells is replaced with an insulating material to prevent multiple rows of memory cells from being electrically connected through the replacement layer 24. In yet another example, the replacement layer 24 between the substrate 1 and the stacked structure may include a sacrificial layer and a first semiconductor layer, wherein the first semiconductor layer in the replacement layer 24 is in contact with the substrate 1, and the sacrificial layer in the replacement layer 24 is in contact with the stacked structure 2. The sacrificial layer in contact with the stacked structure 2 will be replaced with an insulating material in subsequent processes. It should be noted that, in this embodiment of the present disclosure, identical structures located in the same layer (or in the same stacked layers) and arranged along the Y direction are called rows, and identical structures arranged along the Z direction are called columns. For example, memory cells arranged along the Y direction and located in the same first semiconductor layer 21 are called memory cell rows or rows of memory cells, and memory cells arranged along the Z direction are called memory cell columns or columns of memory cells.

[0085] For example, the first semiconductor layer 21 and the sacrificial layer 22 may have the same thickness or different thicknesses, and neither of them is zero. It should be noted that the number of layers of the first semiconductor layer 21 and the sacrificial layer 22 in the stacked structure 2 shown in FIG2 is only an example, and the specific number of layers of the first semiconductor layer 21 and the sacrificial layer 22 in this disclosure is not limited to the number of layers shown in the figure.

[0086] This disclosure does not specifically limit the constituent materials of substrate 1. As an example, substrate 1 can be composed of semiconductor materials, insulating materials, conductive materials, or any combination thereof. The substrate can be a single-layer structure or a multi-layer structure. For example, the substrate can be a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V or II / VI semiconductor substrates. Alternatively, the substrate can be a layered substrate comprising, for example, a stack of Si and SiGe, a stack of Si and SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator.

[0087] The insulating and dielectric materials involved in this disclosure can all be insulating materials with high dielectric constant (High-K, HK), such as dielectric materials with a dielectric constant K greater than or equal to 3.9. These include, but are not limited to, HK materials such as hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), and zirconium oxide (ZrO2); the conductive materials can be materials containing metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; the semiconductor materials can be at least one of monocrystalline silicon, amorphous silicon, polycrystalline silicon, or doped polycrystalline silicon, and the semiconductor materials can also be metal oxide semiconductors.

[0088] The material of the gate dielectric layer (first gate dielectric layer or second gate dielectric layer) involved in this disclosure can be selected from any one or more of silicon oxide (e.g., SiO2), hafnium oxide (e.g., HfO2), zirconium oxide (e.g., ZrO), and aluminum oxide (e.g., Al2O3). The gate dielectric layer can be a single-layer structure or a multi-layer structure. For example, it can include a two-layer structure formed of silicon oxide and hafnium oxide, wherein the silicon oxide layer contacts the channel region and the hafnium oxide layer contacts the gate. The thickness of the gate dielectric layer can be set according to actual electrical requirements, for example, it can be 2 nm to 5 nm.

[0089] It should be noted that the first hole structure and the second hole structure are in one-to-one correspondence. In other words, each column of memory cells includes a first hole structure and a second hole structure, and the device structures in the first hole structure and the second hole structure are coupled.

[0090] In some embodiments, forming a first hole structure includes: forming a first insulating layer and a first hole through the stacked structure, wherein the size of the first hole in the first semiconductor layer is larger than the size of the first hole in the sacrificial layer, and the first insulating layer is located in the sacrificial layer and surrounds the first hole.

[0091] In some embodiments, to avoid electrical connection between multiple first substructures located in the same first hole structure via a sacrificial layer, a first insulating layer surrounding the first hole (first hole structure) can be formed by replacing a portion of the sacrificial layer surrounding the first hole (first hole structure) with an insulating material.

[0092] In some embodiments, forming a first insulating layer and a first via through the stacked structure includes: forming a first initial via through the stacked structure; replacing a portion of the sacrificial layer with an insulating material through the first initial via to form a first insulating layer; and laterally etching a first semiconductor layer through the first initial via to form a first lateral groove surrounding the first initial via, wherein the first initial via and the first lateral groove constitute the first via.

[0093] In some embodiments, forming a first insulating layer and a first hole penetrating the stacked structure 2 includes the following steps:

[0094] The first through hole is formed by patterning the stacked structure 2 through the stacked structure 2 using a patterning process.

[0095] The sacrificial layer 22 is laterally etched through the first through hole to form a first insulating groove surrounding the first through hole. The first insulating groove and the first through hole constitute a first filling hole.

[0096] And deposit insulating material into the first filling hole to form a first filling structure;

[0097] The first filling structure is etched to form a first initial hole, and the first semiconductor layer 21 is laterally etched through the first initial hole to form a first lateral groove surrounding the first initial hole.

[0098] Figure 3(a) is a top perspective view of the structure obtained after forming the first filling hole in an embodiment of this disclosure, located in the sacrificial layer; and Figure 3(b) is a cross-sectional schematic diagram of the structure shown in Figure (a) along line AA'. Referring to Figure 3, a first filling hole is formed that penetrates the stacked structure 2 and the replacement layer 24.

[0099] As shown in Figure 3, a first through-hole 30 is formed, penetrating the stacked structure 2 and the replacement layer 24. Laterally, the sacrificial layer 22 is etched through the first through-hole 30 to form a first insulating groove 31. Here, when forming the first through-hole 30, the substrate 1 is the etching stop layer, meaning the first through-hole 30 theoretically stops on the substrate 1. It should be noted that the trench formed after lateral etching of the sacrificial layer 22 and the replacement layer 24 through the first through-hole 30 is a single unit, where the first through-hole 30 and the first insulating groove 31 are different parts of this trench. The distance between each first filling hole and its adjacent first filling holes is greater than zero.

[0100] In some embodiments, the first through holes 30 are arranged in an array in the stacked structure 2, specifically including a plurality of first through holes 30 arranged along the X direction and a plurality of first through holes 30 arranged along the Y direction. It should be noted that the number of first through holes 30 shown in FIG3 is only an example, and the number of first through holes in this disclosure is not limited to the number shown in FIG3.

[0101] Figure 4(a) is a top perspective view of the structure obtained after forming the first insulating layer and the first initial via in an embodiment of this disclosure, located on the sacrificial layer; Figure 4(b) is a cross-sectional schematic diagram of the structure shown in Figure (a) along line AA'. Referring to Figure 4, insulating material is deposited into the first filling via to form a first filling structure, and the first filling structure is etched to form the first initial via 32. The unetched first filling structure constitutes the first insulating layer 25a and the first isolation portion 26a. The portion of the unetched first filling structure located in the sacrificial layer 22 is the first insulating layer 25a, and the portion of the unetched first filling structure located in the replacement layer 24 is the first isolation portion 26a. Here, the etching of the first initial via 32 needs to stop at the bottom of the first filling structure without penetrating the first filling structure. The distance between the first initial via 32 and the bottom surface (contact surface with the substrate 1) of the first filling structure is greater than zero, that is, the first initial via 32 does not penetrate the first isolation portion 26a. The projection of the first initial via 32 in the XOY plane overlaps with the projection of the first through via 30 in the XOY plane. It should also be noted that the first insulating layer 25a and the first insulating portion 26a are formed in the same steps.

[0102] Figure 5(a) is a top perspective view of the structure obtained after forming the first lateral groove in an embodiment of this disclosure, located in the first semiconductor layer; Figure 5(b) is a cross-sectional schematic diagram of the structure shown in Figure (a) along line AA'. Referring to Figure 5, the first semiconductor layer 21 is laterally etched through the first initial hole 32 to form a first lateral groove 33 surrounding the first initial hole 32. The first initial hole 32 and the first lateral groove 33 constitute the first hole 3. The size of the first hole 3 in the first semiconductor layer 21 is larger than the size of the first hole 3 in the sacrificial layer 22, or in other words, the size of the first hole 3 in the first semiconductor layer 21 is larger than the size of the first hole 3 in the first insulating layer 25a. It can be understood that, on the XOY plane, the orthographic projection of the first hole 3 located in the sacrificial layer 22 falls within the orthographic projection of the first hole 3 located in the first semiconductor layer 21, that is, as shown in Figure 5(b), the cross-section of the first hole 3 is sawtooth-shaped. It should be noted that the trench formed by lateral etching of the first semiconductor layer 21 through the first initial hole 32 is a whole, wherein the first initial hole 32 and the first lateral groove 33 are different parts of the trench. There is a certain distance between each first hole 3 and the other adjacent first holes 3.

[0103] Referring to Figure 5, in the XOY plane, the size of the first insulating layer 25a is at least larger than the size of the first transverse groove 33. It can be understood that, in the XOY plane, the orthographic projection of the first transverse groove 33 falls within the orthographic projection of the first insulating layer 25a.

[0104] In some embodiments, a first hole structure is formed through a first hole, and the first hole structure further includes a reading line that runs through the stacked structure, with a capacitor surrounding the reading line.

[0105] Figure 6(a) is a top perspective view of the structure obtained after forming the first hole structure in an embodiment of the present disclosure, located in the first semiconductor layer; and Figure 6(b) is a cross-sectional schematic diagram of the structure shown in Figure (a) along line AA'. Referring to Figure 6, forming the first hole structure further includes: forming a first hole structure 4 through the first hole 3, wherein the first hole structure 4 includes a first substructure 40 formed in the first semiconductor layer 21.

[0106] In some embodiments, forming a first hole structure through a first hole includes: sequentially forming a first gate structure and a capacitor covering the bottom of a first lateral groove; and depositing conductive material through a first initial hole to form a read line filling the first initial hole.

[0107] Referring to Figure 6, the first hole structure 4 is formed through the first hole 3, including the following steps:

[0108] A first gate structure is formed covering the bottom of the first transverse groove 33;

[0109] A capacitor C (Capacitor) is formed covering the first gate structure;

[0110] This forms a Read Word Line (RWL) that fills the first initial hole 32.

[0111] Exemplarily, the fabrication process of the read transistor Tr includes: forming a first gate dielectric layer 41 covering the bottom and sidewalls of the first lateral groove 33 by a deposition process, and then forming a first conductive layer 42 filling the first lateral groove 33. The portion of the first semiconductor layer 21 that contacts the first gate dielectric layer 41 serves as the channel of the read transistor Tr, and the portion of the first conductive layer 42 that contacts the first gate dielectric layer 41 serves as the gate of the read transistor Tr. The first gate dielectric layer 41 may be a thin film covering the inner wall of the first hole 3. The material of the first gate dielectric layer 41 may be a dielectric material, and the material of the first conductive layer 42 may be a conductive material. In some embodiments, a semiconductor material covering the bottom of the first lateral groove may also be formed by a deposition process before forming the first gate dielectric layer to serve as the channel of the read transistor. It should be noted that the bottom of the first lateral groove refers to the bottom of the first lateral groove in the X direction that exposes the first semiconductor layer, and the sidewalls of the first lateral groove refer to the two opposite sides of the first lateral groove in the Z direction.

[0112] The fabrication process of capacitor C and read line RWL includes: forming a first dielectric layer 43 covering the surfaces of the first gate dielectric layer 41 and the first conductive layer 42 exposed by the first hole 3 through a deposition process; and then depositing conductive material into the first initial hole 32 through a deposition process to form the read line RWL. The first conductive layer 42, the first dielectric layer 43, and a portion of the read line RWL (the portion of the read line RWL corresponding to the first conductive layer 42) located in the same first semiconductor layer 21 can constitute a capacitor C surrounding the read line RWL. It should be noted that the first dielectric layer 43 covers the surfaces of the first gate dielectric layer 41 and the first conductive layer 42 exposed by the first hole 3 after the formation of the first gate structure of the read transistor Tr. The material of the first dielectric layer 43 can be a dielectric material, and the material of the first conductive layer 42 can be a conductive material.

[0113] Understandably, the first gate structure and capacitor C are both formed in the first semiconductor layer 21, and the read word line RWL passes through the stacked structure 2, thereby connecting the first substructures 40 stacked vertically along the Z direction in series. The first insulating layer 25a can prevent multiple first substructures 40 located in the same first hole structure from being electrically connected through the sacrificial layer 22, and the first isolation portion 26a can prevent multiple first hole structures from being electrically connected through the replacement layer 24 and the substrate 1.

[0114] In some embodiments, forming a first hole structure through a first hole includes: sequentially forming a first gate structure and a capacitor covering the bottom and sidewalls of a first lateral groove; depositing conductive material through a first initial hole to form a read line filling the first lateral groove and the first initial hole, wherein the size of the read line in the first semiconductor layer is larger than the size of the read line in the sacrificial layer.

[0115] Figure 7(a) is a top perspective view of the structure obtained after forming the first hole structure in another embodiment of this disclosure, located in the first semiconductor layer; and Figure 7(b) is a cross-sectional schematic diagram of the structure shown in Figure (a) along line AA'. Referring to Figure 7, forming the first hole structure 4' through the first hole 3 includes the following steps:

[0116] A first gate structure is formed that covers the bottom and sidewalls of the first transverse groove 33;

[0117] A capacitor C' covering the first gate structure is formed;

[0118] The reading line RWL' is formed, filling the first transverse groove 33 and the first initial hole 32.

[0119] For example, the fabrication process of the read transistor Tr' includes: forming a first gate dielectric layer 41' covering the bottom and sidewalls of the first lateral groove 33 by a deposition process, and then forming a first conductive layer 42' covering the first gate dielectric layer 41'. The portion of the first semiconductor layer 21 that contacts the first gate dielectric layer 41' serves as the channel of the read transistor Tr', and the portion of the first conductive layer 42' that contacts the first gate dielectric layer 41' serves as the gate of the read transistor Tr'. The first gate dielectric layer 41' may be a thin film covering the inner wall of the first hole 3. The material of the first gate dielectric layer 41' may be a dielectric material, and the material of the first conductive layer 42' may be a conductive material.

[0120] The fabrication process of capacitor C' and read line RWL' includes: forming a first dielectric layer 43' covering the surfaces of the first gate dielectric layer 41' and the first conductive layer 42' exposed by the first hole 3 through a deposition process; and then depositing conductive material into the first hole 3 through a deposition process to form the read line RWL'. The first conductive layer 42', the first dielectric layer 43', and a portion of the read line RWL' (the portion of the read line RWL' corresponding to the first conductive layer 42') located in the same first semiconductor layer 21 can constitute a capacitor C' surrounding the read line RWL'. It should be noted that the first dielectric layer 43' covers the surfaces of the first gate dielectric layer 41' and the first conductive layer 42' exposed by the first hole 3 after the formation of the first gate structure of the read transistor Tr', and the material of the first dielectric layer 43' can be a dielectric material.

[0121] It is understood that the first gate structure and capacitor C' are both formed in the first semiconductor layer 21, and the read word line RWL' passes through the stacked structure 2, thereby connecting the first substructure 40' stacked vertically along the Z direction in series.

[0122] Since the first conductive layer 42' can serve as one of the plates of capacitor C', the first conductive layer 42' can cover the bottom and sidewalls of the first transverse groove 33 (specifically, the inner wall of the first gate dielectric layer 41' in the first semiconductor layer 21) to increase the plate size of capacitor C'. This can increase the capacity of capacitor C' and effectively improve the data storage capacity, data retention time and stability of the storage unit.

[0123] In some embodiments, before forming the second hole structure, the fabrication method further includes: forming a bit line structure extending along a first direction in a first semiconductor layer, wherein a plurality of memory cells arranged along the first direction are connected to the same bit line structure; the bit line structure includes a first bit line located on a first side of the memory cell and a second bit line located on a second side of the memory cell, wherein the first side and the second side are opposite sides of the memory cell in a second direction; the second direction intersects the first direction and is parallel to the substrate.

[0124] In some embodiments, forming a bit line structure extending along a first direction in a first semiconductor layer includes the following steps:

[0125] The stacked structure 2 is patterned using a design process to form an isolation gap that runs through the stacked structure 2;

[0126] The sacrificial layer 22 is replaced with insulating material through the isolation gap to form a second insulating layer;

[0127] The first semiconductor layer 21 is laterally etched through the isolation gap to form the first bit line gap and the second bit line gap.

[0128] Conductive material is deposited in the first and second line gaps through a deposition process to form the first and second lines, and insulating material is filled in the isolation gaps through a deposition process to form an isolation structure.

[0129] Figure 8(a) is a top perspective view of the structure obtained after forming the isolation gap in one embodiment of the present disclosure, located on the sacrificial layer; (b) is a cross-sectional schematic diagram of the structure shown in (a) along line AA'; and (c) is a cross-sectional schematic diagram of the structure shown in (a) along line BB'. Referring to Figure 8, the isolation gap 51 penetrates the stacked structure 2 and the replacement layer 24. The isolation gap 51 is located between two adjacent rows of first substructures 40 along the X direction, and there is a non-zero spacing between the isolation gap 51 and the two adjacent rows of first substructures 40 in the X direction.

[0130] Figure 9(a) is a top perspective view of the structure obtained after forming the second insulating layer in an embodiment of this disclosure, (b) is a cross-sectional schematic diagram of the structure shown in (a) along line AA', and (c) is a cross-sectional schematic diagram of the structure shown in (a) along line BB'. Referring to Figure 9, the remaining sacrificial layer 22 and replacement layer 24 are laterally etched through the isolation gap 51 to form a second insulating groove, and insulating material is deposited into the second insulating groove to form a second insulating layer 25b and a second isolation portion 26b, wherein the first insulating layer 25a and the second insulating layer 25b constitute an insulating layer 25, and the first isolation portion 26a and the second isolation portion 26b constitute an isolation layer 26. It is understood that the sacrificial layer 22 is replaced with insulating material to avoid connection between multiple memory cells located on the same memory cell column, and the replacement layer 24 is replaced with insulating material to avoid connection between multiple memory cell columns. It should be noted that the second insulating layer 25b and the second isolation portion 26b are formed in the same steps.

[0131] Figure 10(a) is a top perspective view of the structure obtained after forming the first and second bit line slots in an embodiment of this disclosure, located on the first semiconductor layer; and (b) is a cross-sectional schematic diagram of the structure shown in (a) along line AA'. Referring to Figure 10, the first semiconductor layer 21 is laterally etched through the isolation slot 51 to form the first bit line slot 52 and the second bit line slot 53. The first bit line slot 52 and the first gate dielectric layer 41 have a certain spacing along the X direction, and the second bit line slot 53 and the first gate dielectric layer 41 also have a certain spacing along the X direction. The first bit line slot 52 is located on the first side of a row of first substructures 40, and the second bit line slot is located on the second side of the same row of first substructures 40. It should be noted that the trench formed after laterally etching the first semiconductor layer 21 through the isolation slot 51 is a whole, wherein the isolation slot 51, the first bit line slot 52, and the second bit line slot 53 are different parts of the trench.

[0132] Figure 11(a) is a top perspective view of the structure obtained after forming the first bit line, the second bit line, and the isolation structure in an embodiment of this disclosure, located in the first semiconductor layer; and (b) is a cross-sectional schematic diagram of the structure shown in (a) along line AA'. Referring to Figure 11, the first bit line 54 is formed in the first bit line gap 52, the second bit line 55 is formed in the second bit line gap 53, and the isolation structure 56 is formed in the isolation gap 51. In some embodiments, before forming the isolation structure 56, the conductive material remaining in the isolation gap 51 (the conductive material remaining when forming the bit line structure 5) can be etched to prevent the bit line structures 5 located in different first semiconductor layers 21 from connecting together. The first bit line 54 is located on the first side of the row read transistor Tr and is connected to the first semiconductor layer 21 (the channel of the read transistor Tr). The second bit line 55 in the same bit line structure 5 is located on the second side of the same row read transistor Tr and is connected to the first semiconductor layer 21 (the channel of the read transistor Tr). The first bit line 54 and the second bit line 55 located on both sides of the row read transistor Tr constitute the bit line structure 5. The isolation structure 56 is used to isolate two adjacent rows of read transistor Tr, that is, to isolate two adjacent bit line structures 5. The part of the first bit line 54 corresponding to the first substructure 40 serves as one pole (source or drain) of the read transistor Tr, and the part of the second bit line 55 corresponding to the same first substructure 40 serves as the other pole (drain or source) of the read transistor Tr. The bit line structure 5 can connect a row of first substructures 40 in series. The first bit line 54 and the second bit line 55 extend along the Y direction.

[0133] In some embodiments, forming a second hole structure includes forming a second hole through the stacked structure, wherein the size of the second hole in the first semiconductor layer is larger than the size of the second hole in the sacrificial layer.

[0134] Figure 12(a) is a top perspective view of the structure obtained after forming the second initial hole in an embodiment of the present disclosure, located in the first semiconductor layer; (b) is a cross-sectional schematic diagram of the structure shown in (a) along line BB'; and (c) is a cross-sectional schematic diagram of the structure shown in (a) along line CC'. Figure 13(a) is a top perspective view of the structure obtained after forming the second initial transverse groove in an embodiment of the present disclosure, located in the first semiconductor layer; (b) is a cross-sectional schematic diagram of the structure shown in (a) along line BB'; and (c) is a cross-sectional schematic diagram of the structure shown in (a) along line CC'. Referring to Figures 12 and 13, forming the second hole structure includes: forming a second hole 6 through the stacked structure 2.

[0135] In some embodiments, forming a second hole through the stacked structure includes: forming a second initial hole through the stacked structure, wherein the projection of the second initial hole on the substrate does not overlap with the projection of the first hole structure on the substrate; and laterally etching the first semiconductor layer and the first gate structure through the second initial hole to expose a portion of the capacitor, thereby forming a second lateral groove surrounding the second initial hole, wherein the second initial hole and the second lateral groove constitute the second hole.

[0136] In some embodiments, forming a second hole 6 through the stacked structure 2 includes the following steps:

[0137] The stacked structure 2 is patterned using a patterning process to form a second initial hole 61 that penetrates the stacked structure 2.

[0138] The first semiconductor layer 21 is laterally etched through the second initial hole 61 to expose a portion of the first gate dielectric layer 41, thereby forming a second initial lateral groove 62 surrounding the second initial hole 61.

[0139] Referring to Figure 12, in the Y direction, the second initial via 61 is disposed between the two first via structures 4, and the distance between the second initial via 61 and the first via structure 4 (specifically the first gate dielectric layer 41) in the same column of memory cells is greater than zero. The distance between the second initial via 61 and the first via structure 4 (specifically the first gate dielectric layer 41) in adjacent other column of memory cells is also greater than zero, and the distance between the second initial via 61 and the first via structure 4 in the same column of memory cells is less than the distance between the second initial via 61 and the first via structure 4 in adjacent other column of memory cells. In the X direction, the second initial via 61 is disposed between the first bit line 54 and the second bit line 55, and the distance between the second initial via 61 and the first bit line 54 is greater than zero. Here, when forming the second initial via 61, the isolation layer 26 is an etching stop layer, that is, the second initial via 61 theoretically stops on the isolation layer 26.

[0140] Referring to Figure 13, the second initial lateral groove 62 surrounds the second initial hole 61. Along the Y direction, the second initial lateral groove 62 is positioned between the two first hole structures 4, and the distance between the second initial lateral groove 62 and the first hole structure 4 in the same column of memory cells (specifically, the portion of the first gate dielectric layer 41 exposed by the second initial lateral groove 62) is zero. The distance between the second initial lateral groove 62 and the first hole structure 4 in adjacent other column of memory cells is greater than zero, ensuring that the channel (first semiconductor layer 21) of the read transistor Tr in adjacent other column of memory cells at least partially surrounds the first gate dielectric layer 41 in the other column of memory cells. In the X direction, the second initial lateral groove 62 exposes the first bit line 54 and the second bit line 55. It should be noted that the trench formed after lateral etching of the first semiconductor layer 21 through the second initial hole 61 is a single unit, wherein the second initial hole 61 and the second initial lateral groove 62 are different parts of this trench.

[0141] In some embodiments, before forming the second hole structure, the preparation method further includes: forming a medium structure between two memory cells disposed along a first direction through the second hole.

[0142] Figure 14(a) is a top perspective view of the structure obtained after forming the dielectric structure and the second hole in an embodiment of this disclosure, located in the first semiconductor layer; (b) is a cross-sectional schematic diagram of the structure shown in (a) along line BB'; and (c) is a cross-sectional schematic diagram of the structure shown in (a) along line CC'. Referring to Figure 14, the following steps are also included before forming the second hole structure:

[0143] Deposit medium material into the second initial hole 61 and the second initial transverse groove 62;

[0144] The dielectric material in the second initial hole 61 and the second initial lateral groove 62, as well as the first gate dielectric layer 41, are laterally etched to expose the first conductive layer 42, the first bit line 54, and the second bit line 55 to form the second lateral groove 64. The remaining dielectric material serves as the dielectric structure 63.

[0145] It should be noted that since the material of the first gate dielectric layer 41 is the same as the dielectric material (the dielectric material filling the second initial hole 61 and the second initial lateral groove 62), when the dielectric material is laterally etched, the first gate dielectric layer 41 is also laterally etched simultaneously to expose the first conductive layer 42 (one electrode of the capacitor C). In other embodiments, the material of the first gate dielectric layer 41 is different from the dielectric material (the dielectric material filling the second initial hole 61 and the second initial lateral groove 62), and the first gate dielectric layer 41 can also be laterally etched to expose the first conductive layer 42 after the dielectric structure 63 is formed.

[0146] In some embodiments, the first gate dielectric layer 41 may be laterally etched to expose the first conductive layer 42 (one electrode of capacitor C) before forming the dielectric structure 63, that is, the first gate dielectric layer 41 may be laterally etched to expose the first conductive layer 42 before depositing dielectric material into the second initial hole 61 and the second initial lateral groove 62.

[0147] Referring to Figure 13, the dimension of the second initial lateral groove 62 in the direction near the first gate dielectric layer 41 is smaller than the dimension of the second initial lateral groove 62 in the direction near the first semiconductor layer 21. After depositing dielectric material in the second initial hole 61 and the second initial lateral groove 62 shown in Figure 13, since the etching rate of the dielectric material in the Y direction is the same, after the etching of the dielectric material stops, there is a dielectric material of a certain thickness between the second initial lateral groove 62 and the first semiconductor layer 21 in another memory cell (dielectric structure 63 shown in Figure 14). The dielectric structure 63 is used to isolate two adjacent rows of memory cells along the Y direction. Referring to Figure 14, the second lateral groove 64 and the second initial hole 61 constitute the second hole 6. It should be noted that the trench formed after lateral etching of the dielectric material and the first gate dielectric layer 41 through the second initial hole 61 is a whole, wherein the second initial hole 61 and the second lateral groove 64 are different parts of the trench.

[0148] Specifically, the size of the second hole 6 in the first semiconductor layer 21 is larger than the size of the second hole 6 in the sacrificial layer 22, or in other words, the size of the second hole 6 in the first semiconductor layer 21 is larger than the size of the second hole 6 in the insulating layer 25. It can be understood that, on the XOY plane, the orthographic projection of the second hole 6 located in the sacrificial layer 22 (or the insulating layer 25) falls within the orthographic projection of the second hole 6 located in the first semiconductor layer 21, as shown in Figures (b) and (c) of Figure 14, where the cross-section of the second hole 6 is serrated.

[0149] In some embodiments, a second hole structure is formed through a second hole, the second hole structure further including a write line through the stacked structure, the first transistor and the second transistor being an integral structure, and the integral structure surrounding the write line.

[0150] Figure 15(a) is a top perspective view of the structure obtained after forming the second hole structure in an embodiment of this disclosure, located in the first semiconductor layer; (b) is a cross-sectional schematic diagram of the structure shown in (a) along line AA'; (c) is a cross-sectional schematic diagram of the structure shown in (a) along line BB'; and (d) is a cross-sectional schematic diagram of the structure shown in (a) along line CC'. Referring to Figure 15, forming the second hole structure further includes: forming a second hole structure 7 through the second hole 6, wherein the second hole structure 7 includes a second substructure 70 formed in the first semiconductor layer 21.

[0151] In some embodiments, forming a second hole structure through a second hole includes: forming a first transistor and a second transistor in a second lateral groove; and depositing conductive material through a second initial hole to form a writing line that fills the second hole.

[0152] Referring to Figure 15, the second hole structure 7 is formed through the second hole 6, including the following steps:

[0153] A first transistor T1 and a second transistor T2 are formed in the second transverse groove 64;

[0154] This forms a Write Word Line (WWL) that fills the second hole 6.

[0155] For example, the fabrication process of the second hole structure 7 includes: forming a second semiconductor layer 71 and a second gate dielectric layer 72 covering the bottom and sidewalls of the second lateral groove 64 by a deposition process; and then depositing conductive material into the second hole 6 by a deposition process to form a write line WWL. The second gate dielectric layer 72 can be a thin film covering the inner wall of the second hole 6. The second semiconductor layer 71 is connected to the first conductive layer 42 in the Y direction, and its first side is connected to the first bit line 54 in the X direction. Its second side is connected to the second bit line 55. The bit line structure 5 connects the memory cells arranged along the Y direction to form a row of memory cells. The material of the second semiconductor layer 71 can be a semiconductor material, and the material of the second gate dielectric layer 72 can be a dielectric material. It should be noted that the bottom of the second lateral groove refers to the bottom of the second lateral groove in the Y direction that exposes the first conductive layer and dielectric structure, and in the X direction that exposes the bit line structure. The sidewalls of the second lateral groove refer to the two opposite sides of the second lateral groove in the Z direction.

[0156] In this configuration, the write line WWL located in the first semiconductor layer 21 serves as the common gate of the first transistor T1 and the second transistor T2. The portion of the first conductive layer 42 that contacts the second substructure 70 serves as the common electrode (common source or common drain) of the first transistor T1 and the second transistor T2. The portion of the first bit line 54 that contacts the second substructure 70 serves as one electrode (drain or source) of the first transistor T1. The portion of the second bit line 55 that contacts the second substructure 70 serves as one electrode (drain or source) of the second transistor T2. The portion of the second semiconductor layer 71 connected to the first bit line 54 and the first conductive layer 42 serves as the channel of the first transistor T1, and the portion of the second semiconductor layer 71 connected to the second bit line 55 and the first conductive layer 42 serves as the channel of the second transistor T2. It is understood that the first transistor T1 and the second transistor T2 are a single integrated structure, comprising the portion of the write line WWL located in the sacrificial layer 22 (or in the insulating layer 25) and in contact with the second gate dielectric layer 72, the second gate dielectric layer 72, and the second semiconductor layer 71.

[0157] It is understandable that the first transistor T1 and the second transistor T2 are disposed in the first semiconductor layer 21, and the write line WWL runs through the stacked structure 2, thereby connecting the integral structure stacked vertically along the Z direction in series.

[0158] As shown in Figure 15, the number of memory cells in a column of memory cells in this semiconductor device is the same as the number of first semiconductor layers 21 in the stacked structure 2. It should be noted that the number of memory cell columns shown in Figure 15 is only an example, and this disclosure does not limit the number of memory cell columns.

[0159] As shown in Figure 15, the outer peripheral shape of the first semiconductor layer 21 is different from the inner peripheral shape of the first semiconductor layer 21. Since the channel (first semiconductor layer 21) of the read transistor Tr is not a thin film formed in the first lateral groove 33, but is formed by multiple etchings of the first semiconductor layer 21 in the stacked structure 2, the outer peripheral wall (first side and second side) of the first semiconductor layer 21 in each memory cell in the X direction matches the bit line structure 5, the outer peripheral wall of the first semiconductor layer 21 in the Y direction matches the dielectric structure 63 and the second substructure 70 (specifically, the outer peripheral wall of the second semiconductor layer 71), and the inner peripheral wall of the first semiconductor layer 21 matches the first substructure 40. Therefore, the outer peripheral shape of the first semiconductor layer 21 is different from the inner peripheral shape of the first semiconductor layer 21. It should be noted that the outer peripheral of the first semiconductor layer 21 refers to the projection of the outer peripheral wall of the first semiconductor layer 21 away from the first substructure 40 onto the XOY plane, and the inner peripheral of the first semiconductor layer 21 refers to the projection of the inner peripheral wall of the first semiconductor layer 21 in contact with the first substructure 40 onto the XOY plane.

[0160] Specifically, because a portion of the first semiconductor layer 21 is removed, the projection of the first semiconductor layer 21 (the channel of the read transistor Tr) onto the XOY plane is an irregular ring with a notch. Specifically, the outer periphery of the first semiconductor layer 21 is a rectangle with a notch, and the inner periphery of the first semiconductor layer 21 is a circle with a notch. It can be understood that the read transistor Tr partially surrounds the capacitor C. Furthermore, the inner peripheral wall of the first semiconductor layer 21 matches the first substructure 40 (specifically, the outer peripheral wall of the first gate dielectric layer 41). Therefore, when the projection of the outer peripheral wall of the first gate dielectric layer 41 onto the XOY plane is a circle with a notch, the inner periphery of the first semiconductor layer 21 is also a circle with a notch. In this case, the shape of the outer periphery of the first semiconductor layer 21 can be different from the shape of its inner periphery. Conversely, when the projection of the outer peripheral wall of the first gate dielectric layer 41 onto the XOY plane is a rectangle with a notch, the inner periphery of the first semiconductor layer 21 is also a rectangle with a notch. In this case, the shape of the outer periphery of the first semiconductor layer 21 can be the same as the shape of its inner periphery. This disclosure does not impose any restrictions on the outer and inner peripheral shapes of the first semiconductor layer 21.

[0161] The outer periphery of the second semiconductor layer 71 has the same shape as its inner periphery. Since the second semiconductor layer 71 is a thin film formed in the second lateral groove 64, its outer periphery has the same shape as its inner periphery, and the outer periphery dimension is larger than the inner periphery dimension. The inner peripheral wall of the second semiconductor layer 71 fits into the bottom of the second lateral groove 64. Therefore, when the projection of the bottom of the second lateral groove 64 onto the XOY plane is circular, the outer and inner peripheries of the second semiconductor layer 71 are circular; when the projection of the bottom of the second lateral groove 64 onto the XOY plane is rectangular, the outer and inner peripheries of the second semiconductor layer 71 are rectangular. Furthermore, the shape of the outer periphery of the second semiconductor layer 71 is also related to the degree of etching of the first semiconductor layer 21 when forming the second lateral groove 64. If the first semiconductor layer 21 is etched to expose the first substructure 40 when forming the second lateral groove 64, then the outer periphery of the second semiconductor layer 71 has an arc-shaped depression on the side near the first conductive layer 42. If the first semiconductor layer 21 is etched to just expose the first substructure 40 when forming the second lateral groove 64, then the outer periphery of the first conductive layer 42 is tangent to the outer periphery of the second semiconductor layer 71, and the outer periphery of the second semiconductor layer 71 can be a straight line on the side near the first conductive layer 42. It should be noted that the outer periphery of the second semiconductor layer 71 refers to the projection of the outer peripheral wall of the second semiconductor layer 71 away from the second gate dielectric layer 72 on the XOY plane, the inner periphery of the second semiconductor layer 71 refers to the projection of the inner peripheral wall of the second semiconductor layer 71 in contact with the second gate dielectric layer 72 on the XOY plane, and the outer periphery of the first conductive layer 42 refers to the projection of the outer peripheral wall of the first conductive layer 42 away from the first dielectric layer 43 on the XOY plane.

[0162] In some embodiments, the channel material of the read transistor includes a single-crystal semiconductor.

[0163] In some embodiments, the channel material (first semiconductor layer 21) of the read transistor Tr includes a single-crystal semiconductor, such as single-crystal silicon. Single-crystal semiconductors have higher mobility than other semiconductor materials. Using a single-crystal semiconductor to form the channel of the read transistor Tr can effectively reduce the ΔVth of the read transistor Tr. A lower ΔVth in the read transistor Tr is beneficial for achieving multi-bit storage in the memory cell and can ensure the reliability of data reading. Specifically, only when the ΔVth of the read transistor Tr is less than ΔVbit can it be ensured that the distinction between different memory states is not reduced by programming or erasing operations. Furthermore, the larger the difference between ΔVth and ΔVbit, the higher the reliability of data reading. Here, ΔVth refers to the threshold voltage change introduced by programming or erasing operations on the read transistor Tr, and ΔVbit refers to the threshold voltage difference between each memory state.

[0164] In some embodiments, the channel material of the first transistor and the channel material of the second transistor include a metal oxide semiconductor, wherein the metal oxide semiconductor includes at least one element selected from indium, gallium, zinc, tin and tungsten.

[0165] The channel materials of the first transistor and the second transistor include metal-oxide-semiconductor (MODS). For example, MODS include at least one of indium, gallium, zinc, tin, and tungsten; compounds containing other elements, such as nitrogen (N) and silicon (Si), are also possible; small amounts of other doping elements are also possible. Furthermore, compared to other semiconductor materials, using MODS to form the channels of the first and second transistors (second semiconductor layer 71) allows for better control of semiconductor device manufacturing costs.

[0166] In some embodiments, the metal oxide semiconductor material can be indium gallium zinc oxide (IGZO). When the metal oxide material is IGZO, the leakage current of the transistor is small (less than or equal to 10-15A), thereby ensuring a low refresh rate of the memory cell.It should be noted that the metal oxide material can also be ITO or InSnOx (Indium Tin Oxide), IWO or InWO (Indium Tungsten Oxide), ZnOx (Zinc Oxide), InOx (Indium Oxide), In2O3 (Indium Oxide), SnO2 (Tin Dioxide), TiOx (Tin Dioxide), ZnxOyNz (Zinc Nitride Oxide), MgxZnyOz (Magnesium Zinc Oxide), InxZnyOz (Indium Zinc Oxide), InxGayZnzOa (Indium Gallium Zinc Oxide), ZrxInyZnzOa (Zirconium Indium Zinc Oxide), HfxInyZnzOa (Hafnium Indium Zinc Oxide). Indium Zinc Oxide, SnxInyZnzOa (Tin Indium Zinc Oxide), AlxSnyInzZnaOd (Aluminum Tin Indium Zinc Oxide), SixInyZnzOa (Silicon Indium Zinc Oxide), ZnxSnyOz (Zinc Tin Oxide), AlxZnySnzOa (Aluminum Indium Tin Oxide), GaxZnySnzOa (Gallium Indium Tin Oxide), ZrxZnySnzOa (Zirconium Indium Tin Oxide), InGaSiO (Indium Gallium Silicon Oxide), IAZO (Indium Aluminum Zinc Oxide), IGO (Indium Gallium Oxide). Materials such as indium gallium oxide (IGAO), indium zinc oxide (IZO), and indium zinc oxide (IZOx) are acceptable, as long as the leakage current of the transistor meets the requirements. The specific requirements can be adjusted according to the actual situation.

[0167] This disclosure also provides a semiconductor device, which will be described below with reference to FIG15.

[0168] This disclosure provides a semiconductor device, including: a substrate and a stacked structure disposed on the substrate, the stacked structure including alternating first semiconductor layers and insulating layers; a plurality of first hole structures and second hole structures penetrating the stacked structure and disposed along a first direction parallel to the substrate; a memory cell, the memory cell including a first substructure disposed in the first hole structure and a second substructure disposed in the second hole structure; the first substructure including a first gate structure of a read transistor and a capacitor, the first substructure being located in the first semiconductor layer; the second substructure including a first transistor and a second transistor, the second substructure being located in the first semiconductor layer.

[0169] This disclosure provides a semiconductor device with 3T1C memory cells, specifically including two write transistors (a first transistor and a second transistor, respectively), one read transistor, and a capacitor. A first gate structure and a first semiconductor layer constitute the read transistor. The two write transistors not only provide redundancy but also enable higher data transfer rates. Furthermore, during the write phase, the parallel connection of the first and second transistors can shunt the write current, thereby reducing the performance requirements on the write transistors. Additionally, the memory cells in this semiconductor device can be stacked not only perpendicular to the substrate but also arranged in an array in a plane parallel to the substrate, which is beneficial for increasing the integration density of the memory cells.

[0170] Referring to Figure 15, the semiconductor device includes a substrate 1 and a stacked structure. The stacked structure includes alternating first semiconductor layers 21 and insulating layers 25. The top surface of the stacked structure away from the substrate 1 may include a protective layer 23 for physically protecting the semiconductor device. Exemplarily, the protective layer 23 may include at least one insulating film layer.

[0171] In some embodiments, to avoid electrical connection between multiple rows of memory cells through the substrate 1, at least one isolation layer 26 may be included between the substrate 1 and the stacked structure 2. The material of the isolation layer 26 is an insulating material. For example, the isolation layer 26 between the substrate 1 and the stacked structure may be an insulating layer.

[0172] The first hole structure 4 and the second hole structure 7 both penetrate the stacked structure 2, and the first substructure 40 and the second substructure 70 are disposed in the first semiconductor layer 21.

[0173] In some embodiments, a first substructure and at least a first semiconductor layer surrounding a portion of the first substructure constitute a first structure, the first structure including a read transistor and a capacitor.

[0174] In some embodiments, the first hole structure includes a read line that penetrates the stacked structure, and the first substructure includes a capacitor surrounding the read line and a first gate structure that partially surrounds the capacitor.

[0175] In some embodiments, the first hole structure 4 includes a read word line RWL that penetrates the stacked structure, and the first substructure 40 includes a capacitor C surrounding the read word line RWL and a first gate structure that partially surrounds the capacitor C. The read word line RWL can connect the first substructures 40 stacked vertically along the Z direction in series to form the first hole structure 4.

[0176] In some embodiments, the first substructure includes a first dielectric layer and a first conductive layer surrounding a read word line, and a first gate dielectric layer partially surrounding the first conductive layer; wherein the first conductive layer and the first gate dielectric layer constitute a first gate structure, and the first gate structure and the first semiconductor layer constitute a read transistor.

[0177] In some embodiments, on the XOY plane, along a direction away from the read word line RWL, the first substructure 40 includes a first dielectric layer 43 and a first conductive layer 42 surrounding the read word line RWL, and a first gate dielectric layer 41 partially surrounding the first conductive layer 42. The portion of the first conductive layer 42 in contact with the first gate dielectric layer 41, along with the first gate dielectric layer 41, constitutes a first gate structure. A first semiconductor layer 21 partially surrounds the first gate structure (specifically, the first gate dielectric layer 41), and the first gate structure and the first semiconductor layer 21 partially surrounding the first gate structure constitute a read transistor Tr. The first dielectric layer 43 may be a film layer covering the sidewalls and bottom of the read word line RWL. The first gate dielectric layer 41 may also cover the sidewalls of the first dielectric layer 43 located in the insulating layer 25. It is understood that the first dielectric layer 43 and the first gate dielectric layer 41 can extend from the top to the bottom of the stacked structure.

[0178] The first conductive layer 42, the first dielectric layer 43, and a portion of the read word line RWL (the portion of the read word line RWL corresponding to the first conductive layer 42) located in the same first semiconductor layer 21 can form a capacitor C surrounding the read word line RWL. The portion of the first semiconductor layer 21 that contacts the first gate dielectric layer 41 serves as the channel of the read transistor Tr, and the portion of the first conductive layer 42 that contacts the first gate dielectric layer 41 serves as the gate of the read transistor Tr.

[0179] In some embodiments, the size of the read line in the first semiconductor layer is larger than the size of the read line in the insulating layer.

[0180] In some embodiments, the size of the read word line RWL in the first semiconductor layer 21 is larger than the size of the read word line RWL in the insulating layer 25. It is understood that the cross-section of the read word line RWL in the plane perpendicular to the substrate 1 is serrated. The first conductive layer 42 and the first gate dielectric layer 41 can be formed as films that sequentially cover the sidewalls of the portion of the read word line RWL located in the first semiconductor layer 21 to increase the size of the capacitor plates. This can increase the capacitance of the capacitor and effectively improve the data storage capacity, data retention time and stability of the storage cell.

[0181] In some embodiments, the second hole structure includes a writing line that penetrates the stacked structure, the first transistor and the second transistor are integral structures, and the integral structure surrounds the writing line.

[0182] In some embodiments, the second hole structure 7 includes a write line WWL that penetrates the stacked structure, and an integral structure surrounds the write line WWL. It is understood that, within the same first semiconductor layer 21, a first transistor T1 surrounds a portion of the sidewall of the write line WWL, and a second transistor T2 surrounds a portion of the sidewall of the write line WWL. The write line WWL can be connected in series with integral structures stacked perpendicularly along the Z direction to form the second hole structure 7.

[0183] In some embodiments, the integral structure includes a second gate dielectric layer and a second semiconductor layer surrounding the writing lines.

[0184] In some embodiments, on the XOY plane, the second substructure 70 along the direction away from the write line WWL includes a second gate dielectric layer 72 and a second semiconductor layer 71 surrounding the write line WWL. The second gate dielectric layer 72 may be a film layer covering the sidewalls and bottom of the write line WWL. It is understood that the first transistor T1 and the second transistor T2 are an integral structure, which includes the portion of the write line WWL located in the first semiconductor layer 21 and in contact with the second gate dielectric layer 72, the second gate dielectric layer 72, and the second semiconductor layer 71.

[0185] In this configuration, the portion of the write line WWL located in the first semiconductor layer 21 serves as the common gate of the first transistor T1 and the second transistor T2, a portion of the second semiconductor layer 71 serves as the channel of the first transistor T1, and a portion of the second semiconductor layer 71 serves as the channel of the second transistor T2.

[0186] In some embodiments, the second semiconductor layer is in contact with the first conductive layer.

[0187] In some embodiments, the portion of the first conductive layer 42 not covered by the first gate dielectric layer 41 and the first semiconductor layer 21 contacts the second semiconductor layer 71, and the portion of the first conductive layer 42 that contacts the second semiconductor layer 71 can serve as the common electrode (common source or common drain) of the first transistor T1 and the second transistor T2.

[0188] In some embodiments, a bit line structure extending along a first direction is further included, and a plurality of memory cells arranged along the first direction are connected to the same bit line structure; the bit line structure includes a first bit line disposed on a first side of the memory cell and a second bit line disposed on a second side of the memory cell, the first side and the second side being opposite sides of the memory cell in a second direction; the second direction intersects the first direction and is parallel to the substrate.

[0189] In some embodiments, the semiconductor device further includes a bit line structure 5 extending along the Y direction, with a row of memory cells connected to the same bit line structure 5. The bit line structure 5 includes a first bit line 54 disposed on a first side of a row of memory cells and a second bit line 55 disposed on a second side of the same row of memory cells, that is, the bit line structure 5 can connect memory cells located in the same first semiconductor layer 21 and arranged along the Y direction to form a row of memory cells.

[0190] In some embodiments, the first bit line is connected to the first semiconductor layer and the second semiconductor layer in the memory cell, and the second bit line is connected to the first semiconductor layer and the second semiconductor layer in the memory cell.

[0191] In some embodiments, along the X direction, the first bit line 54 can be connected to the first semiconductor layer 21 and the second semiconductor layer 71 in a row of memory cells, and the second bit line 55 can be connected to the first semiconductor layer 21 and the second semiconductor layer 71 in the same row of memory cells.

[0192] The portion of the first bit line 54 that contacts the first semiconductor layer 21 in the stored cell serves as one pole (source or drain) of the read transistor Tr, and the portion of the second bit line 55 that contacts the first semiconductor layer 21 in the same stored cell serves as the other pole (drain or source) of the read transistor Tr.

[0193] The portion of the first bit line 54 that contacts the second semiconductor layer 71 in the memory cell serves as one electrode (drain or source) of the first transistor T1, and the portion of the second bit line 55 that contacts the second semiconductor layer 71 in the same memory cell serves as one electrode (drain or source) of the second transistor T2. The portion of the second semiconductor layer 71 connected to the first bit line 54 and the first conductive layer 42 serves as the channel of the first transistor T1, and the portion of the second semiconductor layer 71 connected to the second bit line 55 and the first conductive layer 42 serves as the channel of the second transistor T2.

[0194] In some embodiments, a media structure is included between two adjacent storage cells along a first direction.

[0195] In some embodiments, along the Y direction, at least a medium structure 63 is included between two adjacent memory cells, the medium structure 63 being used to isolate two adjacent memory cells in the Y direction.

[0196] In some embodiments, the semiconductor device may further include an isolation structure 56 that extends through the stacked structure, the isolation structure 56 extending along the Y direction and disposed between two adjacent rows of memory cell columns to isolate two adjacent rows of memory cell columns along the X direction (that is, to isolate two adjacent bit line structures 5).

[0197] In some embodiments, the material of the first semiconductor layer includes a single-crystal semiconductor.

[0198] In some embodiments, the material of the first semiconductor layer 21 includes a single-crystal semiconductor, such as single-crystal silicon. Single-crystal semiconductors have higher mobility than other semiconductor materials. Using a single-crystal semiconductor to form the channel of the read transistor Tr can effectively reduce the ΔVth of the read transistor Tr. A lower ΔVth in the read transistor Tr is beneficial for the memory cell to achieve multi-bit storage and can ensure the reliability of data reading. Specifically, only when the ΔVth of the read transistor Tr is less than ΔVbit can it be ensured that the distinction between different storage states is not reduced by programming or erasing operations. Furthermore, the larger the difference between ΔVth and ΔVbit, the higher the reliability of data reading.

[0199] In some embodiments, the outer peripheral shape of the first semiconductor layer is different from the inner peripheral shape of the first semiconductor layer.

[0200] As shown in Figure 15, the projection of the first semiconductor layer 21 onto the XOY plane is an irregular ring with a notch. The outer periphery of the first semiconductor layer 21 is a rectangle with a notch, and the inner periphery of the first semiconductor layer 21 is a circle with a notch. Specifically, in each memory cell, the outer peripheral wall (first side and second side) of the first semiconductor layer 21 in the X direction matches the bit line structure 5, the outer peripheral wall of the first semiconductor layer 21 in the Y direction matches the dielectric structure 63 and the second substructure 70 (specifically, the outer peripheral wall of the second semiconductor layer 71), and the inner peripheral wall of the first semiconductor layer 21 matches the first substructure 40 (specifically, the outer peripheral wall of the first gate dielectric layer 41), so that the shape of the outer periphery of the first semiconductor layer 21 is different from the shape of the inner periphery of the first semiconductor layer 21.

[0201] The outer periphery shape of the second semiconductor layer 71 is the same as the inner periphery shape of the second semiconductor layer 71, and the outer periphery size of the second semiconductor layer 71 is larger than the inner periphery size of the second semiconductor layer 71.

[0202] In some embodiments, the material of the second semiconductor layer includes a metal oxide semiconductor, wherein the metal oxide semiconductor includes at least one element selected from indium, gallium, zinc, tin, and tungsten.

[0203] In some embodiments, the material of the second semiconductor layer 71 includes a metal oxide semiconductor. For example, the metal oxide semiconductor includes at least one of indium, gallium, zinc, tin, and tungsten; compounds containing other elements, such as nitrogen (N) and silicon (Si), are also excluded; the presence of other small amounts of doping elements is also not excluded. The metal oxide semiconductor material can be indium gallium zinc oxide (IGZO). When the metal oxide material is IGZO, the leakage current of the transistor is relatively small (leakage current less than or equal to 10⁻¹⁵ A), thereby ensuring a low refresh rate for the memory cell. Furthermore, compared to other semiconductor materials, using a metal oxide semiconductor as the channel (second semiconductor layer) for both the first and second transistors allows for better control of the manufacturing cost of the memory cell.

[0204] Here, the specific structure and other details of the semiconductor device are similar to those of the semiconductor device obtained by the aforementioned preparation method. For any parts not mentioned, please refer to the above preparation method embodiments, which will not be repeated here.

[0205] This disclosure provides a memory cell, including: an address line structure comprising a first address line and a second address line; a read transistor comprising a first electrode connected to the first address line, a second electrode connected to the second address line, and a first gate connected to a memory node, wherein the channel material of the read transistor comprises a single-crystal semiconductor; a write transistor comprising a first transistor and a second transistor connected in parallel; wherein the first transistor comprises a third electrode connected to the address line structure, a fourth electrode connected to the memory node, and a second gate connected to a write word line; the second transistor comprises a fifth electrode connected to the address line structure, a sixth electrode connected to the memory node, and a third gate connected to the write word line; the second gate and the third gate serve as connection terminals of the write word line to connect multiple write transistors in series; and a capacitor coupled to the memory node.

[0206] Figure 16(a) is a logic circuit diagram of a memory cell provided in an embodiment of this disclosure, and Figure 16(b) is a structural schematic diagram of the memory cell shown in Figure (a). Referring to Figure 16, the read transistor Tr1 includes a first electrode P11 connected to the first address line A1, a second electrode P21 connected to the second address line A2, and a first gate G11 connected to the storage node SN; the write transistor includes a first transistor T11 and a second transistor T21. The first transistor T11 includes a third electrode P31 connected to the address line structure, a fourth electrode P41 connected to the storage node SN, and a second gate G21 connected to the write word line WWL; the second transistor T21 includes a fifth electrode P51 connected to the address line structure, a sixth electrode P61 connected to the storage node SN, and a third gate G31 connected to the write word line WWL, as well as a capacitor coupled to the storage node SN. The capacitor may be a parasitic capacitance of the read transistor Tr1.

[0207] In some embodiments, the channel material of the read transistor Tr includes a single-crystal semiconductor, such as single-crystal silicon. Single-crystal semiconductors have higher mobility than other semiconductor materials. Using a single-crystal semiconductor to form the channel of the read transistor Tr can effectively reduce the ΔVth of the read transistor Tr. A lower ΔVth in the read transistor Tr is beneficial for achieving multi-bit storage in the memory cell and can ensure the reliability of data retrieval. Specifically, only when the ΔVth of the read transistor Tr is less than ΔVbit can it be ensured that the distinction between different memory states is not reduced by programming or erasing operations. Furthermore, the larger the difference between ΔVth and ΔVbit, the higher the reliability of data retrieval.

[0208] In some embodiments, the third electrode and the fifth electrode are connected to the first address line.

[0209] Referring to Figure 16, the third electrode P31 and the fifth electrode P51 are connected to the first address line A1.

[0210] The memory cell includes a first structure and a second substructure arranged along the Y direction. The first structure includes a read transistor Tr1 and a capacitor, and the second substructure includes a write transistor. The first structure includes an insulating structure 161 extending along the Z direction, a first conductive layer 162 surrounding the insulating structure 161, a first gate dielectric layer 163 partially surrounding the first conductive layer 162, and a first semiconductor layer 164. The second substructure includes a write word line WWL extending along the Z direction, a second gate dielectric layer 165 surrounding the write word line WWL, and a second semiconductor layer 166. The portion of the first conductive layer 162 not covered by the first gate dielectric layer 163 and the first semiconductor layer 164 is connected to the second semiconductor layer 166. The insulating structure 161, the first gate dielectric layer 163, and the second gate dielectric layer 165 are made of dielectric material; the first conductive layer 162, the first address line A1, the second address line A2, and the write word line WWL are made of conductive material; and the first semiconductor layer 164 and the second semiconductor layer 166 are made of semiconductor material.

[0211] The memory cell also includes an address line structure, which includes a first address line A1 extending along the Y direction and a second address line A2 extending along the Z direction. The first address line A1 and the second address line A2 are respectively disposed on both sides of the memory cell along the X direction. Specifically, the first address line A1 is connected to the first semiconductor layer 164 and the second semiconductor layer 166, and the second address line A2 is connected to the first semiconductor layer 164.

[0212] In this configuration, the first conductive layer 162 serves as the storage node SN, the portion of the first address line A1 that contacts the first semiconductor layer 164 serves as the first electrode P11, the portion of the second address line A2 that contacts the first semiconductor layer 164 serves as the second electrode P21, the portion of the first semiconductor layer 164 that contacts the first gate dielectric layer 163 serves as the channel of the read transistor Tr1, and the portion of the first conductive layer 162 that contacts the first gate dielectric layer 163 serves as the first gate G11.

[0213] The portion of the first address line A1 that contacts the second semiconductor layer 166 serves as the third electrode P31 and the fifth electrode P51; the portion of the first conductive layer 162 that contacts the second semiconductor layer 166 serves as the fourth electrode P41 and the sixth electrode P61; the portion of the write line WWL that corresponds to the second semiconductor layer 166 serves as the second gate G21 and the third gate G31; the portion of the second semiconductor layer 166 that contacts the first conductive layer 162 and the first address line A1 serves as the two locations where the channels of the first transistor T11 and the second transistor T21 are connected. It can be understood that the channels of the first transistor T11 and the second transistor T21 are connected end to end to form a loop, and the projection of the channels of the first transistor T11 and the second transistor T21 onto the XOY plane is an irregular ring.

[0214] The first conductive layer, the first gate dielectric layer, and the first semiconductor layer constitute a capacitor coupled to the storage node SN.

[0215] The second address line A2 connects the read transistor Tr1 into a column along the Z direction, and the write word line WWL connects the write transistor into a column along the Z direction. That is, the second address line A2 and the write word line WWL connect the memory cells along the Z direction to form a column of memory cells. The first address line A1 connects the memory cells arranged along the Y direction into a row of memory cells. In addition, adjacent memory cells in the memory cells arranged along the X direction are isolated from each other.

[0216] The memory cell provided in this embodiment includes two write transistors (a first transistor and a second transistor, respectively), one read transistor, and a capacitor. The two write transistors not only provide redundancy but also enable higher data transfer rates. Furthermore, during the write phase, the parallel connection of the first and second transistors can shunt the write current, thereby reducing the performance requirements on the write transistors. In addition, the memory cell can be stacked not only along the Z-axis but also arranged in an array in the XOY plane, which is beneficial for improving the integration density of the memory cell.

[0217] In some embodiments, the size of the insulating structure located in the first structure is larger than the size of the insulating structure located between two adjacent first structures disposed along a direction perpendicular to the substrate. It is understood that the cross-section of the insulating structure in the plane perpendicular to the substrate is serrated. The first conductive layer and the first gate dielectric layer can be formed as film layers that sequentially cover the sidewalls of the portion of the insulating structure located in the first structure to increase the size of the capacitor plates. This can increase the capacitance of the capacitor and effectively improve the data storage capacity, data retention time and stability of the storage cell.

[0218] Here, the specific structure and other details of the first conductive layer, the first gate dielectric layer, the first semiconductor layer and the second substructure in the memory cell in Figure 16 are similar to those in the aforementioned semiconductor device and its fabrication method. For parts not mentioned, please refer to the above-mentioned embodiments of the semiconductor device and its fabrication method, which will not be repeated here.

[0219] In some embodiments, the capacitor includes a first plate connected to the storage node and a second plate grounded; a third electrode and a fifth electrode are connected to a first address line.

[0220] Figure 17(a) is a logic circuit diagram of a memory cell provided in an embodiment of this disclosure, and Figure (b) is a structural schematic diagram of the memory cell shown in Figure (a). Referring to Figure 17, the read transistor Tr2 includes a first electrode P12 connected to the first address line A1, a second electrode P22 connected to the second address line A2, and a first gate G12 connected to the memory node SN; the write transistor includes a first transistor T12 and a second transistor T22. The first transistor T12 includes a third electrode P32 connected to the first address line A1, a fourth electrode P42 connected to the memory node SN, and a second gate G22 connected to the write word line WWL; the second transistor T22 includes a fifth electrode P52 connected to the first address line A1, a sixth electrode P62 connected to the memory node SN, and a third gate G32 connected to the write word line WWL; the capacitor C2 includes a first plate E12 connected to the memory node SN and a grounded second plate E22.

[0221] Referring to Figure 17, the memory cell includes a first structure and a second substructure arranged along the Y direction. The first structure includes a read transistor Tr2 and a capacitor C2, and the second substructure includes a write transistor. The first structure includes a conductive structure 170 extending along the Z direction, a first dielectric layer 171 and a first conductive layer 172 sequentially surrounding the conductive structure 170, a first gate dielectric layer 173 partially surrounding the first conductive layer 172, and a first semiconductor layer 174, wherein the conductive structure 170 is grounded. The second substructure includes a write word line WWL extending along the Z direction, a second gate dielectric layer 175 surrounding the write word line WWL, and a second semiconductor layer 176. The portion of the first conductive layer 172 not covered by the first gate dielectric layer 173 and the first semiconductor layer 174 is connected to the second semiconductor layer 176. The materials of the first dielectric layer 171, the first gate dielectric layer 173, and the second gate dielectric layer 175 include dielectric materials; the materials of the conductive structure 170, the first conductive layer 172, the first address line A1, the second address line A2, and the write word line WWL include conductive materials; and the materials of the first semiconductor layer 174 and the second semiconductor layer 176 include semiconductor materials.

[0222] The memory cell also includes an address line structure, which includes a first address line A1 extending along the Y direction and a second address line A2 extending along the Z direction. The first address line A1 and the second address line A2 are respectively disposed on both sides of the memory cell along the X direction. Specifically, the first address line A1 is connected to the first semiconductor layer 174 and the second semiconductor layer 176, and the second address line A2 is connected to the first semiconductor layer 174.

[0223] In this configuration, the first conductive layer 172 serves as the storage node SN, the portion of the first address line A1 that contacts the first semiconductor layer 174 serves as the first electrode P12, the portion of the second address line A2 that contacts the first semiconductor layer 174 serves as the second electrode P22, the portion of the first semiconductor layer 174 that contacts the first gate dielectric layer 173 serves as the channel of the read transistor Tr2, and the portion of the first conductive layer 172 that contacts the first gate dielectric layer 173 serves as the first gate G12.

[0224] The portion of the first address line A1 that contacts the second semiconductor layer 176 serves as the third electrode P32 and the fifth electrode P52; the portion of the first conductive layer 172 that contacts the second semiconductor layer 176 serves as the fourth electrode P42 and the sixth electrode P62; the portion of the write line WWL that corresponds to the second semiconductor layer 176 serves as the second gate G22 and the third gate G32; the portion of the second semiconductor layer 176 that contacts the first conductive layer 172 and the first address line A1 serves as the two locations where the channels of the first transistor T12 and the second transistor T22 are connected. It can be understood that the channels of the first transistor T12 and the second transistor T22 are connected end to end to form a loop, and the projection of the channels of the first transistor T12 and the second transistor T22 on the XOY plane is an irregular ring.

[0225] The portion of the first conductive layer 172 that contacts the first dielectric layer 171 serves as the first electrode plate E12, and the portion of the conductive structure 170 that corresponds to the first conductive layer 172 serves as the second electrode plate E22, thus forming a capacitor C2.

[0226] Conductive structure 170 connects capacitor C2 in a column along the Z direction, second address line A2 connects read transistor Tr2 in a column along the Z direction, and write word line WWL stacks write transistors in a string along the Z direction. That is, conductive structure 170, second address line A2 and write word line WWL connect memory cells in the Z direction to form a column of memory cells, and first address line A1 connects memory cells arranged along the Y direction to form a row of memory cells.

[0227] In some embodiments, the size of the conductive structure located in the first structure is larger than the size of the conductive structure located between two adjacent first structures disposed along a direction perpendicular to the substrate. It is understood that the cross-section of the conductive structure in the plane perpendicular to the substrate is serrated. The first dielectric layer and the first conductive layer can be formed as film layers that sequentially cover the sidewalls of the portion located in the first conductive structure to increase the size of the capacitor plates. This can increase the capacitance of the capacitor and effectively improve the data storage capacity, data retention time and stability of the storage unit.

[0228] Here, the specific structure and other details of the first dielectric layer, first conductive layer, first gate dielectric layer, first semiconductor layer and second substructure in the memory cell of Figure 17 are similar to those in the aforementioned semiconductor device and its fabrication method. For parts not mentioned, please refer to the above-mentioned embodiments of semiconductor device and its fabrication method, which will not be repeated here.

[0229] In some embodiments, the capacitor includes a first plate connected to the storage node and a second plate connected to the read line; the second plate serves as the connection end of the read line to connect multiple capacitors in series.

[0230] Figure 18(a) is a logic circuit diagram of a memory cell provided in an embodiment of this disclosure, and Figure (b) is a structural schematic diagram of the memory cell shown in Figure (a). Referring to Figure 18, the read transistor Tr3 includes a first electrode P13 connected to the first address line A1, a second electrode P23 connected to the second address line A2, and a first gate G13 connected to the memory node SN; the write transistor includes a first transistor T13 and a second transistor T23. The first transistor T13 includes a third electrode P33 connected to the first address line A1, a fourth electrode P43 connected to the memory node SN, and a second gate G23 connected to the write word line WWL; the second transistor T23 includes a fifth electrode P53 connected to the first address line A1, a sixth electrode P63 connected to the memory node SN, and a third gate G33 connected to the write word line WWL; the capacitor C3 includes a first plate E13 connected to the memory node SN and a second plate E23 connected to the read word line RWL.

[0231] Referring to Figure 18, the memory cell includes a first structure and a second substructure arranged along the Y direction. The first structure includes a read transistor Tr3 and a capacitor C3, and the second substructure includes a write transistor. The first structure includes a read word line RWL extending along the Z direction, a first dielectric layer 181 and a first conductive layer 182 sequentially surrounding the read word line RWL, a first gate dielectric layer 183 partially surrounding the first conductive layer 182, and a first semiconductor layer 184. The second substructure includes a write word line WWL extending along the Z direction, a second gate dielectric layer 185 surrounding the write word line WWL, and a second semiconductor layer 186. The portion of the first conductive layer 182 not covered by the first gate dielectric layer 183 and the first semiconductor layer 184 is connected to the second semiconductor layer 186. The materials of the first dielectric layer 181, the first gate dielectric layer 183, and the second gate dielectric layer 185 include dielectric materials; the materials of the first conductive layer 182, the first address line A1, the second address line A2, the read word line RWL, and the write word line WWL include conductive materials; and the materials of the first semiconductor layer 184 and the second semiconductor layer 186 include semiconductor materials.

[0232] The memory cell also includes an address line structure, which includes a first address line A1 extending along the Y direction and a second address line A2 extending along the Y direction. The first address line A1 and the second address line A2 are respectively disposed on both sides of the memory cell along the X direction. Specifically, the first address line A1 is connected to the first semiconductor layer 184 and the second semiconductor layer 186, and the second address line A2 is connected to the first semiconductor layer 184. It can be understood that the second address line A2 is not in contact with the write transistor.

[0233] In this configuration, the first conductive layer 182 serves as the storage node SN, the portion of the first address line A1 that contacts the first semiconductor layer 184 serves as the first electrode P13, the portion of the second address line A2 that contacts the first semiconductor layer 184 serves as the second electrode P23, the portion of the first semiconductor layer 184 that contacts the first gate dielectric layer 183 serves as the channel of the read transistor Tr3, and the portion of the first conductive layer 182 that contacts the first gate dielectric layer 183 serves as the first gate G13.

[0234] The portion of the first address line A1 that contacts the second semiconductor layer 186 serves as the third electrode P33 and the fifth electrode P53; the portion of the first conductive layer 182 that contacts the second semiconductor layer 186 serves as the fourth electrode P43 and the sixth electrode P63; the portion of the write line WWL that corresponds to the second semiconductor layer 186 serves as the second gate G23 and the third gate G33; the portion of the second semiconductor layer 186 that contacts the first conductive layer 182 and the first address line A1 serves as the two locations where the channels of the first transistor T13 and the second transistor T23 are connected. It can be understood that the channels of the first transistor T13 and the second transistor T23 are connected end to end to form a loop, and the projection of the channels of the first transistor T13 and the second transistor T23 onto the XOY plane is an irregular ring.

[0235] The portion of the first conductive layer 182 that contacts the first dielectric layer 181 serves as the first electrode plate E13, and the portion of the read line RWL that corresponds to the first conductive layer 182 serves as the second electrode plate E23, thus forming a capacitor C3.

[0236] The read word line RWL connects capacitor C3 and read transistor Tr3 in a column along the Z direction, and the write word line WWL connects write transistors in a column along the Z direction. That is, the read word line RWL and the write word line WWL connect the memory cells in the Z direction to form a column of memory cells. The first address line A1 and the second address line A2 connect the memory cells arranged in the Y direction to form a row of memory cells.

[0237] In some embodiments, the second address line A2 in the memory cell shown in FIG18 can be connected to a reference voltage.

[0238] In some embodiments, the size of the read line located in the first structure is larger than the size of the read line located between two adjacent first structures disposed along a direction perpendicular to the substrate. It is understood that the cross-section of the read line in the plane perpendicular to the substrate is sawtooth-shaped. The first dielectric layer and the first conductive layer can be formed as film layers that sequentially cover the sidewalls of the portion of the read line located in the first structure to increase the size of the capacitor plates. This can increase the capacitance of the capacitor and effectively improve the data storage capacity, data retention time and stability of the storage cell.

[0239] Here, the specific structure and other details of the first and second substructures in the memory cell in Figure 18 are similar to those in the aforementioned semiconductor devices and their fabrication methods. For parts not mentioned, please refer to the above-mentioned embodiments of semiconductor devices and their fabrication methods, which will not be repeated here.

[0240] In some embodiments, the third electrode is connected to the first address line, and the fifth electrode is connected to the second address line.

[0241] Figure 19(a) is a logic circuit diagram of a memory cell provided in an embodiment of this disclosure, and Figure 19(b) is a structural schematic diagram of the memory cell shown in Figure (a). Referring to Figure 19, the read transistor Tr4 includes a first electrode P14 connected to the first address line A1, a second electrode P24 connected to the second address line A2, and a first gate G14 connected to the memory node SN; the write transistor includes a first transistor T14 and a second transistor T24. The first transistor T14 includes a third electrode P34 connected to the first address line A1, a fourth electrode P44 connected to the memory node SN, and a second gate G24 connected to the write word line WWL; the second transistor T24 includes a fifth electrode P54 connected to the second address line A2, a sixth electrode P64 connected to the memory node SN, and a third gate G34 connected to the write word line WWL; the capacitor C4 includes a first plate E14 connected to the memory node SN and a second plate E24 connected to the read word line RWL.

[0242] Referring to Figure 19, the memory cell includes a first structure and a second substructure arranged along the Y direction. The first structure includes a read transistor Tr4 and a capacitor C4, and the second substructure includes a write transistor. The first structure includes a read word line RWL extending along the Z direction, a first dielectric layer 191 and a first conductive layer 192 sequentially surrounding the read word line RWL, a first gate dielectric layer 193 partially surrounding the first conductive layer 192, and a first semiconductor layer 194. The second substructure includes a write word line WWL extending along the Z direction, a second gate dielectric layer 195 surrounding the write word line WWL, and a second semiconductor layer 196. The portion of the first conductive layer 192 not covered by the first gate dielectric layer 193 and the first semiconductor layer 194 is connected to the second semiconductor layer 196. The materials of the first dielectric layer 191, the first gate dielectric layer 193, and the second gate dielectric layer 195 include dielectric materials; the materials of the first conductive layer 192, the first address line A1, the second address line A2, the read word line RWL, and the write word line WWL include conductive materials; and the materials of the first semiconductor layer 194 and the second semiconductor layer 196 include semiconductor materials.

[0243] The memory cell also includes an address line structure, which includes a first address line A1 extending along the Y direction and a second address line A2 extending along the Y direction. The first address line A1 and the second address line A2 are respectively disposed on both sides of the memory cell along the X direction. Specifically, the first address line A1 is connected to the first semiconductor layer 194 and the second semiconductor layer 196, and the second address line A2 is connected to the first semiconductor layer 194 and the second semiconductor layer 196.

[0244] In this configuration, the first conductive layer 192 serves as the storage node SN, the portion of the first address line A1 that contacts the first semiconductor layer 194 serves as the first electrode P14, the portion of the second address line A2 that contacts the first semiconductor layer 194 serves as the second electrode P24, the portion of the first semiconductor layer 194 that contacts the first gate dielectric layer 193 serves as the channel of the read transistor Tr4, and the portion of the first conductive layer 192 that contacts the first gate dielectric layer 193 serves as the first gate G14.

[0245] The portion of the first address line A1 that contacts the second semiconductor layer 196 serves as the third electrode P34; the portion of the second address line A2 that contacts the second semiconductor layer 196 serves as the fifth electrode P54; the portion of the first conductive layer 192 that contacts the second semiconductor layer 196 serves as the fourth electrode P44 and the sixth electrode P64; the portion of the write line WWL that corresponds to the second semiconductor layer 196 serves as the second gate G24 and the third gate G34; the portion of the second semiconductor layer 196 that contacts the first conductive layer 192 serves as the location where the channel of the first transistor T14 connects to the channel of the second transistor T24; the second semiconductor layer 196 located between the location where the second semiconductor layer 196 contacts the first address line A1 and the location where the second semiconductor layer 196 contacts the first conductive layer 192 serves as the channel of the first transistor T14; the second semiconductor layer 196 located between the location where the second address line A2 contacts the second address line A2 and the location where the second semiconductor layer 196 contacts the first conductive layer 192 serves as the channel of the second transistor T24. In the memory cell shown in Figure 19, the channel length of the first transistor T14 is basically the same as that of the second transistor T24, which allows the first transistor T14 and the second transistor T24 to have similar performance. Here, performance refers to threshold voltage, maximum current carrying capacity, and other properties.

[0246] The portion of the first conductive layer 192 that contacts the first dielectric layer 191 serves as the first electrode plate E14, and the portion of the read line RWL that corresponds to the first conductive layer 192 serves as the second electrode plate E24, thus forming a capacitor C4.

[0247] The read word line RWL connects capacitor C4 and read transistor Tr4 in a column along the Z direction, and the write word line WWL connects write transistors in a column along the Z direction. That is, the read word line RWL and the write word line WWL connect the memory cells in the Z direction to form a column of memory cells. The first address line A1 and the second address line A2 connect the memory cells arranged in the Y direction to form a row of memory cells.

[0248] In some embodiments, the channel material of the write transistor includes a metal oxide semiconductor, wherein the metal oxide semiconductor includes at least one element selected from indium, gallium, zinc, tin, and tungsten.

[0249] In some embodiments, the channel material of the write transistor includes a metal-oxide-semiconductor (MODS). For example, the MODS includes at least one of indium, gallium, zinc, tin, and tungsten; compounds containing other elements, such as nitrogen (N) and silicon (Si), are also possible; the presence of other small amounts of doping elements is also possible. The MODS material can be indium gallium zinc oxide (IGZO). When the MODS material is IGZO, the transistor has a low leakage current (less than or equal to 10⁻¹⁵ A), thereby ensuring a low refresh rate for the memory cell. Furthermore, compared to other semiconductor materials, using a MODS as the channel (second semiconductor layer) of the write transistor allows for better control of the memory cell manufacturing cost.

[0250] Here, the specific structure and other details of the first structure and the second substructure in the memory cell in Figure 19 are similar to those in the aforementioned semiconductor devices and their fabrication methods. For parts not mentioned, please refer to the above-mentioned embodiments of semiconductor devices and their fabrication methods, which will not be repeated here.

[0251] This disclosure provides a memory including a plurality of memory cells arranged in an array. Each memory cell includes a first structure and a second substructure disposed along a first direction parallel to a substrate. The first structure includes a read transistor and a capacitor, and the second substructure includes a first transistor and a second transistor.

[0252] In some embodiments, the memory further includes read word lines extending in a direction perpendicular to the substrate, with first structures surrounding the read word lines. The read word lines connect the first structures in a column along a direction perpendicular to the substrate.

[0253] In some embodiments, the first structure further includes a capacitor surrounding the read word line and a read transistor partially surrounding the capacitor.

[0254] In some embodiments, the first structure includes a first dielectric layer and a first conductive layer sequentially surrounding a read word line, and a first gate dielectric layer and a first semiconductor layer partially surrounding the first conductive layer. A portion of the first conductive layer not covered by the first gate dielectric layer and the first semiconductor layer is connected to a second substructure. The portion of the first semiconductor layer that contacts the first gate dielectric layer serves as the channel of the read transistor, and the portion of the first conductive layer that contacts the first gate dielectric layer serves as the gate of the read transistor. The portion of the first conductive layer that contacts the first dielectric layer serves as the first plate of a capacitor, and the portion of the read word line corresponding to the first conductive layer serves as the second plate of the capacitor, thus forming a capacitor.

[0255] In some embodiments, the size of the read line located in the first structure is larger than the size of the read line located between two adjacent first structures disposed along a direction perpendicular to the substrate. It is understood that the cross-section of the read line in the plane perpendicular to the substrate is sawtooth-shaped. The first dielectric layer and the first conductive layer can be formed as film layers that sequentially cover the sidewalls of the portion of the read line located in the first structure to increase the size of the capacitor plates. This can increase the capacitance of the capacitor and effectively improve the data storage capacity, data retention time and stability of the storage cell.

[0256] In some embodiments, the memory further includes write word lines extending in a direction perpendicular to the substrate. The first transistor and the second transistor are integral structures, and the integral structure surrounds the write word lines. A second substructure is connected to the portion of the capacitor not surrounded by the read transistor; specifically, the second substructure is connected to the portion of the first conductive layer not covered by the first gate dielectric layer and the first semiconductor layer. The write word lines connect the integral structures in a column along a direction perpendicular to the substrate.

[0257] In some embodiments, the integrated structure includes a second gate dielectric layer and a second semiconductor layer sequentially surrounding the write line. It is understood that the integrated structure includes a portion where the write line contacts the second gate dielectric layer, the second gate dielectric layer, and the second semiconductor layer. The second semiconductor layer serves as the channel for the first transistor and the second transistor, and the portion of the write line corresponding to the second semiconductor layer serves as the gate for the first transistor and the second transistor.

[0258] In some embodiments, the channel material of the read transistor includes a single-crystal semiconductor, such as single-crystal silicon. Single-crystal semiconductors have higher mobility than other semiconductor materials. Using a single-crystal semiconductor to form the channel of the read transistor can effectively reduce the ΔVth of the read transistor. A lower ΔVth in the read transistor is beneficial for achieving multi-bit storage in the memory cell and can ensure the reliability of data retrieval. Specifically, only when the ΔVth of the read transistor is less than ΔVbit can it be ensured that the distinction between different memory states is not reduced by programming or erasing operations. Furthermore, the larger the difference between ΔVth and ΔVbit, the higher the reliability of data retrieval.

[0259] In some embodiments, the channel materials of the first transistor and the second transistor comprise metal-oxide-semiconductor (MODS), wherein the MODS comprises at least one element selected from indium, gallium, zinc, tin, and tungsten. For example, the MODS material can be indium gallium zinc oxide (IGZO). When the MODS material is IGZO, the transistor has a low leakage current (less than or equal to 10⁻¹⁵ A), thereby ensuring a low refresh rate for the memory. Furthermore, compared to other semiconductor materials, using MODS as the channel for both the first and second transistors (the second semiconductor layer) allows for better control over the memory cells and the manufacturing cost of the memory.

[0260] In some embodiments, the memory further includes a bit line structure extending along a first direction; the bit line structure includes a first bit line and a second bit line located on both sides of the memory cell along a second direction, the first bit line and the second bit line being coupled to the memory cell, the second direction intersecting the first direction, and the second direction being parallel to the substrate.

[0261] In some embodiments, the first bit line and the second bit line are located on opposite sides of a row of first structures and connected to the first semiconductor layer (the channel of the read transistor). The first bit line and the second bit line disposed on both sides of the row of first structures constitute a bit line structure. The portion of the first bit line that contacts the first structure serves as one electrode (source or drain) of the read transistor, and the portion of the second bit line that contacts the same first structure serves as the other electrode (drain or source) of the read transistor. The bit line structure can connect a row of memory cells in series.

[0262] In some embodiments, the first bit line and the second bit line are connected to the second semiconductor layer.

[0263] In this configuration, the portion of the first conductive layer that contacts the second substructure (second semiconductor layer) serves as the common electrode (common source or common drain) of the first transistor and the second transistor; the portion of the first bit line that contacts the second substructure (second semiconductor layer) serves as one electrode (drain or source) of the first transistor; the portion of the second bit line that contacts the second substructure (second semiconductor layer) serves as one electrode (drain or source) of the second transistor; the portion of the second semiconductor layer connected to the first bit line and the first conductive layer serves as the channel of the first transistor; and the portion of the second semiconductor layer connected to the second bit line and the first conductive layer serves as the channel of the second transistor.

[0264] In some embodiments, a medium structure may be included between two adjacent storage cells in a row of storage cells to isolate adjacent storage cells along a first direction.

[0265] In some embodiments, the memory may further include an isolation structure that extends through the stacked structure, the isolation structure extending along a first direction and disposed between two adjacent rows of memory cells to isolate two adjacent rows of memory cells along a second direction (that is, to isolate two adjacent bit line structures).

[0266] Here, the specific structures and other details of the first and second substructures in the semiconductor structure are similar to those in the aforementioned semiconductor devices and their fabrication methods. For any parts not mentioned, please refer to the above-mentioned embodiments of semiconductor devices and their fabrication methods, which will not be repeated here.

[0267] This disclosure provides a read / write method for reading and writing data to a storage cell in any of the above embodiments. The read / write method includes: during the write phase, applying a first level to the write word line to turn on the first transistor and the second transistor, and inputting a storage signal to the third electrode and the fifth electrode to write the storage signal into the storage node and use it as stored data; during the read phase, applying a second level to the end of the capacitor opposite to the storage node, and reading the stored data by sensing whether the read transistor is turned on.

[0268] In some embodiments, during the write phase, a first level is applied to the second and third gates via the write word line to turn on the first and second transistors, and a storage signal is input to the third and fifth electrodes to write the storage signal into the storage node as stored data. It is understood that the larger of the levels on the third and fifth electrodes is used as the storage signal written into the storage node. After the storage signal is written into the storage node, the first level can be disengaged from the first and second transistors via the write word line, and the storage signal is no longer input to the third and fifth electrodes.

[0269] In some embodiments, during the read phase, a second level is applied to the end of the capacitor opposite to the storage node, and a third level and a fourth level are applied to the first bit line and the second bit line, respectively. The third level and the fourth level are different, and one of them is a reference level. The read transistor is turned on by sensing the current change on the first bit line or the second bit line, thus enabling the reading of stored data.

[0270] The two write transistors (the first transistor and the second transistor) not only provide redundancy but also enable a higher data transfer rate. Furthermore, since the first transistor and the second transistor are connected in parallel, the current can be shunted during data writing, thereby reducing the performance requirements of the write transistors.

[0271] In some embodiments, during the read phase, if the read transistor is turned on, the stored data is first data; if the read transistor is not turned on, the stored data is second data, and the first data and the second data are different.

[0272] In some embodiments, during the read phase, if the read transistor is turned on, the stored data is a first data "0"; if the read transistor is not turned on, the stored data is a second data "1"; or, during the read phase, if the read transistor is turned on, the stored data is a first data "1"; if the read transistor is not turned on, the stored data is a second data "0".

[0273] It should be noted that the descriptions of the semiconductor devices, memory cells, read / write methods, and memories above are similar to the descriptions of the semiconductor device fabrication method embodiments above, and have similar beneficial effects. For technical details not disclosed in the semiconductor device, memory cell, read / write method, and memory embodiments of this disclosure, please refer to the descriptions of the semiconductor device fabrication method embodiments of this disclosure for understanding.

[0274] This disclosure provides a memory cell, a semiconductor device, and a method for fabricating the same. The semiconductor device includes: a substrate and a stacked structure disposed on the substrate, the stacked structure including alternating first semiconductor layers and insulating layers; a plurality of first and second via structures penetrating the stacked structure and disposed along a first direction parallel to the substrate; a memory cell including a first substructure disposed in the first via structure and a second substructure disposed in the second via structure; the first substructure including a first gate structure of a read transistor and a capacitor, the first substructure being located in the first semiconductor layer; the second via structure including a second substructure disposed in the first semiconductor layer, each second substructure including a first transistor and a second transistor, the second substructure being located in the first semiconductor layer. This disclosure provides a semiconductor device with a 3T1C memory cell, specifically including two write transistors (a first transistor and a second transistor, respectively), one read transistor, and a capacitor, the first gate structure and the first semiconductor layer constituting the read transistor. The two write transistors not only provide redundancy but also achieve a higher data transfer rate. Furthermore, during the write phase of the memory cell, the parallel first and second transistors can shunt the write current, thereby reducing the performance requirements of the write transistor. In addition, the memory cells in this semiconductor device can be stacked not only in a direction perpendicular to the substrate, but also arranged in an array in a plane parallel to the substrate, which is beneficial to improving the integration density of the memory cells.

[0275] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0276] The above description is only a preferred embodiment of this disclosure and does not limit the patent scope of this disclosure. All equivalent structural transformations made using the contents of this specification and drawings under the inventive concept of this disclosure, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this disclosure. Industrial applicability

[0277] This disclosure provides a memory cell, a semiconductor device, and a method for fabricating the same. The semiconductor device includes: a substrate and a stacked structure disposed on the substrate, the stacked structure including alternating first semiconductor layers and insulating layers; a plurality of first and second via structures penetrating the stacked structure and disposed along a first direction parallel to the substrate; a memory cell including a first substructure disposed in the first via structure and a second substructure disposed in the second via structure; the first substructure including a first gate structure of a read transistor and a capacitor; the second substructure including a first transistor and a second transistor, the second substructure being located within the first semiconductor layer. This disclosure also provides a semiconductor device with a three-transistor single-capacitor memory cell, specifically including two write transistors (a first transistor and a second transistor, respectively), one read transistor, and a capacitor, with the first gate structure and the first semiconductor layer constituting the read transistor. The two write transistors not only provide redundancy but also enable higher data transfer rates. Furthermore, during the write phase of the memory cell, the parallel first and second transistors can shunt the write current, thereby reducing the performance requirements of the write transistor. In addition, the memory cells in this semiconductor device can be stacked not only in a direction perpendicular to the substrate, but also arranged in an array in a plane parallel to the substrate, which is beneficial to improving the integration density of the memory cells.

Claims

A semiconductor device, comprising: A substrate (1) and a stacked structure disposed on the substrate (1), the stacked structure comprising an alternating first semiconductor layer (21) and an insulating layer (25); A plurality of first hole structures (4) and second hole structures (7) are provided through the stacked structure and along a first direction, the first direction being parallel to the substrate (1); The storage unit includes a first substructure (40) disposed in the first hole structure (4) and a second substructure (70) disposed in the second hole structure (7); The first substructure (40) includes a first gate structure of a read transistor and a capacitor, and the first substructure (40) is located in the first semiconductor layer (21); The second substructure (70) includes a first transistor and a second transistor, and the second substructure (70) is located in the first semiconductor layer (21). The semiconductor device according to claim 1, wherein, The first hole structure (4) includes a read line through the stacked structure, and the first substructure (40) includes a capacitor surrounding the read line and a first gate structure partially surrounding the capacitor. The semiconductor device according to claim 2, wherein, The first substructure (40) includes a first dielectric layer (43) and a first conductive layer (42) surrounding the read word line, and a first gate dielectric layer (41) partially surrounding the first conductive layer (42); wherein the first conductive layer (42) and the first gate dielectric layer (41) constitute the first gate structure, and the first gate structure and the first semiconductor layer (21) constitute the read transistor. The semiconductor device according to claim 3, wherein, The second hole structure (7) includes a writing line that runs through the stacked structure, the first transistor and the second transistor are an integral structure, and the integral structure surrounds the writing line. The semiconductor device according to claim 4, wherein, The integrated structure includes a second gate dielectric layer (72) and a second semiconductor layer (71) surrounding the writing line. The semiconductor device according to claim 5, wherein, The second semiconductor layer (71) is in contact with the first conductive layer (42). The semiconductor device according to claim 5 or 6, wherein, It also includes a bit line structure (5) extending along the first direction, and a plurality of the memory cells arranged along the first direction are connected to the same bit line structure (5); The bit line structure (5) includes a first bit line (54) disposed on the first side of the memory cell and a second bit line (55) disposed on the second side of the memory cell. The first side and the second side are opposite sides of the memory cell in a second direction. The second direction intersects the first direction and is parallel to the substrate (1). The semiconductor device according to claim 7, wherein, The first bit line (54) is connected to the first semiconductor layer (21) and the second semiconductor layer (71) in the memory cell, and the second bit line (55) is connected to the first semiconductor layer (21) and the second semiconductor layer (71) in the memory cell. The semiconductor device according to any one of claims 5 to 8, wherein, The material of the second semiconductor layer (71) includes a metal oxide semiconductor, wherein the metal oxide semiconductor includes at least one element selected from indium, gallium, zinc, tin and tungsten. The semiconductor device according to any one of claims 2 to 9, wherein, The size of the reading line in the first semiconductor layer (21) is larger than the size of the reading line in the insulating layer (25). The semiconductor device according to any one of claims 1 to 10, wherein, The material of the first semiconductor layer (21) includes single-crystal semiconductors. The semiconductor device according to any one of claims 1 to 11, wherein, The outer periphery shape of the first semiconductor layer (21) is different from the inner periphery shape of the first semiconductor layer (21). The semiconductor device according to any one of claims 1 to 12, wherein, Along the first direction, a medium structure (63) is included between two adjacent storage cells. A method for fabricating a semiconductor device, comprising: A substrate is provided, the substrate comprising a substrate (1) and a stacked structure (2) formed on the substrate (1), the stacked structure (2) comprising an alternately disposed first semiconductor layer (21) and a sacrificial layer (22); A plurality of first hole structures (4) and second hole structures (7) are formed through the stacked structure (2) and disposed along a first direction, wherein the first direction is parallel to the substrate (1); The first hole structure (4) includes a first substructure (40) disposed in the first semiconductor layer (21), and each of the first substructures (40) includes a first gate structure of a read transistor and a capacitor; The second hole structure (7) includes a second substructure (70) disposed in the first semiconductor layer (21). Each second substructure (70) includes a first transistor and a second transistor. The first substructure (40) and the second substructure (70) located in the same first semiconductor layer (21) constitute a memory cell. According to the preparation method of claim 14, wherein, Forming the first hole structure (4) includes: A first insulating layer (25a) and a first hole (3) through the stacked structure (2) are formed. The size of the first hole (3) in the first semiconductor layer (21) is larger than the size of the first hole (3) in the sacrificial layer (22). The first insulating layer (25a) is located in the sacrificial layer (22) and surrounds the first hole (3). The first hole structure (4) is formed through the first hole (3), and the first hole structure (4) also includes a reading line that passes through the stacked structure (2), and the capacitor surrounds the reading line. According to the preparation method of claim 15, wherein, The formation of the first insulating layer (25a) and the first hole (3) penetrating the stacked structure (2) includes: A first initial hole (32) is formed through the stacked structure (2), and a portion of the sacrificial layer (22) is replaced with insulating material through the first initial hole (32) to form the first insulating layer (25a); The first semiconductor layer (21) is laterally etched through the first initial hole (32) to form a first lateral groove (33) surrounding the first initial hole (32), the first initial hole (32) and the first lateral groove (33) constituting the first hole (3). According to the preparation method of claim 16, wherein, The process of forming the first hole structure (4) through the first hole (3) includes: A first gate structure and the capacitor are sequentially formed to cover the bottom of the first transverse groove (33); Conductive material is deposited through the first initial hole (32) to form the reading line that fills the first initial hole (32). According to the preparation method of claim 16, wherein, The process of forming the first hole structure (4) through the first hole (3) includes: A first gate structure and the capacitor are sequentially formed to cover the bottom and sidewalls of the first transverse groove (33); Conductive material is deposited through the first initial hole (32) to form the read line that fills the first lateral groove (33) and the first initial hole (32), the size of the read line on the first semiconductor layer (21) being larger than the size of the read line on the sacrificial layer (22). The preparation method according to any one of claims 14 to 18, wherein, Forming the second hole structure (7) includes: A second hole (6) is formed through the stacked structure (2), the size of the second hole (6) in the first semiconductor layer (21) being larger than the size of the second hole (6) in the sacrificial layer (22); The second hole structure (7) is formed through the second hole (6). The second hole structure (7) also includes a writing line that passes through the stacked structure (2). The first transistor and the second transistor are an integral structure, and the integral structure surrounds the writing line. According to the preparation method of claim 19, wherein, The formation of the second hole (6) through the stacked structure (2) includes: A second initial hole (61) is formed through the stacked structure (2), and the projection of the second initial hole (61) on the substrate (1) does not overlap with the projection of the first hole structure (4) on the substrate (1); The first semiconductor layer (21) and the first gate structure are laterally etched through the second initial hole (61) to expose a portion of the capacitor, thereby forming a second lateral groove (64) surrounding the second initial hole (61). The second initial hole (61) and the second lateral groove (64) constitute the second hole (6). According to the preparation method of claim 20, wherein, The process of forming the second hole structure (7) through the second hole (6) includes: The first transistor and the second transistor are formed in the second lateral groove (64); Conductive material is deposited through the second initial hole (61) to form the writing line that fills the second hole (6). The preparation method according to any one of claims 14 to 21, wherein, The channel material of the read transistor includes a single-crystal semiconductor. The preparation method according to any one of claims 14 to 22, wherein, The channel material of the first transistor and the channel material of the second transistor both comprise metal oxide semiconductors, wherein the metal oxide semiconductor comprises at least one element selected from indium, gallium, zinc, tin, and tungsten. The preparation method according to any one of claims 14 to 23, wherein, Before forming the second pore structure (7), the preparation method further includes: A bit line structure (5) extending along the first direction is formed in the first semiconductor layer (21), and a plurality of memory cells arranged along the first direction are connected to the same bit line structure (5). The bit line structure (5) includes a first bit line (54) located on the first side of the memory cell and a second bit line (55) located on the second side of the memory cell. The first side and the second side are opposite sides of the memory cell in a second direction. The second direction intersects the first direction and is parallel to the substrate. According to the preparation method of claim 20, wherein, Before forming the second pore structure (7), the preparation method further includes: A medium structure (63) is formed between two storage cells arranged along the first direction through the second hole (6). A storage unit, comprising: The address line structure includes a first address line and a second address line. The read transistor includes a first electrode connected to the first address line, a second electrode connected to the second address line, and a first gate connected to the memory node. The channel material of the read transistor includes a single-crystal semiconductor. A write transistor includes a first transistor and a second transistor connected in parallel; wherein the first transistor includes a third electrode connected to the address line structure, a fourth electrode connected to the memory node, and a second gate connected to the write word line; the second transistor includes a fifth electrode connected to the address line structure, a sixth electrode connected to the memory node, and a third gate connected to the write word line; the second gate and the third gate serve as connection terminals of the write word line to connect multiple write transistors in series. And capacitors coupled to the storage node. The storage unit according to claim 26, wherein, The capacitor includes a first plate connected to the storage node and a second plate grounded. The third electrode and the fifth electrode are connected to the first address line. The storage unit according to claim 26, wherein, The capacitor includes a first plate connected to the storage node and a second plate connected to the read line; the second plate serves as the connection end of the read line to connect multiple capacitors in series. The storage unit according to claim 28, wherein, The third electrode and the fifth electrode are connected to the first address line. The storage unit according to claim 28, wherein, The third electrode is connected to the first address line, and the fifth electrode is connected to the second address line. The storage unit according to any one of claims 26 to 30, wherein, The channel material of the write transistor includes a metal oxide semiconductor, wherein the metal oxide semiconductor includes at least one element selected from indium, gallium, zinc, tin and tungsten. The storage unit according to any one of claims 26 to 31, wherein, The storage cell includes a first structure and a second substructure disposed along a first direction, the first direction being parallel to the substrate; The first structure includes the read transistor and the capacitor, and the second substructure includes the first transistor and the second transistor. The storage unit according to any one of claims 26 to 32, wherein, During the writing phase, a first level is applied to the write word line to turn on the first transistor and the second transistor, and a storage signal is input to the third electrode and the fifth electrode to write the storage signal into the storage node as stored data; During the read phase, a second voltage level is applied to the end of the capacitor opposite to the storage node, and the stored data is read by sensing whether the read transistor is turned on.

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