Semiconductor device, manufacturing method therefor, and electronic apparatus

Abstract

A semiconductor device, a manufacturing method therefor, and an electronic apparatus. In the semiconductor device, bit lines extend in a first direction perpendicular to a substrate; a word line extends in a second direction parallel to the substrate; each memory structure layer comprises at least one memory structure; each memory structure comprises a plurality of memory cells successively arranged in the second direction; and each memory cell comprises a capacitor and a transistor, the transistor comprising a semiconductor layer. In each memory cell, a first end of the semiconductor layer in a third direction parallel to the substrate is connected to a first electrode of the capacitor, and a second end of the semiconductor layer in the third direction is connected to a bit line, one bit line being connected to second ends of the semiconductor layers of the plurality of memory cells arranged in the first direction. The word line comprises two sub-word lines spaced apart from each other in the first direction, the plurality of semiconductor layers of the plurality of memory cells distributed at intervals in the second direction in each memory structure being sandwiched between the two sub-word lines. The semiconductor device has a high integration density.

Description

Semiconductor device, method of manufacturing the same, and electronic device TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to a semiconductor device, a method of manufacturing the same, and an electronic device. BACKGROUND

[0002] With the development of integrated circuit technology, the critical dimension of devices is increasingly reduced, and the types and quantities of devices contained in a single chip are increased, so that any slight difference in process production can affect the performance of the devices.

[0003] In order to reduce the cost of products as much as possible, people want to make as many device units as possible on a limited substrate. Since the advent of Moore's Law, various semiconductor structure designs and process optimizations have been proposed in the industry to meet people's current product needs. SUMMARY

[0004] At least one embodiment of the present disclosure provides a semiconductor device, comprising: a plurality of storage structure layers stacked along a first direction perpendicular to a substrate; a bit line extending along the first direction; and a word line extending along a second direction parallel to the substrate, the second direction being perpendicular to the first direction; wherein each of the storage structure layers comprises at least one storage structure, each of the storage structures comprises a plurality of storage cells arranged in sequence along the second direction, each of the storage cells comprises a capacitor and a transistor, the capacitor comprises a first electrode, and the transistor comprises a semiconductor layer; in each of the storage cells, a first end of the semiconductor layer in a third direction parallel to the substrate is connected to the first electrode of the capacitor, and a second end of the semiconductor layer in the third direction is connected to the bit line, the third direction intersects the second direction; the word line comprises two sub-word lines spaced apart in the first direction, and a plurality of semiconductor layers of the plurality of storage cells spaced apart along the second direction in each of the storage structures are sandwiched between the two sub-word lines.

[0005] At least one embodiment of this disclosure also provides a method for fabricating a semiconductor device, comprising: forming a plurality of alternating first sacrificial layers and a plurality of second sacrificial layers on a substrate along a first direction perpendicular to the substrate; forming a first deep trench among the plurality of first sacrificial layers and the plurality of second sacrificial layers, and etching the plurality of second sacrificial layers through the first deep trench to form a sacrificial structure in each of the first sacrificial layers; forming a first conductive structure and a first electrode structure, wherein the first conductive structure includes two first sub-conductive structures spaced apart along the first direction, the two first sub-conductive structures being respectively located on both sides of the sacrificial structure in the first direction and both extending along a second direction parallel to the substrate, the first electrode structure being located on the side of the sacrificial structure in a third direction parallel to the substrate and connected to the sacrificial structure, the second direction and the third direction being perpendicular to the first sacrificial layer. The first and second directions are perpendicular to each other, and the third direction intersects with the second direction. Bit lines extending along the first direction are formed on the substrate, and the sacrificial structure is etched to form multiple sacrificial portions. The sacrificial portions are connected to the first electrode structure at their first end in the third direction and to the bit lines at their second end in the third direction. The multiple second sacrificial layers are removed, and the first conductive structure is etched to form word lines. The two first sub-conductive structures of the first conductive structure form two sub-word lines. Multiple isolation structure layers are formed in the first space left after the removal of the multiple second sacrificial layers. The sacrificial portions are removed, and a semiconductor layer is formed in the space where the sacrificial portions are located. A capacitor is formed in the layer where the first sacrificial layer is located, with the first electrode structure as the first electrode, to form a memory structure layer including the capacitor and the semiconductor layer.

[0006] At least one embodiment of this disclosure also provides an electronic device comprising the semiconductor device described in any of the preceding claims, or a semiconductor device formed by a method for manufacturing the semiconductor device described in any of the preceding claims.

[0007] In the semiconductor device provided in this disclosure, by stacking multiple memory structure layers on a substrate, with bit lines extending vertically and word lines extending horizontally, a three-dimensional semiconductor device is realized, improving the density of memory cells and the integration level of the semiconductor device. Furthermore, since the capacitors in each memory cell have a large area, the distance between vertically extending adjacent bit lines is relatively large, thus avoiding the generation of large parasitic capacitances. Therefore, the semiconductor device optimizes its three-dimensional structure according to the characteristics of the memory cells, improving integration level while avoiding large parasitic capacitances between adjacent bit lines. On the other hand, in this semiconductor device, each memory cell includes a transistor, and the first end of the semiconductor layer is connected to the first electrode of the capacitor, while the second end of the semiconductor layer is connected to the bit line. Therefore, the transistor has a larger on-state current while lacking a long source-drain structure, resulting in a smaller size and further improving the integration level of the semiconductor device. In addition, in the semiconductor device, the word line includes two sub-word lines spaced apart in a first direction, and multiple semiconductor layers of multiple memory cells spaced apart in a second direction in each memory structure are sandwiched between the two sub-word lines; thus, the word line of the semiconductor device has a strong control capability over the transistor channel. Attached Figure Description

[0008] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0009] Figure 1 is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this disclosure;

[0010] Figure 2 is a cross-sectional schematic diagram of a semiconductor device provided in an embodiment of the present disclosure along the AA' direction in Figure 1;

[0011] Figure 3 is a schematic cross-sectional view of a semiconductor device provided in an embodiment of the present disclosure along the BB' direction in Figure 1;

[0012] Figure 4 is a cross-sectional schematic diagram of a semiconductor device provided in an embodiment of the present disclosure along the CC' direction in Figure 1;

[0013] Figure 5 is a schematic flowchart of a method for fabricating a semiconductor device according to an embodiment of this disclosure;

[0014] Figures 6 to 80 are schematic diagrams illustrating the structure of a semiconductor device fabrication method according to an embodiment of this disclosure at different steps; and

[0015] Figure 81 is a schematic diagram of a display device provided in an embodiment of this disclosure. Detailed Implementation

[0016] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Based on the described embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0017] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects.

[0018] To reduce the size of memory cells and increase the density of memory cells in semiconductor devices, memory cells can be formed into three-dimensional structures. On the other hand, in semiconductor devices using three-dimensional memory cell structures, bit lines typically extend horizontally, while word lines typically extend vertically; large parasitic capacitances are easily formed between adjacent bit lines along the horizontal direction, affecting the performance of the semiconductor device.

[0019] In this regard, at least one embodiment of the present disclosure provides a semiconductor device, which includes a substrate, a plurality of memory structure layers, bit lines, and word lines; the plurality of memory structure layers are stacked on the substrate along a first direction perpendicular to the substrate; the bit lines extend along the first direction; the word lines extend along a second direction parallel to the substrate, the second direction being perpendicular to the first direction; each memory structure layer includes at least one memory structure, each memory structure including a plurality of memory cells arranged sequentially along the second direction, each memory cell including a capacitor and a transistor, the capacitor including a first electrode and a second electrode, and the transistor including a semiconductor layer; in each memory cell, the semiconductor layer is connected to the first electrode of the capacitor at a first end in a third direction parallel to the substrate, and the semiconductor layer is connected to the bit line at a second end in a third direction, the third direction intersecting the second direction; a bit line is connected to the second end of the semiconductor layer of a plurality of memory cells arranged along the first direction in the plurality of memory structure layers; the word line includes two sub-word lines spaced apart in the first direction, and the plurality of semiconductor layers of the plurality of memory cells spaced apart in the second direction in each memory structure are sandwiched between the two sub-word lines. In the semiconductor device provided in this disclosure, by stacking multiple memory structure layers on a substrate, with bit lines extending vertically and word lines extending horizontally, a three-dimensional semiconductor device is realized, improving the density of memory cells and the integration level of the semiconductor device. Furthermore, since the capacitors in each memory cell have a large area, the distance between vertically extending adjacent bit lines is relatively large, thus avoiding the generation of large parasitic capacitances. Therefore, the semiconductor device optimizes its three-dimensional structure according to the characteristics of the memory cells, improving integration level while avoiding large parasitic capacitances between adjacent bit lines. On the other hand, in this semiconductor device, each memory cell includes a transistor. The first end of the semiconductor layer of the transistor is connected to the first electrode of the capacitor, and the second end of the semiconductor layer is connected to the bit line. Therefore, the transistor has a larger on-state current while lacking a long source-drain structure, resulting in a smaller size and further improving the integration level of the semiconductor device. In addition, in the semiconductor device, the word line includes two sub-word lines spaced apart in a first direction, and multiple semiconductor layers of multiple memory cells spaced apart in a second direction in each memory structure are sandwiched between the two sub-word lines; thus, the word line of the semiconductor device has a strong control capability over the transistor channel.

[0020] At least one embodiment of this disclosure also provides a method for fabricating a semiconductor device, comprising: forming a plurality of alternating first sacrificial layers and a plurality of second sacrificial layers on a substrate along a first direction perpendicular to the substrate; forming a sacrificial structure, a first conductive structure, and a first electrode structure in each first sacrificial layer, wherein the first conductive structure includes two first sub-conductive structures spaced apart in the first direction, the two first sub-conductive structures being respectively located on both sides of the sacrificial structure in the first direction and both extending along a second direction parallel to the substrate; the first electrode structure being located on the side of the sacrificial structure parallel to a third direction of the substrate and connected to the sacrificial structure; the second direction and the third direction being perpendicular to each other with the first direction, and the third direction intersecting the second direction; forming bit lines extending along the first direction on the substrate and etching the sacrificial structure to form a plurality of... The device comprises a sacrificial portion, wherein a first end of the sacrificial portion in a third-direction direction is connected to a first electrode structure, and a second end of the sacrificial portion in a third-direction direction is connected to a bit line; multiple second sacrificial layers are removed, and a first conductive structure is etched to form a word line, wherein two first sub-conductive structures of the first conductive structure form two sub-word lines; multiple isolation structure layers are formed in the first space left after the removal of multiple second sacrificial layers, the sacrificial portion is removed, and a semiconductor layer is formed in the space where the sacrificial portion is located; and a capacitor is formed in the layer where the first sacrificial layer is located, wherein the capacitor uses a first electrode structure as its first electrode to form a memory structure layer including a capacitor and a semiconductor layer, wherein a first end of the semiconductor layer in a third-direction direction is connected to the first electrode of the capacitor, and a second end of the semiconductor layer in a third-direction direction is connected to the bit line, and the semiconductor layer is sandwiched between two sub-word lines. Thus, the method for fabricating the semiconductor device, through the ingenious use of sacrificial layers and etching processes, can form the aforementioned semiconductor device with a three-dimensional structure. On the other hand, by forming multiple sacrificial portions in the first sacrificial layer, each sacrificial portion being connected to a first electrode structure and a bit line respectively, and then replacing the sacrificial portion with a semiconductor layer, the semiconductor device fabrication method can simultaneously form multiple transistors located in multiple memory structure layers in a semiconductor device with a three-dimensional structure, thereby improving fabrication efficiency and reducing costs. Furthermore, by forming two first sub-conductive structures on both sides of the sacrificial portion, forming two sub-word lines from the two first sub-conductive structures, and then replacing the sacrificial portion with a semiconductor layer, the semiconductor device fabrication method can efficiently form transistors with dual-gate structures in a semiconductor device with a three-dimensional structure.

[0021] At least one embodiment of this disclosure also provides an electronic device comprising the aforementioned semiconductor device. Thus, the electronic device also possesses beneficial effects corresponding to the beneficial effects of the included semiconductor device. For example, because the semiconductor device has a high degree of integration and avoids the generation of large parasitic capacitances, the electronic device can have a high degree of integration and strong storage performance.

[0022] The semiconductor device, the method of manufacturing the semiconductor device, and the electronic device provided in the embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0023] Figure 1 is a schematic diagram of the structure of a semiconductor device according to an embodiment of the present disclosure; Figure 2 is a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure along the AA' direction in Figure 1; Figure 3 is a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure along the BB' direction in Figure 1; Figure 4 is a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure along the CC' direction in Figure 1.

[0024] As shown in Figure 1, the semiconductor device 200 includes a substrate 210, a plurality of memory structure layers 100, bit lines 220, and word lines 230. The plurality of memory structure layers 100 are stacked on the substrate 210 along a first direction Z perpendicular to the substrate 210. The bit lines 220 extend along the first direction Z. The word lines 230 extend along a second direction X parallel to the substrate 210, and the second direction X is perpendicular to the first direction Z. It should be noted that an isolation layer or insulating layer is disposed between adjacent memory structure layers.

[0025] As shown in Figures 1 and 2, each memory structure layer 100 includes at least one memory structure 110. Each memory structure 110 includes a plurality of memory cells 120 sequentially arranged along a second direction X. Each memory cell 120 includes a capacitor 122 and a transistor 124. The capacitor 122 includes a first electrode 1221 and a second electrode 1222. The transistor 124 includes a semiconductor layer 1244. In each memory cell 120, the first end 1244A of the semiconductor layer 1244 in a third direction Y parallel to the substrate 210 is connected to the first electrode 1221 of the capacitor 122, and the second end 1244B of the semiconductor layer 1244 in the third direction Y is connected to the bit line 220. The third direction Y intersects the second direction X and is perpendicular to the first direction Z.

[0026] As shown in Figures 1 and 3, a bit line 220 is connected to the second end 1244B of the semiconductor layer 1244 of a plurality of memory cells 120 arranged along a first direction in a plurality of memory structure layers 100; that is, the bit line 220 extending along the first direction Z perpendicular to the substrate 210 is connected to the second end 1244B of the semiconductor layer 1244 of a plurality of memory cells 120 stacked in the first direction Z.

[0027] As shown in Figures 1, 3, and 4, the word line 230 includes two sub-word lines 232 spaced apart in the first direction Z. Multiple semiconductor layers 1244 of the multiple memory cells 120 spaced apart in the second direction X of each memory structure 110 are sandwiched between the two sub-word lines 232. It should be noted that the two sub-word lines 232 of the word line 230 can be connected to the same electrical signal; for example, the two sub-word lines 232 can be connected at both ends and connected to the same signal input / output terminal.

[0028] In the semiconductor device provided in this embodiment, the transistor 124 in each memory cell 120 functions as a switch. When data needs to be read or written, the transistor 124 is turned on, allowing charge exchange between the capacitor 122 and the bit line 220. The capacitor 122 in each memory cell 120 is used to store binary data. For example, the charging state (charged or uncharged) of the capacitor 122 can be used to represent "1" and "0" in binary data. When data needs to be written, the switching state of the transistor 124 can be controlled by the word line 230 to charge or discharge the capacitor, thereby changing its storage state. When data needs to be read, the switching state of the transistor 124 is also controlled by the word line 230 to exchange charge between the capacitor 122 and the bit line 220, and the storage state of the capacitor is determined by detecting changes in the voltage of the bit line 220. Thus, each memory cell can realize data writing and reading.

[0029] Based on this, by stacking multiple memory structure layers on a substrate, with bit lines extending vertically and word lines extending horizontally, the semiconductor device achieves a three-dimensional structure, improving the density of memory cells and the integration level of the semiconductor device. Furthermore, since the capacitors in each memory cell have a large area, the distance between vertically extending adjacent bit lines is relatively large, thus avoiding the generation of large parasitic capacitances. Therefore, the semiconductor device optimizes its three-dimensional structure according to the characteristics of the memory cells, improving integration level while avoiding large parasitic capacitances between adjacent bit lines. On the other hand, in the semiconductor device, each memory cell includes a transistor. The first end of the semiconductor layer of each transistor is connected to the first electrode of the capacitor, and the second end of the semiconductor layer is connected to the bit line. Therefore, the transistor has a larger on-state current while lacking a long source-drain structure, resulting in a smaller size and further improving the integration level of the semiconductor device. In addition, in the semiconductor device, the word line includes two sub-word lines spaced apart in a first direction, and multiple semiconductor layers of multiple memory cells spaced apart in a second direction in each memory structure are sandwiched between the two sub-word lines; thus, the word line of the semiconductor device has a strong control capability over the transistor channel.

[0030] It should be noted that, as shown in Figures 1, 3, and 4, the semiconductor layer 1244 as a whole serves as the channel of the transistor 124, and the overlapping portions of the two sub-word lines 232 with the semiconductor layer 1244 can serve as the gates of the transistors. Furthermore, the memory cell in the above embodiment adopts a 1T1C structure, but embodiments of this disclosure include, but are not limited to, this, and the memory cell may also adopt other types of structures.

[0031] In some examples, the semiconductor devices described above can be used to construct Dynamic Random Access Memory (DRAM). Of course, embodiments of this disclosure include, but are not limited to, the semiconductor devices described above can also be used to construct other types of memory. In some examples, as shown in Figures 1 and 2, in each memory cell 120, the semiconductor layer 1244 further includes a first protrusion 12441 and a second protrusion 12442 protruding outward in a second direction. The first protrusion 12441 includes a third end 1244C remote from the line connecting the first end 1244A and the second end 1244B, and the second protrusion 12442 includes a fourth end 1244D remote from the line connecting the first end 1244A and the second end 1244B. Because the semiconductor layer includes the aforementioned first and second protrusions, the effective width of the semiconductor layer of the transistor in each memory cell is increased, thereby improving the channel width-to-length ratio and thus having a larger on-state current.

[0032] In some examples, as shown in Figures 1 and 2, the distance between the third terminal 1244C and the fourth terminal 1244D is greater than the average width of the semiconductor layer 1244 in the second direction X, thereby increasing the effective width of the transistors in each memory cell.

[0033] In some examples, as shown in Figures 1 and 2, the edge of the orthographic projection of the semiconductor layer 1244 onto the substrate includes a first curve 301 and a second curve 302. The first curve 301 connects the second end 1244B and the third end 1244C of the semiconductor layer 1244, and the second curve 302 connects the second end 1244B and the fourth end 1244D of the semiconductor layer 1244. Thus, the aforementioned oxide semiconductor layer has relatively smooth edges, thereby improving transistor performance. Furthermore, the aforementioned semiconductor layer is also easily formed using isotropic etching processes, saving on masking processes and reducing costs.

[0034] In some examples, as shown in Figures 1 and 2, the first curve 301 and the second curve 302 may be symmetrical with respect to the line connecting the first terminal 1244A and the second terminal 1244B, thereby giving the transistor better symmetry. Of course, embodiments of this disclosure include, but are not limited to, this.

[0035] In some examples, the aforementioned semiconductor layer 1244 can be an oxide semiconductor layer, the material of which includes indium gallium zinc oxide (IGZO). This results in transistors in the memory cell exhibiting higher carrier mobility and lower leakage current. On one hand, the memory cell can have a smaller volume, thereby further improving the integration density of the semiconductor device; on the other hand, the memory cell can have stronger performance. Of course, embodiments of this disclosure include, but are not limited to, other semiconductor materials may also be used for the aforementioned semiconductor layer.

[0036] For example, the semiconductor layer described above can also be made of other oxide semiconductor materials, such as indium tin oxide (ITO), indium tungsten oxide (IWO), and zinc oxide (ZnO). x Indium oxide (InO) x Indium tungsten oxide (InWO), tin oxide (SnO2), titanium oxide (TiO2) x ), Zinc oxide (Zn) x O y N z ), magnesium zinc oxide (Mg x Zn y O z Indium zinc oxide (In) x Zn y O z Zirconia indium zinc (Zr) x In y Zn z O a ), Hafnium Indium Zinc Oxide (Hf) x In y Zn z O a ), tin indium zinc oxide (Sn x In y Zn z O a ), aluminum tin indium zinc (Al x Sn y In z Zn a O d ) and silicon indium zinc (Si x In y Zn z O a At least one of the following.

[0037] In some examples, the thickness of the semiconductor layer 1244 in the first direction ranges from 5 to 10 nanometers. This provides greater control over the word line over the oxide semiconductor, resulting in superior performance of the transistors in the memory cell.

[0038] In some examples, as shown in Figures 1, 3, and 4, in each memory cell 120, the transistor 124 further includes two gate insulating layers 1246, located between the semiconductor layer 1244 and the two sub-word lines 232, respectively. It should be noted that the two gate insulating layers can be made of the same material or different materials.

[0039] In some examples, the gate insulating layer 1246 described above may be made of a high-k dielectric material (dielectric constant greater than 3.9), thereby making the transistor thinner and lighter. Of course, the embodiments of this disclosure include, but are not limited to, the gate insulating layer 1246 described above may also be made of a low-k dielectric material (dielectric constant greater than or equal to 2.5 and less than 3.9) or an ultra-low-k dielectric material (dielectric constant less than 2.5).

[0040] For example, the high-K dielectric materials mentioned above include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanium oxide (SrTiO3).

[0041] For example, the material of the gate insulating layer 1246 mentioned above includes hafnium oxide (HfO). x This results in the gate insulating layer 1246 having a high dielectric constant and high thermal stability, thereby improving the stability of the transistor and avoiding defects such as leakage current. Of course, embodiments of this disclosure include, but are not limited to, the gate insulating layer described above can also be made of other materials. For example, the gate insulating layer can be made of at least one of silicon oxide, silicon nitride, silicon oxynitride, metal oxide, and metal oxynitride.

[0042] In some examples, as shown in Figures 1 and 2, the semiconductor device 200 includes multiple bit lines 220 arranged along a second direction, and multiple memory cells 120 of each memory structure 110 are respectively connected to the multiple bit lines 220. Each bit line 220 is connected to the second end 1244B of the semiconductor layer 1244 of the multiple memory cells 120 arranged along a first direction in the multiple memory structure layers 100. In this case, the multiple bit lines 220 are spaced apart in the second direction. Since the area occupied by the capacitor in the memory cell 120 is large, the distance between two adjacent bit lines 220 in the second direction is relatively large, thus avoiding the generation of large parasitic capacitance. On the other hand, the memory structure 110 can increase the number of memory cells 120 in the memory structure 110 by providing more memory cells 120 in the second direction, thereby improving the integration of the semiconductor device.

[0043] In some examples, as shown in Figures 1 and 2, each memory structure layer 100 includes at least one memory structure 110. The semiconductor device shown in Figures 1 and 2 includes a first memory structure 110A and a second memory structure 110B. The first memory structure 110A and the second memory structure 110B are arranged relatively spaced apart in the third direction Y. Multiple bit lines 220 connecting multiple memory cells 120 of the first memory structure 110A and multiple bit lines 220 connecting multiple memory cells 120 of the second memory structure 110B are arranged in an array on the substrate 210 with their orthogonal projections along the second direction X and the third direction Y. Thus, each memory structure layer can form more memory structures through the above arrangement, thereby increasing the integration density of the semiconductor device. In addition, since the first memory structure 110A and the second memory structure 110B are arranged at relative intervals in the third direction, the multiple bit lines connected to the multiple memory cells of the first memory structure 110A and the multiple bit lines connected to the multiple memory cells of the second memory structure 110B are arranged in an array on the substrate along the second direction and the third direction. The layout of each memory structure layer is more compact, and the bit lines required for the first memory structure and the second memory structure can be formed in one step by the manufacturing process.

[0044] In some examples, as shown in Figures 1 and 2, the first storage structure 110A and the second storage structure 110B may be mirror-symmetrical with respect to the axis located between the first storage structure 110A and the second storage structure 110B.

[0045] In some examples, as shown in Figures 1 and 3, the semiconductor device 200 further includes an isolation structure layer 240 located between adjacent memory structure layers 100, thereby isolating the adjacent memory structure layers 100 from each other.

[0046] In some examples, the substrate 210 described above may be made of at least one of semiconductor materials, insulating materials, and conductive materials. The substrate 210 may be a single-layer structure or a multilayer structure. For example, the substrate 210 may be a silicon substrate, a silicon-germanium substrate, a silicon-germanium-carbon substrate, a silicon carbide substrate, a gallium arsenide substrate, an indium arsenide substrate, an indium phosphide substrate, or other group III / V or group II / VI semiconductor substrates. Alternatively, the substrate 210 may be a multilayer structure including a silicon layer and a silicon-germanium layer, a multilayer structure including a silicon layer and a silicon carbide layer, or a multilayer structure including silicon-on-insulator or silicon-germanium-on-insulator.

[0047] In some examples, the materials of the bit lines 220 and word lines 230 may include one or more of polysilicon, metals, conductive metal nitrides, conductive metal oxides, and metal silicides. For example, the metals may be tungsten (W), nickel (Ni), copper (Cu), aluminum (Al), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), or titanium (Ti); the conductive metal nitrides may include titanium nitride (TiN); the conductive metal oxides may include iridium oxide (IrO2); and the metal silicides may include tungsten silicon (WSi). It should be noted that the bit lines and word lines may be made of the same material or different materials.

[0048] In some examples, the capacitor 122 described above may be a sandwich capacitor. The capacitor 122 may include two second electrodes 1222. A first dielectric layer 521 is disposed on the outer side of the first electrode 1221, and a second dielectric layer 522 is disposed on the inner side of the first electrode 1221. One of the two second electrodes 1222 is disposed on the side of the first dielectric layer 521 away from the first electrode 1221, and the other of the two second electrodes 1222 is disposed on the side of the second dielectric layer 522 away from the first electrode 1221. The sandwich capacitor 122 has a large capacitance in a small space.

[0049] In some examples, in each capacitor 122, the first electrode 1221 is annular in shape when projected onto the substrate 210, one of the two second electrodes 1222 is located inside the first electrode 1221, and the other of the two second electrodes 1222 is located outside the first electrode 1221.

[0050] In some examples, the orthographic projection of the first electrode 1221 onto the substrate 210 is an elliptical ring.

[0051] At least one embodiment of this disclosure also provides a method for fabricating a semiconductor device. Figure 5 is a schematic flowchart of a method for fabricating a semiconductor device according to an embodiment of this disclosure. As shown in Figure 5, the method for fabricating the semiconductor device includes the following steps S101-S106.

[0052] Step S101: Form a plurality of alternating first sacrificial layers and a plurality of second sacrificial layers on the substrate along a first direction perpendicular to the substrate.

[0053] For example, a deposition process can be used to alternately deposit multiple first sacrificial layers and multiple second sacrificial layers on a substrate.

[0054] Step S102: A first deep trench is formed among multiple first sacrificial layers and multiple second sacrificial layers, and the multiple second sacrificial layers are etched through the first deep trench to form a sacrificial structure in each first sacrificial layer.

[0055] Step S103: Form a first conductive structure and a first electrode structure. The first conductive structure includes two first sub-conductive structures spaced apart in a first direction. The two first sub-conductive structures are located on both sides of the sacrificial structure in the first direction and both extend along a second direction parallel to the substrate. The first electrode structure is located on the side of the sacrificial structure in a third direction parallel to the substrate and is connected to the sacrificial structure. The second direction and the third direction are both perpendicular to the first direction, and the third direction intersects the second direction.

[0056] Step S104: Form multiple bit lines extending along the first direction and etch the sacrificial structure to form multiple sacrificial portions. The first end of the sacrificial portion in the third direction is connected to the first electrode structure, and the second end of the sacrificial portion in the third direction is connected to the bit lines.

[0057] Step S105: Remove multiple second sacrificial layers and etch the first conductive structure to form word lines. The two first sub-conductive structures of the first conductive structure form two sub-word lines.

[0058] Step S106: After the multiple second sacrificial layers are removed, a multiple isolation structure layer is formed in the first space left behind. The sacrificial part is removed, and a semiconductor layer is formed in the space where the sacrificial part is located.

[0059] Step S107: A capacitor is formed in the layer where the first sacrificial layer is located, with the first electrode structure serving as the first electrode, to form a storage structure layer including a capacitor and a semiconductor layer.

[0060] In the semiconductor device fabrication method provided in this disclosure, in the formed semiconductor device, the first end of the semiconductor layer in a third-direction direction is connected to the first electrode of a capacitor, and the second end of the semiconductor layer in a third-direction direction is connected to the bit line. The semiconductor layer is sandwiched between two sub-word lines. By forming multiple sacrificial portions in the first sacrificial layer, each sacrificial portion being connected to the first electrode structure and the bit line respectively, and then replacing the sacrificial portion with the semiconductor layer, the semiconductor device fabrication method can simultaneously form multiple transistors located in multiple memory structure layers in a semiconductor device with a three-dimensional structure, thereby improving fabrication efficiency and reducing costs. Furthermore, by forming two first sub-conductive structures on both sides of the sacrificial portion, forming two sub-word lines from the two first sub-conductive structures, and then replacing the sacrificial portion with the semiconductor layer, the semiconductor device fabrication method can efficiently form transistors with dual-gate structures in a semiconductor device with a three-dimensional structure.

[0061] On the other hand, in the semiconductor device formed by the above-described semiconductor device fabrication method, the first sacrificial layer is ultimately replaced by a memory structure layer including a capacitor and a semiconductor layer. This allows multiple memory structure layers to be stacked on the substrate, with bit lines extending vertically and word lines extending horizontally, thus realizing a semiconductor device with a three-dimensional structure. This improves the density of memory cells and the integration level of the semiconductor device. Furthermore, since the capacitors in each memory cell have a large area, the distance between vertically extending adjacent bit lines is relatively large, thus avoiding the generation of large parasitic capacitances. Therefore, the semiconductor device fabrication method optimizes the three-dimensional structure of the semiconductor device according to the characteristics of the memory cells, improving integration level while avoiding large parasitic capacitances between adjacent bit lines. Furthermore, in the semiconductor device, each memory cell includes a transistor. The first end of the semiconductor layer of the transistor is connected to the first electrode of the capacitor, and the second end of the semiconductor layer is connected to the bit line. Therefore, the transistor has a larger on-state current while lacking a long source-drain structure, resulting in a smaller size and further improving the integration level of the semiconductor device. In addition, the word line includes two sub-word lines spaced apart in the first direction, and multiple semiconductor layers of multiple memory cells spaced apart along the second direction X in each memory structure are sandwiched between the two sub-word lines; thus, the word line has a strong control capability over the transistor channel.

[0062] In some examples, forming multiple bit lines extending along a first direction on a substrate and etching a sacrificial structure to form multiple sacrificial portions includes: forming multiple second conductive structures passing through multiple first sacrificial layers and multiple second sacrificial layers, each second conductive structure having a cylindrical structure extending along the first direction and a conductive portion connected to the sacrificial structure; etching the sacrificial structure based on the multiple second conductive structures to remove a portion of the sacrificial structure and form the multiple sacrificial portions arranged along the second direction; and etching the multiple second conductive structures, retaining multiple conductive portions of the multiple second conductive structures to form multiple bit lines, the multiple bit lines extending along the first direction and spaced apart in the second direction. It should be noted that the above-mentioned etching of the sacrificial structure based on multiple second conductive structures to remove a portion of the sacrificial structure and form multiple sacrificial portions arranged along the second direction refers to using multiple second conductive structures as barrier structures to etch the sacrificial structure to remove a portion of the sacrificial structure and form multiple sacrificial portions arranged along the second direction.

[0063] In the semiconductor device fabrication method provided in the example, a second conductive structure with a cylindrical shape is formed, and then a sacrificial structure is etched using multiple second conductive structures as barrier structures. The second conductive structure itself can not only be used to form bit lines, but also act as a barrier structure during the etching process to protect the subsequently formed sacrificial portion (semiconductor layer) from being removed by the etching process. Furthermore, due to the cylindrical shape of the second conductive structure, the etched portion of the sacrificial structure can be subsequently used to form a containment structure, thereby facilitating the limitation of the area during subsequent replacement of the sacrificial portion. Additionally, the etched portion of the sacrificial structure can also enlarge the third deep hole, facilitating the etching of the second conductive structure to form bit lines. Therefore, in the above steps, the cylindrical second conductive structure plays multiple roles, simplifying the process steps and reducing manufacturing costs.

[0064] In some examples, forming a sacrificial structure in each first sacrificial layer includes: forming a first deep trench in a plurality of first sacrificial layers and a plurality of second sacrificial layers, the first deep trench extending along a first direction and a second direction; and laterally etching the plurality of second sacrificial layers through the first deep trench to form a plurality of first grooves in each second sacrificial layer that extend along the second direction and are spaced apart in the first direction, each first groove being recessed from the first deep trench along a third direction, wherein the first sacrificial layer between two adjacent first grooves forms a sacrificial structure.

[0065] In some examples, forming the first conductive structure and the first electrode structure includes: depositing an initial gate insulating layer and a first conductive layer on the surface of the first deep trench and the first groove, the first conductive layer including a first conductive portion located on two sidewalls of the first groove, a second conductive portion located at the bottom of the first groove, and a third conductive portion located on the sacrificial structure near the center of the first deep trench; filling the first deep trench and the first groove with a first filler structure; etching the first filler structure to form a second deep trench to expose the third conductive portion; etching and removing the third conductive portion and the exposed initial gate insulating layer through the second deep trench, thereby disconnecting the two first conductive portions located on both sides of the sacrificial structure in a first direction, and forming the first conductive structure. The fabrication method, by forming the aforementioned first deep trench and first groove, can form the first conductive structure in the layer space where multiple first sacrificial layers are located, and the first conductive structure is used to form subsequent word lines with two sub-word lines.

[0066] The following detailed description of the semiconductor device fabrication method, with reference to specific embodiments, provides a concrete example.

[0067] Figure 6 is a schematic diagram of the steps of a method for fabricating a semiconductor device according to an embodiment of the present disclosure. Figure 7 is a cross-sectional view along line AA' in Figure 6; Figure 8 is a cross-sectional view along line BB' in Figure 6; Figure 9 is a cross-sectional view along line CC' in Figure 6.

[0068] As shown in FIG6, after forming a plurality of alternating first sacrificial layers 410 and a plurality of second sacrificial layers 420 on the substrate 210 along a first direction perpendicular to the substrate 210, a first deep trench 431 can be formed in the plurality of first sacrificial layers 410 and the plurality of second sacrificial layers 420 to separate the plurality of first sacrificial layers 410 and the plurality of second sacrificial layers 420 into two parts.

[0069] As shown in Figure 7, a first deep trench 431 can be formed in multiple first sacrificial layers 410 and multiple second sacrificial layers 420. It should be noted that the circular holes in Figure 7 are the areas where capacitors are formed, which will be described below.

[0070] For example, the first deep trench 431 described above can be formed in a plurality of first sacrificial layers 410 and a plurality of second sacrificial layers 420 using photolithography and etching processes. The first deep trench 431 extends along a first direction and a second direction.

[0071] As shown in Figure 6, after forming a first deep trench 431 in multiple first sacrificial layers 410 and multiple second sacrificial layers 420, the multiple second sacrificial layers 420 are etched through the first deep trench 431 to form multiple first grooves 425 extending in a second direction and spaced apart in a first direction in each second sacrificial layer 420. Each first groove 425 is recessed from the first deep trench 431 in a third direction. At this time, a sacrificial structure 415 is formed in the first sacrificial layer 410 between two adjacent first grooves 425. The sacrificial structure 415 is a protrusion structure located between two adjacent first grooves 425.

[0072] As shown in Figure 8, a plurality of recessed first grooves 425 and a sacrificial structure 415 located between two adjacent first grooves are formed on the sidewall of the first deep trench 431. It should be noted that the first sacrificial layer and the second sacrificial layer are made of different materials. Therefore, the second sacrificial layer can be partially etched and removed by selective etching, but the first sacrificial layer is not etched, thereby forming the aforementioned first grooves and sacrificial structures.

[0073] For example, the material of the first sacrificial layer described above can be silicon oxide, and the material of the second sacrificial layer can be silicon nitride. Of course, the embodiments disclosed herein are not limited to this, and the first and second sacrificial layers can also be made of other materials, as long as they are different from each other.

[0074] As shown in Figures 7 and 9, multiple deep holes are formed in the multiple first sacrificial layers 410 and multiple second sacrificial layers 420 on both sides of the first deep trench 431, and annular electrode structures are formed in each deep hole. These deep holes are used to subsequently form a capacitor. Of course, the embodiments of this disclosure include, but are not limited to, this method of fabricating the semiconductor device, and can also form other types of capacitors.

[0075] Figure 10 is a schematic diagram of the steps of another semiconductor device fabrication method provided in an embodiment of the present disclosure. Figure 11 is a cross-sectional view along line AA' in Figure 10; Figure 12 is a cross-sectional view along line BB' in Figure 10; Figure 13 is a cross-sectional view along line CC' in Figure 10.

[0076] As shown in Figure 10, an initial gate insulating layer 440 and a first conductive layer 450 are deposited on the surfaces of the first deep trench 431 and the first recess 425. The first conductive layer 450 covers the surfaces of the first deep trench 431 and the first recess 425, and therefore includes a first conductive portion 451 located on the two sidewalls of the first recess 425, a second conductive portion 452 located at the bottom of the first recess 425, and a third conductive portion 453 located on the sacrificial structure 415 near the center of the first deep trench 431. It should be noted that the initial gate insulating layer 440 described above is formed into the final gate insulating layer of the semiconductor device, namely the gate insulating layer 1246 described above, after processing.

[0077] As shown in Figure 11, an initial gate insulating layer 440 and a first conductive layer 450 are formed on the inner surface of the first deep trench 431. For example, the initial gate insulating layer 440 and the first conductive layer 450 can be deposited sequentially on the surfaces of the first deep trench 431 and the first groove 425 by a deposition process.

[0078] As shown in Figure 12, the aforementioned initial gate insulating layer 440 and first conductive layer 450 are also deposited on the side of the plurality of first sacrificial layers 410 and the plurality of second sacrificial layers 420 away from the substrate 210, and they can be removed in subsequent process steps.

[0079] As shown in FIG13, the first conductive layer 450 covers the surface of the first deep trench 431 and the first groove 425, and therefore includes a first conductive portion 451 located on the two sidewalls of the first groove 425, a second conductive portion 452 located at the bottom of the first groove 425, and a third conductive portion 453 located on the sacrificial structure 415 near the center of the first deep trench 431.

[0080] In some examples, as shown in Figures 10 and 13, after etching multiple second sacrificial layers 420 through a first deep trench 431 to form a first groove 425 recessed from the first deep trench 431 in a third direction in each second sacrificial layer 420, the sacrificial structure 415 located between two adjacent first grooves 425 can be thinned by an etching process. This results in a thinner final semiconductor layer, giving the word lines stronger control over the semiconductor layer. It should be noted that since other structures, such as capacitors, need to be formed in the space where the first sacrificial layer is located, the first sacrificial layer has a certain thickness. The above-described thinning process can simultaneously satisfy the formation of other structures and also form a thinner semiconductor layer.

[0081] For example, the thickness of the first sacrificial layer 410 in the first direction Z perpendicular to the substrate 210 can be 30-50 nanometers, and the thickness of the thinned sacrificial structure 415 in the first direction Z perpendicular to the substrate 210 can be 5-10 nanometers.

[0082] In some examples, the initial gate insulating layer 440 described above may be made of a high-k dielectric material (dielectric constant greater than 3.9), thereby making the transistor thinner and lighter. Of course, the embodiments of this disclosure include, but are not limited to, the initial gate insulating layer 440 described above may also be made of a low-k dielectric material (dielectric constant greater than or equal to 2.5 and less than 3.9) or an ultra-low-k dielectric material (dielectric constant less than 2.5).

[0083] For example, the high-K dielectric materials mentioned above include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanium oxide (SrTiO3).

[0084] For example, the material of the initial gate insulating layer 440 mentioned above includes hafnium oxide (HfO). x This results in the initial gate insulating layer having a high dielectric constant and high thermal stability, thereby improving the stability of the transistor and avoiding defects such as leakage. Of course, the embodiments disclosed herein are not limited to this, and the initial gate insulating layer described above can also be made of other materials. For example, the initial gate insulating layer may be made of at least one of silicon oxide, silicon nitride, silicon oxynitride, metal oxide, and metal oxynitride.

[0085] In some examples, the material of the first conductive layer 450 described above includes titanium nitride (TiN). Of course, embodiments of this disclosure include, but are not limited to, other conductive materials may also be used for the first conductive layer described above.

[0086] For example, the material of the first conductive layer 450 may include one or more of polycrystalline silicon, metal, conductive metal nitride, conductive metal oxide, and metal silicide. For example, the metal may be tungsten (W), nickel (Ni), copper (Cu), aluminum (Al), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), or titanium (Ti); the conductive metal nitride may include titanium nitride (TiN); the conductive metal oxide may include iridium oxide (IrO2); and the metal silicide may include tungsten silicon (WSi). Furthermore, the first conductive layer may be a single-layer structure or a multi-layer composite structure.

[0087] Figure 14 is a schematic diagram of the steps of another semiconductor device fabrication method provided in an embodiment of the present disclosure; Figure 15 is a cross-sectional schematic diagram along line AA' in Figure 14; Figure 16 is a cross-sectional schematic diagram along line BB' in Figure 14; Figure 17 is a cross-sectional schematic diagram along line CC' in Figure 14.

[0088] As shown in Figure 14, after depositing an initial gate insulating layer 440 and a first conductive layer 450 on the surfaces of the first deep trench 431 and the first groove 425, a first filling structure 461 is filled into the first deep trench 431 and the first groove 425; the first filling structure 461 completely fills the first deep trench 431 and the first groove 425. It should be noted that since the first filling structure 461 is partially removed after its formation, Figure 14 only shows the portion of the first filling structure 461 in the first groove 425.

[0089] For example, the material of the first filling structure 461 described above includes silicon oxide. The first filling structure is essentially a sacrificial structure; using silicon oxide to form the first filling structure facilitates compatibility with conventional semiconductor processes and also facilitates subsequent etching and removal. Of course, embodiments of this disclosure include, but are not limited to, other materials may also be used to form the first filling structure.

[0090] As shown in Figure 14, after the first filling structure 461 is formed, the first filling structure 461 is etched to form a second deep trench 432 to expose the third conductive portion 453. At this time, the remaining portion of the first filling structure 461 fills the first groove 425 and is located between adjacent first conductive portions 451.

[0091] As shown in Figure 14, by etching and removing the third conductive portion 453 and the exposed initial gate insulating layer 440 through the second deep trench 432, the two first conductive portions 451 located on both sides of the sacrificial structure 415 in the first direction are disconnected, forming the aforementioned first conductive structure 455. At this time, the first conductive structure 455 includes two first conductive portions 451 and a second conductive portion 452 located at the bottom of the first groove 425.

[0092] As shown in Figure 15, the first conductive layer 450 after etching only includes the first conductive structure located in the first groove 425. The third conductive part 453 is removed. At the same time, while removing the third conductive part 453, a portion of the two first conductive parts 451 are etched away from the second deep trench 432 along a third direction. This facilitates the formation of isolation between the first conductive part 451 and other conductive structures when forming the insulating layer later.

[0093] As shown in Figure 16, the portion of the first conductive layer 450 located on the side of the plurality of first sacrificial layers 410 and the plurality of second sacrificial layers 420 away from the substrate 210 is also removed in the etching process.

[0094] As shown in Figure 17, the first conductive structure 455 includes two first conductive portions 451 and a second conductive portion 452 located at the bottom of the first groove 425. Additionally, the portion of the first conductive layer 450 located at the bottom of the second deep trench 432 is also removed during the etching process.

[0095] Figure 18 is a schematic diagram of the steps of another semiconductor device fabrication method provided in an embodiment of the present disclosure; Figure 19 is a cross-sectional view along line AA' in Figure 18; Figure 20 is a cross-sectional view along line BB' in Figure 18; Figure 21 is a cross-sectional view along line CC' in Figure 18.

[0096] As shown in Figure 18, after the first conductive structure 455 is formed, a first insulating layer 471 is deposited on the sidewall of the second deep trench 432; and a second filling structure 462 is filled in the second deep trench 432 where the first insulating layer 471 is formed.

[0097] For example, the material of the first insulating layer 471 described above includes silicon oxide. Of course, the embodiments disclosed herein are not limited to this, and the first insulating layer may also be made of other suitable insulating materials.

[0098] For example, the material of the second filling structure 462 described above includes polysilicon. The second filling structure is essentially a sacrificial structure; using polysilicon to form the second filling structure facilitates compatibility with conventional semiconductor processes and also facilitates subsequent etching and removal. Of course, embodiments of this disclosure include, but are not limited to, other materials may also be used to form the second filling structure.

[0099] As shown in Figure 19, the first insulating layer 471 is located on the sidewall of the second deep trench 432. In addition, the second filling structure 462 is located between the first insulating layers 471, filling the second deep trench 432.

[0100] As shown in Figure 18, after forming the second filling structure 462 described above, a first hard mask layer 481 is formed on the side of the plurality of first sacrificial layers 410, the plurality of second sacrificial layers 420, and the second filling structure 462 away from the substrate 210. The first hard mask layer 481 can be used as a mask and can protect the top of the overall structure in subsequent etching processes, facilitating etching from the side.

[0101] For example, the material of the first hard mask layer 481 can be silicon oxide. Of course, embodiments of this disclosure include, but are not limited to, the material of the first hard mask layer 481 can also be other materials.

[0102] As shown in FIG18, a plurality of second deep holes 492 extending in a first direction and spaced apart in a second direction are formed in the first hard mask layer 481 and the second filling structure 462, and each second deep hole 492 passes through a plurality of first sacrificial layers 410 and a plurality of second sacrificial layers 420.

[0103] For example, multiple second deep holes 492 can be formed in the first hard mask layer 481 and the second filling structure 462 by photolithography and dry etching processes.

[0104] As shown in Figures 20 and 21, a plurality of second deep holes 492 are formed in the first hard mask layer 481 and the second filling structure 462; the second deep holes 492 do not expose the sacrificial structure 415.

[0105] Figure 22 is a schematic diagram of the steps of another semiconductor device fabrication method provided in an embodiment of the present disclosure; Figure 23 is a cross-sectional view along line AA' in Figure 22; Figure 24 is a cross-sectional view along line BB' in Figure 22; Figure 25 is a cross-sectional view along line CC' in Figure 22.

[0106] As shown in Figure 22, after forming multiple second deep holes 492 in the first hard mask layer 481 and the second filling structure 462 using an etching process, a wet etching process can be used to etch the second filling structure 462 and the first insulating layer 471 through the multiple second deep holes 492, widening the width of the second deep holes 492 and exposing the sacrificial structure 415 to form multiple first deep holes 491. The multiple first deep holes 491 are spaced apart in the second direction. Each first deep hole 491 exposes the sacrificial structure 415 on both sides along the third direction; that is, it can contact the sacrificial structure 415 through the first deep hole 491. Therefore, a bit line extending in the vertical direction and in contact with the sacrificial structure 415 can be formed by depositing conductive material on the sidewalls of the first deep holes 491.

[0107] As shown in Figure 22, a second conductive layer 510 is deposited inside a plurality of first deep holes 491. The second conductive layer 510 can contact the sacrificial structure 415 through the first deep holes 491.

[0108] In some examples, the material of the second conductive layer 510 described above includes titanium nitride (TiN). Of course, embodiments of this disclosure include, but are not limited to, other conductive materials may also be used for the second conductive layer described above.

[0109] For example, the material of the second conductive layer 510 may include one or more of polycrystalline silicon, metal, conductive metal nitride, conductive metal oxide, and metal silicide. For example, the metal may be tungsten (W), nickel (Ni), copper (Cu), aluminum (Al), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), or titanium (Ti); the conductive metal nitride may include titanium nitride (TiN); the conductive metal oxide may include iridium oxide (IrO2); and the metal silicide may include tungsten silicon (WSi). Furthermore, the second conductive layer may be a single-layer structure or a multi-layer composite structure.

[0110] As shown in Figure 23, a second conductive layer 510 is formed on the inner sidewalls of the plurality of first deep holes 491. As shown in Figure 24, the second conductive layer 510 also includes a portion located at the bottom of the first deep holes 491.

[0111] As shown in Figure 25, the second conductive layer 510 also includes a portion located away from the substrate in the first hard mask layer 481; the portion of the second conductive layer 510 located on the inner sidewall of the first deep hole 491 can contact the sacrificial structure 415. The portion of the second conductive layer 510 located on the inner sidewall of the first deep hole 491 is insulated from the first conductive structure 455.

[0112] It is worth noting that, as shown in Figures 18 and 22, the embodiments of this disclosure employ two steps to form the first deep hole. This is because dry etching processes are not prone to maintaining consistent aperture diameters at different depths when etching thicker film layers. The embodiments first form a second deep hole using a dry etching process, and then widen the second deep hole using a wet etching process to form the first deep hole, thereby maintaining consistent aperture diameters at different depths. Therefore, the semiconductor device fabrication method can stack more memory structure layers on the substrate, thereby further improving the integration density of the semiconductor device.

[0113] Of course, the embodiments disclosed herein include, but are not limited to, if the process conditions are mature or the film thickness is small, multiple first deep holes can also be formed directly in the first hard mask layer and the second filling structure, each first deep hole passing through multiple first sacrificial layers and multiple second sacrificial layers, and each first deep hole exposing the sacrificial structure.

[0114] Figure 26 is a schematic diagram of the steps of another semiconductor device fabrication method provided in an embodiment of the present disclosure; Figure 27 is a cross-sectional view along line AA' in Figure 26; Figure 28 is a cross-sectional view along line BB' in Figure 26; Figure 29 is a cross-sectional view along line CC' in Figure 26.

[0115] As shown in Figure 26, the portion of the second conductive layer 510 located at the bottom of the plurality of first deep holes 491 can be removed by etching process to form a plurality of second conductive structures 515 passing through the plurality of first sacrificial layers 410 and the plurality of second sacrificial layers 420. Each second conductive structure 515 has a cylindrical structure extending along a first direction and each second conductive structure 515 has a conductive portion 5150 connected to the sacrificial structure 415.

[0116] As shown in Figure 26, multiple third filling structures 463 are formed by filling multiple second conductive structures 515 with insulating material.

[0117] For example, the material of the third filling structure 463 can be silicon oxide. Of course, the embodiments disclosed herein include, but are not limited to, other materials may also be used for the third filling structure.

[0118] Optionally, as shown in FIG26, the second filling structure 462 is removed to form a plurality of third deep holes 493 between adjacent second conductive structures 515.

[0119] Optionally, as shown in Figures 27 and 28, a plurality of third filling structures 463 are formed in the plurality of second conductive structures 515, and the second filling structure 462 between adjacent second conductive structures 515 is removed to form a third deep hole 493 between adjacent second conductive structures 515.

[0120] Optionally, as shown in FIG29, the portion of the second conductive layer 510 located at the bottom of the first deep hole 491 is removed, and the second conductive structure 515 passing through the plurality of first sacrificial layers 410 and the plurality of second sacrificial layers 420 has a cylindrical structure extending along the first direction, and each second conductive structure 515 has a conductive portion 5150 connected to the sacrificial structure 415.

[0121] Figure 30 is a schematic diagram of the steps of another semiconductor device fabrication method provided in an embodiment of the present disclosure; Figure 31 is a cross-sectional schematic diagram along line AA' in Figure 30; Figure 32 is a cross-sectional schematic diagram along line BB' in Figure 30; Figure 33 is a cross-sectional schematic diagram along line CC' in Figure 30; Figure 34 is a cross-sectional schematic diagram along line DD' in Figure 30.

[0122] As shown in Figure 30, the first insulating layer 471 is etched through the third deep hole 493 and multiple second conductive structures 515 as blocking structures. That is, the first insulating layer 471 is etched based on the multiple second conductive structures 515, thereby removing the first insulating layer 471. Then, the sacrificial structure 415 is etched through the third deep hole 493 and with multiple second conductive structures 515 as blocking structures to remove part of the sacrificial structure 415 and form multiple sacrificial portions 4150 arranged along the second direction.

[0123] As shown in Figure 31, during the etching process of the first insulating layer 471 and the sacrificial structure 415 through the third deep hole 493 and using multiple second conductive structures 515 as barrier structures, the second conductive structures 515 can act as barrier structures to protect the subsequently formed sacrificial part (semiconductor layer) from being removed by the etching process.

[0124] As shown in Figure 32, the second conductive structure 515, acting as a barrier structure, was not etched during the aforementioned etching process and maintained its cylindrical structure. However, if the third filling structure 463 in the second conductive structure 515 is made of the same material as the first insulating layer 471 or the sacrificial structure 415, the third filling structure 463 in the second conductive structure 515 will be partially etched away.

[0125] As shown in Figure 34, the sacrificial portion 4150 is arranged along the second direction; in subsequent processes, the sacrificial portion 4150 can be replaced by a semiconductor material to form a plurality of semiconductor layers arranged along the second direction.

[0126] As shown in Figure 34, during the etching process of the sacrificial structure 415 through the third deep hole 493 and with multiple second conductive structures 515 as blocking structures, the first sacrificial layer 410 located at the top layer is removed.

[0127] It should be noted that during the etching process of the first insulating layer 471 and the sacrificial structure 415 through the third deep hole 493 and using multiple second conductive structures 515 as blocking structures, the etched portion of the sacrificial structure 415 can subsequently form a containment structure, thereby facilitating the limitation of the area during the subsequent replacement of the sacrificial portion. Furthermore, the etched portion of the sacrificial structure can also enlarge the third deep hole, making it easier to etch the second conductive structure to form bit lines. Therefore, in the above steps, the cylindrical second conductive structure plays multiple roles, simplifying the process steps and reducing manufacturing costs.

[0128] In some examples, after etching the first insulating layer 471 through the third deep hole 493 and using multiple second conductive structures 515 as barrier structures, the burrs of the second conductive structures 515 can be removed by etching, making the structure formed by subsequent processes more stable and improving product yield.

[0129] Figure 35 is a schematic diagram of the steps of another semiconductor device fabrication method provided in an embodiment of the present disclosure; Figure 36 is a cross-sectional schematic diagram along line AA' in Figure 35; Figure 37 is a cross-sectional schematic diagram along line BB' in Figure 35; Figure 38 is a cross-sectional schematic diagram along line CC' in Figure 35; Figure 39 is a cross-sectional schematic diagram along line DD' in Figure 35.

[0130] As shown in Figure 35, after etching the sacrificial structure 415 with multiple second conductive structures 515 as barrier structures to remove part of the sacrificial structure 415, a second insulating layer 472 is deposited in the space left by the etched part of the sacrificial structure 415. The second insulating layer 472 is located between adjacent sacrificial portions 4150.

[0131] For example, the material of the second insulating layer 472 includes silicon oxide. Of course, the embodiments disclosed herein include, but are not limited to, other suitable insulating materials may also be used for the second insulating layer.

[0132] As shown in Figure 35, multiple second conductive structures 515 are etched, retaining multiple conductive portions 5150 of the multiple second conductive structures 515 to form multiple bit lines 220. The multiple bit lines 220 extend along a first direction and are spaced apart in a second direction. Since the second conductive structure 515 has a cylindrical structure, after etching the second conductive structure 515 from both sides, conductive portions 5150 extending along the first direction Z that contact the sacrificial portion 4150 can be left. In addition, during the above etching process, the second insulating layer 472 can also cover part of the outer surface of the second conductive structure 515, thereby making the etching process more controllable and facilitating the formation of the final bit lines.

[0133] As shown in Figure 36, a slit is formed between the second insulating layer 472 and the third filling structure 463. The slit makes the etching process of the second conductive structure 515 more controllable and is beneficial for forming bit lines.

[0134] As shown in Figure 37, the portion of the second conductive structure 515 located in the third deep hole 493 is removed.

[0135] As shown in FIG38, the conductive portion 5150 extends along a first direction Z perpendicular to the substrate 210 and is connected to a plurality of sacrificial portions 4150 stacked along the first direction Z.

[0136] As shown in Figure 39, due to the protection of the second insulating layer 472, a plurality of sacrificial portions 4150 are arranged along the second direction; in subsequent processes, the sacrificial portions 4150 can be replaced by semiconductor material, thereby forming a plurality of semiconductor layers arranged along the second direction.

[0137] Figure 40 is a schematic diagram of the steps of another semiconductor device fabrication method provided in an embodiment of the present disclosure; Figure 41 is a cross-sectional schematic diagram along line AA' in Figure 40; Figure 42 is a cross-sectional schematic diagram along line BB' in Figure 40; Figure 43 is a cross-sectional schematic diagram along line CC' in Figure 40; Figure 44 is a cross-sectional schematic diagram along line DD' in Figure 40.

[0138] As shown in Figure 40, after etching multiple second conductive structures 515 and retaining multiple conductive portions 5150 of the multiple second conductive structures 515 to form multiple bit lines 220, a fourth filling structure 464 is formed by filling multiple third deep holes 493.

[0139] For example, the material of the fourth filling structure 464 and the material of the second insulating layer 472 can be the same, both being silicon oxide. Of course, embodiments of this disclosure include, but are not limited to, this.

[0140] As shown in Figure 40, a second hard mask layer 482 is formed on the side of the plurality of first sacrificial layers 410, the plurality of second sacrificial layers 420, and the fourth filling structure 464 away from the substrate 210. Thus, the second hard mask layer 482 can form a top cover, thereby playing a protective role in subsequent etching processes.

[0141] As shown in Figure 40, the multiple second sacrificial layers 420 are laterally etched along the third direction from the side of the multiple second sacrificial layers 420 in the third direction to remove the multiple second sacrificial layers 420 and leave a first space at the location of the multiple second sacrificial layers 420.

[0142] As shown in Figure 41, a fourth filling structure 464 is formed by filling the third deep hole 493. The fourth filling structure 464 and the second insulating layer 472 form an isolation structure between the first storage structure and the second storage structure. The isolation structure can play a supporting role in the process of removing multiple second sacrificial layers.

[0143] As shown in Figure 42, the second hard mask layer 482 covers the entire fourth filler structure 464, thereby protecting the fourth filler structure 464 in subsequent etching processes.

[0144] As shown in Figure 43, after the multiple second sacrificial layers 420 are removed, a first space is left at the location where the multiple second sacrificial layers 420 were located, and the first space exposes the first conductive structure 455.

[0145] As shown in Figure 44, multiple sacrificial parts 4150 are spaced apart along the second direction.

[0146] Figure 45 is a schematic diagram of the steps of another semiconductor device fabrication method provided in an embodiment of the present disclosure; Figure 46 is a cross-sectional schematic diagram along line AA' in Figure 45; Figure 47 is a cross-sectional schematic diagram along line BB' in Figure 45; Figure 48 is a cross-sectional schematic diagram along line CC' in Figure 45; Figure 49 is a cross-sectional schematic diagram along line DD' in Figure 45.

[0147] As shown in Figure 45, the initial gate insulating layer and the first conductive structure 455 are etched through the first space to remove the second conductive portion 452 of the first conductive structure 455, so that the two first conductive portions 451 located on both sides of the sacrificial structure 415 in the first direction form word lines 230. These two first conductive portions 451 correspond to the two sub-word lines 232 of the word line 230.

[0148] As shown in Figure 46, the fourth filling structure 464 and the second insulating layer 472 form an isolation structure between the first storage structure 110A and the second storage structure 110B. The isolation structure can play a supporting role in the process of removing multiple second sacrificial layers and etching the first conductive structure.

[0149] As shown in Figure 47, the two first conductive portions 451 of the first conductive structure 455 are located on both sides of each sacrificial portion 4150 in the first direction, and thus can serve as word lines.

[0150] As shown in Figure 48, since the first conductive structure 455 is a structure formed in the groove of the second sacrificial layer, the first space left after removing the second sacrificial layer exposes the second conductive part 452 of the first conductive structure 455; by etching the first conductive structure 455 through the first space, the second conductive part 452 of the first conductive structure 455 can be removed.

[0151] As shown in Figure 49, the first space left by removing the second sacrificial layer makes the multiple first sacrificial layers 410 spaced apart.

[0152] Figure 50 is a schematic diagram of the steps of another semiconductor device fabrication method provided in an embodiment of the present disclosure; Figure 51 is a cross-sectional schematic diagram along line AA' in Figure 50; Figure 52 is a cross-sectional schematic diagram along line BB' in Figure 50; Figure 53 is a cross-sectional schematic diagram along line CC' in Figure 50; Figure 54 is a cross-sectional schematic diagram along line DD' in Figure 50.

[0153] As shown in Figure 50, a plurality of isolation structure layers 240 are formed by depositing insulating material in the first space; the plurality of isolation structure layers 240 are etched from the side of the plurality of isolation structure layers 240 in the third direction Y to expose the first sacrificial layer 410 in the adjacent isolation structure layers 240, thereby providing an etching window.

[0154] For example, the material of the isolation structure layer 240 can be silicon oxide. Of course, the embodiments disclosed herein include, but are not limited to, other materials that can be used for the isolation structure layer described above.

[0155] As shown in Figure 51, the fourth filling structure 464 and the second insulating layer 472 form an isolation structure between the first storage structure and the second storage structure, and the isolation structure can play a supporting role.

[0156] As shown in Figure 52, the two first conductive portions 451 of the first conductive structure 455 are located on both sides of each sacrificial portion 4150 in the first direction, and thus can serve as word lines.

[0157] As shown in Figure 53, multiple isolation structure layers 240 are located between multiple first sacrificial layers 410, and the multiple isolation structure layers 240 and multiple first sacrificial layers 410 are alternately disposed on the substrate 210.

[0158] As shown in Figure 54, multiple isolation structure layers 240 are also located between adjacent sacrificial portions 4150 in the first direction Z, thereby maintaining the stability of the space where the sacrificial portion is located during the subsequent replacement of the sacrificial portion with a semiconductor layer.

[0159] Figure 55 is a schematic diagram of the steps of another semiconductor device fabrication method provided in an embodiment of the present disclosure; Figure 56 is a cross-sectional schematic diagram along line AA' in Figure 55; Figure 57 is a cross-sectional schematic diagram along line BB' in Figure 55; Figure 58 is a cross-sectional schematic diagram along line CC' in Figure 55; Figure 59 is a cross-sectional schematic diagram along line DD' in Figure 55.

[0160] As shown in Figure 55, an etching process is used to remove multiple first sacrificial layers 410 to remove the sacrificial portion 4150. Semiconductor material is deposited in the second space left after the removal of the multiple first sacrificial layers 410. The semiconductor material is etched to expose the first electrode structure 531 (the formation process of the first electrode structure 531 will be described in detail in the relevant descriptions of Figures 69-72), leaving the semiconductor material in the space where the sacrificial portion 4150 is located, thereby forming a semiconductor layer 1244 in the space where the sacrificial portion 4150 is located. It should be noted that exposing the first electrode structure 531 is for forming a sandwich capacitor on the side.

[0161] As shown in Figure 56, the sacrificial portion 4150 is replaced by the semiconductor layer 1244. The first end 1244A of the semiconductor layer 1244 in the third direction Y parallel to the substrate 210 is connected to the first electrode structure 531, and the second end 1244B of the semiconductor layer 1244 in the third direction Y is connected to the bit line 220.

[0162] As shown in Figure 56, the semiconductor layer 1244 further includes a first protrusion 12441 and a second protrusion 12442 protruding outward in a second direction. The first protrusion 12441 includes a third end 1244C away from the line connecting the first end 1244A and the second end 1244B, and the second protrusion 12442 includes a fourth end 1244D away from the line connecting the first end 1244A and the second end 1244B. Because the semiconductor layer includes the aforementioned first and second protrusions, the effective width of the transistors in each memory cell is increased, thereby improving the channel width-to-length ratio and resulting in a larger on-state current.

[0163] In some examples, as shown in Figure 56, the distance between the third terminal 1244C and the fourth terminal 1244D is greater than the average width of the semiconductor layer 1244 in the second direction X, thereby increasing the effective width of the transistors in each memory cell.

[0164] In some examples, as shown in Figure 56, the edge of the orthographic projection of the semiconductor layer 1244 onto the substrate includes a first curve 301 and a second curve 302. The first curve 301 connects the second end 1244B and the third end 1244C of the semiconductor layer 1244, and the second curve 302 connects the second end 1244B and the fourth end 1244D of the semiconductor layer 1244. Thus, the semiconductor layer has relatively smooth edges, thereby improving transistor performance. Furthermore, the semiconductor layer is also easily formed using isotropic etching processes, saving on masking processes and reducing costs.

[0165] In some examples, as shown in FIG56, the first curve 301 and the second curve 302 may be symmetrical with respect to the line connecting the first terminal 1244A and the second terminal 1244B, thereby giving the transistor better symmetry. Of course, embodiments of this disclosure include, but are not limited to, this.

[0166] In some examples, the semiconductor layer 1244 described above can be made of an oxide semiconductor material, such as indium gallium zinc oxide (IGZO). This results in transistors in the memory cell having higher carrier mobility and lower leakage current. On the one hand, the memory cell can have a smaller volume, thereby further improving the integration density of the semiconductor device; on the other hand, the memory cell can have stronger performance. Of course, embodiments of this disclosure include, but are not limited to, other semiconductor materials can also be used for the semiconductor layer described above.

[0167] For example, the materials for the oxide semiconductor layer described above can also be indium tin oxide (ITO), indium tungsten oxide (IWO), or zinc oxide (ZnO). x Indium oxide (InO) x Indium tungsten oxide (InWO), tin oxide (SnO2), titanium oxide (TiO2) x ), Zinc oxide (Zn) x O y N z ), magnesium zinc oxide (Mg x Zn y O z Indium zinc oxide (In) x Zn y O z Zirconia indium zinc (Zr) x In y Zn z Oa ), Hafnium Indium Zinc Oxide (Hf) x In y Zn z O a ), tin indium zinc oxide (Sn x In y Zn z O a ), aluminum tin indium zinc (Al x Sn y In z Zn a O d ) and silicon indium zinc (Si x In y Zn z O a At least one of the following.

[0168] In some examples, the thickness of the semiconductor layer 1244 in the first direction ranges from 5 to 10 nanometers. This provides stronger control over the semiconductor layer by the word line, resulting in superior performance of the transistors in the memory cell.

[0169] As shown in Figure 57, in the space where each first sacrificial layer is located, multiple semiconductor layers 1244 are arranged along the second direction X, and each semiconductor layer 1244 has two sub-line 232 on both sides in the first direction Z.

[0170] As shown in Figure 58, the first end 1244A of the semiconductor layer 1244 in the third direction Y parallel to the substrate 210 is connected to the first electrode structure 531, and the second end 1244B of the semiconductor layer 1244 in the third direction Y is connected to the bit line 220.

[0171] As shown in Figure 59, after the removal of multiple first sacrificial layers 410, a second space is left, located between the multiple isolation structure layers 240 mentioned above.

[0172] Figure 60 is a schematic diagram of the steps of another semiconductor device fabrication method provided in an embodiment of the present disclosure; Figure 61 is a cross-sectional schematic diagram along line AA' in Figure 60; Figure 62 is a cross-sectional schematic diagram along line BB' in Figure 60; Figure 63 is a cross-sectional schematic diagram along line CC' in Figure 60; Figure 64 is a cross-sectional schematic diagram along line DD' in Figure 60.

[0173] As shown in Figure 60, a first dielectric layer 521 is deposited on the third-direction side of multiple isolation structure layers 240, and the first dielectric layer 521 is in contact with the exposed first electrode structure 531; a second electrode structure 532 is formed on the side of the first dielectric layer 521 away from the first electrode structure 531. Thus, the first electrode structure 531, the second electrode structure 532, and the first dielectric layer 521 located between the first electrode structure 531 and the second electrode structure 532 can form a capacitor. It should be noted that the aforementioned first electrode structure 531 can be the first electrode 1221 of the capacitor 122 mentioned above.

[0174] As shown in Figure 61, the first electrode structure 531 is connected to the first end 1244A of the semiconductor layer 1244, and a first dielectric layer 521 is disposed between the first electrode structure 531 and the second electrode structure 532.

[0175] As shown in Figure 61, the shape of the orthographic projection of the first electrode structure 531 onto the substrate 210 can be annular.

[0176] As shown in Figure 62, in the space where each first sacrificial layer is located, multiple semiconductor layers 1244 are arranged along the second direction X, and each semiconductor layer 1244 has two sub-line 232 on both sides in the first direction Z.

[0177] As shown in Figure 63, the first electrode structure 531, the second electrode structure 532, and the first dielectric layer 521 located between the first electrode structure 531 and the second electrode structure 532 can form a capacitor 122.

[0178] As shown in Figure 64, the second electrode structure 532 may include a first sub-electrode structure 532A and a second sub-electrode structure 532B; the first sub-electrode structure 532A is located between multiple adjacent isolation structure layers 240, and the second sub-electrode structure 532B is located on the third-direction side of the multiple isolation structures 240.

[0179] The formation process of the first electrode structure 531 will now be described by way of example. It is worth noting that the formation of the first electrode structure includes, but is not limited to, the process steps described below, and may also be formed using other process steps.

[0180] Figure 65 is a schematic diagram of the steps of another semiconductor device fabrication method provided in an embodiment of the present disclosure; Figure 66 is a cross-sectional view along line AA' in Figure 65; Figure 67 is a cross-sectional view along line BB' in Figure 65; Figure 68 is a cross-sectional view along line CC' in Figure 65.

[0181] As shown in Figure 65, before forming the first deep trench 431 among the plurality of first sacrificial layers 410 and the plurality of second sacrificial layers 420, a fourth deep hole 494 is formed among the plurality of first sacrificial layers 410 and the plurality of second sacrificial layers 420. The plurality of first sacrificial layers 410 are etched through the fourth deep hole 494 to form a plurality of second grooves 417 recessed into the fourth deep hole 494.

[0182] As shown in Figure 66, the orthographic projection of each fourth deep hole 494 onto the substrate 210 can be elliptical. Of course, embodiments of this disclosure include, but are not limited to, other shapes, such as circles, rounded rectangles, etc., can also be formed by the orthographic projection of each fourth deep hole onto the substrate.

[0183] As shown in Figures 67 and 68, each of the second grooves 417 is recessed from the side wall of the fourth deep hole 494.

[0184] Figure 69 is a schematic diagram of the steps of another semiconductor device fabrication method provided in an embodiment of the present disclosure; Figure 70 is a cross-sectional schematic diagram along line AA' in Figure 69; Figure 71 is a cross-sectional schematic diagram along line BB' in Figure 69; Figure 72 is a cross-sectional schematic diagram along line CC' in Figure 69.

[0185] As shown in Figure 69, a third conductive layer 540 is deposited on the sidewalls of the fourth deep hole 494 and the plurality of second grooves 417. The third conductive layer 540 includes a fourth conductive portion 544 located in each of the second grooves 417 and a fifth conductive portion (not shown) located between adjacent second grooves 417. A fifth filling structure 465 is filled in the fourth deep hole 494 and the plurality of second grooves 417. The fifth filling structure 465 is etched to remove the fifth filling structure 465 in the fourth deep hole 494, while retaining the fifth filling structure 465 in the plurality of second grooves 417 and exposing the fifth conductive portion. The fifth conductive portion is removed so that adjacent fourth conductive portions 544 are disconnected to form the first electrode structure 531 described above.

[0186] As shown in Figure 70, the fifth filling structure 465 in the fourth deep hole 494 is removed, while the fifth filling structure 465 in the multiple second grooves 417 is retained.

[0187] As shown in Figures 71 and 72, the fifth filling structure 465 retained in the plurality of second grooves 417 can protect the fourth conductive part 544 from being removed during the etching process.

[0188] In some examples, as shown in Figures 71 and 72, a protective film 470 may be formed on the inner surfaces of the fourth deep hole 494 and the second groove 417, thereby protecting the inner surfaces of the fourth deep hole 494 and the second groove 417 in subsequent processes and improving product yield. Of course, embodiments of this disclosure include, but are not limited to, the formation of the aforementioned protective film 470 is not required.

[0189] Figure 73 is a schematic diagram of the steps of another semiconductor device fabrication method provided in an embodiment of the present disclosure; Figure 74 is a cross-sectional schematic diagram along line AA' in Figure 73; Figure 75 is a cross-sectional schematic diagram along line BB' in Figure 73; Figure 76 is a cross-sectional schematic diagram along line CC' in Figure 73.

[0190] As shown in Figure 73, the fourth deep hole 494 is filled again to form the sixth filling structure 466, and then the first deep trench mentioned above is formed.

[0191] As shown in Figures 74-76, the sixth filling structure 466 fills the fourth deep hole 494. For example, the material of the sixth filling structure 466 can be the same as the material of the fifth filling structure 465.

[0192] For example, the materials of the sixth filling structure 466 and the fifth filling structure 465 can both be polycrystalline silicon. Of course, embodiments of this disclosure include, but are not limited to, this.

[0193] Figure 77 is a schematic diagram of the steps of another semiconductor device fabrication method provided in an embodiment of the present disclosure; Figure 78 is a cross-sectional schematic diagram along line AA' in Figure 77; Figure 79 is a cross-sectional schematic diagram along line BB' in Figure 77; Figure 80 is a cross-sectional schematic diagram along line CC' in Figure 77.

[0194] As shown in Figure 77, after the fourth deep hole 494 is filled with the sixth filling structure 466, the sixth filling structure 466 and the remaining fifth filling structure 465 can be removed after the second electrode structure 532 of the capacitor is formed, thereby exposing the inner wall of the first electrode structure 531.

[0195] As shown in Figure 77, a second dielectric layer 522 is deposited on the side of the first electrode structure 531 away from the semiconductor layer 1244, and a third electrode structure 533 is formed on the side of the second dielectric layer 522 away from the first electrode structure 531, thereby forming a sandwich capacitor 122. The sandwich capacitor 122 has a large capacitance in a small space. It should be noted that when the capacitor 122 is a sandwich capacitor, the second electrode 1222 can be the second electrode structure 532, the third electrode structure 533, or both.

[0196] As shown in Figures 78-80, a first dielectric layer 521 is disposed on the outer side of the first electrode structure 531, and a second dielectric layer 522 is disposed on the inner side of the first electrode structure 531; thus, a sandwich capacitor 122 can be formed by the first electrode structure 531, the first dielectric layer 521, the second electrode structure 532, the second dielectric layer 522, and the third electrode structure 533. Alternatively, the sandwich capacitor 122 includes one first electrode structure and two second electrode structures.

[0197] At least one embodiment of this disclosure also provides an electronic device. FIG81 is a schematic diagram of a display device provided in an embodiment of this disclosure. As shown in FIG81, the electronic device 800 includes the semiconductor device 200 described above. Thus, the electronic device also has beneficial effects corresponding to the beneficial effects of the included semiconductor device. For example, since the semiconductor device has a high degree of integration and avoids the generation of large parasitic capacitors, the electronic device can have a high degree of integration and strong storage performance.

[0198] In some examples, the aforementioned electronic devices may be desktop computers, laptops, smartphones, tablets, artificial intelligence devices, wearable smart devices, navigators, electronic picture frames, etc.

[0199] The following points need to be explained:

[0200] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure, and other structures can be referred to the general design.

[0201] (2) Where there is no conflict, features of the same embodiment and different embodiments of this disclosure may be combined with each other.

[0202] The above description is merely an exemplary embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure, which is determined by the appended claims.

Claims

1. A semiconductor device, comprising: Multiple storage structure layers are stacked along a first direction perpendicular to the substrate; Bit lines extend along the first direction; as well as The character line extends along a second direction parallel to the substrate, the second direction being perpendicular to the first direction; Wherein, each of the memory structure layers includes at least one memory structure, each memory structure includes a plurality of memory cells arranged sequentially along the second direction, each memory cell includes a capacitor and a transistor, the capacitor includes a first electrode, and the transistor includes a semiconductor layer; In each of the memory cells, the semiconductor layer is connected to the first electrode of the capacitor at a first end in a third direction parallel to the substrate, and the semiconductor layer is connected to the bit line at a second end in the third direction, the third direction intersecting the second direction; The word line includes two sub-word lines spaced apart in the first direction, and the semiconductor layers of the plurality of memory cells spaced apart in the second direction in each of the memory structures are sandwiched between the two sub-word lines.

2. The semiconductor device according to claim 1, wherein, The semiconductor layer is an oxide semiconductor layer.

3. The semiconductor device according to claim 1, wherein, The thickness of the semiconductor layer along the first direction ranges from 5 to 10 nm.

4. The semiconductor device according to claim 1, wherein, The semiconductor device includes a plurality of bit lines spaced apart along the second direction. The plurality of memory cells of each memory structure are respectively connected to the plurality of bit lines. Each bit line is connected to the second end of the semiconductor layer of the plurality of memory cells arranged along the first direction in the plurality of memory structure layers.

5. The semiconductor device according to any one of claims 1-4, wherein, In each of the memory cells, the semiconductor layer further includes a first protrusion and a second protrusion that protrude outward in the second direction. The first protrusion includes a third end that is away from the line connecting the first end and the second end, and the second protrusion includes a fourth end that is away from the line connecting the first end and the second end.

6. The semiconductor device according to claim 5, wherein, The edge of the orthogonal projection of the semiconductor layer on the substrate includes a first curve and a second curve, the first curve connecting the second end and the third end of the semiconductor layer, and the second curve connecting the second end and the fourth end of the semiconductor layer.

7. The semiconductor device according to claim 5, wherein, The distance between the third end and the fourth end is greater than the average width of the semiconductor layer in the second direction.

8. The semiconductor device according to any one of claims 1-4, wherein, In each of the memory cells, the transistor further includes two gate insulating layers, respectively located between the semiconductor layer and the two sub-word lines.

9. The semiconductor device according to any one of claims 1-4, wherein, The capacitor includes two second electrodes and one first electrode, with the first electrode located between the two second electrodes. The capacitor further includes a first dielectric layer and a second dielectric layer, which are located between the first electrode and the two second electrodes, respectively.

10. The semiconductor device according to claim 9, wherein, In each of the capacitors, the first electrode has a ring-shaped orthogonal projection onto the substrate, one of the two second electrodes is located inside the first electrode, and the other of the two second electrodes is located outside the first electrode.

11. The semiconductor device according to claim 10, wherein, The shape of the orthographic projection of the first electrode onto the substrate is an elliptical ring.

12. A method for fabricating a semiconductor device, comprising: A plurality of first sacrificial layers and a plurality of second sacrificial layers are alternately arranged on the substrate along a first direction perpendicular to the substrate; A first deep trench is formed in the plurality of first sacrificial layers and the plurality of second sacrificial layers, and the plurality of second sacrificial layers are etched through the first deep trench to form a sacrificial structure in each of the first sacrificial layers; A first conductive structure and a first electrode structure are formed, wherein the first conductive structure includes two first sub-conductive structures spaced apart in the first direction, the two first sub-conductive structures being located on both sides of the sacrificial structure in the first direction and both extending along a second direction parallel to the substrate; the first electrode structure is located on the side of the sacrificial structure in a third direction parallel to the substrate and is connected to the sacrificial structure; the second direction and the third direction are both perpendicular to the first direction, and the third direction intersects the second direction. A bit line extending along the first direction is formed on the substrate, and the sacrificial structure is etched to form a plurality of sacrificial portions, wherein the sacrificial portion is connected to the first electrode structure at a first end in the third direction and to the bit line at a second end in the third direction. The plurality of second sacrificial layers are removed, and the first conductive structure is etched to form word lines, wherein the two first sub-conductive structures of the first conductive structure form two sub-word lines; After the removal of the plurality of second sacrificial layers, a plurality of isolation structure layers are formed in the first space remaining therefrom; the sacrificial portion is removed; and a semiconductor layer is formed in the space where the sacrificial portion is located; and A capacitor is formed in the layer containing the first sacrificial layer, with the first electrode structure serving as the first electrode, to form a storage structure layer including the capacitor and the semiconductor layer.

13. The method for fabricating a semiconductor device according to claim 12, wherein, Forming bit lines extending along the first direction on the substrate and etching the sacrificial structure to form a plurality of sacrificial portions includes: A plurality of second conductive structures are formed passing through the plurality of first sacrificial layers and the plurality of second sacrificial layers, each second conductive structure having a cylindrical structure extending along the first direction, and each second conductive structure having a conductive portion connected to the sacrificial structure; The sacrificial structure is etched based on the plurality of second conductive structures to remove a portion of the sacrificial structure and form the plurality of sacrificial portions arranged along the second direction; and The plurality of second conductive structures are etched to retain the plurality of conductive portions of the plurality of second conductive structures to form a plurality of bit lines, the plurality of bit lines extending along a first direction and spaced apart in a second direction.

14. The method for fabricating a semiconductor device according to claim 12 or 13, wherein, Forming a first deep trench among the plurality of first sacrificial layers and the plurality of second sacrificial layers, and etching the plurality of second sacrificial layers through the first deep trench to form a sacrificial structure in each of the first sacrificial layers includes: The first deep trench is formed in the plurality of first sacrificial layers and the plurality of second sacrificial layers, and the first deep trench extends along the first direction and the second direction; The plurality of second sacrificial layers are laterally etched through the first deep trench to form a plurality of first grooves in each of the second sacrificial layers that extend along the second direction and are spaced apart in the first direction. The first sacrificial layer between two adjacent first grooves forms a sacrificial structure.

15. The method for fabricating a semiconductor device according to claim 14, wherein, The formation of the first conductive structure and the first electrode structure includes: An initial gate insulating layer and a first conductive layer are deposited on the surfaces of the first deep trench and the first groove. The first conductive layer includes a first conductive portion located on the two sidewalls of the first groove, a second conductive portion located at the bottom of the first groove, and a third conductive portion located near the center of the sacrificial structure near the first deep trench. A first filling structure is filled into the first deep trench and the first groove; The first filling structure is etched to form a second deep trench to expose the third conductive portion; By etching and removing the third conductive portion and the exposed initial gate insulating layer through the second deep trench, the two first conductive portions located on both sides of the sacrificial structure in the first direction are disconnected, and the first conductive structure is formed.

16. The method for fabricating a semiconductor device according to claim 15, wherein, The formation of the first conductive structure and the first electrode structure further includes: After the first groove is formed, the sacrificial structure located between two adjacent first grooves is thinned by an etching process.

17. The method for fabricating a semiconductor device according to claim 16, wherein, The thickness of the thinned sacrificial structure in the first direction ranges from 5 to 10 nanometers.

18. The method for fabricating a semiconductor device according to claim 15, wherein, The formation of the plurality of second conductive structures passing through the plurality of first sacrificial layers and the plurality of second sacrificial layers includes: A first insulating layer is deposited on the sidewall of the second deep trench; A second filling structure is filled in the second deep trench where the first insulating layer is formed; A first hard mask layer is formed on the side of the plurality of first sacrificial layers, the plurality of second sacrificial layers, and the second filling structure away from the substrate; A plurality of first deep holes are formed in the first hard mask layer and the second filling structure, each first deep hole passing through the plurality of first sacrificial layers and the plurality of second sacrificial layers. The plurality of first deep holes are spaced apart in the second direction, wherein each first deep hole exposes the sacrificial structure on both sides along the third direction; and A second conductive layer is deposited inside the plurality of first deep holes, and the portion of the second conductive layer located at the bottom of the plurality of first deep holes is etched away to form the plurality of second conductive structures.

19. The method for fabricating a semiconductor device according to claim 18, wherein, The formation of a plurality of first deep holes in the first hard mask layer and the second filling structure includes: A plurality of second deep holes extending along a first direction and spaced apart in a second direction are formed in the first hard mask layer and the second filling structure using an etching process; and An etching process is used to etch the second filling structure and the first insulating layer through the plurality of second deep holes, widening the width of the second deep holes and exposing the sacrificial structure to form the plurality of first deep holes.

20. The method for fabricating a semiconductor device according to claim 18, wherein, Before etching the sacrificial structure based on the plurality of second conductive structures to remove a portion of the sacrificial structure, the process of forming a plurality of bit lines extending along the first direction on the substrate and etching the sacrificial structure to form a plurality of sacrificial portions further includes: A plurality of third filling structures are formed by filling the plurality of second conductive structures with insulating material. Remove the first hard mask layer; Remove the second filling structure to form a plurality of third deep holes between adjacent second conductive structures; and The first insulating layer is etched through the third deep hole and the plurality of second conductive structures.

21. The method for fabricating a semiconductor device according to claim 20, wherein, After etching the sacrificial structure based on the plurality of second conductive structures to remove a portion of the sacrificial structure, the process of forming a plurality of bit lines extending along the first direction on the substrate and etching the sacrificial structure to form a plurality of sacrificial portions further includes: A second insulating layer is deposited in the space left by the etched portion of the sacrificial structure. The second insulating layer is located between adjacent sacrificial portions.

22. The method for fabricating a semiconductor device according to claim 21, wherein, The step of removing the plurality of second sacrificial layers and etching the first conductive structure to form word lines includes: A fourth filling structure is formed by filling the plurality of third deep holes; A second hard mask layer is formed on the side of the plurality of first sacrificial layers, the plurality of second sacrificial layers, and the fourth filling structure away from the substrate; and The plurality of second sacrificial layers are etched from the third-direction side of the plurality of second sacrificial layers to remove the plurality of second sacrificial layers and leave the first space at the location of the plurality of second sacrificial layers; The first conductive structure is etched through the first space to remove the second conductive portion, so that the two first conductive portions located on both sides of the sacrificial structure in the first direction form word lines.

23. The method for fabricating a semiconductor device according to claim 22, wherein, The process of forming multiple isolation structure layers in the first space left after the removal of the multiple second sacrificial layers, removing the sacrificial portion, and forming a semiconductor layer in the space where the sacrificial portion is located includes: Multiple isolation structure layers are deposited in the first space; The plurality of isolation structure layers are etched from the third-party-oriented side to expose the first sacrificial layer in the adjacent isolation structure layers; The sacrificial portion is removed by etching a process to remove multiple first sacrificial layers. Semiconductor material is deposited in the second space left after the plurality of first sacrificial layers are removed; The semiconductor material is etched to expose the first electrode structure and leave the semiconductor material in the space where the sacrificial part is located, thereby forming a semiconductor layer in the space where the sacrificial part is located.

24. The method for fabricating a semiconductor device according to claim 23, wherein, Forming a capacitor in the layer containing the first sacrificial layer includes: A first dielectric layer is deposited on the third-side orientation of the plurality of isolation structure layers, wherein the first dielectric layer is disposed in contact with the exposed first electrode structure; A second electrode structure is formed on the side of the first dielectric layer away from the first electrode structure.

25. The method for fabricating a semiconductor device according to claim 24, wherein, Also includes: Before forming a first deep trench in the plurality of first sacrificial layers and the plurality of second sacrificial layers, a fourth deep hole is formed in the plurality of first sacrificial layers and the plurality of second sacrificial layers; The plurality of first sacrificial layers are etched through the fourth deep hole to form a plurality of second grooves recessed from the fourth deep hole; A third conductive layer is deposited on the sidewalls of the fourth deep hole and the plurality of second grooves, the third conductive layer comprising a fourth conductive portion located within each of the second grooves and a fifth conductive portion located between adjacent second grooves; A fifth filling structure is filled into the fourth deep hole and the plurality of second grooves; The fifth filling structure is etched to remove the fifth filling structure in the fourth deep hole, while retaining the fifth filling structure in the plurality of second grooves, and exposing the fifth conductive portion; The fifth conductive portion is removed, thereby disconnecting the adjacent fourth conductive portion to form the first electrode structure.

26. The method for manufacturing a semiconductor device according to claim 25, further comprising: The fourth deep hole is filled again to form a sixth filling structure, wherein forming a capacitor in the layer containing the first sacrificial layer further includes: Remove the sixth filling structure; A second dielectric layer is deposited on the side of the first electrode structure away from the semiconductor layer; A third electrode structure is formed on the side of the second dielectric layer away from the first electrode structure.

27. An electronic device, wherein, The semiconductor device includes any one of claims 1-11, or a semiconductor device formed by a method of manufacturing a semiconductor device according to any one of claims 12-26.

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