Charge pump circuit and charge pump system

Abstract

A charge pump circuit and a charge pump system. The charge pump circuit comprises: a comparison unit, which is adapted to receive a reference signal and a voltage-divided signal and compare the reference signal with the voltage-divided signal, so as to obtain a feedback signal; a signal processing unit, which is connected to the comparison unit and is adapted to receive the feedback signal and process the feedback signal, so as to obtain a processed feedback signal; a driving unit, which is connected to the signal processing unit and is adapted to receive a clock signal and the processed feedback signal and perform a NOR operation on the clock signal and the processed feedback signal, so as to obtain a driving signal; and a charge pump unit, which is connected to the driving unit and is adapted to receive the driving signal and turn on or off under the control of the driving signal. By adjusting the feedback signal by means of the signal processing unit, a processed feedback signal with an increased duty cycle can be obtained, thereby improving the boost performance of the charge pump.

Description

Charge pump circuit and charge pump system

[0001] This application claims priority to Chinese Patent Application No. 202411567733.3, filed on November 4, 2024, entitled “Charge Pump Circuit and Charge Pump System”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This invention relates to the field of semiconductor manufacturing, and more particularly to a charge pump circuit and a charge pump system. Background Technology

[0003] A charge pump circuit is a device used for voltage conversion, which can realize voltage transformation, such as boost, buck, and inversion.

[0004] Charge pump circuits boost voltage by charging and discharging capacitors through switches. Since charge pump circuits do not have inductors for energy storage and have weak driving capabilities, they can be used in low-current applications and are therefore often used in flash memory for voltage conversion.

[0005] However, current charge pump circuits have poor boost performance. Summary of the Invention

[0006] The technical problem solved by this invention is how to improve the boost performance of a charge pump circuit.

[0007] To address the aforementioned technical problems, embodiments of the present invention provide a charge pump circuit, comprising:

[0008] The comparison unit is adapted to receive a reference signal and a voltage divider signal, and compare the reference signal and the voltage divider signal to obtain a feedback signal;

[0009] A signal processing unit, connected to the comparison unit, is adapted to receive the feedback signal and process the feedback signal to obtain a processed feedback signal, wherein the duty cycle of the processed feedback signal is greater than the duty cycle of the original feedback signal.

[0010] A driving unit, connected to the signal processing unit, is adapted to receive a clock signal and a processed feedback signal, and to perform a NOR operation on the clock signal and the processed feedback signal to obtain a driving signal.

[0011] And a charge pump unit, connected to the drive unit, adapted to receive the drive signal and to be turned on or off under the control of the drive signal;

[0012] During the period when the clock signal is in the second level state, the processed feedback signal remains in the first level state; the first level state and the second level state are logically opposite.

[0013] Optionally, the signal processing unit is further adapted to receive a processing signal and perform delay processing on the feedback signal based on the processing signal to obtain the processed feedback signal.

[0014] Optionally, the processed feedback signal is synchronized with the clock signal.

[0015] Optionally, the signal processing unit includes: a pulse signal generation module connected to the comparison unit, adapted to receive the processing signal and generate a pulse signal according to the processing signal; and a sampling module connected to the pulse signal generation module, adapted to receive the feedback signal and the pulse signal, and sample the feedback signal according to the pulse signal to obtain the processed feedback signal synchronized with the clock signal.

[0016] Optionally, the pulse signal generation module includes: a first submodule, adapted to receive the processing signal and process the rising edge of the processing signal to obtain a first subpulse signal; a second submodule, connected in parallel with the first submodule, adapted to receive the processing signal and process the falling edge of the processing signal to obtain a second subpulse signal; and a merging submodule, connected to the first submodule and the second submodule, adapted to receive the first subpulse signal and the second subpulse signal and merge the first subpulse signal and the second subpulse signal to obtain the pulse signal.

[0017] Optionally, the first submodule includes: a first inverter, a first delay unit, and a first NOR gate; wherein: the input terminal of the first inverter is adapted to receive the processed signal, and the output terminal of the first inverter is connected to the input terminal of the first delay unit; the output terminal of the first delay unit is connected to the second input terminal of the first NOR gate; the first input terminal of the first NOR gate is adapted to receive the processed signal, and the output terminal of the first NOR gate is adapted to output a first sub-pulse signal.

[0018] Optionally, the second submodule includes: a second inverter, a second delay unit, and a second NOR gate; wherein: the input terminal of the second inverter is adapted to receive the processed signal, and the output terminal of the second inverter is connected to the input terminal of the second delay unit; the output terminal of the second delay unit is connected to the second input terminal of the second NOR gate; the first input terminal of the second NOR gate is adapted to receive the processed signal, and the output terminal of the second NOR gate is adapted to output a second sub-pulse signal.

[0019] Optionally, the merging submodule includes: a third NOR gate; the first input terminal of the third NOR gate is adapted to receive the first sub-pulse signal, the second input terminal of the third NOR gate is adapted to receive the second sub-pulse signal, and the output terminal of the third NOR gate is adapted to output the pulse signal.

[0020] Optionally, the sampling module includes: a trigger; the first input terminal of the trigger is adapted to receive the feedback signal, the second input terminal of the trigger is adapted to receive a pulse signal, and the output terminal of the trigger is adapted to output the synchronously processed feedback signal.

[0021] Optionally, the driving unit includes: a fourth NOR gate and a third inverter; wherein: the first input terminal of the fourth NOR gate is adapted to receive the clock signal, the second input terminal of the fourth NOR gate is adapted to receive the processed feedback signal, the output terminal of the fourth NOR gate is connected to the input terminal of the third inverter; and the output terminal of the third inverter is connected to the charge pump unit.

[0022] Optionally, the comparison unit includes: a comparator; a first input terminal of the comparator is adapted to receive a reference signal, a second input terminal of the comparator is adapted to receive a voltage divider signal, and an output terminal of the comparator is adapted to output a feedback signal.

[0023] Optionally, the charge pump circuit further includes a voltage divider circuit connected to the second input terminal of the comparator, adapted to generate a voltage divider signal.

[0024] Optionally, the charge pump circuit further includes a reference circuit connected to the first input terminal of the comparator, adapted to generate a reference signal.

[0025] Accordingly, the present invention also provides a charge pump system, including multiple cascaded charge pump circuits as described above, each charge pump circuit including an input terminal and an output terminal, wherein the output terminal of the previous stage charge pump circuit is connected to the input terminal of the next stage charge pump circuit.

[0026] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0027] In this invention, a signal processing unit is added to the charge pump circuit. This unit adjusts the feedback signal to obtain a processed feedback signal with an increased duty cycle. Since the processed feedback signal remains at the first level while the clock signal is in the second level state, the drive signal can keep the charge pump unit in the on state and perform boost processing until a preset voltage value is reached during the second level state. This prevents the charge pump unit from switching off due to changes in the processed feedback signal state, which would reduce the boost time and prevent the preset voltage value from being reached. Therefore, the boost performance of the charge pump is improved.

[0028] Furthermore, since the processed feedback signal is synchronized with the clock signal, the duration of the clock signal in the second level state is equal to the duration of the processed feedback signal in the first level state. This reduces the power consumption increase caused by the processed feedback signal remaining in the first level state for too long, thereby minimizing the power consumption of the charge pump. Attached Figure Description

[0029] Figure 1 is a schematic diagram of a charge pump circuit;

[0030] Figure 2 is a timing diagram of a portion of the signals in a charge pump circuit;

[0031] Figure 3 is a schematic diagram of a charge pump circuit according to an embodiment of the present invention;

[0032] Figure 4 is a schematic diagram of another charge pump circuit in an embodiment of the present invention;

[0033] Figure 5 is a timing diagram of a portion of the signals in a charge pump circuit according to an embodiment of the present invention;

[0034] Figure 6 is a schematic diagram of a charge pump circuit in an embodiment of the present invention when the clock signal and the processed feedback signal are synchronized.

[0035] Figure 7 is a schematic diagram of another charge pump circuit in an embodiment of the present invention when the clock signal and the processed feedback signal are synchronized.

[0036] Figure 8 is a schematic diagram of another charge pump circuit in an embodiment of the present invention when the clock signal and the processed feedback signal are synchronized.

[0037] Figure 9 is a timing diagram of a portion of the charge pump circuit signals in another embodiment of the present invention;

[0038] Figure 10 is a schematic diagram of a charge pump system according to an embodiment of the present invention. Detailed Implementation

[0039] The current charge pump circuit has poor boost performance, which reduces the boost performance of the charge pump circuit.

[0040] Figure 1 is a schematic diagram of a charge pump circuit. Referring to Figure 1, the charge pump circuit includes: a comparator 11, adapted to receive a reference signal VREF and a voltage divider signal VDET, and compare the reference signal VREF and the voltage divider signal VDET to obtain a feedback signal F1; a drive unit 12, connected to the comparator 11, adapted to receive the feedback signal F1 and a clock signal CLK, and output a drive signal based on the feedback signal F1 and the clock signal CLK; and a charge pump unit 13, connected to the drive unit 12, adapted to receive the drive signal D1, and turn it on or off according to the drive signal D1.

[0041] Figure 2 is a timing diagram of the signals in the charge pump circuit described above.

[0042] In the above scheme, the boost performance of the charge pump unit is poor. Specifically, referring to Figure 2, between time t1 and t3, the feedback signal F1 is low, and between time t1 and t2, the clock signal CLK is high. It can be seen that the time the feedback signal F1 is low is shorter than the time the clock signal CLK is high. Since the feedback signal F1 is low when the clock signal CLK is high, the drive signal D1 can also be high during the high clock signal CLK period, thus keeping the charge pump unit in the on state and performing boost processing to reach the preset voltage value. However, in this scheme, the feedback signal F1 changes from low to high at time t3, causing the drive signal D1 to change from high to low at time t3. This results in the drive signal D1 prematurely turning off the charge pump unit at time t3, causing the charge pump unit to change from the on state to the off state. Consequently, the boost time of the charge pump unit is reduced, failing to reach the preset voltage value, thus reducing the boost performance of the charge pump unit.

[0043] To address the aforementioned technical problems, this invention provides a charge pump circuit. By placing a signal processing unit between a comparator unit and a drive unit, the signal processing unit adjusts the feedback signal, increasing its duty cycle and thus extending the time the feedback signal remains in a first-level state. During the second-level state of the clock signal, the processed feedback signal remains in the first-level state. The drive signal can then activate the charge pump unit during the second-level state of the clock signal and perform boost processing until a preset voltage value is reached. This prevents the charge pump unit from switching off due to changes in the processed feedback signal state, which would reduce the boost time and prevent the preset voltage value from being reached. Therefore, the boost performance of the charge pump is improved.

[0044] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0045] Referring to Figure 3, an embodiment of the present invention proposes a charge pump circuit, the charge pump circuit comprising:

[0046] The comparison unit 21 is adapted to receive the reference signal VREF and the voltage divider signal VDET, and compare the reference signal VREF and the voltage divider signal VDET to obtain the feedback signal F1;

[0047] The signal processing unit 22 is connected to the comparison unit 21 and is adapted to receive the feedback signal F1 and process the feedback signal F1 to obtain the processed feedback signal F2, wherein the duty cycle of the processed feedback signal F2 is greater than the duty cycle of the feedback signal F1.

[0048] The driving unit 23 is connected to the signal processing unit 22 and is adapted to receive the clock signal CLK and the processed feedback signal F2, and to perform a NOR operation on the clock signal CLK and the processed feedback signal F2 to obtain the driving signal D1.

[0049] And a charge pump unit 24, connected to the drive unit 23, adapted to receive the drive signal D1, and to be turned on or off under the control of the drive signal D1;

[0050] During the period when the clock signal CLK is in the second level state, the processed feedback signal F2 remains in the first level state; the first level state and the second level state are logically opposite.

[0051] In one embodiment, the first level state is low level and the second level state is high level.

[0052] In another embodiment, the first level state is high and the second level state is low.

[0053] In some embodiments of the present invention, the signal processing unit 22 is further adapted to receive a processing signal and perform delay processing on the feedback signal F1 based on the processing signal to obtain the processed feedback signal F2.

[0054] In a specific embodiment, the signal processing unit 22 can perform various logical operations on the feedback signal F1 and the processing signal to obtain the processed feedback signal F2, such as NOR operation, NAND operation, OR operation and AND operation, etc., which can be set as needed.

[0055] In one embodiment of the present invention, the driving unit 23 can perform a NOR operation on the clock signal CLK and the processed feedback signal F2 to obtain the driving signal D1.

[0056] The duty cycle of the processed feedback signal F2 is the ratio of the time the processed feedback signal F2 is in the first level state to the total time of the cycle within one period; the duty cycle of the feedback signal F1 is the ratio of the time the feedback signal F1 is in the first level state to the total time of the cycle within one period.

[0057] In one embodiment, the duty cycle of the processed signal is greater than the duty cycle of the clock signal CLK.

[0058] The duty cycle of the processing signal is the ratio of the time the processing signal is in the second level state to the total time of the cycle within one period; the duty cycle of the clock signal CLK is the ratio of the time the clock signal CLK is in the second level state to the total time of the cycle within one period.

[0059] Therefore, the time during which the processed feedback signal F2 is in the first level state is longer than the time during which the feedback signal is in the first level state. Furthermore, during the period when the clock signal CLK is in the second level state, the processed feedback signal F2 remains in the first level state. This ensures that during the period when the clock signal CLK is in the second level state, the drive signal D1 can drive the charge pump unit to remain in the on state, without the charge pump unit changing from the on state to the off state due to the change in the state of the processed feedback signal F2. This would prevent the boost time of the charge pump unit from being reduced and the preset voltage value not being reached, thereby improving the boost performance of the charge pump.

[0060] In one embodiment of the present invention, referring to FIG4, the comparison unit may be a comparator COMP, the first input terminal of the comparator COMP is adapted to receive a reference signal VREF, the second input terminal of the comparator COMP is adapted to receive a voltage divider signal VDET, and the output terminal of the comparator COMP is adapted to output a feedback signal F1.

[0061] In one embodiment, the comparator COMP further includes a power supply voltage terminal VCC and a ground terminal GND. The power supply voltage terminal VCC is adapted to pull up the output terminal of the comparator COMP to a high level, and the ground terminal GND is adapted to pull down the output terminal of the comparator COMP to a low level.

[0062] In a specific embodiment, the comparator COMP is adapted to compare the reference voltage and the voltage divider, outputting a feedback signal at a first level when the voltage divider is less than the reference voltage, and outputting a feedback signal at a second level when the voltage divider is greater than the reference voltage.

[0063] In one embodiment, the driving unit 23 includes: a fourth NOR gate NOR4 and a third inverter INV3; wherein:

[0064] The first input terminal of the fourth NOR gate NOR4 is adapted to receive the clock signal CLK, the second input terminal of the fourth NOR gate NOR4 is adapted to receive the processed feedback signal F2, the output terminal of the fourth NOR gate NOR4 is connected to the input terminal of the third inverter INV3, and the output terminal of the third inverter INV3 is connected to the charge pump unit 24.

[0065] In one embodiment, the charge pump circuit further includes: a voltage divider circuit connected to the second input terminal of the comparator COMP, adapted to generate a voltage divider signal VDET; and a reference circuit connected to the first input terminal of the comparator COMP, adapted to generate a reference signal VREF.

[0066] The voltage divider signal is generated by a voltage divider circuit. Specifically, the voltage divider signal can be a voltage divider signal.

[0067] The reference signal is generated by a comparator. Specifically, the reference signal can be a reference voltage signal.

[0068] The comparison unit can generate a feedback signal by comparing the voltage of the voltage divider signal and the reference signal. The feedback signal can be a continuous square wave signal.

[0069] In a specific embodiment, the comparison unit can control the feedback signal to a first level state when the voltage divider is less than the reference voltage, and control the feedback signal to a second level state when the voltage divider is greater than the reference voltage, thereby obtaining a continuous square wave signal F1.

[0070] In a specific embodiment, the voltage divider circuit may include: a first resistor R1 and a second resistor R2. The charge pump includes an output terminal. The first terminal of the first resistor R1 is connected to the output terminal OUT of the charge pump, which is suitable for inputting the output voltage of the charge pump. The second terminal of the first resistor R1 is connected to the first terminal of the second resistor R2 and is suitable for outputting the divided voltage VDET. The second terminal of the second resistor R2 is grounded to GND.

[0071] The first resistor R1 and the second resistor R2 divide the output voltage of the charge pump to obtain a divided voltage VDET, and the voltage value of the divided voltage VDET is related to the ratio of the output voltage of the charge pump and the resistance values ​​of the first resistor R1 and the second resistor R2.

[0072] In one embodiment, the charge pump unit 24 is a charge pump.

[0073] In a specific embodiment, the charge pump circuit can adjust the output voltage of the charge pump PUMP through a comparator to stabilize it at a set target value. Specifically, the comparator COMP compares the output voltage of the charge pump PUMP with a reference voltage, and then adjusts the operating state of the charge pump PUMP according to the comparison result to achieve the purpose of stabilizing the output voltage.

[0074] In some embodiments of the present invention, the charge pump circuit further includes a third delay unit Delay3, which is connected to the signal processing unit 22.

[0075] In some embodiments of the present invention, the processing signal S1 is generated by the clock signal CLK, and the clock signal CLK is delayed by the third delay unit Delay3 to obtain the processing signal S1.

[0076] Figure 5 is a timing diagram of a portion of the signals in a charge pump circuit according to an embodiment of the present invention. Referring to Figure 5, taking the first level state as low (i.e., logic "0") and the second level state as high (i.e., logic "1") as an example, between time t1 and time t2, the processed feedback signal F2 is low, and between time t3 and time t4, the clock signal CLK is high. It can be seen that the time during which the processed feedback signal F2 is low is longer than the time during which the clock signal CLK is high, and time t1 is earlier than time t3, and time t2 is later than time t4. Therefore, during the period when the clock signal CLK is high, the processed feedback signal F2 is low. After subsequent NOR operation by the fourth NOR gate NOR4 and inversion by the third inverter INV3, the resulting drive signal D1 is high, which can drive the charge pump unit to remain in the on state and perform boost processing until the preset voltage value is reached, thus ensuring the boost performance of the charge pump. Furthermore, in this embodiment of the invention, at time t2, the processed feedback signal F2 changes from a low level to a high level. At this time, the drive signal D1 is at a low level, and the drive signal D1 remains at a low level from time t4 to time t2. That is, the charge pump unit 24 is in a turned-off state from time t4 to time t2, so as to avoid the charge pump unit 24 from continuously changing from the turned-on state to the turned-off state due to the change in the state of the processed feedback signal F2, thereby improving the boost performance of the charge pump.

[0077] In another embodiment of the present invention, the processed feedback signal F3 is synchronized with the clock signal CLK. Specifically, the duty cycle of the processed feedback signal F3 is the same as the duty cycle of the clock signal CLK, and the falling edge of the processed feedback signal F3 is aligned with the rising edge of the clock signal CLK.

[0078] The duty cycle of the processed feedback signal F3 is the ratio of the time the processed feedback signal F3 is in the first level state to the total time of the cycle within one period; the duty cycle of the clock signal CLK is the ratio of the time the clock signal CLK is in the second level state to the total time of the cycle within one period.

[0079] Specifically, referring to Figure 6, the signal processing unit 22 includes:

[0080] The pulse signal generation module 221 is connected to the comparison unit 21 and is adapted to receive the processing signal S1 and generate a pulse signal according to the processing signal S1.

[0081] The sampling module 222 is connected to the pulse signal generation module 221 and is adapted to receive the feedback signal F1 and the pulse signal, and to sample the feedback signal F1 according to the pulse signal to obtain the processed feedback signal F3 synchronized with the clock signal CLK.

[0082] In one embodiment, the duty cycle of the processing signal S1 is equal to the duty cycle of the clock signal CLK, that is, the processing signal S1 at this time is the clock signal CLK.

[0083] In one embodiment of the present invention, referring to FIG7, the pulse signal generation module 221 includes:

[0084] The first submodule 2211 is adapted to receive the processing signal S1 and process the rising edge of the processing signal S1 to obtain a first subpulse signal;

[0085] The second submodule 2212 is connected in parallel with the first submodule 2211 and is adapted to receive the processing signal S1 and process the falling edge of the processing signal S1 to obtain the second subpulse signal.

[0086] The merging submodule 2213 is connected to the first submodule 2211 and the second submodule 2212, and is adapted to receive the first subpulse signal and the second subpulse signal, and merge the first subpulse signal and the second subpulse signal to obtain the pulse signal.

[0087] In one embodiment of the present invention, referring to FIG8, the first submodule 2211 includes: a first inverter INV1, a first delay unit Delay1, and a first NOR gate NOR1; wherein:

[0088] The input terminal of the first inverter INV1 is adapted to receive the processing signal S1, and the output terminal of the first inverter INV1 is connected to the input terminal of the first delay unit Delay1; the output terminal of the first delay unit Delay1 is connected to the second input terminal of the first NOR gate NOR1.

[0089] The first input terminal of the first NOR gate NOR1 is adapted to receive the processing signal S1, and the output terminal of the first NOR gate NOR1 is adapted to output the first sub-pulse signal.

[0090] In a specific embodiment, the first delay unit Delay1 is adapted to generate a pulse when the processed signal is at the falling edge. Subsequently, the feedback signal can be sampled according to this pulse, and the time between adjacent pulses can be adjusted so that the falling edge of the processed feedback signal can be aligned with the rising edge of the processed signal, and the rising edge of the processed feedback signal can be aligned with the falling edge of the processed signal.

[0091] In one embodiment of the present invention, the second submodule 2212 includes: a second inverter INV2, a second delay unit Delay2, and a second NOR gate NOR2; wherein:

[0092] The input terminal of the second inverter INV2 is adapted to receive the processing signal S1, and the output terminal of the second inverter INV2 is connected to the input terminal of the second delay unit Delay2; the output terminal of the second delay unit Delay2 is connected to the second input terminal of the second NOR gate NOR2.

[0093] The first input terminal of the second NOR gate NOR2 is adapted to receive the processing signal S1, and the output terminal of the second NOR gate NOR2 is adapted to output the second sub-pulse signal.

[0094] In a specific embodiment, the second delay unit Delay2 is adapted to generate a pulse when the processed signal is at its rising edge. Subsequently, the feedback signal can be sampled based on this pulse, and the time between adjacent pulses can be adjusted so that the falling edge of the processed feedback signal can be aligned with the rising edge of the processed signal, and the rising edge of the processed feedback signal can be aligned with the falling edge of the processed signal.

[0095] In one embodiment of the present invention, the merging submodule 2213 includes: a third NOR gate NOR3;

[0096] The first input terminal of the third NOR gate NOR3 is adapted to receive the first sub-pulse signal, the second input terminal of the third NOR gate NOR3 is adapted to receive the second sub-pulse signal, and the output terminal of the third NOR gate NOR3 is adapted to output the pulse signal.

[0097] In one embodiment of the present invention, the sampling module 222 includes: a trigger 2221;

[0098] The first input terminal of the trigger 2221 is adapted to receive the feedback signal F1, the second input terminal of the trigger 2221 is adapted to receive a pulse signal, and the output terminal of the trigger 2221 is adapted to output the synchronously processed feedback signal F3.

[0099] In one embodiment, the trigger 2221 further includes a reset terminal RN.

[0100] Figure 9 is a timing diagram of a portion of the charge pump circuit signals in another embodiment of the present invention. Referring to Figure 9, taking the first level state as low (i.e., logic "0") and the second level state as high (i.e., logic "1") as an example, between time t1 and time t2, the processed feedback signal F3 is low, and between time t1 and time t2, the clock signal CLK is high. It can be seen that the time during which the processed feedback signal F3 is low is equal to the time during which the clock signal CLK is high. Therefore, during the period when the clock signal CLK is high, the processed feedback signal F3 is low. After subsequent NOR operation by the fourth NOR gate NOR4 and inversion by the third inverter INV3, the resulting drive signal is high, which can drive the charge pump unit to remain in the on state and perform boost processing until the preset voltage value is reached, thus ensuring the boost performance of the charge pump. Furthermore, the processed feedback signal F3 changes from high to low at time t1, and the corresponding clock signal CLK changes from low to high at time t1. The processed feedback signal F3 changes from low to high at time t2, and the corresponding clock signal CLK changes from high to low at time t2. That is, the processed feedback signal F3 is synchronized with the clock signal CLK, which reduces the power consumption of the charge pump circuit caused by the processed feedback signal F3 remaining at a high level for too long, and minimizes the power consumption of the charge pump circuit.

[0101] In one embodiment, when the above-described charge pump circuit is used, and the processed feedback signal F3 is synchronized with the clock signal CLK, the power consumption of the charge pump circuit can be reduced from 900 microamps to 700 microamps.

[0102] In summary, this invention, by setting a signal processing unit and adjusting the feedback signal through the signal processing unit, can obtain a processed feedback signal with an increased duty cycle. Since the processed feedback signal remains at the first level while the clock signal is in the second level state, the drive signal can keep the charge pump unit in the on state and perform boost processing until the preset voltage value is reached during the second level state of the clock signal. This prevents the charge pump unit from changing from the on state to the off state due to changes in the processed feedback signal state, which would reduce the boost time of the charge pump unit and prevent it from failing to reach the preset voltage value, thereby improving the boost performance of the charge pump.

[0103] This invention also provides a charge pump system. Referring to FIG10, the charge pump system may include multiple cascaded charge pump circuits 20 as described above. Each charge pump circuit 20 includes an input terminal and an output terminal. The output terminal of the previous stage charge pump circuit is connected to the input terminal of the next stage charge pump circuit. The input terminal VIN of the first stage charge pump circuit is adapted to receive an initial voltage.

[0104] In a specific embodiment, the charge pump circuit further includes a drive input terminal, a power input terminal VDD, and a ground terminal GND, wherein the drive input terminal is used to receive the drive signal D1.

[0105] In the above scheme, after adopting the above-described charge pump circuit, the charge pump circuits at each stage of the charge pump system can achieve the following: during the period when the clock signal is in the second level state, the drive signal can drive the charge pump unit to remain in the on state and perform boost processing until the preset voltage value is reached, and provide sufficient input voltage for the next stage charge pump circuit, thereby ensuring the boost performance of the charge pump system; and the duration of the clock signal in the second level state in each stage of the charge pump circuit is equal to the duration of the processed feedback signal remaining in the first level state, reducing the power consumption of each stage of the charge pump circuit due to the excessive duration of the processed feedback signal remaining in the first level state, thereby reducing the power consumption of the charge pump system.

[0106] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A charge pump circuit, characterized by, The application relates to a charge pump circuit, comprising: a comparison unit adapted to receive a reference signal and a divided voltage signal, and compare the reference signal and the divided voltage signal to obtain a feedback signal; a signal processing unit connected with the comparison unit, adapted to receive the feedback signal, and process the feedback signal to obtain a processed feedback signal, the duty cycle of the processed feedback signal being greater than the duty cycle of the feedback signal; a driving unit connected with the signal processing unit, adapted to receive a clock signal and the processed feedback signal, and perform an AND operation on the clock signal and the processed feedback signal to obtain a driving signal; and a charge pump unit connected with the driving unit, adapted to receive the driving signal, and start or stop under the control of the driving signal; wherein, during the clock signal being in a second level state, the processed feedback signal remains in a first level state; the first level state and the second level state are logically opposite.

2. The charge pump circuit of claim 1, wherein, The signal processing unit is further adapted to receive a processing signal, and perform a delay processing on the feedback signal based on the processing signal to obtain the processed feedback signal.

3. The charge pump circuit of claim 2, wherein, The processed feedback signal is synchronous with the clock signal.

4. The charge pump circuit of claim 3, wherein, The signal processing unit comprises: a pulse signal generation module connected with the comparison unit, adapted to receive a processing signal, and generate a pulse signal according to the processing signal; a sampling module connected with the pulse signal generation module, adapted to receive the feedback signal and the pulse signal, and sample the feedback signal according to the pulse signal to obtain the processed feedback signal synchronous with the clock signal.

5. The charge pump circuit of claim 4, wherein, The pulse signal generation module comprises: a first sub-module adapted to receive the processing signal, and process a rising edge of the processing signal to obtain a first sub-pulse signal; a second sub-module connected with the first sub-module in parallel, adapted to receive the processing signal, and process a falling edge of the processing signal to obtain a second sub-pulse signal; and a merging sub-module connected with the first sub-module and the second sub-module, adapted to receive the first sub-pulse signal and the second sub-pulse signal, and merge the first sub-pulse signal and the second sub-pulse signal to obtain the pulse signal.

6. The charge pump circuit of claim 5, wherein, The first sub-module comprises a first inverter, a first delay device and a first NAND gate; wherein: an input end of the first inverter is adapted to receive the processing signal, an output end of the first inverter is connected with an input end of the first delay device, and an output end of the first delay device is connected with a second input end of the first NAND gate; a first input end of the first NAND gate is adapted to receive the processing signal, and an output end of the first NAND gate is adapted to output the first sub-pulse signal.

7. The charge pump circuit of claim 5, wherein, The second sub-module comprises a second inverter, a second delay device and a second NAND gate; wherein: an input end of the second inverter is adapted to receive the processing signal, an output end of the second inverter is connected with an input end of the second delay device, and an output end of the second delay device is connected with a second input end of the second NAND gate; a first input end of the second NAND gate is adapted to receive the processing signal, and an output end of the second NAND gate is adapted to output the second sub-pulse signal. The first input terminal of the second NOR gate is adapted to receive the processed signal, and the output terminal of the second NOR gate is adapted to output the second sub-pulse signal.

8. The charge pump circuit of claim 5, wherein, The merging submodule includes: a third NOR gate; The first input terminal of the third NOR gate is adapted to receive the first sub-pulse signal, the second input terminal of the third NOR gate is adapted to receive the second sub-pulse signal, and the output terminal of the third NOR gate is adapted to output the pulse signal.

9. The charge pump circuit of claim 4, wherein, The sampling module includes: a trigger; The first input terminal of the trigger is adapted to receive the feedback signal, the second input terminal of the trigger is adapted to receive the pulse signal, and the output terminal of the trigger is adapted to output the feedback signal after synchronization processing.

10. The charge pump circuit of claim 1, wherein, The driving unit includes: a fourth NOR gate and a third inverter; wherein: The first input terminal of the fourth NOR gate is adapted to receive the clock signal, the second input terminal of the fourth NOR gate is adapted to receive the processed feedback signal, and the output terminal of the fourth NOR gate is connected to the input terminal of the third inverter. The output terminal of the third inverter is connected to the charge pump unit.

11. The charge pump circuit of claim 1, wherein, The comparison unit includes: a comparator; the first input terminal of the comparator is adapted to receive a reference signal, the second input terminal of the comparator is adapted to receive a voltage divider signal, and the output terminal of the comparator is adapted to output a feedback signal.

12. The charge pump circuit of claim 1, wherein, Also includes: A voltage divider circuit, connected to the second input terminal of the comparator, is adapted to generate a voltage divider signal.

13. The charge pump circuit of claim 1, wherein, Also includes: A reference circuit, connected to the first input terminal of the comparator, is adapted to generate a reference signal.

14. A charge pump system, characterized by The invention includes multiple cascaded charge pump circuits as described in any one of claims 1 to 13, each charge pump circuit including an input terminal and an output terminal, wherein the output terminal of the preceding charge pump circuit is connected to the input terminal of the following charge pump circuit.

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