Display substrate and display apparatus

Abstract

The present disclosure belongs to the technical field of display. Provided are a display substrate and a display apparatus. The display substrate in the present disclosure comprises: a base substrate, which is divided into a display area and a peripheral area located on at least one side of the display area; and a gate driving circuit and a frame start signal line, which are arranged on the base substrate and located in the peripheral area, wherein the frame start signal line is configured to provide a frame start signal for at least one shift register in the gate driving circuit, the frame start signal line comprises at least two signal line segments that are arranged in a disconnected manner, and a transfer electrode that connects two signal line segments arranged adjacent to each other, and the transfer electrode and the signal line segments are located in different layers.

Description

Display substrate and display device Technical Field

[0001] This disclosure belongs to the field of display technology, specifically relating to a display substrate and a display device. Background Technology

[0002] During the manufacturing process of TFT-LCD (Thin Film Transistor Liquid Crystal Display), electrostatic charges accumulate on the substrate due to various factors such as equipment, power application during testing, and the external environment. When the charge on the substrate reaches a certain peak value, it triggers electrostatic discharge (ESD). This discharge typically generates a very strong discharge current, which can potentially damage components in the circuitry, leading to display device malfunctions.

[0003] In many current TFT-LCD products, gate drive electrodes are located in the peripheral area. These gate drive electrodes include multiple cascaded shift registers, with the signal input of the first shift register typically connected to the frame enable signal line. Because the frame enable signal line is singular and has few discharge paths, it is prone to ESD, which can burn out the via structure and GOA (Gate on Array) units, causing abnormal screen display. Summary of the Invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art, and to provide a display substrate and a display device.

[0005] This disclosure provides a display substrate, which includes:

[0006] The substrate is divided into a display area and a peripheral area located on at least one side of the display area;

[0007] A gate drive circuit and a frame enable signal line are disposed on the substrate, located in the peripheral region. The frame enable signal line is configured to provide a frame enable signal to at least one shift register in the gate drive circuit.

[0008] The frame enable signal line includes at least two disconnected signal segments and a transition electrode connecting two adjacent signal segments; the transition electrode and the signal segments are located on different layers.

[0009] The display substrate further includes:

[0010] A first conductive layer is disposed on the substrate, and the gates of each thin-film transistor of the shift register are located in the first conductive layer;

[0011] The first interlayer insulating layer is disposed on the side of the first conductive layer away from the substrate.

[0012] The second conductive layer is disposed on the side of the first interlayer insulating layer away from the first conductive layer, and the source and drain of each thin film transistor of the shift register are located in the second conductive layer.

[0013] The second interlayer insulating layer is disposed on the side of the second conductive layer that is opposite to the first interlayer insulating layer;

[0014] The third conductive layer is disposed on the side of the second interlayer insulating layer away from the second conductive layer, and the common electrode of the pixel unit located in the display area is located in the third conductive layer.

[0015] The adapter electrode includes a first adapter portion, a second adapter portion, and a third adapter portion; the first adapter portion and the second adapter portion are located in the third conductive layer, and the third adapter portion is located in the second conductive layer. The first adapter portion and the second adapter portion are respectively connected to the third adapter portion through at least one first connection via and at least one second connection via; both the first connection via and the second connection via penetrate the second interlayer insulating layer.

[0016] The signal line segment is located in the first conductive layer. For two adjacent signal line segments, one is connected to the first adapter through at least one third connecting via, and the other is connected to the second adapter through at least one fourth connecting via. Both the third connecting via and the fourth connecting via penetrate the first interlayer insulation layer and the second interlayer insulation layer.

[0017] Wherein, the orthographic projections of the third adapter and the signal line segment on the substrate do not overlap, and the orthographic projection of one of the third adapters on the substrate is located between two adjacent orthographic projections of the signal line segment on the substrate.

[0018] For two adjacent signal segments and a connecting electrode for connecting them, the third connecting portion of the connecting electrode has a first end and a second end disposed opposite to each other along its extending direction; one signal segment has a third end connected to the first end of the third connecting portion via the first connecting portion; and the other signal segment has a fourth end connected to the second end of the third connecting portion via the second connecting portion. The orthographic projection of the first end on the substrate is wider the closer it is to the orthographic projection of the third end on the substrate; the orthographic projection of the second end on the substrate is wider the closer it is to the orthographic projection of the fourth end on the substrate; the orthographic projection of the third end on the substrate is wider the closer it is to the orthographic projection of the first end on the substrate; and the orthographic projection of the fourth end on the substrate is wider the closer it is to the orthographic projection of the second end on the substrate.

[0019] The orthographic projection of the first connecting via for connecting the third adapter and the first adapter on the substrate is covered by the orthographic projection of the first end on the substrate; the orthographic projection of the second connecting via for connecting the third adapter and the second adapter on the substrate is covered by the orthographic projection of the second end on the substrate.

[0020] The orthographic projection of the third connecting via for connecting the signal line segment and the first adapter on the substrate is covered by the orthographic projection of the third end on the substrate; the orthographic projection of the fourth connecting via for connecting the signal line segment and the second adapter on the substrate is covered by the orthographic projection of the fourth end on the substrate.

[0021] The orthographic projection of the first adapter portion on the substrate covers the orthographic projections of the first end and the third end on the substrate; the orthographic projection of the second connecting portion on the substrate covers the orthographic projections of the second end and the fourth end on the substrate.

[0022] Among them, there are multiple first connection vias at the first end, and the multiple first connection vias are arranged in multiple columns, and the number of first connection vias in each column is positively correlated with the line width of the first end;

[0023] The second end has multiple second connection vias, and the multiple second connection vias are arranged in multiple columns. The number of second connection vias in each column is positively correlated with the line width of the second end.

[0024] The third connection vias located at the third end are multiple, and the multiple third connection vias are arranged in multiple columns. The number of third connection vias in each column is positively correlated with the line width of the third end.

[0025] The fourth connection vias located at the fourth end are multiple, and the multiple fourth connection vias are arranged in multiple columns. The number of fourth connection vias in each column is positively correlated with the line width of the fourth end.

[0026] Specifically, for two adjacent signal line segments, one is connected to the third adapter through at least one fifth connecting via, and the other is connected to the third adapter through at least one sixth connecting via; both the fifth and sixth connecting vias penetrate the first interlayer insulation layer.

[0027] In this embodiment, for two adjacent signal segments and a connecting electrode for connecting the two, the third connecting portion of the connecting electrode has a first end and a second end disposed opposite to each other along its extending direction; one signal segment has a third end connected to the first end of the third connecting portion through the first connecting portion; and the other signal segment has a fourth end connected to the second end of the third connecting portion through the second connecting portion. The orthographic projection of the first end on the substrate is wider the closer it is to the orthographic projection of the third end on the substrate; the orthographic projection of the second end on the substrate is wider the closer it is to the orthographic projection of the fourth end on the substrate.

[0028] The orthographic projection of the first end on the substrate covers the orthographic projection of the third end on the substrate; the orthographic projection of the second end on the substrate covers the orthographic projection of the fourth end on the substrate.

[0029] The fifth connecting via is projected onto the substrate and is located within the area defined by the projected projections of the first connecting via and the third connecting via onto the substrate.

[0030] The sixth connection via is projected onto the substrate and is located within the area defined by the projections of the second and fourth connection vias onto the substrate.

[0031] The first end portion includes a first extension portion and a second extension portion; the second end portion includes a third extension portion and the fourth extension portion.

[0032] The orthographic projections of the first extension portion and the second extension portion on the substrate do not overlap with the orthographic projection of the third end portion on the substrate; the orthographic projections of the third extension portion and the fourth extension portion on the substrate do not overlap with the orthographic projection of the fourth end portion on the substrate.

[0033] At least a portion of the first connecting via overlaps with the orthographic projection of the first extension portion on the substrate; at least a portion of the first connecting via overlaps with the orthographic projection of the second extension portion on the substrate.

[0034] At least a portion of the second connecting via overlaps with the orthographic projection of the third extension on the substrate; at least a portion of the second connecting via overlaps with the orthographic projection of the fourth extension on the substrate.

[0035] The adapter electrode further includes a fourth adapter portion; the second adapter portion is located between adjacent signal segments and is connected to the third adapter portion through at least one seventh connection via; the seventh connection via penetrates the first interlayer insulation layer.

[0036] The display substrate further includes a redundant shift register located in the peripheral area;

[0037] The redundant shift register includes: an input sub-circuit, an output sub-circuit, at least one pull-down control sub-circuit, and at least one pull-down sub-circuit.

[0038] The input sub-circuit is configured to pre-charge the pull-up node in response to an input signal at the signal input terminal; the connection node between the input sub-circuit, the output sub-circuit, and the pull-down sub-circuit;

[0039] The output sub-circuit is configured to output a clock signal through a signal output terminal in response to the potential of the pull-up node.

[0040] The output sub-circuit is configured to output a clock signal through a cascaded signal terminal in response to the potential of the pull-up node.

[0041] The pull-down control subcircuit is configured to respond to the power supply voltage and control the potential of the pull-down node through the power supply voltage; one of the pull-down control subcircuits connects one of the pull-down subcircuits and one of the pull-down subcircuits, and the connection node between the two is the pull-down node;

[0042] The pull-down sub-circuit is configured to pull down the potential of the pull-up node by a non-operating level signal in response to the potential of the pull-up node.

[0043] The output sub-circuit includes a third transistor and a storage capacitor;

[0044] The first end of the storage capacitor is connected to the gate of the third transistor, and the second end of the storage capacitor is connected to the drain of the third transistor; at least one of the source and drain of the third transistor is connected to the frame enable signal line.

[0045] The output sub-circuit includes a third transistor and a storage capacitor;

[0046] The first end of the storage capacitor is connected to the gate of the third transistor, and the second end of the storage capacitor is connected to the drain of the third transistor; at least one of the source and drain of the third transistor is connected to the first tip structure, and the frame enable signal line is connected to the second tip structure.

[0047] The tip of the first tip structure is opposite to the tip of the second tip structure;

[0048] or,

[0049] The first tip structure includes a first body portion and at least one first tip portion connected to one side of the first body portion extending in the direction of extension; the second tip structure includes a second body portion and at least one second tip portion connected to one side of the second body portion extending in the direction of extension; the first tip portion and the second tip portion are opposite to each other.

[0050] The pull-down control sub-circuit includes a fifth transistor and a ninth transistor; the pull-down sub-circuit includes a sixth transistor and an eighth transistor.

[0051] The gate of the fifth transistor is connected to the drain of the ninth transistor and the source of the eighth transistor. The source of the fifth transistor is connected to the power supply voltage terminal and the gate of the ninth transistor. The drain of the fifth transistor is connected to the pull-down node.

[0052] The gate of the sixth transistor is connected to the gate of the eighth transistor and the pull-up node, and the source of the sixth transistor is connected to the pull-down node; the drain of the sixth transistor and the drain of the eighth transistor are both connected to a non-operating level signal terminal.

[0053] The frame enable signal line is connected to the source of the eighth transistor, and / or the frame enable signal line is connected to the gate of the sixth transistor.

[0054] The pull-down control sub-circuit includes a fifth transistor and a ninth transistor; the pull-down sub-circuit includes a sixth transistor and an eighth transistor.

[0055] The gate of the fifth transistor is connected to the drain of the ninth transistor and the source of the eighth transistor. The source of the fifth transistor is connected to the power supply voltage terminal and the gate of the ninth transistor. The drain of the fifth transistor is connected to the pull-down node.

[0056] The gate of the sixth transistor is connected to the gate of the eighth transistor and the pull-up node, and the source of the sixth transistor is connected to the pull-down node; the drain of the sixth transistor and the drain of the eighth transistor are both connected to a non-operating level signal terminal.

[0057] One of the source of the eighth transistor and the gate of the sixth transistor is connected to the first tip structure, and the frame enable signal line is connected to the second tip structure.

[0058] The tip of the first tip structure is opposite to the tip of the second tip structure;

[0059] or,

[0060] The first tip structure includes a first body portion and at least one first tip portion connected to one side of the first body portion extending in the direction of extension; the second tip structure includes a second body portion and at least one second tip portion connected to one side of the second body portion extending in the direction of extension; the first tip portion and the second tip portion are opposite to each other.

[0061] The display substrate further includes a redundant clock signal line, and the frame enable signal line is connected to the redundant clock signal line.

[0062] This disclosure provides a display device comprising any of the display substrates described above. Attached Figure Description

[0063] Figure 1 is a schematic diagram of an exemplary display substrate.

[0064] Figure 2 is a circuit diagram of an exemplary shift register.

[0065] Figure 3 is a partial schematic diagram of the display substrate according to an embodiment of the present disclosure.

[0066] Figure 4 is a schematic diagram of the film layers of the display substrate according to an embodiment of the present disclosure.

[0067] Figure 5 is a cross-sectional view of A-A' in Figure 3.

[0068] Figure 6 is a top view of the connection between the signal line segment and the adapter electrode in a first example of an embodiment of this disclosure;

[0069] Figure 7 is a cross-sectional view of B-B' in Figure 6.

[0070] Figure 8 is a partial top view of the connection between the signal line segment and the adapter electrode in the first case of the second example of the present disclosure.

[0071] Figure 9 is a partial top view of the second case of the second example of the present disclosure, in which the signal segment is connected to the adapter electrode.

[0072] Figure 10 is a top view of the connection between the signal line segment and the adapter electrode in a third example of an embodiment of this disclosure.

[0073] Figure 11 is a cross-sectional view of C-C' in Figure 10.

[0074] Figure 12 shows a connection method between the frame enable signal line and the redundant shift register according to an embodiment of this disclosure.

[0075] Figure 13 shows another connection method between the frame enable signal line and the redundant shift register according to an embodiment of this disclosure.

[0076] Figure 14 shows another connection method between the frame enable signal line and the redundant shift register according to an embodiment of the present disclosure;

[0077] Figure 15 is a schematic diagram of the coupling between a first tip structure and a second tip structure according to an embodiment of the present disclosure.

[0078] Figure 16 is a schematic diagram of the coupling between a first tip structure and a second tip structure according to another embodiment of this disclosure. Detailed Implementation

[0079] To enable those skilled in the art to better understand the technical solution of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0080] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0081] Figure 1 is a schematic diagram of an exemplary display substrate; as shown in Figure 1, this display substrate can be applied to a liquid crystal display. The display substrate includes a substrate, and multiple gate lines (Gate), multiple data lines (data), multiple pixel units (P), and a gate driving circuit (GOA) disposed on the substrate. The substrate is divided into a display area AA and a peripheral area BA located on at least one side of the display area AA. In this embodiment, the peripheral area BA surrounds the display area AA as an example. The gate lines (Gate) and data lines (data) extend from the display area AA to the peripheral area BA. The pixel units are located in the display area AA, and the gate driving circuit (GOA) is located in the peripheral area BA. The gate lines (Gate) and data lines (data) are intersecting, and the pixel units (P) are located within the area defined by the intersection of the gate lines (Gate) and data lines (data). Each pixel unit (P) includes a thin-film transistor (TFT), a pixel electrode, and a common electrode. The gates of the TFTs in pixel units (P) located in the same row are connected to the same gate line (Gate), the sources of the TFTs in pixel units (P) located in the same column are connected to the same data line (data), the drains of the TFTs are connected to the pixel electrode, and the common electrode is located on the side of the pixel electrode facing away from the substrate. The gate drive circuit (GOA) includes multiple cascaded shift registers, each providing a gate drive signal for one gate line. Typically, a redundant shift register is also provided in the peripheral area (BA). The structure of the redundant shift register is roughly the same as the regular shift registers, except that it does not operate when the regular shift registers can normally provide the gate drive signal. Therefore, some functional modules within the redundant shift register are not connected to each other. In this embodiment, only the output sub-circuit of the redundant shift register is shown as an example where other sub-circuits are not connected.

[0082] Since the structure of a redundant shift register is largely the same as that of a shift register, only one exemplary shift register architecture will be described below. It should be understood that this is only one shift register architecture and does not constitute a limitation on the scope of protection of the embodiments of this disclosure. In actual products, other architectures of shift registers can also be used to provide gate drive signals for the gate lines. Figure 2 is a circuit diagram of a shift register according to an embodiment of this disclosure; as shown in Figure 2, the shift register includes not only the aforementioned input sub-circuit 1, output sub-circuit 2, and pull-up reset sub-circuit 3, but also two pull-down control sub-circuits 5 / 5', two pull-down sub-circuits 6 / 6', two first noise reduction sub-circuits 7 / 7', two second noise reduction sub-circuits 8 / 8', two third noise reduction sub-circuits 9 / 9', two auxiliary sub-circuits 11 / 11', and a discharge circuit 10. In this shift register, pull-down control sub-circuit 5 is connected to a pull-down sub-circuit 6, with the connection node being the first pull-down node PD1. Pull-down control sub-circuit 5' is connected to a pull-down sub-circuit 6', with the connection node being the second pull-down node PD2. The first pull-down node PD1 connects to a first noise reduction sub-circuit 7, a second noise reduction sub-circuit 8, and a third noise reduction sub-circuit 9. The second pull-down node PD2 connects to another first noise reduction sub-circuit 7', another second noise reduction sub-circuit 8', and another third noise reduction sub-circuit 9'. The two pull-down control sub-circuits 5 / 5' in this shift register have the same structure and function, except that they operate in a time-sharing manner during shift register operation, meaning the timing of the control signals used to control these two pull-down control sub-circuits 5 / 5' is reversed. Similarly, the two pull-down sub-circuits 6 / 6' have the same structure and function, and they operate in a time-sharing manner; the two first noise reduction sub-circuits 7 / 7' have the same structure and function, and they operate in a time-sharing manner; the two second noise reduction sub-circuits 8 / 8' have the same structure and function, and they operate in a time-sharing manner; the two third noise reduction sub-circuits 9 / 9' have the same structure and function, and they operate in a time-sharing manner.

[0083] The output sub-circuit 2 responds to the potential of the pull-up node PU and outputs the clock signal input at the clock signal terminal through the signal output terminal OUTPUT. The reset sub-circuit 3 responds to the reset signal output at the first reset signal terminal Reset_PU and resets the pull-up node PU through a low-level signal. The discharge circuit 10 responds to the frame pre-open signal input at the frame pre-open signal terminal Trst and discharges the pull-up node PU through a low-level signal input at the low-level signal terminal. One pull-down control sub-circuit 5 controls the potential of the first pull-down node PD1 under the control of the first power supply voltage VDDO, and the other pull-down control sub-circuit 5' controls the potential of the second pull-down node PD2 under the control of the second power supply voltage VDDE. One pull-down sub-circuit 6 pulls down the potential of the first pull-down node PD1 in response to the potential of the pull-up node PU, and the other pull-down sub-circuit 6' pulls down the potential of the second pull-down node PD2 in response to the potential of the pull-up node PU. One of the first noise reduction sub-circuits 7 responds to the potential of the first pull-down node PD1 and reduces the noise of the potential of the pull-up node PU. Another first noise reduction sub-circuit 7' responds to the potential of the second pull-down node PD2 and reduces the noise of the potential of the pull-up node PU. One of the second noise reduction sub-circuits 8 responds to the potential of the first pull-down node PD1 and reduces the noise of the output of the signal output terminal Output. Another second noise reduction sub-circuit 8' responds to the potential of the second pull-down node PD2 and reduces the noise of the output of the signal output terminal Output. One of the third noise reduction sub-circuits 9 responds to the potential of the first pull-down node PD1 and reduces the noise of the output of the cascaded signal output terminal Out_C. Another third noise reduction sub-circuit 9' responds to the potential of the second pull-down node PD2 and reduces the noise of the output of the cascaded signal output terminal Out_C. The cascaded sub-circuit 12 responds to the potential of the pull-up node PU and outputs the clock signal CLK through the cascaded signal output terminal Out_C.

[0084] Specifically, referring to Figure 2, input sub-circuit 1 includes a first transistor M1; first reset sub-circuit 3 includes a second transistor M2; output sub-circuit 2 includes a third transistor M3 and a storage capacitor C. Each pull-down control sub-circuit includes a fifth transistor and a ninth transistor; the fifth transistors in the two pull-down control sub-circuits 5 / 5' are represented by M5 and M5', respectively, and the ninth transistors are represented by M9 and M9', respectively. Each pull-down sub-circuit includes a sixth transistor and an eighth transistor; the sixth transistors in the two pull-down sub-circuits 6 / 6' are represented by M6 and M6', respectively, and the eighth transistors are represented by M8 and M8', respectively. Each first noise reduction sub-circuit includes a tenth transistor; the tenth transistors in the two first noise reduction sub-circuits 7 / 7' are represented by M10 and M10', respectively. Each second noise reduction sub-circuit includes an eleventh transistor; the eleventh transistors in the two second noise reduction sub-circuits 8 / 8' are represented by M11 and M11', respectively. Each third noise reduction sub-circuit includes a twelfth transistor; the twelfth transistors in the two third noise reduction sub-circuits 9 / 9' are denoted as M12 and M12', respectively. Each auxiliary sub-circuit includes a sixteenth transistor; the sixteenth transistors in the two auxiliary sub-circuits 11 / 11' are denoted as M16 and M16', respectively. The discharge circuit 10 includes a seventh transistor M7. The cascaded sub-circuit includes a thirteenth transistor M13.

[0085] Referring to Figure 2, the gate and source of M1 are connected to the signal input terminal INPUT, and the drain of M1 is connected to the pull-up node PU; the gate of M2 is connected to the first reset signal terminal RESET_PU, the source of M2 is connected to the pull-up node PU, and the drain of M2 is connected to the low-level signal terminal; the gate of M3 is connected to the pull-up node PU, the source of M3 is connected to the clock signal terminal, and the drain of M3 is connected to the signal output terminal OUTPUT; the first terminal of C is connected to the pull-up node PU, and the second terminal of C is connected to the signal output terminal OUTPUT; the gate and source of M5 are both connected to the first power supply voltage terminal, and the drain of M5 is connected to the first pull-down control node PD_CN1; the gate of M9 is connected to the first pull-down control node PD_CN1, and the source of M9 is connected to... At the first power supply voltage terminal, the drain of M9 is connected to the first pull-down node PD1; the gate and source of M5' are both connected to the second power supply voltage terminal, and the drain of M5' is connected to the second pull-down control node PD_CN2; the gate of M9' is connected to the second pull-down control node PD_CN2, the source of M9' is connected to the second power supply voltage terminal, and the drain of M9' is connected to the first pull-down node PD1; the gate of M6 is connected to the pull-up node PU, the source of M6 is connected to the first pull-down node PD1, and the drain of M6 is connected to the low-level signal terminal; the gate of M8 is connected to the pull-up node PU, the source of M8 is connected to the first pull-down control node PD_CN1, and the drain of M8 is connected to the low-level signal terminal; the gate of M6' is connected to the pull-up node PU, and the source of M6' is connected to... Connect the second pull-down node PD2, the drain of M6' is connected to the low-level signal terminal; the gate of M8' is connected to the pull-up node PU, the source of M8' is connected to the second pull-down control node PD_CN2, and the drain of M8' is connected to the low-level signal terminal; the gate of M10 is connected to the first pull-down node PD1, the source of M10 is connected to the pull-up node PU, and the drain of M10 is connected to the low-level signal terminal; the gate of M11 is connected to the first pull-down node PD1, the source of M11 is connected to the signal output terminal OUTPUT, and the drain of M11 is connected to the low-level signal terminal; the gate of M12 is connected to the first pull-down node PD1, the source of M12 is connected to the cascaded signal output terminal OUT_C, and the drain of M12 is connected to the low-level signal terminal; the gate of M10' is connected to... Connect the second pull-down node PD2, connect the source of M10' to the pull-up node PU, and connect the drain of M10' to the low-level signal terminal; connect the gate of M11' to the second pull-down node PD2, connect the source of M11' to the signal output terminal OUTPUT, and connect the drain of M11' to the low-level signal terminal; connect the gate of M12' to the second pull-down node PD2, connect the source of M12' to the cascade signal output terminal OUT_C, and connect the drain of M12' to the low-level signal terminal; connect the gate of M7 to the frame-before-enabled signal terminal, connect the source of M7 to the pull-up node PU, and connect the drain of M7 to the low-level signal terminal; connect the gate of M13 to the pull-up node PU, connect the source of M13 to the clock signal terminal, and connect the drain of M13 to the cascade signal terminal.The gate of M16 is connected to the signal input terminal INPUT, the source of M16 is connected to the first pull-down node PD1, and the drain of M16 is connected to a low-level signal terminal. The gate of M16' is connected to the signal input terminal INPUT, the source of M16' is connected to the second pull-down node PD2, and the drain of M16' is connected to a low-level signal terminal.

[0086] In this circuit, M5 and M9 form one pull-down control subcircuit, and M5' and M9' form another pull-down control subcircuit. The two pull-down control subcircuits operate in a 5 / 5' time-sharing manner (i.e., alternately). Correspondingly, since the first, second, and third noise reduction subcircuits composed of M10, M11, and M12 are all controlled by the first pull-down node PD1, and the first, second, and third noise reduction subcircuits composed of M10', M11', and M12' are all controlled by the second pull-down node PD2, when the pull-down control subcircuits operate in a time-sharing manner, the first, second, and third noise reduction subcircuits will also operate in a time-sharing manner. The following explanation uses only one working cycle as an example to illustrate the working principle of the shift register.

[0087] During the discharge phase, before the frame is displayed, a high-level signal is input to the frame pre-enabled signal terminal TRST. The low-level signal input at the low-level signal terminal discharges the pull-up node PU to prevent residual charge in the pull-up node PU from causing display abnormalities.

[0088] During the input phase, a high-level signal is input to the signal input terminal Input, M1 is turned on, and the pull-up node PU is pulled high through the high-level signal to charge C. At the same time, M16 and M16' are both turned on, pulling down the first pull-down node PD1 and the second pull-down node PD2 to avoid affecting the potential of the pull-up node PU.

[0089] During the output phase, since the pull-up node PU is pulled high during the input phase, M3 and M13 are turned on, and the high-level signal input from the clock signal terminal is output to the gate line connected to it through the signal output terminal Output. At the same time, the cascaded signal output terminal Out_C outputs the same signal as the signal output terminal Output, that is, it outputs a high-level signal to the pull-up reset signal terminal RESET_PU of the previous stage shift register unit and the signal input terminal Input of the next stage shift register unit.

[0090] During the reset phase, a high-level signal is input to the first reset signal terminal RESET_PU. M2 is enabled, and the low-level signal input through the low-level signal terminal pulls down the potential of the pull-up node PU to reset it. Since the pull-up node PU is pulled low, M3 and M13 are turned off, and the signal output terminal Output and the cascaded signal output terminal Out_C no longer output high-level signals. At the same time, the pull-down control node PD_CN1 and the first pull-down node PD1 are both high-level signals, and M10, M11, and M12 are enabled to reduce noise in the outputs of the pull-up node PU, the signal output terminal Output, and the cascaded signal output terminal Out_C, respectively, until the pull-up node PU potential is pulled high at the start of the next frame scan.

[0091] The inventors discovered that the signal input terminal of the first shift register is typically connected to the frame enable signal line. Because the frame enable signal line is singular and has few discharge paths, it is prone to ESD, causing burnout of the via structure and GOA unit, resulting in abnormal screen display. To address this problem, the present disclosure provides the following technical solution.

[0092] Figure 3 is a partial schematic diagram of a display substrate according to an embodiment of the present disclosure. As shown in Figure 3, an embodiment of the present disclosure provides a display substrate, which includes a substrate, a gate driving circuit, pixel units, gate lines, and data lines disposed on the substrate. The substrate is divided into a display area and a peripheral area located on at least one side of the display area. The gate driving circuit is disposed on the substrate and located in the peripheral area. A frame enable signal line is also provided in the peripheral area to provide a frame enable signal to at least one shift register in the gate driving circuit.

[0093] It should be noted that when the gate drive circuit includes only one set of shift registers, the frame enable signal line is connected to the signal input terminal of the first shift register in the scan sequence, providing it with the frame enable signal as an input signal. When the gate drive circuit includes multiple sets of shift registers, the frame enable signal line is connected to the signal input terminal of the first shift register in the scan sequence within each set of shift registers, providing it with the frame enable signal as an input signal. In this case, the frame enable signal line includes multiple branches, each branch corresponding to the signal input terminal of the first shift register in the scan sequence within each set of shift registers. Accordingly, a switching transistor can be configured on each branch, and the frame enable signal can be written to each branch in turn through timing control. Of course, in this case, there can also be multiple frame enable signal lines, each corresponding to the signal input terminal of the first shift register in the scan sequence within each set of shift registers. In this case, it is necessary to control the frame enable signal line to be selected according to a preset scan sequence.

[0094] In this embodiment, the frame enable signal line includes at least two disconnected signal segments 11 and a transition electrode 2 connecting two adjacent signal segments 11; the transition electrode 2 and the signal segments 11 are located on different layers. Furthermore, the length of the current path formed by the connection of the signal segments 11 through the transition electrode 2 is greater than the sum of the lengths of all signal segments 11. This method increases the electrostatic discharge path, thereby solving the problem of a single frame enable signal line, few discharge paths, and susceptibility to ESD damage that could burn out the aperture structure and shift register, leading to abnormal screen display.

[0095] In some examples, both the shift register and the redundant shift register in this embodiment can be the shift register described above. In the following description, it is only assumed that both the shift register and the redundant shift register can be the shift register described above. For the thin-film transistors in the shift register and the redundant shift register, and even the thin-film transistors in the pixel unit, bottom-gate thin-film transistors are used as an example.

[0096] Specifically, Figure 4 is a schematic diagram of the film layers of the display substrate according to an embodiment of this disclosure; as shown in Figure 4, the display substrate includes a first conductive layer 100, a first interlayer insulating layer 3, a second conductive layer 200, a second interlayer insulating layer 4, and a third conductive layer 300 sequentially disposed along a direction away from the substrate 10. The gate of the thin-film transistor is located in the first conductive layer 100, the source and drain of the thin-film transistor are located in the second conductive layer 200, and each common electrode is located in the third conductive layer 300. Each signal segment 11 of the frame enable signal line in this embodiment of the disclosure is located in the first conductive layer 100.

[0097] Based on the above film structure and the specific structure of the transfer electrode 2, the specific connection method between the signal line segment 11 and the transfer electrode 2 will be explained.

[0098] First example: Figure 5 is a cross-sectional view along line A-A' in Figure 3; as shown in Figures 3 and 5, the adapter electrode 2 includes a first adapter portion 21, a second adapter portion 22, and a third adapter portion 23. The first adapter portion 21 and the second adapter portion 22 are located on the same layer, and both can be located on the third conductive layer 300. The third adapter portion 23 is located on a different layer from the first adapter portion 21, and the third adapter portion 23 can be disposed on the second conductive layer 200. The first adapter portion 21 is connected to the third adapter portion 23 through at least one first connection via 101, and the second adapter portion 22 is connected to the third adapter portion 23 through at least one second connection via 102. The first connection via 101 and the second connection via 102 penetrate the second interlayer insulating layer 4. In this case, since the signal segment 11 is located in the first conductive layer 100, for two adjacent signal segments 11 and the adapter electrode 2 connecting the two, one signal segment 11 is connected to the first adapter portion 21 of the adapter electrode 2 through at least one third connection via 103, and the other signal segment 11 is connected to the second connection portion of the adapter electrode 2 through at least one fourth connection via 104; the third connection via 103 and the fourth connection via 104 penetrate the first interlayer insulating layer 3 and the second interlayer insulating layer 4.

[0099] In this example, the first adapter 21 and the second adapter 22 are both disposed on different layers from the third adapter 23. The first adapter 21 and the third adapter 23 are connected by a first connection via 101 penetrating the second interlayer insulating layer 4, and the second adapter 22 and the third adapter 23 are connected by a second connection via 102 penetrating the second interlayer insulating layer 4. This structure increases the conductive path of the adapter electrode 2. Connecting adjacent signal segments 11 with this structure further increases the conductive path of the frame-on signal line, thereby preventing ESD-induced burn-out of the hole structure and shift register, which could cause abnormal screen display. Furthermore, since the first adapter 21 and the second adapter 22 are located on the third conductive layer 300, and the third adapter 23 is located on the second conductive layer 200, the thickness of the display substrate is not increased, nor is the manufacturing cost increased.

[0100] Referring again to Figure 3, the number of first connecting vias 101 depends on the size of the overlap area between the first adapter 21 and the third adapter 23. A larger overlap area between the orthographic projections of the first adapter 21 and the third adapter 23 onto the substrate 10 results in a larger number of first connecting vias 101. Similarly, the number of second connecting vias 102 depends on the size of the overlap area between the second adapter 22 and the third adapter 23; the number of third connecting vias 103 depends on the overlap area between the signal segment 11 and the first adapter 21; and the number of fourth connecting vias 104 depends on the overlap area between the signal segment 11 and the second adapter 22. Taking the arrangement of the first connecting vias 101 connecting the first adapter 21 and the third adapter 23 as an example, multiple first connecting vias 101 can be arranged in an array. The size, number, and spacing between adjacent first connecting vias 101 can be set according to the specific product requirements.

[0101] In one example, referring to FIG5, the orthographic projection of the third transition portion 23 on the substrate 10 is located between the orthographic projections of two adjacent signal segments 11 on the substrate 10, and does not overlap with the orthographic projections of the signal segments 11 on the substrate 10. The conductive path of the frame-on signal line is signal segment 11 → first transition portion 21 → third transition portion 23 → second transition portion 22 → signal segment 11. Compared with related technologies, this extends the conductive path and effectively reduces the risk of ESD.

[0102] In another example, FIG6 is a top view of the connection between signal segment 11 and adapter electrode 2 in a first example of the present disclosure embodiment; FIG7 is a cross-sectional view along B-B' of FIG6; referring to FIG6 and 7, the orthographic projection of the third adapter portion 23 on the substrate 10 overlaps with the orthographic projection of the adjacent signal segment 11 on the substrate 10. For example, the third adapter portion 23 has a first end and a second end disposed opposite to each other along its extension direction. For two adjacent signal segments 11, one signal segment 11 at least partially overlaps with the orthographic projection of the first end of the third adapter portion 23 on the substrate 10 and is connected to the first end of the third adapter portion 23 through at least one fifth connection via 105 penetrating the first interlayer insulating layer 3; the other signal segment 11 at least partially overlaps with the orthographic projection of the second end of the third adapter portion 23 on the substrate 10 and is connected to the second end of the third adapter portion 23 through at least one sixth connection via 106 penetrating the first interlayer insulating layer 3. In this case, the conductive path of the frame enable signal line is changed from a single path in the related technology to two paths. One path is signal segment 11 → first transition part 21 → third transition part 23 → second transition part 22 → signal segment 11, and the other path is signal segment 11 → third transition part 23 → signal segment 11. This method extends the conductive path and effectively reduces the risk of ESD.

[0103] Furthermore, the size, quantity, and arrangement of the fifth connecting via 105 and the sixth connecting via 106 in this example can all adopt the setting method of the first connecting via 101 described above, so they will not be repeated here.

[0104] The second example: This example has a structure that is largely the same as the first example, except that the shape of the third adapter portion 23 of the adapter electrode 2 and the signal line segment 11 is different from the example above. Please refer to the following description for details.

[0105] First case: Figure 8 is a partial top view of the connection between signal segment 11 and adapter electrode 2 in the first case of the second example of the present disclosure embodiment; as shown in Figure 8, when the orthographic projection of the third adapter portion 23 of the adapter electrode 2 on the substrate 10 is located between two adjacent signal segments 11 and does not overlap with the orthographic projection of the signal segments 11 on the substrate 10, for two adjacent signal segments 11 and the adapter electrode 2 for connecting the two, the third adapter portion 23 of the adapter electrode 2 has a first end and a second end disposed opposite to each other along its extension direction, and a signal segment 11 has a first end and a second end disposed opposite to each other through the first adapter portion 21 and the third adapter portion 23. One end is connected to a third end, and the other signal line segment 11 has a fourth end connected to the second end of the third transition portion 23 via the second transition portion 22; the orthographic projection of the first end on the substrate 10 is wider the closer it is to the orthographic projection of the third end on the substrate 10; the orthographic projection of the second end on the substrate 10 is wider the closer it is to the orthographic projection of the fourth end on the substrate 10; the orthographic projection of the third end on the substrate 10 is wider the closer it is to the orthographic projection of the first end on the substrate 10; the orthographic projection of the fourth end on the substrate 10 is wider the closer it is to the orthographic projection of the second end on the substrate 10. For example, the first end and the second end of the aforementioned third transition portion 23, the third end of one signal line segment 11 located on both sides of the third transition portion 23, and the fourth end of another signal line segment 11 are all isosceles trapezoids. The first end is connected to the first adapter 21 through the first connecting through hole 101, the second end is connected to the second adapter 22 through the second connecting through hole 102, the third end is connected to the first adapter 21 through the third connecting through hole 103, and the fourth end is connected to the second adapter 22 through the fourth connecting through hole 104.

[0106] Based on the pattern design of the signal segment 11 and the third adapter 23 described above, the orthographic projection of the first adapter 21 on the substrate 10 covers the orthographic projections of the first end and the third end on the substrate 10, and the orthographic projection of the second adapter 22 on the substrate 10 covers the orthographic projections of the second end and the fourth end on the substrate 10. In this case, compared to a linear signal segment 11 and the third adapter 23, more first connecting vias 101 and second connecting vias 102 can be provided at the positions corresponding to the first and second ends of the third adapter 23 in this pattern; more third connecting vias 103 can be provided at the position corresponding to one signal segment 11; and more fourth connecting vias 104 can be provided at the position corresponding to another signal segment 11. In this way, under the same current, the current borne by a single connecting via is reduced, which is equivalent to increasing the area for electrostatic discharge.

[0107] Furthermore, referring to Figure 8, multiple first connecting vias 101 are arranged in multiple columns, and the number of first connecting vias 101 in each column is positively correlated with the linewidth of the first end; that is, the wider the linewidth of the first end, the more first connecting vias 101 are in a corresponding column. Similarly, there are multiple second connecting vias 102 at the second end, and these multiple second connecting vias 102 are arranged in multiple columns, with the number of second connecting vias 102 in each column being positively correlated with the linewidth of the second end; there are multiple third connecting vias 103 at the third end, and these multiple third connecting vias 103 are arranged in multiple columns, with the number of third connecting vias 103 in each column being positively correlated with the linewidth of the third end; there are multiple fourth connecting vias 104 at the fourth end, and these multiple fourth connecting vias 104 are arranged in multiple columns, with the number of fourth connecting vias 104 in each column being positively correlated with the linewidth of the fourth end.

[0108] In the second case, Figure 9 is a partial top view of the connection between signal segment 11 and adapter electrode 2 in the second case of the second example of the present disclosure embodiment. Referring to Figure 9, when the orthographic projection of the third adapter portion 23 on the substrate 10 overlaps with the orthographic projection of the adjacent signal segment 11 on the substrate 10, for the two adjacent signal segments 11 and the adapter electrode 2 used to connect the two, the third adapter portion 23 of the adapter electrode 2 has a first end and a second end disposed opposite to each other along its extension direction, one signal segment 11 has a third end connected to the first end of the third adapter portion 23 through the first adapter portion 21, and the other signal segment 11 has a fourth end connected to the second end of the third adapter portion 23 through the second adapter portion 22; the orthographic projection of the first end on the substrate 10 is wider the closer it is to the orthographic projection of the third end on the substrate 10; the orthographic projection of the second end on the substrate 10 is wider the closer it is to the orthographic projection of the fourth end on the substrate 10. The first end is connected to the first adapter 21 through the first connecting through hole 101, the second end is connected to the second adapter 22 through the second connecting through hole 102, the third end is connected to the first adapter 21 through the third connecting through hole 103, and the fourth end is connected to the second adapter 22 through the fourth connecting through hole 104. The first end is connected to the third end through the fifth connecting through hole 105, and the second end is connected to the fourth end through the sixth connecting through hole 106.

[0109] Based on the pattern design of the signal segment 11 and the third adapter 23 described above, the orthographic projection of the first adapter 21 on the substrate 10 covers the orthographic projections of the first connecting via 101, the third connecting via 103, and the fifth connecting via 105 on the substrate 10. The orthographic projection of the second adapter 22 on the substrate 10 covers the orthographic projections of the second connecting via 102, the fourth connecting via 104, and the sixth connecting via 106 on the substrate 10. The orthographic projection of the fifth connecting via 105 on the substrate 10 is located within the area defined by the orthographic projections of the first connecting via 101 and the third connecting via 103 on the substrate 10; the orthographic projection of the sixth connecting via 106 on the substrate 10 is located within the area defined by the orthographic projections of the second connecting via 102 and the fourth connecting via 104 on the substrate 10.

[0110] Referring again to Figure 9, the first end of the third connecting portion 23 includes a first extension portion and a second extension portion; the second end includes a third extension portion and a fourth extension portion. The orthographic projections of the first extension portion 231 and the second extension portion 232 on the substrate 10 do not overlap with the orthographic projection of the third end of the signal line segment 11 on the substrate 10; the orthographic projections of the third extension portion and the fourth extension portion on the substrate 10 do not overlap with the orthographic projection of the fourth end of the signal line segment 11 on the substrate 10. In other words, the first extension portion 231 and the second extension portion 232 are the portions of the first end that extend beyond the first transition portion 21, and the third extension portion and the fourth extension portion are the portions of the second end that extend beyond the second transition portion 22.

[0111] Furthermore, at least a portion of the first connecting via 101 and the first extension 231 overlap in their orthographic projections on the substrate 10; at least a portion of the first connecting via 101 and the second extension 232 overlap in their orthographic projections on the substrate 10. At least a portion of the second connecting via 102 and the third extension overlap in their orthographic projections on the substrate 10; at least a portion of the second connecting via 102 and the fourth extension overlap in their orthographic projections on the substrate 10. This ensures that both the first extension 231 and the second extension 232 of the third connecting portion 23 can connect to the first adapter 21, and that both the third and fourth extensions of the third connecting portion 23 can connect to the second adapter 22, thereby dispersing current and reducing ESD risk.

[0112] The third example: Figure 10 is a top view of the connection between the signal segment 11 and the adapter electrode 2 in the third example of the present disclosure; Figure 11 is a cross-sectional view along C-C' in Figure 10; as shown in Figures 10 and 11, this example has a structure that is largely the same as the first example, except that the adapter electrode 2 in this example includes not only the first adapter portion 21, the second adapter portion 22, and the third adapter portion 23, but also a fourth adapter portion 24. The second adapter portion 22 is located between adjacent signal segments 11 and is connected to the third adapter portion 23 through at least one seventh connection via 107; the seventh connection via 107 penetrates the first interlayer insulating layer 3. That is, the fourth adapter portion 24 and the signal segment 11 are disposed on the same layer and are both located in the first conductive layer 100. Since the third adapter portion 23 and the fourth adapter portion 24 are connected, it is equivalent to increasing the thickness of the third adapter portion 23, which can improve the current withstand value of the conductive line of the frame opening signal. Moreover, the increased thickness of the conductive structure can reduce the resistance and effectively improve the risk of ESD.

[0113] The above only provides a few exemplary structures of signal segment 11 and adapter electrode 2, as well as their connection relationship. However, this does not constitute a limitation on the scope of protection of the present disclosure. Any modifications or similar improvements based on this are within the scope of protection of the present disclosure.

[0114] In some examples, the display substrate in this disclosure can reduce the risk of ESD not only by extending the conductive path of the frame enable signal, but also by using a redundant shift register located in the peripheral area as an electrostatic discharge unit. The structure of each sub-circuit of the redundant shift register can adopt the same structure as shown in Figure 2 above, and therefore will not be described again here. The output sub-circuit of the redundant shift register in this disclosure embodiment is disconnected from the other sub-circuits.

[0115] In the first embodiment, Figure 12 illustrates a connection between the frame enable signal line STV and the redundant shift register according to an embodiment of this disclosure. As shown in Figure 12, at least one of the gate of the sixth transistor M16 in the auxiliary sub-circuit and the source of the eighth transistor M8 in the pull-down sub-circuit is connected to the frame enable signal line STV. Figure 12 only illustrates an example where the frame enable signal line STV is simultaneously connected to the gate of the sixth transistor M16 and the source of the eighth transistor M8 in the pull-down sub-circuit. In this case, since the frame enable signal line STV is located in the first conductive layer 100, and the gate of M16 is also located in the first conductive layer, they can be directly connected. However, the source of the eighth transistor M8 is located in the second conductive layer, therefore the frame enable signal line STV and the source of the eighth transistor M8 need to be connected through a via penetrating the first interlayer insulating layer.

[0116] The second method: Figure 13 shows another connection method between the frame enable signal line STV and the redundant shift register according to an embodiment of this disclosure. As shown in Figure 13, the frame enable signal line STV is connected to at least one of the gate of the sixth transistor M6 in the pull-down circuit and the redundant clock signal line CLK. Figure 13 only uses the example of the frame enable signal line STV being connected to the gate of the sixth transistor M6 in the pull-down circuit and the redundant clock signal line CLK. The connection of the frame enable signal line STV to both ends of the redundant clock signal line CLK in Figure 13 means that the enable signal line STV can be connected to either end of the redundant clock signal line CLK. In practical applications, the enable signal line STV cannot be connected to both ends of the redundant clock signal line CLK simultaneously. In this case, since both the gate of the sixth transistor M6 and the frame enable signal line STV are located in the first conductive layer 100, they can be directly connected. Since the redundant clock signal line CLK is located in the conductive layer, the redundant clock signal line CLK and the frame enable signal line STV need to be connected through a via penetrating the first interlayer insulating layer.

[0117] The third method, as shown in Figure 14, is another connection between the frame enable signal line STV and the redundant shift register according to an embodiment of this disclosure. As shown in Figure 14, at least one of the source and drain of the third transistor M3 in the output sub-circuit is connected to the frame enable signal line STV. In this case, since the frame enable signal line STV is located in the first conductive layer 100 and the source and drain of the third transistor M3 are located in the second conductive layer 200, the frame enable signal line STV can be connected to at least one of the source and drain of the third transistor M3 through a via penetrating the first interlayer insulating layer 3.

[0118] It should be noted that the above only provides a few exemplary connection relationships between the frame enable signal line STV and the redundant shift register. In practical applications, as long as the frame enable signal line STV is connected to the redundant shift register for electrostatic discharge, it is acceptable.

[0119] Regardless of the method used, the transistors or redundant clock signal lines of the redundant shift register can be directly connected or coupled when connected to the frame enable signal line STV. When coupled, a first tip structure 201 is connected to the structure coupled to the frame enable signal line STV, and a second tip structure 202 is connected to the frame enable signal line STV. The tips of the first tip structure 201 and the second tip structure 202 are opposite each other, as shown in Figure 15. Alternatively, as shown in Figure 16, the first tip structure 201 can be composed of a first main body 2011 and at least one first tip 2012 connected to one side of the first main body 2011 extending in the direction of extension. The second tip structure 202 can be composed of a second main body 2021 and at least one second tip 2022 connected to one side of the second main body 2021 extending in the direction of extension. The first tip 2012 and the second tip 2022 are opposite each other.

[0120] This disclosure also provides a display device, which includes the display substrate described above.

[0121] The display devices disclosed herein include, but are not limited to, any products or components with display functions such as mobile phones, tablets, televisions, monitors, laptops, digital photo frames, and navigators. The embodiments of the present invention are not limited thereto.

[0122] It is understood that the above embodiments are merely exemplary implementations used to illustrate the principles of the present invention, and the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A display substrate, comprising: The substrate is divided into a display area and a peripheral area located on at least one side of the display area; A gate drive circuit and a frame enable signal line are disposed on the substrate, located in the peripheral region. The frame enable signal line is configured to provide a frame enable signal to at least one shift register in the gate drive circuit. The frame enable signal line includes at least two disconnected signal segments and a transition electrode connecting two adjacent signal segments; the transition electrode and the signal segments are located on different layers.

2. The display substrate according to claim 1, wherein, Also includes: A first conductive layer is disposed on the substrate, and the gates of each thin-film transistor of the shift register are located in the first conductive layer; The first interlayer insulating layer is disposed on the side of the first conductive layer away from the substrate. The second conductive layer is disposed on the side of the first interlayer insulating layer away from the first conductive layer, and the source and drain of each thin film transistor of the shift register are located in the second conductive layer. The second interlayer insulating layer is disposed on the side of the second conductive layer that is opposite to the first interlayer insulating layer; The third conductive layer is disposed on the side of the second interlayer insulating layer away from the second conductive layer, and the common electrode of the pixel unit located in the display area is located in the third conductive layer.

3. The display substrate according to claim 2, wherein, The adapter electrode includes a first adapter portion, a second adapter portion, and a third adapter portion; the first adapter portion and the second adapter portion are located in the third conductive layer, the third adapter portion is located in the second conductive layer, and the first adapter portion and the second adapter portion are respectively connected to the third adapter portion through at least one first connection via and at least one second connection via; the first connection via and the second connection via both penetrate the second interlayer insulating layer; The signal line segment is located in the first conductive layer. For two adjacent signal line segments, one is connected to the first adapter through at least one third connecting via, and the other is connected to the second adapter through at least one fourth connecting via. Both the third connecting via and the fourth connecting via penetrate the first interlayer insulation layer and the second interlayer insulation layer.

4. The display substrate according to claim 3, wherein, The orthographic projections of the third adapter and the signal line segment on the substrate do not overlap, and the orthographic projection of one of the third adapters on the substrate is located between two adjacent orthographic projections of the signal line segment on the substrate. For two adjacent signal segments and a connecting electrode for connecting them, the third connecting portion of the connecting electrode has a first end and a second end disposed opposite to each other along its extending direction; one signal segment has a third end connected to the first end of the third connecting portion via the first connecting portion; and the other signal segment has a fourth end connected to the second end of the third connecting portion via the second connecting portion. The orthographic projection of the first end on the substrate is wider the closer it is to the orthographic projection of the third end on the substrate; the orthographic projection of the second end on the substrate is wider the closer it is to the orthographic projection of the fourth end on the substrate; the orthographic projection of the third end on the substrate is wider the closer it is to the orthographic projection of the first end on the substrate; and the orthographic projection of the fourth end on the substrate is wider the closer it is to the orthographic projection of the second end on the substrate.

5. The display substrate according to claim 4, wherein, The orthographic projection of the first connecting via used to connect the third adapter and the first adapter on the substrate is covered by the orthographic projection of the first end on the substrate. The orthographic projection of the second connecting via used to connect the third adapter and the second adapter on the substrate is covered by the orthographic projection of the second end on the substrate. The orthogonal projection of the third connection via used to connect the signal line segment and the first adapter on the substrate is covered by the orthogonal projection of the third end on the substrate. The orthogonal projection of the fourth connection via used to connect the signal line segment and the second adapter on the substrate is covered by the orthogonal projection of the fourth end on the substrate. The orthographic projection of the first adapter portion on the substrate covers the orthographic projections of the first end portion and the third end portion on the substrate. The orthographic projection of the second adapter on the substrate covers the orthographic projections of the second end and the fourth end on the substrate.

6. The display substrate according to claim 5, wherein, The first end has multiple first connection vias, and the multiple first connection vias are arranged in multiple columns. The number of first connection vias in each column is positively correlated with the line width of the first end. The second end has multiple second connection vias, and the multiple second connection vias are arranged in multiple columns. The number of second connection vias in each column is positively correlated with the line width of the second end. The third connection vias located at the third end are multiple, and the multiple third connection vias are arranged in multiple columns. The number of third connection vias in each column is positively correlated with the line width of the third end. The fourth connection vias located at the fourth end are multiple, and the multiple fourth connection vias are arranged in multiple columns. The number of fourth connection vias in each column is positively correlated with the line width of the fourth end.

7. The display substrate according to claim 3, wherein, For two adjacent signal segments, one is connected to the third adapter through at least one fifth connecting via, and the other is connected to the third adapter through at least one sixth connecting via; both the fifth connecting via and the sixth connecting via penetrate the first interlayer insulation layer.

8. The display substrate according to claim 7, wherein, For two adjacent signal segments and a connecting electrode for connecting them, the third connecting portion of the connecting electrode has a first end and a second end disposed opposite to each other along its extending direction; one signal segment has a third end connected to the first end of the third connecting portion via the first connecting portion; the other signal segment has a fourth end connected to the second end of the third connecting portion via the second connecting portion; the orthographic projection of the first end on the substrate is wider the closer it is to the orthographic projection of the third end on the substrate; the orthographic projection of the second end on the substrate is wider the closer it is to the orthographic projection of the fourth end on the substrate. The orthographic projection of the first end on the substrate covers the orthographic projection of the third end on the substrate; The orthographic projection of the second end on the substrate covers the orthographic projection of the fourth end on the substrate.

9. The display substrate according to claim 8, wherein, The fifth connection via is projected onto the substrate and is located within the area defined by the projected projections of the first connection via and the third connection via onto the substrate. The sixth connection via is projected onto the substrate and is located within the area defined by the projections of the second and fourth connection vias onto the substrate.

10. The display substrate according to claim 8, wherein, The first end portion includes a first extension portion and a second extension portion; the second end portion includes a third extension portion and the fourth extension portion; The orthographic projections of the first extension portion and the second extension portion on the substrate do not overlap with the orthographic projection of the third end portion on the substrate. The orthographic projections of the third extension and the fourth extension on the substrate do not overlap with the orthographic projection of the fourth end on the substrate. At least a portion of the first connecting via overlaps with the orthographic projection of the first extension portion on the substrate. At least a portion of the first connecting via overlaps with the orthographic projection of the second extension portion onto the substrate. At least a portion of the second connecting via overlaps with the orthographic projection of the third extension on the substrate. At least a portion of the second connecting via overlaps with the orthographic projection of the fourth extension on the substrate.

11. The display substrate according to claim 3, wherein, The adapter electrode further includes a fourth adapter portion; the second adapter portion is located between adjacent signal segments and is connected to the third adapter portion through at least one seventh connection via; the seventh connection via penetrates the first interlayer insulation layer.

12. The display substrate according to any one of claims 1-11, wherein, It also includes redundant shift registers located in the peripheral area; The redundant shift register includes: an input sub-circuit, an output sub-circuit, at least one pull-down control sub-circuit, and at least one pull-down sub-circuit. The input sub-circuit is configured to pre-charge the pull-up node in response to an input signal at the signal input terminal; the connection node between the input sub-circuit, the output sub-circuit, and the pull-down sub-circuit; The output sub-circuit is configured to output a clock signal through a signal output terminal in response to the potential of the pull-up node. The output sub-circuit is configured to output a clock signal through a cascaded signal terminal in response to the potential of the pull-up node. The pull-down control subcircuit is configured to respond to the power supply voltage and control the potential of the pull-down node through the power supply voltage; one of the pull-down control subcircuits connects one of the pull-down subcircuits and one of the pull-down subcircuits, and the connection node between the two is the pull-down node; The pull-down sub-circuit is configured to pull down the potential of the pull-up node by a non-operating level signal in response to the potential of the pull-up node.

13. The display substrate according to claim 12, wherein, The output sub-circuit includes: a third transistor and a storage capacitor; The first end of the storage capacitor is connected to the gate of the third transistor, and the second end of the storage capacitor is connected to the drain of the third transistor; at least one of the source and drain of the third transistor is connected to the frame enable signal line.

14. The display substrate according to claim 12, wherein, The output sub-circuit includes: a third transistor and a storage capacitor; The first end of the storage capacitor is connected to the gate of the third transistor, and the second end of the storage capacitor is connected to the drain of the third transistor; at least one of the source and drain of the third transistor is connected to the first tip structure, and the frame enable signal line is connected to the second tip structure. The tip of the first tip structure is opposite to the tip of the second tip structure; or, The first tip structure includes a first body portion and at least one first tip portion connected to one side of the first body portion extending in the direction of extension; the second tip structure includes a second body portion and at least one second tip portion connected to one side of the second body portion extending in the direction of extension; the first tip portion and the second tip portion are opposite to each other.

15. The display substrate according to claim 12, wherein, The pull-down control sub-circuit includes a fifth transistor and a ninth transistor; the pull-down circuit includes a sixth transistor and an eighth transistor; The gate of the fifth transistor is connected to the drain of the ninth transistor and the source of the eighth transistor. The source of the fifth transistor is connected to the power supply voltage terminal and the gate of the ninth transistor. The drain of the fifth transistor is connected to the pull-down node. The gate of the sixth transistor is connected to the gate of the eighth transistor and the pull-up node, and the source of the sixth transistor is connected to the pull-down node; the drains of the sixth transistor and the eighth transistor are both connected to a non-operating level signal terminal. The frame enable signal line is connected to the source of the eighth transistor, and / or the frame enable signal line is connected to the gate of the sixth transistor.

16. The display substrate according to claim 12, wherein, The pull-down control sub-circuit includes a fifth transistor and a ninth transistor; the pull-down circuit includes a sixth transistor and an eighth transistor; The gate of the fifth transistor is connected to the drain of the ninth transistor and the source of the eighth transistor. The source of the fifth transistor is connected to the power supply voltage terminal and the gate of the ninth transistor. The drain of the fifth transistor is connected to the pull-down node. The gate of the sixth transistor is connected to the gate of the eighth transistor and the pull-up node, and the source of the sixth transistor is connected to the pull-down node; the drains of the sixth transistor and the eighth transistor are both connected to a non-operating level signal terminal. One of the source of the eighth transistor and the gate of the sixth transistor is connected to the first tip structure, and the frame enable signal line is connected to the second tip structure. The tip of the first tip structure is opposite to the tip of the second tip structure; or, The first tip structure includes a first body portion and at least one first tip portion connected to one side of the first body portion in the extending direction; The second tip structure includes a second body portion and at least one second tip portion connected to one side of the second body portion in the extending direction; the first tip portion and the second tip portion are opposite each other.

17. The display substrate according to any one of claims 1-11, wherein, It also includes a redundant clock signal line, and the frame enable signal line is connected to the redundant clock signal line.

18. A display device comprising a display substrate according to any one of claims 1-17.

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