Array substrate and display panel

Abstract

Disclosed in the present invention are an array substrate and a display panel. The array substrate comprises: a common electrode layer; and a pixel electrode layer, located on the side of the common electrode layer facing away from data lines, and comprising a plurality of pixel electrode rows extending in a first direction, wherein each pixel electrode row comprises a plurality of pixel electrode groups arranged in the first direction, each pixel electrode group comprises two pixel electrodes, and either of the pixel electrodes in the pixel electrode group spans across the other one of the pixel electrodes and is electrically connected to a data line by means of a transistor. At least one of the common electrode layer and the pixel electrode layer comprises a plurality of first wires extending in a second direction, wherein the first wires are electrically connected to common electrodes, and the orthographic projections of the first wires on a substrate cover the orthographic projections of the data lines on the substrate.

Description

An array substrate and a display panel

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. 202411514083.6, filed on October 28, 2024, entitled "An Array Substrate and Display Panel", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This invention relates to the field of display technology, and more particularly to an array substrate and a display panel. Background Technology

[0004] At the same resolution, the dual-gate pixel architecture can reduce the number of source drivers by half compared to the single-gate pixel architecture, thereby reducing IC costs and serving as an effective low-cost solution. Summary of the Invention

[0005] This invention provides an array substrate and a display panel. The array substrate includes:

[0006] Substrate;

[0007] Multiple transistors;

[0008] Multiple gate line groups are located on one side of the substrate, and each gate line group includes two gate lines extending along the first direction;

[0009] Multiple data cables;

[0010] A common electrode layer is located on the side of the data line opposite to the substrate; the common electrode layer includes multiple common electrodes;

[0011] A pixel electrode layer, located on the side of the common electrode layer opposite to the data line, includes: a plurality of pixel electrode rows extending along a first direction; each pixel electrode row includes a plurality of pixel electrode groups arranged along the first direction; a gate line group is located in the region between adjacent pixel electrode rows, and the pixel electrode group is located in the region formed by the intersection of the gate line group and the data line; each pixel electrode group includes two pixel electrodes, and any pixel electrode in the pixel electrode group is electrically connected to the data line through the transistor across the other pixel electrode;

[0012] Wherein, at least one of the common electrode layer and the pixel electrode layer includes: a plurality of first traces extending along the second direction; the first traces are electrically connected to the common electrode, and the orthographic projection of the first traces on the substrate covers the orthographic projection of the data line on the substrate.

[0013] In one possible implementation, the first trace is located in the pixel electrode layer;

[0014] The common electrode layer has a first cutout; the orthographic projection of the first trace on the substrate overlaps with the orthographic projection of the first cutout on the substrate.

[0015] In one possible implementation, the first trace is disconnected at the location of the gate line group.

[0016] In one possible implementation, the common electrode extends along the first direction and is arranged along the second direction, and the region of the common electrode located between adjacent gate line groups is within the orthographic projection of the substrate.

[0017] The common electrode has a connection portion at at least one end of the first cutout, and the common electrode is connected to the first trace through a first via at the connection portion.

[0018] In one possible implementation, the extension length of the first trace is greater than the extension length of the first cutout.

[0019] In one possible implementation, the orthographic projection of the first trace on the substrate covers the orthographic projection of the first cutout on the substrate, and also covers the orthographic projection of the connection portion on the substrate.

[0020] In one possible implementation, the orthographic projection of the first trace on the substrate covers the orthographic projection of the common electrode on the substrate on both sides of the first cutout.

[0021] In one possible implementation, the orthographic projection of the first trace onto the substrate does not overlap with the orthographic projection of the common electrode on both sides of the first cutout onto the substrate.

[0022] In one possible implementation, the first trace is located on the common electrode layer and is integrally connected to the common electrode.

[0023] In one possible implementation, the orthogonal projection of the outer edge of the pixel electrode onto the substrate coincides with the outer edge of the data line onto the substrate.

[0024] In one possible implementation, the array substrate further includes: a plurality of second traces and a plurality of second via groups; the second via group includes: two second vias; the two second vias of the second via group are respectively located on both sides of the gate line group and on different sides of the second traces; the common electrode on both sides of the gate line group is electrically connected to the second traces through the two second vias of the second via group.

[0025] In one possible implementation, the second trace is on the same layer and made of the same material as the data line; the array substrate further includes: an organic insulating layer located between the data line and the common electrode layer, and a passivation layer located between the common electrode layer and the pixel electrode layer; the pixel electrode layer further includes: an overlap portion;

[0026] The second via penetrates the passivation layer and the organic insulating layer, and exposes a portion of the second trace and a portion of the common electrode. The overlap portion contacts the common electrode and the second trace through the second via.

[0027] In one possible implementation, the common electrode has a recess at the location of the second via; the orthographic projection of the second via onto the substrate partially overlaps with the recess and partially overlaps with the common electrode on the side of the recess away from the gate line group.

[0028] In one possible implementation, the second trace is located on the side of the common electrode layer facing the substrate and is in direct contact with the common electrode.

[0029] This disclosure also provides a display panel, which includes the array substrate as described in this disclosure. Attached Figure Description

[0030] Figure 1 is a comparative diagram of the Single gate pixel architecture and the Dual gate pixel architecture;

[0031] Figure 2 shows the timing diagram of the Dual gate pixel architecture in monochrome red image;

[0032] Figure 3 is a schematic diagram of two Dual gate pixel architectures provided in the embodiments of this disclosure;

[0033] Figure 4 is a schematic diagram of the display panel refresh;

[0034] Figure 5 is a schematic diagram of the inter-frame data signal transition in the RG color mixing image;

[0035] Figure 6 is a schematic diagram of the vertical stripe phenomenon produced when RG color mixing occurs;

[0036] Figure 7 is a schematic diagram of the vertical crosstalk pattern;

[0037] Figure 8 is a schematic diagram of the vertical crosstalk pattern changing between frames of data signals;

[0038] Figure 9 is a schematic diagram showing that the vertical crosstalk pattern is partially bright and partially dark during the inter-frame data signal transition;

[0039] Figure 10 is a schematic diagram of the array substrate structure and process flow of the related technology;

[0040] Figure 11 is a cross-sectional view of Figure 10 at the location of the data line;

[0041] Figure 12A is one of the top views of the array substrate provided in the embodiment of this disclosure;

[0042] Figure 12B is a schematic diagram of a single film layer of the gate line layer in Figure 12A;

[0043] Figure 12C is a schematic diagram of a single film layer of the data line layer in Figure 12A;

[0044] Figure 12D is a schematic diagram of a single film layer of the common electrode layer in Figure 12A;

[0045] Figure 12E is a schematic diagram of a single film layer of the pixel electrode layer in Figure 12A;

[0046] Figure 12F is a cross-sectional view along the dashed line e1 in Figure 12A;

[0047] Figure 12G is a cross-sectional schematic diagram of another array substrate provided in an embodiment of this disclosure;

[0048] Figure 13A is a second top view of the array substrate provided in an embodiment of this disclosure;

[0049] Figure 13B is a partially enlarged schematic diagram of Figure 13A;

[0050] Figure 13C is a schematic diagram of the cross section along the dashed line e2 in Figure 13A;

[0051] Figure 13D is a cross-sectional view along the dashed line e3 in Figure 13A;

[0052] Figure 13E is a schematic diagram of the cross section along the dashed line e4 in Figure 13B;

[0053] Figure 14A is a third top view of the array substrate provided in the embodiment of this disclosure;

[0054] Figure 14B is a schematic diagram of the cross section along the dashed line e5 in Figure 14A;

[0055] Figure 15 is one of the cross-sectional schematic diagrams of the display panel provided in this embodiment;

[0056] Figure 16 is a schematic diagram of the display panel structure provided in an embodiment of this disclosure. Detailed Implementation

[0057] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0058] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0059] As used herein, “approximately” or “substantially the same” includes the stated value and means within an acceptable range of deviations from the specific value, as determined by a person skilled in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., limitations of the measurement system). For example, “substantially the same” may mean a difference relative to the stated value within one or more standard deviations, or within ±30%, 20%, 10%, or 5%.

[0060] In the accompanying drawings, the thicknesses of layers, films, panels, regions, etc., are enlarged for clarity. Exemplary embodiments are described herein with reference to cross-sectional views that are schematic diagrams of idealized embodiments. Thus, deviations from the shapes shown in the drawings will be expected as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described herein should not be construed as limited to the specific shapes of the regions shown herein, but rather include deviations in shape caused, for example, by manufacturing processes. For example, regions illustrated or described as flat may typically have rough and / or non-linear characteristics. Furthermore, sharp corners illustrated may be rounded. Thus, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the regions, nor are they intended to limit the scope of the claims.

[0061] To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of known functions and known components are omitted.

[0062] As shown in Figure 1, compared to the Single Gate pixel architecture, the Dual Gate pixel architecture halves the number of data lines and doubles the number of gate lines. Therefore, the charging time of each row of pixels is also halved. In other words, the Dual Gate pixel architecture saves the number of ICs, but at the cost of pixel charging rate. Insufficient pixel charging rate will bring some image quality-related problems, such as common red-green-blue monochrome or mixed color images. For example, monochrome red (R), monochrome green (G), monochrome blue (B), red-green mixed color (yellow), red-blue mixed color (magenta), and blue-green mixed color (indigo) will all have horizontal or vertical stripes because some pixels have a long pre-charging time and some pixels do not have a short pre-charging time. Taking the dual-gate pixel architecture on the right side of Figure 1 as an example of displaying a monochrome red (R) image: the high level of each row of gate lines lasts for 4 hours (4 hours is taken as an example, but 2 hours / 3 hours / 4 hours / 5 hours / 6 hours / 7 hours are also applicable). The gate signals corresponding to sub-pixels R1 / R2 / R3 / R4 are G1 / G2 / G3 / G4, respectively, and the timing diagram is shown in Figure 2. The actual data charging time for R1 / R2 / R3 / R4 is the last hour of the 4-hour high-level time of G1 / G2 / G3 / G4, and the first 3 hours are the pre-charging time. D1 / D2 / D3 are the data signals for R1 / R2 & R3 / R4, respectively. For the three red sub-pixels R1 / R2 / R4, during the first hour of charging, the data line levels are inconsistent with the charging level of the red sub-pixel, thus pre-charging is not possible. Therefore, the actual charging time for each red sub-pixel is 1 hour (1 hour = 1.85µs in an 8K Dual gate 60Hz product). Considering signal line delay, the actual charging time is even shorter than 1.85µs. For R3, during the first hour of charging, the data signal is the same as that of R2. Since R3 and R2 need to be charged with the same data, R3's charging time is equivalent to 2 hours. This results in R3 having a higher charging rate than R1 / 2 / 4, leading to uneven screen brightness.

[0063] In the Dual Gate pixel architecture, some pixel architectures are all long-connected (each data line drives a sub-pixel with a gap of one sub-pixel, so the path from the data line to the sub-pixel it actually drives is relatively long, hence the name), as shown in Figure 3. Sub-pixels connected on the same Data line have the same color. These two architectures do not exhibit image quality issues such as horizontal, vertical, or diagonal stripes caused by different pre-charge times when displaying monochrome or mixed-color images. However, other problems exist. The main problems are mixed-color vertical stripes caused by parasitic capacitance Cpd between the data line and the pixel electrode, and V-crosstalk issues.

[0064] The mechanism of vertical line mixing caused by parasitic capacitance Cpd coupling: As shown in Figures 4, 5, and 6, the display panel charges sequentially from the opposite bonding area (DPO) to the bonding area (DP). In the current frame (N frames), the DP-side pixels have just finished charging. After a short blanking period between frames, the polarity of the Data data in the next frame flips, starting to charge the DPO-side pixels. The inter-frame polarity flip ΔVdata causes a jump in the DP-side pixel voltage Vpixel through Cpd coupling (ΔVpixel = Cpd * ΔVdata / Ctotal of (Pixel); The voltage jump of the DP-side pixel lasts for nearly a frame, so the DP-side pixel is most affected by the polarity switching between Data frames; Taking RG color mixing as an example: D1 / D2 / D4 / D5, which charge R and G, have voltage jumps during frame switching, while D3 / D6, which charges B, does not have voltage jumps during frame switching. The R and G pixel electrodes next to D1 / D2 / D4 / D5 will be pulled by the Data jump, the "-" pixel is pulled down, and the "+" pixel is pulled up, both becoming brighter; the R and G pixels next to D3 / D6 are not pulled, and their brightness remains unchanged, resulting in alternating bright and dark vertical stripes as shown in Figure 6.

[0065] The V-crosstalk mechanism caused by parasitic capacitance Cpd coupling: As shown in Figure 7, with a grayscale of 127 as the background and a grayscale of 255 in the middle, the grayscale pattern of 255 occupies 1 / 2 of the vertical length of the entire display panel in the vertical (V) direction. Figure 8 shows a schematic diagram of the voltage jump of the Data line at different positions of the display panel in Figure 7 under the V-crosstalk pattern. The V-Crosstalk phenomenon caused by parasitic capacitance Cpd coupling is shown in Figure 9. It will cause the display panel to be partially dark and partially bright in the vertical direction. That is, as shown in Figure 9, area ① will be dark due to coupling, and area ③ will be bright due to coupling.

[0066] Employing a fully long-connected dual-gate pixel architecture can mitigate the head-shaking effect through high resolution and high refresh rates. Specifically, as shown in Figure 3, this architecture presents two columns of sub-pixels with the same polarity across the entire display panel. Because the voltage setting of the common electrode makes it difficult to ensure completely consistent brightness across all sub-pixels at the same grayscale, especially between sub-pixels with positive and negative polarities relative to the common electrode, the brightness displayed by these sub-pixels differs when displaying the same grayscale. This inconsistency leads to head-shaking (where the human eye, in a non-static state, misses some frames, causing the eye to continuously see either positive or negative frames, resulting in alternating bright and dark lines). The fully long-connected dual-gate architecture widens the intervals between bright and dark areas, making this difference more easily perceptible to the human eye, thus exacerbating the head-shaking effect. However, using this design on a higher resolution (PPI) display panel reduces the size of the sub-pixels, mitigating the head-shaking effect; or a high refresh rate can prevent the human eye from discerning this difference.

[0067] To ensure high transmittance and driving capability requirements for this type of high refresh rate, high PPI display panel, a high transmittance advanced dimension switch (HADS) display mode is typically used. Organic films are employed in the manufacturing process to reduce the load on the data signal lines. Referring to Figures 10 and 11, the pixel planar diagram and process flow of HADS are typically as shown in Figure 10. The TFT substrate process is: Gate metal → insulating layer → semiconductor layer → source / drain metal layer (including data lines) → organic insulating layer ORG → transparent pixel electrode → insulating layer → common electrode layer. Because the characteristic of the HADS pixel mode is that the transparent common electrode must completely cover the data lines to shield the electric field of the data lines, the area of ​​the black matrix above the data lines can be minimized (in this pixel structure, the black matrix is ​​only used to prevent color crosstalk between adjacent sub-pixels when there is a large misalignment between the color filter substrate and the array substrate), thus improving the pixel aperture ratio. The ORG layer is placed on the source... After the metal layer is exposed, the parasitic capacitance between the data line and the common electrode covering it can be reduced. On the one hand, this can reduce the load on the data line and improve the pixel charging rate; on the other hand, it can also reduce the coupling effect of the data line jump on the common electrode and reduce the risk of H-crosstalk. The cross-sectional view of this pixel structure above the data line is shown in Figure 11. In order to ensure the light transmission efficiency of the pixel, the projection of the pixel electrode edge is set between the two patterns of the common electrode layer (referring to the pattern covering the data line and the adjacent common electrode pattern in the common electrode layer). However, even with this setting, there is still a large lateral parasitic capacitance Cpd between the data line and the pixel electrode through the organic insulating layer.

[0068] Referring to Figures 12A-12F, where Figure 12B is a schematic diagram of a single film layer of the gate line layer in Figure 12A, Figure 12C is a schematic diagram of a single film layer of the data line layer in Figure 12A, Figure 12D is a schematic diagram of a single film layer of the common electrode layer in Figure 12A, Figure 12E is a schematic diagram of a single film layer of the pixel electrode layer in Figure 12A, and Figure 12F is a cross-sectional schematic diagram along the dashed line e1 in Figure 12A, this disclosure provides an array substrate, comprising:

[0069] Substrate 1;

[0070] Multiple transistors T;

[0071] Multiple gate line groups 20 are located on one side of the substrate 1. Each gate line group 20 includes two gate lines 2 extending along a first direction X.

[0072] Multiple data cables 3;

[0073] A common electrode layer 40 is located on the side of the data line 3 away from the substrate 1; the common electrode layer 40 includes a plurality of common electrodes 4;

[0074] The pixel electrode layer 50, located on the side of the common electrode layer 40 away from the data line 3, includes: a plurality of pixel electrode rows 500 extending along a first direction X; the pixel electrode rows 500 include a plurality of pixel electrode groups PZ arranged along the first direction X; the gate line group 20 is located in the region between adjacent pixel electrode rows 500, and the pixel electrode group PZ is located in the region formed by the intersection of the gate line group 20 and the data line 3; the pixel electrode group PZ includes two pixel electrodes 5, and any pixel electrode 5 in the pixel electrode group PZ is electrically connected to the data line 3 through a transistor T across the other pixel electrode 5;

[0075] Among them, at least one of the common electrode layer 40 and the pixel electrode layer 50 includes: a plurality of first traces 6 extending along the second direction Y; the first traces 6 are electrically connected to the common electrode 4, and the orthographic projection of the first traces 6 on the substrate 1 covers the orthographic projection of the data line 3 on the substrate 1.

[0076] In this embodiment, any pixel electrode 5 in the pixel electrode group PZ is electrically connected to the data line 3 via a transistor T across another pixel electrode 5, which is a fully connected pixel architecture. This avoids image quality problems such as horizontal, vertical, and diagonal lines caused by different pre-charging times when displaying monochrome or mixed-color images. Moreover, in this embodiment, the array substrate includes a first trace 6 electrically connected to the common electrode 4 and covering the data line 3, which can have a high aperture ratio, high transmittance, high pixel charging rate, and reduced horizontal crosstalk. In addition, the pixel electrode layer 50 is located on the side of the common electrode layer 40 away from the data line 3, which can make the pixel electrode 5 and the data line 3 farther apart in the direction perpendicular to the substrate 1, with more insulating layers between them. This can reduce the parasitic capacitance Cpd between the pixel electrode 5 and the data line 3, improve the vertical line defects and vertical crosstalk problems caused by the parasitic capacitance Cpd when displaying monochrome or mixed-color images.

[0077] In one possible implementation, as shown in FIG3, in this embodiment of the present disclosure, the sub-pixels electrically connected to the same data line can have the same color. That is, color resists of the same color can be provided in the corresponding areas of the color filter substrate in each pixel electrode region electrically connected to the same data line by using transistors, thereby making the sub-pixels electrically connected to the same data line have the same color.

[0078] The array substrate of this disclosure can be applied to display products with high resolution and high refresh rate. In this disclosure, it is suitable for display products with a resolution (PPI) ≥ 27 inches 4K, i.e., products with a PPI of 160 or higher; and for display panels with a refresh rate ≥ 120Hz. That is, in this disclosure, the resolution of the display panel can be 160 or higher, and the refresh rate can be higher than 120Hz. This disclosure is applicable to high refresh rate or high resolution products. For cost considerations, it utilizes a fully long-connected Dual-gate pixel architecture to avoid the horizontal and vertical stripe problems caused by charging rate in monochrome and mixed-color display products of the prior art. Furthermore, it proposes to reduce or eliminate the parasitic capacitance Cpd between the pixel electrode and the data line for the high-transmittance HADS pixel architecture, improving the poor image quality caused by parasitic capacitance Cpd coupling in the fully long-connected Dual-gate pixel architecture.

[0079] In one possible implementation, as shown in Figures 12A-12F, the first trace 6 is located in the pixel electrode layer 50; the common electrode layer 40 has a first cutout 41; the orthographic projection of the first trace 6 onto the substrate 1 overlaps with the orthographic projection of the first cutout 41 onto the substrate 1. In this embodiment, the first trace 6 is located in the pixel electrode layer 50, and the common electrode layer 40 has a first cutout 41 at the location of the data line 3. The combination of the first trace 6 and the common electrode 4 can cover the data line 3 and shield the parasitic capacitance Cpd between the pixel electrode 5 and the data line 3. Moreover, the dielectric layer at the overlapping position of the data line 3 and the common electrode is a superposition of an organic film layer 92 and a passivation layer 93, which reduces the parasitic capacitance between the data line 3 and the common electrode (first trace 6) covering it. This can reduce the load on the data line, improve the pixel charging rate, and also reduce the coupling effect of the voltage polarity jump of the data line 3 on the common electrode, reducing the problem of horizontal crosstalk.

[0080] In one possible implementation, as shown in Figures 12A-12F, the orthographic projection shape of the first cutout 41 onto the substrate 1 can be consistent with the shape of the data line 3 at that location. For example, if the data line 3 is bent, the first cutout 41 is also bent.

[0081] In one possible implementation, as shown in Figures 12A-12F, the first trace 6 is disconnected at the location of the gate line group 20. In this embodiment, the first trace 6 covering the data line 3 does not need to completely cover the entire data line 3; it can be disconnected at the location of the gate line group 20. That is, at the location of the black matrix corresponding to the color filter substrate covering the gate line group 20, the first trace 6 may not cover the data line 3, further reducing the parasitic capacitance between the common electrode layer 40 and the data line 3, reducing the load on the data line, and the light leakage of the data line 3 at this location will be covered by the black matrix parallel to the gate line 2, eliminating the risk of light leakage.

[0082] In one possible implementation, referring to Figures 12A-12F, the common electrode 4 extends along the first direction X and is arranged along the second direction Y. The region between adjacent gate line groups 20 in the orthographic projection of the common electrode 4 onto the substrate 1 is within the orthographic projection of the substrate 1. The common electrode 4 has connecting portions 42 at both ends of the first cutout 41, and the common electrode 4 is connected to the first trace 6 through a first via K1 at the connecting portions 42. In this embodiment, the common electrode 4 has a connecting portion 42 at at least one end of the first cutout 41. That is, in the second direction Y, the first cutout 41 does not penetrate the common electrode 4, allowing the common electrodes 4 located on both sides of the first cutout 41 in the first direction X to be electrically connected. This avoids increasing the fabrication process of the array substrate and raising the cost of the array substrate when connecting the common electrodes 4 in the first direction X through other structures.

[0083] In one possible implementation, the common electrode 4 has a connecting portion 42 at both ends of the first cutout 41, which can improve the reliability of the connection between the first trace 6 and the common electrode 4. Accordingly, as shown in FIG12A, the first trace 6 between two adjacent gate line groups 20 can be connected to the common electrode 4 through two first vias K1. The two first vias K1 can be located on different sides of the first trace 6, so as to avoid occupying too much area of ​​the same pixel electrode 5 when they are set on the same side, which would affect the normal display of the pixel electrode 5.

[0084] In one possible implementation, as shown in Figures 12A-12F, the extension length d3 of the first trace 6 is greater than the extension length d4 of the first cutout 41. This allows the first trace 6 to be electrically connected to the connecting portion 42 at both ends of the first cutout 41.

[0085] In one possible implementation, referring to Figures 12A-12F, the orthographic projection of the first trace 61 onto the substrate 1 covers the orthographic projection of the first cutout 41 onto the substrate 1, and also covers the orthographic projection of the connection portion 42 onto the substrate. In this way, the first trace 6 can be electrically connected to the connection portion 42 at both ends of the first cutout 41.

[0086] In one possible implementation, referring to Figure 12F, the width d1 of the first cutout 41 in the first direction X is greater than the width d2 of the first trace 6 in the first direction X. This allows the dielectric layer at each location in the overlapping area of ​​the data line 3 and the common electrode layer 40 to be a superposition of the organic film layer 92 and the passivation layer 93, maximizing the reduction of parasitic capacitance between the data line 3 and the common electrode (first trace 6) covering it. This reduces the load on the data line, improves the pixel charging rate, and also reduces the coupling effect of the voltage polarity jump of the data line 3 on the common electrode, thus reducing the problem of horizontal crosstalk.

[0087] In one possible implementation, referring to Figure 12F, the orthographic projection of the first trace 6 onto the substrate covers the orthographic projection of the common electrode 4 on both sides of the first cutout 41 onto the substrate 1. That is, there can be an overlapping region S between the first trace 6 and the common electrode 4 on both sides of the first cutout 41. In this way, the combination of the first trace 6 and the common electrode 4 can completely shield the parasitic capacitance Cpd between the pixel electrode 5 and the data line 3.

[0088] In some pixel designs, the parasitic capacitance Cpd between the pixel electrode 5 and the data line 3 does not need to be completely eliminated. Reducing it to a certain limit can avoid the image quality problems caused by the fully long-connected dual-gate pixel architecture, which places higher demands on reducing the load on the data line 3. In one possible implementation, as shown in Figure 12G, the orthographic projection of the first trace 6 onto the substrate 1 does not overlap with the orthographic projection of the common electrodes 4 on both sides of the first cutout 41 onto the substrate 1. That is, on a plane parallel to the substrate 1, the distance between the edge of the common electrodes 4 on both sides of the first cutout 41 and the edge of the data line 3 is increased. In this way, the coupling capacitance between the data line 3 and the common electrode layer 40 can be further reduced, the load on the data line can be reduced, the pixel charging rate can be improved, and the coupling effect of the voltage polarity jump of the data line 3 on the common electrode can be reduced, thus reducing the problem of horizontal crosstalk.

[0089] In one possible implementation, as shown in Figures 13A-13E, the first trace 6 is located on the common electrode layer 40 and is integrally connected to the common electrode 4. In this embodiment, the first trace 6 is located on the common electrode layer 40 and is integrally connected to the common electrode 4. The common electrode 4 can cover the data line 3, completely shielding the electric field of the data line 3. There is no longer a parasitic capacitance between the upper pixel electrode 5 and the data line 3, and the parasitic capacitance Cpd between the pixel electrode 5 and the data line 3 can be eliminated. The upper pixel electrode layer 50 does not have a pattern for shielding the data line 3, and the pixel electrodes 5 of two adjacent sub-pixels can be closer together (the minimum distance is based on the process to avoid short circuits, and this distance is usually ≥3um), which can increase the aperture ratio of the display panel.

[0090] In one possible implementation, as shown in FIG13C, the orthographic projection of the outer edge w1 of the pixel electrode 5 onto the substrate 1 coincides with the outer edge w2 of the data line 3 on the substrate 1. This can improve the aperture ratio of the display panel.

[0091] In one possible implementation, referring to Figures 12A-12F and 13A-13E, the array substrate further includes: multiple second traces 7 and multiple second via groups K20; each second via group K20 includes two second vias K2; the two second vias K20 are located on opposite sides of the gate line group 2 and on different sides of the second traces 7; the common electrode 4 on both sides of the gate line group 20 is electrically connected to the second traces 7 through the two second vias K20. Thus, the common electrode 4 on both sides of the gate line group 20 can be connected together through the second traces 7.

[0092] In one possible implementation, as shown in Figures 12A-12F and 13A-13E, the second via K2 can be located at the area where the gate line group 20 intersects with the data line 3.

[0093] In one possible implementation, as shown in Figures 12A-12F and 13A-13E, the second trace 7 is on the same layer and made of the same material as the data line 3; the array substrate further includes an organic insulating layer 92 located between the data line 3 and the common electrode layer 40, and a passivation layer 93 located between the common electrode layer 40 and the pixel electrode layer 50; the pixel electrode layer 40 further includes an overlap portion 51; a second via K2 penetrates the passivation layer 93 and the organic insulating layer 92, and exposes a portion of the second trace 7 and a portion of the common electrode 4, and the overlap portion 51 contacts the common electrode 4 and the second trace 7 through the second via K2.

[0094] In one possible implementation, as shown in Figures 12A-12F and 13A-13E, the second trace 7 may include a second trace main portion 71 and a second trace extension portion 72; wherein the orthographic projection of the second trace extension portion 72 onto the substrate 1 may overlap with the orthographic projection of the overlapping portion 51 onto the substrate 1, so as to achieve electrical connection with the common electrode 4 through the second trace extension portion 72.

[0095] In one possible implementation, referring to Figures 12A-12D and 13B, the common electrode 4 has a recess 43 at the location of the second via K2. The orthographic projection of the second via K2 onto the substrate 1 partially overlaps with the recess 43 and partially overlaps with the common electrode 4 on the side of the recess 43 away from the gate line group 20. In this embodiment, the recess 43 at the location of the second via K2 facilitates the contact between the upper layer overlap 51 and the lower layer second trace 7, avoiding the obstruction of the common electrode 4 in the middle layer, which would prevent the upper layer overlap 51 from contacting the lower layer second trace 7. Moreover, the second via K2 partially exposes the second trace 7 and partially exposes the common electrode 4, with half used for the connection between the second trace 7 and the overlap 51 and the other half for the connection between the common electrode 4 and the overlap 51, which helps to reduce the area of ​​the second via and increase the aperture ratio of the display panel.

[0096] In one possible implementation, as shown in Figures 14A-14B, the second trace 7 is located on the side of the common electrode layer 40 facing the substrate 1 and is in direct contact with the common electrode 4. In this embodiment, the second trace 7 being located on the side of the common electrode layer 40 facing the substrate 1 and in direct contact with the common electrode 4 can improve the uniformity of the common electrode voltage when the resolution and refresh rate of the display panel are both high. Moreover, the second trace 7 and the common electrode 4 do not require via connections and can be in direct contact, resulting in better connectivity. Furthermore, the area of ​​vias is saved, and the light transmittance of the pixels can also be improved.

[0097] In one possible implementation, as shown in FIG16, the common electrode layer 40 may be disposed on the side of the pixel electrode layer 50 away from the substrate 1, and the parasitic capacitance Cpd between the data line 3 and the pixel electrode 5 may be reduced by increasing the lateral distance between the pixel electrode 5 and the data line 3.

[0098] Based on the same inventive concept, this disclosure also provides a display panel, as shown in FIG15, which includes an array substrate as provided in this disclosure, and a color filter substrate disposed opposite to the array substrate. The color filter substrate may include: a color filter substrate 95, a black matrix 96 located on the side of the color filter substrate 95 facing the array substrate, and a color filter layer located on the side of the black matrix 96 facing the array substrate. The color filter layer may include: a first color resist 971, a second color resist 972, and a third color resist (not shown in the figure). The first color resist 971 may be a red color resist, the second color resist 972 may be a green color resist, and the third color resist may be a blue color resist. Optionally, the orthogonal projection of the black matrix 96 onto the substrate 1 may cover the orthogonal projection of the gate line group 20 onto the substrate 1; optionally, the color filter substrate may not have a black matrix or may have a narrower black matrix at the position corresponding to the data line 3, that is, the data line 3 may be covered by the first trace 6 to shield the electric field on the data line 3 and shield light leakage.

[0099] Based on the same inventive concept, this disclosure also provides a display device, including the display panel described above. Implementation of this display device can refer to the embodiments of the display panel described above, and repeated details will not be repeated. The display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of this display device are understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting this disclosure.

[0100] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0101] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. An array substrate, wherein, include: Substrate; Multiple transistors; Multiple gate line groups are located on one side of the substrate, and each gate line group includes two gate lines extending along the first direction; Multiple data cables; A common electrode layer is located on the side of the data line opposite to the substrate; the common electrode layer includes multiple common electrodes; A pixel electrode layer, located on the side of the common electrode layer opposite to the data line, includes: a plurality of pixel electrode rows extending along a first direction; each pixel electrode row includes a plurality of pixel electrode groups arranged along the first direction; a gate line group is located in the region between adjacent pixel electrode rows, and the pixel electrode group is located in the region formed by the intersection of the gate line group and the data line; each pixel electrode group includes two pixel electrodes, and any pixel electrode in the pixel electrode group is electrically connected to the data line through the transistor across the other pixel electrode; Wherein, at least one of the common electrode layer and the pixel electrode layer includes: a plurality of first traces extending along the second direction; the first traces are electrically connected to the common electrode, and the orthographic projection of the first traces on the substrate covers the orthographic projection of the data line on the substrate.

2. The array substrate as claimed in claim 1, wherein, The first trace is located in the pixel electrode layer; The common electrode layer has a first cutout; the orthographic projection of the first trace on the substrate overlaps with the orthographic projection of the first cutout on the substrate.

3. The array substrate as described in claim 2, wherein, The first trace is broken at the location of the gate line group.

4. The array substrate as described in claim 2 or 3, wherein, The common electrode extends along the first direction and is arranged along the second direction, and the region of the common electrode located between adjacent gate line groups is within the orthogonal projection of the substrate. The common electrode has a connection portion at at least one end of the first cutout, and the common electrode is connected to the first trace through a first via at the connection portion.

5. The array substrate according to any one of claims 2-4, wherein, The extension length of the first trace is greater than the extension length of the first cutout.

6. The array substrate according to any one of claims 2-5, wherein, The orthographic projection of the first trace on the substrate covers the orthographic projection of the first cutout on the substrate, and covers the orthographic projection of the connection portion on the substrate.

7. The array substrate according to any one of claims 2-6, wherein, The orthographic projection of the first trace on the substrate covers the orthographic projection of the common electrode on the substrate on both sides of the first cutout.

8. The array substrate according to any one of claims 2-4, wherein, The orthographic projection of the first trace on the substrate does not overlap with the orthographic projection of the common electrode on both sides of the first cutout on the substrate.

9. The array substrate as claimed in claim 1, wherein, The first trace is located in the common electrode layer and is integrally connected to the common electrode.

10. The array substrate as claimed in claim 9, wherein, The orthographic projection of the outer edge of the pixel electrode onto the substrate coincides with the outer edge of the data line onto the substrate.

11. The array substrate according to any one of claims 3-10, wherein, The array substrate further includes: multiple second traces and multiple second via groups; the second via group includes: two second vias; the two second vias of the second via group are respectively located on both sides of the gate line group and on different sides of the second trace; the common electrode on both sides of the gate line group is electrically connected to the second trace through the two second vias of the second via group.

12. The array substrate as claimed in claim 11, wherein, The second trace is on the same layer and made of the same material as the data line; the array substrate further includes: an organic insulating layer located between the data line and the common electrode layer, and a passivation layer located between the common electrode layer and the pixel electrode layer; the pixel electrode layer further includes: an overlap portion; The second via penetrates the passivation layer and the organic insulating layer, and exposes a portion of the second trace and a portion of the common electrode. The overlap portion contacts the common electrode and the second trace through the second via.

13. The array substrate as claimed in claim 12, wherein, The common electrode has a recess at the location of the second via; the orthographic projection of the second via onto the substrate partially overlaps with the recess and partially overlaps with the common electrode on the side of the recess away from the gate line group.

14. The array substrate as claimed in claim 11, wherein, The second trace is located on the side of the common electrode layer facing the substrate and is in direct contact with the common electrode.

15. A display panel, wherein, Includes the array substrate as described in any one of claims 1-14.

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