Pixel driving circuit, display panel, and display apparatus

Abstract

A pixel driving circuit, a display panel, and a display apparatus. The pixel driving circuit comprises a data writing sub-circuit, a first capacitor, and a driving sub-circuit. The data writing sub-circuit is configured to control a data signal end to be connected to or disconnected from a first node, and comprises a first transistor and a second transistor. First electrodes of the first transistor and the second transistor are both connected to the data signal end, and second electrodes are both connected to the first node. A control electrode of the first transistor is connected to a high-refresh scanning signal end. A control electrode of the second transistor is connected to a first scanning signal end. The data writing sub-circuit is configured to, when pixels are in a high-refresh mode, turn on the first transistor and turn on the second transistor in a data writing phase. One end of the first capacitor is connected to the first node, and the other end is connected to a second node. The driving sub-circuit is connected to the second node, a third node, and a fourth node, and is configured to control the third node to be connected to or disconnected from the fourth node.

Description

Pixel driving circuit, display panel and display device TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a pixel driving circuit, a display panel and a display device. BACKGROUND

[0002] OLED (Organic Light Emitting Diode) has the advantages of bright color, higher refresh rate, higher contrast, lower power consumption, etc., so that it gradually replaces LCD (Liquid Crystal Display) in small size market. But AMOLED (Active Matrix Organic Light Emitting Diode) has more complex pixel driving circuit than LCD, which makes the TFT (Thin Film Transistor) process of AMOLED more complex, so the design of AMOLED pixel driving circuit is particularly important. SUMMARY

[0003] The purpose of the present application is to provide a pixel driving circuit, a display panel and a display device with excellent data signal writing capability.

[0004] The present application discloses a pixel driving circuit, which comprises:

[0005] A data writing sub-circuit is connected with a data signal end and a first node, and is configured to control the communication or disconnection of the data signal end and the first node; the data writing sub-circuit comprises a first transistor and a second transistor; the first electrode of the first transistor and the first electrode of the second transistor are connected with the data signal end, and the second electrode of the first transistor and the second electrode of the second transistor are connected with the first node; the control electrode of the first transistor is connected with a high brush scanning signal end, and the control electrode of the second transistor is connected with a first scanning signal end;

[0006] The data writing sub-circuit is configured to control the first transistor to be turned on by the high brush scanning signal end and control the second transistor to be turned on by the first scanning signal end in the data writing stage when the pixel is in the high brush mode;

[0007] A first capacitor has one end connected with the first node and the other end connected with a second node;

[0008] A driving sub-circuit is connected with the second node, a third node and a fourth node, and is configured to control the communication or disconnection of the third node and the fourth node; the third node is connected with a light emitting unit, and the fourth node is connected with a first power signal end.

[0009] Optionally, the data writing sub-circuit is further configured to, when the pixel is in a low brush mode, control the first transistor to be turned off and the second transistor to be turned on by the high brush scanning signal end in the data writing stage.

[0010] Optionally, the pixel driving circuit further comprises:

[0011] a compensation sub-circuit connected with the second node and the third node, and configured to compensate the data signal;

[0012] The compensation sub-circuit comprises a fourth transistor, a first electrode of the fourth transistor being connected with the third node, a second electrode of the fourth transistor being connected with the second node, and a control electrode of the fourth transistor being connected with a second scanning signal end.

[0013] The fourth transistor is a metal oxide thin film transistor.

[0014] Optionally, the compensation sub-circuit further comprises a tenth transistor.

[0015] A first electrode of the tenth transistor is connected with a second electrode of the fourth transistor, a second electrode of the tenth transistor is connected with the second node, and a control electrode of the tenth transistor is connected with a second gate signal end; or a first electrode of the tenth transistor is connected with the third node, a second electrode of the tenth transistor is connected with a first electrode of the fourth transistor, and a control electrode of the tenth transistor is connected with the second gate signal end.

[0016] The tenth transistor is a low temperature poly-silicon transistor.

[0017] Optionally, the driving sub-circuit comprises a third transistor and a ninth transistor.

[0018] A first electrode of the third transistor is connected with the fourth node, a second electrode of the third transistor is connected with the third node, and a control electrode of the third transistor is connected with a second electrode of the ninth transistor.

[0019] A first electrode of the ninth transistor is connected with the second node, and a control electrode of the ninth transistor is connected with a fourth scanning signal end; the ninth transistor is a metal oxide thin film transistor.

[0020] Optionally, the driving sub-circuit further comprises a fifteenth transistor.

[0021] A first electrode of the fifteenth transistor is connected with a second electrode of the ninth transistor, a second electrode of the fifteenth transistor is connected with a control electrode of the third transistor, and a control electrode of the fifteenth transistor is connected with a fourth gate signal end; or a first electrode of the fifteenth transistor is connected with the second node, a second electrode of the fifteenth transistor is connected with a first electrode of the ninth transistor, and a control electrode of the fifteenth transistor is connected with the fourth gate signal end.

[0022] The fifteenth transistor is a low-temperature polysilicon transistor.

[0023] Optionally, the pixel driving circuit further comprises a first light-emitting control sub-circuit.

[0024] The first light-emitting control sub-circuit comprises a sixth transistor and an eleventh transistor, one of the sixth transistor and the eleventh transistor is a low-temperature polysilicon transistor, and the other is a metal oxide thin film transistor.

[0025] The first electrode of the sixth transistor is connected with the second electrode of the eleventh transistor, the second electrode is connected with the fourth node, and the control electrode is connected with a first light-emitting control signal end.

[0026] The first electrode of the eleventh transistor is connected with the first power signal end, and the control electrode is connected with a first gate control signal end.

[0027] Optionally, the pixel driving circuit further comprises a second light-emitting control sub-circuit.

[0028] The second light-emitting control sub-circuit comprises a fifth transistor and a twelfth transistor, one of the fifth transistor and the twelfth transistor is a low-temperature polysilicon transistor, and the other is a metal oxide thin film transistor.

[0029] The first electrode of the fifth transistor is connected with the second electrode of the twelfth transistor, the second electrode is connected with the light-emitting unit, and the control electrode is connected with a second light-emitting control signal end.

[0030] The first electrode of the twelfth transistor is connected with the third node, and the control electrode is connected with a second gate control signal end.

[0031] Optionally, the pixel driving circuit further comprises a first reset sub-circuit.

[0032] The first reset sub-circuit comprises an eighth transistor and a thirteenth transistor, one of the eighth transistor and the thirteenth transistor is a low-temperature polysilicon transistor, and the other is a metal oxide thin film transistor.

[0033] The first electrode of the eighth transistor is connected with the second electrode of the thirteenth transistor, the second electrode is connected with the light-emitting unit, and the control electrode is connected with a third scanning signal end.

[0034] The first electrode of the thirteenth transistor is connected with a second reset signal end, and the control electrode is connected with a third gate signal end.

[0035] Optionally, the pixel driving circuit further comprises a second reset sub-circuit.

[0036] The second reset sub-circuit comprises a seventh transistor and a fourteenth transistor, one of the seventh transistor and the fourteenth transistor is a low-temperature polysilicon transistor, and the other is a metal oxide thin film transistor;

[0037] The first electrode of the seventh transistor is connected with a first reset signal terminal, the second electrode is connected with the first electrode of the fourteenth transistor, and the control electrode is connected with a third scan signal terminal;

[0038] The second electrode of the fourteenth transistor is connected with the first node, and the control electrode is connected with a third gate signal terminal.

[0039] Optionally, the pixel driving circuit further comprises a pre-charging circuit.

[0040] The pre-charging circuit is connected with a data signal terminal, the data writing sub-circuit is connected with the data signal terminal through a wire, and the pre-charging circuit is configured to pre-charge a line between the data signal terminal and the data writing sub-circuit.

[0041] Optionally, the pixel driving circuit further comprises a first light-emitting control sub-circuit and a second light-emitting control sub-circuit, the first light-emitting control sub-circuit is connected between the first power signal terminal and the fourth node and connected with a first light-emitting control signal terminal, and the second light-emitting control sub-circuit is connected between the third node and the fourth node and connected with a second light-emitting control signal terminal.

[0042] The pre-charging circuit comprises a seventeenth transistor.

[0043] The first electrode of the seventeenth transistor is connected with the pre-charging signal terminal, the second electrode is connected with the wire between the data signal terminal and the data writing sub-circuit, and the control electrode is connected with the first light-emitting control signal terminal or the second light-emitting control signal terminal; the first light-emitting control signal terminal or the second light-emitting control signal terminal is configured to control the seventeenth transistor to be turned on before a data writing stage.

[0044] Optionally, the pre-charging circuit further comprises a sixteenth transistor.

[0045] The first electrode of the sixteenth transistor is connected with the second electrode of the seventeenth transistor, the second electrode is connected with the wire between the data signal terminal and the data writing sub-circuit, and the control electrode is connected with a control signal terminal.

[0046] Optionally, the control signal terminal is configured to control the sixteenth transistor to be turned on when the pixel is in a high-brush mode, and control the sixteenth transistor to be turned off when the pixel is in a low-brush mode.

[0047] This application also provides a display panel, which includes the pixel driving circuit described above.

[0048] Optionally, the display panel includes multiple pixel driving circuits, multiple first light emission control signal lines, and multiple second light emission control signal lines. The multiple pixel driving circuits are arranged in multiple rows. The first light emission control signal terminals of the pixel driving circuits in one row are connected to the same first light emission control signal line, and the second light emission control signal terminals of the pixel driving circuits in one row are connected to the same second light emission control signal line.

[0049] When the precharge electronic circuit includes the seventeenth transistor, in the pixel driving circuit, the control terminal of the seventeenth transistor is connected to the first light emission control signal terminal or the second light emission control signal terminal of the n-row pixel driving circuit, where n is an integer greater than 0.

[0050] This application also provides a display device, which includes the display panel described above.

[0051] Compared with related technologies, the data writing sub-circuit of this application includes a first transistor and a second transistor connected in parallel. When the pixel is in high refresh mode, the first transistor and the second transistor are turned on simultaneously during the data writing stage to improve the data signal writing capability.

[0052] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this specification. Attached Figure Description

[0053] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this specification and, together with the specification, serve to explain the principles of this specification.

[0054] Figure 1 is a schematic block diagram of a pixel driving circuit in one embodiment of this application.

[0055] Figure 2 is a schematic block diagram of a pixel driving circuit in one embodiment of this application.

[0056] Figure 3 is a circuit diagram of the pixel driving circuit in Figure 2 in one embodiment.

[0057] Figure 4 is a circuit diagram of the pixel driving circuit in Figure 2 in one embodiment.

[0058] Figure 5 is a circuit diagram of the pixel driving circuit in Figure 2 in one embodiment.

[0059] Figure 6 is a circuit diagram of the pixel driving circuit in Figure 2 in one embodiment.

[0060] Figure 7 is a circuit diagram of the pixel driving circuit in Figure 2 in one embodiment.

[0061] Figure 8 is a circuit diagram of the pixel driving circuit in Figure 2 in one embodiment.

[0062] Figure 9 is a circuit diagram of the pixel driving circuit in Figure 2 in one embodiment.

[0063] Figure 10 is a circuit diagram of the pixel driving circuit in Figure 2 in one embodiment.

[0064] Figure 11 is a circuit diagram of the pixel driving circuit in Figure 2 in one embodiment.

[0065] Figure 12 is a timing diagram of the pixel driving circuit shown in Figure 4 in one embodiment.

[0066] Figure 13 is a schematic block diagram of a pixel driving circuit in one embodiment of this application.

[0067] Figure 14 is a detailed connection circuit diagram of multiple pixel driving circuits shown in Figure 13 in one embodiment.

[0068] Figure 15 is a detailed connection circuit diagram of multiple pixel driving circuits shown in Figure 13 in one embodiment. Detailed Implementation

[0069] The technical solutions in the embodiments (or "implementations") of this application will be clearly and completely described herein with reference to the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements.

[0070] The terms "first" and "second" used in the embodiments of this application are for descriptive convenience only and should not be construed as indicating or implying relative importance.

[0071] This application provides a pixel driving circuit for a display panel. As shown in Figures 1 to 3, the pixel driving circuit includes a data writing sub-circuit 10, a first capacitor C1, and a driving sub-circuit 20.

[0072] The data writing sub-circuit 10 is connected to the data signal terminal DATA and the first node N1, and is configured to control the connection or disconnection between the data signal terminal DATA and the first node N1. The data writing sub-circuit 10 includes a first transistor T1 and a second transistor T2. The first terminals of both the first transistor T1 and the second transistor T2 are connected to the data signal terminal DATA, and the second terminals of both are connected to the first node N1. The control terminal of the first transistor T1 is connected to the high-brush scan signal terminal SC-HR, and the control terminal of the second transistor T2 is connected to the first scan signal terminal SC1.

[0073] The data writing sub-circuit DATA is configured such that, when the display panel is in high refresh rate mode, during the data writing phase, the high refresh rate scan signal terminal SC-HR controls the first transistor T1 to turn on, and the first scan signal terminal SC1 controls the second transistor T2 to turn on. The display panel can have both high refresh rate and low refresh rate modes; the number of images displayed per second in high refresh rate mode is greater than the number of images displayed per second in low refresh rate mode.

[0074] One end of the first capacitor C1 is connected to the first node N1, and the other end of the first capacitor C1 is connected to the second node N2.

[0075] The driving sub-circuit 20 is connected to the second node N2, the third node N3, and the fourth node N4. The driving sub-circuit 20 is configured to control the connection or disconnection of the third node N3 and the fourth node N4. The third node N3 is connected to the light-emitting unit 90, and the fourth node N4 is connected to the first power signal terminal VDD.

[0076] The data writing sub-circuit of this application includes a first transistor and a second transistor connected in parallel. When the pixel is in high refresh mode, the first transistor and the second transistor are turned on simultaneously during the data writing stage to increase the conduction current between the data signal terminal DATA and the first node N1, thereby improving the writing capability of the data signal DATA.

[0077] The following will provide a detailed description of various embodiments of this application that conform to the above-described inventive concept.

[0078] As shown in Figure 3, the signal terminals connected to the pixel circuit provided in this application also include a first power supply signal terminal VDD, a second power supply signal terminal VSS, a first scan signal terminal SC1, a second scan signal terminal SC2, a third scan signal terminal SC3 and a fourth scan signal terminal SC4, a second gate signal terminal VC2, a third gate signal terminal VC3 and a fourth gate signal terminal VC4, a first light emission control signal terminal EM1, a second light emission control signal terminal EM2, a first gate control signal terminal VC-M1 and a second gate control signal terminal VC-M2, a first reset signal terminal VINIT1, a second reset signal terminal VINIT2, a control signal terminal CONTROL and a precharge signal terminal VRE-CHARGE.

[0079] Specifically, the first power signal terminal VDD and the second power signal terminal VSS are configured to provide the pixel circuit with the first power signal VDD and the second power signal VSS, respectively. The first scan signal terminal SC1, the second scan signal terminal SC2, the third scan signal terminal SC3, and the fourth scan signal terminal SC4 are configured to provide the pixel circuit with the first scan signal SC1, the second scan signal SC2, the third scan signal SC3, and the fourth scan signal SC4, respectively. The second gate signal terminal VC2, the third gate signal VC3, and the fourth gate signal VC4 are configured to provide the pixel circuit with the second gate signal VC2, the third gate signal VC3, and the fourth gate signal VC4, respectively. The second gate signal VC2, the third gate signal VC3, and the fourth gate signal VC4 are out of phase with the second scan signal SC2, the third scan signal SC3, and the fourth scan signal SC4, respectively. The high refresh rate scan signal terminal SC-HR is configured to output the high refresh rate scan signal SC-HR. The first light emission control signal terminal EM1 and the second light emission control signal terminal EM2 are configured to provide the pixel circuit with the first light emission control signal em1 and the second light emission control signal em2, respectively. The first gate control signal terminal VC-M1 and the second gate control signal terminal VC-M2 are configured to provide the pixel circuit with the first gate control signal vc-m1 and the second gate control signal vc-m2, respectively, wherein the first gate control signal vc-m1 and the second gate control signal vc-m2 are out of phase with the first light emission control signal em1 and the second light emission control signal em2, respectively. The first reset signal terminal VINIT1 and the second reset signal terminal VINIT2 are configured to provide the pixel circuit with the first reset signal vinit1 and the second reset signal vinit2, respectively. The data signal terminal DATA is configured to output the data signal data. The control signal terminal CONTROL is configured to provide the pixel circuit with the control signal control. The precharge signal terminal VRE-CHARGE is configured to provide the pixel circuit with the precharge signal vre-charge.

[0080] Unless otherwise specified, the transistors used in this application can be bipolar junction transistors (BJTs), thin-film transistors (TFTs), field-effect transistors (FETs), or other devices with similar characteristics. In the embodiments of this disclosure, to distinguish the two terminals of a transistor other than the control terminal, one terminal is referred to as the first terminal and the other as the second terminal.

[0081] In actual operation, when the transistor is a bipolar junction transistor (BJT), the control electrode can be the base, the first electrode can be the collector, and the second electrode can be the emitter; or, the control electrode can be the base, the first electrode can be the emitter, and the second electrode can be the collector.

[0082] In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the control electrode can be the gate, the first electrode can be the drain, and the second electrode can be the source; or, the control electrode can be the gate, the first electrode can be the source, and the second electrode can be the drain.

[0083] As shown in Figure 1, in an optional embodiment, the pixel driving circuit includes a data writing sub-circuit 10, a first capacitor C1, and a driving sub-circuit 20.

[0084] The data writing sub-circuit 10 is connected to the first scan signal terminal SC1, the data signal terminal DATA, and the first node N1. The data writing sub-circuit 10 is configured to control whether the data signal DATA is written to the first node N1 under the control of the first scan signal SC1.

[0085] The first node N1 is coupled to the second node N2 through the first capacitor C1, so that the potential of the second node N2 can be adjusted by the potential change of the first node N1.

[0086] The driving sub-circuit 20 is connected to the second node N2, the third node N3, and the fourth node N4. The driving sub-circuit 20 is configured to control the conduction of the third node N3 and the fourth node N4 under the control of the second node N2. The fourth node N4 is connected to the first power signal terminal VDD, and the third node N3 is connected to the light-emitting unit 90.

[0087] As shown in Figure 2, in an optional embodiment, the pixel driving circuit further includes a compensation sub-circuit 30 and / or a first light emission control sub-circuit 40 and / or a second light emission control sub-circuit 50 and / or a first reset sub-circuit 60 and / or a second reset circuit 70.

[0088] The compensation sub-circuit 30 is connected to the second scan signal terminal SC2, the second node N2, and the third node N3. The compensation sub-circuit 30 is configured to control the connection between the second node N2 and the third node N3 under the control of the second scan signal SC2.

[0089] The first light-emitting control sub-circuit 40 is disposed between the driving sub-circuit 20 and the first power supply signal terminal VDD. Specifically, the first light-emitting control sub-circuit 40 is connected to the first power supply signal terminal VDD, the first light-emitting control signal terminal EM1, and the fourth node N4. The first light-emitting control sub-circuit 40 is configured to control whether the first power supply signal VDD is written to the fourth node N4 under the control of the first light-emitting control signal EM1.

[0090] The second light-emitting control sub-circuit 50 is disposed between the driving sub-circuit 20 and the light-emitting unit 90. Specifically, the second light-emitting control sub-circuit 50 is connected to the second light-emitting control signal terminal EM2, the third node N3, and the fifth node N5, with the fifth node N5 connected to the light-emitting unit 90. The second light-emitting control sub-circuit 50 is configured to control the connection between the fifth node N5 and the third node N3 under the control of the second light-emitting control signal EM2.

[0091] The first reset sub-circuit 60 is connected to the second reset signal terminal VINIT2, the third scan signal terminal SC3, and the fifth node N5. The first reset sub-circuit 60 is configured to control whether the second reset signal vinit2 is written to the fifth node N5 under the control of the third scan signal sc3.

[0092] The second reset sub-circuit 70 is connected to the first reset signal terminal VINIT1, the third scan signal terminal SC3, and the first node N1. The second reset sub-circuit 70 is configured to control whether the first reset signal vinit1 is written to the first node N1 under the control of the third scan signal sc3.

[0093] As shown in Figure 3, in an optional embodiment, the data writing sub-circuit 10 includes a first transistor T1 and a second transistor T2. The first terminals of both the first transistor T1 and the second transistor T2 are connected to the data signal terminal DATA, and the second terminals of both are connected to the first node N1. The control terminal of the first transistor T1 is connected to the high-brush scan signal terminal SC-HR, and the control terminal of the second transistor T2 is connected to the first scan signal terminal SC1. Both the first transistor T1 and the second transistor T2 can be low-temperature polysilicon transistors.

[0094] The driving sub-circuit 20 includes a third transistor T3. The first terminal of the third transistor T3 is connected to the fourth node N4, the second terminal of the third transistor T3 is connected to the third node N3, and the control terminal of the third transistor T3 is connected to the second node N2. The third transistor T3 can be a low-temperature polysilicon transistor.

[0095] The compensation sub-circuit 30 includes a fourth transistor T4. The first terminal of the fourth transistor T4 is connected to the third node N3, the second terminal of the fourth transistor T4 is connected to the second node N2, and the control terminal of the fourth transistor T4 is connected to the second scan signal terminal SC2. The fourth transistor T4 can be a metal-oxide-slim transistor, specifically, it can be an IGZO (Indium Gallium Zinc Oxide) transistor. When the refresh rate of the display panel is low, the fourth transistor T4 is an IGZO transistor, whose lower leakage current can make the potential of the second node N2 more stable, thereby making the signal at the control terminal of the third transistor T3 more stable, resulting in better optical performance.

[0096] The first light-emitting control sub-circuit 40 includes a sixth transistor T6. The first terminal of the sixth transistor T6 is connected to the first power supply signal terminal VDD, the second terminal of the sixth transistor T6 is connected to the fourth node N4, and the control terminal of the sixth transistor T6 is connected to the first light-emitting control signal terminal EM1. The sixth transistor T6 can be a low-temperature polysilicon transistor.

[0097] The second light-emitting control sub-circuit 50 includes a fifth transistor T5. The first terminal of the fifth transistor T5 is connected to the third node N3, the second terminal of the fifth transistor T5 is connected to the light-emitting unit 90, and the control terminal of the fifth transistor T5 is connected to the second light-emitting control signal terminal EM2. The fifth transistor T5 can be a low-temperature polysilicon transistor.

[0098] The first reset circuit 60 includes an eighth transistor T8. The first terminal of the eighth transistor T8 is connected to the second reset signal terminal VINIT2, the second terminal of the eighth transistor T8 is connected to the fifth node N5, and the control terminal of the eighth transistor T8 is connected to the third scan signal terminal SC3. The eighth transistor T8 can be a low-temperature polysilicon transistor.

[0099] The second reset circuit 70 includes a seventh transistor T7. The first terminal of the seventh transistor T7 is connected to the first reset signal terminal VINIT1, the second terminal of the seventh transistor T7 is connected to the first node N1, and the control terminal of the seventh transistor T7 is connected to the third scan signal terminal SC3. The seventh transistor T7 can be a low-temperature polysilicon transistor.

[0100] Figure 4 shows a circuit diagram of the pixel circuit in another optional embodiment. Compared with the circuit shown in Figure 3, the driving sub-circuit 20 of the circuit shown in Figure 4 further includes a ninth transistor T9. The ninth transistor T9 is disposed between the control electrode of the third transistor T3 and the second node N2. Specifically, the first electrode of the ninth transistor T9 is connected to the second node N2, the second electrode of the ninth transistor T9 is connected to the control electrode of the third transistor T3, and the control electrode of the ninth transistor T9 is connected to the fourth scan signal terminal SC4. The ninth transistor T9 can be a metal-oxide-slim thin-film transistor, specifically, the ninth transistor T9 can be an IGZO transistor. When the pixel refresh rate is low, the ninth transistor T9 is an IGZO transistor, whose lower leakage current can make the signal transmitted from the second node N2 to the control electrode of the third transistor T3 more stable, thereby bringing better optical performance.

[0101] As shown in Figure 5, which is a circuit diagram of the pixel circuit in another optional embodiment, the driving sub-circuit 20 of the circuit shown in Figure 5 further includes a fifteenth transistor T15 compared to the circuit shown in Figure 4. The first terminal of the fifteenth transistor T15 is connected to the second terminal of the ninth transistor T9, the second terminal of the fifteenth transistor T15 is connected to the control terminal of the third transistor T3, and the control terminal of the fifteenth transistor T15 is connected to the fourth gate signal terminal SC4. Alternatively, the first terminal of the fifteenth transistor T15 is connected to the second node N2, the second terminal of the fifteenth transistor T15 is connected to the first terminal of the ninth transistor T9, and the control terminal of the fifteenth transistor T15 is connected to the fourth gate signal terminal SC4. The fifteenth transistor T15 can be a low-temperature polysilicon transistor. Since the ninth transistor T9 and the fifteenth transistor T15 are connected in series, and the ninth transistor T9 is a low-temperature polysilicon transistor while the fifteenth transistor T15 is an IGZO transistor, the leakage current of the second node N2 can be effectively prevented from affecting the control terminal of the third transistor T3.

[0102] Figure 6 shows a circuit diagram of the pixel circuit in another optional embodiment. Compared with the circuit shown in Figure 3, the compensation sub-circuit 30 of the circuit shown in Figure 6 further includes a tenth transistor T10. The first terminal of the tenth transistor T10 is connected to the second terminal of the fourth transistor T4, the second terminal of the tenth transistor T10 is connected to the second node N2, and the control terminal of the tenth transistor T10 is connected to the second gate signal terminal VC2. Alternatively, the first terminal of the tenth transistor T10 is connected to the third node N3, the second terminal of the tenth transistor T10 is connected to the first terminal of the fourth transistor T4, and the control terminal of the tenth transistor T10 is connected to the second gate signal terminal VC2. The tenth transistor is a low-temperature polysilicon transistor. Since the tenth transistor T10 and the fourth transistor T4 are connected in series, and the tenth transistor T10 is a low-temperature polysilicon transistor while the fourth transistor T4 is an IGZO transistor, the leakage current of the third node N3 can be effectively prevented from affecting the second node N2.

[0103] As shown in Figure 7, which is a circuit diagram of the pixel circuit in another optional embodiment, the first light-emitting control sub-circuit 40 of the circuit shown in Figure 7 further includes an eleventh transistor T11. The first terminal of the eleventh transistor T11 is connected to the first power supply signal terminal VDD, the second terminal of the eleventh transistor T11 is connected to the first terminal of the sixth transistor T6, and the control terminal of the eleventh transistor T11 is connected to the first gate control signal terminal VC-M1. One of the sixth transistor T6 and the eleventh transistor T11 is a low-temperature polysilicon transistor and the other is a metal-oxide-slim thin-film transistor. In this embodiment, the sixth transistor T6 is a low-temperature polysilicon transistor and the eleventh transistor T11 is an IGZO transistor, which can effectively prevent the leakage current of the first power supply signal terminal VDD from affecting the fourth node N4.

[0104] As shown in Figure 8, which is a circuit diagram of the pixel circuit in another optional embodiment, the second light-emitting control sub-circuit 50 of the circuit shown in Figure 8 further includes a twelfth transistor T12. The first terminal of the twelfth transistor T12 is connected to the third node N3, the second terminal of the twelfth transistor T12 is connected to the first terminal of the fifth transistor T5, and the control terminal of the twelfth transistor T12 is connected to the second gate control signal terminal VC-M2. One of the fifth transistor T5 and the twelfth transistor T12 is a low-temperature polysilicon transistor and the other is a metal-oxide-slim thin-film transistor. In this embodiment, the fifth transistor T5 is a low-temperature polysilicon transistor and the twelfth transistor T12 is an IGZO transistor, which can effectively prevent the leakage current of the third node N3 from affecting the fifth node N5.

[0105] As shown in Figure 9, which is a circuit diagram of the pixel circuit in another optional embodiment, the first reset sub-circuit 60 of the circuit shown in Figure 9 further includes a thirteenth transistor T13. The first terminal of the thirteenth transistor T13 is connected to the second reset signal terminal VINIT2, the second terminal of the thirteenth transistor T13 is connected to the first terminal of the eighth transistor T8, and the control terminal of the thirteenth transistor T13 is connected to the third gate signal terminal VC3. One of the eighth transistor T8 and the thirteenth transistor T13 is a low-temperature polysilicon transistor and the other is a metal-oxide-slim thin-film transistor. In this embodiment, the eighth transistor T8 is a low-temperature polysilicon transistor and the thirteenth transistor T13 is an IGZO transistor, which can effectively prevent the leakage current of the second reset signal terminal VINIT2 from affecting the fifth node N5.

[0106] As shown in Figure 10, this is a circuit diagram of the pixel circuit in another optional embodiment. Compared to the circuit shown in Figure 3, the second reset circuit 70 of the circuit shown in Figure 10 further includes a fourteenth transistor T14. The first terminal of the fourteenth transistor T14 is connected to the second terminal of the seventh transistor T7, the second terminal of the fourteenth transistor T14 is connected to the first node N1, and the control terminal of the fourteenth transistor T14 is connected to the third gate signal terminal VC3. One of the seventh transistor T7 and the fourteenth transistor T14 is a low-temperature polysilicon transistor and the other is a metal-oxide-slim transistor. In this embodiment, the seventh transistor T7 is a low-temperature polysilicon transistor and the fourteenth transistor T14 is an IGZO transistor, which can effectively prevent the leakage current of the first reset signal terminal VINIT1 from affecting the first node N1.

[0107] As shown in Figure 11, this is a circuit diagram of the pixel circuit in another optional embodiment. Compared with the circuit shown in Figure 3, the driving sub-circuit 20 of the circuit shown in Figure 11 further includes a ninth transistor T9 and a fifteenth transistor T15; the compensation sub-circuit 30 further includes a tenth transistor T10; the first light-emitting control sub-circuit 40 further includes an eleventh transistor T11; the second light-emitting control sub-circuit 50 further includes a twelfth transistor T12; the first reset sub-circuit 60 further includes a thirteenth transistor T13; and the second reset sub-circuit 70 further includes a fourteenth transistor T14. The connection method and type of the above transistors are the same as those in the embodiments shown in Figures 4 to 10, and will not be described in detail here. Of course, in some optional embodiments, the pixel circuit can be a combination of the embodiments shown in Figures 4 to 10. For example, the pixel circuit can be configured with the ninth transistor T9 and the fifteenth transistor T15 shown in Figure 5 and the fourteenth transistor T14 shown in Figure 10, or it can be configured with the tenth transistor T10 shown in Figure 6 and the eleventh transistor T11 shown in Figure 7, and so on.

[0108] As shown in Figure 12, which is a timing diagram of the circuit diagram shown in Figure 4 in one embodiment, the driving period of one frame includes an initialization period S1, a compensation period S2, a data writing period S3, and a light emission period S4. The data writing sub-circuit 10 is configured such that when the display panel is in high refresh rate mode, the high refresh rate scan signal terminal SC-HR controls the first transistor T1 to turn on in stage S3; when the display panel is in low refresh rate mode, the high refresh rate scan signal terminal SC-HR controls the first transistor to turn off in stage S3.

[0109] As shown in Figure 12, during time period S1, the first scan signal sc1 is at a high potential, the second scan signal sc2 is at a low potential, the third scan signal sc3 is at a low potential, the fourth scan signal sc4 is at a low potential, and the first light emission control signal em1 is at a high potential. The first light emission control signal em1 changes to a high potential. The first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the ninth transistor T9 are turned off. The seventh transistor T7 and the eighth transistor T8 are turned on. The first reset signal vinit1 resets the first node N1 and the second node N2, and the second reset signal vinit2 resets the fifth node N5.

[0110] As shown in Figure 12, during time period S2, the second scan signal sc2 and the fourth scan signal sc4 both transition to a high potential, while the first light emission control signal em1 transitions to a low potential. The fourth transistor T4, the sixth transistor T6, and the ninth transistor T9 become active. The first power supply signal vdd begins charging the second node N2 until it reaches a potential of ELVDD + Vth, where ELVDD is the potential of the first power supply signal vdd, and Vth is the threshold voltage of the third transistor T3.

[0111] As shown in Figure 12, during period S3, the first scan signal sc1 transitions to a low potential, the second scan signal sc2 transitions to a low potential, the third scan signal sc3 transitions to a high potential, and the first light emission control signal em1 transitions to a high potential. The first transistor T1 and the second transistor T2 become active, while the fourth transistor T4, the seventh transistor T7, the eighth transistor T8, and the sixth transistor T6 become inactive. The data signal data is written to the first node N1 and then to the second node N2 through the first capacitor C1. The potential of the second node N2 becomes Vdata + ELVDD + Vth. Thus, when the third transistor T3 is driven, it can counteract both the effect of the ELVDD voltage drop and the effect of Vth.

[0112] As shown in Figure 12, during time period S4, the first scan signal sc1 transitions to a high potential, the first light-emitting control signal em1 transitions to a low potential, and the second light-emitting control signal em2 transitions to a low potential. The first transistor T1 and the second transistor T2 transition to the off state, while the fifth transistor T5 and the sixth transistor T6 transition to the on state. The third transistor T3 transitions to the on state under the control of the second node N2 potential. The first power supply signal vdd is connected to the light-emitting unit 90 via the sixth transistor T6, the third transistor T3, and the fifth transistor T5 to drive the light-emitting unit 90 to emit light.

[0113] The pixel circuit then repeats the above driving timing sequence to control the light-emitting unit 90 to emit light.

[0114] For pixel circuits in other embodiments of this application, the light-emitting unit 90 can also be driven to emit light according to the timing logic described above. For example, for the pixel circuit shown in FIG11, since the added transistor and driving terminal do not affect the conduction of the original circuit, it can also be driven according to the timing diagram shown in FIG12.

[0115] As shown in Figure 13, in an optional embodiment, the pixel driving circuit further includes a pre-charge sub-circuit 80. The pre-charge sub-circuit 80 is connected to the data signal terminal DATA, and the data writing sub-circuit 10 is connected to the data signal terminal DATA via a wire. The pre-charge sub-circuit 80 is configured to pre-charge the line between the data signal terminal DATA and the data writing sub-circuit 10.

[0116] As shown in Figure 14, the pre-charge sub-circuit 80 also includes a seventeenth transistor T17. The first terminal of the seventeenth transistor T17 is connected to the pre-charge signal terminal VRE-CHARGE, the second terminal of the seventeenth transistor T17 is connected to the wire between the data signal terminal DATA and the data writing sub-circuit 10, and the control terminal of the seventeenth transistor T17 is connected to either the first light-emitting control signal terminal EM1 or the second light-emitting control signal terminal EM2. The seventeenth transistor T17 can be a metal-oxide-slim film transistor, specifically, it can be an IGZO transistor. According to the timing diagram shown in Figure 12, the seventeenth transistor T17 will be turned on before the S3 period, i.e., the data writing period, thereby allowing the pre-charge signal terminal VRE-CHARGE to pre-charge the wire between the data signal terminal DATA and the data writing sub-circuit 10.

[0117] As shown in Figure 14, optionally, the precharge sub-circuit 80 also includes a sixteenth transistor T16. The first terminal of the sixteenth transistor T16 is connected to the second terminal of the seventeenth transistor T17. The second terminal of the sixteenth transistor T16 is connected to the wire between the data signal terminal DATA and the data writing sub-circuit 10. The control terminal of the sixteenth transistor T16 is connected to the control signal terminal CONTRIL. The control signal terminal CONTRIL is configured to turn on the sixteenth transistor T16 when the pixel is in high refresh mode and turn off the sixteenth transistor T16 when the pixel is in low refresh mode. This improves the writing capability of the data signal DATA in high refresh mode and saves power in low refresh mode. The sixteenth transistor T16 is a low-temperature polysilicon transistor, while the seventeenth transistor T17 is a metal-oxide-slim film transistor. This effectively prevents the leakage current of the precharge signal terminal VRE-CHARGE from affecting the wire between the data signal terminal DATA and the data writing sub-circuit 10.

[0118] This application also provides a display panel, which includes the pixel driving circuit described above. The display panel further includes a plurality of sub-pixels, each sub-pixel corresponding to a pixel driving circuit, with each pixel driving circuit electrically connected to its corresponding sub-pixel to drive the sub-pixel.

[0119] The display panel includes multiple pixel driving circuits, multiple first light emission control signal lines, and multiple second light emission control signal lines. The multiple pixel driving circuits are arranged in multiple rows. The first light emission control signal terminal EM1 of a row of pixel driving circuits is connected to the same first light emission control signal line, and the second light emission control signal terminal EM2 of a row of pixel driving circuits is connected to the same second light emission control signal line.

[0120] As shown in Figure 15, when the pre-charge sub-circuit 80 includes the seventeenth transistor T17, in the pixel driving circuit, the control electrode of the seventeenth transistor T17 is connected to the first light-emitting control signal terminal EM1-N or the second light-emitting control signal terminal EM2-N of the n-row pixel driving circuit, where n is an integer greater than 0. Thus, when the light-emitting control signal provided by the first light-emitting control signal terminal EM1-N or the second light-emitting control signal terminal EM2-N of the n-row pixel driving circuit is at a high potential, the seventeenth transistor T17 is turned on, effectively ensuring that the pre-charge signal terminal VRE-CHARGE pre-charges the wires between the data signal terminal DATA and the data writing sub-circuit 10 before the pixel circuit performs data writing.

[0121] This application also provides a display device, which includes the display panel described above.

[0122] In one embodiment, the display device further includes a driver and a power supply circuit, wherein the driver is used to provide a driving signal for driving the sub-pixels to emit light, and the power supply circuit is used to supply power to the display substrate.

[0123] In one embodiment, the display device further includes a housing, and the display panel is disposed within the housing.

[0124] The display device provided in this application embodiment can be any device with display function, such as a mobile phone, tablet computer, television, laptop computer, or vehicle-mounted equipment.

[0125] It should be noted that the technical solutions or features described in the above embodiments can be combined or supplemented with each other without conflict. The scope of protection of this application is not limited to the precise structures described in the above embodiments and shown in the accompanying drawings; all modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A pixel driving circuit, characterized in that, For use in display panels; The pixel driving circuit includes: A data writing sub-circuit, connected to the data signal terminal and the first node, is configured to control the connection or disconnection between the data signal terminal and the first node; the data writing sub-circuit includes a first transistor and a second transistor; the first terminals of the first transistor and the second transistor are both connected to the data signal terminal, and the second terminals are both connected to the first node; the control terminal of the first transistor is connected to the high-brush scan signal terminal, and the control terminal of the second transistor is connected to the first scan signal terminal. The data writing sub-circuit is configured such that when the display panel is in high refresh mode, during the data writing phase, the high refresh scan signal terminal controls the first transistor to turn on, and the first scan signal terminal controls the second transistor to turn on. The first capacitor has one end connected to the first node and the other end connected to the second node; A driving sub-circuit, connected to the second node, the third node and the fourth node, is configured to control the connection or disconnection of the third node and the fourth node. The third node is connected to the light-emitting unit and the fourth node is connected to the first power signal terminal.

2. The pixel driving circuit according to claim 1, characterized in that, The data writing sub-circuit is further configured such that, when the display panel is in low refresh mode, during the data writing phase, the high refresh scan signal terminal controls the first transistor to turn off, and the first scan signal terminal controls the second transistor to turn on.

3. The pixel driving circuit according to claim 1, characterized in that, The pixel driving circuit also includes: A compensation sub-circuit, connected to the second node and the third node, is configured to compensate for the data signal; The compensation sub-circuit includes a fourth transistor, the first terminal of which is connected to the third node, the second terminal of which is connected to the second node, and the control terminal of which is connected to the second scan signal terminal. The fourth transistor is a metal oxide thin-film transistor.

4. The pixel driving circuit according to claim 3, characterized in that, The compensation sub-circuit also includes a tenth transistor; The first terminal of the tenth transistor is connected to the second terminal of the fourth transistor, the second terminal is connected to the second node, and the control terminal is connected to the second gate signal terminal; or the first terminal of the tenth transistor is connected to the third node, the second terminal is connected to the first terminal of the fourth transistor, and the control terminal is connected to the second gate signal terminal. The tenth transistor is a low-temperature polycrystalline silicon transistor.

5. The pixel driving circuit according to claim 1, characterized in that, The driving sub-circuit includes a third transistor and a ninth transistor; The first terminal of the third transistor is connected to the fourth node, the second terminal is connected to the third node, and the control terminal is connected to the second terminal of the ninth transistor; The first electrode of the ninth transistor is connected to the second node, and the control electrode is connected to the fourth scan signal terminal; the ninth transistor is a metal oxide thin film transistor.

6. The pixel driving circuit according to claim 5, characterized in that, The driving sub-circuit also includes a fifteenth transistor; The first terminal of the fifteenth transistor is connected to the second terminal of the ninth transistor, the second terminal is connected to the control terminal of the third transistor, and the control terminal is connected to the fourth gate signal terminal; or the first terminal of the fifteenth transistor is connected to the second node, the second terminal is connected to the first terminal of the ninth transistor, and the control terminal is connected to the fourth gate signal terminal. The fifteenth transistor is a low-temperature polycrystalline silicon transistor.

7. The pixel driving circuit according to claim 1, characterized in that, The pixel driving circuit also includes a first light emission control sub-circuit; The first light-emitting control sub-circuit includes a sixth transistor and an eleventh transistor, wherein one of the sixth transistor and the eleventh transistor is a low-temperature polycrystalline silicon transistor and the other is a metal oxide thin-film transistor; The first terminal of the sixth transistor is connected to the second terminal of the eleventh transistor, the second terminal is connected to the fourth node, and the control terminal is connected to the first light-emitting control signal terminal. The first electrode of the eleventh transistor is connected to the first power supply signal terminal, and the control electrode is connected to the first gate control signal terminal.

8. The pixel driving circuit according to claim 1, characterized in that, The pixel driving circuit also includes a second light emission control sub-circuit; The second light-emitting control sub-circuit includes a fifth transistor and a twelfth transistor, wherein one of the fifth transistor and the twelfth transistor is a low-temperature polycrystalline silicon transistor and the other is a metal oxide thin-film transistor; The first terminal of the fifth transistor is connected to the second terminal of the twelfth transistor, the second terminal is connected to the light-emitting unit, and the control terminal is connected to the second light-emitting control signal terminal; The first electrode of the twelfth transistor is connected to the third node, and the control electrode is connected to the second gate control signal terminal.

9. The pixel driving circuit according to claim 1, characterized in that, The pixel driving circuit also includes a first reset sub-circuit; The first reset circuit includes an eighth transistor and a thirteenth transistor, wherein one of the eighth transistor and the thirteenth transistor is a low-temperature polycrystalline silicon transistor and the other is a metal oxide thin-film transistor; The first terminal of the eighth transistor is connected to the second terminal of the thirteenth transistor, the second terminal is connected to the light-emitting unit, and the control terminal is connected to the third scanning signal terminal. The first terminal of the thirteenth transistor is connected to the second reset signal terminal, and the control terminal is connected to the third gate signal terminal.

10. The pixel driving circuit according to claim 1, characterized in that, The pixel driving circuit also includes a second reset sub-circuit; The second reset circuit includes a seventh transistor and a fourteenth transistor, wherein one of the seventh transistor and the fourteenth transistor is a low-temperature polysilicon transistor and the other is a metal oxide thin-film transistor; The first terminal of the seventh transistor is connected to the first reset signal terminal, the second terminal is connected to the first terminal of the fourteenth transistor, and the control terminal is connected to the third scan signal terminal; The second electrode of the fourteenth transistor is connected to the first node, and the control electrode is connected to the third gate signal terminal.

11. The pixel driving circuit according to claim 1, characterized in that, The pixel driving circuit also includes a pre-charge electronic circuit; The pre-charge sub-circuit is connected to the data signal terminal, and the data writing sub-circuit is connected to the data signal terminal via a wire. The pre-charge sub-circuit is configured to pre-charge the line between the data signal terminal and the data writing sub-circuit.

12. The pixel driving circuit according to claim 11, characterized in that, The pixel driving circuit further includes a first light emission control sub-circuit and a second light emission control sub-circuit. The first light emission control sub-circuit is connected between the first power signal terminal and the fourth node, and is also connected to the first light emission control signal terminal. The second light-emitting control sub-circuit is connected between the third node and the fourth node, and is connected to the second light-emitting control signal terminal; The precharged electronic circuit includes a seventeenth transistor; The first terminal of the seventeenth transistor is connected to the pre-charge signal terminal, the second terminal is connected to the wire between the data signal terminal and the data writing sub-circuit, and the control terminal is connected to the first light-emitting control signal terminal or the second light-emitting control signal terminal; the first light-emitting control signal terminal or the second light-emitting control signal terminal is configured to control the seventeenth transistor to be turned on before the data writing stage.

13. The pixel driving circuit according to claim 12, characterized in that, The precharged electronic circuit also includes a sixteenth transistor; The first terminal of the sixteenth transistor is connected to the second terminal of the seventeenth transistor, the second terminal is connected to the wire between the data signal terminal and the data writing sub-circuit, and the control terminal is connected to the control signal terminal.

14. The pixel driving circuit according to claim 13, characterized in that, The control signal terminal is configured to: control the sixteenth transistor to be turned on when the display panel is in high refresh mode, and control the sixteenth transistor to be turned off when the pixel is in low refresh mode.

15. A display panel, characterized in that, The display panel includes a pixel driving circuit as described in any one of claims 1-14.

16. The display panel according to claim 15, characterized in that, The display panel includes multiple pixel driving circuits, multiple first light emission control signal lines, and multiple second light emission control signal lines. The multiple pixel driving circuits are arranged in multiple rows. The first light emission control signal terminals of the pixel driving circuits in one row are connected to the same first light emission control signal line, and the second light emission control signal terminals of the pixel driving circuits in one row are connected to the same second light emission control signal line. When the precharge electronic circuit includes the seventeenth transistor, in the pixel driving circuit, the control terminal of the seventeenth transistor is connected to the first light emission control signal terminal or the second light emission control signal terminal of the n-row pixel driving circuit, where n is an integer greater than 0.

17. A display device, characterized in that, The display device includes the display panel as described in claim 15 or 16.

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