Method for acquiring log-likelihood ratio information of LDPC algorithm, and device and medium

Abstract

The present application relates to the technical field of flash memories. Disclosed are a method for acquiring log-likelihood ratio information of an LDPC algorithm, and a device and a medium. The method comprises: acquiring a data sequence to be decoded, and an LDPC parity-check matrix, wherein the LDPC parity-check matrix comprises a plurality of candidate row parity-check sequences; on the basis of said data sequence and the LDPC parity-check matrix, performing row parity-check processing to obtain a row parity-check result; on the basis of the row parity-check result, determining a target row parity-check sequence from among the plurality of candidate row parity-check sequences; performing sequence superposition processing on the target row parity-check sequence, so as to obtain a weight sequence; and on the basis of said data sequence, the weight sequence and a preset index mapping table, performing mapping processing to obtain log-likelihood ratio information, so as to perform, on the basis of said data sequence and the log-likelihood ratio information, LDPC decoding processing for flash memory error correction. Log-likelihood ratio information of an LDPC decoding algorithm can be quickly acquired, such that the LDPC decoding algorithm has both a relatively high decoding speed and a relatively strong decoding capability.

Description

Methods, devices, and media for obtaining log-likelihood ratio information of the LDPC algorithm Technical Field

[0001] This application relates to the field of flash memory technology, and in particular to a method, apparatus, and medium for obtaining log-likelihood ratio information of the LDPC algorithm. Background Technology

[0002] LDPC (Low-Density Parity-Check) is currently the mainstream algorithm for flash memory data error correction. There are two types of LDPC algorithms: hardware decoding and software decoding. Hardware decoding offers fast execution speed and low latency, but its decoding capability is relatively weak; software decoding offers strong decoding capability, but it is slow and has higher latency. The current mainstream approach is to combine both algorithms: first using hardware decoding, and then switching to software decoding if decoding fails. This approach ensures good decoding capability but requires more flash memory data recovery time, easily leading to data recovery timeouts; it also struggles to balance fast decoding speed and strong decoding capability. Therefore, how to achieve a balance between fast decoding speed and strong decoding capability in LDPC decoding is a problem that urgently needs to be solved. Summary of the Invention

[0003] This application aims to at least solve one of the technical problems existing in the prior art. To this end, this application proposes a method, apparatus, and medium for obtaining the log-likelihood ratio information of the LDPC algorithm, which can quickly obtain the log-likelihood ratio information of the LDPC decoding algorithm, thereby enabling the LDPC decoding algorithm to achieve both fast decoding speed and strong decoding capability.

[0004] In a first aspect, embodiments of this application provide a method for obtaining the log-likelihood ratio information of the LDPC algorithm, including:

[0005] Obtain the data sequence to be decoded and the LDPC check matrix; wherein the LDPC check matrix includes multiple candidate row check sequences;

[0006] Perform row check processing based on the data sequence to be decoded and the LDPC check matrix to obtain the row check result;

[0007] Based on the row verification results, a target row verification sequence is determined from the plurality of candidate row verification sequences;

[0008] The target row verification sequence is subjected to sequence superposition processing to obtain a weighted sequence;

[0009] The data sequence to be decoded, the weight sequence, and the preset index mapping table are used for mapping to obtain the log-likelihood ratio information, so as to perform LDPC decoding processing for flash memory error correction based on the data sequence to be decoded and the log-likelihood ratio information.

[0010] According to some embodiments of this application, the step of performing row check processing based on the data sequence to be decoded and the LDPC check matrix to obtain the row check result includes:

[0011] Obtain multiple candidate row check sequences from the LDPC check matrix;

[0012] Each candidate row check sequence is multiplied by the data sequence to be decoded to obtain an initial check value for each candidate row check sequence; each initial check value is then modulo-2 to obtain a row check value for each candidate row check sequence.

[0013] The row check result of each candidate row check sequence is determined based on the row check value of each candidate row check sequence.

[0014] According to some embodiments of this application, determining the row check result of each candidate row check sequence based on the row check value of each candidate row check sequence includes:

[0015] If the row check value of the candidate row check sequence is not equal to zero, the row check result of the candidate row check sequence is determined to be a check failure.

[0016] When the row check value of the candidate row check sequence is equal to zero, the row check result of the candidate row check sequence is determined to be a pass check.

[0017] According to some embodiments of this application, the row verification result includes: verification passed and verification failed; the step of determining the target row verification sequence from a plurality of candidate row verification sequences based on the row verification result includes:

[0018] When the row verification result is a verification failure, the candidate row verification sequence with the row verification result being a verification failure is determined as the target row verification sequence.

[0019] According to some embodiments of this application, there are at least two target row check sequences, and the number of columns in multiple target row check sequences is the same; the step of performing sequence superposition processing on the target row check sequences to obtain a weighted sequence includes:

[0020] Determine the column position and column position order of the target row verification sequence;

[0021] In multiple target row verification sequences, the elements corresponding to the same column position are summed to obtain the weight value of each column position;

[0022] The weight sequence is generated based on the column position order and the weight value of each column position.

[0023] According to some embodiments of this application, the step of performing mapping processing based on the data sequence to be decoded, the weight sequence, and a preset index mapping table to obtain log-likelihood ratio information includes:

[0024] Determine the column positions and column order of the data sequence to be decoded and the weight sequence; wherein the data sequence to be decoded and the weight sequence have the same number of columns;

[0025] At the same column position, the undecoded data value of the data sequence to be decoded is obtained, and the weight value of the weight sequence is obtained; and based on the undecoded data value and the weight value, the log-likelihood ratio corresponding to the column position is determined in the index mapping table;

[0026] After traversing all the column positions, the log-likelihood ratio corresponding to each column position is obtained;

[0027] Based on the positional order and the log-likelihood ratio corresponding to each of the column positions, an LLR value sequence is generated, and the LLR value sequence is determined as the log-likelihood ratio information.

[0028] According to some embodiments of this application, the index mapping table includes: a first mapping table and a second mapping table; determining the log-likelihood ratio corresponding to the column position in the index mapping table based on the unsolved data value and the weight value includes:

[0029] When the value of the data to be solved is 0, determine the first mapping table;

[0030] Based on the weight value, the log-likelihood ratio corresponding to the column position is determined from the first mapping table.

[0031] According to some embodiments of this application, the step of determining the log-likelihood ratio corresponding to the column position in the index mapping table based on the unsolved data value and the weight value further includes:

[0032] When the value of the data to be solved is 1, determine the second mapping table;

[0033] Based on the weight value, the log-likelihood ratio corresponding to the column position is determined from the second mapping table.

[0034] In a second aspect, embodiments of this application provide an electronic device, including at least one processor and a memory for communicatively connecting to the at least one processor; the memory stores instructions executable by the at least one processor, which, when executed by the at least one processor, enable the at least one processor to perform a method for obtaining log-likelihood ratio information of the LDPC algorithm as described in any of the embodiments of the first aspect.

[0035] Thirdly, embodiments of this application provide a computer-readable storage medium storing computer-executable instructions for causing a computer to perform a method for obtaining log-likelihood ratio information of the LDPC algorithm as described in any of the embodiments of the first aspect.

[0036] This application embodiment includes: In the process of performing flash memory LDPC error correction processing, firstly, the data sequence to be decoded and the LDPC parity matrix are obtained; wherein, the LDPC parity matrix includes multiple candidate row parity sequences; then, row parity processing is performed based on the data sequence to be decoded and the LDPC parity matrix to obtain row parity results; then, based on the row parity results, the target row parity sequence is determined from the multiple candidate row parity sequences; subsequently, the target row parity sequence is subjected to sequence superposition processing to obtain a weight sequence; the weight sequence is quickly determined through sequence superposition processing, providing a reliable reference for subsequent determination of log-likelihood ratio information; finally, based on the data sequence to be decoded, the weight sequence, and a preset... The index mapping table is used to perform mapping processing to obtain the log-likelihood ratio information, which is then used for LDPC decoding processing for flash memory error correction based on the data sequence to be decoded and the log-likelihood ratio information. By setting the index mapping table, the log-likelihood ratio information can be quickly determined based on the data sequence to be decoded and the weight sequence, which helps to reduce the latency of the overall LDPC decoding algorithm. In addition, applying the log-likelihood ratio information to the LDPC hard decoding process can effectively improve the decoding capability and convergence speed of the LDPC decoding algorithm. That is to say, the embodiments of this application can quickly obtain the log-likelihood ratio information of the LDPC decoding algorithm, so that the LDPC decoding algorithm can achieve both fast decoding speed and strong decoding capability.

[0037] Other features and advantages of this application will be set forth in the following description and will be apparent in part from the description or may be learned by practicing the application. The objectives and other advantages of this application may be realized and obtained by means of the structures particularly pointed out in the description and the accompanying drawings. Attached Figure Description

[0038] Figure 1 is a flowchart illustrating the steps of a method for obtaining the log-likelihood ratio information of the LDPC algorithm according to an embodiment of this application;

[0039] Figure 2 is a schematic diagram of the specific process of obtaining a weighted sequence after row verification and sequence superposition according to an embodiment of this application;

[0040] Figure 3 is a schematic diagram of an index mapping table provided in one embodiment of this application;

[0041] Figure 4 is a schematic diagram comparing the data sequence to be decoded, the weight sequence, and the LLR sequence provided in one embodiment of this application;

[0042] Figure 5 is a schematic diagram of the hardware structure of an electronic device provided in one embodiment of this application. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments.

[0044] It should be understood that in the description of this application, the orientation descriptions, such as up, down, front, back, left, right, etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0045] It should be noted that although a logical order is shown in the flowcharts in this application, in some cases, the steps shown or described may be performed in a different order than that shown in the flowcharts. In the description of this application, "several" means one or more, and "more" means two or more. The terms "first" and "second" are used only to distinguish technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of technical features indicated, or implicitly indicating the order in which the technical features are indicated.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0047] First, let me explain some of the terms used in this application:

[0048] Flash memory error correction technology is a key means to improve the data reliability of storage devices, and the LDPC (Low-density Parity-check) algorithm is one of the most efficient methods. The LDPC algorithm is widely used in NAND flash memory due to its excellent error correction capabilities.

[0049] LLR (Log-Likelihood Ratio) is a commonly used metric in signal detection and information theory to quantify the relative probability of the presence or absence of a signal.

[0050] This application discloses a method and electronic device, and a computer-readable storage medium for obtaining the log-likelihood ratio information of the LDPC algorithm, relating to the field of flash memory technology. The method includes: obtaining a data sequence to be decoded and an LDPC parity-check matrix; wherein the LDPC parity-check matrix includes multiple candidate row check sequences; performing row check processing based on the data sequence to be decoded and the LDPC parity-check matrix to obtain row check results; determining a target row check sequence from the multiple candidate row check sequences based on the row check results; performing sequence superposition processing on the target row check sequence to obtain a weight sequence; and performing mapping processing based on the data sequence to be decoded, the weight sequence, and a preset index mapping table to obtain log-likelihood ratio information, so as to perform LDPC decoding processing for flash memory error correction based on the data sequence to be decoded and the log-likelihood ratio information. This method can quickly obtain the log-likelihood ratio information of the LDPC decoding algorithm, enabling the LDPC decoding algorithm to balance fast decoding speed and strong decoding capability.

[0051] The embodiments of this application will be further described below with reference to the accompanying drawings.

[0052] Firstly, as shown in FIG1, FIG1 is a flowchart illustrating the steps of a method for obtaining the log-likelihood ratio information of the LDPC algorithm according to an embodiment of the present application; the method for obtaining the log-likelihood ratio information of the LDPC algorithm may include, but is not limited to, steps S110 to S150.

[0053] Step S110: Obtain the data sequence to be decoded and the LDPC check matrix; wherein, the LDPC check matrix includes multiple candidate row check sequences.

[0054] Step S120: Perform row check processing based on the data sequence to be decoded and the LDPC check matrix to obtain the row check result.

[0055] Step S130: Based on the row check results, determine the target row check sequence from multiple candidate row check sequences.

[0056] Step S140: Perform sequence superposition processing on the target row verification sequence to obtain the weight sequence.

[0057] Step S150: Perform mapping processing based on the data sequence to be decoded, the weight sequence, and the preset index mapping table to obtain the log-likelihood ratio information, and then perform LDPC decoding processing for flash memory error correction based on the data sequence to be decoded and the log-likelihood ratio information.

[0058] Specifically, the data sequence S to be decoded consists of binary digits 0 and 1; the data sequence S to be decoded is denoted as: S = [s1, s2, s3, ..., s n}

[0059] Specifically, the LDPC parity-check matrix H is an m-row, n-column matrix, denoted as:

[0060] It should be noted that the column weight information of the LDPC parity check matrix H is k. The column weight information k refers to the number of "1" elements in each column vector of the LDPC parity check matrix H. The LDPC parity check matrix H satisfies the condition that the number of "1" elements in each column vector is fixed, and there are k "1" elements.

[0061] It is important to emphasize that LDPC codes can be divided into regular and irregular types based on the H matrix. In regular LDPC codes, the row weights are consistent across all rows, and the column weights are consistent across all columns. Irregular LDPC codes have inconsistent row or column weights. Regular LDPC codes are more commonly used, and this application focuses on processing regular LDPC codes.

[0062] Specifically, each row vector in the LDPC check matrix H is a candidate row check sequence in step S110 of this embodiment. The candidate row check sequence is used as a row check formula to perform check processing with the data sequence S to be decoded.

[0063] Specifically, the row validation results include: validation passed and validation failed.

[0064] Specifically, in step S150, the LDPC decoding process for flash memory error correction based on the data sequence to be decoded and the log-likelihood ratio information includes: inputting the data sequence to be decoded and the log-likelihood ratio information into the LDPC error correction engine for decoding.

[0065] In this embodiment of the application, through steps S110 to S150, during the flash memory LDPC error correction processing, firstly, the data sequence to be decoded and the LDPC parity matrix are obtained; wherein, the LDPC parity matrix includes multiple candidate row parity sequences; next, row parity processing is performed based on the data sequence to be decoded and the LDPC parity matrix to obtain row parity results; then, based on the row parity results, the target row parity sequence is determined from the multiple candidate row parity sequences; subsequently, the target row parity sequence is subjected to sequence superposition processing to obtain a weight sequence; the weight sequence is quickly determined through sequence superposition processing, providing a reliable reference for subsequent determination of log-likelihood ratio information; finally, based on the data sequence to be decoded and the weight sequence, the target row parity sequence is determined; and finally, based on the data sequence to be decoded and the target row parity sequence, the target row parity sequence is determined; then, based on the target row parity sequence and the target row parity sequence, the target row parity sequence is determined; finally, based on the target row parity sequence and the target row parity sequence, the target row parity sequence is determined; and ... The re-sequence and a preset index mapping table are mapped to obtain the log-likelihood ratio information, which is then used for LDPC decoding for flash memory error correction based on the data sequence to be decoded and the log-likelihood ratio information. By setting the index mapping table, the log-likelihood ratio information can be quickly determined based on the data sequence to be decoded and the weight sequence, which helps to reduce the latency of the overall LDPC decoding algorithm. In addition, applying the log-likelihood ratio information to the LDPC hard decoding process can effectively improve the decoding capability and convergence speed of the LDPC decoding algorithm. Therefore, the embodiments of this application can quickly obtain the log-likelihood ratio information of the LDPC decoding algorithm, so that the LDPC decoding algorithm can achieve both fast decoding speed and strong decoding capability.

[0066] According to some embodiments of this application, step S120 is further described. Step S120: Perform row check processing based on the data sequence to be decoded and the LDPC check matrix to obtain the row check result, including but not limited to steps S121 to S123.

[0067] Step S121: Obtain multiple candidate row check sequences from the LDPC check matrix.

[0068] Step S122: Perform dot product processing on each candidate row check sequence and the data sequence to be decoded to obtain the initial check value of each candidate row check sequence; perform modulo 2 operation on each initial check value to obtain the row check value of each candidate row check sequence.

[0069] Step S123: Determine the row check result of each candidate row check sequence based on the row check value of each candidate row check sequence.

[0070] It is understandable that since the LDPC parity-check matrix H contains multiple row vectors, multiple candidate row parity sequences can be obtained from the LDPC parity-check matrix. The candidate row parity sequence for the i-th row can be represented as:

[0071] h i =[h i1 ,h i2 ,h i3 ,…,hin}, where i represents the row number, and the row number i is less than or equal to the number of rows m of the LDPC parity-check matrix H.

[0072] Specifically, the obtained candidate row verification sequence of the first row can be represented as:

[0073] h1 = [h 11 ,h 12 ,h 13 ,…,h 1n}

[0074] It is understandable that the candidate row check sequence consists of binary numbers 0 and 1; the 1 in the candidate row check sequence (i.e., row check formula) indicates that the corresponding bit of the data sequence to be decoded at the corresponding position participates in the check.

[0075] Step S121 yields multiple candidate row verification sequences, laying the data foundation for dot product processing.

[0076] Specifically, the dot product processing in step S122 refers to the sum of the products of corresponding positions between two vectors. The process of performing dot product processing on each candidate row check sequence with the data sequence to be decoded in step S122 to obtain the initial check values ​​of each candidate row check sequence can be performed simultaneously to improve check efficiency, thereby improving the overall efficiency of obtaining the log-likelihood ratio information of the LDPC decoding algorithm.

[0077] For example, the initial check value of the candidate row check sequence of the first row is obtained by performing a dot product operation between the candidate row check sequence of the first row and the data sequence to be decoded S. The initial check value is then processed by a modulo-2 operation to obtain the row check value A1. The specific calculation process of the row check value A1 is as follows:

[0078] A1 = (S·h1) mod 2 = [(s1*h 11 +s2*h 12 +s3*h 13 +…+s n *h 1n )]mod 2.

[0079] It is understandable that, because the initial check value was processed by modulo 2, all row check values ​​can only take the values ​​0 or 1.

[0080] It is understandable that the row check values ​​of each of the other candidate row check sequences can be obtained through step S122.

[0081] According to some embodiments of this application, step S123 is further described. Step S123: Based on the row check value of each candidate row check sequence, determine the row check result of each candidate row check sequence, including but not limited to: when the row check value of the candidate row check sequence is not equal to zero, determine that the row check result of the candidate row check sequence is a check failure; when the row check value of the candidate row check sequence is equal to zero, determine that the row check result of the candidate row check sequence is a check pass.

[0082] Specifically, for example: Suppose the data sequence S to be decoded is: [1, 0, 1, 1, 0, 0, 1, 1, 0].

[0083] When the candidate row verification sequence is h = [0, 0, 0, 0, 0, 0, 0, 1], the verification value is 0, and the verification passes.

[0084] If the candidate row check sequence is h = [1, 0, 0, 0, 0, 0, 0, 0, 1], then the check value is 1, which is not equal to zero, and the check fails.

[0085] Through steps S121 to S123, the row check results of each candidate row check sequence are determined, providing a reliable reference for the subsequent selection of the target row check sequence.

[0086] According to some embodiments of this application, the row verification result includes: verification passed and verification failed; further, step S130 is described as follows: based on the row verification result, a target row verification sequence is determined from multiple candidate row verification sequences, including: when the row verification result is verification failed, the candidate row verification sequence with the verification failed result is determined as the target row verification sequence. This provides a reliable reference for subsequent calculation of the weight sequence.

[0087] According to some embodiments of this application, step S140 is further described, which includes, but is not limited to: when there is only one target row check sequence, the target row check sequence is subjected to sequence superposition processing to obtain a weight sequence, and the weight sequence is the target row check sequence itself.

[0088] According to some embodiments of this application, there are at least two target row check sequences, and the number of columns in multiple target row check sequences is the same; further, step S140 is described as follows: the target row check sequences are subjected to sequence superposition processing to obtain a weight sequence, including but not limited to steps S141 to S143.

[0089] Step S141: Determine the column position and column position order of the target row verification sequence.

[0090] Step S142: In multiple target row verification sequences, sum up the elements corresponding to the same column position to obtain the weight value of each column position.

[0091] Step S143: Generate a weight sequence based on the column position order and the weight value of each column position.

[0092] It is understandable that a row check failure indicates that the position of the data sequence to be decoded corresponding to bit 1 in the candidate row check sequence where the row check failed has a bit flip.

[0093] It is understandable that in the weight sequence obtained by superimposing the target row verification sequences that are determined to have failed verification, the weight value corresponding to each column position is less than or equal to the column weight information k of the LDPC verification matrix. In the weight sequence, the larger the weight value corresponding to a certain column position, the greater the probability that the data bit at the corresponding position in the data sequence to be solved will be flipped.

[0094] Through steps S141 to S143, the weight sequence can be quickly determined by sequence superposition processing, providing a reliable reference for subsequent determination of log-likelihood ratio information.

[0095] Referring to Figure 2, an example is given to illustrate the specific process of obtaining the weighted sequence after row verification and sequence superposition.

[0096] Specifically, consider an LDPC parity check matrix H with m=5 rows and n=3 columns, and a data sequence S=[s1,s2,s3] to be decoded containing three data elements.

[0097] First, the LDPC parity check matrix H is determined to include five candidate row check sequences as shown in Figure 2: h1, h2, h3, h4, and h5. Row check processing is then performed based on the data sequence to be decoded and the LDPC parity check matrix, and the row check results are shown in Figure 2.

[0098] Secondly, the candidate row verification sequences h1, h2, h3 that fail the row verification are determined as the target row verification sequences.

[0099] Then, for the three target rows, the elements corresponding to the same column position are summed to obtain the weight value of each column position, as shown in Figure 2. The weight value corresponding to the first column is: w1 = h 11 +h 21 +h 31 The weight value corresponding to the second column is: w2 = h 12 +h 22 +h 32 The weight value corresponding to the third column is: w3 = h 13 +h 23 +h 33 .

[0100] Finally, the weight sequence W = [w1, w2, w3] is generated as shown in Figure 2.

[0101] According to some embodiments of this application, step S150 is further described. Step S150: Mapping is performed according to the data sequence to be decoded, the weight sequence and the preset index mapping table to obtain log-likelihood ratio information, including but not limited to steps S151 to S154.

[0102] Step S151: Determine the column positions and column order of the data sequence to be decoded and the weight sequence; wherein the data sequence to be decoded and the weight sequence have the same number of columns.

[0103] Step S152: At the same column position, obtain the data value to be decoded in the data sequence to be decoded, and obtain the weight value of the weight sequence; and determine the log-likelihood ratio corresponding to the column position in the index mapping table based on the data value to be decoded and the weight value.

[0104] Step S153: After traversing all column positions, obtain the log-likelihood ratio corresponding to each column position.

[0105] Step S154: Generate an LLR value sequence based on the positional order and the corresponding log-likelihood ratio values ​​of each column position, and determine the LLR value sequence as log-likelihood ratio information.

[0106] Specifically, the index mapping table includes: a first mapping table and a second mapping table.

[0107] According to some embodiments of this application, step S152 is further described, wherein determining the log-likelihood ratio corresponding to the column position in the index mapping table based on the data value to be solved and the weight value includes: when the data value to be solved is 0, determining a first mapping table; and determining the log-likelihood ratio corresponding to the column position from the first mapping table based on the weight value.

[0108] According to some embodiments of this application, step S152 is further described, wherein determining the log-likelihood ratio corresponding to the column position in the index mapping table based on the data value to be solved and the weight value further includes: when the data value to be solved is 1, determining a second mapping table; and determining the log-likelihood ratio corresponding to the column position from the second mapping table based on the weight value.

[0109] It should be noted that the weight values ​​in the weight sequence are less than or equal to the column weight information k of the LDPC parity-check matrix, so the weight values ​​range from 0 to k. An LLR value needs to be assigned to all possible weight values ​​in the index mapping table. The LLR value in the index mapping table can be set according to the actual situation; this application does not impose specific restrictions on this.

[0110] Through steps S151 to S154, this embodiment of the application can combine a preset index mapping table to quickly determine the LLR value at the corresponding position of the data sequence to be decoded based on the bit information at the corresponding position of the data sequence to be decoded and the weight sequence, and generate an LLR sequence based on multiple LLR values; that is, quickly generate the log-likelihood ratio information required for flash LDPC decoding. This allows the error correction capability of the LDPC decoding algorithm to be significantly improved after the probability information of the data sequence to be decoded and the log-likelihood ratio information is input into the LDPC decoding unit.

[0111] Referring to Figures 3 and 4, an example is given to illustrate the specific process by which this application determines the LLR sequence based on the data sequence to be decoded and the weight sequence using an index mapping table. As shown in Figure 3, the index mapping table provided in this embodiment includes a first mapping table and a second mapping table.

[0112] Specifically, when the undecoded data value in the first column of the acquired data sequence is 1, and the weight value in the first column of the acquired weight sequence is 0, then based on the undecoded data value of 1, the second mapping table is selected from the index mapping table shown in Figure 3. Furthermore, based on the weight value of 0, the LLR value is determined to be -7 in the second mapping table. Next, when the undecoded data value in the second column of the acquired data sequence is 0, and the weight value in the second column of the acquired weight sequence is 1, then based on the undecoded data value of 0, the first mapping table is selected from the index mapping table shown in Figure 3. Furthermore, based on the weight value of 1, the LLR value is determined to be 5 in the first mapping table. This process continues until the weight values ​​corresponding to each column position are obtained, ultimately generating the LLR sequence shown in Figure 4.

[0113] In summary, this embodiment of the application, by rapidly acquiring the probability information (i.e., log-likelihood ratio information) of the flash memory bits, performs LDPC decoding processing on the data sequence to be decoded and the log-likelihood ratio information, significantly improving the error correction capability of the LDPC decoding algorithm; and while improving the decoding capability, it ensures that the data recovery time is within a certain range, reducing the probability of data recovery timeout. It is evident that the decoding capability of the LDPC decoding algorithm based on the rapidly acquired log-likelihood ratio information in this embodiment of the application is stronger than that of the LDPC hardware decoding algorithm, and the decoding speed is faster than that of the LDPC software decoding algorithm. It achieves a balance between fast decoding speed and strong decoding capability.

[0114] Secondly, as shown in Figure 5, this application also provides an electronic device, including:

[0115] The processor 501 can be implemented using a general-purpose central processing unit (CPU), microprocessor, application specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this application.

[0116] The memory 502 can be implemented as a read-only memory (ROM), static storage device, dynamic storage device, or random access memory (RAM). The memory 502 can store the operating system and other application programs. When the technical solutions provided in the embodiments of this specification are implemented through software or firmware, the relevant program code is stored in the memory 502, and the processor 501 calls and executes the method for obtaining the log-likelihood ratio information of the LDPC algorithm according to the embodiments of this application.

[0117] The input / output interface 503 is used to implement information input and output;

[0118] The communication interface 504 is used to enable communication and interaction between this device and other devices. Communication can be achieved through wired means (such as USB, network cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.).

[0119] Bus 505 transmits information between various components of the device (e.g., processor 501, memory 502, input / output interface 503, and communication interface 504);

[0120] The processor 501, memory 502, input / output interface 503, and communication interface 504 are connected to each other within the device via bus 505.

[0121] Thirdly, embodiments of this application provide a computer-readable storage medium storing computer-executable instructions for causing a computer to perform a method for obtaining log-likelihood ratio information of the LDPC algorithm as described in any of the above embodiments.

[0122] Memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs. Furthermore, memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, memory may optionally include memory remotely located relative to the processor, and these remote memories can be connected to the processor via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof. The device embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separate, and may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0123] It will be understood by those skilled in the art that all or some of the steps and systems in the methods disclosed above can be implemented as software, firmware, hardware, and suitable combinations thereof. Some or all of the physical components can be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable medium, which can include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible to a computer. Furthermore, as is known to those skilled in the art, communication media typically include computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0124] The above provides a detailed description of the preferred embodiments of this application. However, this application is not limited to the above-described embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of this application. All such equivalent modifications or substitutions are included within the scope defined by this application.

Claims

1. A method for obtaining the log-likelihood ratio information of the LDPC algorithm, characterized in that, include: Obtain the data sequence to be decoded and the LDPC check matrix; wherein the LDPC check matrix includes multiple candidate row check sequences; Row verification is performed based on the data sequence to be decoded and the LDPC check matrix to obtain the row verification result; Based on the row verification results, a target row verification sequence is determined from a plurality of candidate row verification sequences; The target row verification sequence is subjected to sequence superposition processing to obtain a weight sequence; The data sequence to be decoded, the weight sequence, and the preset index mapping table are used for mapping to obtain the log-likelihood ratio information, so as to perform LDPC decoding processing for flash memory error correction based on the data sequence to be decoded and the log-likelihood ratio information.

2. The method for obtaining the log-likelihood ratio information of the LDPC algorithm according to claim 1, characterized in that, The step of performing row check processing based on the data sequence to be decoded and the LDPC check matrix to obtain the row check result includes: Obtain multiple candidate row check sequences from the LDPC check matrix; Each candidate row check sequence is multiplied by the data sequence to be decoded to obtain an initial check value for each candidate row check sequence; each initial check value is then modulo-2 to obtain a row check value for each candidate row check sequence. The row check result of each candidate row check sequence is determined based on the row check value of each candidate row check sequence.

3. The method for obtaining the log-likelihood ratio information of the LDPC algorithm according to claim 2, characterized in that, Determining the row check result of each candidate row check sequence based on the row check value of each candidate row check sequence includes: If the row check value of the candidate row check sequence is not equal to zero, the row check result of the candidate row check sequence is determined to be a check failure. When the row check value of the candidate row check sequence is equal to zero, the row check result of the candidate row check sequence is determined to be a pass check.

4. The method for obtaining the log-likelihood ratio information of the LDPC algorithm according to claim 1 or 3, characterized in that, The row validation result includes: validation passed and validation failed; the step of determining the target row validation sequence from the multiple candidate row validation sequences based on the row validation result includes: When the row verification result is a verification failure, the candidate row verification sequence with the row verification result being a verification failure is determined as the target row verification sequence.

5. The method for obtaining the log-likelihood ratio information of the LDPC algorithm according to claim 1, characterized in that, There are at least two target row check sequences, and multiple target row check sequences have the same number of columns; The step of performing sequence superposition processing on the target row verification sequence to obtain a weight sequence includes: Determine the column position and column position order of the target row verification sequence; In multiple target row verification sequences, the elements corresponding to the same column position are summed to obtain the weight value of each column position; The weight sequence is generated based on the column position order and the weight value of each column position.

6. The method for obtaining the log-likelihood ratio information of the LDPC algorithm according to claim 1, characterized in that, The step of mapping the data sequence to be decoded, the weight sequence, and a preset index mapping table to obtain the log-likelihood ratio information includes: Determine the column positions and column order of the data sequence to be decoded and the weight sequence; wherein the data sequence to be decoded and the weight sequence have the same number of columns; At the same column position, the undecoded data value of the data sequence to be decoded is obtained, and the weight value of the weight sequence is obtained; and based on the undecoded data value and the weight value, the log-likelihood ratio corresponding to the column position is determined in the index mapping table; After traversing all the column positions, the log-likelihood ratio corresponding to each column position is obtained; Based on the positional order and the log-likelihood ratio corresponding to each of the column positions, an LLR value sequence is generated, and the LLR value sequence is determined as the log-likelihood ratio information.

7. The method for obtaining the log-likelihood ratio information of the LDPC algorithm according to claim 6, characterized in that, The index mapping table includes: a first mapping table and a second mapping table; determining the log-likelihood ratio corresponding to the column position in the index mapping table based on the unsolved data value and the weight value includes: When the value of the data to be solved is 0, determine the first mapping table; Based on the weight value, the log-likelihood ratio corresponding to the column position is determined from the first mapping table.

8. The method for obtaining the log-likelihood ratio information of the LDPC algorithm according to claim 7, characterized in that, The step of determining the log-likelihood ratio corresponding to the column position in the index mapping table based on the unsolved data value and the weight value further includes: When the value of the data to be solved is 1, determine the second mapping table; Based on the weight value, the log-likelihood ratio corresponding to the column position is determined from the second mapping table.

9. An electronic device, characterized in that, The device includes at least one processor and a memory for communicatively connecting to the at least one processor; the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method for obtaining log-likelihood ratio information of the LDPC algorithm as described in any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions for causing a computer to perform the method for obtaining log-likelihood ratio information of the LDPC algorithm as described in any one of claims 1 to 8.

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