Erasure method for flash memory cell

Abstract

Provided in the present disclosure is an erasure method for a flash memory cell. The flash memory cell comprises storage transistors and a gating transistor that are connected in series. The erasure method in the present disclosure comprises: applying erasure voltages to electrodes of a flash memory cell and gate electrodes of transistors, wherein the erasure voltage applied to a gate electrode of a storage transistor to be subjected to erasure is lower than a second power source voltage, such that the physical effect of channel hot-electron induced hot hole injection occurs, and thus hot holes in a channel are attracted into a storage medium layer for erasing. Compared with existing band-to-band hot-hole (BBHH) erasure methods, the erasure method for a flash memory cell in the present disclosure provides wider hole distribution and higher injection efficiency, such that the erasure method in the present disclosure achieves a higher erasure speed, a larger erasure window, reduced hot-carrier damage, a lower leakage current and improved endurance reliability.

Description

Flash memory cell erasure method Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a method for erasing flash memory cells. Background Technology

[0002] Flash memory, or flash storage for short, is a type of non-volatile memory, meaning that stored data is retained even when power is off. It is particularly suitable for applications in mobile communications and computer storage components. Furthermore, some flash memories offer high-density storage capabilities, making them suitable for applications such as high-capacity mobile storage media.

[0003] Traditional flash memory employs a floating-gate cell structure. Floating-gate non-volatile memory originated from the MIMIS (Metal-Insulator-Metal-Insulator-Semiconductor) structure proposed by D. Kahng and S. Sze in 1967. This structure adds a metal floating gate and an ultra-thin tunneling oxide layer to the traditional MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), thereby utilizing the metal floating gate to store charge. Based on this, Masuoka et al. first proposed the concept of flash memory in 1984, achieving high-speed erasure capability through sector-based erasure and bit-by-bit writing (programming), and eliminating the select transistors required in EEPROM (Erasable Programmable Read-only memory), thus resulting in a smaller memory cell size. Since its advent, flash memory has rapidly developed due to its high write speed, high integration density, and superior performance. In 1988, Intel proposed the ETOX structure for flash memory cells (ETOX: Electron Tunneling Oxide device), which became the basis for the development of most floating gate flash memory cell structures to date.

[0004] However, floating-gate flash memory has the following drawbacks: its manufacturing process is relatively complex; the presence of the floating gate structure in the flash memory cell increases the vertical height of the gate structure, which is not conducive to proportionally reducing the process size and cell area; and because of the conductivity of the floating gate, the stored charge can move freely within the floating gate, thus hindering the improvement of memory reliability. To address the problems of complex manufacturing processes and poor reliability of floating-gate flash memory, researchers proposed a charge-trapping memory (CTM) that uses silicon nitride as the medium to store charge, also known as SONOS-type (Silicon-Oxide-Nitride-Oxide-Silicon) flash memory. Based on this, B. Eitan et al. proposed a two-bit memory cell structure, NROM (Nitride-Read-Only-Memory), in 2000. This cell structure utilizes the non-conductive property of the insulating silicon nitride storage medium to realize two storage bits at the source and drain terminals of a storage transistor, respectively. However, this cell structure suffers from drawbacks such as mutual interference between the two storage bits and the inability to reduce the device size.

[0005] However, existing floating-gate ETOX flash memories and SONOS-type NROM flash memories suffer from problems such as limited process size, large cell area, high write power consumption, and large array area overhead, making it impossible to achieve high-density integration with gigabit (Gb) capacity or higher.

[0006] With the rapid development of applications such as mobile smart terminals, wearable devices, and smart sensor networks, higher requirements have been placed on the power consumption, storage capacity, and cost of flash memory. Therefore, a flash memory technology with advantages such as low power consumption, small cell area, shrinkable process size, high array integration density, and large capacity is needed. Summary of the Invention

[0007] The information disclosed in this background section is only for understanding the background of the inventive concept, and therefore may contain information that does not constitute prior art.

[0008] To address the aforementioned problems in the prior art, this disclosure proposes a method for erasing flash memory cells.

[0009] According to one aspect of this disclosure, a method for erasing a flash memory cell is provided. The flash memory cell includes: a substrate and a well region disposed within the substrate; a storage transistor disposed on the well region and configured to store data; and a gate transistor disposed horizontally on one side of the storage transistor on the well region and configured to perform a gate operation on the storage transistor. The gate transistor and the storage transistor are connected in series. The source region of the storage transistor is connected to a first electrode of the flash memory cell, and the drain region of the gate transistor is connected to a second electrode of the flash memory cell. The erasing method includes: applying a second power supply voltage to the well region, applying a first erase voltage to the first electrode, and applying a second erase voltage to the second electrode. An erase operation is performed on the storage transistor by applying a third erase voltage to the gate electrode of the storage transistor and a fourth erase voltage to the gate electrode of the gate transistor, wherein the first erase voltage is higher than a preset voltage, the second erase voltage is equal to or higher than the second power supply voltage, the third erase voltage is equal to or lower than the second power supply voltage, and the fourth erase voltage is equal to or lower than the first power supply voltage, wherein the first power supply voltage is higher than the second power supply voltage, wherein the preset voltage is preset based on the carrier barrier height at the interface between the substrate and the gate dielectric stack of the storage transistor, and wherein the first erase voltage and the fourth erase voltage are higher than the second erase voltage, such that both the storage transistor and the gate transistor are turned on.

[0010] According to another aspect of this disclosure, a method for erasing a flash memory cell is provided. The flash memory cell includes: a substrate and a well region disposed within the substrate; a first storage transistor disposed on the well region and configured to store first data; a second storage transistor disposed on the well region and configured to store second data; and a gate transistor disposed horizontally on the well region between the first and second storage transistors, configured to isolate the first and second storage transistors and perform a gate operation on the first and second storage transistors, wherein the first storage transistor, the gate transistor, and the second storage transistor are connected in series, wherein the source region of the first storage transistor is connected to a first electrode of the flash memory cell, and the drain region of the second storage transistor is connected to a second electrode of the flash memory cell. The erasing method includes: applying a second power supply voltage to the well region, applying a first erase voltage to the first electrode or the second electrode, and applying the second erase voltage to the second electrode. The first or second storage transistor is erased by applying a third erase voltage to the gate electrode of the first or second storage transistor, applying a fourth erase voltage to the gate electrode of the gate transistor, and applying a fifth erase voltage to the gate electrode of the second or first storage transistor. The first erase voltage is higher than a preset voltage, the second erase voltage is equal to or higher than a second power supply voltage, the third erase voltage is equal to or lower than the second power supply voltage, and the fourth erase voltage is equal to or lower than the first power supply voltage. The first power supply voltage is higher than the second power supply voltage. The preset voltage is predetermined based on the carrier barrier height at the interface between the substrate and the gate dielectric stack of the first and second storage transistors. The first, fourth, and fifth erase voltages are higher than the second erase voltage, causing the first, second, and gate transistors to all conduct.

[0011] According to the erasure method of this disclosure, the erasure voltage applied to the gate electrode of the memory transistor to be erased is lower than the second power supply voltage, thereby causing a channel hot electron-induced hot hole injection physical effect to attract hot holes in the channel to the memory dielectric layer to achieve erasure. This results in a wider hole distribution and higher injection efficiency compared to the existing band-to-band tunneling hot hole (BBHH) erasure method. Therefore, the erasure method of this disclosure has a higher erasure speed (tens of microseconds), a larger erasure window, less hot carrier damage, lower leakage current, and higher durability and reliability.

[0012] However, the effects of this disclosure are not limited to those described above, and various extensions can be made without departing from the spirit and scope of this disclosure. It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory, and are intended to provide further illustration of the claimed disclosure. Attached Figure Description

[0013] The accompanying drawings, which are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the present disclosure and, together with the specification, serve to explain the inventive concept.

[0014] Figure 1 shows a cross-sectional view of a flash memory cell according to an embodiment of the present disclosure.

[0015] Figure 2 shows an equivalent circuit diagram of a flash memory cell according to an embodiment of the present disclosure.

[0016] Figure 3 shows a schematic diagram of performing an erase operation on a first storage transistor using an erase method according to an embodiment of the present disclosure.

[0017] Figure 4 shows a schematic diagram of performing an erase operation on a second storage transistor using an erase method according to an embodiment of the present disclosure.

[0018] Figure 5 shows a cross-sectional view of a flash memory cell according to another embodiment of the present disclosure.

[0019] Figure 6 shows an equivalent circuit diagram of a flash memory cell according to another embodiment of the present disclosure.

[0020] Figure 7 shows a schematic diagram of performing an erase operation on a storage transistor by an erase method according to another embodiment of the present disclosure. Detailed Implementation

[0021] In the following description, numerous specific details are set forth for illustrative purposes to provide a thorough understanding of the various exemplary embodiments or implementations of this disclosure. As used herein, "implementation" and "implementation" are interchangeable terms and are non-limiting examples of apparatus or methods employing one or more inventive concepts disclosed herein. However, it will be apparent that the exemplary embodiments may be practiced without these specific details or with one or more equivalent arrangements. Furthermore, the exemplary embodiments may be different, but not necessarily exclusive. For example, particular shapes, configurations, and characteristics of the exemplary embodiments may be used or implemented in other exemplary embodiments without departing from the inventive concept.

[0022] Unless otherwise stated, the exemplary embodiments described should be understood as exemplary features providing details of variations in some ways in which the inventive concept can be implemented in practice. Therefore, unless otherwise stated, features, components, modules, layers, films, substrates, regions and / or aspects (hereinafter individually or collectively referred to as “elements”) of various embodiments may be combined, separated, interchanged and / or rearranged without departing from the inventive concept.

[0023] The use of crosshairs and / or shading in the accompanying drawings is generally provided to clarify the boundaries between adjacent elements. Thus, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for particular materials, material properties, dimensions, proportions, commonalities between illustrated elements, and / or any other characteristics, properties, shapes, etc., of the elements, unless otherwise stated. Furthermore, in the drawings, the dimensions and relative dimensions of elements may be exaggerated for clarity and / or descriptive purposes. A particular order of processes may be performed differently than the order described when exemplary embodiments can be implemented in different ways. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of their description. Similarly, the same reference numerals denote the same elements.

[0024] When an element, such as a layer, is referred to as being "on," "connected to," or "coupled to" another element or layer, it may be directly on, directly connected to, or directly coupled to the other element or layer, or there may be an intervening element or layer. However, when an element or layer is referred to as being "directly" on, "directly connected to," or "directly coupled to" another element or layer, there is no intervening element or layer. Therefore, the term "connection" can refer to a physical, electrical, and / or fluid connection with or without an intervening element. Furthermore, the D1, D2, and D3 axes are not limited to the three axes of a Cartesian coordinate system, such as the x, y, and z axes, and can be interpreted in a broader sense. For example, the D1, D2, and D3 axes can be perpendicular to each other, or they can represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as X only, Y only, Z only, or any combination of two or more of X, Y, and Z, such as, for example, XYZ, XYY, YZ, and ZZ. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0025] Although the terms “first,” “second,” etc., may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Therefore, without departing from the teachings of this disclosure, the first element discussed below may be referred to as the second element.

[0026] Spatial relation terms, such as “below,” “under,” “below,” “down,” “above,” “above,” “higher,” and “side” (e.g., as in “sidewall”), are used herein for descriptive purposes to describe the relationship between one element and other elements as shown in the figures. Spatial relation terms are intended to cover different orientations of the device in use, operation, and / or manufacture other than those shown in the figures. For example, if the device in the figures is flipped, an element described as “below” or “under” other elements or features would be oriented as “above” other elements or features. Thus, the exemplary term “below” can cover both above and below orientations. Furthermore, the device may be oriented in other ways (e.g., rotated 90 degrees or otherwise), and therefore the spatial relation descriptive terms used herein are interpreted accordingly.

[0027] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, the singular forms “a,” “an,” and “the” are intended to also include the plural forms unless the context clearly indicates otherwise. Furthermore, when used in this specification, the terms “comprising” and / or “including” indicate the presence of the stated features, integers, steps, operations, elements, components, and / or groups thereof, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It should also be noted that, as used herein, the terms “substantially,” “about,” and other similar terms are used as approximations rather than terms of degree, and are therefore used to account for inherent deviations in measurements, calculations, and / or values ​​provided that are recognized by those skilled in the art.

[0028] The embodiments are described herein with reference to cross-sectional and / or exploded views, which are schematic diagrams of idealized embodiments and / or intermediate structures. Thus, variations in the illustrated shapes, for example due to manufacturing techniques and / or tolerances, are to be expected. Therefore, the embodiments disclosed herein should not necessarily be interpreted as limited to the specific shapes shown for a particular region, but rather include shape deviations caused, for example, by manufacturing. In this way, the regions shown in the figures can be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device, and therefore this is not necessarily intended to be limiting.

[0029] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms, such as those defined in common dictionaries, shall be interpreted as having meanings consistent with their meanings in the context of the relevant field and shall not be interpreted in an idealized or overly formal sense, unless expressly defined herein.

[0030] Figure 1 shows a cross-sectional view of a flash memory cell MC 100 according to an embodiment of the present disclosure.

[0031] As shown in FIG1, the flash memory cell MC 100 according to an embodiment of the present disclosure may include a substrate 101, which includes a deep well region DNW 103 of a second doping type and a well region PW 102 of a first doping type disposed on the deep well region DNW 103.

[0032] Although the first doping type is defined as P-type and the second doping type as N-type in FIG1 as an example, those skilled in the art will recognize that the present disclosure is not limited thereto, and the first doping type may also be N-type, in which case the second doping type may be P-type.

[0033] According to embodiments of this disclosure, substrate 101 may be, for example, a silicon (Si) substrate.

[0034] Furthermore, the flash memory cell MC 100 includes a first storage transistor MS110, a gating transistor MG 120, and a second storage transistor MD 130 connected in series. The first storage transistor MS 110 can be disposed on the well region PW 102 and stores first data DATA1. The second storage transistor MD 130 can be disposed on the well region PW 102 and stores second data DATA2. The gating transistor MG 120 is disposed horizontally DR1 on the well region PW 102 between the first storage transistor MS 110 and the second storage transistor MD 130, for isolating the first storage transistor MS 110 and the second storage transistor MD 130 and performing a gating operation on the first storage transistor MS 110 and the second storage transistor MD 130.

[0035] According to an embodiment of the present disclosure, the flash memory cell MC 100 includes two storage transistors MS110 and MD 130, so the flash memory cell MC 100 can realize the function of two-bit storage, that is, simultaneously storing the first data DATA1 and the second data DATA2.

[0036] Furthermore, as shown in Figure 1, the source region of the first storage transistor MS 110 is connected to the first electrode S of the flash memory cell MC 100, and it can also be referred to as the source S of the flash memory cell MC 100, while the drain region of the second storage transistor MD 130 is connected to the second electrode D of the flash memory cell MC 100, and it can also be referred to as the drain D of the flash memory cell MC 100.

[0037] Those skilled in the art will recognize that the source and drain of a flash memory cell are defined herein for ease of description; however, the definition of the source and drain of a flash memory cell is relative, and the terms "source" and "drain" may be used interchangeably under different operating conditions.

[0038] Furthermore, as shown in FIG1, the first storage transistor MS 110 has a gate structure including a channel region 111, a gate dielectric stack 112, a gate electrode 116, and a hard mask blocking portion 117 sequentially arranged along the vertical direction DR2. The gate dielectric stack 112 has a first oxide layer 113, a storage dielectric layer 114, and a second oxide layer 115 sequentially stacked along the vertical direction. Furthermore, the second storage transistor MD 130 has a gate structure including a channel region 131, a gate dielectric stack 132, a gate electrode 136, and a hard mask blocking portion 137 sequentially arranged along the vertical direction DR2. The gate dielectric stack 132 has a first oxide layer 133, a storage dielectric layer 134, and a second oxide layer 135 sequentially stacked along the vertical direction.

[0039] According to embodiments of this disclosure, the flash memory cell MC 100 includes two storage transistors MS110 and MD 130, thus enabling two-bit storage functionality.

[0040] According to an embodiment of the present disclosure, as shown in FIG1, the flash memory cell MC100 for two-bit storage can be composed of three closely arranged transistors, namely, a gating transistor MG 120 located in the middle of the flash memory cell MC 100, a first storage transistor MS 110 located at the first end of the flash memory cell MC 100, and a second storage transistor MD 130 located at the second end of the flash memory cell MC 100.

[0041] As shown in Figure 1, the flash memory cell MC 100 can be formed on the well region PW 102 within the semiconductor substrate 101. Furthermore, in order to isolate the well region PW 102 from the substrate 101 so that a voltage can be applied to the well region PW 102 under certain operating conditions, as shown in Figure 1, the well region PW 102 can be formed in a deep well region DNW 103.

[0042] As shown in Figure 1, a source region 140 formed by N-type doping is provided at the first end of the flash memory cell MC 100, and a drain region 150 formed by N-type doping is also provided at the second end of the flash memory cell MC 100. The source region 140 is connected to the upper metal source 142, i.e., the first electrode S, through a contact hole 141, and the drain region 150 is connected to the upper metal drain 152, i.e., the second electrode D, through a contact hole 151.

[0043] According to embodiments of this disclosure, the first electrode S and the second electrode D may comprise metal or highly doped polycrystalline silicon. When the first electrode S and the second electrode D are formed of metal, they may comprise at least one of the following materials: aluminum, titanium, titanium nitride, copper, tungsten, cobalt, and manganese.

[0044] As described above, as shown in FIG1, the gate structure of the first storage transistor MS 110 may, from bottom to top, include a channel region 111, a gate dielectric stack 112, a gate electrode 116, and a hard mask barrier 117 for sidewall self-alignment. According to embodiments of this disclosure, the gate electrode 116 may include, for example, polysilicon, a metal gate, a metal silicide material, or a combination of the above materials. According to embodiments of this disclosure, the hard mask barrier 117 may include, for example, silicon oxide, silicon nitride, a silicon glass material, or a combination of the above materials.

[0045] Furthermore, as shown in FIG1, the gate dielectric stack 112 has a first oxide layer (tunneling oxide layer) 113, a storage dielectric layer (charge storage layer) 114, and a second oxide layer (barrier oxide layer) 115 sequentially stacked from bottom to top along the vertical direction DR2. According to embodiments of the present disclosure, the first oxide layer 113 and the second oxide layer 115 may include, for example, silicon oxide or aluminum oxide. According to embodiments of the present disclosure, the thickness of the first oxide layer (tunneling oxide layer) 113 may be 1 to 6 nm.

[0046] According to embodiments of this disclosure, the storage medium layer 114 may include one or more layers of storage media. Furthermore, according to embodiments of this disclosure, the storage medium forming the storage medium layer 114 may include: mono- or multi-component oxides, such as hafnium oxide, tantalum oxide, titanium oxide, zirconium oxide, or hafnium aluminum oxide; mono- or multi-component nitrides, such as silicon nitride; mono- or multi-component nitrides, such as silicon oxynitride; polycrystalline silicon or nanocrystalline materials; or combinations of the above materials.

[0047] According to embodiments of this disclosure, when the storage medium layer 114 is formed of, for example, silicon nitride material, the first oxide layer 113, the storage medium layer 114, and the second oxide layer 115 can form a gate dielectric stack 112 as an ONO (oxide-nitride-oxide) composite storage medium. In this case, the first storage transistor MS 110 can be a SONOS (silicon-oxide-nitride-oxide-silicon) type storage transistor.

[0048] Furthermore, according to embodiments of this disclosure, the first storage transistor MS 110 may be another trap charge-trapping storage transistor with a similar operating mechanism to the SONOS type storage transistor. This type of storage transistor uses a high-K material rich in charge traps, such as silicon oxynitride, hafnium oxide, tantalum oxide, titanium oxide, zirconium oxide, hafnium aluminum oxide, etc., to replace the silicon nitride material in the SONOS memory as the storage medium layer 114.

[0049] Furthermore, according to embodiments of this disclosure, the first storage transistor MS 110 may also be a floating-gate storage transistor. This type of storage transistor uses polysilicon material instead of silicon nitride material in the SONOS memory to form a floating gate for storing charge, as the storage dielectric layer 114.

[0050] Furthermore, according to embodiments of this disclosure, the first storage transistor MS 110 may also be a nano-crystal memory, in which a nano-crystal material with quantum dots is used instead of silicon nitride material in the SONOS memory as the storage medium layer 114.

[0051] According to embodiments of this disclosure, the length of the gate electrode 116 of the first storage transistor MS 110 can be defined by the length of the hard mask blocking portion 117 disposed on the gate electrode 116 through a self-alignment process. Those skilled in the art should note that the term "length" as used herein refers to the dimension of the described object in the first direction DR1.

[0052] According to embodiments of this disclosure, except that it is disposed on the opposite side of the gate transistor MG 120, the second storage transistor MD 130 has the same structure as the first storage transistor MS 110 and can be manufactured by the same process as the first storage transistor MS 110. Therefore, for the sake of brevity, a detailed description of the structure of the second storage transistor MD 130 will be omitted here.

[0053] The gate structure of the gate transistor MG 120 may, from bottom to top, include a channel region 121, a gate dielectric layer 122, and a gate electrode 123. According to embodiments of this disclosure, the gate electrode 123 of the gate transistor MG 120 is connected to a word line, and the length of the gate electrode 123 is defined by the process dimensions of the photolithography process. According to embodiments of this disclosure, the gate dielectric layer 122 may include materials such as silicon oxide, silicon oxynitride, hafnium oxide, etc. Furthermore, according to embodiments of this disclosure, the gate electrode 123 may include materials such as polysilicon, a metal gate, a metal silicide, or a combination of the above materials.

[0054] According to embodiments of this disclosure, the channel regions 111, 131, and 121 of the first storage transistor MS 110, the second storage transistor MD 130, and the gating transistor MG 120 may all have a first doping type, and the doping concentration of the channel regions 111 and 131 of the first storage transistor MS 110 and the second storage transistor MD 130 may be lower than the doping concentration of the channel region 121 of the gating transistor MG 120.

[0055] Furthermore, according to embodiments of this disclosure, the channel regions 111 and 131 of the first storage transistor MS 110 and the second storage transistor MD 130 may have a second doping type or an undoped intrinsic channel region, and the channel region 121 of the gate transistor MG 120 may have a first doping type different from the second doping type.

[0056] For example, as shown in FIG1, when the first doping type is P-type and the second doping type is N-type, the doping concentration of the P-type channels 111 and 131 of the first storage transistor MS 110 and the second storage transistor MD 130 is lower than the doping concentration of the P-type channel 121 of the gate transistor MG 120. Furthermore, according to embodiments of this disclosure, channel regions 111 and 131 may also be undoped intrinsic channels or N-type doped channel regions.

[0057] According to embodiments of this disclosure, the flash memory cell MC 100 may further include: a first isolation portion 124 disposed horizontally DR1 between the first storage transistor MS 110 and the gate transistor MG 120, for isolating the gate electrode 116 of the first storage transistor MS 110 and the gate electrode 123 of the gate transistor MG 120; and a second isolation portion 125 disposed horizontally DR1 between the gate transistor MG 120 and the second storage transistor MD 130, for isolating the gate electrode 123 of the gate transistor MG 120 and the gate electrode 136 of the second storage transistor MD 130.

[0058] Specifically, as shown in FIG1, a first isolation portion 124 and a second isolation portion 125 in the form of sidewalls are provided on both sides of the gate electrode 123 of the gate transistor MG 120. They are used to electrically isolate the gate electrode 116 of the first storage transistor MS 110 and the gate electrode 136 of the second storage transistor MD 130 with a specific isolation gap length, respectively. According to an embodiment of the present disclosure, the first isolation portion 124 and the second isolation portion 125 may include the same material as the gate dielectric layer 122.

[0059] The flash memory cell according to the embodiments of this disclosure can realize two storage transistors in one flash memory cell, thus greatly reducing the equivalent area of ​​each storage bit, thereby achieving lower cost and higher integration density.

[0060] Furthermore, the storage transistors in the flash memory cells according to the embodiments of this disclosure can adopt a simple SONOS-type device structure, which has the advantages of simple process, low gate electrode operating voltage, and good data retention reliability.

[0061] Furthermore, in the flash memory cell according to the embodiments of this disclosure, the mutual influence between two storage bits is isolated by a gating transistor, and the distribution width and lateral diffusion of the storage charge are suppressed, thereby enabling a higher storage charge density to be obtained in the silicon nitride storage layer. This avoids the problems of wide charge distribution, large mutual interference, and inability to reduce gate length that exist in existing NROM storage cells that also use two storage bits, and significantly improves the storage window and data reliability.

[0062] Specifically, the equivalent channel length of the flash memory cell according to embodiments of this disclosure is the sum of the lengths of the gate electrodes of the first storage transistor, the gate transistor, and the second storage transistor. As described above, the gate electrode length of the gate transistor is defined by the process feature size of the photolithography process, and is typically approximately equal to or slightly larger than the critical feature size of the photolithography process, which is usually denoted as F (or CF). Furthermore, the gate electrode lengths of the first and second storage transistors are each defined by the length of the self-aligned sidewall hard mask blocking portion, and therefore their dimensions can be smaller than F. Thus, according to embodiments of this disclosure, a smaller channel length of the flash memory cell can be obtained with the same process feature size, thereby achieving the goal of reducing the area and manufacturing cost of the flash memory cell.

[0063] Furthermore, in a flash memory cell array composed of flash memory cells according to embodiments of the present disclosure, for flash memory cells not selected for operation, the gate electrodes of the selection transistor and the first and second storage transistors are grounded, thereby completely turning off the entire series channel of the flash memory cell and increasing the equivalent channel length. This avoids source-drain punch-through of the flash memory cell under high operating voltages at smaller process feature sizes, thus overcoming the problem that the gate electrode length of existing flash memory cells cannot be reduced as process feature sizes shrink. Therefore, the flash memory cells according to embodiments of the present disclosure have better process miniaturization capabilities, thereby enabling smaller cell areas and manufacturing costs by reducing process feature sizes.

[0064] Furthermore, in the flash memory cell according to embodiments of this disclosure, by reducing the doping concentration of the P-type channel regions of the first and second storage transistors or designing them as N-type doped channel regions, the threshold voltage of the storage transistors and the gate electrode operating voltage during erase, write, and read operations can be reduced, thereby improving the reliability of the storage transistors. Simultaneously, by increasing the doping concentration of the P-type channel region of the gate transistor, the punch-through voltage of the flash memory cell can be increased, and the leakage current between the source and drain of unselected flash memory cells can be reduced.

[0065] Figure 2 shows an equivalent circuit diagram of the flash memory cell MC 100 according to an embodiment of the present disclosure. Figure 3 shows a schematic diagram of performing an erase operation on the first storage transistor MS110 according to the erase method of an embodiment of the present disclosure. Figure 4 shows a schematic diagram of performing an erase operation on the second storage transistor MD 130 according to the erase method of an embodiment of the present disclosure.

[0066] Specifically, as shown in Figure 2, the flash memory cell MC 100 includes a first storage transistor MS 110, a gating transistor MG 120, and a second storage transistor MD 130 connected in series. The gating transistor MG 120 can isolate the first storage transistor MS 110 and the second storage transistor MD 130 and perform a gating operation on the first storage transistor MS 110 and the second storage transistor MD 130. As shown in Figure 2, by controlling the voltage applied to the source region (i.e., the first electrode S) of the first storage transistor MS 110, the gate electrode 116 of the first storage transistor MS 110, the gate electrode 123 of the gating transistor MG 120, the gate electrode 136 of the second storage transistor MD 130, and the drain region (i.e., the second electrode D) of the second storage transistor MD 130, the erase operation of the first storage transistor MS 110 or the second storage transistor MD 130 can be realized respectively.

[0067] According to an embodiment of this disclosure, when performing an erase operation on the flash memory cell MC 100, the well region PW 102 of the flash memory cell MC 100 can be grounded.

[0068] Specifically, according to an embodiment of this disclosure, as shown in FIG3, when performing an erase operation on the first storage transistor MS 110 of the flash memory cell MC 100, the erase method according to this disclosure includes applying a second power supply voltage VSS to the well region PW 102, applying a first erase voltage VE1 to the first electrode S, applying a second erase voltage VE2 to the second electrode D, applying a third erase voltage VE3 to the gate electrode 116 of the first storage transistor MS 110, applying a fourth erase voltage VE4 to the gate electrode 123 of the gate transistor MG 120, and applying a fifth erase voltage VE5 to the gate electrode 136 of the second storage transistor MD 130. For example, the second power supply voltage VSS can be ground voltage GND, such as 0V.

[0069] According to embodiments of this disclosure, the first erase voltage VE1 can be higher than a preset voltage VP, wherein the preset voltage VP is predetermined based on the carrier barrier height at the interface between the substrate and the gate dielectric stack 112 of the first storage transistor MS 110. For example, in the flash memory cell MC 100 shown in FIG. 1, the preset voltage allows carriers to overcome the carrier barrier at the interface between the P-type channel region 111 and the lower first oxide layer (tunneling oxide) 113 in the gate dielectric stack 112. For example, if the P-type channel region 111 comprises silicon and the first oxide layer 113 comprises silicon dioxide, the carriers are holes, and the hole barrier height is 4.8 electron volts (eV). In this case, the first erase voltage VE1 is typically greater than 4 volts (V). For example, the first erase voltage VE1 can be in the range of 3V to 6V, such as 4.6V. According to embodiments of this disclosure, the first erase voltage VE1 can be provided by an external constant voltage source.

[0070] According to embodiments of this disclosure, the second erase voltage VE2 can be equal to or higher than the second power supply voltage VSS, wherein the second power supply voltage VSS can be ground voltage GND. For example, according to embodiments of this disclosure, the second erase voltage VE2 can be 0.2V.

[0071] According to embodiments of this disclosure, the third erase voltage VE3 can be equal to or lower than the second power supply voltage VSS. According to embodiments of this disclosure, the third erase voltage VE3 can be in the range of -8V to 0V. For example, according to embodiments of this disclosure, the third erase voltage VE3 can be -4.8V.

[0072] According to an embodiment of this disclosure, a negative third erase voltage VE3 applied to the gate electrode 116 of the first storage transistor MS 110 can attract ionized hot holes (hollow circles in FIG. 3 representing holes) in the depletion region of the first electrode S (source) and inject them into the storage dielectric layer 114, such as silicon nitride, in the gate dielectric stack 112 of the first storage transistor MS 110 (as shown by the hollow arrow in FIG. 3). These hot holes neutralize electrons (solid circles in FIG. 3 representing electrons) stored during the write (programming) operation of the flash memory cell MC 100, causing the threshold voltage of the first storage transistor MS 110 to drop, thereby erasing the first storage transistor MS 110.

[0073] According to embodiments of this disclosure, the fourth erase voltage VE4 may be equal to or lower than the first power supply voltage VDD, wherein the first power supply voltage VDD is higher than the second power supply voltage VSS, and may be in the range of 0.8V to 5V. For example, according to embodiments of this disclosure, the fourth erase voltage VE4 may be 1V.

[0074] According to the embodiments of this disclosure, the first erase voltage VE1, the fourth erase voltage VE4, and the fifth erase voltage VE5 are higher than the second erase voltage VE2, so that the first storage transistor MS 110, the second storage transistor MD 130, and the gating transistor MG 120 are all turned on, that is, the flash memory cell MC100 is turned on as a whole.

[0075] According to embodiments of this disclosure, the fifth erase voltage VE5 can be in the range of 3V to 8V. For example, according to embodiments of this disclosure, the fifth erase voltage VE5 can be 5V.

[0076] Similarly, according to an embodiment of the present disclosure, as shown in FIG4, when performing an erase operation on the second storage transistor MD 130 of the flash memory cell MC 100, the erase method according to the present disclosure includes applying a second power supply voltage VSS to the well region PW 102, applying a first erase voltage VE1 to the second electrode D, applying a second erase voltage VE2 to the first electrode S, applying a fifth erase voltage VE5 to the gate electrode 116 of the first storage transistor MS 110, applying a fourth erase voltage VE4 to the gate electrode 123 of the gate transistor MG 120, and applying a third erase voltage VE3 to the gate electrode 136 of the second storage transistor MD 130.

[0077] As can be seen, due to the symmetrical structure of the flash memory cell MC 100, the erase voltages VE1 to VW5 applied during the erasure of the first storage transistor MS 110 and the second storage transistor MD 130 also exhibit a symmetrical relationship. Therefore, for the sake of simplicity, the erase voltage applied during the erasure of the second storage transistor MD 130 will not be described repeatedly here.

[0078] Specifically, taking the first storage transistor MS 110 as an example, when performing an erase operation on the first storage transistor MS 110, a fourth erase voltage VE4, slightly higher than its threshold voltage, is applied to the gate electrode 123 of the turn-on transistor MG 120, thus placing it in a weakly on-conducting state. This suppresses the on-current of the flash memory cell MC 100 (typically in the microampere range), which greatly reduces the voltage difference between the series channels (121 and 131) of the turn-on transistor MG 120 and the second storage transistor MD 130. Therefore, the voltage difference VE1-VE2 between the first electrode S and the second electrode D of the flash memory cell MC 110 is mostly applied to the channel region 111 of the first storage transistor MS 110, resulting in the channel hot electron-induced hot hole injection physical effect.

[0079] In particular, the erasure method according to the embodiments of this disclosure is based on the channel hot electron-induced hot hole injection physical effect first discovered by the inventors. Specifically, taking the erasure of the first storage transistor MS 110 as an example, when the erasure operation is performed on the first storage transistor MS 110, the selection transistor MG 120 and the second storage transistor MD 130 are turned on. At the same time, the first erasure voltage VE1 applied to the first electrode 142 completely depletes the channel region 111 of the first storage transistor MS 110, forming a depletion region. The flash memory cell MC 100 is turned on as a whole. An electron current is generated in the channel region and hot electrons are formed under the acceleration of the transverse electric field. Then, electron-hole pairs are generated in the depletion region through collisional ionization. The hot holes are injected into the storage medium layer 114 of the first storage transistor MS 110 under the attraction of the negative third erasure voltage VE3 applied to the gate electrode 116 of the first storage transistor MS 110, thereby realizing the erasure of the first storage transistor MS 110.

[0080] According to an embodiment of this disclosure, when an erase operation is performed on the first storage transistor MS 110, since the fourth erase voltage VE4 applied to the gate electrode 123 of the gating transistor MG 120 and the erase voltage VE5 applied to the gate electrode 136 of the second storage transistor MD 130 are both higher than the second power supply voltage VSS, i.e., positive voltages, the second storage transistor MD 130 and the gating transistor MG 120 are turned on. Furthermore, according to an embodiment of this disclosure, when an erase operation is performed on the first storage transistor MS 110, although the third erase voltage VE3 applied to the gate electrode 116 of the first storage transistor MS 110 is equal to or lower than the second power supply voltage VSS, as described above, since the first erase voltage VE1 completely depletes the channel region 111 of the first storage transistor MS 110 to form a depletion region, the first storage transistor MS 110 is still turned on. Therefore, when the erase method according to an embodiment of this disclosure is performed, the flash memory cell MC 100 is turned on overall.

[0081] Although the first doping type is limited to P-type and the second doping type to N-type in the above example, such that the first storage transistor MS 110, the gating transistor MG 120, and the second storage transistor MD 130 are all N-type transistors, those skilled in the art will recognize that this disclosure is not limited thereto, and the first doping type can also be N-type, and correspondingly the second doping type can be P-type, in which case the first storage transistor MS 110, the gating transistor MG 120, and the second storage transistor MD 130 are all P-type transistors. In this case, the erasure method according to the embodiments of this disclosure is based on the channel hot hole-induced hot electron injection (CHOTI) physical effect, the basic principle of which is consistent with the channel hot electron-induced hot hole injection physical effect described above, and therefore will not be described in more detail.

[0082] Furthermore, since the gate electrode length of the first storage transistor MS 110 is much smaller than the equivalent channel length of the flash memory cell MC 100, the lateral electric field and channel hot hole injection efficiency of the conduction channel of the first storage transistor MS 110 can be significantly increased.

[0083] Those skilled in the art will recognize that although the method for erasing a flash memory cell of this disclosure has been described above in conjunction with the flash memory cell MC 100 shown in FIG1, the method for erasing a flash memory cell of this disclosure is not limited to the flash memory cell MC 100 shown in FIG1. ​​Based on the teachings of this disclosure, those skilled in the art can conceive of applying the method for erasing a flash memory cell of this disclosure to other types of flash memory cells, such as flash memory cells comprising only one storage transistor, and all such variations should be covered within the scope of this disclosure.

[0084] Figure 5 shows a cross-sectional view of a flash memory cell MC 200 according to another embodiment of the present disclosure. Figure 6 shows an equivalent circuit diagram of a flash memory cell MC 200 according to another embodiment of the present disclosure.

[0085] As shown in Figures 5 and 6, the flash memory cell MC 200 differs from the flash memory cell MC 100 described above with reference to Figures 1 and 2 only in that the flash memory cell MC 200 includes only one storage transistor, which may correspond to the first storage transistor MS 110 in the flash memory cell MC 100. Therefore, in the flash memory cell MC 200 shown in Figures 5 and 6, the same components as those in the flash memory cell MC 100 shown in Figures 1 and 2 are indicated by the same reference numerals, and the corresponding detailed descriptions will be omitted.

[0086] As shown in FIG5, a flash memory cell MC 200 according to another embodiment of the present disclosure may include a substrate 101, which includes a deep well region DNW 103 of a second doping type and a well region PW 102 of a first doping type disposed on the deep well region DNW 103. According to an embodiment of the present disclosure, the substrate 101 may be, for example, a silicon (Si) substrate.

[0087] As shown in Figures 5 and 6, according to another embodiment of this disclosure, the flash memory cell MC 200 includes a storage transistor MS 110 and a gating transistor MG 120 connected in series. The storage transistor MS 110 may be disposed on the well region PW 102 and stores data DATA1. The gating transistor MG 120 is disposed on one side of the storage transistor MS 110 on the well region PW 102 along the horizontal direction DR1, and is used to perform a gating operation on the storage transistor MS 110.

[0088] As shown in FIG5, according to another embodiment of the present disclosure, the source region of the storage transistor MS 110 is connected to the first electrode S of the flash memory cell MC 200, which may also be referred to as the source S of the flash memory cell MC 200, and the drain region of the gate transistor MG 120 is connected to the second electrode D of the flash memory cell MC 200, which may also be referred to as the drain D of the flash memory cell MC 200.

[0089] As shown in FIG5, according to another embodiment of the present disclosure, the storage transistor MS 110 has a gate structure including a channel region 111, a gate dielectric stack 112, a gate electrode 116, and a hard mask blocking portion 117 sequentially disposed along the vertical direction DR2. The gate dielectric stack 112 has a first oxide layer 113, a storage dielectric layer 114, and a second oxide layer 115 sequentially stacked along the vertical direction. According to an embodiment of the present disclosure, when the storage dielectric layer 114 is formed of, for example, silicon nitride, the first oxide layer 113, the storage dielectric layer 114, and the second oxide layer 115 can form a gate dielectric stack 112 as an ONO composite storage dielectric. In this case, the storage transistor MS 110 can be a SONOS type storage transistor.

[0090] As shown in Figure 5, according to another embodiment of the present disclosure, the gate structure of the gate transistor MG 120 may include, from bottom to top, a channel region 121, a gate dielectric layer 122, and a gate electrode 123.

[0091] As shown in Figure 5, according to another embodiment of this disclosure, a source region 140 formed by N-type doping is provided at the first end of the flash memory cell MC 200, and a drain region 150 formed by N-type doping is also provided at the second end of the flash memory cell MC 200. The source region 140 is connected to the upper metal source 142, i.e., the first electrode S, through a contact hole 141, and the drain region 150 is connected to the upper metal drain 152, i.e., the second electrode D, through a contact hole 151.

[0092] As shown in FIG5, according to another embodiment of the present disclosure, the flash memory cell MC 200 may further include an isolation section 124, which is disposed in the horizontal direction DR1 between the storage transistor MS 110 and the gate transistor MG 120 for isolating the gate electrode 116 of the storage transistor MS 110 and the gate electrode 123 of the gate transistor MG 120.

[0093] Figure 7 shows a schematic diagram of performing an erase operation on the storage transistor MS 110 by an erase method according to another embodiment of the present disclosure.

[0094] Specifically, as shown in Figure 6, the flash memory cell MC 200 includes a storage transistor MS 110 and a gating transistor MG 120 connected in series. The gating transistor MG 120 can perform a gating operation on the storage transistor MS 110. As shown in Figure 6, by controlling the voltage applied to the source region (i.e., the first electrode S) of the storage transistor MS 110, the gate electrode 116 of the storage transistor MS 110, the gate electrode 123 of the gating transistor MG 120, and the drain region (i.e., the second electrode D) of the gating transistor MG 120, an erase operation on the storage transistor MS 110 can be achieved.

[0095] According to another embodiment of this disclosure, when performing an erase operation on the flash memory cell MC 200, the well region PW 102 of the flash memory cell MC 200 can be grounded.

[0096] Specifically, according to another embodiment of this disclosure, as shown in FIG7, when performing an erase operation on the storage transistor MS 110 of the flash memory cell MC 200, the erase method according to this disclosure includes applying a second power supply voltage VSS to the well region PW 102, applying a first erase voltage VE1 to the first electrode S, applying a second erase voltage VE2 to the second electrode D, applying a third erase voltage VE3 to the gate electrode 116 of the storage transistor MS 110, and applying a fourth erase voltage VE4 to the gate electrode 123 of the gate transistor MG 120. For example, the second power supply voltage VSS can be ground voltage GND, such as 0V.

[0097] According to another embodiment of this disclosure, the first erase voltage VE1 can be higher than a preset voltage VP, wherein the preset voltage VP is preset based on the carrier barrier height at the interface between the substrate and the gate dielectric stack 112 of the storage transistor MS 110. For example, in the flash memory cell MC 200 shown in FIG. 5, the preset voltage allows holes to overcome the hole barrier at the interface between the P-type channel region 111 and the lower first oxide layer (tunneling oxide) 113 in the gate dielectric stack 112. For example, if the P-type channel region 111 comprises silicon and the first oxide layer 113 comprises silicon dioxide, the barrier height is 4.8 electron volts (eV). In this case, the first erase voltage VE1 is typically greater than 4 volts (V). For example, the first erase voltage VE1 can be in the range of 3V to 6V, for example, the first erase voltage VE1 can be 4.6V. According to an embodiment of this disclosure, the first erase voltage VE1 can be provided by an external constant voltage source.

[0098] According to another embodiment of this disclosure, the second erase voltage VE2 can be equal to or higher than the second power supply voltage VSS, wherein the second power supply voltage VSS can be ground voltage GND. For example, according to an embodiment of this disclosure, the second erase voltage VE2 can be 0.2V.

[0099] According to another embodiment of this disclosure, the third erase voltage VE3 can be equal to or lower than the second power supply voltage VSS. According to an embodiment of this disclosure, the third erase voltage VE3 can be in the range of -8V to 0V. For example, according to an embodiment of this disclosure, the third erase voltage VE3 can be -4.8V.

[0100] According to another embodiment of this disclosure, a negative third erase voltage VE3 applied to the gate electrode 116 of the storage transistor MS 110 can attract ionized hot holes (holes represented by hollow circles in FIG. 7) in the depletion region of the first electrode S (source) and inject them into the storage dielectric layer 114, such as silicon nitride, in the gate dielectric stack 112 of the storage transistor MS 110 (as shown by the hollow arrow in FIG. 3). These hot holes neutralize electrons (electrons represented by solid circles in FIG. 7) stored during the write (programming) operation of the flash memory cell MC200, causing the threshold voltage of the storage transistor MS 110 to drop, thereby erasing the storage transistor MS 110.

[0101] According to embodiments of this disclosure, the fourth erase voltage VE4 may be equal to or lower than the first power supply voltage VDD, wherein the first power supply voltage VDD is higher than the second power supply voltage VSS, and may be in the range of 0.8V to 5V. For example, according to embodiments of this disclosure, the fourth erase voltage VE4 may be 1V.

[0102] According to the embodiments of this disclosure, the first erase voltage VE1 and the fourth erase voltage VE4 are higher than the second erase voltage VE2, so that both the storage transistor MS 110 and the gating transistor MG 120 are turned on, that is, the flash memory cell MC 200 is turned on as a whole.

[0103] The erasure method according to another embodiment of this disclosure is also based on the channel hot electron-induced hot hole injection physical effect first discovered by the inventors, therefore, for the sake of brevity, it will not be described in further detail here.

[0104] The erasure method according to the embodiments of this disclosure is based on the channel hot electron-induced hot hole injection physical effect first discovered by the inventors. Compared with the existing band-to-band tunneling hot hole (BBHH) erasure method, it has a wider hole distribution and higher injection efficiency, which makes the erasure method according to the embodiments of this disclosure have a higher erasure speed (tens of microseconds), a larger erasure window, less hot carrier damage, lower leakage current and higher durability and reliability.

[0105] Although this disclosure has been described with reference to embodiments thereof, those skilled in the art will understand that various modifications and changes may be made to this disclosure without departing from the spirit and scope of the disclosure as disclosed in the appended claims.

Claims

1. A method for erasing a flash memory cell, the flash memory cell comprising: Substrate and well region disposed within the substrate; A storage transistor is disposed on the well region and configured to store data; as well as A gating transistor, disposed horizontally on one side of the storage transistor in the well region, is configured to enable the storage transistor to perform a gating operation. The gating transistor and the storage transistor are connected in series. The source region of the storage transistor is connected to the first electrode of the flash memory cell, and the drain region of the gate transistor is connected to the second electrode of the flash memory cell. The erasure method includes: An erase operation is performed on the memory transistor by applying a second power supply voltage to the well region, applying a first erase voltage to the first electrode, applying a second erase voltage to the second electrode, applying a third erase voltage to the gate electrode of the memory transistor, and applying a fourth erase voltage to the gate electrode of the gate transistor. Wherein, the first erase voltage is higher than a preset voltage, the second erase voltage is equal to or higher than the second power supply voltage, the third erase voltage is equal to or lower than the second power supply voltage, and the fourth erase voltage is equal to or lower than the first power supply voltage. Wherein, the first power supply voltage is higher than the second power supply voltage. The preset voltage is predetermined based on the carrier barrier height at the interface between the substrate and the gate dielectric stack of the storage transistor, and Wherein, the first erase voltage and the fourth erase voltage are higher than the second erase voltage, so that both the storage transistor and the gating transistor are turned on.

2. A method for erasing a flash memory cell, the flash memory cell comprising: Substrate and well region disposed within the substrate; A first storage transistor is disposed on the well region and configured to store first data; A second storage transistor is disposed on the well region and configured to store second data; as well as A gating transistor, horizontally disposed on the well region between the first and second storage transistors, is configured to isolate the first and second storage transistors and perform a gating operation on them. The first storage transistor, the gating transistor, and the second storage transistor are connected in series. In this configuration, the source region of the first storage transistor is connected to the first electrode of the flash memory cell, and the drain region of the second storage transistor is connected to the second electrode of the flash memory cell. The erasure method includes: An erase operation is performed on the first or second storage transistor by applying a second power supply voltage to the well region, applying a first erase voltage to the first or second electrode, applying a second erase voltage to the second or first electrode, applying a third erase voltage to the gate electrode of the first or second storage transistor, applying a fourth erase voltage to the gate electrode of the gate transistor, and applying a fifth erase voltage to the gate electrode of the second or first storage transistor. Wherein, the first erase voltage is higher than a preset voltage, the second erase voltage is equal to or higher than the second power supply voltage, the third erase voltage is equal to or lower than the second power supply voltage, and the fourth erase voltage is equal to or lower than the first power supply voltage. Wherein, the first power supply voltage is higher than the second power supply voltage. The preset voltage is predetermined based on the carrier barrier height at the interface between the substrate and the gate dielectric stack of the first and second storage transistors. Wherein, the first erase voltage, the fourth erase voltage, and the fifth erase voltage are higher than the second erase voltage, so that the first storage transistor, the second storage transistor, and the gating transistor are all turned on.

3. The erasure method according to claim 1 or 2, wherein, The erasure method is based on the physical effect of channel hot electron-induced thermal hole injection.

4. The erasure method according to claim 1 or 2, wherein, The storage transistor is a charge-trapping storage transistor, and its gate dielectric stack includes a tunneling oxide layer, a charge storage layer, and a barrier oxide layer.

5. The erasure method according to claim 4, wherein, The thickness of the tunneling oxide layer is 1 to 6 nm.

6. The erasure method according to claim 4, wherein, The charge storage layer comprises a mono- or multi-component oxide, a mono- or multi-component nitride, a mono- or multi-component nitride, polycrystalline silicon or nanocrystalline material, or a combination of the above materials.

7. The erasure method according to claim 4, wherein, The charge storage layer comprises a high-K material rich in charge traps.

8. The erasure method according to claim 4, wherein, The tunneling oxide layer and the barrier oxide layer comprise silicon oxide or aluminum oxide.

9. The erasure method according to claim 1, wherein, The first power supply voltage is in the range of 0.8V to 5V. The second power supply voltage is ground voltage. The first erase voltage is in the range of 3V to 6V, and The third erase voltage is in the range of -8V to 0V.

10. The erasure method according to claim 2, wherein, The first power supply voltage is in the range of 0.8V to 5V. The second power supply voltage is ground voltage. The first erase voltage is in the range of 3V to 6V. The third erase voltage is in the range of -8V to 0V, and The fifth erase voltage is in the range of 3V to 8V.

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