Display driving circuit and display panel

Abstract

The present application is applicable to the technical field of display. Provided are a display driving circuit and a display panel. The display driving circuit comprises: a first light-emitting device and a second light-emitting device which are stacked; and a pixel driving circuit connected to the first light-emitting device and the second light-emitting device. The pixel driving circuit comprises: a driving circuit, the driving circuit being connected to anodes of the first light-emitting device and the second light-emitting device and being used for controlling voltages applied to the first light-emitting device and the second light-emitting device; a first switch circuit, which is arranged between the driving circuit and the anode of the first light-emitting device and is used for controlling the first light-emitting device to emit light; a second switch circuit, which is arranged between the driving circuit and the anode of the second light-emitting device and is used for controlling the second light-emitting device to emit light; and a dimming circuit, which is connected to control ends of the first switch circuit and the second switch circuit and is used for outputting a frequency modulation signal to control the first light-emitting device to emit light and the second light-emitting device to emit light. By means of the described circuit, the problem of uneven light-emitting efficiency is mitigated.

Description

Display driver circuit and display panel

[0001] Cross-referencing of related applications

[0002] This application claims priority to Chinese Patent Application No. 2024115587549, filed on November 4, 2024, the entire contents of which are incorporated herein by reference. [Technical Field]

[0003] This invention relates to the field of display panels, and in particular to display driving circuits and display panels. [Background Technology]

[0004] Tandem OLED, or stacked evaporation display technology, is a device structure that connects multiple light-emitting units in series through a charge generation layer. Tandem OLED is a novel display technology. Its principle is to use a transparent connecting layer to connect several light-emitting devices in series. Specifically, an OLED pixel consists of an anode, a cathode, and multiple layers of organic material sandwiched in between. When current flows, the anode emits holes, and the cathode emits electrons. These holes and electrons meet and recombine in the organic layers, producing light. In a tandem OLED, this structure is replicated twice, forming two light-emitting layers connected by a charge generation layer (CGL). When current flows, some holes and electrons recombine in the first light-emitting layer to emit light, while the remaining holes and electrons pass through the CGL and recombine again in the second light-emitting layer to emit light.

[0005] Compared to traditional single-layer OLEDs, Tandem OLEDs offer several advantages. First, they achieve more than double the brightness. Second, Tandem OLEDs consume less energy; compared to single-layer OLEDs, they are more efficient and consume less energy when displaying the same brightness. Third, their device lifespan is more than four times longer, effectively mitigating the common "burn-in" problem in OLED screens. Fourth, while achieving high brightness, Tandem OLEDs can reduce the number of optical components and simplify circuitry, resulting in reduced weight and thickness.

[0006] Nevertheless, Tandem OLEDs still face numerous unresolved issues in practical research and application. Firstly, for a Tandem OLED to display a correct image, the two stacked OLED layers must have identical display effects. However, even OLED screens from the same production line with identical parameters and processes will exhibit differences in display effects between different batches, making it difficult to achieve a high yield rate for Tandem OLED screens. Secondly, due to the parallel topology of the two layers in a Tandem OLED, the voltage across the layer closest to the cathode is significantly affected by the voltage drop across the previous layer. Because of the differences in the two deposition processes, differences in display effects between the two layers are almost inevitable. [Summary of the Invention]

[0007] The main technical problem addressed by this application is to provide a display driving circuit and a display panel to improve the uneven luminous efficiency of multilayer OLEDs.

[0008] To address the aforementioned problems, the first technical solution adopted in this application is to provide a display driving circuit, wherein the display driving circuit includes: a first light-emitting device and a second light-emitting device stacked together; a pixel driving circuit connected to the first light-emitting device and the second light-emitting device; the pixel driving circuit includes: a driving circuit connected to the anodes of the first light-emitting device and the second light-emitting device, used to control the voltage applied to the first light-emitting device and the second light-emitting device; a first switching circuit disposed between the driving circuit and the anode of the first light-emitting device, used to control the first light-emitting device to emit light; a second switching circuit disposed between the driving circuit and the anode of the second light-emitting device, used to control the second light-emitting device to emit light; and a dimming circuit connected to the control terminals of the first switching circuit and the second switching circuit, used to output a frequency modulation signal to control the first light-emitting device and the second light-emitting device to emit light.

[0009] The first switching circuit includes a first switching transistor, and the second switching circuit includes a second switching transistor. The first switching transistor and the second switching transistor are a pair of transistors with opposite driving characteristics.

[0010] The driving circuit includes: a driving transistor, the gate of which is connected to a first signal line, the first electrode of which is connected to a power supply line, and the second electrode of which is connected to the anodes of the first and second light-emitting devices; a storage capacitor, the first plate of which is connected to the gate of the driving transistor, and the second plate of which is connected to the power supply line, for maintaining the gate voltage of the driving transistor; a third switching transistor, disposed between the first electrode of the driving transistor and a data line; the first electrode of the third switching transistor is connected to the data line, and the second electrode of the third switching transistor is connected to the first electrode of the driving transistor; a fourth switching transistor, disposed between the second electrode of the driving transistor and the gate of the driving transistor; the first electrode of the fourth switching transistor is connected to the second electrode of the driving transistor, and the second electrode of the fourth switching transistor is connected to the gate of the driving transistor and the first plate of the storage capacitor; and a fifth switching transistor, disposed between the power supply line and the first electrode of the driving transistor; the first electrode of the fifth switching transistor is connected to the power supply line, and the second electrode of the fifth switching transistor is connected to the first electrode of the driving transistor.

[0011] The driving circuit further includes: a first reset transistor disposed between the first signal line and the gate of the driving transistor, wherein the first electrode of the first reset transistor is connected to the first signal line, and the second electrode of the first reset transistor is connected to the gate of the driving transistor, for controlling the driving transistor.

[0012] The driving circuit further includes a second reset transistor, wherein the first electrode of the second reset transistor is connected to a second signal line, and the second electrode of the second reset transistor is connected to the anodes of the first light-emitting device and the second light-emitting device, for resetting the anodes of the first light-emitting device and the second light-emitting device.

[0013] The gates of the third switching transistor and the fifth switching transistor are connected to the same signal line, and the third switching transistor and the fifth switching transistor are a pair of transistors with opposite driving characteristics.

[0014] The dimming circuit includes: a low-potential driving transistor, the gate of which is connected to a control circuit, a first electrode connected to a low-potential signal line, and a second electrode connected to the gates of the first and second switching transistors; and a high-potential driving transistor, the gate of which is connected to a control circuit, a first electrode connected to a high-potential signal line, and a second electrode connected to the gates of the first and second switching transistors.

[0015] The low-potential driving transistor and the high-potential driving transistor are a pair of transistors with opposite driving characteristics.

[0016] The control circuit includes a low-potential control circuit, a high-potential control circuit, and a bootstrap capacitor. The first plate of the bootstrap capacitor is connected to the low-potential control circuit and the gate of the high-potential driving transistor, and the second plate is connected to the high-potential control circuit and the gate of the low-potential driving transistor. The low-potential control circuit provides a low-potential driving signal to the gate of the low-potential driving transistor through the bootstrap capacitor to control the low-potential driving transistor to conduct. The high-potential control circuit provides a high-potential driving signal to the gate of the high-potential driving transistor through the bootstrap capacitor to control the high-potential driving transistor to conduct.

[0017] The low-potential control circuit includes a first transistor, the gate of which is connected to a first control signal line, the first electrode of which is connected to a low-potential signal line, and the second electrode of which is connected to the first plate of the bootstrap capacitor; the high-potential control circuit includes a second transistor, the gate of which is connected to a second control signal line, the first electrode of which is connected to a high-potential signal line, and the second electrode of which is connected to the second plate of the bootstrap capacitor.

[0018] Wherein, the first control signal line and the second control signal line are a set of clock signals with opposite phases; the first transistor and the second transistor are a set of transistors with opposite driving characteristics.

[0019] The control circuit further includes: a sixth switching transistor, the gate of which is connected to the first control signal line, the first electrode of which is connected to the second plate of the bootstrap capacitor, and the second electrode of which is connected to the gate of the low-potential driving transistor. It is simultaneously turned on with the first transistor and is used to control the transmission of the low-potential driving signal output by the low-potential control circuit to the gate of the low-potential driving transistor, thereby controlling the conduction of the low-potential driving transistor; and a seventh switching transistor, the gate of which is connected to the second control signal line, the first electrode of which is connected to the first plate of the bootstrap capacitor, and the second electrode of which is connected to the gate of the high-potential driving transistor. The seventh switching transistor and the second transistor are simultaneously turned on and are used to control the transmission of the high-potential driving signal output by the high-potential control circuit to the gate of the high-potential driving transistor, thereby controlling the conduction of the high-potential driving transistor.

[0020] The control circuit includes a cascaded signal and a pre-charge transistor. The gate of the pre-charge transistor is connected to the second control signal line, the first electrode is connected to the cascaded signal, and the second electrode is connected to the first plate of the bootstrap capacitor, for charging the bootstrap capacitor during the pre-charge phase.

[0021] The control circuit further includes a precharge-hold transistor; the gate of the precharge-hold transistor is connected to the cascaded signal, the first electrode of the precharge-hold transistor is grounded, and the second electrode of the precharge-hold transistor is connected to the second plate of the bootstrap capacitor, for enabling the bootstrap capacitor to have a storage function during the precharge phase.

[0022] Both the precharge transistor and the precharge hold transistor are P-type transistors.

[0023] The control circuit further includes: a first isolation transistor disposed between the second transistor and the second plate of the bootstrap capacitor, used to isolate the cascaded signal from the high-potential signal line during the pre-charge phase, thereby pre-charging the bootstrap capacitor; and a second isolation transistor disposed between the seventh switching transistor and the gate of the high-potential driving transistor, used to isolate the cascaded signal from the high-potential driving transistor during the pre-charge phase, thereby preventing the high-potential driving transistor from turning on prematurely.

[0024] The first isolation transistor and the second isolation transistor are N-type transistors.

[0025] The control circuit further includes: a second capacitor, the first plate of which is connected to the gate of the first isolation transistor, and the second plate of which is grounded, for controlling the on / off state of the first isolation transistor; a third capacitor, the first plate of which is connected to the gate of the second isolation transistor, and the second plate of which is grounded, for controlling the on / off state of the second isolation transistor; a first diode, the forward terminal of which is connected to the cascaded signal, and the reverse terminal of which is connected to the first electrode of the precharge transistor; a second diode, the forward terminal of which is connected to the first plate of the second capacitor and the gate of the first isolation transistor, and the reverse terminal of which is connected to the second electrode of the first transistor; and a third diode, the forward terminal of which is connected to the first plate of the third capacitor and the gate of the second isolation transistor, and the reverse terminal of which is connected to the second electrode of the first transistor.

[0026] The control circuit includes a reset signal line connected to the bootstrap capacitor, the second capacitor, and the third capacitor. The reset signal line is connected to the first plate of the bootstrap capacitor, the first plate of the second capacitor, and the first plate of the third capacitor, respectively, for resetting the bootstrap capacitor, the second capacitor, and the third capacitor.

[0027] To solve the above problems, the second technical solution adopted in this application is to provide a display panel, wherein the display panel includes the display driving circuit described in any embodiment of the first technical solution above.

[0028] The beneficial effects of this application are: based on the luminous efficiency of the two stacked OLEDs, the duty cycle of the frequency modulation signal output to the first and second switching circuits is adjusted by the dimming circuit, thereby changing the luminous frequency of the two stacked OLEDs, improving the problem of uneven luminous efficiency of the two OLED light-emitting devices in the stack, and thus effectively adjusting the panel display effect. [Attached Image Description]

[0029] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 is a schematic diagram of an OLED stacking structure provided in this application;

[0031] Figure 2 is a schematic diagram of a display driving circuit according to an embodiment of the present application;

[0032] Figure 3 is a schematic diagram of a specific embodiment of the driving circuit of this application;

[0033] Figure 4 is a timing signal diagram of an embodiment of the driving circuit of this application;

[0034] Figure 5 is a schematic diagram of the equivalent circuit structure of the driving circuit in the reset phase of this application;

[0035] Figure 6 is a schematic diagram of the equivalent circuit structure of the driving circuit in the sampling stage of this application;

[0036] Figure 7 is a schematic diagram of the equivalent circuit structure of the driving circuit in the light-emitting stage of this application;

[0037] Figure 8 is a schematic diagram of the structure of the first embodiment of the dimming circuit of this application;

[0038] Figure 9 is a schematic diagram of the specific structure of the second embodiment of the dimming circuit of this application;

[0039] Figure 10 is a timing signal diagram of a second specific embodiment of the dimming circuit of this application;

[0040] Figure 11 is a schematic diagram of the equivalent circuit structure of the dimming circuit in the pre-charge stage of this application;

[0041] Figure 12 is a schematic diagram of the equivalent circuit structure of the dimming circuit in the first driving stage of this application;

[0042] Figure 13 is a schematic diagram of the equivalent circuit structure of the dimming circuit in the second driving stage of this application;

[0043] Figure 14 is a schematic diagram of the equivalent circuit structure of the dimming circuit in the blank stage of this application;

[0044] Figure 15 is a schematic diagram of the structure of an embodiment of the display panel of this application.

[0045] In the diagram: First light-emitting device OLED1; Second light-emitting device OLED2; Driving circuit 11; Dimming circuit 12; First switching transistor T1; Second switching transistor T2; Driving transistor DT1; First reset transistor T3; Storage capacitor Cst; Third switching transistor T4; Fourth switching transistor T5; Fifth switching transistor T6; Second reset transistor T7; Power supply line VDD; First signal line Vint; Second signal line Vint-Anode; First control line PSCAN(N); Second control line PSCAN(N-1); Data line data; Frequency modulation signal EN(N); Low-level driving transistor DT11; High-level driving transistor... Transistor DT12; Control circuit 120; Low-level signal line VGL; High-level signal line VGH; Low-level control circuit 121; High-level control circuit 122; Bootstrap capacitor C1; First transistor T11; Second transistor T12; Sixth switching transistor T13; Seventh switching transistor T14; First control signal line XCK; Second control signal line CK; Precharge transistor T15; Precharge hold transistor T10; Cascade signal EN(N-1); First isolation transistor T16; Second isolation transistor T17; Reset signal line CLR; Second capacitor C2; Third capacitor C3; First diode D1; Second diode D2; Third diode D3.

Detailed Implementation Methods

[0046] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0047] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to limit the application. The singular forms “a,” “said,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms, unless otherwise clearly indicated above. “Multiple” generally includes at least two, but does not exclude the inclusion of at least one.

[0048] It should be understood that the term "and / or" used herein is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Furthermore, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship. The terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0049] It should be understood that the terms "comprising," "including," or any other variations used herein are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0050] It should be noted that if the embodiments of this application involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicators will also change accordingly.

[0051] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in every place in the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0052] This application provides a display driving circuit, which includes: a first light-emitting device and a second light-emitting device stacked together.

[0053] Specifically, please refer to Figure 1, which is a schematic diagram of an OLED stacked structure provided in this application. As shown in Figure 1, it includes a first light-emitting device OLED1 and a second light-emitting device OLED2, which are stacked together. While maintaining the same light emission direction, the driving of the light-emitting layers is implemented in parallel in the circuit structure. The OLED stacked structure includes a hole injection layer (HIL), a hole transport layer (HTL), a light-emitting layer (EM), an electron transport layer (ETL), and an electron injection layer (EIL). As shown in Figure 1(a), the first light-emitting device OLED1 and the second light-emitting device OLED2 share a common cathode layer. As shown in Figure 1(b), the cathode layer can be replaced by a transparent thin-film metal to form a charge generation layer (CGL), which serves to connect the light-emitting layers. The OLED stacked structure is connected to the display driving circuit through vias in areas such as the PDL (pixel definition layer). It should be noted that the functional layers shown in Figure 1, such as the EM-R / G / B (red / green / blue emitting layers), may also contain both host and guest emitting materials. For the purpose of adjusting the transmission rate, the electron / hole transport layer may also include a blocking layer. The example shown in Figure 1 is for illustrative purposes only and should not be considered the sole reference for practical applications.

[0054] The display driving circuit is located at the anode end of the OLED stacked structure and is used to control the light emission of the first light-emitting device and the second light-emitting device.

[0055] Please refer to Figure 2 for details. Figure 2 is a schematic diagram of an embodiment of the display driving circuit provided in this application. As shown in Figure 2, the display driving circuit includes: a first light-emitting device OLED1 and a second light-emitting device OLED2, and a pixel driving circuit connected to the anode of the first light-emitting device OLED1 and the second light-emitting device OLED2. The first light-emitting device OLED1 and the second light-emitting device OLED2 are stacked, and the specific structure can be as shown in Figure 1.

[0056] The pixel driving circuit includes: a driving circuit 11, a first switching circuit and a second switching circuit, and a dimming circuit 12.

[0057] The driving circuit 11 is connected to the anode of the first light-emitting device OLED1 and the second light-emitting device OLED2, and is used to control the driving voltage applied to the first light-emitting device OLED1 and the second light-emitting device OLED2.

[0058] The first switching circuit is disposed between the driving circuit 11 and the anode of the first light-emitting device OLED1, and is used to control the first light-emitting device OLED1 to emit light. When the first switching circuit is turned on, the first light-emitting device OLED1 emits light; when the first switching circuit is turned off, the first light-emitting device OLED1 does not emit light.

[0059] The second switching circuit is located between the driving circuit 11 and the anode of the second light-emitting device OLED2, and is used to control the light emission of the second light-emitting device OLED2. The on / off state of the second switching circuit controls whether the second light-emitting device OLED2 emits light.

[0060] The dimming circuit 12 is connected to the control terminals of the first switching circuit and the second switching circuit, and is used to output a frequency modulation signal to control the duty cycle of the first light-emitting device OLED1 and the second light-emitting device OLED2.

[0061] In this embodiment, the first switching circuit and the second switching circuit are not turned on at the same time, so that the first light-emitting device OLED1 and the second light-emitting device OLED2 emit light respectively, thereby ensuring that the anode voltage applied to the first light-emitting device OLED1 and the second light-emitting device OLED2 is the same.

[0062] Specifically, the first switching circuit includes a first switching transistor T1, and the second switching circuit includes a second switching transistor T2. The first switching transistor T1 and the second switching transistor T2 are a pair of transistors with opposite driving characteristics. When the first switching transistor T1 is turned on, the second switching transistor T2 is turned off; when the first switching transistor T1 is turned off, the second switching transistor T2 is turned on. The frequency modulation signal includes a low-level signal and a high-level signal.

[0063] In one specific embodiment, please further refer to FIG3, which is a schematic diagram of the structure of a specific embodiment of the driving circuit of this application. As shown in FIG3, the driving circuit 11 includes a driving transistor DT1, a first reset transistor T3, a storage capacitor Cst, a third switching transistor T4, a fourth switching transistor T5, and a fifth switching transistor T6.

[0064] The gate of driving transistor DT1 is connected to the first signal line Vint, the first electrode of driving transistor DT1 is connected to the power supply line VDD, and the second electrode of driving transistor DT1 is connected to the anode of the first light-emitting device OLED1 and the second light-emitting device OLED2. The voltage flowing through the anode of the first light-emitting device OLED1 and the second light-emitting device OLED2 is controlled by controlling the gate voltage of driving transistor DT1. One of the first electrode and the other of the second electrode is the source and the other is the drain.

[0065] The first reset transistor T3 is disposed between the first signal line Vint and the gate of the driving transistor DT1. The first electrode of the first reset transistor T3 is connected to the first signal line Vint, and the second electrode is connected to the gate of the driving transistor DT1, and is used to control the driving transistor DT1. Specifically, it is used to control the start voltage or reset voltage of the driving transistor DT1.

[0066] The first plate of the storage capacitor Cst is connected to the gate of the driving transistor DT1, and the second plate of the storage capacitor Cst is connected to the power supply line VDD to maintain the voltage on the gate of the driving transistor DT1.

[0067] The third switching transistor T4 is positioned between the first electrode of the driving transistor DT1 and the data line data. The first electrode of the third switching transistor T4 is connected to the data line data, and the second electrode is connected to the first electrode of the driving transistor DT1. The third switching transistor T4 is used to charge voltage to the gate of the driving transistor DT1 through the driving transistor DT1 during the sampling phase.

[0068] The fourth switching transistor T5 is disposed between the second electrode of the driving transistor DT1 and the gate of the driving transistor DT1. The first electrode of the fourth switching transistor T5 is connected to the second electrode of the driving transistor DT1, and the second electrode is connected to the gate of the driving transistor DT1 and the first plate of the storage capacitor Cst. This connection is used to connect the gate and drain of the driving transistor DT1 during the sampling phase to charge the gate of the second driving transistor DT1.

[0069] The fifth switching transistor T6 is positioned between the power supply line VDD and the first electrode of the driving transistor DT1. The first electrode of the fifth switching transistor T6 is connected to the power supply line VDD, and its second electrode is connected to the first electrode of the driving transistor DT1 and the second electrode of the third switching transistor T4. It is used to control the connection between the power supply line VDD and the driving transistor DT1.

[0070] The driving circuit 11 also includes a second reset transistor T7. The first electrode of the second reset transistor T7 is connected to the second signal line Vint-Anode, and the second electrode is connected to the anode of the first light-emitting device OLED1 and the second light-emitting device OLED2. This resets the anodes of the first light-emitting device OLED1 and the second light-emitting device OLED2, preventing them from turning on prematurely. Specifically, the second electrode of the second reset transistor T7 is connected to the first electrode of the first switching transistor T1 and the second switching transistor T2. In other embodiments, the second reset transistor T7 may be omitted; this is not a limitation here.

[0071] The gates of the third switching transistor T4 and the fifth switching transistor T6 can be connected to the same signal line. The third switching transistor T4 and the fifth switching transistor T6 are a pair of transistors with opposite driving characteristics; one is an N-type transistor, and the other is a P-type transistor.

[0072] It should be noted that, in this application, the first electrode and the second electrode of each transistor refer to the source and drain terminals of the transistor, respectively, and no specific limitation is made as to which terminal it is.

[0073] In this embodiment, the driving circuit includes a reset stage, a sampling stage, and a light emission stage. See Figure 4 for details; Figure 4 is a timing signal diagram of an embodiment of the driving circuit of this application.

[0074] Specifically, the gates of the first reset transistor T3 and the second reset transistor T7 are connected to the same signal line. The gates of the third switching transistor T4 and the fifth switching transistor T6 are connected to the first control line PSCAN(N), and the gates of the first reset transistor T3 and the second reset transistor T7 are connected to the second control line PSCAN(N-1).

[0075] During the reset phase, the second control line PSCAN(N-1) controls the first reset transistor T3 and the second reset transistor T7 to conduct, thereby resetting the gate of the driving transistor DT1 and the anodes of the first light-emitting device OLED1 and the second light-emitting device OLED2. See Figure 5 for details; Figure 5 is a schematic diagram of the equivalent circuit structure of the driving circuit in the reset phase of this application. As shown in Figure 5, during the reset phase, the first reset transistor T3 and the second reset transistor T7 are turned on, and the second signal line Vint-Anode resets the anode, ensuring that the anode potential of the light-emitting device is in the initial stage, while preventing the first switching transistor T1 and the second switching transistor T2 from turning on prematurely. The first signal line Vint charges the gate of the driving transistor DT1, refreshing the data potential stored in the previous frame, and simultaneously charging the storage capacitor Cst, ensuring that the driving transistor DT1 is turned on during the sampling phase. In this embodiment, the fifth switching transistor T6 can also be turned on. Preferably, the fifth switching transistor T6 is not turned on.

[0076] During the sampling phase, the first control line PSCAN(N) controls the third switching transistor T4 and the fourth switching transistor T5 to conduct simultaneously, and the driving transistor DT1 is also turned on to charge the gate of the driving transistor DT1. Please refer to Figure 6 for details; Figure 6 is a schematic diagram of the equivalent circuit structure of the driving circuit in the sampling phase of this application. The third switching transistor T4, the driving transistor DT1, and the fourth switching transistor T5 form a sampling loop. The data line data enters Cst through the third switching transistor T4, the fourth switching transistor T5, and the driving transistor DT1. At this time, the voltage at the end of the storage capacitor Cst connected to the gate of the driving transistor DT1 is Vdata + Vth, which means the sampling voltage of the first plate of the storage capacitor Cst is Vdata + Vth.

[0077] During the light-emitting stage, the first control line PSCAN(N) controls the fifth switching transistor T6 to conduct. See Figure 7 for details; Figure 7 is a schematic diagram of the equivalent circuit structure of the driving circuit in the light-emitting stage of this application. During the light-emitting stage, the first switching transistor T1 and the second switching transistor T2 are alternately turned on under the action of the frequency modulation signal EN(N). The driving transistor DT1 generates a data current under the action of the storage capacitor Cst and the power supply voltage VDD, driving the OLED to emit light. The frequency modulation signal EN(N) is a transition signal including both high-level and low-level signals.

[0078] In this embodiment, the effect of threshold voltage Vth drift is eliminated by charging the gate of the driving transistor DT1 with a threshold voltage Vth during the sampling phase.

[0079] It should be noted that in other embodiments, the gate of the driving transistor DT1 can be pre-charged using other circuit structures or data signal lines. In other embodiments, the second reset transistor T7 can be omitted to reset the anode of the OLED light-emitting device.

[0080] In one embodiment, the dimming circuit 12 may consist of two control signal lines with opposite phases.

[0081] In a further embodiment, the dimming circuit 12 includes a low-level driving transistor DT11 and a high-level driving transistor DT12. The low-level driving transistor DT11 is used to output a low-level signal to the first switching transistor T1 and the second switching transistor T2, and the high-level driving transistor DT12 is used to output a high-level signal to the first switching transistor T1 and the second switching transistor T2.

[0082] Please refer to Figure 8 for details. Figure 8 is a schematic diagram of the structure of the first embodiment of the dimming circuit of this application. As shown in Figure 8, the gate of the low-potential driving transistor DT11 is connected to the control circuit 120, the first electrode is connected to the low-potential signal line VGL, and the second electrode is connected to the gate of the first switching transistor T1 and the second switching transistor T2, outputting a frequency modulation signal EN(N). The gate of the high-potential driving transistor DT12 is connected to the control circuit 120, the first electrode is connected to the high-potential signal line VGH, and the second electrode is connected to the gate of the first switching transistor T1 and the second switching transistor T2.

[0083] In this embodiment, the low-potential signal line VGL and the high-potential signal line VGH transmit a set of clock signals with opposite phases.

[0084] Furthermore, the control circuit 120 includes a low-potential control circuit 121, a high-potential control circuit 122, and a bootstrap capacitor C1. The first plate of the bootstrap capacitor C1 is connected to the gate of the low-potential control circuit 121 and the high-potential driving transistor DT12, and the second plate is connected to the gate of the high-potential control circuit 122 and the low-potential driving transistor DT11. The low-potential control circuit 121 transmits a low-potential driving signal to the second plate of the bootstrap capacitor C1, thereby providing a low-potential driving signal to the gate of the low-potential driving transistor DT11, causing DT11 to conduct and output a low-level frequency-modulated signal to the gates of the first switching transistor T1 and the second switching transistor T2. The high-potential control circuit also provides a high-potential driving signal to the gate of the high-potential driving transistor DT12 through the bootstrap effect of the bootstrap capacitor C1, controlling DT12 to conduct and output a high-level frequency-modulated signal to the gates of the first switching transistor T1 and the second switching transistor T2.

[0085] In this embodiment, the low-potential control circuit 121 and the high-potential control circuit 122 transmit clock signals with opposite phases to the high-potential driving transistor DT12 and the low-potential driving transistor DT11, so as to control the high-potential driving transistor DT12 and the low-potential driving transistor DT11 to be turned on respectively, forming a frequency modulation signal EN(N) that can be switched. In other embodiments, the control circuit 120 may be directly composed of a set of clock signals with opposite phases, which is not limited here.

[0086] In one specific embodiment, the low-level control circuit 121 includes a first transistor T11, the gate of which is connected to a first control signal line XCK, the first electrode of which is connected to a low-level signal line VGL, and the second electrode of which is connected to the first plate of the bootstrap capacitor C1. The high-level control circuit 122 includes a second transistor T12, the gate of which is connected to a second control signal line CK, the first electrode of which is connected to a high-level signal line VGH, and the second electrode of which is connected to the second plate of the bootstrap capacitor C1. The first control signal line XCK and the second control signal line CK are a set of clock signals with opposite phases. In other embodiments, the first transistor T11 and the second transistor T12 may also be a set of transistors with opposite driving characteristics, one being an N-type transistor and the other a P-type transistor, with the first control signal line XCK and the second control signal line CK having the same phase.

[0087] In this specific embodiment, when the low-potential control circuit 121 is working, the high-potential control circuit 122 is not working; when the high-potential control circuit 122 is working, the low-potential control circuit 121 is not working.

[0088] It should be noted that the operating cycle of the dimming circuit 12 includes a first driving stage P2 and a second driving stage P3. In the first driving stage P2, the low-potential control circuit 121 controls the low-potential driving transistor DT11 to turn on; in the second driving stage P3, the high-potential control circuit 122 controls the high-potential driving transistor DT12 to turn on, thereby outputting a jumping frequency modulation signal EN(N).

[0089] In a further embodiment, the control circuit 120 also includes a sixth switching transistor T13 and a seventh switching transistor T14.

[0090] The gate of the sixth switching transistor T13 is connected to the first control signal line XCK, its first electrode is connected to the second plate of the bootstrap capacitor C1, and its second electrode is connected to the gate of the low-potential drive transistor DT11. The sixth switching transistor T13 and the first transistor T11 are simultaneously turned on. The sixth switching transistor T13 controls whether the low-potential drive signal output by the low-potential control circuit 121 can be transmitted to the gate of the low-potential drive transistor DT11, thereby controlling the conduction of the low-potential drive transistor DT11.

[0091] The gate of the seventh switching transistor T14 is connected to the second control signal line CK, the first electrode is connected to the first plate of the bootstrap capacitor C1, and the second electrode is connected to the gate of the high-potential driving transistor DT12. The seventh switching transistor T14 and the second transistor T12 are simultaneously turned on, controlling the transmission of the high-potential driving signal output by the high-potential control circuit 122 to the gate of the high-potential driving transistor DT12, thereby controlling the conduction of the high-potential driving transistor DT12.

[0092] Simultaneously, during the first driving phase P2, when the sixth switching transistor T13 is turned on, the seventh switching transistor T14 is turned off, thus preventing the seventh switching transistor T14 from turning on and consequently affecting the voltage division across the bootstrap capacitor C1. During the second driving phase P3, when the seventh switching transistor T14 is turned on, the sixth switching transistor T13 is turned off, thus preventing the sixth switching transistor T13 from turning on and consequently affecting the voltage division across the bootstrap capacitor C1.

[0093] It should be noted that in other embodiments, the sixth switching transistor T13 and the seventh switching transistor T14 may not be provided. This is because the high-potential driving transistor DT12 is a high-potential turn-on transistor, and even if the low-potential voltage on the first transistor T11 is transferred to the high-potential driving transistor DT12, it will not turn on, but other effects (such as voltage division) will occur. Similarly, the low-potential driving transistor DT11 is a low-potential turn-on transistor, and even if the high-potential voltage on the second transistor T12 is transferred to the low-potential driving transistor DT11, it will not turn on.

[0094] In the above embodiment, the low-potential driving transistor DT11 and the high-potential driving transistor DT12 are a pair of transistors with opposite driving characteristics. Specifically, the low-potential driving transistor DT11 is a low-potential turn-on transistor, and the high-potential driving transistor DT12 is a high-potential turn-on transistor.

[0095] In other embodiments, the low-potential driving transistor DT11 and the high-potential driving transistor DT12 can also be transistors with the same driving characteristics. The first electrodes of the first transistor T11 and the second transistor T12 are connected to the same potential signal (such as both being high-potential signals VGH or both being low-potential signals VGL). In this case, the connection between the first transistor T11 and the high-potential driving transistor DT12 can be disconnected by the sixth switch transistor T13, and the connection between the second transistor T12 and the low-potential driving transistor DT11 can be disconnected by the seventh switch transistor T14, thereby controlling the low-potential driving transistor DT11 to turn on or controlling the high-potential driving transistor DT12 to turn on respectively.

[0096] It should be noted that, through the coupling effect of the bootstrap capacitor C1, when the voltage on its first plate decreases, the voltage on its second plate also decreases, thereby lowering the gate voltage of the low-potential drive transistor DT11 and turning it on. When the voltage on its second plate increases, the voltage on its first plate also increases, thereby raising the gate voltage of the high-potential drive transistor DT12 and turning it on.

[0097] In a further embodiment, please refer to FIG9, which is a schematic diagram of the specific structure of the second embodiment of the dimming circuit of this application. As shown in FIG9, the control circuit 120 further includes a cascaded signal EN(N-1) and a pre-charge transistor T15 based on FIG8. This is used to charge the bootstrap capacitor C1 with a starting voltage, thereby enabling the bootstrap capacitor C1 to have a bootstrap function, and thus controlling the conduction of the high-potential drive transistor DT12 and the low-potential drive transistor DT11 during the driving phase, and ensuring that this conduction has a certain stability. Specifically, the gate of the pre-charge transistor T15 is connected to the second control signal line CK, the first electrode is connected to the cascaded signal EN(N-1), and the second electrode is connected to the first plate of the bootstrap capacitor C1, used to charge the bootstrap capacitor C1 with P1 during the pre-charge phase, so that the first plate of the bootstrap capacitor C1 carries a positive charge. The cascaded signal EN(N-1) is the frequency modulation signal of the previous stage. In one specific embodiment, the dimming circuit 12 is a cascaded GOA circuit, and the frequency modulation signal output by the dimming circuit 12 is also connected to the input terminal of the precharge transistor T15 of the next stage.

[0098] To ensure successful charging of the bootstrap capacitor C1 by the precharge transistor T15 and prevent charging failure due to the lower plate of the bootstrap capacitor C1 being in a floating state, the control circuit 120 further includes a precharge hold transistor T10. The gate of the precharge hold transistor T10 is connected to the cascaded signal EN(N-1), the first electrode is grounded, and the second electrode is connected to the second plate of the bootstrap capacitor C1. This transistor is used to activate the bootstrap capacitor C1 during the precharge phase P1, thereby charging the first plate of the bootstrap capacitor C1 and enabling it to store the initial potential.

[0099] Furthermore, the control circuit 120 also includes a first isolation transistor T16 and a second isolation transistor T17. The first isolation transistor T16 is disposed between the second transistor T12 and the second plate of the bootstrap capacitor C1, and is used to isolate the cascaded signal EN(N-1) from the high-potential signal line VGH during the pre-charging stage, thereby enabling the pre-charging of the bootstrap capacitor C1 and preventing the cascaded signal EN(N-1) from being directly connected to the high-potential signal line VGH, which would affect the pre-charging of the bootstrap capacitor C1.

[0100] The second isolation transistor T17 is disposed between the gate of the seventh switching transistor T14 and the high-potential driving transistor DT12. It is used to isolate the cascaded signal EN(N-1) from the high-potential driving transistor DT12 during the pre-charge phase, so as to prevent the cascaded signal EN(N-1) from being transmitted to the high-potential driving transistor DT12, which would cause the high-potential driving transistor DT12 to turn on prematurely.

[0101] The control circuit 120 also includes a second capacitor C2, a third capacitor C3, a first diode D1, a second diode D2, and a third diode D3.

[0102] The first plate of the second capacitor C2 is connected to the gate of the first isolation transistor T16, and the second plate is grounded, used to control the on / off state of the first isolation transistor T16. In other embodiments, the on / off state of the first isolation transistor T16 can also be controlled by a low-potential signal line.

[0103] The first plate of the third capacitor C3 is connected to the gate of the second isolation transistor T17, and the second plate is grounded, used to control the on / off state of the second isolation transistor T17. In other embodiments, the on / off state of the second isolation transistor T17 can also be controlled by a low-potential signal line.

[0104] The forward terminal of the first diode D1 is connected to the cascaded signal EN(N-1), and the reverse terminal is connected to the first electrode of the precharge transistor T15 and the gate of the precharge holding transistor T10, so that P1 can maintain the precharge voltage through the precharge transistor T15 to charge the bootstrap capacitor C1 during the precharge phase.

[0105] The forward terminal of the second diode D2 is connected to the first plate of the second capacitor C2 and the gate of the first isolation transistor T16, and the reverse terminal is connected to the second electrode of the first transistor T11. It is used to release the high potential voltage on the second capacitor C2 in the first driving stage P2, so that the voltage on the second capacitor C2 is a low potential voltage, thereby controlling the first isolation transistor T16 to be in the conducting state after the first driving stage P2.

[0106] The forward terminal of the third diode D3 is connected to the first plate of the third capacitor C3 and the gate of the second isolation transistor T17, and the reverse terminal is connected to the second electrode of the first transistor T11. This is used to release the high potential voltage on the third capacitor C3 during the first driving phase P2, thereby reducing the voltage on the third capacitor C3 to a low potential voltage, and thus controlling the second isolation transistor T17 to be in a conducting state after the first driving phase P2.

[0107] Furthermore, the control circuit 120 also includes a reset signal line CLR connected to the bootstrap capacitor C1, the second capacitor C2, and the third capacitor C3. The reset signal line CLR is connected to the first plate of the bootstrap capacitor C1, the first plate of the second capacitor C2, and the first plate of the third capacitor C3, respectively, and is used to reset the bootstrap capacitor C1, the second capacitor C2, and the third capacitor C3. Specifically, the reset signal line CLR is at a high potential. Before the pre-charge phase P1, the second capacitor C2 and the third capacitor C3 are charged to a high potential and maintained, thereby keeping the first isolation transistor T16 and the second isolation transistor T17 in the off state during the pre-charge phase P1, thus avoiding signal crosstalk.

[0108] In other embodiments, the first isolation transistor T16 and the second isolation transistor T17 can also be turned on / off by other low-potential signal lines, thereby enabling P1 to play an isolation role during the pre-charge phase.

[0109] In this embodiment, the dimming circuit 12 also includes a Blanking stage. During the Blanking stage, the bootstrap capacitor C1, the second capacitor C2, and the third capacitor C3 are reset, mainly resetting the potential of C1 to prepare for the next frame. At the same time, the second capacitor C2 and the third capacitor C3 are reset, so that the first isolation transistor T16 and the second isolation transistor T17 are not working.

[0110] Please refer further to Figure 10, which is a timing signal diagram of a second specific embodiment of the dimming circuit of this application. As shown in Figure 10, the driving of the dimming circuit includes a pre-charge stage P1, an alternating first driving stage P2, and a second driving stage P3. In this embodiment, the low-potential driving transistor DT11, the first isolation transistor T16, and the second isolation transistor T17 are N-type transistors (low-potential turn-on transistors), and the rest are P-type transistors (high-potential turn-on transistors).

[0111] During the pre-charge phase P1, the second control signal line CK controls the pre-charge transistor T15 to turn on. The cascaded signal EN(N-1) charges the first plate of the bootstrap capacitor C1 through the pre-charge transistor T15. The cascaded signal EN(N-1) also controls the pre-charge holding transistor T10 to turn on, enabling the bootstrap capacitor C1 to have storage capacity, thus allowing the first plate of the bootstrap capacitor C1 to store the initial charge. See Figure 11 for details; Figure 11 is a schematic diagram of the equivalent circuit structure of the dimming circuit in the pre-charge phase of this application. The first diode D1 ensures forward charging, preventing power loss on the bootstrap capacitor C1.

[0112] In the first driving stage P2, the first control signal line XCK outputs a high level, controlling the first transistor T11 to turn on and the sixth switching transistor T13 to turn on; simultaneously, a low potential voltage is charged (discharge process) to the gates of the first isolation transistor T16 and the second isolation transistor T17, thereby controlling the first isolation transistor T16 and the second isolation transistor T17 to turn on. See Figure 12 for details; Figure 12 is a schematic diagram of the equivalent circuit structure of the dimming circuit in the first driving stage of this application. The second diode D2 and the third diode D3 are used to maintain the low potential voltage on the second capacitor C2 and the third capacitor C3. In this stage, the low potential signal on the low potential control signal line VGL is transmitted to the first plate of the bootstrap capacitor C1 through the first transistor T11. Based on the coupling effect of the bootstrap capacitor C1, the gate voltage of the low potential driving transistor DT11 is pulled low, thereby turning on the low potential driving transistor DT11 and outputting a low-potential frequency modulation signal EN(N). Meanwhile, due to the isolation effect of the second transistor T12 and the seventh switching transistor T14, even if the first isolation transistor T16 and the second isolation transistor T17 are turned on, the charge on the bootstrap capacitor C1 will not be discharged.

[0113] In the second driving stage P3, the second control signal line CK outputs a high potential, controlling the second transistor T12, the seventh switching transistor T14, and the pre-charge transistor T15 to all conduct. Since the gate voltages of the first isolation transistor T16 and the second isolation transistor T17 remain at a low potential, they are also in the conducting state during the second driving stage P3. Please refer to Figure 13 for details; Figure 13 is a schematic diagram of the equivalent circuit structure of the dimming circuit in the second driving stage of this application. In this stage, the high-potential signal on the high-potential control signal line VGH is transmitted to the second plate of the bootstrap capacitor C1 through the second transistor T12. Based on the coupling effect of the bootstrap capacitor C1, the gate voltage of the high-potential driving transistor DT12 is pulled high, thereby turning on the high-potential driving transistor DT12 and outputting a high-potential frequency modulation signal EN(N).

[0114] It should be noted that, since the voltage difference between the first and second plates of the bootstrap capacitor C1 is fixed, its pull-up and pull-down voltages also have a certain stability under the action of the high-potential signal line VGH and the low-potential signal line VGL, thereby improving the stability of the output signal of the dimming circuit 12. Meanwhile, the conduction condition for the high-potential driving transistor DT12 and the low-potential driving transistor DT11 is that the absolute value of the gate-source voltage Vgs (Vgate - Vsource) > Vth. In the example circuit model, Vsource is the EM(N) terminal, which is in a floating state. When in operation, due to the parasitic capacitance and other effects at the output terminal, EM(N) may retain a potential close to the previous timing in some abnormal states. At the same time, due to the voltage drop at the junction of the second transistor T12, the sixth switching transistor T13, the seventh switching transistor T14, and the first isolation transistor T16, the voltage transmitted from the high-potential signal line VGH and the low-potential signal line VGL to the gate of the high-potential transistor D12 and the low-potential driving transistor D11 may be slightly lower than VGH and VGL (absolute value). In this case, Vgate - Vsource may be close to or lower than Vth, causing the high-potential transistor D12 and the low-potential driving transistor D11 to fail to conduct, thus affecting the function. The stability of the voltage drop across the gates of the high-potential signal line VGH and the low-potential signal line VGL to the gates of the high-potential transistor D12 and the low-potential drive transistor D11 is ensured by the bootstrap capacitor C1.

[0115] Furthermore, the driving cycle of the dimming circuit 12 includes a blank phase, as detailed in Figure 14, which is a schematic diagram of the equivalent circuit structure of the dimming circuit in the blank phase. During this phase, the bootstrap capacitor C1, the second capacitor C2, and the third capacitor C3 are reset via the reset signal line CLR, the first isolation transistor T16 and the second isolation transistor T17 are turned off, and the potential on the bootstrap capacitor C1 is reset, preparing for the next frame.

[0116] In the light-emitting stage, the dimming circuit 12 controls the alternation of the first driving stage P2 and the second driving stage P3 to output the frequency modulation signal EN(N). The frequency modulation signal EN(N) is a transition signal consisting of a high-level signal and a low-level signal. The duty cycle of the high-level signal and the low-level signal can be adjusted according to the control signals on the first control signal line XCK and the second control signal line CK. For example, when the luminous efficiency of the first light-emitting device OLED1 is significantly lower than that of the second light-emitting device OLED2, the duty cycle of the high-potential control signal output by the second control signal line CK can be increased, while the duty cycle of the high-potential control signal output by the first control signal line XCK can be decreased, thereby increasing the duty cycle (light-emitting time) of the first light-emitting device OLED1 and thus increasing the brightness of the light-emitting layer corresponding to the first light-emitting device OLED1.

[0117] The beneficial effects of this embodiment are as follows: By placing the anodes of the pixel driving circuit on both sides of the light-emitting group and setting the output terminals of the driving transistors as two parallel anode outputs, it is ensured that the voltage applied to the anode terminals of the two OLEDs is equal during operation. By designing the control transistors (first switching transistor and second switching transistor) to which the two anode outputs belong as a set of TFTs with opposite channel types, the two light-emitting layers are controlled to emit light in a time-division manner. By changing the pulse signal output by the dimming circuit (GOA) to a frequency-modulated signal with positive and negative values, the duty cycle can be adjusted simultaneously. Based on the luminous efficiency of the two OLED light-emitting devices, the PWM (pulse width modulation) frequency of the two OLEDs is changed by adjusting the duty cycles of CK and XCK, thereby effectively adjusting the panel display effect.

[0118] This application also provides a display panel, specifically referring to FIG15, which is a structural schematic diagram of an embodiment of the display panel of this application. As shown in FIG15, the display panel includes a substrate 10, a pixel driving circuit layer 20 disposed on the substrate 10, and an OLED stacked structure 30 disposed on the pixel driving circuit layer 20. The OLED stacked structure 30 includes a first light-emitting device OLED1 and a second light-emitting device OLED2. The first light-emitting device OLED1 and the second light-emitting device OLED2 are stacked in parallel as shown in FIG1(a). Specifically, the light-emitting layers of the first light-emitting device OLED1 and the second light-emitting device OLED2 are stacked, and the anodes of the first light-emitting device OLED1 and the second light-emitting device OLED2 are disposed opposite each other on both sides of the stacked light-emitting layer. The cathodes of the first light-emitting device OLED1 and the second light-emitting device OLED2 are shared. Specifically, referring to FIG15, the first anode 31 of the first light-emitting device OLED1 and the second anode 32 of the second light-emitting device OLED2 are disposed on the upper and lower sides of the stacked light-emitting layer. The second anode 32 of the second light-emitting device OLED2 can be connected to the pixel driving circuit in the lower pixel driving circuit layer 20 through vias on the pixel definition layer.

[0119] The pixel driving circuit layer 20 contains multiple transistors, which are interconnected to form the pixel driving circuit in the above embodiment. The pixel driving circuit is connected to the anode of the stacked first light-emitting device OLED1 and the second light-emitting device OLED2, and is used to control the light emission of the first light-emitting device OLED1 and the second light-emitting device OLED2. The first light-emitting device OLED1 can be positioned above the second light-emitting device OLED2, or the second light-emitting device OLED2 can be positioned above the first light-emitting device OLED1; this is not limited here. The OLED stacked structure 30 is shown in Figure 1(a).

[0120] The above are merely embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A display driving circuit, characterized in that, The display driving circuit includes: A first light-emitting device and a second light-emitting device stacked together; A pixel driving circuit connected to the first light-emitting device and the second light-emitting device; The pixel driving circuit includes: A driving circuit, which is connected to the anodes of the first light-emitting device and the second light-emitting device, is used to control the voltage applied to the first light-emitting device and the second light-emitting device; A first switching circuit is disposed between the driving circuit and the anode of the first light-emitting device, and is used to control the first light-emitting device to emit light; A second switching circuit is disposed between the driving circuit and the anode of the second light-emitting device, and is used to control the second light-emitting device to emit light; A dimming circuit is connected to the control terminals of the first and second switching circuits and is used to output a frequency modulation signal to control the first light-emitting device and the second light-emitting device to emit light.

2. The display driving circuit according to claim 1, characterized in that, The first switching circuit includes a first switching transistor, and the second switching circuit includes a second switching transistor. The first switching transistor and the second switching transistor are a pair of transistors with opposite driving characteristics.

3. The display driving circuit according to claim 1, characterized in that, The driving circuit includes: A driving transistor, wherein the gate of the driving transistor is connected to a first signal line, the first electrode of the driving transistor is connected to a power supply line, and the second electrode of the driving transistor is connected to the anode of the first light-emitting device and the second light-emitting device; A storage capacitor, wherein the first plate of the storage capacitor is connected to the gate of the driving transistor, and the second plate of the storage capacitor is connected to the power supply line, for maintaining the gate voltage of the driving transistor; A third switching transistor is disposed between the first electrode of the driving transistor and the data line; the first electrode of the third switching transistor is connected to the data line, and the second electrode of the third switching transistor is connected to the first electrode of the driving transistor. A fourth switching transistor is disposed between the second electrode of the driving transistor and the gate of the driving transistor; the first electrode of the fourth switching transistor is connected to the second electrode of the driving transistor, and the second electrode of the fourth switching transistor is connected to the gate of the driving transistor and the first plate of the storage capacitor. A fifth switching transistor is disposed between the power supply line and the first electrode of the driving transistor; the first electrode of the fifth switching transistor is connected to the power supply line, and the second electrode of the fifth switching transistor is connected to the first electrode of the driving transistor.

4. The display driving circuit according to claim 3, characterized in that, The driving circuit also includes: A first reset transistor is disposed between the first signal line and the gate of the driving transistor. The first electrode of the first reset transistor is connected to the first signal line, and the second electrode of the first reset transistor is connected to the gate of the driving transistor, for controlling the driving transistor.

5. The display driving circuit according to claim 3, characterized in that, The driving circuit also includes: The second reset transistor has its first electrode connected to the second signal line and its second electrode connected to the anodes of the first and second light-emitting devices, and is used to reset the anodes of the first and second light-emitting devices.

6. The display driving circuit according to claim 3, characterized in that, The gate of the third switching transistor is connected to the gate of the fifth switching transistor via the same signal line, and the third switching transistor and the fifth switching transistor are a pair of transistors with opposite driving characteristics.

7. The display driving circuit according to claim 2, characterized in that, The dimming circuit includes: A low-potential driving transistor, wherein the gate of the low-potential driving transistor is connected to a control circuit, the first electrode of the low-potential driving transistor is connected to a low-potential signal line, and the second electrode of the low-potential driving transistor is connected to the gates of the first switching transistor and the second switching transistor. A high-potential driving transistor, wherein the gate of the high-potential driving transistor is connected to a control circuit, the first electrode of the high-potential driving transistor is connected to a high-potential signal line, and the second electrode of the high-potential driving transistor is connected to the gates of the first switching transistor and the second switching transistor.

8. The display driving circuit according to claim 7, characterized in that, The low-potential driving transistor and the high-potential driving transistor are a set of transistors with opposite driving characteristics.

9. The display driving circuit according to claim 7, characterized in that, The control circuit includes a low-potential control circuit, a high-potential control circuit, and a bootstrap capacitor. The first plate of the bootstrap capacitor is connected to the low-potential control circuit and the gate of the high-potential driving transistor, and the second plate is connected to the high-potential control circuit and the gate of the low-potential driving transistor. The low-potential control circuit provides a low-potential driving signal to the gate of the low-potential driving transistor through the bootstrap capacitor to control the low-potential driving transistor to turn on. The high-potential control circuit provides a high-potential driving signal to the gate of the high-potential driving transistor through the bootstrap capacitor to control the high-potential driving transistor to turn on.

10. The display driving circuit according to claim 9, characterized in that, The low-potential control circuit includes a first transistor, the gate of the first transistor is connected to a first control signal line, the first electrode of the first transistor is connected to a low-potential signal line, and the second electrode of the first transistor is connected to the first plate of the bootstrap capacitor. The high-potential control circuit includes a second transistor, the gate of which is connected to a second control signal line, the first electrode of which is connected to a high-potential signal line, and the second electrode of which is connected to the second plate of a bootstrap capacitor.

11. The display driving circuit according to claim 10, characterized in that, The first control signal line and the second control signal line are a set of clock signals with opposite phases; the first transistor and the second transistor are a set of transistors with opposite driving characteristics.

12. The display driving circuit according to claim 9, characterized in that, The control circuit also includes: A sixth switching transistor, the gate of which is connected to the first control signal line, the first electrode of which is connected to the second plate of the bootstrap capacitor, and the second electrode of which is connected to the gate of the low-potential drive transistor, wherein the sixth switching transistor and the first transistor are simultaneously turned on, for controlling the transmission of the low-potential drive signal output by the low-potential control circuit to the gate of the low-potential drive transistor, so as to control the turn-on of the low-potential drive transistor; A seventh switching transistor, the gate of which is connected to the second control signal line, the first electrode of which is connected to the first plate of the bootstrap capacitor, and the second electrode of which is connected to the gate of the high-potential driving transistor; the seventh switching transistor and the second transistor are simultaneously turned on to control the transmission of the high-potential driving signal output by the high-potential control circuit to the gate of the high-potential driving transistor, thereby controlling the turn-on of the high-potential driving transistor.

13. The display driving circuit according to claim 12, characterized in that, The control circuit includes cascaded signals and a precharge transistor; The gate of the precharge transistor is connected to the second control signal line, the first electrode of the precharge transistor is connected to the cascaded signal, and the second electrode of the precharge transistor is connected to the first plate of the bootstrap capacitor, for charging the bootstrap capacitor during the precharge phase.

14. The display driving circuit according to claim 13, characterized in that, The control circuit also includes a pre-charge hold transistor; The gate of the precharge-hold transistor is connected to the cascaded signal, the first electrode of the precharge-hold transistor is grounded, and the second electrode of the precharge-hold transistor is connected to the second plate of the bootstrap capacitor, which is used to enable the bootstrap capacitor to have a storage function during the precharge phase.

15. The display driving circuit according to claim 14, characterized in that, Both the precharge transistor and the precharge hold transistor are P-type transistors.

16. The display driving circuit according to claim 13, characterized in that, The control circuit also includes: A first isolation transistor is disposed between the second transistor and the second plate of the bootstrap capacitor, and is used to isolate the cascaded signal from the high-potential signal line during the pre-charge phase, thereby enabling the pre-charge of the bootstrap capacitor. The second isolation transistor is disposed between the gate of the seventh switching transistor and the gate of the high-potential driving transistor, and is used to isolate the cascaded signal from the high-potential driving transistor during the pre-charge phase, so as to prevent the high-potential driving transistor from turning on prematurely.

17. The display driving circuit according to claim 16, characterized in that, The first isolation transistor and the second isolation transistor are N-type transistors.

18. The display driving circuit according to claim 16, characterized in that, The control circuit also includes: The second capacitor has its first plate connected to the gate of the first isolation transistor and its second plate grounded, and is used to control the on / off state of the first isolation transistor. The third capacitor has its first plate connected to the gate of the second isolation transistor and its second plate grounded, and is used to control the on / off state of the second isolation transistor. A first diode, the forward terminal of which is connected to the cascaded signal, and the reverse terminal of which is connected to the first electrode of the precharge transistor; The second diode has its forward terminal connected to the first plate of the second capacitor and the gate of the first isolation transistor, and its reverse terminal connected to the second electrode of the first transistor. The third diode has its forward terminal connected to the first plate of the third capacitor and the gate of the second isolation transistor, and its reverse terminal connected to the second electrode of the first transistor.

19. The display driving circuit according to claim 18, characterized in that, The control circuit includes a reset signal line connected to the bootstrap capacitor, the second capacitor, and the third capacitor; The reset signal line is connected to the first plate of the bootstrap capacitor, the first plate of the second capacitor, and the first plate of the third capacitor, respectively, for resetting the bootstrap capacitor, the second capacitor, and the third capacitor.

20. A display panel, characterized in that, The display panel includes the display driving circuit according to any one of claims 1 to 19.

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