Image sensor with a pixel processor including a replica transistor

Abstract

An image sensor includes a pixel processing circuit that converts radiation into digital pixel data. The pixel processing circuit includes a signal amplifier circuit, and an autozero transistor configured to temporarily connect a signal input of the signal amplifier circuit with a reset node. The image sensor further includes a replica amplifier circuit, a diode-connected replica transistor with a load path electrically connected in series with a current source, and a gate voltage circuit. The gate voltage circuit supplies an autozero switch signal AZSW to a gate of the autozero transistor, wherein an active signal level of the autozero switch signal AZSW for turning on the autozero transistor is a function of a voltage level at a gate of the replica transistor and an output voltage of the replica amplifier circuit.

Description

[0001] 73784

[0002] 1

[0003] IMAGE SENSOR WITH PIXEL PROCESSING CIRCUIT AND REPLICA TRANSISTOR

[0004] The present disclosure relates to a pixel processing circuit for converting incoming radiation into digital image data and a replica transistor emulating an autozero transistor of the pixel processing circuit. More particularly, the present disclosure relates to an emulating a portion of the pixel processing circuit to track process comers, temperature variations, and voltage fluctuations.

[0005] BACKGROUND

[0006] Complementary metal oxide semiconductor imaging sensors (CMOS Imaging Sensors, CIS) convert radiation into analog voltage signals. In event-based vision sensors (EVS), luminance changes detected by each pixel are filtered to extract only those that exceed a preset threshold value. This event is then combined with the pixel coordinate, time, and polarity information to digital event data. In both CIS and EVS, signal amplifier circuits amplify an analog voltage, compare analog voltages, and / or charge capacitances to temporary store electric charge. Amplifier circuits usually have an input offset voltage. Autozeroing is an offset-cancellation technique that samples the input offset voltage of an amplifier circuit in an autozero phase and then subtracts the sampled voltage from the input voltage in a working phase of the amplifier circuit. Further, in EVS the autozero operation is not only to cancel non-idealities, but it is part of the specific principle of operation: the voltage is stored on a capacitor in order to be sensitive only to luminance changes. Metal oxide field effect transistors (MOSFETs) can be used for autozeroing amplifier circuits. Typically, some parts of a pixel processing circuit operate with a low supply voltage than other parts.

[0007] SUMMARY

[0008] A gate voltage effective between the gate terminal and the MOSFET transistor channel must be sufficiently high to fully turn on the MOSFET and is therefore selected higher than the transistor channel voltage plus the transistor threshold voltage. In a pixel processing circuit containing a signal amplifier circuit, the transistor channel voltage of the autozero transistor can assume the positive supply voltage for the signal amplifier circuit. Due to variations in the manufacturing process, the positive supply voltage may vary between different pixel processing circuits of the same image sensor and between corresponding pixel processing circuits of different image sensors of the same lot. In addition, the positive supply voltage can change with temperature. The transistor threshold voltage depends on the individual characteristics of the autozero transistor and may vary between different autozero transistors of the same image sensor and between corresponding autozero transistors of different image sensors of the same lot. In addition, the transistor threshold voltage can change with temperature. A common approach is to provide a sufficiently high gate voltage to ensure that the autozero transistor is fully switched on even in the worst case. However, even if a sufficiently high fixed gate voltage is used to switch on the autozero transistor even in the worst case, this fixed gate voltage may leave the stated good region across PVT due to varying characteristics of the amplifier circuit and the autozero transistor. Further, if unnecessarily high gate voltages are used to switch on the autozero transistor, negative effects can occur in the part of the circuit generating the gate voltage signal. Higher gate voltages may also make the charge injection worse at transistor turn-off phase. This makes variations across PVT also worse, and charge injection of a MOS switch may introduce an 73784

[0009] 2 offset. Capacitive couplings to other circuits may be larger if the voltage swing is larger, so negative effects may not only remain in the part of the circuit that generates the gate voltage signal.

[0010] The present disclosure inter alia mitigates deficiencies in pixel processing circuits with autozeroed signal amplifier circuits. For this purpose, an image sensor includes a pixel processing circuit that converts radiation into digital pixel data. The pixel processing circuit includes a signal amplifier circuit and an autozero transistor configured to temporarily connect a signal input of the signal amplifier circuit with a reset node. The image sensor further includes a replica amplifier circuit, a diode-connected replica transistor with a load path electrically connected in series with a current source, and a gate voltage circuit. The gate voltage circuit supplies an autozero switch signal AZSW to a gate of the autozero transistor, wherein an active signal level of the autozero switch signal AZSW (active autozero switch signal AZSW) for turning on the autozero transistor is a function of a voltage level at a gate of the replica transistor and an output voltage of the replica amplifier circuit.

[0011] The diode-connected replica transistor operates in full saturation. Provided sufficient similarity between the diode-connected replica transistor and the autozero transistor, the gate voltage of the diode-connected replica transistor and the threshold voltage of the autozero transistor show almost identical dependencies on process comers, supply voltage fluctuations and temperature variations. Provided sufficient similarity between the signal amplifier circuit in the pixel processing circuit and the replica amplifier circuit, the output voltage of the signal amplifier circuit and the output voltage of the replica amplifier transistor show almost identical dependencies on process comers, supply voltage fluctuations and temperature variations. Based on the gate voltage of the diode-connected replica transistor and the output voltage of the replica amplifier circuit, the gate voltage circuit can turn on the autozero switch with an active signal level that follows process comers, voltage fluctuations and temperature variations. The active signal level (active voltage level) of the gate signal can be provided with a minimum safety margin. A lower active signal level reduces adverse effects in the gate voltage generation circuitry. The pixel processing circuit can work more reliably.

[0012] BRIEF DESCRIPTION OF THE DRAWINGS

[0013] A more complete appreciation of the disclosure and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein:

[0014] FIG. 1 is a simplified circuit diagram illustrating a portion of a pixel processing circuit with an n-channel MOSFET (NMOS transistor) autozero transistor, a replica transistor, a replica amplifier circuit and a gate voltage circuit, in accordance with an embodiment.

[0015] FIG. 2 is a simplified circuit diagram illustrating a portion of a pixel processing circuit with a p-channel MOSFET (PMOS transistor) autozero transistor, a replica transistor, a replica amplifier circuit and a gate voltage circuit, in accordance with an embodiment. 3

[0016] FIG. 3 is a simplified circuit diagram illustrating a portion of a pixel processing circuit with a signal amplifier circuit and an NMOS autozero transistor with a controlled load path between a signal input of the signal amplifier circuit and a reference potential, a replica transistor, a replica amplifier circuit and a gate voltage circuit, in accordance with an embodiment.

[0017] FIG. 4 is a simplified circuit diagram illustrating a portion of a pixel processing circuit with a signal amplifier circuit and an NMOS autozero transistor with a controlled load path between a signal input and a signal output of the signal amplifier circuit, a replica transistor, a replica amplifier circuit and a gate voltage circuit, in accordance with another embodiment.

[0018] FIG. 5 is a simplified circuit diagram illustrating a portion of a pixel processing circuit, a replica transistor, a replica amplifier circuit and a gate voltage circuit with a digital memory for obtaining the signal level for the active autozero switch signal from the gate voltage of the replica transistor and the output voltage of the replica amplifier circuit, in accordance with an embodiment.

[0019] FIG. 6 is a simplified circuit diagram illustrating a portion of a pixel processing circuit, a replica transistor, a replica amplifier circuit and a gate voltage circuit with a digital memory for obtaining the signal level for the active autozero switch signal from the gate voltage of the replica transistor, the output voltage of the replica amplifier circuit, and a measured temperature, in accordance with an embodiment.

[0020] FIG. 7 is a simplified circuit diagram illustrating a portion of a pixel processing circuit, a replica transistor, a replica amplifier circuit and a gate voltage circuit with voltage coupling elements for obtaining the signal level for the active autozero switch signal directly from the gate voltage of the replica transistor and the output voltage of the replica amplifier circuit, in accordance with another embodiment.

[0021] FIG. 8 is a circuit diagram illustrating a signal amplifier circuit with PMOS input, NMOS autozero transistor, a replica transistor, a replica amplifier circuit and a gate voltage circuit with voltage coupling elements, in accordance with another embodiment.

[0022] FIG. 9 is a circuit diagram illustrating a signal amplifier circuit with PMOS input, NMOS autozero transistor, NMOS replica transistor, a replica amplifier circuit and agate voltage circuit with voltage buffers as voltage coupling element in accordance with an embodiment.

[0023] FIG. 10 is a circuit diagram illustrating a signal amplifier circuit with PMOS input, PMOS autozero transistor, PMOS replica transistor, a replica amplifier circuit and a gate voltage circuit with voltage buffers as voltage coupling element in accordance with another embodiment.

[0024] FIG. 11 is a circuit diagram illustrating a signal amplifier circuit with NMOS input, NMOS autozero transistor, NMOS replica transistor, a replica amplifier circuit and agate voltage circuit with voltage buffers as voltage coupling element in accordance with an embodiment. 4

[0025] FIG. 12 is a circuit diagram illustrating a signal amplifier circuit with NMOS input, PMOS autozero transistor, PMOS replica transistor, a replica amplifier circuit and a gate voltage circuit with voltage buffers as voltage coupling element in accordance with an embodiment.

[0026] FIG. 13 is a circuit diagram illustrating a differential amplifier as signal amplifier circuit, NMOS autozero transistor, NMOS replica transistor, a replica amplifier circuit and agate voltage circuit with voltage buffers as voltage coupling element in accordance with an embodiment.

[0027] FIG. 14A is a timing diagram of the autozero switch signal in accordance with an embodiment.

[0028] FIG. 14B is a circuit diagram illustrating an autozero circuit for an NMOS autozero transistor in accordance with an embodiment.

[0029] FIG. 15 is a simplified block diagram illustrating a configuration example of a solid-state imaging device in accordance with an embodiment with pixel circuits and shared replica circuits integrated in an EVS image sensor for synchronous readout.

[0030] FIG. 16 is a simplified block diagram illustrating a configuration example of a solid-state imaging device in accordance with an embodiment with pixel circuits including replica circuits integrated in an EVS image sensor for asynchronous readout.

[0031] FIG. 17 is a simplified circuit diagram of an EVS pixel circuit that includes a signal amplifier circuit with PMOS input, an NMOS autozero transistor, an NMOS replica transistor, a replica amplifier circuit and a gate voltage circuit with voltage buffers as voltage coupling element in accordance with an embodiment.

[0032] FIG. 18 is a timing diagram for control signals for the image sensor of FIG. 17 in accordance with an embodiment.

[0033] FIG. 19 is a simplified circuit diagram of a portion of a CIS pixel circuit with a signal amplifier circuit having a differential input, NMOS autozero transistors, an NMOS replica transistor, a replica amplifier circuit and a gate voltage circuit in accordance with another embodiment.

[0034] FIG. 20 is a diagram showing an example of a laminated structure of a solid-state imaging device according to an embodiment of the present disclosure.

[0035] FIG. 21 is a block diagram depicting an example of a schematic configuration of a vehicle control system.

[0036] FIG. 22 is a diagram of assistance in explaining an example of installation positions of an outside-vehicle information detecting section and an imaging section of the vehicle control system of FIG. 21.

[0037] DETAILED DESCRIPTION 5

[0038] Embodiments for implementing techniques of the present disclosure (also referred to as “embodiments” in the following) will be described below in detail using the drawings. The techniques of the present disclosure are not limited to the described embodiments, and various features in the embodiments are illustrative only. The same elements or elements with the same functions are denoted by the same reference signs. Duplicate descriptions are omitted.

[0039] Connected electronic elements may be electrically connected through a direct, permanent low-resistive connection, e.g., through a conductive line. The terms “electrically connected” and “signal-connected” may also include a connection through other electronic elements provided and suitable for permanent and / or temporary signal transmission and / or transmission of energy. Electronic elements can be electrically connected or signal-connected via resistors, capacitors, electronic switches such as MOSFETs, or transistor circuits such as transmission gates. Directly electrically connected electronic elements are connected through a low-resistive wiring, an ohmic contact and / or a unipolar semiconductor junction.

[0040] The load path of a transistor is the controlled current path through a transistor. A voltage applied to the gate of a field effect transistor controls the current flow through the load path (controlled path) between source and drain of the MOSFET by field effect.

[0041] A digital signal alternates between at least one active level and at least one inactive level. A digital signal having an active level is active. A digital signal having an inactive level is inactive. For each signal separately, the active level can be a digital high level and the inactive level a digital low level, or the active level can be the digital low level and the inactive level the digital high level.

[0042] Though in the following a technology for tracking process comers, voltage fluctuations and temperature variations is described in the context of certain types of CIS pixel circuits, EVS pixel circuits and readout schemes, the technology may also be used for other types of CIS and EVS pixel circuits and other pixel readout schemes.

[0043] FIG. 1 and FIG. 2 show a portion of a pixel processing circuit 100 of an image sensor 70. The pixel processing circuit 100 converts radiation into digital pixel data and includes a signal amplifier circuit 120 and an autozero transistor 130 that temporarily connects a signal input of the signal amplifier circuit 120 with a reset node 135. The image sensor 70 further includes a replica amplifier circuit 220, a diode- connected replica transistor 230 with a load path electrically connected in series with a current source 240, and a gate voltage circuit 300. The gate voltage circuit 300 supplies an autozero switch signal AZSW to a gate of the autozero transistor 130, wherein an active signal level of the autozero switch signal AZSW for turning on the autozero transistor 130 is a function of a voltage level at a gate of the replica transistor 230 and an output voltage of the replica amplifier circuit 220.

[0044] The image sensor 70 may be a EVS or CIS. The pixel processing circuit 100 may include a photoelectric conversion element that generates a photocurrent with a current rating that is proportional to received radiation intensity. The pixel processing circuit 100 converts the photocurrent into a pixel voltage. For CIS, the pixel processing circuit 100 includes a downstream analog -to-digital converter that converts the analog 73784

[0045] 6 pixel voltage into a digital pixel value (digital pixel data). For EVS, the pixel processing circuit 100 fdters luminance changes detected by the photoelectric conversion element to extract luminance changes that exceed a preset threshold value. The pixel processing circuit 100 combines this event data with a pixel coordinate, time, and polarity information to digital pixel data.

[0046] The signal amplifier circuit 120 may be a two-port electronic circuit that uses electric power from a power supply to increase the signal amplitude of a time-varying input signal applied to an input port. At an output port, the signal amplifier circuit 120 produces an output signal with a signal level proportionally greater than the signal level of the input signal, or a digital output signal with a high-amplitude output signal when a signal level of the input signal is above a threshold level and with a low-amplitude signal level otherwise, or a digital output signal with a low-amplitude output signal when a signal level of the input signal is above a threshold level and with a high-amplitude signal level otherwise.

[0047] A power supply supplies a positive first supply voltage VDDL and a supply reference potential GND to the signal amplifier circuit 120. The input signal is a voltage signal with time-dependent voltage amplitude and is applied between a signal input and the supply reference potential GND. The output signal is a voltage signal with time-dependent voltage amplitude produced between a signal output and the supply reference potential GND.

[0048] For EVS, the signal amplifier circuit 120 may be part of a comparator circuit for detecting whether a luminance change exceeds or falls below a threshold. For CIS, the signal amplifier circuit 120 may be used to temporarily store a charge sampled from the photocurrent, e.g., for global shutter readout, analog binning, in-pixel analog -to-digital conversion, and / or pixel signal time-multiplexing. Also, the signal amplifier circuit may be a column amplifier that reads the charge-dependent voltage from the pixel and passes it to the ADC.

[0049] A load path of the autozero transistor 130 is electrically connected between the signal input of the amplifier circuit and a reference node 135. The reference node 135 is a non-floating circuit node with constant or changing potential. The potential of the reference node 135 may be fixed, e.g., a potential driven by a driver output with constant input signal, a potential derived from a passive voltage divider, a positive supply potential, or the supply reference potential. Alternatively, the reference node 135 can be an internal network node of the pixel processing circuit 100 with changing potential.

[0050] The autozero transistor 130 may be a MOSFET with lower leakage current than other MOSFETs of the pixel processing circuit 100. For example, the autozero transistor 130 may have a significant thicker gate dielectric than all other MOSFETs of the pixel processing circuit 100.

[0051] In FIG. 1 the autozero transistor 130 is an NMOS transistor with the controlled load path between source and drain electrically connected between the signal input of the signal amplifier circuit 120 and the reference node 135. 7

[0052] In FIG. 2 the autozero transistor 130 is a PMOS transistor with the controlled load path between source and drain electrically connected between the signal input of the signal amplifier circuit 120 and the reference node 135.

[0053] The replica amplifier circuit 220 may have the same electrical configuration of components as the signal amplifier circuit 120. For example, the signal amplifier circuit 120 and the replica amplifier circuit 220 may include the same electrical components, which have the same nominal characteristics and which are electrically connected in the same way. The replica amplifier circuit 220 may be supplied through the first supply voltage VDDL and supply reference potential GND in the same way as the signal amplifier circuit 120.

[0054] At least one of temperature responses, supply voltage dependencies and manufacturing process dependencies of the signal amplifier circuit 120 and the replica amplifier circuit 220 may be proportional per design.

[0055] Corresponding target dimensions and target doping concentrations of components of the autozero amplifier circuit 120 and target dimensions and target doping concentrations of corresponding components of the replica amplifier circuit 120 have a preset relationship. With zero deviations of the actual device dimensions and doping concentrations from the respective target dimensions and doping concentrations, the signal amplifier circuit 120 and the replica amplifier circuit 220 show known supply voltage and temperature dependencies. When process conditions change, the electrical characteristics of the signal amplifier circuit 120 and the replica amplifier circuit 220 change in a predictable and / or correlated way, i.e. changes are not contrasted but copied.

[0056] The temperature responses, supply voltage dependencies and manufacturing process dependencies of the signal amplifier circuit 120 and the replica amplifier circuit 220 may be identical per design. For example, signal amplifier circuit 120 and replica amplifier circuit 220 may emerge from the same lithography masks, the same target dimensions, and the same exposure, deposition and etch processes.

[0057] With zero deviations of the actual device dimensions and doping concentrations form from the respective target dimensions and doping concentrations, the signal amplifier circuit 120 and the replica amplifier circuit 220 show the same supply voltage and temperature dependencies. When process conditions change, the electrical characteristics of the signal amplifier circuit 120 and the replica amplifier circuit 220 change in the same way. For example, signal amplifier circuit 120 and replica amplifier circuit 220 may emerge from the same lithography masks and the same exposure, deposition and etch processes.

[0058] The replica transistor 230 is diode-connected and operates in full saturation. The current source 240 and the load path of the replica transistor 230 are electrically connected in series between a positive supply potential VDD and the supply reference potential GND. Further electric elements may be electrically connected in series with the current source 240 and the load path of the replica transistor 230 between the positive supply potential VDD and the supply reference potential GND. The positive supply potential VDD may be the first supply potential VDDL or may deviate from the first supply potential VDDL. 8

[0059] The current source 240 may be or may include a resistor or a transistor, e.g., a MOSFET with constant or programmable gate bias voltage. The replica transistor 230 and the autozero transistor 130 have the same type.

[0060] In FIG. 1, the autozero transistor 130 and the replica transistor 230 are NMOS transistors. The current source 240 is electrically connected between the positive supply potential VDD and the drain of the replica transistor 230. The drain and the gate of the replica transistor 230 are electrically connected. The source is electrically connected to the supply reference potential GND. The current source 240 supplies a current high enough to ensure that the voltage at the gate of the replica transistor 230 can reach the threshold voltage for saturation.

[0061] In FIG. 2, the autozero transistor 130 and the replica transistor 230 are PMOS transistors. The source of the replica transistor 230 is electrically connected to the positive supply potential VDD. The current source 240 is electrically connected between the drain of the replica transistor 230 and the supply reference potential GND. The drain and the gate of the replica transistor 230 are electrically connected. The current source 240 supplies a current high enough to ensure that the voltage drop across the load path of the replica transistor 230 can reach the threshold voltage for saturation, i.e. that the replica transistor 230 is “sufficiently on”. The voltage drop is then copied to the autozero transistor 130. Here, it is important to notice that the particular connection is arbitrary as long as the gate voltage circuit 300 can take the source-gate voltage of the replica transistor 230 and stack it by subtraction to the voltage generated by the replica amplifier circuit 220. This makes sure that the voltage between the input of the signal amplifier circuit 120 and the gate of the autozero transistor 130 is equal to the voltage between the source and gate of the replica transistor 230.

[0062] At least one of temperature responses, supply voltage dependencies and manufacturing process dependencies of the autozero transistor 130 and the replica transistor 230 may be proportional per design.

[0063] With zero deviations of the actual device dimensions and doping concentrations form from the respective target dimensions and doping concentrations, the autozero transistor 130 and the replica transistor 230 show known supply voltage and temperature dependencies. When process conditions change, the electrical characteristics of the autozero transistor 130 and the replica transistor 230 change in a predictable way.

[0064] The temperature responses, supply voltage dependencies and manufacturing process dependencies of the autozero transistor 130 and the replica transistor 230 may be identical per design.

[0065] With zero deviations of the actual device dimensions and doping concentrations form from the respective target dimensions and doping concentrations, the autozero transistor 130 and the replica transistor 230 show the same supply voltage and temperature dependencies. When process conditions change, the electrical characteristics of the autozero transistor 130 and the replica transistor 230 change in the same way. For example, autozero transistor 130 and the replica transistor 230 may emerge from the same lithography masks, the same target dimensions, and the same exposure, deposition and etch processes. 9

[0066] The replica amplifier circuit 220, the diode-connected replica transistor 230, and the current source 240 form components of a replica circuit 200 that images the electrical behavior of the signal amplifier circuit 120 and the autozero transistor 130. The gate voltage of the diode-connected replica transistor 230 shows the same dependencies from process, voltage, and temperature variations as the threshold voltage of the autozero transistor 130. The output voltage of the replica amplifier circuit 220 shows the same dependencies from process, voltage, and temperature variations as the output voltage of the signal amplifier circuit 120.

[0067] From the voltage level at the gate of the replica transistor 230 and the output voltage of the replica amplifier circuit 220, the gate voltage circuit 300 derives the active signal level of an autozero switch signal AZSW, which is applied to the gate of the autozero transistor 130 to turn on the autozero transistor 130 in an autozero phase of the signal amplifier circuit 120.

[0068] The current source 240 may be controllable.

[0069] If the current source 240 includes a MOSFET with gate bias voltage, the gate bias voltage may be programmable during a device test for the image sensor towards the end of the manufacturing process and / or in-situ during operation. In the latter case, a sensor controller integrated in the image sensor 70 may output a voltage control signal that selects or adjusts the gate bias voltage in response to changing environmental conditions and / or user settings. The current source 240 may be adjusted to supply a sufficiently high current to reliably fully turn on the replica transistor over the temperature and voltage ranges of the safe operating area the image sensor is specified for. For example, the replica circuit 200 may include a one-time writeable or rewriteable register 242 written in a test procedure or during operation. A digital-to-analog converter 242 converts the digital value stored in the register 242 into a corresponding analog voltage biasing the gate the MOSFET.

[0070] The active signal level of the autozero switch signal AZSW may be higher than a sum of a nominal threshold voltage of the autozero transistor 130 and a highest voltage at the reset node 135.

[0071] The highest voltage at the reset node 135 is the highest potential the reset node can have during operation within the safe operating area and can be identical with the first supply voltage VDDL. In case the reset node 135 is a node with fixed potential, the highest voltage is identical with the fixed potential.

[0072] In FIG. 3, the reset node 135 is connected to a fixed potential.

[0073] In the illustrated example, the fixed potential is the supply reference potential GND. A storage capacitance 119 may decouple the signal input of the signal amplifier circuit 120 from an up-stream part of the pixel processing circuit 100. The autozero transistor 130 and the replica transistor 230 are NMOS transistors. The source of the replica transistor 230 is directly connected to the supply reference potential.

[0074] The pixel processing circuit 100 may be that of an EVS, wherein a momentary voltage drop across the storage capacitance 119 results from a voltage obtained by current-to-voltage conversion of the momentary 73784

[0075] 10 photocurrent and a preceding voltage drop across the storage capacitance 119 in the preceding autozero phases.

[0076] The signal amplifier circuit 100 may include a single comparator stage for successively comparing the voltage at the signal input to two different threshold voltages for detecting on-events indicating increasing light intensity and off-events indicating decreasing light intensity, or a double comparator stage for simultaneously comparing the voltage at the signal input to two different threshold voltages for detecting on-events and off-events. Here, the input of the replica amplifier 220 may be a fixed voltage that is chosen in accordance to what is the input for the pixel amplifier circuit 120.

[0077] In FIG. 4, the autozero transistor 130 is electrically connected between the signal input and a signal output of the signal amplifier circuit 120.

[0078] The load path of the autozero transistor 130 is electrically connected between the signal input and the signal output of the signal amplifier circuit 120. The signal input of the replica amplifier circuit 220 can be directly electrically connected with the signal output of the replica amplifier circuit 220. The output voltage of the replica amplifier circuit 220 images the output voltage of the signal amplifier circuit 120.

[0079] The signal amplifier circuit 120 may further include a feedback / hold capacitance 129 electrically connected between the signal input and the signal output of the signal amplifier circuit 120.

[0080] In FIG. 5, a gate voltage circuit 300 uses a look-out table to obtain a suitable active signal level for the autozero switch signal AZSW from the voltage level at the gate of the replica transistor 230 and the output voltage of the replica amplifier circuit 220.

[0081] The gate voltage circuit 300 includes a measurement circuit 312 that obtains digital values of a voltage level at the gate of the replica transistor 230 and the output voltage of the replica amplifier circuit 220. A memory circuit 314 stores and outputs process values for a plurality of combinations of different voltage levels at the gate of the replica transistor 230 and the output voltage of the replica amplifier circuit 220. A digital-to-analog converter 318 converts a selected process value output by the memory circuit 314 into a ramp reference voltage REFR. An autozero circuit 380 may generate the autozero switch signal AZSW with an active high level based on the ramp reference voltage REFR.

[0082] The measurement circuit 312 may measure the voltage level at the gate of the replica transistor 230 and the output voltage of the replica amplifier circuit 220 permanently, at regular intervals, in response to a change of internal conditions in the image sensor 70, or in response to a control signal output by a sensor controller integrated in the image sensor 70. The measurement circuit 312 generates and outputs digital values for both the voltage level at the gate of the replica transistor 230 and the output voltage of the replica amplifier circuit 220.

[0083] The memory circuit 314 may contain programmable or writeable memory cells, wherein each memory cell has a unique memory address. Each memory cell stores a process value, wherein each process value stands 73784

[0084] 11 for a specific active signal level of the autozero switch signal matching with the measured values for the voltage level at the gate of the replica transistor 230 and the output voltage of the replica amplifier circuit 220. The process values can be written into the memory circuit 314 in an initialization routine towards the end of a device test for the image sensor. During operation, the memory circuit 314 outputs the process value stored at the memory address accessible through the digital values for the voltage level at the gate of the replica transistor 230 and the output voltage of the replica amplifier circuit 220.

[0085] The digital -to-analog converter 318 converts the output process value into an analog ramp reference voltage REFR. The autozero circuit 380 switches the autozero switch signal AZSW between an active level and an inactive level in response to an autozero signal AZ, wherein the active level is a function of the ramp reference voltage REFR, and wherein a transition from the active level to the inactive level can be significantly slower that a transition from the inactive lever to the active level to avoid a separation of channel charge in the autozero transistor 130. The active level of the autozero switch signal AZSW be the same as the ramp reference voltage REFR.

[0086] In FIG. 6, the gate voltage circuit 300 further includes a temperature measurement circuit 316 to obtain a digital temperature value of the image sensor 70. The memory circuit 314 stores and outputs process values for a plurality of combinations of different temperatures of the image sensor 70, different voltage levels at the gate of the replica transistor 230 and different voltage levels of the output voltage of the replica amplifier circuit 220.

[0087] A digital -to-analog converter 318 converts the selected process value output by the memory circuit 314 into the ramp reference voltage REFR. The autozero circuit 380 generates the autozero switch signal AZSW with an active high level derived from or equal to the ramp reference voltage REFR.

[0088] The signal amplifier circuit 120 includes a p channel MOSFET 121 and an n channel MOSFET 122 electrically connected in series between a positive first supply voltage VDDL and a supply reference potential GND, wherein a gate of one of the n channel MOSFET 122 and the p channel MOSFET 121 represents the signal input of the signal amplifier circuit 120 and a node between the p channel MOSFET 121 and the n channel MOSFET 122 represents the signal output of the signal amplifier circuit 120.

[0089] More specifically, the PMOS transistor 121 and the NMOS transistor 122 are electrically connected in this order between a positive first supply voltage VDDL and the supply reference potential GND and form a comparator. The signal input of the signal amplifier circuit 120 is the gate of the PMOS transistor 121. The signal output is the node between the PMOS transistor 121 and the NMOS transistor 122. A constant or switched signal bias voltage VBS is applied to the gate of the NMOS transistor 122. The autozero transistor 130 is an NMOS transistor with the load path electrically connected between the signal input and the signal output of the signal amplifier circuit 120.

[0090] The replica amplifier circuit 220 includes a replica comparator with a replica PMOS transistor 221 and a replica NMOS transistor 222 electrically connected in this order between the positive first supply voltage 73784

[0091] 12

[0092] VDDL and the supply reference potential GND. The gate of the replica PMOS transistor 221 is electrically connected to the node between the replica PMOS transistor 221 and the replica NMOS transistor 222.

[0093] A constant replica bias voltage VBR is applied to the gate of the replica NMOS transistor 222. In case of a constant signal bias voltage VBS, the signal bias voltage VBS and the replica bias voltage VBR may be equal. In case of switched signal bias voltages VBS, the replica bias voltage VBR may be equal to one of the switched signal bias voltages or equal to a mean value of the switched signal bias voltages.

[0094] Here, the replica bias voltage VBR is not necessarily constant. More generally, VBR may be switched. For example, it may be constant only during sensing. For instance, the digital circuit could be also used to collect information about the replica amplifier circuit 220 and the replica transistor 230 at bias conditions that are not the ones during autozero, and have a compensation scheme that uses also this information to extract, for instance, transistor characteristics specific to the chip and conditions in an automate way.

[0095] The diode-connected replica transistor 230 is an NMOS transistor, wherein a current source 240 and the load path of the replica transistor 230 are electrically connected in series between a positive supply voltage VDD and the supply reference potential GND. The positive supply voltage VDD may be the same as the first supply voltage VDDL.

[0096] The ramp reference voltage REFR tracks the threshold voltages of the PMOS transistor 121 and the autozero transistor 130, the first supply voltage VDDL, the transconductance of the NMOS transistor 122 and the signal bias voltage VBS.

[0097] FIG. 7 illustrates a gate voltage circuit 300 that obtains a suitable active voltage level for the autozero switch signal AZSW directly, i.e. per analog signal -coupling, from the voltage level at the gate ofthe replica transistor 230 and the output voltage of the replica amplifier circuit 220 in combination with the signal amplifier circuit 120, the autozero transistor 130, the replica amplifier circuit 220 and the replica transistor 230 as described with reference to FIG. 1. The current source 240 is electrically connected to a positive second supply voltage VDDH, wherein the positive second supply voltage VDDH is higher than the first supply voltage VDDL.

[0098] The gate voltage circuit 300 includes a first voltage coupling element 330 that supplies a first coupling voltage in series with the current source 240 and the load path of the replica transistor 230, wherein the coupling voltage is a function of the output voltage of the replica amplifier circuit 220.

[0099] For example, the coupling voltage may be identical with the output voltage of the replica amplifier circuit 220. Alternatively, the coupling voltage may be a known fraction or a known multiple of the output voltage of the replica amplifier circuit 220. The voltage at the gate of the replica transistor 230 increases by the coupling voltage and follows both the threshold voltage of the replica transistor 230 and the output voltage of the replica amplifier circuit 120. 73784

[0100] 13

[0101] In the illustrated example, the gate voltage circuit 300 further includes a second voltage coupling element 340 that supplies a ramp reference voltage REFR, wherein the ramp reference voltage REFR is a function of the gate voltage of the replica transistor 230.

[0102] For example, the ramp reference voltage REFR may be identical with the gate voltage of the replica transistor 230. Alternatively, the ramp reference voltage REFR may be a known fraction or a known multiple of the gate voltage at the replica transistor 230. The ramp reference voltage REFR contains information about both the threshold voltage of the replica transistor 230 and the output voltage of the replica amplifier circuit 120.

[0103] FIG. 8 shows the gate voltage circuit 300 illustrated in FIG. 7 in combination with a signal amplifier circuit 120 and a replica amplifier circuit 220 as described with reference to FIG. 6.

[0104] In each of FIG. 9 to FIG. 13, the gate voltage circuit 300 includes an input buffer circuit 325, wherein an input of the input buffer circuit 325 receives the output voltage of the replica amplifier circuit 220, and an output of the input buffer circuit 325 is electrically connected with the load path of the replica transistor 230.

[0105] The input buffer circuit 325 decouples the voltage at the output of the replica amplifier circuit 220 from the circuit including the replica transistor 230.

[0106] The gate voltage circuit 300 further includes an output buffer circuit 335, wherein an input of the output buffer circuit 335 receives the gate voltage of the replica transistor 230, and an output of the output buffer circuit 335 is electrically connected with an input of an autozero circuit 380.

[0107] In FIG. 9, the signal amplifier circuit 120 includes a comparator with PMOS input. Load paths of a PMOS transistor 121 and an NMOS transistor 122 are electrically connected in series between a first positive supply voltage VDDL and a supply reference potential GND. A gate of the PMOS transistor 121 receives an input signal derived from the photocurrent of a photoelectric conversion element. A constant or switched signal bias voltage VBS is applied to the gate of the NMOS transistor 122. The signal amplifier circuit 120 outputs an output signal at the node between the PMOS transistor 121 and the NMOS transistor 122. The autozero transistor 130 is an NMOS transistor with the load path electrically connected between the input and output of the signal amplifier circuit 120.

[0108] The replica amplifier circuit 220 corresponds to that in FIG. 6 and FIG. 8, wherein the output voltage of the replica amplifier circuit 220 is passed to the input of the input buffer circuit 325. The output voltage of the input buffer circuit 325 is supplied to the source of the replica transistor 230, which is an NMOS transistor, wherein the potential at the source of the replica transistor 230 rises by the output voltage of the input buffer circuit 325.

[0109] The current source 240 is electrically connected between a positive second supply voltage VDDH and the drain of the replica transistor 230. The second output buffer 335 outputs the ramp reference voltage REFR. 73784

[0110] 14

[0111] The autozero circuit 380 receives the ramp reference voltage REFR and an autozero signal AZ and generates the autozero switch signal AZSW to control the autozero transistor 130, wherein the ramp reference voltage REFR defines the high level of the autozero switch signal and the autozero switch signal AZSW includes slow transitions from the high level to the low level.

[0112] In FIG. 10, the autozero transistor 130 is a PMOS transistor with the load path electrically connected between the input and output of the signal amplifier circuit 120. The output signal of the input buffer circuit 325 is supplied to the source of the replica transistor 230, which is a PMOS transistor.

[0113] The current source 240 is electrically connected between the drain of the replica transistor 230 and the supply reference potential GND. The second output buffer 335 outputs the ramp reference voltage REFR. The autozero circuit 380 receives the ramp reference voltage REFR and an autozero signal AZ and generates the autozero switch signal AZSW to control the autozero transistor 130, wherein the ramp reference voltage REFR defines the low level of an active low autozero switch signal and the autozero switch signal AZSW includes slow transitions from the low level to the high level.

[0114] In FIG. 11, the signal amplifier circuit 120 includes a comparator with NMOS input. Load paths of a PMOS transistor 121 and an NMOS transistor 122 are electrically connected in series between a positive first supply voltage VDDL and a supply reference potential GND. A constant or switched signal bias voltage VBS is applied to the gate of the PMOS transistor 121. A gate of the NMOS transistor 122 receives an input signal derived from the photocurrent of a photoelectric conversion element. The signal amplifier circuit 120 outputs an output signal at the node between the PMOS transistor 121 and the NMOS transistor 122. The autozero transistor 130 is an NMOS transistor with the load path electrically connected between the input and output of the signal amplifier circuit 120.

[0115] The replica circuit 200 distinguishes from the replica circuit 200 in FIG. 9 in that the gate of the replica NMOS transistor 222 is electrically connected to the output of the replica amplifier circuit 220 and a constant replica bias voltage VBR is applied to the gate of the replica PMOS transistor 221.

[0116] In FIG. 12, the autozero transistor 130 is a PMOS transistor with the load path electrically connected between the input and output of the signal amplifier circuit 120. The output signal of the input buffer circuit 325 is supplied to the source of the replica transistor 230, which is a PMOS transistor.

[0117] FIG. 13 shows a signal amplifier circuit 120 including a differential amplifier.

[0118] The autozero circuit 380 generates the autozero switch signal AZSW, which turns the autozero transistor 130 on and off in response to an autozero control signal AZ. While the autozero transistor 130 can usually be turned on without timing constraints, properly turning off the autozero transistor 130 may require a smooth transition of the gate voltage from the active to the inactive level to avoid or minimize charge injection from the channel into the node that floats after the autozero transistor 130 is turned off. FIG. 14A shows an on-phase of an autozero switch signal AZSW with active high level for controlling an NMOS transistor. At tl, the autozero switch signal AZSW changes to the high level, which is a known function of the ramp reference voltage REFR. At t2, the voltage of the autozero switch signal AZSW begins to linearly drop at a rate which is at least ten times slower than the rate of the transition from the low level to the high level. At t3, the voltage of the autozero switch signal AZSW reaches the low level.

[0119] The autozero circuit 380 generates the autozero switch signal AZSW with a fast transition from the inactive level to the active level and with a slow transition from active level to the inactive level, wherein the active level is derived from the ramp reference voltage REFR.

[0120] The autozero circuit 380 may generate the ramp for the autozero switch signal AZSW in response to an active autozero control signal AZ. In EVS, each EVS pixel circuit may generate a pixel-internal autozero control signal after having detected an event, simultaneously with outputting event signal, or after having output an event signal. In CIS, a controller integrated in the image sensor may generate an active autozero control signal AZ after further processing of a temporarily stored charge or voltage signal is completed.

[0121] The autozero circuit 380 may be completely integrated in the pixel circuits, wherein each pixel circuit includes an autozero circuit 380 that may directly generate the ramp phase of the autozero switching signal AZSW in response to an autozero signal.

[0122] In FIG.14B, the autozero circuit 380 includes a ramp signal circuit 381 for generating the ramp phase of an autozero switching signal AZSW and a plurality of pixel-internal analog switching circuits 386 selectively routing the active ramp phase to only such pixel circuits that have detected an event.

[0123] The ramp generator circuit 381 receives the ramp reference voltage REFR and generates a ramp signal RMP with a fast transition from the inactive level to the active level and a slow transition from the active level to the inactive level. The transition from the active level to the inactive level may be at least 10 times slower than the transition from the inactive level to the active level. The active level is defined by the ramp reference voltage REFR. In case the autozero transistor 130 is an NMOS transistor, the active level is the digital high level. In case the autozero transistor 130 is a PMOS transistor, the active level is the digital low level.

[0124] For the latter case, the ramp generator circuit 381 may include a PMOS transistor and at least one NMOS transistor with the load paths electrically connected in series between the output of the digital-to-analog converter and the supply reference potential GND. A constant bias voltage is applied to the gate of the PMOS transistor. A digital ramp control signal RZ is applied to the gate of the NMOS transistor. The ramp generator circuit 381 outputs the ramp signal RMP at the output node between the PMOS transistor and the NMOS transistor. When the digital ramp control signal RZ goes low, the NMOS transistor switches the output node at a fast rate to the supply reference potential, which corresponds to the active low level. When the digital ramp control signal RZ goes high, the NMOS transistor switches off and the gate-biased PMOS transistor charges the output node to the level of the ramp reference voltage REFR at a slow rate. The 73784

[0125] 16 described ramp generator circuit 381 may form a complete pixel-internal autozero circuit 380, with the autozero signal AZ used as ramp control signal RZ.

[0126] The analog switching circuit 386 receives the ramp signal RMP and passes the ramp signal RMP as the autozero switch signal AZSW to the gate of the autozero transistor 130, when the pixel-internal autozero control signal AZ is active (has the active level). The analog switching circuit 386 outputs the inactive level of the autozero switch signal AZSW to the gate of the autozero transistor 130 when the pixel-internal autozero control signal AZ is inactive (has the inactive level).

[0127] The illustrated analog switching circuit 386 includes a PMOS transistor 387 and an NMOS transistor 388 with the load paths electrically connected in series between the output of the ramp generator circuit 381 and the supply reference potential GND. A load path of a further NMOS transistor 389 is electrically connected in parallel with the PMOS transistor 387. The autozero control signal AZ controls the further NMOS transistor 389. The inverted autozero control signal XAZ controls the PMOS transistor 387 and the NMOS transistor 388. The PMOS transistor 387 and the further NMOS transistor 388 form a transmission gate passing the ramp reference voltage REFRto the output node between the PMOS transistor 387 and the NMOS transistor 388 when the autozero control signal AZ is active. The NMOS transistor 388 connects the output node to the supply reference potential GND when the autozero control signal AZ is inactive.

[0128] A leakage current through the PMOS transistor 387 increases with increasing voltage level of the ramp signal RMP. When the ramp signal RMP is supplied to a plurality of analog switching circuits 386 in parallel, all analog switching circuits 386 that do not receive an active autozero signal AZ are susceptible for unwanted leakage. A low reference ramp voltage REFR reduces the leakage current when the active autozero signal AZ is active.

[0129] FIG. 15 and FIG. 16 relate to an image sensor 70 for event detection. A solid-state imaging device 90 integrates the image sensor 70 and a signal processing unit 80. The image sensor 70 includes a pixel array 10 with a plurality of pixel circuits 11, wherein each pixel circuit 11 is addressable through a unique row address and column address, a signal buffer circuit 20, a row arbiter 30, and a sensor control circuit 50.

[0130] The pixel circuits 11 are arrayed in a two-dimensional matrix in pixel rows and pixel columns. For simplicity, pixel circuits 11 belonging to the same pixel row are arranged along a horizontal line, and pixel circuits 11 belonging to the same pixel column are arranged along a vertical line. Each pixel circuit 11 includes a photoelectronic conversion device that outputs a pixel voltage with a voltage level corresponding to the intensity of received radiation. A capacitive element receives the pixel voltage at a first electrode. A pixel processing circuit includes an event detection circuit. The event detection circuit includes a signal amplifier circuit that outputs an active comparator output signal when a resettable voltage at a floating second electrode of the capacitive element passes a predefined threshold voltage.

[0131] The event detection circuit detects events based on a magnitude of changes in a pixel voltage received from the radiation sensitive circuit. Each event detection circuit is resettable to an initial state by temporarily turning on an autozero transistor that resets the resettable voltage during autozeroing. A digital pixel back- 73784

[0132] 17 end controls the output of event data from the pixel circuit 11 and the autozeroing of the event detection circuit.

[0133] The event data may indicate that the intensity of incident radiation has decreased by more than a step-down value compared to the previous event readout (“OFF event”). Alternatively, the event data may indicate that the intensity of incident radiation has increased by more than a step-up value compared to the magnitude at the previous event readout (“ON event”).

[0134] The signal buffer circuit 20 passes one or more threshold voltages and a memory mode signal to groups of pixel circuits 11 through a control bus 21. Each group of pixel circuits 11 (pixel group) can include some or all pixel circuits 11 of a pixel row, the pixel circuits 11 of more than one pixel row, or all pixel circuits 11 of the pixel array 10.

[0135] FIG. 15 shows an image sensor 70 for synchronous readout. Group control buses 31 connect the pixel circuits 11 with the row arbiter 30. Each group control bus 31 connects the pixel circuits 11 of one pixel group with the row arbiter 30. Each group control bus 31 may include a group request line for transmitting request signals from the pixel circuits 11 of the pixel group to the row arbiter 30, and a group acknowledgement line for transmitting a group acknowledgement signal from the row arbiter 30 to the pixel circuits 11 of a pixel group to be selected.

[0136] For each pixel circuit 11 detecting an event, the digital pixel back-end of the concerned pixel circuit 11 outputs an active request to the row arbiter 30 on the group request line. For transmitting the request, a request signal transmitted on the group request line has an active level.

[0137] The row arbiter 30 performs arbitration among the pending active requests output from the pixel circuits 11 of the pixel array 10. The row arbiter 30 selects a request received from a specific group of pixel circuits 11 according to a predefined priority scheme, acknowledges the selected request by outputting a confirmation on the group control bus 31, and transmits the corresponding group address (e.g. the row number) to a column readout circuit 40. For transmitting the confirmation, the row arbiter 30 outputs an active group acknowledgement signal on the group acknowledgement line. The active group acknowledgement signal selects a group of pixel circuits 11.

[0138] In response to the confirmation, all selected pixel circuits 11 in which an event has been detected, apply the event data on the respective event data bus 41 and clear the event, wherein the pixel circuit 11 is reset and the event detection circuit autozeroed. Each event data bus 41 may be connected to some or all pixel circuits 11 of a same pixel column, or to all pixel circuits 11 of more than one pixel column.

[0139] The event data bus 41 may include a common data line for transmitting the ON events and the OFF events by different signal levels or in a time multiplex scheme. In the illustrated embodiment, the event data bus 41 includes a first data line 42 for transmitting the ON events and a second data line 43 for transmitting the OFF events. For transmitting an ON event, an on-event data signal transmitted on the first data line 42 has 73784

[0140] 18 an active level. For transmitting an OFF event, an off-event data signal transmitted on the second data line 43 has an active level.

[0141] The column readout circuit 40 receives the event data from all pixel circuits 11 of the selected pixel group via the event data bus 41, and the group address(es) of the selected pixel group from which the received event data originates from the row arbiter 30. From the group address and identifiers of the event data buses 41 transmitting event data, the column readout circuit 40 compiles a digital address event representation AER for each event. The AER includes the group address, a column address derived from the identifiers of the event data busses transmitting events, the event data, and, if applicable, a time stamp. The column readout circuit 40 outputs the AERs to the signal processing unit 60.

[0142] A replica circuit 200 with at least one replica amplifier and at least one diode-connected replica transistors is connected to a global ramp reference voltage generating part 320 of a global gate voltage circuit 300. The ramp reference voltage generating part 320 outputs a ramp reference voltage REFR being a function of the voltage level at a gate of the replica transistor and an output voltage of the replica amplifier circuit. A ramp generator circuit 381 receives the ramp reference voltage REFR and generates a ramp signal RMP periodically or in response to a control signal from the signal controller 50.

[0143] The digital pixel back-end includes an analog switching circuit 386 to control the autozeroing of the event detection circuit. The analog switching circuits 386 in the pixel circuits 11 let pass the ramp signal RMP as the autozero switching signal only in pixel circuits having detected an event.

[0144] The solid stage imaging device 90 in FIG. 16 is configured for asynchronous event-triggered readout. The digital pixel back-end controls the output of event data from the pixel circuit 11 and the autozeroing of the event detection circuit by using an autozero circuit 380.

[0145] Each pixel circuit 11 that detects an event may indicate the event by outputting a group request signal on a group request line of a group control bus 31 to the row arbiter 30 and a column request signal on a column interface bus 46 to a column arbiter 45. In the row arbiter 30 and the column arbiter 45, the request signals trigger the compilation of event information. The event information includes a pixel address identifying the position of the pixel circuit 11 in the pixel array 10, the sign of the change in light intensity, and a time stamp. The row arbiter 30 and the column arbiter 45 output the event information to the signal processing unit 60 and confirm to the pixel circuit 11 reception of the event. Upon receiving the confirmations from both the row arbiter 30 and the column arbiter 45, the event in the pixel circuit 11 is cleared and the pixel circuit 11 is reset, which includes an autozeroing of the event detection circuit.

[0146] A replica circuit 200 with at least one replica amplifier and at least one diode-connected replica transistor is connected to a global ramp reference voltage generating part 320 of a global gate voltage circuit 300. The ramp reference voltage generating part 320 outputs a ramp reference voltage REFR being a function of the voltage level at a gate of the replica transistor and an output voltage of the replica amplifier circuit. The ramp reference voltage REFR is passed to all pixel circuits 11. For each pixel circuit 100 separately, 73784

[0147] 19 the pixel-internal autozero circuit 380 generates the autozero switching signal AZSW simultaneously with outputting an event.

[0148] The sensor control circuits 50 may control a timing of changing analog voltage signals in the signal buffer circuit 20, a selection of voltage levels output by the signal buffer circuit 20 according to internal states and / or user settings, the memory mode signal, and / or a communication between the column readout circuit 40 and the signal processing unit 60 of FIG. 15 or between the row arbiter 30, the column arbiter 45 and the signal processing unit 60 of FIG. 16 as indicated by the dashed line.

[0149] FIG. 17 shows the pixel circuit 11 of the EVS image sensor 70 of FIG. 15 in more detail and FIG. 18 illustrates the time charts of the signals in the pixel circuit 11.

[0150] FIG. 19 illustrates a portion of a pixel processing circuit 100 for a time-of-flight (TOF) image sensor with global shutter pixels and using analog binning.

[0151] The pixel processing circuit 100 is configured to temporarily store a pixel charge on a feedback / hold capacitance 129, the pixel charge being a function of received light intensity.

[0152] A column multiplexer 115 performs pixel selection and electrical pixel binning functions. Gain selection comparators 116 check input signal polarities versus decision thresholds to select one of several gains for a signal amplifier circuit 120 operating as column amplifier. The gain of the signal amplifier circuit 120 is programmed with adjustable input and feedback capacitors C1-C6 to allow different gains. For analog correlated double sampling, the signal amplifier circuit 120 subtracts the sampled pixel reset voltage from the pixel voltage before amplification while rejecting common-mode differences and cancelling amplifier offset. During phases <j)l and <|)2, the pixel reset and amplifier offset are sampled on C3 and C5 and the image data and amplifier offset are sampled on C4 and C6. During phase <|)3, the charge on C3-C6 is moved to the feedback capacitors Cl and C2 representing feedback / hold capacitances 129. The output signals of the signal amplifier circuit 120 are passed to analog -to-digital converters 171 receiving a common ramp signal from a ramp signal generator circuit 172.

[0153] The signal amplifier circuit 120 includes a differential amplifier 128 with differential input and differential output. A first feedback / hold capacitance 129 and a first autozero transistor 130 are electrically connected in parallel between the non-inverting amplifier output and the inverting amplifier input. A second feedback / hold capacitance 129 and a second autozero transistor 130 are electrically connected in parallel between the inverting amplifier output and the non-inverting amplifier input. The signal amplifier circuit 120 runs on a lower positive supply voltage than other parts of the pixel processing circuit 100, in particular, the light receiving pixel part.

[0154] Each of the autozero transistors may be provided with a thick gate dielectric and a high threshold voltage to avoid excessive leakage. It is beneficial to operate the autozero transistors 130 with just enough overdrive to turn them on. Any higher gate voltage consumes more electric power and generates unnecessary 73784

[0155] 20 capacitive coupling to other signals. Also, charge injection at transistor turn-off is made worse by higher switch-on gate voltages.

[0156] A replica circuit 200 as described above tracks the relevant threshold voltages of the autozero transistors 130 and the signal amplifier circuit 120 and provides a ramp reference voltage for generating an autozero switch signal AZSW with appropriate active voltage level. Here, the replica amplifier circuit 220 may be a copy, or scaled copy, of the signal amplifier circuit 120, with input and output shorted. Then the gate voltage circuit 300 derives a voltage to operate the autozero transistor 130 based on the three voltages. In principle, there could be one replica transistor 230, one replica amplifier circuit 220, and the voltage to operate all the autozero transistors 130 could be either a separate one for each of the two, or there could also be simply one voltage for all of the autozero transistors 130, e.g. derived by averaging the voltages from the replica transistor 230.

[0157] FIG. 20 is a diagram illustrating an example in which the CIS is formed by a stacked CMOS CIS having a two-layer structure with a first chip 910 (radiation receiving chip) and a second chip 920 (processing chip). The radiation receiving chip includes at least the photoelectric conversion elements. For example, the radiation receiving chip may include only the photoelectric conversion elements, only the conversion portions of the pixel circuits, or the conversion portions and at least some elements of the PWM portions of the pixel circuits. The image sensor assembly is formed as one sensor by bonding the radiation receiving chip and the processing chip while electrically bringing contact pads on the radiation receiving chip in contact with corresponding contact pads on the processing chip.

[0158] FIG. 21 is a block diagram depicting an example of schematic configuration of a vehicle control system as an example of a system to which the technology according to an embodiment of the present disclosure can be applied.

[0159] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. In the example depicted in FIG. 21, the vehicle control system 12000 includes a driving system control unit 12010, a body system control unit 12020, an outside-vehicle information detecting unit 12030, an in-vehicle information detecting unit 12040, and an integrated control unit 12050. In addition, a microcomputer 12051, a sound / image output section 12052, and a vehiclemounted network interface 12053 are illustrated as a functional configuration of the integrated control unit 12050.

[0160] The driving system control unit 12010 controls the operation of devices related to the driving system of the vehicle in accordance with various kinds of programs. For example, the driving system control unit 12010 functions as a control device for a driving force generating device for generating the driving force of the vehicle, such as an internal combustion engine, a driving motor, or the like, a driving force transmitting mechanism for transmitting the driving force to wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating the braking force of the vehicle, and the like. 73784

[0161] 21

[0162] The body system control unit 12020 controls the operation of various kinds of devices provided to a vehicle body in accordance with various kinds of programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various kinds of lamps such as a headlamp, a backup lamp, a brake lamp, a turn signal, a fog lamp, or the like. In this case, radio waves transmitted from a mobile device as an alternative to a key or signals of various kinds of switches can be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals, and controls a door lock device, the power window device, the lamps, or the like of the vehicle.

[0163] The outside-vehicle information detecting unit 12030 detects information about the outside of the vehicle including the vehicle control system 12000. The outside-vehicle information detecting unit 12030 can be connected with an imaging section 12031. The outside-vehicle information detecting unit 12030 makes the imaging section 12031 imaging an image of the outside of the vehicle and receives the imaged image. Based on the received image, the outside-vehicle information detecting unit 12030 may perform processing of detecting an object such as a human, a vehicle, an obstacle, a sign, a character on a road surface, or the like, or processing of detecting a distance thereto.

[0164] The imaging section 12031 may be or may include an image sensor assembly according to the embodiments of the present disclosure. The light received by the imaging section 12031 may contain visible light and / or invisible light such as infrared rays or the like.

[0165] The in-vehicle information detecting unit 12040 detects information about the inside of the vehicle and may be or may include an image sensor assembly according to the embodiments of the present disclosure. The in-vehicle information detecting unit 12040 is, for example, connected with a driver state detecting section 12041 that detects the state of a driver. The driver state detecting section 12041, for example, includes a camera that includes the solid-stage imaging device and that is focused on the driver. Based on detection information input from the driver state detecting section 12041, the in-vehicle information detecting unit 12040 may calculate a degree of fatigue of the driver or a degree of concentration of the driver or may determine whether the driver is dozing.

[0166] The microcomputer 12051 can calculate a control target value for the driving force generating device, the steering mechanism, or the braking device based on the information about the inside or outside of the vehicle which information is obtained by the outside-vehicle information detecting unit 12030 or the in- vehicle information detecting unit 12040 and output a control command to the driving system control unit 12010. For example, the microcomputer 12051 can perform cooperative control intended to implement functions of an advanced driver assistance system (ADAS) which functions include collision avoidance or shock mitigation for the vehicle, following driving based on a following distance, vehicle speed maintaining driving, a warning of collision of the vehicle, a warning of deviation of the vehicle from a lane, or the like.

[0167] In addition, the microcomputer 12051 can perform cooperative control intended for automatic driving, which makes the vehicle to travel autonomously without depending on the operation of the driver, or the like, by controlling the driving force generating device, the steering mechanism, the braking device, or the 73784

[0168] 22 like on the basis of the information about the outside or inside of the vehicle which information is obtained by the outside-vehicle information detecting unit 12030 or the in-vehicle information detecting unit 12040.

[0169] In addition, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information about the outside of the vehicle which information is obtained by the outsidevehicle information detecting unit 12030. For example, the microcomputer 12051 can perform cooperative control intended to prevent a glare by controlling the headlamp so as to change from a high beam to a low beam, for example, in accordance with the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detecting unit 12030.

[0170] The sound / image output section 12052 transmits an output signal of at least one of a sound or an image to an output device capable of visually or audible notifying information to an occupant of the vehicle or the outside of the vehicle. In the example of FIG. 21, an audio speaker 12061, a display section 12062, and an instrument panel 12063 are illustrated as the output device. The display section 12062 may, for example, include at least one of an on-board display or a head-up display.

[0171] FIG. 22 is a diagram depicting an example of the installation position of the imaging section 12031, wherein the imaging section 12031 may include imaging sections 12101, 12102, 12103, 12104, and 12105.

[0172] The imaging sections 12101, 12102, 12103, 12104, and 12105 are, for example, disposed at positions on a front nose, side-view mirrors, a rear bumper, and a back door of the vehicle 12100 as well as a position on an upper portion of a windshield within the interior of the vehicle. The imaging section 12101 provided to the front nose and the imaging section 12105 provided to the upper portion of the windshield within the interior of the vehicle obtain mainly an image of the front of the vehicle 12100. The imaging sections 12102 and 12103 provided to the side view mirrors obtain mainly an image of the sides of the vehicle 12100. The imaging section 12104 provided to the rear bumper or the back door obtains mainly an image of the rear of the vehicle 12100. The imaging section 12105 provided to the upper portion of the windshield within the interior of the vehicle is used mainly to detect a preceding vehicle, a pedestrian, an obstacle, a signal, a traffic sign, a lane, or the like.

[0173] Incidentally, FIG. 22 depicts an example of photographing ranges of the imaging sections 12101 to 12104. An imaging range 12111 represents the imaging range of the imaging section 12101 provided to the front nose. Imaging ranges 12112 and 12113 respectively represent the imaging ranges of the imaging sections 12102 and 12103 provided to the side view mirrors. An imaging range 12114 represents the imaging range of the imaging section 12104 provided to the rear bumper or the back door. A bird's-eye image of the vehicle 12100 as viewed from above is obtained by superimposing image data imaged by the imaging sections 12101 to 12104, for example.

[0174] At least one of the imaging sections 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging sections 12101 to 12104 may be a stereo camera constituted of a plurality of imaging elements, imaging element having pixels for phase difference detection or may include a ToF module including an image sensor according to the embodiments of the present disclosure. 73784

[0175] 23

[0176] For example, the microcomputer 12051 can determine a distance to each three-dimensional object within the imaging ranges 12111 to 12114 and a temporal change in the distance (relative speed with respect to the vehicle 12100 on the basis of the distance information obtained from the imaging sections 12101 to 12104, and thereby extract, as a preceding vehicle, a nearest three-dimensional object in particular that is present on a traveling path of the vehicle 12100 and which travels in substantially the same direction as the vehicle 12100 at a predetermined speed (for example, equal to or more than 0 km / hour). Further, the microcomputer 12051 can set a following distance to be maintained in front of a preceding vehicle in advance and perform automatic brake control (including following stop control), automatic acceleration control (including following start control), or the like. It is thus possible to perform cooperative control intended for automatic driving that makes the vehicle travel autonomously without depending on the operation of the driver or the like.

[0177] For example, the microcomputer 12051 can classify three-dimensional object data on three-dimensional objects into three-dimensional object data of a two-wheeled vehicle, a standard-sized vehicle, a large-sized vehicle, a pedestrian, a utility pole, and other three-dimensional objects on the basis of the distance information obtained from the imaging sections 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic avoidance of an obstacle. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that the driver of the vehicle 12100 can recognize visually and obstacles that are difficult for the driver of the vehicle 12100 to recognize visually. Then, the microcomputer 12051 determines a collision risk indicating a risk of collision with each obstacle. In a situation in which the collision risk is equal to or higher than a set value and there is thus a possibility of collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or the display section 12062 and performs forced deceleration or avoidance steering via the driving system control unit 12010. The microcomputer 12051 can thereby assist in driving to avoid collision.

[0178] At least one of the imaging sections 12101 to 12104 may be an infrared camera that detects infrared rays. The microcomputer 12051 can, for example, recognize a pedestrian by determining whether there is a pedestrian in imaged images of the imaging sections 12101 to 12104. Such recognition of a pedestrian is, for example, performed by a procedure of extracting characteristic points in the imaged images of the imaging sections 12101 to 12104 as infrared cameras and a procedure of determining whether it is the pedestrian by performing pattern matching processing on a series of characteristic points representing the contour of the object. When the microcomputer 12051 determines that there is a pedestrian in the imaged images of the imaging sections 12101 to 12104, and thus recognizes the pedestrian, the sound / image output section 12052 controls the display section 12062 so that a square contour line for emphasis is displayed so as to be superimposed on the recognized pedestrian. The sound / image output section 12052 may also control the display section 12062 so that an icon or the like representing the pedestrian is displayed at a desired position.

[0179] The example of the vehicle control system to which the technology according to an embodiment of the present disclosure is applicable has been described above. By applying an image sensor according to the 73784

[0180] 24 embodiments of the present disclosure, an early error detection can be implemented, and reliability of the system can be enhanced.

[0181] Additionally, embodiments of the present technology are not limited to the above-described embodiments, but various changes can be made within the scope of the present technology without departing from the gist of the present technology.

[0182] The image sensor according to the present disclosure may be any device used for analyzing and / or processing radiation such as visible light, infrared light, ultraviolet light, and X-rays. For example, an image sensor according to the embodiments may be any electronic device in the field of traffic, the field of home appliances, the field of medical and healthcare, the field of security, the field of beauty, the field of sports, the field of agriculture, the field of image reproduction or the like.

[0183] Specifically, in the field of image reproduction, the image sensor according to the embodiments may be a device for capturing an image to be provided for appreciation, such as a digital camera, a smart phone, or a mobile phone device having a camera function. In the field of traffic, for example, a solid-state imaging device including an image sensor according to the embodiments may be integrated in an in-vehicle sensor that captures the front, rear, peripheries, an interior of the vehicle, etc. for safe driving such as automatic stop, recognition of a state of a driver, or the like, in a monitoring camera that monitors traveling vehicles and roads, or in a distance measuring sensor that measures a distance between vehicles or the like.

[0184] In the field of home appliances, the image sensor according to the embodiments may be integrated in any type of sensor that can be used in devices provided for home appliances such as TV receivers, refrigerators, and air conditioners to capture gestures of users and perform device operations according to the gestures. Accordingly, the image sensor according to the embodiments may be integrated in home appliances such as TV receivers, refrigerators, and air conditioners and / or in devices controlling the home appliances. Furthermore, in the field of medical and healthcare, the image sensor according to the embodiments may be integrated in any type of sensor, e.g., a solid-state image device, provided for use in medical and healthcare, such as an endoscope or a device that performs angiography by receiving infrared light.

[0185] In the field of security, the image sensor according to the embodiments can be integrated in a device provided for use in security, such as a monitoring camera for crime prevention or a camera for person authentication use. Furthermore, in the field of beauty, an image sensor according to the embodiments can be used in a device provided for use in beauty, such as a skin measuring instrument that captures skin or a microscope that captures a probe. In the field of sports, an image sensor according to the embodiments can be integrated in a device provided for use in sports, such as an action camera or a wearable camera for sport use or the like. Furthermore, in the field of agriculture, the image sensor can be used in a device provided for use in agriculture, such as a camera for monitoring the condition of fields and crops.

[0186] The present technology can also be configured as described below:

[0187] [1] An image sensor, comprising: 73784

[0188] 25 a pixel processing circuit (100) configured to convert radiation into digital pixel data, the pixel processing circuit (100) comprising a signal amplifier circuit (120), an autozero transistor (130) configured to temporarily connect a signal input of the signal amplifier circuit (120) with a reset node (135); a replica amplifier circuit (220) and a diode-connected replica transistor (230) with a load path electrically connected in series with a current source (240); and a gate voltage circuit (300) configured to supply an autozero switch signal AZSW to a gate of the autozero transistor (130), wherein an active signal level of the autozero switch signal AZSW for turning on the autozero transistor (130) is a function of a voltage level at a gate of the replica transistor (230) and an output voltage of the replica amplifier circuit (220).

[0189] [2] The image sensor according to [1], wherein at least one of temperature responses, supply voltage dependencies and manufacturing process dependencies of the signal amplifier circuit (120) and the replica amplifier circuit (220) are proportional per design.

[0190] [3] The image sensor according to [1] or [2], wherein at least one of temperature responses, supply voltage dependencies and manufacturing process dependencies of the autozero transistor (130) and the replica transistor (230) are proportional per design.

[0191] [4] The image sensor according to any one of [1] to [3], wherein the current source (240) is controllable.

[0192] [5] The image sensor according to any one of [1] to [4], wherein the active signal level of the autozero switch signal AZSW is higher than a sum of a nominal threshold voltage of the autozero transistor (130) and a highest voltage at the reset node (135).

[0193] [6] The image sensor according to any one of [1] to [5], wherein the reset node (135) is connected to a fixed potential.

[0194] [7] The image sensor according to any one of [1] to [6], wherein the autozero transistor (130) is electrically connected between the signal input and a signal output of the signal amplifier circuit (120).

[0195] [8] The image sensor according to [7], further comprising: a feedback / hold capacitance (129) electrically connected between the signal input and the signal output of the signal amplifier circuit (120).

[0196] [9] The image sensor according to any one of [1] to [8], wherein the gate voltage circuit (300) comprises a measurement circuit (312) configured to obtain digital values of a voltage level at the gate of the replica transistor (230) and the output voltage of the replica amplifier circuit (220), 73784

[0197] 26 a memory circuit (314) configured to store and output process values for a plurality of combinations of different voltage levels at the gate of the replica transistor (230) and the output voltage of the replica amplifier circuit (220), a digital -to-analog converter (318) configured to convert a selected process value output by the memory circuit (314) into a ramp reference voltage REFR, and an autozero circuit (380) configured to generate the autozero switch signal AZSW with an active high level based on the ramp reference voltage REFR.

[0198]

[0010] The image sensor according to [9], wherein the gate voltage circuit (300) further comprises a temperature measurement circuit (316) configured to obtain a digital temperature value of the image sensor, and wherein the memory circuit (314) is configured to store and output process values for a plurality of combinations of different temperatures of the image sensor, different voltage levels at the gate of the replica transistor (230) and different voltage levels of the output voltage of the replica amplifier circuit (220).

[0199]

[0011] The image sensor according to any one of [1] to

[0010] , wherein the signal amplifier circuit (120) comprises a p channel MOSFET (121) and an n channel MOSFET (122) electrically connected in series between a low positive supply voltage VDDL and a supply reference potential GND, wherein a gate of one of the n channel MOSFET (122) and the p channel MOSFET (121) represents the signal input of the signal amplifier circuit (120) and a node between the p channel MOSFET (121) and the n channel MOSFET (122) represents the signal output of the signal amplifier circuit (120).

[0200]

[0012] The image sensor according to any one of [1] to

[0011] , wherein the gate voltage circuit (300) comprises a first voltage coupling element (330) configured to supply a first coupling voltage in series with the current source (240) and the load path of the replica transistor (230), the coupling voltage being a function of the output voltage of the replica amplifier circuit 220.

[0201]

[0013] The image sensor according to any one of [1] to

[0012] , wherein the gate voltage circuit (300) comprises a second voltage coupling element (340) configured to supply a ramp reference voltage REFR, the ramp reference voltage REFR being a function of the gate voltage of the replica transistor (230).

[0202]

[0014] The image sensor according to any one of [1] to

[0013] , wherein the gate voltage circuit (300) comprises an input buffer circuit (325), an input of the input buffer circuit (325) is configured to receive the output voltage of the replica amplifier circuit (220), and an output of the input buffer circuit (325) is electrically connected with the load path of the replica transistor (230). 73784

[0203] 27

[0204]

[0015] The image sensor according to any one of [1] to

[0014] , wherein the gate voltage circuit (300) further comprises an output buffer circuit (335), an input of the output buffer circuit (335) is configured to receive the gate voltage of the replica transistor (230), and an output of the output buffer circuit (335) is electrically connected with an input of an autozero circuit (380).

[0205]

[0016] The image sensor according to any one of [1] to

[0015] , wherein the pixel processing circuit (100) is configured to temporarily store a pixel charge on a feedback / hold capacitance (129) electrically connected between the signal input and a signal output of the signal amplifier circuit (120), the pixel charge being a function of received light intensity.

Claims

7378428CLAIMS1. An image sensor, comprising: a pixel processing circuit configured to convert radiation into digital pixel data, the pixel processing circuit comprising a signal amplifier circuit, an autozero transistor configured to temporarily connect a signal input of the signal amplifier circuit with a reset node; a replica amplifier circuit and a diode-connected replica transistor with a load path electrically connected in series with a current source; and a gate voltage circuit configured to supply an autozero switch signal AZSW to a gate of the autozero transistor, wherein an active signal level of the autozero switch signal AZSW for turning on the autozero transistor is a function of a voltage level at a gate of the replica transistor and an output voltage of the replica amplifier circuit.

2. The image sensor according to claim 1, wherein at least one of temperature responses, supply voltage dependencies and manufacturing process dependencies of the signal amplifier circuit and the replica amplifier circuit are proportional per design.

3. The image sensor according to claim 1, wherein at least one of temperature responses, supply voltage dependencies and manufacturing process dependencies of the autozero transistor and the replica transistor are proportional per design.

4. The image sensor according to claim 1, wherein the current source is controllable.

5. The image sensor according to claim 1, wherein the active signal level of the autozero switch signal AZSW is higher than a sum of a nominal threshold voltage of the autozero transistor and a highest voltage at the reset node.

6. The image sensor according to claim 1, wherein the reset node is connected to a fixed potential.

7. The image sensor according to claim 1, wherein the autozero transistor is electrically connected between the signal input and a signal output of the signal amplifier circuit.

8. The image sensor according to the preceding claim, further comprising: a feedback / hold capacitance electrically connected between the signal input and the signal output of the signal amplifier circuit.

9. The image sensor according to claim 1,7378429 wherein the gate voltage circuit comprises a measurement circuit configured to obtain digital values of a voltage level at the gate of the replica transistor and the output voltage of the replica amplifier circuit, a memory circuit configured to store and output process values for a plurality of combinations of different voltage levels at the gate of the replica transistor and the output voltage of the replica amplifier circuit, a digital-to-analog converter configured to convert a selected process value output by the memory circuit into a ramp reference voltage REFR, and an autozero circuit configured to generate the autozero switch signal AZSW with an active high level based on the ramp reference voltage REFR.

10. The image sensor according to the preceding claim, wherein the gate voltage circuit further comprises a temperature measurement circuit configured to obtain a digital temperature value of the image sensor, and wherein the memory circuit is configured to store and output process values for a plurality of combinations of different temperatures of the image sensor, different voltage levels at the gate of the replica transistor and different voltage levels of the output voltage of the replica amplifier circuit.

11. The image sensor according to claim 1, wherein the signal amplifier circuit comprises a p channel MOSFET and an n channel MOSFET electrically connected in series between a low positive supply voltage VDDL and a supply reference potential GND, wherein a gate of one of the n channel MOSFET and the p channel MOSFET represents the signal input of the signal amplifier circuit and a node between the p channel MOSFET and the n channel MOSFET represents the signal output of the signal amplifier circuit.

12. The image sensor according to claim 1, wherein the gate voltage circuit comprises a first voltage coupling element configured to supply a first coupling voltage in series with the current source and the load path of the replica transistor, the coupling voltage being a function of the output voltage of the replica amplifier circuit.

13. The image sensor according to the claim 1, wherein the gate voltage circuit comprises a second voltage coupling element configured to supply a ramp reference voltage REFR, the ramp reference voltage REFR being a function of the gate voltage of the replica transistor.

14. The image sensor according to claim 1, wherein the gate voltage circuit comprises an input buffer circuit, an input of the input buffer circuit is configured to receive the output voltage of the replica amplifier circuit, and an output of the input buffer circuit is electrically connected with the load path of the replica transistor.

15. The image sensor according to claim 1,30 wherein the gate voltage circuit further comprises an output buffer circuit, an input of the output buffer circuit is configured to receive the gate voltage of the replica transistor, and an output of the output buffer circuit is electrically connected with an input of an autozero circuit.

16. The image sensor according to claim 1, wherein the pixel processing circuit is configured to temporarily store a pixel charge on a feedback / hold capacitance electrically connected between the signal input and a signal output of the signal amplifier circuit, the pixel charge being a function of received light intensity.

Images