Semiconductor device

Abstract

The present invention provides a highly reliable semiconductor device. Provided is a semiconductor device comprising a plurality of transistors, wherein transistors containing an oxide semiconductor in a channel formation region are used as some of the transistors. Thus, a semiconductor device exhibiting little fluctuation in characteristics due to radiation or the like is realized. For example, a latch circuit constituted by transistors that contain silicon in a channel formation region is combined with transistors that contain an oxide semiconductor in a channel formation region, thereby realizing a highly reliable semiconductor device in which soft errors substantially do not occur.

Description

Semiconductor equipment

[0001] One aspect of the present invention relates to a semiconductor device.

[0002] It should be noted that one aspect of the present invention is not limited to the above-mentioned technical field. Examples of technical fields of one aspect of the present invention disclosed herein include semiconductor devices, display devices, light-emitting devices, energy storage devices, memory devices, electronic devices, lighting devices, input devices, input / output devices, methods for driving them, or methods for manufacturing them.

[0003] In recent years, with the increasing volume of data being handled, there has been a demand for storage devices with larger storage capacities. Furthermore, there is a need for highly reliable storage devices that are less prone to data loss due to soft errors. A soft error is a defect in which some of the data stored in a storage device is unintentionally reversed (bit inversion) due to radiation. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, as well as particle radiation such as alpha rays, beta rays, neutrons, protons, heavy ions, and mesons. In particular, radiation believed to originate from outer space is also called "cosmic rays." Soft errors caused by radiation are also known as SEU (Single Event Upset).

[0004] A defect in which a single bit soft error occurs within a single word (a block of data) is called an SBU (Single Bit Upset). A defect in which multiple bits soft errors occur within a single word is called an MBU (Multi Bit Upset).

[0005] Soft errors are easy to recover from because they do not involve physical damage. For example, ECC (Error Check and Correct) memory, which enables error detection and data correction in SBUs, is well known. ECC memory is used in electronic devices where data errors are unacceptable, such as computers used in scientific and technical calculations or in financial institutions.

[0006] On the one hand, it is difficult to correct data in the ECC memory for the MBU. As a countermeasure for the MBU, memory scrubbing that corrects data at the SBU stage is known. Further, Patent Document 1 discloses an ECC memory that divides one word to be stored into a plurality of parts and assigns a correction code (also referred to as a "check bit") to each division to realize a countermeasure for the MBU.

[0007] Tokuhyo Hei 5-508042

[0008] Takaaki Kohda, "High-mobility transparent conductive film", National Institute of Advanced Industrial Science and Technology, AIST Solar Power Generation Research Results Report 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.Pdf>

[0009] The ECC memory calculates a check bit for error correction corresponding to the data for one word, and generates and stores new data for one word (also referred to as a "Hamming code") that combines the data and the check bit. Therefore, the amount of data stored in the physical memory increases, and the substantially usable storage capacity decreases. Further, since the ECC memory verifies the presence or absence of an error bit when reading data, time for error verification is required when reading data. Therefore, the operating speed becomes slow.

[0010] Further, in the ECC memory, when the above-described memory scrubbing is performed, correction and rewriting of the Hamming code including the error bit are performed. At this time, not only the memory cell in which the Hamming code is stored but also the data of other memory cells connected to the same word line as the memory cell need to be rewritten again. Therefore, if the execution frequency of memory scrubbing is increased for the MBU countermeasure, the power consumption increases accordingly.

[0011] One aspect of the present invention aims to provide a semiconductor device with high soft error tolerance. Or, one aspect of the present invention aims to provide a highly reliable semiconductor device. Or, one aspect of the present invention aims to provide a novel semiconductor device.

[0012] Furthermore, the description of the above problems does not preclude the existence of other problems. Other problems can be naturally derived from the description in the specification, drawings, and claims of a person skilled in the art, and it is possible to extract other problems from the description in the specification, drawings, and claims. Furthermore, one aspect of the present invention does not need to solve all of these problems (the above problems and other problems).

[0013] In a semiconductor device containing multiple transistors, using transistors that contain oxide semiconductors in the channel formation region of the semiconductor layer (also called the "channel formation region") (also called "OS transistors") allows for the realization of a semiconductor device with less characteristic fluctuation due to radiation. OS transistors exhibit small fluctuations in electrical characteristics due to radiation irradiation. For example, by combining OS transistors with a latch circuit constructed using transistors that contain silicon in the channel formation region (also called "Si transistors"), a highly reliable semiconductor device with virtually no soft errors can be realized.

[0014] (1) One aspect of the present invention includes a first memory circuit and a second memory circuit, the first memory circuit having a first inverter circuit, a second inverter circuit, a first transistor, and a second transistor, the output of the first inverter circuit being electrically connected to the input of the second inverter circuit and the first terminal of the first transistor, the output of the second inverter circuit being electrically connected to the input of the first inverter circuit and the first terminal of the second transistor, the second memory circuit having third to sixth transistors and a capacitive element, the first terminal of the third transistor being connected to the output of the first inverter circuit and the second The third transistor and the fifth transistor are semiconductor devices in which the channel-forming region contains indium and oxygen. The third transistor is electrically connected to the input of the inverter circuit and the first terminal of the fourth transistor, the first terminal of the fifth transistor is electrically connected to the output of the second inverter circuit, the input of the first inverter circuit and the first terminal of the sixth transistor, the second terminal of the third transistor is electrically connected to the first terminal of the capacitive element and the gate of the sixth transistor, and the second terminal of the fifth transistor is electrically connected to the second terminal of the capacitive element and the gate of the fourth transistor.

[0015] (2) Another aspect of the present invention has a first memory circuit and a second memory circuit. The first memory circuit includes a first inverter circuit, a second inverter circuit, a first transistor, and a second transistor. The output of the first inverter circuit is electrically connected to the input of the second inverter circuit and the first terminal of the first transistor. The output of the second inverter circuit is electrically connected to the input of the first inverter circuit and the first terminal of the second transistor. The second memory circuit includes transistors from the third to the sixth. The first terminal of the third transistor is electrically connected to the output of the first inverter circuit, the input of the second inverter circuit, and the first terminal of the fourth transistor. The first terminal of the fifth transistor is electrically connected to the output of the second inverter circuit, the input of the first inverter circuit, and the first terminal of the sixth transistor. The second terminal of the third transistor is electrically connected to the gate of the sixth transistor. The second terminal of the fifth transistor is electrically connected to the gate of the fourth transistor. Each of the third and fifth transistors is a semiconductor device including an oxide semiconductor in a channel formation region.

[0016] Further, in (1) or (2), each of the first inverter circuit and the second inverter circuit preferably has a transistor including silicon in a channel formation region. Also, each of the fourth transistor and the sixth transistor preferably includes silicon in a channel formation region. Each of the fourth transistor and the sixth transistor can also include an oxide semiconductor in a channel formation region. As an example of the oxide semiconductor, a semiconductor including indium and oxygen can be mentioned. Also, p-type transistors can be used for both the fourth transistor and the sixth transistor. The first memory circuit and the second memory circuit preferably have an overlapping region with each other.

[0017] Furthermore, in (2), it is preferable that the oxide semiconductor contains indium. Also, in (2), it is possible to provide a capacitive element in the semiconductor device. For example, the first terminal of the capacitive element can be electrically connected to the second terminal of the third transistor and the gate of the sixth transistor, and the second terminal of the capacitive element can be electrically connected to the second terminal of the fifth transistor and the gate of the fourth transistor.

[0018] According to one aspect of the present invention, a semiconductor device with high soft error tolerance can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with high reliability can be provided. Alternatively, according to one aspect of the present invention, a novel semiconductor device can be provided.

[0019] Furthermore, the description of the above effects does not preclude the existence of other effects. Other effects can be naturally derived from the description in the specification, drawings, and claims by those skilled in the art, and it is possible to extract other effects from the description in the specification, drawings, and claims. Furthermore, one aspect of the present invention does not need to have all of these effects (the above effects and other effects).

[0020] Figures 1A and 1B illustrate semiconductor devices. Figures 2A and 2B illustrate semiconductor devices. Figures 3A and 3B illustrate semiconductor devices. Figures 4A and 4B illustrate semiconductor devices. Figure 5 is an illustration of a semiconductor device. Figures 6A, 6B, and 6C illustrate semiconductor devices. Figures 7A and 7B illustrate semiconductor devices. Figure 8 is an illustration of a semiconductor device. Figure 9 is an illustration of a semiconductor device. Figure 10 is an illustration of a semiconductor device. Figure 11 is an illustration of a semiconductor device. Figure 12 is an illustration of a semiconductor device. Figures 13A and 13B illustrate semiconductor devices. Figure 14 is an illustration of a semiconductor device. Figure 15 is an illustration of a semiconductor device. Figure 16 is an illustration of a semiconductor device. Figure 17 is an illustration of a semiconductor device. Figure 18 is a timing chart illustrating the operation of a semiconductor device. Figure 19 is an illustration illustrating the operation of a semiconductor device. Figure 20 is an illustration illustrating the operation of a semiconductor device. Figure 21 is an illustration illustrating the operation of a semiconductor device. Figure 22 is an illustration illustrating the operation of a semiconductor device. Figure 23 is an illustration illustrating the operation of a semiconductor device. Figure 24 is a timing chart illustrating the operation of a semiconductor device. Figure 25 is a diagram illustrating the operation of a semiconductor device. Figure 26 is a diagram illustrating the operation of a semiconductor device. Figure 27 is a diagram illustrating the operation of a semiconductor device. Figure 28 is a diagram illustrating the operation of a semiconductor device. Figure 29 is a diagram illustrating a semiconductor device. Figures 30A, 30B, 30C, and 30D are diagrams illustrating a semiconductor device. Figure 31 is a diagram illustrating an example configuration of a semiconductor device. Figures 32A and 32B are diagrams illustrating an example configuration of a semiconductor device. Figures 33A, 33B, and 33C are diagrams illustrating an example configuration of a transistor. Figures 34A, 34B, and 34C are diagrams illustrating an example configuration of a transistor. Figures 35A and 35B are diagrams illustrating an example configuration of a transistor. Figure 36 is a diagram illustrating an example configuration of a semiconductor device. Figures 37A and 37B are diagrams illustrating the carrier concentration dependence of hole mobility. Figure 37C is a cross-sectional view illustrating an indium oxide film.Figure 38 is a diagram showing various storage devices in hierarchical order. Figures 39A and 39B are diagrams showing examples of electronic components. Figures 40A, 40B, 40C, 40D, 40E, 40F, 40G, 40H, 40I, and 40J are diagrams illustrating examples of electronic equipment. Figures 41A, 41B, 41C, 41D, and 41E are diagrams illustrating examples of electronic equipment. Figures 42A, 42B, and 42C are diagrams illustrating examples of electronic equipment. Figure 43 is a diagram showing an example of space equipment.

[0021] The embodiments will be described below with reference to the drawings. However, it will be readily apparent to those skilled in the art that the embodiments can be implemented in many different ways, and their form and details can be modified in various ways without departing from the spirit and scope thereof. Accordingly, the present invention shall not be construed as being limited to the contents of the following embodiments.

[0022] In this specification, a semiconductor device refers to a device that utilizes semiconductor properties, including circuits containing semiconductor elements (transistors, diodes, photodiodes, etc.), devices having such circuits, etc. It also refers to any device that can function by utilizing semiconductor properties. For example, integrated circuits, chips equipped with integrated circuits, and electronic components with chips housed in packages are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, and electronic devices are themselves semiconductor devices, and may also contain semiconductor devices.

[0023] In the drawings and other illustrations relating to this specification, the size, layer thickness, or area may be exaggerated for clarity. Therefore, the size or aspect ratio is not necessarily limited to those shown. Furthermore, the drawings are schematic representations of ideal examples and are not limited to the shapes or values ​​shown in the drawings.

[0024] In the configuration of the embodiment of the invention, the same reference numerals are used in common across different drawings for the same part or parts having similar functions, and repeated explanations may be omitted. Also, when referring to similar functions, the same hatching pattern may be used, and no reference numerals may be assigned. Furthermore, in order to make the drawings easier to understand, the description of some components may be omitted in perspective views or plan views, etc.

[0025] In this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion of constituent elements. Therefore, they do not limit the number of constituent elements, nor do they limit the order of the constituent elements. For example, a constituent element referred to as "first" in one embodiment of this specification may be referred to as "second" in another embodiment or in the claims. Also, for example, a constituent element referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0026] In this specification, phrases indicating arrangement such as "above," "below," "upward," or "downward" are sometimes used for convenience to explain the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each component is depicted. Therefore, the phrases described in the specification are not limited to those explained and can be appropriately rephrased depending on the situation. For example, the expression "insulator located on the upper surface of the conductor" can be rephrased as "insulator located on the lower surface of the conductor" by rotating the orientation of the drawing shown by 180 degrees.

[0027] Furthermore, the terms "above" and "below" do not limit the positional relationship of the components to being directly above or below each other and in direct contact. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude cases where other components are included between insulating layer A and electrode B.

[0028] In this specification, terms such as "overlapping" do not limit the stacking order or other states of the constituent elements. For example, the expression "electrode B overlapping insulating layer A" does not exclude not only the state in which electrode B is formed on top of insulating layer A, but also the state in which electrode B is formed below insulating layer A, or the state in which electrode B is formed to the right (or left) of insulating layer A, etc.

[0029] In this specification, the terms "adjacent" and "proximity" are not limited to direct contact between components. For example, the expression "electrode B adjacent to insulating layer A" does not require that insulating layer A and electrode B be formed in direct contact, and does not exclude cases where other components are included between insulating layer A and electrode B.

[0030] In this specification, terms such as "film" and "layer" can be interchanged as needed. For example, the term "conductive layer" may be changed to the term "conductive film." Or, for example, the term "insulating film" may be changed to the term "insulating layer." Alternatively, depending on the circumstances, terms such as "film" and "layer" can be omitted and replaced with other terms. For example, the term "conductive layer" or "conductive film" may be changed to the term "conductor." Or, the term "conductor" may be changed to the term "conductive layer" or "conductive film." Alternatively, for example, the term "insulating layer" or "insulating film" may be changed to the term "insulator." Or, the term "insulator" may be changed to the term "insulating layer" or "insulating film."

[0031] Voltage often refers to the potential difference between a given potential and a reference potential (e.g., ground potential or source potential). Therefore, voltage and potential are often interchangeable. In this specification, unless otherwise specified, voltage and potential are considered interchangeable.

[0032] In this specification, terms such as "electrode," "wiring," and "terminal" do not functionally limit these components. For example, "electrode" may be used as part of "wiring," and vice versa. Furthermore, the terms "electrode" or "wiring" include cases where multiple "electrodes" or "wiring" are formed as a single unit. Similarly, for example, "terminal" may be used as part of "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" also includes cases where multiple "electrodes," "wiring," or "terminals" are formed as a single unit. Therefore, for example, an "electrode" can be part of "wiring" or a "terminal," and for example, a "terminal" can be part of "wiring" or an "electrode." In addition, terms such as "electrode," "wiring," and "terminal" may be replaced with terms such as "region" depending on the context.

[0033] In this specification, terms such as "wiring," "signal line," and "power line" can be interchanged with each other depending on the circumstances. For example, the term "wiring" may be changed to the term "signal line." Similarly, the term "wiring" may be changed to the term "power line." The reverse is also true; terms such as "signal line" and "power line" may be changed to the term "wiring." Terms such as "power line" may be changed to the term "signal line." Similarly, terms such as "signal line" may be changed to the term "power line." In addition, the term "potential" applied to the wiring may be changed to the term "signal," depending on the circumstances. Similarly, terms such as "signal" may be changed to the term "potential."

[0034] In this specification, one of the sources or drains of a transistor may be referred to as the "first terminal of the transistor," and the other of the sources or drains of a transistor may be referred to as the "second terminal of the transistor."

[0035] Generally, "capacitance" has a configuration in which two electrodes face each other with an insulator (dielectric) in between. In this specification, the term "capacitive element" includes the case of the aforementioned "capacitance." That is, in this specification, the term "capacitive element" includes cases in which two electrodes face each other with an insulator in between, cases in which two wires face each other with an insulator in between, or cases in which two wires are arranged with an insulator in between. In addition, in this specification, one electrode of a capacitive element may be referred to as the "first terminal of the capacitive element," and the other electrode may be referred to as the "second terminal of the capacitive element."

[0036] In this specification, "parallel" means a state in which two lines are positioned at an angle of -10° or more and 10° or less. Therefore, the case of -5° or more and 5° or less is also included. Furthermore, "approximately parallel" or "roughly parallel" means a state in which two lines are positioned at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" means a state in which two lines are positioned at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included. Furthermore, "approximately perpendicular" or "roughly perpendicular" means a state in which two lines are positioned at an angle of 60° or more and 120° or less.

[0037] In this specification, when count values ​​and measured values ​​are referred to as "identical," "same," "equal," or "uniform" (including synonyms thereof), unless otherwise explicitly stated, this shall include an error margin of plus or minus 10%.

[0038] Furthermore, in this specification, the high power supply potential VDD (hereinafter also simply referred to as "VDD") refers to a power supply potential that is higher than the low power supply potential VSS. The low power supply potential VSS (hereinafter also simply referred to as "VSS") refers to a power supply potential that is lower than the high power supply potential VDD. The ground potential GND (hereinafter also simply referred to as "GND") can also be used as VDD or VSS. For example, if VDD is GND, then VSS is at a lower potential than GND, and if VSS is GND, then VDD is at a higher potential than GND.

[0039] In this specification, the "on state" of a transistor means that the source and drain of the transistor are conductive (a state in which current can be conducted). The "off state" of a transistor means that the source and drain of the transistor are non-conductive (a state in which it can be considered electrically blocked).

[0040] Furthermore, in this specification, "on-current" refers to the current that flows between the source and drain when the transistor is in the ON state. "Off-current" refers to the current that flows between the source and drain when the transistor is in the OFF state.

[0041] In this specification, potential H is the potential that turns an n-channel transistor (also called an "n-type transistor") on, and the potential that turns a p-channel transistor (also called a "p-type transistor") off. Similarly, potential L is the potential that turns an n-type transistor off, and the potential that turns a p-type transistor on. Therefore, potential H is higher than potential L. Potential H may be equal to VDD, but does not represent a specific potential. Potential L may be equal to VSS, but does not represent a specific potential.

[0042] For example, if it is stated that "potential L is supplied" to each of two wires, the potential L supplied to each wire does not necessarily have to be at the same potential. Similarly, if it is stated that "potential H is supplied" to each of two wires, the potential H supplied to each wire does not necessarily have to be at the same potential.

[0043] Furthermore, unless otherwise specified, the transistors described herein are enhancement-type (normally-off) n-type transistors. A high threshold voltage (also called "Vth") of a transistor means a large absolute value of Vth. Conversely, a low Vth of a transistor means a small absolute value of Vth.

[0044] Furthermore, in drawings and other diagrams, to clearly indicate the potential of wiring, electrodes, etc., the letter "H" indicating a high potential or "L" indicating a low potential may be added adjacent to the wiring, electrodes, etc. Also, when a potential change occurs in wiring, electrodes, etc., the letter "H" or "L" may be enclosed in a box. In addition, if a transistor is in the off state, the symbol "×" may be superimposed on the transistor. Arrows indicating the direction of current flow may also be added.

[0045] In drawings and other illustrations relating to this specification, arrows indicating the X, Y, and Z directions may be included. In this specification, the "X direction" refers to the direction along the X-axis, and unless explicitly stated, the forward and reverse directions may not be distinguished. The same applies to the "Y direction" and "Z direction." Furthermore, the X, Y, and Z directions are directions that intersect each other. For example, the X, Y, and Z directions are directions that are orthogonal to each other. In this specification, one of the X, Y, or Z directions may be referred to as the "first direction" or "first direction." Another may be referred to as the "second direction" or "second direction." The remaining one may be referred to as the "third direction" or "third direction."

[0046] In this specification, when the same symbol is used for multiple elements, and especially when it is necessary to distinguish them, the symbols may be accompanied by identifying symbols such as "A", "b", "_1", "[n]", and "[m,n]".

[0047] Furthermore, one aspect of the present invention includes a configuration in which at least one of the gates, sources, or drains of one or more transistors is either unconnected to anything or connected to any node. Also, one aspect of the present invention includes a configuration in which one or more wires have no input or have any signal or voltage input to them.

[0048] In this specification, "connection" includes, for example, "electrical connection." When "electrical connection" is used to define the connection relationship of circuit elements as a physical object, "electrical connection" includes, for example, "direct connection" and "indirect connection." "A and B are directly connected" means, for example, that A and B are connected without the use of a circuit element (e.g., a transistor or a switch; however, wiring is not a circuit element) between them. On the other hand, "A and B are indirectly connected" means, for example, that A and B are connected through one or more circuit elements.

[0049] Here, when we define "A and B are indirectly connected," it refers to the following type of connection, as an example: That is, assuming the circuit is operating, if there are times during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then such a circuit can be defined as having "A and B indirectly connected" as a physical object. Even if there are times when no electrical signals are exchanged or potential interactions occur between A and B, if there are times during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then it can be defined as having "A and B indirectly connected." Note that "A and B are indirectly connected" is a definition of the connection relationship between circuit elements as a physical object. Therefore, for example, even if no power supply voltage is supplied to the circuit and the circuit is not operating, the circuit can still be defined as having "A and B indirectly connected" as a physical object (however, as an example, this is limited to cases where, when power supply voltage is supplied to the circuit and the circuit is operating, electrical signals are exchanged or potential interactions occur between A and B during the circuit's operation).

[0050] The following are specific examples of "indirect connections." First, an example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. Another example of a case where "A and B are indirectly connected" is when A and B are connected via one or more switches. When "A and B are indirectly connected," assuming the circuit is operating, one transistor between A and B will be in an ON state, conducting state, or a state in which current can flow at least once. Note that when "A and B are indirectly connected," this includes the case where one transistor between A and B is in an OFF state or a non-conducting state. When "A and B are indirectly connected" and multiple transistors are connected between A and B, assuming the circuit is operating, each of the multiple transistors between A and B will be in an ON state, conducting state, or a state in which current can flow at least once. In other words, when "A and B are indirectly connected," it is not necessary for all of the transistors to be in an ON state, a conducting state, or a state in which current can flow simultaneously. Therefore, when "A and B are indirectly connected," it includes cases where the transistors between A and B are in an OFF state or a non-conducting state at the same time or at different times. As another example, when A and C are connected via the source and drain of transistor TrP, and B and C are connected via the source and drain of transistor TrQ, it can be defined as "A and C are indirectly connected," "B and C are indirectly connected," or "A and B are indirectly connected." However, as will be discussed later, if a constant potential V is supplied to C from a power supply or GND, it can be said that "A and C are indirectly connected," or "B and C are indirectly connected," but it cannot be said that "A and B are indirectly connected."

[0051] Having shown examples of cases where a connection can be considered "indirect" and cases where it cannot, let's look at another example of a case where a connection cannot be considered "indirect." Even if electrical signals are exchanged or potential interactions occur between A and B during the operation of the circuit, there are exceptional cases where it cannot be said that "A and B are indirectly connected." An example of such an exceptional case is when A and B are connected via an insulator. In other words, when A and B are connected via an insulator, it cannot be said that "A and B are indirectly connected." A specific example of when A and B are connected via an insulator is when a capacitive element is connected between A and B. Another example of when A and B are connected via an insulator is when a transistor gate insulating film is interposed between A and B. In this case, it cannot be said that "A (the gate of the transistor) and B (the source or drain of the transistor) are indirectly connected."

[0052] Another example of a situation where it cannot be said that "A and B are indirectly connected" is when there is no timing for the exchange of electrical signals or potential interaction between A and B. For example, if multiple transistors are connected via their sources and drains in the path from A to B, and a constant potential V is supplied to the nodes between the transistors from a power source or GND, then it cannot be said that "A and B are indirectly connected," but it can be said that "A and V are indirectly connected," or "B and V are indirectly connected." Furthermore, if A and C are connected via the source and drain of transistor TrP, and B and C are connected via the source and drain of transistor TrQ, and a constant potential V is supplied to C from a power source or GND, then it cannot be said that "A and B are indirectly connected," but it can be said that "A and C are indirectly connected," or "B and C are indirectly connected."

[0053] As shown above, we have provided an example of "indirect connection." As an example, the provisions for "indirect connection" are included in the provisions for "electrical connection," so if "A and B are indirectly connected," then "A and B are electrically connected."

[0054] Next, let's look at specific examples of "direct connection." An example of "A and B being directly connected" is when A and B are connected without any circuit elements in between. If A and B are connected to a power source that supplies a constant potential V, or to GND, without any circuit elements in between, then we can say that "A and B are directly connected," "A and V are directly connected," or "B and V are directly connected." Even if A (or B) is connected to a constant potential V via the source and drain of a transistor, we can still say that "A and B are directly connected." However, since A and V, or B and V, are connected via the source and drain of a transistor, they cannot be considered directly connected, and we can say that "A and V are indirectly connected," or "B and V are indirectly connected."

[0055] As shown above, an example of "direct connection" has been given, but as an example, since the provisions for "direct connection" are included in the provisions for "electrical connection," if "A and B are directly connected," then "A and B are electrically connected."

[0056] (Embodiment 1) A memory cell 100 according to one aspect of the present invention will be described. Figure 1A is a diagram illustrating an example of the configuration of a memory cell 100, which is a type of semiconductor device.

[0057] The memory cell 100 has a first memory circuit 110 and a second memory circuit 120. Each of the first memory circuit 110 and the second memory circuit 120 has the function of holding 1 bit of data. In this embodiment, the data held by the first memory circuit 110 may be referred to as "first data". Also, the data held by the second memory circuit 120 may be referred to as "second data".

[0058] The first memory circuit 110 is connected to wiring 101, wiring 102, and wiring 103. The second memory circuit 120 is connected to wiring 104 and wiring 105.

[0059] <<Circuit Configuration Examples>> Next, a detailed circuit configuration example of the memory cell 100 will be described. In the following, circuit configuration examples of memory cells 100A to 100G will be described as memory cells 100.

[0060] <Circuit Configuration Example 1> Figure 1B shows an example of the circuit configuration of the memory cell 100A. The memory cell 100A has a first memory circuit 110 and a second memory circuit 120a, which is a type of second memory circuit 120.

[0061] The first memory circuit 110 includes an inverter circuit INV1, an inverter circuit INV2, a transistor Tr11, and a transistor Tr12. The output of inverter circuit INV1 is connected to the input of inverter circuit INV2, and the output of inverter circuit INV2 is connected to the input of inverter circuit INV1.

[0062] One of the sources or drains of transistor Tr11 is connected to the output of inverter circuit INV1 and the input of inverter circuit INV2. The other of the sources or drains of transistor Tr11 is connected to wiring 101. One of the sources or drains of transistor Tr12 is connected to the output of inverter circuit INV2 and the input of inverter circuit INV1. The other of the sources or drains of transistor Tr12 is connected to wiring 102. The gates of transistor Tr11 and transistor Tr12 are connected to wiring 103. The first memory circuit 110 functions as a latch circuit.

[0063] In this specification, the region where either the source or drain of transistor Tr11, the output of inverter circuit INV1, and the input of inverter circuit INV2 are connected and always at the same potential is referred to as "node Q". Also, in this specification, the region where either the source or drain of transistor Tr12, the output of inverter circuit INV2, and the input of inverter circuit INV1 are connected and always at the same potential is referred to as "node QB".

[0064] The second memory circuit 120a includes transistors Tr21 to Tr24 and a capacitive element Cs. One of the sources or drains of transistor Tr21 is connected to the output of inverter circuit INV1, the input of inverter circuit INV2, one of the sources or drains of transistor Tr11, and one of the sources or drains of transistor Tr22. The other of the sources or drains of transistor Tr21 is connected to the gate of transistor Tr24 and one of the terminals of the capacitive element Cs.

[0065] One of the sources or drains of transistor Tr23 is connected to the output of inverter circuit INV2, the input of inverter circuit INV1, one of the sources or drains of transistor Tr12, and one of the sources or drains of transistor Tr24. The other of the sources or drains of transistor Tr23 is connected to the gate of transistor Tr22 and the other terminal of the capacitive element Cs. The gates of transistor Tr21 and transistor Tr23 are connected to wiring 104.

[0066] In Figure 1B and other diagrams, the region where the source or drain of transistor Tr21, the gate of transistor Tr24, and one terminal of the capacitive element Cs are connected and always at the same potential is referred to as "node SN". In this specification and other documents, the region where the source or drain of transistor Tr23, the other terminal of the capacitive element Cs, and the gate of transistor Tr22 are connected and always at the same potential is referred to as "node SNB".

[0067] Additionally, signal BL is supplied to wiring 101, and signal BLB, which is the inverted signal of signal BL, is supplied to wiring 102. Signal WL is supplied to wiring 103. Signal SET is supplied to wiring 104. Signal PL is supplied to wiring 105.

[0068] It is preferable to use single-crystal semiconductors, polycrystalline semiconductors, microcrystalline semiconductors, or amorphous semiconductors, either individually or in combination, as the semiconductor layer on which the transistor channels of the first memory circuit 110 are formed. As semiconductor materials, for example, silicon, germanium, etc., can be used. Alternatively, compound semiconductors such as silicon germanium, silicon carbide, or gallium arsenide can be used.

[0069] More specifically, for example, Si transistors are used as inverter circuits INV1, INV2, transistor Tr11, and transistor Tr12 included in the first memory circuit 110. In particular, it is preferable to use Si transistors made of single-crystal or polycrystalline semiconductors for the semiconductor in which the channel is formed. Si transistors made of single-crystal or polycrystalline semiconductors have high operating speed and are relatively easy to manufacture, resulting in excellent productivity. Memory circuits or memory elements using Si transistors (also called "Si memory") have high data read speed and data write speed. On the other hand, Si memory, such as SRAM, is prone to soft errors. That is, it has low soft error tolerance.

[0070] It is preferable to use n-type transistors as transistors Tr11 and Tr12. N-type transistors can conduct a larger on-current than p-type transistors. Therefore, by using n-type transistors as transistors Tr11 and Tr12, the operating speed of the first memory circuit 110 can be increased. Therefore, the operating speed of the memory cell 100A can be increased.

[0071] As shown in Figure 2A, it is also possible to use p-type transistors as transistors Tr11 and Tr12 in the first memory circuit 110. Furthermore, as shown in Figure 2B, it is also possible to use p-type transistors as transistors Tr22 and Tr24 in the second memory circuit 120a. P-type transistors are easier to implement as normally-off transistors than n-type transistors. Using p-type transistors as transistors Tr11 and Tr12 reduces the leakage current between node Q and wiring 101 and between node QB and wiring 102. Using p-type transistors as transistors Tr22 and Tr24 reduces the leakage current between node Q and wiring 105 and between node QB and wiring 105. Therefore, the power consumption of memory cell 100A can be reduced. In addition, because it becomes less susceptible to the influence of leakage current from other memory cells 100A connected to the same wiring 101 and the same wiring 102, the operation of memory cell 100A becomes more stable and its reliability is improved. Therefore, the operation of the semiconductor device using the memory cell 100A becomes more stable and its reliability is improved.

[0072] Of the transistors Tr21 to Tr24 included in the second memory circuit 120a, at least transistors Tr21 and Tr23 are OS transistors. Although OS transistors operate slower than Si transistors, their bandgap is 2 eV or more, resulting in significantly lower off-current compared to Si transistors. Therefore, data written to nodes SN and SNB of the second memory circuit 120 can be retained for a long period of time. Generally, OS transistors are often n-type transistors. Therefore, in this specification, OS transistors are described as n-type transistors.

[0073] Furthermore, OS transistors operate stably even in high-temperature environments and exhibit minimal characteristic fluctuations. For example, the off-current hardly increases even in high-temperature environments. Specifically, the off-current hardly increases even at ambient temperatures between room temperature and 200°C. Also, the on-current does not easily decrease even in high-temperature environments. Therefore, memory circuits or memory elements using OS transistors (also called "OS memory") operate stably even in high-temperature environments and provide high reliability. By using an OS transistor in the second memory circuit 120a, the second memory circuit 120a can function as an OS memory.

[0074] Furthermore, OS memory exhibits minimal fluctuations in its electrical properties due to radiation exposure such as cosmic rays. In other words, it functions as a memory element that is less susceptible to soft errors caused by radiation and has high soft error tolerance. Therefore, by enabling the second memory circuit 120a to function as OS memory, the reliability of the memory cell 100A can be improved.

[0075] A memory cell 100A according to one aspect of the present invention is a memory element that includes Si memory and OS memory. By combining a Si memory with high operating speed and an OS memory with high reliability, a memory cell that is fast and highly reliable can be realized. Therefore, a storage device that is fast and highly reliable can be realized. In other words, a memory cell that is highly reliable and has low output impedance can be realized. Because the memory cell 100A according to one aspect of the present invention has low output impedance, it can stably operate a load connected to the memory cell 100A.

[0076] Furthermore, the memory cell 100A can be configured by overlapping the first memory circuit 110 and the second memory circuit 120a. By overlapping the first memory circuit 110 and the second memory circuit 120a, the occupied area of ​​the memory cell 100A can be reduced. In other words, the occupied area of ​​the memory cell 100A can be reduced by having overlapping regions between the first memory circuit 110 and the second memory circuit 120a.

[0077] Figure 3A shows a perspective conceptual diagram of the memory cell 100A. Figure 3B is a perspective conceptual diagram for explaining the circuit configuration of the memory cell 100A in more detail. The element layer 10 has a first memory circuit 110. The element layer 20 has a second memory circuit 120a. For example, a single-crystal silicon substrate can be used as the element layer 10, and the first memory circuit 110 can be formed on the silicon substrate. By forming the channel formation region of the Si transistor included in the first memory circuit 110 on the silicon substrate, a single-crystal Si transistor with a single-crystal semiconductor in the channel formation region and a high operating speed can be formed. Also, Figure 3B shows an example in which wirings 101 to 104 are provided on the element layer 10, but is not limited to this. Wirings 101 to 104 can also be provided on the element layer 20. It is also possible to provide some of the wirings 101 to 104 on the element layer 10 and some on the element layer 20.

[0078] Furthermore, for example, an SOI (Silicon on Insulator) substrate can be used as the element layer 10. As an SOI substrate, SIMOX (Separation by Improved Oxygen) substrates can be used, which are formed by implanting oxygen ions into a mirror-polished wafer and then heating it at a high temperature to form an oxide layer to a certain depth from the surface and eliminate defects that have formed in the surface layer; smart cut methods that cleave a semiconductor substrate by utilizing the growth of minute voids formed by hydrogen ion implantation through heat treatment; and ELTRAN (Registered Trademark: Epitaxial Layer Transfer) methods. Si transistors fabricated using an SOI substrate have reduced parasitic capacitance and can achieve high-speed operation.

[0079] Furthermore, since OS transistors can be formed as a type of thin-film transistor, they can be easily superimposed on the element layer 10 as element layer 20. In addition, as mentioned above, OS transistors operate stably even in high-temperature environments and exhibit little characteristic variation. For this reason, even if a second memory circuit 120 including an OS transistor is superimposed on a first memory circuit 110 including a Si transistor, the second memory circuit 120 is less affected by the heat generated by the first memory circuit 110. Thus, high reliability can be obtained.

[0080] The semiconductor layer compositions used for transistors Tr21 through Tr24 can all be the same, but they can also be different. For example, it is possible to use a semiconductor layer with a first composition for transistors Tr21 and Tr23, and a semiconductor layer with a second composition for transistors Tr21 and Tr23.

[0081] When the second memory circuit 120 is superimposed on the first memory circuit 110, it is preferable to use transistors that exhibit less fluctuation in electrical characteristics due to radiation irradiation than the transistors constituting the inverter circuit INV1 and the transistors constituting the inverter circuit INV2, as transistors Tr21 and Tr23. For example, it is preferable to use OS transistors containing indium in the semiconductor layer as transistors Tr21 and Tr23. Alternatively, it is more preferable to use OS transistors containing indium and zinc in the semiconductor layer. Or, it is even more preferable to use OS transistors containing element M in addition to indium and zinc in the semiconductor layer. For example, gallium can be used as element M. In this case, indium gallium zinc oxide can be used as the semiconductor layer. Element M will be described in detail later.

[0082] Furthermore, when the second memory circuit 120 is superimposed on the first memory circuit 110, it is preferable to use OS transistors as transistors Tr22 and Tr24, which have a higher field-effect mobility than transistors Tr21 and Tr23. For example, it is preferable to use OS transistors that contain indium in the semiconductor layer. It is also preferable to increase the ratio of the number of indium atoms to the sum of the number of atoms of all metal elements contained in the semiconductor layer. As an example, indium oxide (also called "indium oxide") can be used.

[0083] For example, Si transistors can be used as transistors Tr22 and Tr24. Si transistors often have a faster operating speed than OS transistors. By using Si transistors for transistors Tr22 and Tr24, the charge supply capability to nodes Q and QB can be increased. Therefore, the time required to correct soft errors can be shortened. In other words, the recovery time from soft errors can be shortened. By shortening the recovery time from soft errors, the operating speed of the memory cell 100A can be improved, as can the reliability of the memory cell 100A.

[0084] By determining the composition of the semiconductor layer of each transistor according to the required characteristics for each of the multiple transistors constituting the memory cell 100A, the performance of the memory cell 100A can be efficiently improved. Furthermore, the reliability of the memory cell 100A can be enhanced.

[0085] When, for example, Si transistors are used as transistors Tr22 and Tr24, it is possible to provide transistors Tr22 and Tr24 in the element layer 10 in the same way as the first memory circuit 110. Figure 4A is a perspective conceptual diagram when n-type transistors are used for transistors Tr22 and Tr24, and Figure 4B is a perspective conceptual diagram when p-type transistors are used for transistors Tr22 and Tr24.

[0086] By providing transistors Tr22 and Tr24 in the element layer 10, spatial space is created in the element layer 20, allowing for a larger transistor size for transistors Tr21 and Tr23 provided in the element layer 20. For example, the channel width of transistors Tr21 and Tr23 can be increased, and the on-current of transistors Tr21 and Tr23 can be increased. By increasing the on-current of transistors Tr21 and Tr23, the data writing time to node SN and node SNB can be shortened. Therefore, the operating speed of memory cell 100A can be increased.

[0087] Furthermore, it is preferable that the channel widths of transistors Tr21 and Tr23 are larger than, for example, the channel widths of the transistors constituting inverter circuits INV1 and INV2. By increasing the channel widths of transistors Tr21 and Tr23, the on-current of transistors Tr21 and Tr23 can be increased. That is, the time required to write data to nodes SN and SNB can be shortened. Therefore, the operating speed of memory cell 100A can be increased.

[0088] If the parasitic capacitances of nodes SN and SNB are sufficiently large, the formation of the capacitive element Cs may be omitted (see Figure 5). For example, if the gate capacitances of transistors Tr22 and Tr24 are sufficiently large, the formation of the capacitive element Cs can be omitted.

[0089] Furthermore, transistors having back gates can be used in the transistors constituting the memory cell 100A. In particular, it is preferable to use transistors having back gates for transistors Tr21 to Tr24. Figure 6A shows an example of a circuit configuration of memory cell 100A using transistors having back gates for transistors Tr11, Tr12, and Tr21 to Tr24. Figures 6B and 6C show circuit symbols for transistors having back gates.

[0090] The back gate of a transistor can function similarly to the gate. In the configuration shown in the circuit symbol in Figure 6B, the back gate can be at the same potential as the gate, or it can be at a reference potential, GND, or any other potential. By changing the potential of the back gate independently of the gate, the threshold voltage of the transistor can be changed. In the configuration shown in the circuit symbol in Figure 6C, the gate and back gate are connected, so they are always at the same potential. By supplying the potential that turns the transistor ON to both the gate and the back gate, the ON current can be increased compared to supplying it to only one of them.

[0091] Furthermore, by providing a back gate, a function is obtained that prevents electric fields generated outside the transistor from acting on the channel formation region (particularly an electric field shielding function against static electricity). Therefore, by providing a back gate, the transistor can be operated stably. In addition, the reliability of the semiconductor device containing the transistor can be improved. Moreover, by providing a back gate in addition to the gate, the variation in characteristics between multiple transistors can be reduced. Note that the electric field shielding effect can be obtained even if one or both of the gate and back gate are electrically floating (also called a "floating state"), but the effect can be further enhanced by supplying potential to the gate and back gate.

[0092] The operation example of memory cell 100A will be explained in detail later.

[0093] <Circuit Configuration Example 2> It is also possible to configure the second memory circuit 120 so that it is not connected to the wiring 104. Figure 7A shows an example of the configuration of the memory cell 100 when the second memory circuit 120 is not connected to the wiring 104 but is connected to the wiring 103. Figure 7B shows an example of the circuit configuration of memory cell 100B, which is a type of memory cell 100. Figure 8 shows a perspective conceptual diagram to explain the circuit configuration of memory cell 100B in more detail.

[0094] Memory cell 100B is a modified version of memory cell 100A. To reduce repetition, a detailed explanation of memory cell 100B is omitted. For parts of the configuration of memory cell 100B that are not explained, the explanation of memory cell 100A can be used as a reference.

[0095] Memory cell 100B has a configuration in which wiring 104 is removed from the multiple wirings that connect to memory cell 100A. In memory cell 100B, the gates of transistors Tr21 and Tr23 of the second memory circuit 120a are connected to wiring 103.

[0096] In memory cell 100B, the formation of wiring 104 can be eliminated. By not providing wiring 104, the density of memory cells can be increased. In other words, the storage capacity per unit area can be increased.

[0097] <Circuit Configuration Example 3> As another example of the configuration of the memory cell 100, Figure 9 shows a circuit configuration example of memory cell 100C. Also, Figure 10 shows a perspective conceptual diagram to explain the circuit configuration of memory cell 100C in more detail.

[0098] Memory cell 100C is a modified version of memory cell 100A. To reduce repetition, a detailed explanation of memory cell 100C is omitted. For parts of the configuration of memory cell 100C that are not explained, refer to the explanation of memory cell 100A, etc.

[0099] The memory cell 100C includes a first memory circuit 110 and a second memory circuit 120b, which is a type of second memory circuit 120. The second memory circuit 120b has capacitive elements Csa and Csb instead of the capacitive element Cs of the second memory circuit 120a.

[0100] One terminal of the capacitive element Csa is connected to the other source or drain of transistor Tr21 and to the gate of transistor Tr24. In Figure 9 and other diagrams, the region where the other source or drain of transistor Tr21, one terminal of the capacitive element Csa, and the gate of transistor Tr24 are connected and always at the same potential corresponds to the "node SN" in the memory cell 100A.

[0101] One terminal of the capacitive element Csb is connected to the other source or drain of transistor Tr23, and to the gate of transistor Tr22. In Figure 9 and other diagrams, the region where the other source or drain of transistor Tr23, one terminal of the capacitive element Csb, and the gate of transistor Tr22 are connected and always at the same potential corresponds to the "node SNB" in the memory cell 100A.

[0102] The other terminal of the capacitive element Csa and the other terminal of the capacitive element Csb are each connected to the wiring 106 to which the signal CL is supplied.

[0103] According to the circuit configuration of memory cell 100C, the driving force of transistors Tr22 and Tr24 can be increased by setting the signal CL to potential L during data writing and to potential H during data retention. In other words, the on-current of transistors Tr22 and Tr24 can be increased. By increasing the on-current of transistors Tr22 and Tr24, soft error tolerance can be further improved.

[0104] <Circuit Configuration Example 4> As another example of the configuration of memory cell 100, Figure 11 shows a circuit configuration example of memory cell 100D. Furthermore, Figure 12 shows a perspective conceptual diagram to explain the circuit configuration of memory cell 100D in more detail.

[0105] Memory cell 100D is a modified version of memory cell 100C. To reduce repetition, a detailed explanation of memory cell 100D is omitted. For parts of the configuration of memory cell 100D that are not explained, please refer to the explanation of memory cell 100C.

[0106] Memory cell 100D has a configuration similar to memory cell 100C, but without the wiring 104. In memory cell 100D, the gates of transistors Tr21 and Tr23 are connected to the wiring 103. Memory cell 100D is also a modified version of memory cell 100B.

[0107] In the memory cell 100D, the occupied area can be reduced by not providing the wiring 104. Therefore, the storage capacity per unit area can be increased.

[0108] <Circuit Configuration Example 5> As another example of the configuration of the memory cell 100, Figure 13A shows an example of the circuit configuration of the memory cell 100E. Furthermore, Figure 14 shows a perspective conceptual diagram to explain the circuit configuration of the memory cell 100E in more detail.

[0109] Memory cell 100E is a modified version of memory cell 100A. To reduce repetition, a detailed explanation of memory cell 100E is omitted. For parts of the memory cell 100E configuration that are not explained, refer to the explanation of memory cell 100A, etc.

[0110] The memory cell 100E includes a first memory circuit 110 and a second memory circuit 120c, which is a type of second memory circuit 120. The second memory circuit 120c has different gate, source, and drain connections for transistors Tr22 and Tr24 compared to the second memory circuit 120a.

[0111] In the second memory circuit 120c, the gate of transistor Tr22 is connected to one terminal of the capacitive element Cs and the other source or drain of transistor Tr21. In the second memory circuit 120c, the region where the gate of transistor Tr22, one terminal of the capacitive element Cs, and the other source or drain of transistor Tr21 are connected and always at the same potential corresponds to the "node SN".

[0112] In the second memory circuit 120c, the gate of transistor Tr24 is connected to the other terminal of the capacitive element Cs and to the other source or drain of transistor Tr23. In the memory cell 100E, the region where the gate of transistor Tr24, the other terminal of the capacitive element Cs, and the other source or drain of transistor Tr23 are connected and always at the same potential corresponds to the "node SNB".

[0113] Furthermore, in the second memory circuit 120c, one source or drain of transistor Tr22, one source or drain of transistor Tr23, one source or drain of transistor Tr12, the output of inverter circuit INV2, and the input of inverter circuit INV1 are connected to each other. The region where one source or drain of transistor Tr22, one source or drain of transistor Tr23, one source or drain of transistor Tr12, the output of inverter circuit INV2, and the input of inverter circuit INV1 are connected and always at the same potential corresponds to "node QB".

[0114] Furthermore, in the second memory circuit 120c, one source or drain of transistor Tr24, one source or drain of transistor Tr21, one source or drain of transistor Tr11, the output of inverter circuit INV1, and the input of inverter circuit INV2 are connected to each other. The region where one source or drain of transistor Tr24, one source or drain of transistor Tr21, one source or drain of transistor Tr11, the output of inverter circuit INV1, and the input of inverter circuit INV2 are connected and always at the same potential corresponds to "node Q".

[0115] Furthermore, similar to the modified example of the second memory circuit 120a shown in Figure 2B, it is also possible to use p-type transistors as transistors Tr22 and Tr24 in the second memory circuit 120c (see Figure 13B).

[0116] Furthermore, in the memory cell 100E, as shown in the memory cell 100C in Figure 9, it is possible to have a configuration in which capacitive elements Csa and Csb are used instead of capacitive element Cs.

[0117] <Circuit Configuration Example 6> In addition, similar to the memory cell 100B described above, it is also possible to configure the memory cell 100E so that the second memory circuit 120 is not connected to the wiring 104. Figure 15 shows an example of a circuit configuration of memory cell 100F in which the second memory circuit 120c is not connected to the wiring 104 but is connected to the wiring 103.

[0118] To reduce repetition, a detailed explanation of memory cell 100F will be omitted. For information on memory cell 100F, please refer to the explanations of memory cells 100B and 100E.

[0119] Furthermore, in the memory cell 100F, as shown in the memory cell 100C in Figure 9, it is possible to have a configuration in which capacitive elements Csa and Csb are used instead of capacitive element Cs.

[0120] <Circuit Configuration Example 7> As another example of the configuration of the memory cell 100, Figure 16 shows a circuit configuration example of memory cell 100G. Figure 17 shows a perspective conceptual diagram to explain the circuit configuration of memory cell 100G in more detail.

[0121] Memory cell 100G is a modified version of memory cell 100E. As mentioned above, memory cell 100E is a modified version of memory cell 100A. Therefore, memory cell 100G is also a modified version of memory cell 100A.

[0122] To reduce repetition, a detailed explanation of memory cell 100G will be omitted. For parts of the configuration of memory cell 100G that are not explained, please refer to the explanations of memory cells 100E and 100A.

[0123] The memory cell 100G includes a first memory circuit 110 and a second memory circuit 120d, which is a type of second memory circuit 120. The second memory circuit 120d has a configuration in which transistors Tr25 and Tr26 are added to the second memory circuit 120c. Furthermore, n-type transistors are used for transistors Tr22 and Tr24, and p-type transistors are used for transistors Tr25 and Tr26.

[0124] In the second memory circuit 120d, one source or drain of transistor Tr25 is connected to one source or drain of transistor Tr22, one source or drain of transistor Tr23, one source or drain of transistor Tr12, the input of inverter circuit INV1, and the output of inverter circuit INV2. The other source or drain of transistor Tr25 is connected to wiring 107. The gate of transistor Tr25 is connected to the gate of transistor Tr22, the other source or drain of transistor Tr21, and one terminal of capacitive element Cs.

[0125] In the second memory circuit 120d, one source or drain of transistor Tr26 is connected to one source or drain of transistor Tr24, one source or drain of transistor Tr21, one source or drain of transistor Tr11, the output of inverter circuit INV1, and the input of inverter circuit INV2. The other source or drain of transistor Tr26 is connected to wiring 107. The gate of transistor Tr26 is connected to the gate of transistor Tr24, the other source or drain of transistor Tr23, and the other terminal of capacitive element Cs.

[0126] Furthermore, in the second memory circuit 120d, potential L is supplied to wiring 105 as a signal PLL, and potential H is supplied to wiring 107 as a signal PLH.

[0127] In memory cell 100G, the region where one source or drain of transistor Tr26, one source or drain of transistor Tr24, one source or drain of transistor Tr21, one source or drain of transistor Tr11, the output of inverter circuit INV1, and the input of inverter circuit INV2 are connected and always at the same potential corresponds to "node Q".

[0128] Furthermore, the region connected to either the source or drain of transistor Tr25, the input of inverter circuit INV1, the output of inverter circuit INV2, either the source or drain of transistor Tr12, either the source or drain of transistor Tr23, and either the source or drain of transistor Tr22, and which is always at the same potential, corresponds to "Node QB".

[0129] Furthermore, in memory cell 100G, the region connected to the other source or drain of transistor Tr21, the gate of transistor Tr25, the gate of transistor Tr22, and one terminal of the capacitive element Cs, and which is always at the same potential, corresponds to "node SN". Also, the region connected to the other source or drain of transistor Tr23, the gate of transistor Tr26, the gate of transistor Tr24, and the other terminal of the capacitive element Cs, and which is always at the same potential, corresponds to "node SNB".

[0130] In memory cells 100A to 100F, when correcting soft errors, a potential corresponding to the correct data is supplied to either node Q or node QB. In memory cell 100G, when correcting soft errors, a potential corresponding to the correct data can be supplied to both node Q and node QB. When a potential is supplied to both node Q and node QB, the time required for correcting soft errors can be shortened compared to when a potential is supplied to only one of them. Therefore, soft error tolerance can be improved. Thus, a memory cell with high operating speed and high reliability can be realized.

[0131] For the p-type transistors Tr25 and Tr26, for example, Si transistors can be used. Also, for the n-type transistors Tr22 and Tr24, for example, Si transistors or OS transistors can be used. Therefore, transistors Tr22, Tr24, Tr25, and Tr26 can be formed in the element layer 10.

[0132] Furthermore, it is also possible to form p-type transistors Tr25 and Tr26 on the element layer 10, and n-type transistors Tr22 and Tr24 on the element layer 20.

[0133] Furthermore, in the memory cell 100G, as shown in the memory cell 100C in Figure 9, it is possible to have a configuration in which capacitive elements Csa and Csb are used instead of capacitive element Cs.

[0134] <<Circuit Operation Example>> Next, we will explain an example of the operation of the memory cell 100. In the following, we will explain the operation examples of memory cells 100A to 100D as memory cells 100.

[0135] <Circuit Operation Example 1> Figure 18 is a timing chart illustrating the operation of memory cell 100A. Figures 19 to 23 are circuit diagrams illustrating the operating state of memory cell 100A.

[0136] [Data Writing Operation] The operation of writing data to the memory cell 100A shown in Figure 1 will be explained below.

[0137] In this specification, when the potential of node Q is potential H and the potential of node QB is potential L, the data "1" is written to or held as a logical value in the first memory circuit 110. That is, when the output potential of inverter circuit INV1 is potential H and the output potential of inverter circuit INV2 is potential L, the data "1" is written to or held as the first data in the first memory circuit 110.

[0138] Furthermore, when the potential of node Q is potential L and the potential of node QB is potential H, the data "0" is assumed to have been written to or held as a logical value in the first memory circuit 110. That is, when the output potential of inverter circuit INV1 is potential L and the output potential of inverter circuit INV2 is potential H, the data "0" is assumed to have been written to or held as the first data in the first memory circuit 110.

[0139] Furthermore, in this specification, when the potential of node SN is potential H and the potential of node SNB is potential L, it is assumed that the data "1" has been written to or held as a logical value in the second memory circuit 120a. That is, when the gate potential of transistor Tr22 is potential L and the gate potential of transistor Tr24 is potential H, it is assumed that the data "1" has been written to or held as second data in the second memory circuit 120a.

[0140] Furthermore, in this specification, when the potential of node SN is potential L and the potential of node SNB is potential H, it is assumed that the data "0" has been written to or held as a logical value in the second memory circuit 120. That is, when the gate potential of transistor Tr22 is potential H and the gate potential of transistor Tr24 is potential L, it is assumed that the data "0" has been written to or held as second data in the second memory circuit 120.

[0141] Furthermore, immediately before the data writing operation begins, the signals BL, nodes QB and SNB are assumed to be at potential H. Also, the signals BLB, WL, node Q, SET, node SN and signal PL are assumed to be at potential L. Note that, as shown in Figure 2B, if p-type transistors are used for transistors Tr22 and Tr24, signal PL is set to potential H.

[0142] During period T11, the potentials of signals WL and SET are set to H (see Figures 18 and 19). When signal WL reaches potential H, transistors Tr11 and Tr12 turn on, the potential of node Q becomes H, and the potential of node QB becomes L.

[0143] In this specification, "signal WL is active" when the potential of signal WL is such that transistors Tr11 and Tr12 are turned on. By activating signal WL, data is written to the first memory circuit 110 or data is read from the first memory circuit 110.

[0144] Furthermore, when the signal SET reaches a potential of H, transistors Tr21 and Tr23 turn on, causing the potential of node SN to reach H and the potential of node SNB to reach L.

[0145] In this specification, "signal SET is active" when the potential of signal SET is such that transistors Tr21 and Tr23 are turned on. By activating signal SET, data is written to the second memory circuit 120.

[0146] When the potential of node SNB reaches potential L, transistor Tr22 turns off. When the potential of node SN reaches potential H, transistor Tr24 turns on. When transistor Tr24 is on, node QB and wiring 105 are connected via the source and drain of transistor Tr24. Therefore, node QB is always supplied with potential L via wiring 105 and the source and drain of transistor Tr24.

[0147] During period T12, the potentials of signals WL and SET are set to L (see Figures 18 and 20). When signal WL reaches potential L, transistors Tr11 and Tr12 turn off. Also, when signal SET reaches potential L, transistors Tr21 and Tr23 turn off.

[0148] When transistors Tr11 and Tr12 are turned off, the potential of node Q is fixed at potential H, and the potential of node QB is fixed at potential L. Also, when transistors Tr21 and Tr23 are turned off, nodes SN and SNB enter a floating state (electrically floating), and the potentials written to nodes SN and SNB during period T11 are retained. In this way, data with a logical value of "1" is retained in both the first memory circuit 110 and the second memory circuit 120.

[0149] When memory cell 100A is loaded with data with a logical value of "1", node QB and wiring 105 are connected via transistor Tr24 for the duration of the data retention period of memory cell 100A. Therefore, a potential L is always supplied to node QB.

[0150] Furthermore, when data with a logical value of "0" is written to memory cell 100A, the potentials of nodes Q and SN become potential L, and the potentials of nodes QB and SNB become potential H. In this case, transistor Tr22 turns ON and transistor Tr24 turns OFF. Therefore, when data with a logical value of "0" is written to memory cell 100A, node Q and wiring 105 are connected via transistor Tr22 during the data retention period. Thus, node Q is always supplied with potential L.

[0151] [Data Read Operation] Next, the data read operation held in memory cell 100A will be described. Here, it is assumed that data with a logical value of "1" has been written to memory cell 100A. Also, it is assumed that immediately before the read operation starts (immediately before period T13), the signals WL and SET are at potential L. Furthermore, it is assumed that the potential of wiring 101 is at potential L and the potential of wiring 102 is at potential H.

[0152] During period T13, wiring 101 and wiring 102 are precharged to a predetermined potential. Specifically, wiring 101 and wiring 102 are made to float at a potential intermediate or near the intermediate potential between potential H and potential L (hereinafter also referred to as the "intermediate potential"). By making wiring 101 and wiring 102 float at the intermediate potential, the time required for the potential change of wiring 101 and wiring 102 during data reading operation can be shortened. Therefore, the reading speed of the retained data can be improved.

[0153] During period T14, the signal WL is activated. In this embodiment, the signal WL is set to potential H (see Figures 18 and 21). When the signal WL is activated, transistors Tr11 and Tr12 are turned on. When transistor Tr11 is turned on, the output potential of inverter circuit INV1 is supplied to wiring 101. When transistor Tr12 is turned on, the output potential of inverter circuit INV2 is supplied to wiring 102. By detecting the potentials of wiring 101 and wiring 102, or the potential difference between wiring 101 and wiring 102, the data held by memory cell 100 can be read. In this embodiment, the potential of wiring 101 is potential H, and the potential of wiring 102 is potential L.

[0154] [Soft Error Tolerance of Memory Cell 100A] Next, the soft error tolerance of memory cell 100A will be explained. As mentioned above, a potential L is always supplied to node QB of memory cell 100A via wiring 105 and the source and drain of transistor Tr24. For this reason, bit inversion of the first memory circuit 110 is extremely unlikely to occur in memory cell 100A. In other words, memory cell 100A has extremely high soft error tolerance.

[0155] [Soft Error Correction Operation of Memory Cell 100A] The correction operation in the event of a soft error will be explained using periods T15 and T16. Here, it is assumed that memory cell 100A holds data with a logical value of "1". That is, both the first data and the second data hold data with a logical value of "1".

[0156] First, let's assume that a soft error occurred in memory cell 100A during period T15 (see Figures 18 and 22). For example, let's assume that radiation 999 enters memory cell 100A, causing a bit inversion in the first memory circuit 110, which is composed of Si transistors. That is, the logical value of the first data changes from "1" to "0" due to the soft error. Specifically, the potential of node Q becomes potential L, and the potential of node QB becomes potential H.

[0157] On the other hand, the second memory circuit 120, which is composed of OS transistors, is extremely resistant to soft errors, so bit inversion does not occur in the second memory circuit 120. The logical value of the second data remains "1". Therefore, in the memory cell 100A where a soft error occurs, the logical values ​​of the first data and the second data are different from each other.

[0158] Next, the recovery operation from a soft error will be described as period T16 (see Figures 18 and 23). As mentioned above, node QB is connected to wiring 105. Wiring 105 is supplied with a potential L as signal PL. Therefore, even if a bit inversion occurs in the first memory circuit 110 due to a soft error and the potential of node QB changes from potential L to potential H, potential L is immediately supplied to node QB from wiring 105. When the potential of node QB, to which the input of inverter circuit INV1 is connected, becomes potential L, the output of inverter circuit INV1 becomes potential H. Therefore, the potential of node Q becomes potential H.

[0159] Furthermore, if p-type transistors are used for transistors Tr22 and Tr24, a potential H is supplied to the wiring 105 as signal PL.

[0160] In this way, the memory cell 100A according to one aspect of the present invention repairs bit inversions caused by soft errors. In this embodiment, the occurrence of soft errors and data repair were described separately in periods T15 and T16, but in the memory cell 100A according to one aspect of the present invention, data repair is performed almost simultaneously with the occurrence of soft errors. For this reason, the memory cell 100A according to one aspect of the present invention functions as a memory element that has the function of automatically repairing soft errors. The memory cell 100A according to one aspect of the present invention functions as a memory element in which soft errors do not occur substantially.

[0161] <Circuit Operation Example 2> Next, the operation of memory cell 100B will be explained. Memory cell 100B is a modified version of memory cell 100A, and in order to reduce repetition of explanations, we will mainly explain the differences from Circuit Operation Example 1.

[0162] As explained in Circuit Configuration Example 2, memory cell 100B has a configuration similar to memory cell 100A, but without the wiring 104. Memory cell 100B operates similarly to memory cell 100A, but differs in that transistors Tr21 and Tr23 are turned on during both data writing and data reading operations.

[0163] In memory cell 100B, data is written to the second storage circuit 120 even during data read operations, allowing the potentials of node SN and node SNB to be refreshed. This prevents potential changes in node SN and node SNB, thereby improving the reliability of the memory cell.

[0164] <Circuit Operation Example 3> Next, the operation of memory cell 100C will be explained. Memory cell 100C is a modified version of memory cell 100A, and in order to reduce repetition of explanations, we will mainly explain the differences from Circuit Operation Example 1. Figure 24 is a timing chart that explains the operation of memory cell 100C. Figures 25 and 26 are circuit diagrams that explain the operating state of memory cell 100C.

[0165] [Data Writing Operation] Data writing to memory cell 100C differs from that of memory cell 100A in that the potential of signal CL is changed (see Figures 24 and 25). Data is written to memory cell 100C during period T31, and the written data is held during period T32. In the timing chart shown in Figure 24, period T31 corresponds to the aforementioned period T11, and period T32 corresponds to the aforementioned period T12.

[0166] Furthermore, immediately before the data writing operation begins, the potential of signal CL is assumed to be higher than potential L by a voltage Vb (also written as "Vb"). Voltage Vb is a voltage whose potential difference with potential L is greater than 0V and which is less than the threshold voltages of transistors Tr22 and Tr24.

[0167] During period T31, when writing data to memory cell 100C, the potential of the signal CL supplied to wiring 106 is set to potential L. Other operations are the same as those of memory cell 100A described in circuit operation example 1, so their explanation is omitted here.

[0168] During period T32, the potentials of signals WL and SET are set to potential L. After setting the potentials of signals WL and SET to potential L, Vb is supplied to wiring 106 as signal CL. As a result, the potential of node SN, which was supplied with potential H, becomes potential H + Vb. Also, the potential of node SNB, which was supplied with potential L, becomes potential L + Vb. Figure 26 shows the operating state when Vb is supplied to wiring 106.

[0169] Since Vb is a voltage lower than the threshold voltage of transistor Tr22, transistor Tr22 remains in the off state. Furthermore, a potential of H + Vb is applied to the gate of transistor Tr24. Therefore, the on-current of transistor Tr24 is greater than when only potential H is applied.

[0170] As mentioned above, when p-type transistors are used for transistors Tr22 and Tr24, a potential H is supplied to the wiring 105 as the signal PL. Also, when p-type transistors are used for transistors Tr22 and Tr24, addition of Vb is interpreted as subtraction, and subtraction of Vb is interpreted as addition.

[0171] [Data Reading Operation] Pre-charging is performed on wiring 101 and wiring 102 during period T33 as shown in Figure 24, and data is read during period T34. Period T33 corresponds to period T13 mentioned above, and period T34 corresponds to period T14 mentioned above. Data held in memory cell 100C can be read in the same way as in memory cell 100A.

[0172] [Soft Error Tolerance of Memory Cell 100C] Next, the soft error tolerance of memory cell 100C will be described. Similar to memory cell 100A, in this embodiment, a potential L is always supplied to node QB of memory cell 100C via wiring 105 and the source and drain of transistor Tr24. For this reason, bit inversion of the first storage circuit 110 is extremely unlikely to occur in memory cell 100C as well. The period T35 shown in Figure 24 corresponds to the aforementioned period T15, and the period T36 corresponds to the aforementioned period T16.

[0173] In addition, in memory cell 100C, it is possible to maintain a potential higher than potential H at node SN or node SNB. Therefore, it is possible to increase the on-current of transistor Tr22 or transistor Tr24, and thus improve soft error tolerance compared to memory cell 100A.

[0174] Furthermore, the signal CL supplied to wiring 106 can be set to a fixed potential such as GND, VDD, or VSS. In this case, it is not possible to maintain a potential higher than potential H at node SN or node SNB. However, since the potentials of the other terminal of capacitive element Csa and the other terminal of capacitive element Csb are fixed, the potentials written to node SN and node SNB can be stably maintained. Therefore, the reliability of memory cell 100C can be improved.

[0175] <Circuit Operation Example 4> Next, the operation of memory cell 100D will be explained. As mentioned above, memory cell 100D is a modified version of memory cell 100C and also a modified version of memory cell 100B. Memory cell 100D has a configuration in which wiring 104 is removed from memory cell 100B. Memory cell 100D operates similarly to memory cell 100C, but differs in that transistors Tr21 and Tr23 are turned on during both data writing and data reading operations.

[0176] Memory cell 100D functions as a memory element possessing the characteristics of memory cell 100B and memory cell 100C. The operation of memory cell 100D can be understood by referring to circuit operation 1 to circuit operation 3, so a detailed explanation is omitted.

[0177] <Circuit Operation Example 5> Next, the operation of memory cell 100E will be explained. As mentioned above, memory cell 100E is a modified version of memory cell 100A. Memory cell 100E operates similarly to memory cell 100A, but the connection paths between node Q and wiring 105 and between node QB and wiring 105 during the period in which data is held are different.

[0178] Figure 27 is a circuit diagram illustrating the operating state of the memory cell 100E during the period in which it holds data. Figure 27 shows the state in which the memory cell 100E holds data with a logical value of "1". When the memory cell 100E holds a logical value of "1", transistor Tr22 turns ON, and the node QB and wiring 105 become conductive through transistor Tr22. When the memory cell 100E holds a logical value of "0", transistor Tr24 turns ON, and the node Q and wiring 105 become conductive through transistor Tr24 (not shown).

[0179] Similar to memory cell 100A, in memory cell 100E, a potential L is always supplied to node Q or node QB depending on the data being held. Therefore, memory cell 100E also functions as a memory element in which virtually no soft errors occur. Furthermore, similar to the second memory circuit 120a, if p-type transistors are used for transistors Tr22 and Tr24 constituting the second memory circuit 120c, the signal PL is set to a potential H.

[0180] <Circuit Operation Example 6> Next, the operation of memory cell 100G will be explained. Memory cell 100G operates similarly to memory cell 100A, but the connection paths between node Q and wiring 105 and between node QB and wiring 105 are different during the period in which data is held.

[0181] Figure 28 is a circuit diagram illustrating the operating state of memory cell 100G during the period in which it holds data. Figure 28 shows the state in which memory cell 100G holds data with a logical value of "1". When memory cell 100G holds a logical value of "1", transistor Tr22 turns ON, and node QB and wiring 105 become conductive through transistor Tr22. Also, when memory cell 100G holds a logical value of "1", transistor Tr26 turns ON, and node Q and wiring 107 become conductive through transistor Tr26.

[0182] When memory cell 100G holds a logical value of "0", transistor Tr24 turns ON, and node Q and wiring 105 become conductive via transistor Tr24 (not shown). Also, when memory cell 100G holds a logical value of "0", transistor Tr25 turns ON, and node QB and wiring 107 become conductive via transistor Tr25 (not shown).

[0183] Memory cell 100G also functions as a memory element that is virtually free from soft errors. Furthermore, in memory cell 100G, a potential is always supplied to both node Q and node QB depending on the data being held. For this reason, memory cell 100G achieves higher reliability than memory cell 100A and the like.

[0184] A memory cell 100 (memory cell 100A, memory cell 100B, memory cell 100C, memory cell 100D, memory cell 100E, memory cell 100F, and memory cell 100G) according to one aspect of the present invention is a memory element in which soft errors are extremely unlikely to occur, and in fact virtually no soft errors occur. By using the memory cell 100 according to one aspect of the present invention, the generation of Hamming codes is unnecessary, and a highly reliable storage device can be realized without reducing the usable storage capacity. Furthermore, since error verification is not required during reading, high-speed reading can be achieved. It is also possible to generate and store Hamming codes as needed. By using the memory cell 100 according to one aspect of the present invention as a storage element of an ECC memory, the reliability of the ECC memory can be improved.

[0185] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments.

[0186] (Embodiment 2) In this embodiment, a memory cell array 200 including a memory cell 100 (memory cell 100A, memory cell 100B, memory cell 100C, or memory cell 100D) according to one aspect of the present invention, and a storage device 300 including the memory cell array 200 will be described.

[0187] <Memory Cell Array 200> Figure 29 shows an example configuration of a memory cell array 200 including a plurality of memory cells 100 arranged in a matrix of m rows and n columns (where m and n are integers of 1 or more). By arranging a plurality of memory cells 100 in a matrix, a storage device with a large storage capacity can be realized. In this embodiment, the example configuration is shown assuming memory cell 100A as the memory cell 100.

[0188] Generally, rows and columns extend in directions that are orthogonal to each other. In this embodiment, the X direction (direction along the X-axis) is defined as "rows" and the Y direction (direction along the Y-axis) is defined as "columns," but it is also possible to define the X direction as "columns" and the Y direction as "rows."

[0189] In Figure 29, the memory cell 100 in the first row and first column is shown as memory cell 100[1,1], the memory cell 100 in the mth row and nth column is shown as memory cell 100[m,n], the memory cell 100 in the ith row and first column (where i is an integer between 1 and m that represents any row) is shown as memory cell 100[i,1], the memory cell 100 in the mth row and first column is shown as memory cell 100[m,1], the memory cell 100 in the first row and nth column is shown as memory cell 100[1,n], and the memory cell 100 in the ith row and nth column is shown as memory cell 100[i,n].

[0190] Furthermore, in this specification and other documents, the memory cell 100 in the i-th row and j-th column (where j is an integer from 1 to n that represents any column) may be referred to as memory cell 100[i,j]. In this specification and other documents, any memory cell 100 among a plurality of memory cells 100 arranged in a matrix may be referred to as "memory cell 100" or "memory cell 100[i,j]".

[0191] Furthermore, the first memory circuit 110 and the second memory circuit 120 (second memory circuit 120a or second memory circuit 120b) included in each of the multiple memory cells 100 arranged in a matrix are also shown in the same way as the memory cell 100. For example, the first memory circuit 110 and the second memory circuit 120 included in memory cell 100[1,1] are shown as the first memory circuit 110[1,1] and the second memory circuit 120[1,1], respectively. Also, for example, the first memory circuit 110 and the second memory circuit 120 included in memory cell 100[m,n] are shown as the first memory circuit 110[m,n] and the second memory circuit 120[m,n], respectively.

[0192] In Figure 29, the wirings 103, 104, and 105 that connect to the multiple memory cells 100 arranged in the first row are shown as wiring 103[1], wiring 104[1], and wiring 105[1], respectively. Also in Figure 29, the signal WL supplied to wiring 103[1] is shown as signal WL[1], the signal SET supplied to wiring 104[1] is shown as signal SET[1], and the signal PL supplied to wiring 105[1] is shown as signal PL[1]. The wiring and signals of the mth row and the ith row are shown similarly.

[0193] In Figure 29, the wiring 101 connecting to the multiple memory cells 100 arranged in the first row is shown as wiring 101[1]. Similarly, the wiring 102 connecting to the multiple memory cells 100 arranged in the first row is shown as wiring 102[1]. In Figure 29, the signal BL supplied to wiring 101[1] is shown as signal BL[1], and the signal BLB supplied to wiring 102[1] is shown as signal BLB[1]. The wiring and signals in the nth row are shown similarly.

[0194] <Storage Device 300> Figure 30A shows a block diagram illustrating an example of the configuration of a storage device 300 including a memory cell 100 according to one aspect of the present invention. The storage device 300 shown in Figure 30A includes a drive circuit 21 and a memory cell array 200.

[0195] The drive circuit 21 includes a PSW 22 (power switch), a PSW 23, and a peripheral circuit 31. The peripheral circuit 31 includes a peripheral circuit 41, a control circuit 32, and a voltage generation circuit 33.

[0196] In the storage device 300, each circuit, each signal, and each voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or other signals can be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are external input signals, and signal RDA is an external output signal. Signal CLK is a clock signal.

[0197] Furthermore, signals BW, CE, and GW are control signals. Signal CE is the chip enable signal, signal GW is the global write enable signal, and signal BW is the byte write enable signal. Signal ADDR is the address signal. Signal WDA is the write data signal, and signal RDA is the read data signal. Signals PON1 and PON2 are power gating control signals. Signals PON1 and PON2 can also be generated by the control circuit 32.

[0198] The control circuit 32 is a logic circuit that has the function of controlling the overall operation of the storage device 300. For example, the control circuit performs logical operations on signals CE, GW, and BW to determine the operating mode of the storage device 300 (e.g., write operation, read operation). Alternatively, the control circuit 32 generates control signals for the peripheral circuit 41 so that this operating mode is executed.

[0199] The voltage generation circuit 33 has the function of generating voltage. The signal WAKE has the function of controlling the input of the signal CLK to the voltage generation circuit 33. For example, when a signal with a potential of H is applied to the signal WAKE, the signal CLK is input to the voltage generation circuit 33, and the voltage generation circuit 33 generates the voltage necessary for the operation of the memory device 300. For example, it is also possible to generate a negative voltage.

[0200] The peripheral circuit 41 is a circuit for writing and reading data to and from the memory cell 100. The peripheral circuit 41 includes a row decoder 42, a column decoder 44, a row driver 43, a column driver 45, an input circuit 47, and an output circuit 48.

[0201] The row decoder 42 and column decoder 44 have the function of decoding the ADDR signal. The row decoder 42 is a circuit for specifying the row to access, and the column decoder 44 is a circuit for specifying the column to access. The row driver 43 has the function of selecting the wiring specified by the row decoder 42. The column driver 45 has the function of writing data to the memory cell 100, reading data from the memory cell 100, and holding the read data.

[0202] The input circuit 47 has the function of holding the signal WDA. The data held by the input circuit 47 is output to the column driver 45. The output data of the input circuit 47 is the data (Din) to be written to the memory cell 100. The data (Dout) read by the column driver 45 from the memory cell 100 is output to the output circuit 48. The output circuit 48 has the function of holding Dout. The output circuit 48 also has the function of outputting Dout to the outside of the storage device 300. The data output from the output circuit 48 is the signal RDA.

[0203] PSW22 has the function of controlling the supply of VDD to the peripheral circuit 31. PSW23 has the function of controlling the supply of VHM to the row driver 43. Here, the high power supply potential of the storage device 300 is VDD, and the low power supply potential is GND. VHM is a high power supply potential used to bring the word lines to potential H, and is higher than VDD. The on / off state of PSW22 is controlled by signal PON1, and the on / off state of PSW23 is controlled by signal PON2. In Figure 30A, the number of power supply domains to which VDD is supplied in the peripheral circuit 31 is set to 1, but it can be multiple. In this case, a power switch can be provided for each power supply domain.

[0204] Furthermore, as shown in Figure 30B, the element layer 10 can be provided with a first memory circuit 110 and a drive circuit 21. By providing the element layer 10 with the first memory circuit 110 and the drive circuit 21, the first memory circuit 110 and the drive circuit 21 can be formed simultaneously, thereby increasing the productivity of the memory device 300.

[0205] Furthermore, as shown in Figure 30C, a drive circuit 21 can be provided in layer 50, and element layers 10 and 20 can be placed on top of layer 50. Similar to element layer 10, layer 50 can be made from a single-crystal semiconductor substrate or an SOI substrate. Layer 50 and element layer 10 can be connected using through-electrode technology such as TSV (Through Silicon Via) or bonding technology such as Cu-Cu direct bonding. By forming layer 50 with the drive circuit 21 and element layer 10 separately, the operation of the drive circuit 21 contained in layer 50 can be confirmed before connecting layer 50 and element layer 10. Therefore, only good quality layer 50 can be connected to element layer 10, thereby improving the manufacturing yield of the memory device 300.

[0206] Furthermore, as shown in Figure 30D, it is also possible to repeatedly stack element layers 10 and 20 that constitute the memory cell array 200 on the layer 50 including the drive circuit 21. Figure 30D shows an example in which k layers (where k is an integer of 2 or more) of element layers 10 and k layers of element layers 20 are stacked on the layer 50. The element layers 10 and 20 provided in the first layer on the layer 50 are shown as element layer 10[1] and element layer 20[1], respectively, and the element layers 10 and 20 provided in the kth layer are shown as element layer 10[k] and element layer 20[k], respectively.

[0207] By stacking the layer 50 containing the drive circuit 21 with the element layers 10 and 20 that constitute the memory cell array 200, the signal propagation distance between the drive circuit 21 and the memory cell array 200 can be shortened. Therefore, parasitic resistance and parasitic capacitance between the drive circuit 21 and the memory cell array 200 are reduced, resulting in reduced power consumption and signal delay. Furthermore, the storage device 300 can be miniaturized. In addition, the storage capacity per unit area can be increased.

[0208] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments.

[0209] (Embodiment 3) In this embodiment, a planar configuration example and a cross-sectional configuration example of the second memory circuit 120 provided on the element layer 20 will be described. The second memory circuit 120 is a type of semiconductor device.

[0210] In this embodiment, a planar configuration example and a cross-sectional configuration example of the second memory circuit 120a will be described as an example of the second memory circuit 120. Figure 31 is a plan view of the second memory circuit 120a as seen from the Z direction. Figure 32A is a cross-sectional view of the area indicated by the dashed line A1-A2 in Figure 31 as seen from the X direction. Figure 32B is a cross-sectional view of the area indicated by the dashed line A3-A4 in Figure 31 as seen from the Y direction. Note that in the plan view of Figure 31, some components such as the insulating layer have been omitted for clarity.

[0211] In Figures 31, 32A, and 32B, the second memory circuit 120a, which is a type of semiconductor device, has an insulating layer 311 and an insulating layer 312 on top of the insulating layer 311. It also has a conductive layer 313 (conductive layer 313[1], conductive layer 313[2], and conductive layer 313[3]) and a conductive layer 340 that penetrate the insulating layer 311 and the insulating layer 312. It also has an insulating layer 314 on top of the insulating layer 312. It also has a conductive layer 315 (conductive layer 315[1], conductive layer 315[2], and conductive layer 315[3]) and a conductive layer 340 that penetrate the insulating layer 314. The conductive layer 315 penetrates the insulating layer 314 and is in contact with the conductive layer 313.

[0212] Furthermore, the second memory circuit 120a has an insulating layer 316 on top of the insulating layer 314, and on top of the insulating layer 316, there is an insulating layer 317 (insulating layer 317[1], insulating layer 317[2] (not shown), insulating layer 317[3] and insulating layer 317[4] (not shown)), semiconductor layer 318 (semiconductor layer 318[1], semiconductor layer 318[2] (not shown), semiconductor layer 318[3] and semiconductor layer 318[4] (not shown)). Furthermore, on top of the semiconductor layer 318 there is a pair of conductive layers 319 (a pair of conductive layers 319[1], a pair of conductive layers 319[2], a pair of conductive layers 319[3] and a pair of conductive layers 319[4]).

[0213] Furthermore, the second memory circuit 120a has insulating layers 320 and 321 on top of insulating layer 316 and conductive layer 319. In addition, a conductive layer 322 (conductive layer 322[1], conductive layer 322[2], conductive layer 322[3] and conductive layer 322[4]) is provided in the region where a portion of insulating layer 321 and insulating layer 320 has been removed and conductive layer 319 has not been formed. Conductive layer 322[1] also functions as conductive layer 322[3].

[0214] A portion of the conductive layer 322[1] overlaps with the semiconductor layer 318[1]. Another portion of the conductive layer 322[1] overlaps with the semiconductor layer 318[3]. A portion of the conductive layer 322[2] overlaps with the semiconductor layer 318[2]. A portion of the conductive layer 322[4] overlaps with the semiconductor layer 318[4]. The semiconductor layer 318 and the conductive layer 322 function as part of the transistor. Examples of transistor configurations that can be used for transistors Tr21 to Tr24 will be described in detail separately.

[0215] Furthermore, the second memory circuit 120a has an insulating layer 323 that covers the insulating layer 321 and the conductive layer 322, and an insulating layer 324 on the insulating layer 323. It also has a conductive layer 325 (conductive layer 325[1], conductive layer 325[2], conductive layer 325[3] and conductive layer 325[4]) that penetrates the insulating layer 324, insulating layer 323, insulating layer 321 and insulating layer 320 and reaches the conductive layer 319. It also has a conductive layer 326 (conductive layer 326[1], conductive layer 326[2], conductive layer 326[3] and conductive layer 326[4]) that penetrates the insulating layer 324, insulating layer 323, insulating layer 321 and insulating layer 320 and reaches the conductive layer 319.

[0216] Furthermore, the second memory circuit 120a has conductive layers 327 (conductive layers 327[1], 327[2], and 327[3]) and 332 that penetrate the insulating layers 324, 323, 321, 320, and 316 and reach the conductive layer 315.

[0217] Furthermore, the second memory circuit 120a has a conductive layer 331 that penetrates the insulating layer 324 and the insulating layer 323 and reaches the conductive layer 322[1], a conductive layer 338 that reaches the conductive layer 322[4], and a conductive layer 342 that reaches the conductive layer 322[2].

[0218] Furthermore, the second memory circuit 120a has conductive layers 328 (conductive layer 328[1], conductive layer 328[2], and conductive layer 328[3]), conductive layer 334, conductive layer 335, conductive layer 336, and conductive layer 337 on the insulating layer 324.

[0219] Furthermore, the second memory circuit 120a has an insulating layer 329 on top of an insulating layer 324, a conductive layer 328, a conductive layer 334, a conductive layer 335, a conductive layer 336, and a conductive layer 337. It also has a conductive layer 339 and a conductive layer 330 that penetrate the insulating layer 329. Furthermore, the second memory circuit 120a has a conductive layer 333 on top of the insulating layer 329.

[0220] The conductive layer 328[1] has a region connected to one of the pair of conductive layers 319[1] via conductive layer 325[1], a region connected to one of the pair of conductive layers 319[2] via conductive layer 325[2], and a region connected to conductive layer 315[1] via conductive layer 327[1]. The conductive layer 315[1] also has a region connected to conductive layer 313[1].

[0221] The conductive layer 328[3] has a region connected to one of the pair of conductive layers 319[3] via conductive layer 325[3], a region connected to one of the pair of conductive layers 319[4] via conductive layer 325[4], and a region connected to conductive layer 315[3] via conductive layer 327[3]. The conductive layer 315[3] also has a region connected to conductive layer 313[3].

[0222] The conductive layer 328[2] has a region connected to the other of the pair of conductive layers 319[2] via conductive layer 326[2], a region connected to the other of the pair of conductive layers 319[4] via conductive layer 326[4], and a region connected to conductive layer 315[2] via conductive layer 327[2]. The conductive layer 315[2] also has a region connected to conductive layer 313[2].

[0223] Conductive layer 334 has a region connected to the other of the pair of conductive layers 319[1] via conductive layer 326[1] and a region connected to conductive layer 322[4] via conductive layer 338. Conductive layer 335 has a region connected to the other of the pair of conductive layers 319[3] via conductive layer 326[3] and a region connected to conductive layer 339. Conductive layer 337 has a region connected to conductive layer 322[1] via conductive layer 331 and a region connected to conductive layer 341 via conductive layer 332. Conductive layer 341 also has a region connected to conductive layer 340.

[0224] The conductive layer 333 has a region connected to the conductive layer 335 via the conductive layer 339 and a region connected to the conductive layer 336 via the conductive layer 330. The conductive layer 336 also has a region connected to the conductive layer 322[2] via the conductive layer 342.

[0225] The region where conductive layer 333 and conductive layer 334 overlap each other via insulating layer 329 functions as a capacitive element Cs. Therefore, a part of conductive layer 334 functions as one terminal of the capacitive element Cs, and a part of conductive layer 333 functions as the other terminal of the capacitive element Cs. The other of the pair of conductive layers 319[1], conductive layer 326[1], conductive layer 334, conductive layer 338, and conductive layer 322[4] correspond to node SN. The other of the pair of conductive layers 319[3], conductive layer 326[3], conductive layer 335, conductive layer 339, conductive layer 333, conductive layer 330, conductive layer 336, conductive layer 342, and conductive layer 322[2] correspond to node SNB.

[0226] Furthermore, conductive layer 313[1] is connected to node Q of the first memory circuit 110, and conductive layer 313[3] is connected to node QB of the first memory circuit 110. Also, conductive layer 340 is connected to wiring 104, and conductive layer 313[2] is connected to wiring 105.

[0227] <Constituent Materials> Next, we will describe an example of materials that can be used in the second memory circuit 120a, which is a type of semiconductor device.

[0228] [Insulating Layer] As insulating layers (insulating layers 311, 312, 314, 316, 317, 320, 321, 323, 324, 329, etc.), insulating oxides, nitrides, oxidized nitrides, nitride oxides, metal oxides, metal oxidized nitrides, metal nitride oxides, etc. can be used. For example, as insulating layers, insulating materials selected from aluminum nitride, aluminum oxide, aluminum oxide nitride, aluminum oxide nitride, magnesium oxide, silicon nitride, silicon oxide, silicon oxide nitride, silicon oxide nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, aluminum silicate, etc., can be used as a single layer or in layers. It is also possible to use multiple oxide materials, nitride materials, oxidized nitride materials, and nitride oxide materials.

[0229] In this specification, a nitride oxide refers to a material with a higher nitrogen content than oxygen content. Similarly, an oxidized nitride refers to a material with a higher oxygen content than nitrogen content. The content of each element can be measured, for example, using Rutherford backscattering spectroscopy (RBS).

[0230] As transistors become smaller and more integrated, thinning of the gate insulating layer can lead to problems such as leakage current. By using a high-k material (a high dielectric constant material; a material with a high relative permittivity) for the insulating layer that functions as the gate insulating layer, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. Furthermore, it becomes possible to thin the equivalent oxide film thickness (EOT) of the gate insulating layer. On the other hand, by using a material with a low relative permittivity for the insulating layer that functions as the interlayer film, it is possible to reduce parasitic capacitance between wiring. Therefore, it is crucial to select materials according to the function required of the insulating layer.

[0231] Materials with a high dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxide nitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxide nitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0232] Materials with low dielectric constant include silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, carbon and nitrogen-added silicon oxide, porous silicon oxide, or resins.

[0233] The method for forming the insulating material is not particularly limited, and various formation methods such as vapor deposition, ALD, CVD, sputtering, and spin coating can be used.

[0234] For example, the insulating layer 316 and the insulating layer 323 are preferably formed using an insulating material that does not easily allow impurities to permeate. For example, insulating materials containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or in a laminated form. Examples of insulating materials that do not easily allow impurities to permeate include aluminum oxide, aluminum nitride, aluminum oxide nitride, aluminum oxide nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and silicon nitride.

[0235] By using an insulating material that is resistant to the permeability of impurities in the insulating layer 316, the diffusion of impurities from below can be suppressed, thereby improving the reliability of the transistor. In other words, the reliability of the semiconductor device including the transistor can be improved. By using an insulating material that is resistant to the permeability of impurities in the insulating layer 323, the diffusion of impurities from above the insulating layer 323 can be suppressed, thereby improving the reliability of the transistor. In other words, the reliability of the semiconductor device including the transistor can be improved.

[0236] Furthermore, an insulating layer that can function as both an insulating layer and a planarizing layer can be used. Examples of materials that function as a planarizing layer include acrylic resin, polyimide, epoxy resin, polyamide, polyimidoamide, siloxane resin, benzocyclobutene resin, phenolic resin, and their precursors. In addition to the above organic materials, low-k materials (low dielectric constant materials; materials with a small relative permittivity), siloxane resin, PSG (phosphorus glass), BPSG (phosphorus boron glass), etc. can also be used. It is also possible to laminate multiple insulating layers formed from these materials.

[0237] Siloxane resin refers to a resin containing Si-O-Si bonds formed from siloxane-based materials as starting materials. Siloxane resin may use organic groups (e.g., alkyl or aryl groups) or fluoro groups as substituents. Furthermore, the organic groups may also contain fluoro groups.

[0238] Furthermore, a three-layer insulating layer (also called "ZAZ") consisting of aluminum oxide sandwiched between two layers of zirconium oxide can be used as the insulating layer 329 that functions as the dielectric of the capacitive element Cs. ZAZ is a material with a high dielectric constant, and by using ZAZ as the dielectric of the capacitive element Cs, the occupied area of ​​the capacitive element Cs can be reduced.

[0239] [Conductive Layers] Conductive materials used in conductive layers (conductive layer 313, conductive layer 315, conductive layer 319, conductive layer 322, conductive layer 325, conductive layer 326, conductive layer 327, conductive layer 328, conductive layer 330, conductive layer 333, conductive layer 334, conductive layer 335, conductive layer 336, conductive layer 337, conductive layer 338, conductive layer 339, conductive layer 340, conductive layer 341, conductive layer 342, etc.) of various wirings and electrodes that constitute semiconductor devices include aluminum (Al), chromium (Cr), copper (Cu), silver ( Metal elements selected from Ag, gold (Au), platinum (Pt), tantalum (Ta), nickel (Ni), titanium (Ti), molybdenum (Mo), tungsten (W), hafnium (Hf), vanadium (V), niobium (Nb), manganese (Mn), magnesium (Mg), zirconium (Zr), beryllium (Be), ruthenium (Ru), etc., alloys composed of the above-mentioned metal elements, or alloys combining the above-mentioned metal elements can be used.

[0240] As alloys composed of the aforementioned metal elements, nitrides or oxides of the alloys can also be used. For example, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. can be used. In addition, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide can also be used.

[0241] Furthermore, conductive materials containing nitrogen, such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, nitrides containing titanium and aluminum, conductive materials containing oxygen, such as oxides containing ruthenium oxide, strontium and ruthenium, oxides containing lanthanum and nickel, and materials containing metallic elements such as titanium, tantalum, and ruthenium, are preferred because they are conductive materials that are resistant to oxidation, conductive materials that have the function of suppressing oxygen diffusion, or materials that maintain conductivity even when absorbing oxygen. Examples of conductive materials containing oxygen include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide (ITO), indium tin oxide containing titanium oxide, silicon-added indium tin oxide (also called ITSO), indium zinc oxide (also called IZO®), and indium zinc oxide containing tungsten oxide.

[0242] Furthermore, it is possible to use multiple conductive layers formed from the above materials in a laminated structure. For example, a laminated structure can be formed by combining the aforementioned metal element material with an oxygen-containing conductive material. Alternatively, a laminated structure can be formed by combining the aforementioned metal element material with a nitrogen-containing conductive material. Furthermore, a laminated structure can be formed by combining the aforementioned metal element material with an oxygen-containing conductive material and a nitrogen-containing conductive material.

[0243] Furthermore, Cu-X alloy (where X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) can be used as the conductive material. Since layers formed from Cu-X alloy can be processed using a wet etching process, manufacturing costs can be reduced. In addition, aluminum alloys containing one or more elements selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium can be used as the conductive material.

[0244] When an oxide semiconductor, a type of metal oxide, is used as the semiconductor layer 318, the conductive layer 319 is a conductive layer in contact with the semiconductor layer 318. Therefore, it is preferable to use a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, a conductive metal oxide (also called an "oxide conductive layer"), or a conductive material that has the function of suppressing oxygen diffusion. Examples of such conductive materials include conductive materials containing nitrogen and conductive materials containing oxygen. This makes it possible to suppress a decrease in the conductivity of the conductive layer 319.

[0245] By using an oxide conductive layer as the conductive layer 319, conductivity can be maintained even if the conductive layer 319 absorbs oxygen. For example, even when an insulating layer containing oxygen that is desorbed by heating (also called "excess oxygen") is used as the insulating layer in contact with the conductive layer 319, the conductive layer 319 can maintain its conductivity, making it suitable. For example, ITO, ITSO, IZO (registered trademark), etc., can be used as the conductive layer 319.

[0246] [Semiconductor Layer] As the semiconductor layer, single-crystal semiconductors, polycrystalline semiconductors, microcrystalline semiconductors, or amorphous semiconductors can be used individually or in combination. The semiconductor material is not limited to elemental semiconductors whose main component is a single element (e.g., silicon, germanium), but can also be compound semiconductors (e.g., silicon germanium, silicon carbide, gallium arsenide, nitride semiconductors, etc.). Furthermore, as compound semiconductors, organic substances with semiconductor properties or metal oxides with semiconductor properties (also called "oxide semiconductors") can be used. It is also possible to include impurities as dopants in these semiconductor materials.

[0247] For example, single-crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon can be used as semiconductor layers. As polycrystalline silicon, for example, low-temperature polysilicon (LTPS) can be used.

[0248] Furthermore, as described in the above embodiment, since oxide semiconductors have a band gap of 2 eV or more, the OS transistor has a remarkably low off-current. The off-current value of the OS transistor per 1 μm of channel width at room temperature is 1a (1 × 10⁻¹⁰). −１８ A) Below, 1zA (1×10 −２１ A) Less than or equal to, or 1yA (1 × 10 −２４ A) The following is possible. Furthermore, OS transistors operate stably even in high-temperature environments and exhibit little variation in characteristics. For example, OS transistors can perform good switching operations even in environments between 125°C and 200°C because the ratio of on-current to off-current is large. In addition, memory circuits or memory elements using OS transistors are less susceptible to soft errors caused by radiation such as cosmic rays, thus increasing the reliability of the memory circuit or memory element.

[0249] Therefore, in this embodiment and others, it is preferable to use OS transistors as transistors Tr21 to Tr24. In particular, it is preferable to use OS transistors for transistors Tr21 and Tr23. In addition, because OS transistors have a high dielectric strength between the source and drain, the channel length can be shortened. Therefore, the on-current can be increased.

[0250] The metal oxide that can be used in the semiconductor layer 318, which is the semiconductor layer of the OS transistor, preferably contains at least indium (In). Furthermore, it is preferable that the metal oxide contains at least one of indium (In) or zinc (Zn). Moreover, it is preferable that the metal oxide has two or three elements selected from indium, element M, and zinc. Element M is a metal element or metalloid with a high bond energy with oxygen, for example, a metal element or metalloid with a higher bond energy with oxygen than indium.

[0251] Specific examples of element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, yttrium, and tungsten, and even more preferably gallium. In this specification, metal elements and metalloid elements are sometimes collectively referred to as "metal elements," and the "metal elements" described in this specification may include metalloid elements.

[0252] For example, metal oxides that can be used in the semiconductor layer of an OS transistor include indium oxide (In oxide, indium oxide), indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium tungsten oxide (In-W oxide, also written as "IWO"), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide), gallium zinc oxide (Ga-Zn oxide, also written as "GZO"), and aluminum oxide. Indium zinc oxide (Al-Zn oxide, also written as "AZO"), indium aluminum zinc oxide (In-Al-Zn oxide, also written as "IAZO"), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also written as "IGZO"), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also written as "IGZTO"), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also written as "IGAZO" or "IAGZO"), etc., can be used. Alternatively, silicon-containing indium tin oxide, gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), etc., can be used.

[0253] Examples of crystal structures for metal oxides that function as semiconductors include amorphous (including completely amorphous), CAAC (c-axis-aligned crystalline), nc (nanocrystalline), CAC (cloud-aligned composite), single crystal, and polycrystalline.

[0254] Furthermore, by increasing the ratio of zinc atoms to the sum of the atoms of other metal elements in a metal oxide that functions as a semiconductor, a highly crystalline metal oxide can be obtained, suppressing the diffusion of impurities within the metal oxide. Consequently, fluctuations in the electrical properties of the transistor can be suppressed, improving reliability.

[0255] Furthermore, by increasing the ratio of element M atoms to the sum of the atoms of metal elements among the main constituent elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation caused by oxygen vacancies is suppressed, resulting in a transistor with low off-current. In addition, fluctuations in the electrical characteristics of the transistor are suppressed, and reliability can be improved.

[0256] The field-effect mobility of a transistor can be increased by increasing the ratio of indium atoms to the sum of the total number of atoms of all metal elements contained in the metal oxide. Typically, using single-crystal or polycrystalline indium oxide in the semiconductor layer can significantly increase the field-effect mobility of a transistor. Furthermore, transistors using single-crystal or polycrystalline indium oxide in the semiconductor layer can achieve good frequency characteristics.

[0257] <<Example of Transistor Configuration>> Next, an example of a transistor configuration that can be used in a semiconductor device according to one aspect of the present invention will be described.

[0258] Various transistor structures can be used as transistors according to one aspect of the present invention. For example, various transistor structures can be used, such as top-gate type (e.g., planar type and staggered type), bottom-gate type (e.g., inverse planar type and inverse staggered type), dual-gate type (structure in which gates are arranged on both sides (e.g., top and bottom) of the channel formation region), FIN type, TRI-GATE type, GAA type (gate all-around type), and CFET type (complementary field effect transistor type). In addition, for example, a vertical transistor (a transistor whose channel length direction has a component in the vertical direction (also called the height direction or the direction perpendicular to the surface to which it is formed)) can be used.

[0259] <Transistor Configuration Example 1> Figures 33A, 33B, and 33C are a plan view and a cross-sectional view of a transistor 751 that can be used in a semiconductor device according to one aspect of the present invention. Transistor 751 can be applied to, for example, transistors Tr21 to Tr24.

[0260] Figure 33A is a plan view of transistor 751. Figures 33B and 33C are cross-sectional views of transistor 751. Here, Figure 33B is a cross-sectional view of the area indicated by the dashed line A1-A2 in Figure 33A, and is also a cross-sectional view of transistor 751 in the channel length direction. Similarly, Figure 33C is a cross-sectional view of the area indicated by the dashed line A3-A4 in Figure 33A, and is also a cross-sectional view of transistor 751 in the channel width direction. Note that in the plan view of Figure 33A, some elements have been omitted for clarity.

[0261] As shown in Figures 33A to 33C, the transistor 751 has a metal oxide 220a disposed on top of a substrate (not shown), a metal oxide 220b disposed on top of the metal oxide 220a, conductive layers 242a and 242b disposed on top of the metal oxide 220b at a distance from each other, an insulating layer 280 disposed on the conductive layers 242a and 242b with an opening formed between the conductive layers 242a and 242b, a conductive layer 260 disposed in the opening, and an insulating layer 250 disposed between the metal oxide 220b, the conductive layer 242a, the conductive layer 242b, the insulating layer 280, and the conductive layer 260. Here, as shown in Figures 33B and 33C, it is preferable that the upper surface of the conductive layer 260 substantially coincides with the upper surfaces of the insulating layer 250, the insulating layer 254, and the insulating layer 280. In the following, metal oxide 220a and metal oxide 220b may be collectively referred to as metal oxide 220. Also, conductive layer 242a and conductive layer 242b may be collectively referred to as conductive layer 242.

[0262] When semiconductor devices such as transistors are mounted on a substrate, there are no major restrictions on the material used for the substrate. Depending on the purpose, the material can be determined by considering factors such as the presence or absence of light transmission and heat resistance sufficient to withstand heat treatment. For example, an insulating substrate, a semiconductor substrate, or a conductive substrate can be used. As insulating substrates, for example, glass substrates such as barium borosilicate glass and aluminoborosilicate glass, ceramic substrates, quartz substrates, sapphire substrates, and stabilized zirconia substrates (such as yttria-stabilized zirconia substrates) can be used. In addition, semiconductor substrates, flexible substrates, and resin substrates can be used.

[0263] Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, there are semiconductor substrates having insulating regions within the aforementioned semiconductor substrates, such as SOI substrates. In addition, the semiconductor substrate may be a single-crystal semiconductor or a polycrystalline semiconductor.

[0264] Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, there are substrates containing metal nitrides and substrates containing metal oxides. Furthermore, there are substrates in which a conductive layer or semiconductor layer is provided on an insulating substrate, substrates in which a conductive layer or insulating layer is provided on a semiconductor substrate, and substrates in which a semiconductor layer or insulating layer is provided on a conductive substrate.

[0265] Examples of materials that can be used for flexible substrates or resin substrates include polyesters such as polyethylene terephthalate (PET) and polyethylene naphthalate (PEN), polyacrylonitrile, acrylic resin, polyimide, polymethyl methacrylate, polycarbonate (PC), polyethersulfone (PES), polyamide (nylon, aramid, etc.), polysiloxane, cycloolefin resin, polystyrene, polyamide-imide, polyurethane, polyvinyl chloride, polyvinylidene chloride, polypropylene, polytetrafluoroethylene (PTFE), ABS resin, and cellulose nanofiber.

[0266] By using the above material as a substrate, a lightweight semiconductor device can be provided. Furthermore, by using the above material as a substrate, a semiconductor device that is resistant to impact can be provided. Furthermore, by using the above material as a substrate, a semiconductor device that is less prone to damage can be provided.

[0267] Alternatively, it is possible to use substrates on which elements are mounted. Elements mounted on the substrate include capacitive elements, resistive elements, switch elements, light-emitting elements, and memory elements.

[0268] As shown in Figures 33A to 33C, it is preferable that an insulating layer 254 is placed between the insulating layer 224, the metal oxide 220a, the metal oxide 220b, the conductive layer 242a, and the conductive layer 242b, and the insulating layer 280. Here, as shown in Figures 33B and 33C, it is preferable that the insulating layer 254 is in contact with the upper and side surfaces of the conductive layer 242a, the upper and side surfaces of the conductive layer 242b, the side surfaces of the metal oxide 220a and the metal oxide 220b, and the side surfaces of the insulating layer 224.

[0269] Although the transistor 751 is shown with a configuration in which two layers of metal oxide 220a and metal oxide 220b are stacked in and near the channel formation region, the present invention is not limited to this. For example, a single-layer structure of metal oxide or a stacked structure of three or more layers can be provided. Furthermore, it is also possible for each of the metal oxide 220a and metal oxide 220b to have a stacked structure of two or more layers.

[0270] Here, the conductive layer 260 functions as the gate electrode of the transistor, and the conductive layers 242a and 242b function as the source electrode or drain electrode, respectively. As described above, the conductive layer 260 is formed to be embedded in the opening of the insulating layer 280 and in the region sandwiched between the conductive layers 242a and 242b. Here, the arrangement of the conductive layer 260, conductive layer 242a, and conductive layer 242b is self-aligned with respect to the opening of the insulating layer 280. In other words, in the transistor 751, the gate electrode can be self-aligned between the source electrode and the drain electrode. Therefore, since the conductive layer 260 can be formed without providing a positional margin, the occupied area of ​​the transistor 751 can be reduced. This reduces the occupied area of ​​the semiconductor device. Furthermore, the integration density of the semiconductor device can be increased.

[0271] As shown in Figures 33A to 33C, the conductive layer 260 preferably has a conductive layer 260a provided inside the insulating layer 250 and a conductive layer 260b provided so as to be embedded inside the conductive layer 260a. In the transistor 751, the conductive layer 260 is shown as a two-layer laminated structure, but the present invention is not limited thereto. For example, the conductive layer 260 may be a single-layer structure or a laminated structure of three or more layers.

[0272] The transistor 751 preferably has an insulating layer 214 disposed on a substrate (not shown), an insulating layer 216 disposed on the insulating layer 214, an insulating layer 222 disposed on the insulating layer 216, and an insulating layer 224 disposed on the insulating layer 222. It is preferable that a metal oxide 220a is disposed on the insulating layer 224.

[0273] It is preferable that insulating layers 274 and 281, which function as interlayer films, are arranged on the transistor 751. Here, it is preferable that the insulating layer 274 is arranged in contact with the upper surfaces of the conductive layer 260, insulating layer 250, insulating layer 254, and insulating layer 280.

[0274] It is preferable that insulating layers 222, 254, and 274 have a function to suppress the diffusion of hydrogen (for example, at least one such as hydrogen atoms or hydrogen molecules). For example, it is preferable that insulating layers 222, 254, and 274 have lower hydrogen permeability than insulating layers 224, 250, and 280. It is also preferable that insulating layers 222 and 254 have a function to suppress the diffusion of oxygen (for example, at least one such as oxygen atoms or oxygen molecules). For example, it is preferable that insulating layers 222 and 254 have lower oxygen permeability than insulating layers 224, 250, and 280.

[0275] Here, the insulating layer 224, the metal oxide 220, and the insulating layer 250 are separated by the insulating layer 222 and the insulating layer 274. Therefore, it is possible to suppress the diffusion of impurities such as hydrogen and excess oxygen contained in the layer above the insulating layer 274 and the layer below the insulating layer 222 into the insulating layer 224, the metal oxide 220, and the insulating layer 250.

[0276] It is preferable that a conductive layer 245 (conductive layer 245a and conductive layer 245b) is provided to connect to the transistor 751 and function as a plug. Furthermore, an insulating layer 241 (insulating layer 241a and insulating layer 241b) is provided in contact with the side surface of the conductive layer 245 that functions as a plug. That is, the insulating layer 241 is provided in contact with the inner wall of the opening of the insulating layer 254, insulating layer 280, insulating layer 274, and insulating layer 281. Additionally, a first conductive layer of the conductive layer 245 is provided in contact with the side surface of the insulating layer 241, and a second conductive layer of the conductive layer 245 is provided further inside. Here, the height of the upper surface of the conductive layer 245 and the height of the upper surface of the insulating layer 281 can be approximately the same. While the transistor 751 shows a configuration in which the first conductive layer and the second conductive layer of the conductive layer 245 are stacked, the present invention is not limited to this. For example, the conductive layer 245 can be provided as a single layer or as a laminated structure of three or more layers. When a structure has a laminated structure, ordinal numbers may be assigned to distinguish the layers in the order of formation.

[0277] In transistor 751, it is preferable to use an oxide semiconductor for the metal oxide 220 (metal oxide 220a and metal oxide 220b) including the channel formation region.

[0278] Furthermore, the thickness of the metal oxide 220b in the region that does not overlap with the conductive layer 242 may be thinner than the thickness of the metal oxide 220b in the region that overlaps with the conductive layer 242. This is formed by removing a portion of the upper surface of the metal oxide 220b when forming the conductive layers 242a and 242b. When a conductive film that will become the conductive layer 242 is formed on the upper surface of the metal oxide 220b, a region with low resistance may be formed near the interface with the conductive film. In this way, by removing the region with low resistance located between the conductive layers 242a and 242b on the upper surface of the metal oxide 220b, it is possible to prevent the formation of a channel in that region.

[0279] The insulating layer 214 preferably functions as a barrier insulating film that suppresses the diffusion of impurities such as water or hydrogen from the substrate side to the transistor 751. Therefore, the insulating layer 214 is preferably composed of hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２O, NO, NO ２ It is preferable to use an insulating material that has the function of suppressing the diffusion of impurities such as copper atoms (i.e., the above impurities are less permeable). Alternatively, it is preferable to use an insulating material that has the function of suppressing the diffusion of oxygen (i.e., at least one such as oxygen atoms or oxygen molecules) (i.e., the above oxygen is less permeable).

[0280] For example, it is preferable to use aluminum oxide or silicon nitride as the insulating layer 214. This suppresses the diffusion of impurities such as water or hydrogen from the substrate side to the transistor 751 side beyond the insulating layer 214. Alternatively, it suppresses the diffusion of oxygen contained in the insulating layer 224, etc., toward the substrate side beyond the insulating layer 214.

[0281] The insulating layers 216, 280, and 281, which function as interlayer films, preferably have a lower dielectric constant than the insulating layer 214. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance between wiring can be reduced. For example, silicon oxide, silicon oxynitride, silicon nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, or porous silicon oxide may be used as the insulating layers 216, 280, and 281.

[0282] Here, it is preferable that the insulating layer 224 in contact with the metal oxide 220 deoxygenates upon heating. In this specification, oxygen deoxygenated upon heating is sometimes referred to as excess oxygen. For example, the insulating layer 224 may be made of silicon oxide or silicon oxynitride, or the like, as appropriate. By providing an insulating layer containing oxygen in contact with the metal oxide 220, oxygen deficiency in the metal oxide 220 can be reduced, and the reliability of the transistor 751 can be improved.

[0283] Specifically, it is preferable to use an oxide material from which some oxygen is desorbed by heating as the insulating layer 224.

[0284] The insulating layer 222, like the insulating layer 214, preferably functions as a barrier insulating film that suppresses the diffusion of impurities such as water or hydrogen from the substrate side to the transistor 751. For example, it is preferable that the insulating layer 222 has lower hydrogen permeability than the insulating layer 224. By surrounding the insulating layer 224, the metal oxide 220, and the insulating layer 250, etc., with the insulating layer 222, insulating layer 254, and insulating layer 274, it is possible to suppress the intrusion of impurities such as water or hydrogen into the transistor 751 from the outside.

[0285] Furthermore, it is preferable that the insulating layer 222 has a function to suppress the diffusion of oxygen (for example, at least one such as oxygen atoms or oxygen molecules) (i.e., it is difficult for the above-mentioned oxygen to permeate it). For example, it is preferable that the insulating layer 222 has lower oxygen permeability than the insulating layer 224. It is preferable that the insulating layer 222 has a function to suppress the diffusion of oxygen and impurities, thereby suppressing the diffusion of oxygen contained in the metal oxide 220 toward the substrate side.

[0286] The insulating layer 222 may be an insulating layer containing an oxide of one or both of the insulating materials aluminum and hafnium. Preferably, the insulating layer containing an oxide of one or both of aluminum and hafnium is an insulating layer containing aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). When the insulating layer 222 is formed using such a material, the insulating layer 222 functions as a layer that suppresses the release of oxygen from the metal oxide 220 and the incorporation of impurities such as hydrogen from the periphery of the transistor 751 into the metal oxide 220.

[0287] Alternatively, these insulating layers can be enriched with, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide. These insulating layers can also be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride can be laminated onto the insulating layers. For example, the insulating layer 222 can be a structure in which silicon nitride, silicon oxide, and aluminum oxide are laminated in this order in three layers.

[0288] The insulating layer 222 is made of, for example, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO). ３ ) or (Ba, Sr)TiO ３ It is possible to use insulating layers containing so-called high-k materials such as (BST) in single-layer or multi-layer configurations. As transistors become smaller and more highly integrated, thinning of the gate insulating layer can sometimes lead to problems such as leakage current. By using a high-k material in the insulating layer that functions as the gate insulating layer, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0289] Furthermore, the insulating layer 222 and insulating layer 224 may also have a laminated structure of two or more layers. In that case, the laminated structure is not limited to being made of the same material, but can also be made of different materials. For example, it is possible to have an insulating layer similar to insulating layer 224 provided below insulating layer 222.

[0290] The metal oxide 220 comprises a metal oxide 220a and a metal oxide 220b on the metal oxide 220a. By having the metal oxide 220a below the metal oxide 220b, the diffusion of impurities from structures formed below the metal oxide 220a to the metal oxide 220b can be suppressed.

[0291] Furthermore, it is preferable that the metal oxide 220 contains indium (In). Also, for example, it is preferable that the metal oxide 220 has a laminated structure of multiple oxide layers with different atomic ratios of each metal atom. For example, if the metal oxide 220 contains indium (In) and element M, it is preferable that the ratio of the number of atoms of element M contained in metal oxide 220a to the total number of atoms of all elements constituting metal oxide 220a is higher than the ratio of the number of atoms of element M contained in metal oxide 220b to the total number of atoms of all elements constituting metal oxide 220b. Furthermore, it is preferable that the atomic ratio of element M contained in metal oxide 220a to In is higher than the atomic ratio of element M contained in metal oxide 220b to In.

[0292] It is preferable that the energy at the lower end of the conduction band of metal oxide 220a is higher than the energy at the lower end of the conduction band of metal oxide 220b. In other words, it is preferable that the electron affinity of metal oxide 220a is smaller than that of metal oxide 220b. Specifically, it is preferable that the ratio of the number of atoms of element M contained in metal oxide 220a to the total number of atoms of all elements constituting metal oxide 220a is higher than the ratio of the number of atoms of element M contained in metal oxide 220b to the total number of atoms of all elements constituting metal oxide 220b. Furthermore, it is preferable that the atomic ratio of element M contained in metal oxide 220a to In is higher than the atomic ratio of element M contained in metal oxide 220b to In.

[0293] Here, at the junction of metal oxide 220a and metal oxide 220b, the energy level at the lower end of the conduction band changes smoothly. In other words, the energy level at the lower end of the conduction band at the junction of metal oxide 220a and metal oxide 220b can be said to change continuously or be continuously joined. To achieve this, it is preferable to lower the defect level density of the mixed layer formed at the interface between metal oxide 220a and metal oxide 220b.

[0294] Specifically, by having a common element other than oxygen (which serves as the main component) between metal oxide 220a and metal oxide 220b, a mixed layer with a low defect level density can be formed. For example, when metal oxide 220b is In-Ga-Zn oxide, it is preferable to use In-Ga-Zn oxide, Ga-Zn oxide, gallium oxide, etc. as metal oxide 220a. Furthermore, metal oxide 220a can also be in a layered structure. For example, a layered structure of In-Ga-Zn oxide and Ga-Zn oxide on the In-Ga-Zn oxide, or a layered structure of In-Ga-Zn oxide and gallium oxide on the In-Ga-Zn oxide can be used. In other words, it is also possible to use a layered structure of In-Ga-Zn oxide and an oxide that does not contain In as metal oxide 220a.

[0295] Specifically, as metal oxide 220a, a metal oxide with an atomic ratio of In:Ga:Zn = 1:3:4 or nearby, or 1:1:0.5 or nearby, may be used. Similarly, as metal oxide 220b, a metal oxide with an atomic ratio of In:Ga:Zn = 4:2:3 or nearby, or 3:1:2 or nearby, or 1:1:1 or nearby, may be used. Furthermore, specific examples of layered structures for the metal oxide 220a include a layered structure of In:Ga:Zn = 4:2:3 [atomic ratio] or nearby and Ga:Zn = 2:1 [atomic ratio] or nearby, a layered structure of In:Ga:Zn = 4:2:3 [atomic ratio] or nearby and Ga:Zn = 2:5 [atomic ratio] or nearby, and a layered structure of In:Ga:Zn = 4:2:3 [atomic ratio] or nearby and gallium oxide.

[0296] In this case, the main carrier pathway is through the metal oxide 220b. By configuring the metal oxide 220a as described above, the defect level density at the interface between the metal oxide 220a and the metal oxide 220b can be reduced. As a result, the influence of interface scattering on carrier conduction is reduced, and the transistor 751 can obtain a high on-current and high frequency characteristics.

[0297] A conductive layer 242 (conductive layer 242a and conductive layer 242b) is provided on the metal oxide 220b, which functions as a source electrode and a drain electrode. It is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum as the conductive layer 242, or an alloy containing the above metal elements, or an alloy combining the above metal elements. For example, it is preferable to use tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen.

[0298] By providing the conductive layer 242 in contact with the metal oxide 220, the oxygen concentration in the vicinity of the conductive layer 242 of the metal oxide 220 may be reduced. In addition, a metal compound layer containing the metal contained in the conductive layer 242 and the components of the metal oxide 220 may be formed in the vicinity of the conductive layer 242 of the metal oxide 220. In such cases, the carrier concentration increases in the region of the metal oxide 220 near the conductive layer 242, and this region becomes a low-resistance region.

[0299] Here, the region between the conductive layer 242a and the conductive layer 242b is formed superimposed on the opening of the insulating layer 280. This allows the conductive layer 260 to be positioned self-aligned between the conductive layer 242a and the conductive layer 242b.

[0300] The insulating layer 250 functions as a gate insulating layer. The insulating layer 250 can be made of silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, or silicon oxide with vacancies. Silicon oxide and silicon oxide nitride are particularly preferred because they are stable to heat.

[0301] Similar to the insulating layer 224, it is preferable that the insulating layer 250 has a reduced concentration of impurities such as water or hydrogen. The thickness of the insulating layer 250 is preferably 1 nm or more and 20 nm or less.

[0302] A metal oxide can be provided between the insulating layer 250 and the conductive layer 260. Preferably, this metal oxide suppresses oxygen diffusion from the insulating layer 250 to the conductive layer 260. This suppresses oxidation of the conductive layer 260 by oxygen in the insulating layer 250.

[0303] The metal oxide may function as part of the gate insulating layer. Therefore, when silicon oxide or silicon oxynitride is used for the insulating layer 250, it is preferable to use a metal oxide that is a high-k material with a high dielectric constant. By making the gate insulating layer a laminated structure of the insulating layer 250 and the metal oxide, a laminated structure that is stable against heat and has a high dielectric constant can be made. Therefore, it becomes possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulating layer. Furthermore, it becomes possible to make the insulating layer that functions as a gate insulating layer thinner.

[0304] Specifically, metal oxides containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, or magnesium can be used. In particular, it is preferable to use insulators containing oxides of aluminum, hafnium, or both, such as aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate).

[0305] The conductive layer 260a preferably uses a conductive layer material having a function of suppressing the diffusion of impurities such as the above-described hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N ２ O, NO, NO ２ etc.), copper atoms, etc. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0306] Since the conductive layer 260a has a function of suppressing the diffusion of oxygen, it is possible to suppress the conductive layer 260b from being oxidized by oxygen contained in the insulating layer 250 and the conductivity from decreasing. As the conductive material having a function of suppressing the diffusion of oxygen, for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc. are preferably used.

[0307] The conductive layer 260b preferably uses a conductive material mainly composed of tungsten, copper, or aluminum. Also, since the conductive layer 260 also functions as a wiring, it is preferable to use a conductive layer with high conductivity. For example, a conductive material mainly composed of tungsten, copper, or aluminum can be used. Also, the conductive layer 260b may have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above conductive material can also be used.

[0308] As shown in FIGS. 33A and 33C, in a region that does not overlap with the conductive layer 242 of the metal oxide 220b, in other words, in the channel formation region of the metal oxide 220, the side surface of the metal oxide 220 is arranged to be covered by the conductive layer 260. Thereby, the electric field of the conductive layer 260 functioning as the first gate electrode can be easily applied to the side surface of the metal oxide 220. Therefore, the on-current of the transistor 751 can be increased and the frequency characteristics can be improved.

[0309] The insulating layer 254 preferably functions as a barrier insulating film that suppresses the diffusion of impurities such as water or hydrogen from the insulating layer 280 to the transistor 751, similar to the insulating layer 214. For example, it is preferable that the insulating layer 254 has lower hydrogen permeability than the insulating layer 224. Furthermore, as shown in Figures 33B and 33C, it is preferable that the insulating layer 254 is in contact with the upper and side surfaces of the conductive layer 242a, the upper and side surfaces of the conductive layer 242b, the side surfaces of the metal oxide 220a and metal oxide 220b, and the upper surface of the insulating layer 224. With this configuration, it is possible to suppress the penetration of hydrogen contained in the insulating layer 280 into the metal oxide 220 from the upper or side surfaces of the conductive layer 242a, conductive layer 242b, metal oxide 220a, metal oxide 220b, and insulating layer 224.

[0310] Furthermore, it is preferable that the insulating layer 254 has a function to suppress the diffusion of oxygen (for example, at least one such as oxygen atoms or oxygen molecules) (i.e., it is difficult for the above-mentioned oxygen to permeate through it). For example, it is preferable that the insulating layer 254 has lower oxygen permeability than the insulating layer 280 or the insulating layer 224.

[0311] The insulating layer 254 is preferably formed using a sputtering method. By forming the insulating layer 254 using a sputtering method in an oxygen-containing atmosphere, oxygen can be added to the vicinity of the region of the insulating layer 224 that is in contact with the insulating layer 254. This allows oxygen to be supplied from this region to the metal oxide 220 via the insulating layer 224. Here, the insulating layer 254 has a function to suppress upward diffusion of oxygen, thereby preventing oxygen from diffusing from the metal oxide 220 to the insulating layer 280. In addition, the insulating layer 222 has a function to suppress downward diffusion of oxygen, thereby preventing oxygen from diffusing from the metal oxide 220 to the substrate side. In this way, oxygen is supplied to the channel formation region of the metal oxide 220. This reduces oxygen deficiency in the metal oxide 220 and suppresses normally-on formation of the transistor.

[0312] As the insulating layer 254, for example, an insulating layer containing an oxide of either or both aluminum and hafnium can be used. It is preferable to use aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) as the insulating layer containing an oxide of either or both aluminum and hafnium.

[0313] The insulating layer 280 is provided on the insulating layer 224, the metal oxide 220, and the conductive layer 242 via the insulating layer 254. For example, the insulating layer 280 is preferably made of silicon oxide, silicon oxynitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, or silicon oxide with vacancies. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Materials such as silicon oxide, silicon oxynitride, and silicon oxide with vacancies are particularly preferred because they can easily form regions containing oxygen that is desorbed by heating.

[0314] It is preferable that the concentration of impurities such as water or hydrogen in the insulating layer 280 is reduced. It is also preferable that the upper surface of the insulating layer 280 is flattened. For example, the flatness of the upper surface of the insulating layer 280 can be improved by performing a chemical mechanical polishing (CMP) treatment. Furthermore, by performing a CMP treatment, the positions of the upper surfaces of the insulating layer 280, the insulating layer 250, and the conductive layer 260 can be aligned or nearly aligned. By performing a CMP treatment, the surface irregularities of the sample can be reduced, and the coverage of the insulating layer and conductive layer formed thereafter can be improved.

[0315] The insulating layer 274 preferably functions as a barrier insulating film that suppresses the diffusion of impurities such as water or hydrogen into the insulating layer 280 from above, similar to the insulating layer 214. For example, the insulating layer 274 can be an insulating layer that can be used for the insulating layer 214, insulating layer 254, etc.

[0316] It is preferable to provide an insulating layer 281 that functions as an interlayer film on top of the insulating layer 274. It is preferable that the insulating layer 281, like the insulating layer 224, has a reduced concentration of impurities such as water or hydrogen in the film.

[0317] Conductive layers 245a and 245b are placed in openings formed in insulating layers 281, 274, 280, and 254. Conductive layer 245a has a region that overlaps with conductive layer 242a and a portion of the metal oxide 220 when viewed from the Z direction. Conductive layer 245b has a region that overlaps with conductive layer 242b and another portion of the metal oxide 220 when viewed from the Z direction. Preferably, the upper surfaces of conductive layers 245a and 245b are at the same position as or approximately the same as the upper surface of insulating layer 281.

[0318] Furthermore, insulating layer 241a is provided in contact with the inner wall of the opening of insulating layer 281, insulating layer 274, insulating layer 280, and insulating layer 254, and the first conductive layer of conductive layer 245a is formed in contact with its side surface. Conductive layer 242a is located in at least a portion of the bottom of the opening, and conductive layer 245a is in contact with conductive layer 242a. Similarly, insulating layer 241b is provided in contact with the inner wall of the opening of insulating layer 281, insulating layer 274, insulating layer 280, and insulating layer 254, and the first conductive layer of conductive layer 245b is formed in contact with its side surface. Conductive layer 242b is located in at least a portion of the bottom of the opening, and conductive layer 245b is in contact with conductive layer 242b.

[0319] It is preferable that conductive layers 245a and 245b be made of conductive materials mainly composed of tungsten, copper, or aluminum. Furthermore, conductive layers 245a and 245b can also be arranged in a laminated structure.

[0320] When the conductive layer 245 has a laminated structure, it is preferable to use a conductive material that has the function of suppressing the diffusion of impurities such as water or hydrogen in the conductive layers that are in contact with the metal oxide 220a, metal oxide 220b, conductive layer 242, insulating layer 254, insulating layer 280, insulating layer 274, and insulating layer 281. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide. Furthermore, the conductive material that has the function of suppressing the diffusion of impurities such as water or hydrogen can be used in a single layer or laminated form. By using this conductive material, it is possible to suppress the absorption of oxygen added to the insulating layer 280 into the conductive layers 245a and 245b. In addition, it is possible to suppress the diffusion of impurities such as water or hydrogen from the layers above the insulating layer 281 into the metal oxide 220 through the conductive layers 245a and 245b.

[0321] For insulating layers 241a and 241b, for example, insulating layers that can be used for insulating layer 254 may be used. Since insulating layers 241a and 241b are provided in contact with insulating layer 254, it is possible to suppress the diffusion of impurities such as water or hydrogen from insulating layer 280, etc., into the metal oxide 220 through conductive layer 245a and conductive layer 245b. Furthermore, it is possible to suppress the absorption of oxygen contained in insulating layer 280 into conductive layer 245a and conductive layer 245b.

[0322] Although not shown in the figures, conductive layers that function as wiring can be placed in contact with the upper surfaces of conductive layer 245a and conductive layer 245b. The conductive layers that function as wiring preferably use a conductive material mainly composed of tungsten, copper, or aluminum. Furthermore, the conductive layers can be formed in a laminated structure. For example, they can be laminated with titanium or titanium nitride and the conductive material. The conductive layers can also be formed so as to be embedded in openings provided in the insulating layer.

[0323] Furthermore, insulating layer 214 corresponds to insulating layer 312, insulating layer 216 corresponds to insulating layer 314, insulating layer 222 corresponds to insulating layer 316, insulating layer 224 corresponds to insulating layer 317, and metal oxide 220 corresponds to semiconductor layer 318. Conductive layer 242a corresponds to one of the pair of conductive layers 319, and conductive layer 242b corresponds to the other of the pair of conductive layers 319. Furthermore, insulating layer 254 corresponds to insulating layer 320, insulating layer 280 corresponds to insulating layer 321, insulating layer 274 corresponds to insulating layer 323, and insulating layer 281 corresponds to insulating layer 324. Furthermore, conductive layer 245a corresponds to conductive layer 326, and conductive layer 245b corresponds to conductive layer 325.

[0324] <Transistor Configuration Example 2> Next, we will describe transistor 752, which is a modified version of transistor 751. Figures 34A, 34B, and 34C are a plan view and a cross-sectional view of transistor 752. To reduce repetition in the explanation, this embodiment will mainly describe the differences between transistor 752 and transistor 751.

[0325] Transistor 752 has a configuration in which a conductive layer 205 is added to transistor 751. The conductive layer 205 is arranged to have an overlapping region with the metal oxide 220 and the conductive layer 260.

[0326] The conductive layer 205 comprises a conductive layer 205a and a conductive layer 205b. The conductive layer 205a is provided in contact with the bottom surface and side wall of an opening provided in the insulating layer 216. The conductive layer 205b is provided so as to be embedded in a recess formed in the conductive layer 205a. Here, the height of the upper surface of the conductive layer 205b is approximately equal to the height of the upper surface of the conductive layer 205a and the height of the upper surface of the insulating layer 216.

[0327] The conductive layer 205a contains hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ It is preferable to use a conductive material that has the function of suppressing the diffusion of impurities such as copper atoms. Alternatively, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one such as an oxygen atom or oxygen molecule).

[0328] By using a conductive material that has the function of reducing hydrogen diffusion in the conductive layer 205a, it is possible to suppress the diffusion of impurities such as hydrogen contained in the insulating layer 214 and insulating layer 216 into the metal oxide 220 via the conductive layer 205b, etc. Furthermore, by using a conductive material that has the function of suppressing oxygen diffusion in the conductive layer 205a, it is possible to suppress the phenomenon of oxidation of the conductive layer 205b and a decrease in conductivity. As a conductive material that has the function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc. Therefore, a single layer or a laminate of the above conductive material is preferred for the conductive layer 205a. For example, titanium nitride can be used for the conductive layer 205a.

[0329] Furthermore, it is preferable to use a conductive material mainly composed of tungsten, copper, or aluminum for the conductive layer 205b. For example, tungsten may be used for the conductive layer 205b.

[0330] In transistor 752, both conductive layer 260 and conductive layer 205 can function as gate electrodes. In transistor 752, when one of the conductive layer 260 or conductive layer 205 is referred to as the "gate electrode," the other may be referred to as the "back gate electrode." Also, when one of the conductive layer 260 or conductive layer 205 is referred to as the "first gate electrode," the other may be referred to as the "second gate electrode."

[0331] For example, the threshold voltage of transistor 751 can be controlled by independently changing the potential applied to conductive layer 205, rather than in conjunction with the potential applied to conductive layer 260. In particular, by applying a negative potential to conductive layer 205, it is possible to increase the Vth of transistor 751 and reduce the off-current. Therefore, applying a negative potential to conductive layer 205 reduces the drain current when the potential applied to conductive layer 260 is 0V compared to not applying a negative potential.

[0332] The conductive layer 205 should be larger than the channel-forming region in the metal oxide 220. In particular, as shown in Figure 34C, it is preferable that the conductive layer 205 extends beyond the region outside the end that intersects the channel width direction of the metal oxide 220. That is, it is preferable that the conductive layer 205 and the conductive layer 260 are superimposed on the outside of the side surface in the channel width direction of the metal oxide 220, with an insulating layer in between.

[0333] With the above configuration, the electric field of the conductive layer 260, which functions as the first gate electrode, and the electric field of the conductive layer 205, which functions as the second gate electrode, can surround the channel formation region of the metal oxide 220, which functions as a semiconductor layer, with conductive layers. By surrounding the channel formation region with conductive layers, the aforementioned electric field shielding function is obtained. Therefore, variations in characteristics between transistors are reduced, and the transistors can be operated stably.

[0334] The conductive layer 205 can also be extended beyond the metal oxide 220 and used as wiring. However, it is not limited to this, and it is also possible to configure it so that a conductive layer that functions as wiring is provided below the conductive layer 205.

[0335] Furthermore, it is preferable that the insulating layer 222 formed on the conductive layer 205 has lower oxygen permeability than the insulating layer 224. The insulating layer 222 has a function of suppressing the diffusion of oxygen and impurities, thereby suppressing the reaction of the conductive layer 205 with the oxygen present in the insulating layer 224 or the metal oxide 220.

[0336] <Transistor Configuration Example 3> Figure 35A is a plan view of transistor 753, which has a different configuration from transistors 751 and 752. Figure 35B is a cross-sectional view corresponding to the cutting line shown A1-A2 in Figure 35A. In the following, we will mainly explain the parts that differ from the above. Therefore, explanations of parts that overlap with the above may be omitted.

[0337] The transistor 753 has a conductive layer 255 on top of an insulating element layer 201. Furthermore, it has an insulating layer 257 on top of the conductive layer 255, an insulating layer 258 on top of the insulating layer 257, and an insulating layer 259 on top of the insulating layer 258. In this specification, the insulating layers 257, 258, and 259 may be collectively referred to as an insulating layer 256 or a spacer layer. Additionally, it has a conductive layer 261 on top of the insulating layer 259.

[0338] Furthermore, in a region overlapping with a portion of the conductive layer 255, an opening 262 is provided that penetrates the conductive layer 261, the insulating layer 259, the insulating layer 258, and the insulating layer 257. In addition, a metal oxide 220 is provided to cover the inner wall of the opening 262.

[0339] The metal oxide 220 has a region that overlaps with the bottom of the opening 262 and a region that overlaps with the side of the opening 262. That is, the metal oxide 220 has a region that is in contact with the insulating layer 256 inside the opening 262. The metal oxide 220 also has a region that is in contact with the conductive layer 255 and a region that is in contact with the conductive layer 261 inside the opening 262.

[0340] Furthermore, an insulating layer 250 is provided on top of the insulating layer 259, the conductive layer 261, and the metal oxide 220. A conductive layer 265 is also provided on top of the insulating layer 250. The conductive layer 265 has a region that overlaps with the metal oxide 220. The conductive layer 265 has a region that overlaps with the metal oxide 220 via the insulating layer 250. The conductive layer 265 functions as a gate electrode. Therefore, the conductive layer 265 corresponds to the conductive layer 260 in transistors 751 and 752.

[0341] Furthermore, each of the insulating layer 250 and the conductive layer 265 has a region that overlaps with the opening 262. Also, each of the insulating layer 250 and the conductive layer 265 has a region that overlaps with the inside of the opening 262. Inside the opening 262, the metal oxide 220 has a region that overlaps with the conductive layer 265 via the insulating layer 250, and a region that overlaps with the side surface of the opening 262 (the side surface of the insulating layer 256).

[0342] Furthermore, an insulating layer 285 is provided on top of the insulating layer 250. It is preferable that the upper surface of the insulating layer 285 is flat. Alternatively, it is preferable that the heights (positions in the Z direction) of the upper surfaces of the insulating layer 285 and the conductive layer 265 coincide or substantially coincide. For example, the flatness of the upper surface of the insulating layer 285 can be improved by performing CMP treatment. Also, by performing CMP treatment, the positions of the upper surfaces of the insulating layer 285 and the conductive layer 265 can be made to coincide or substantially coincide. By performing CMP treatment, surface irregularities of the sample can be reduced, thereby improving the coverage of the insulating layer and conductive layer formed thereafter.

[0343] Furthermore, when an oxide semiconductor is used for the metal oxide 220, it is preferable that the conductive layer 255 and the conductive layer 261 in contact with the metal oxide 220 use a conductive material that converts the oxide semiconductor to n-type. For example, a conductive material containing nitrogen may be used. For example, a conductive material containing titanium or tantalum and nitrogen may be used. It is also possible to provide other conductive materials on top of the conductive material containing nitrogen.

[0344] Furthermore, when an oxide semiconductor is used for the metal oxide 220, it is preferable to use a material with reduced hydrogen and containing oxygen for the insulating layer 258. For example, a material containing silicon and oxygen may be used. Specifically, silicon oxide or silicon oxynitride may be used. Since hydrogen is an impurity element in oxide semiconductors, the contact between the oxide semiconductor metal oxide 220 and the hydrogen-reduced insulating layer 258 makes it less likely for the metal oxide 220 to become n-type. In addition, the contact between the oxide semiconductor metal oxide 220 and the oxygen-containing insulating layer 258 reduces oxygen vacancies in the metal oxide 220, stabilizing the transistor's characteristics and improving reliability.

[0345] Furthermore, when an oxide semiconductor is used for the metal oxide 220, the insulating layer 258 may contain excess oxygen. In this specification, excess oxygen refers to oxygen that is desorbed by heating. A material that desorbs oxygen by heating is one in which the amount of oxygen desorbed, converted to oxygen atoms, is 1.0 × 10¹⁶ by TDS (Thermal Desorption Spectroscopy) analysis. １８ atoms / cm ３Preferably 1.0 × 10 １９ atoms / cm ３ More preferably 2.0 × 10 １９ atoms / cm ３ The above or 3.0 x 10 ２０ atoms / cm ３ The material is as described above. Furthermore, the surface temperature of the film during the TDS analysis is preferably in the range of 100°C to 700°C or 100°C to 500°C.

[0346] Furthermore, when using a material containing excess oxygen for the insulating layer 258, it is preferable to use materials that are impermeable to oxygen for the insulating layers 257 and 259. Examples of materials that are impermeable to oxygen include oxides containing one or both of aluminum and hafnium, and silicon nitrides. By using materials that are impermeable to oxygen for the insulating layers 257 and 259, excess oxygen contained in the insulating layer 258 is less likely to desorb to the lower or upper layer. Therefore, sufficient oxygen can be supplied to the oxide semiconductor. For example, a configuration having an insulating layer (insulating layer 258) containing silicon and oxygen between two insulating layers (insulating layer 257 and insulating layer 259) containing silicon and nitrogen is preferred.

[0347] Furthermore, when an oxide semiconductor is used for the metal oxide 220, by using a hydrogen-containing material for the insulating layer 257 and the insulating layer 259, hydrogen is supplied to the region of the metal oxide 220 in contact with the insulating layer 257 and the region of the metal oxide 220 in contact with the insulating layer 259, and depending on the composition of the oxide semiconductor used for the metal oxide 220, each region becomes n-type. Therefore, the region of the metal oxide 220 in contact with the conductive layer 261 and the region of the metal oxide 220 in contact with the insulating layer 259 function as either a source region or a drain region. Also, the region of the metal oxide 220 in contact with the conductive layer 255 and the region of the metal oxide 220 in contact with the insulating layer 257 function as either a source region or a drain region.

[0348] The conductive layer 261 functions as either the source electrode or the drain electrode of the transistor 753. The conductive layer 255 functions as the other source electrode or drain electrode of the transistor 753. Therefore, the conductive layer 261 functions as either the conductive layer 242a or the conductive layer 242b in transistors 751 and 752. Also, the conductive layer 255 functions as the other conductive layer 242a or the conductive layer 242b in transistors 751 and 752.

[0349] Transistor 753 is a transistor in which the source electrode and drain electrode are arranged in the Z direction. That is, the source and drain of transistor 753 are positioned at different heights. In other words, the source and drain of transistor 753 are positioned at different locations in the Z direction. Such a transistor is also called a "vertical channel transistor," "vertical transistor," or "VFET (Vertical Field Effect Transistor)."

[0350] In the above configuration, for the VFET transistor 753, the length of the side surface of the insulating layer 158 viewed from the X or Y direction becomes the channel length L (channel length L1) (see Figure 35B). Therefore, the channel length L of the transistor 753 is determined according to the thickness t1 of the insulating layer 258.

[0351] Furthermore, it is possible to use materials that do not contain hydrogen or contain very little hydrogen for the insulating layer 257 and insulating layer 259. When silicon nitride or silicon nitride oxide with very little hydrogen is used for the insulating layer 257 and insulating layer 259, the regions in contact with the insulating layer 257 and the regions in contact with the insulating layer 259 of the metal oxide 220 are not n-type. Therefore, the region of the metal oxide 220 in contact with the conductive layer 261 functions as either a source region or a drain region. Also, the region of the metal oxide 220 in contact with the conductive layer 255 functions as either a source region or a drain region. Furthermore, the region of the metal oxide 220 in contact with the insulating layer 258 functions as a channel-forming region.

[0352] In this case, the sum of the lengths of the sides of insulating layers 257, 258, and 259 as viewed from the X or Y direction becomes the channel length L (channel length L2). Therefore, the channel length L of the transistor 753 is determined according to the thickness t2 obtained by adding the thicknesses of insulating layers 257, 258, and 259. Thus, the transistor 753 has a channel formation region that is aligned with the side surface of the insulating layer 256.

[0353] Furthermore, since the metal oxide 220 is provided in the opening 262, the length of the perimeter of the opening 262 when viewed from the Z direction becomes the channel width W of the transistor 753 (see Figure 35A). The length of the perimeter can be determined, for example, at a point where the thickness t1 of the insulating layer 258 is halfway, or at a point where the thickness t2 is halfway. If necessary, the length of the perimeter at any position of the opening 262 can be used as the channel width W. For example, the length of the perimeter at the bottom of the opening 262 can be used as the channel width W, or the length of the perimeter at the top of the opening 262 can be used as the channel width W. Also, although the contour (planar shape) of the opening 262 when viewed from the Z direction is shown as a circle in Figure 35A, it is not limited to this. For example, the contour of the opening 262 when viewed from the Z direction can be an ellipse, a rectangle, etc.

[0354] Furthermore, in order to improve the coverage of the metal oxide 220, insulating layer 250, and conductive layer 265 formed inside the opening 262, it is preferable to set the taper angle θ of the side surface of the opening 262, that is, the taper angle θ of the side surfaces of the insulating layer 257, insulating layer 258, and insulating layer 259 to 45° or more and less than 90°, preferably 50° or more and 75° or less. Note that the taper angle θ of the side surface of a layer (insulating layer, conductive layer, or semiconductor layer) refers to the angle between the bottom surface and the side surface of the layer (see Figure 35B).

[0355] Vertical transistors can reduce the area occupied by a transistor (also called a "horizontal transistor") in which the channel formation region, source region, and drain region are separately located on the XY plane. Therefore, by using vertical channel transistors in semiconductor devices, the area occupied by the semiconductor device can be reduced. Furthermore, by using vertical channel transistors in semiconductor devices, high integration of the semiconductor device can be achieved.

[0356] Furthermore, in lateral transistors, the channel length was limited by the exposure limit of photolithography. In one aspect of the present invention, the vertical channel transistor allows the channel length to be set by the thickness of the insulating layer 256 or insulating layer 258. Therefore, the channel length of the transistor can be made into an extremely fine structure below the exposure limit of photolithography (for example, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 1 nm or more or 5 nm or more). This increases the on-current of the transistor 753, improving the frequency characteristics. By using a vertical channel transistor, a semiconductor device with a high operating speed can be provided.

[0357] <<Example of Memory Cell Configuration>> Next, we will describe an example of a stacked configuration of a memory cell 100, which is a type of semiconductor device. Figure 36 shows an enlarged example of a stacked configuration of a memory cell 100A, which is a type of memory cell 100. The memory cell 100A has an element layer 20 containing a second memory circuit 120a above an element layer 10 containing a first memory circuit 110. In Figure 36, the configuration shown in Figure 1B is shown as an example of the second memory circuit 120a. To reduce repetition in the explanation, the explanation of the second memory circuit 120a here will be omitted.

[0358] Furthermore, Figure 36 illustrates transistor Tr12 as a transistor included in the first memory circuit 110. Transistor Tr12 is provided on a substrate 371 and has a conductive layer 376 that functions as a gate, an insulating layer 375 that functions as a gate insulating layer, a semiconductor region 373 that is part of the substrate 371, and low-resistance regions 374a and 374b that function as a source region or drain region. Transistor Tr12 can be either a p-channel type transistor or an n-channel type transistor. For example, a single-crystal silicon substrate can be used as the substrate 371.

[0359] In Figure 36, the transistor Tr12 has a convex shape in the semiconductor region 373 (part of the substrate 371) where the channel is formed. Furthermore, a conductive layer 376 covers the side and top surfaces of the semiconductor region 373 via an insulating layer 375. The conductive layer 376 can be made of a material that adjusts the work function. Such a transistor Tr12 is also called a FIN-type transistor because it utilizes the convex portion of the semiconductor substrate. It is also preferable to provide an insulating layer in contact with the upper part of the convex portion, which functions as a mask for forming the convex portion. While this example shows the formation of the convex portion by processing a part of the semiconductor substrate, it is also possible to form a semiconductor film with a convex shape by processing an SOI substrate.

[0360] Note that the configuration of transistor Tr12 shown in Figure 36 is just one example, and is not limited to this configuration. Any transistor with an appropriate configuration can be used depending on the circuit configuration or driving method.

[0361] The element layer 10 and the element layer 20 may be provided with a wiring layer having an interlayer film, wiring, and a plug. Furthermore, multiple wiring layers may be provided depending on the design. Also, in this specification, the wiring and the plug connected to the wiring may be an integrated unit. That is, a portion of the conductive layer may function as wiring, and a portion of the conductive layer may function as a plug.

[0362] For example, on the transistor Tr12, insulating layers 390, 391, 393, and 394 are sequentially stacked as interlayer films. Furthermore, conductive layers 395 and the like are embedded in insulating layers 390, 391, 393, and 394.

[0363] The transistor Tr12 of the first memory circuit 110 is connected to the transistor Tr23 of the second memory circuit 120a via conductive layers 392, 395, 386, etc. Conductive layers 392 and 395 function as contact plugs or wiring.

[0364] Furthermore, the insulating layer, which functions as an interlayer film, also functions as a planarizing film that covers the uneven shape beneath it. For example, the upper surface of the insulating layer 391 may be subjected to CMP treatment or the like to improve its flatness.

[0365] A wiring layer can be provided on the insulating layer 394 and the conductive layer 395. For example, in Figure 36, insulating layers 396, 382, ​​and 384 are sequentially laminated on the insulating layer 394 and the conductive layer 395. The conductive layer 386 is formed on the insulating layer 396, insulating layer 382, ​​and insulating layer 384. The conductive layer 386 functions as a contact plug or wiring.

[0366] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments.

[0367] (Embodiment 4) This embodiment describes an indium oxide film that can be used in the semiconductor layer of a transistor in a memory cell 100 according to one aspect of the present invention.

[0368] In this specification, indium oxide having at least a crystalline portion or crystalline region in the film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystal IO or crystalline IO include single-crystal indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0369] Indium oxide is a semiconductor material with completely different physical properties from oxide semiconductors such as In-Ga-Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0370] The carrier concentration dependence of the hole (Hall) mobility of indium oxide, silicon, and IGZO is described. Figure 37A shows silicon (Si) and indium oxide (InO Ｘ Figure 37B is a schematic diagram of the carrier concentration dependence of hole mobility for IGZO.

[0371] First, as indicated by the arrows in Figure 37B, IGZO tends to exhibit higher hole mobility as the carrier concentration increases. On the other hand, as indicated by the arrows in Figure 37A, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases (see Non-Patent Literature 1). This trend is similar to that of silicon, where the lower the concentration of dopants (impurities) in the material, the less impurity scattering occurs and the higher the hole mobility. In other words, the higher the purity and intrinsic nature of indium oxide, the higher its hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to silicon. Note that the properties of indium oxide shown in Figure 37A are assumed to be those of a single crystal. Therefore, when indium oxide is not a single crystal (for example, polycrystalline), the properties may differ from those shown in Figure 37A.

[0372] In Figure 37A, the low carrier concentration range R1 exhibits extremely high hole mobility, making it a suitable carrier concentration range for, for example, the channel formation region of a transistor. For example, in the case of indium oxide, the range R1 has a carrier concentration of 1 × 10⁻⁶. １５ cm −３ This range includes, for example, 1 × 10 １４ cm −３ The above is 1 x 10 １８ cm −３ The range is as follows: By sufficiently reducing the carrier concentration, the hole mobility value can be increased to 270 cm⁻¹. ２ It can be expected to be raised to the level of / (V・s).

[0373] Furthermore, in indium oxide, the region where the carrier concentration is in the range R1 may contain elements that lower the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Other elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0374] On the other hand, the range R2 with high carrier concentration has low electrical resistance and can be said to be a suitable range of carrier concentration for applications such as the source and drain regions of a transistor, or resistors, or transparent conductive films. Range R2 is when the carrier concentration value is 1 × 10⁻⁶ ２０ cm −３ This range includes, for example, 1 × 10 １９ cm −３ The above is 1 x 10 ２２ cm −３ The range is as follows: By making the carrier concentration sufficiently high, the resistivity can be increased to 1 × 10⁻⁶. −４ It is expected that the level can be reduced to below Ω·cm.

[0375] Furthermore, in the indium oxide, the region where the carrier concentration is in the range R2 may contain elements that increase the carrier concentration. For example, it is preferable to include elements common to the source and drain electrodes of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use elements in which the oxide is conductive or semiconducting.

[0376] In this way, indium oxide uses regions with low carrier concentrations for the transistor's channel formation region and regions with high carrier concentrations for the transistor's source and drain regions. In other words, indium oxide can be said to be an oxide in which valence electron control is possible. In IGZO, however, strain can form in the source and drain regions due to stress on the electrodes in contact with the IGZO, sometimes resulting in the formation of an n-type region. On the other hand, unlike IGZO, indium oxide allows for valence electron control, so it does not require the formation of strain in the film as in IGZO. Less strain in the film is expected to improve reliability. For example, by creating regions with carrier concentrations in the range R1 and range R2 shown in Figure 37A within the indium oxide film, a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Valence electron control in silicon transistors is generally known. On the other hand, valence electron control in indium oxide transistors is a novel technological concept that would not normally be conceived.

[0377] By applying the above technical concept, the indium oxide transistor described herein has two or more, preferably three or more, more preferably four or more, and most preferably five of the following features (1) to (5): (1) High on-current (in other words, high mobility). (2) Low off-current. (3) Normally off is possible. (4) High reliability. (5) High cutoff frequency (fT). For example, the indium oxide transistor described herein has high mobility, low off-current, and is normally off. This transistor is different from a transistor that is high mobility and normally on.

[0378] Next, we will describe indium oxide films applied to transistors. Indium oxide films are preferably crystalline (i.e., they have crystal grains). Examples of films with crystal grains include single-crystal films, polycrystalline films, or amorphous films containing crystal grains (also called microcrystalline films). In particular, polycrystalline films are preferred for indium oxide films, and single-crystal films are more preferred. Single-crystal films do not have crystal grain boundaries. Impurities that inhibit carrier flow (typically insulating impurities, insulating oxides, etc.) tend to segregate at crystal grain boundaries. By using single-crystal films, carrier scattering at crystal grain boundaries can be suppressed, enabling the realization of transistors exhibiting high field-effect mobility. Furthermore, it has the excellent effect of suppressing variations in transistor characteristics caused by these crystal grain boundaries.

[0379] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using polycrystalline films, it is preferable to use films with the largest possible grain size and few grain boundaries. In a transistor to which a polycrystalline indium oxide film is applied, if there are no grain boundaries in the channel formation region, or if no grain boundaries are observed, the channel formation region is located within the single-crystal region contained in the polycrystalline film, and therefore it can be considered a transistor to which single-crystal indium oxide is applied.

[0380] The crystallinity of indium oxide can be analyzed, for example, by X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0381] Furthermore, in this specification, a semiconductor layer in which no grain boundaries are observed in the channel-forming region, a semiconductor layer in which the channel-forming region is contained within a single crystal grain, or a semiconductor layer in which the direction of the crystal axes is the same in at least two regions within the channel-forming region can be called a single crystal film. In addition, a semiconductor layer in which, within a single crystal grain in the channel-forming region, the direction of other crystal axes changes continuously with respect to a certain crystal axis or crystal orientation as the axis of rotation can be called a single crystal film.

[0382] The channel formation region refers to the area within the semiconductor layer that overlaps with (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, grain boundaries, crystal axes, and crystal orientation in the channel formation region can be confirmed by cross-sectional observation including the semiconductor layer, source electrode, and drain electrode.

[0383] The indium oxide film in the channel-forming region is preferable to have a low impurity concentration. Impurities in the indium oxide film in the channel-forming region can act as a scattering source for carriers, and thus can cause a decrease in field-effect mobility. Furthermore, these impurities can also inhibit crystal growth in the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The concentration of these impurities in the indium oxide film is preferably 0.1% or less, and more preferably 0.01% (100 ppm) or less. Note that elements such as carbon and hydrogen may be present in the deposition gas or precursor during film formation, and may remain in the indium oxide film in higher concentrations than the impurities mentioned above.

[0384] Furthermore, the indium oxide film in the channel-forming region may contain elements that can become trivalent cations like indium, as long as their crystals maintain a cubic crystal structure (Bixbite type). Examples include Group 13 elements of the periodic table such as gallium and aluminum, and Group 3 elements of the periodic table. Since these elements mainly exist as trivalent cations in the oxide, the carrier concentration of indium oxide can be kept low.

[0385] By using such an indium oxide film in a transistor, the field-effect mobility of the transistor can be increased to 50 cm². ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ It can be set to (V・s) or more.

[0386] One of the characteristics of indium oxide films is that they have higher oxygen permeability (diffusivity) compared to IGZO films. As shown in Figure 37C, indium oxide films (InO Ｘ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and oxygen molecules (O) ２ It is released as water molecules (H) by reacting with hydrogen contained in the membrane. ２ It may also be released as O. Furthermore, oxygen deficiencies (V) can form in the membrane. Ｏ If oxygen atoms are present, diffusing oxygen atoms will fill the oxygen deficiency. Indium oxide films allow oxygen to diffuse easily, so they can be said to fill oxygen deficiencies more easily than IGZO films.

[0387] Thus, because indium oxide films are more likely to reduce oxygen vacancies in the film compared to IGZO films, applying such indium oxide films to transistors makes it possible to realize transistors with extremely high reliability.

[0388] Furthermore, as shown in Figure 37C, the indium oxide film diffuses hydrogen. Hydrogen diffusing into the indium oxide film from the outside permeates the film and forms hydrogen molecules (H ２ It is released as ) or, by reacting with oxygen contained in the membrane, it is released as water molecules.

[0389] Transistors using indium oxide films are storage-type transistors that use electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, in a transistor, the on-current or field-effect mobility of the transistor can be increased.

[0390] Table 1 shows single crystal indium oxide (here, In ２ O ３ The effective masses of indium oxide and single-crystal silicon (Si) are shown below. As shown in Table 1, indium oxide is characterized by a small effective electron mass and a large effective hole mass. Furthermore, the effective electron mass of indium oxide is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in transistors, transistors with high field-effect mobility and high frequency characteristics (also called f-characteristics) can be realized. In addition, because the effective hole mass is large, transistors with extremely low off-currents can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width is 1 fA (1 × 10⁻¹⁶) in an environment of 125°C. −１５ A) Less than or equal to, or 1aA (1 × 10 −１８ A) Less than or equal to 1aA (1 × 10) in a room temperature (25°C) environment. −１８ A) Less than or equal to, or 1zA (1 × 10⁻¹⁰ −２１ A) The following is possible. Also, as shown in Table 1, indium oxide has a smaller effective electron mass and a larger effective hole mass than silicon, so it may be possible to realize a transistor with higher field-effect mobility and lower off-current than a Si transistor.

[0391]

[0392] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. It is preferable to use a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with the indium oxide for the seed layer. This improves the crystallinity of the indium oxide film. A substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0393] One method for evaluating the degree of lattice mismatch is to use the following lattice mismatch value. The lattice mismatch Δa [%] of the crystals in the formed film (in this case, the indium oxide film) relative to the crystals in the seed layer is given by Δa = ((L １ -L ２ ) / L ２ It is calculated as ) × 100. Here L １ L is the length of the unit cell vector of the crystals in the formed film, or the lattice constant. ２ This is the length of the unit cell vector of the crystal in the seed layer, or the lattice constant.

[0394] The lattice mismatch Δa between the seed layer and the indium oxide film is preferably small in absolute value, and most preferably zero. For example, Δa can be -5% or more and 5% or less, preferably -4% or more and 4% or less, more preferably -3% or more and 3% or less, and even more preferably -2% or more and 2% or less.

[0395] Here, the indium oxide crystal has a cubic structure (bixbite type). For example, yttria-stabilized zirconia (YSZ) crystals can have a cubic structure (fluorite type). The lattice mismatch of the indium oxide crystal with respect to the cubic YSZ crystal is in the range of -2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on a YSZ substrate.

[0396] Furthermore, the crystal structure of the seed layer and the crystal structure of the indium oxide film do not necessarily have to be the same in terms of crystal system or crystal orientation. For example, a film with a hexagonal or trigonal crystal structure can be used beneath an indium oxide film with a cubic crystal structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to crystal orientation necessary for epitaxial growth can be met. Examples of hexagonal or trigonal crystals include wurtzite-type structures and YbFe. ２ O ４ Type structure, Yb ２ Fe ３ O ７ These include type structures and their modified type structures. YbFe ２ O ４ Type structure or Yb ２ Fe ３ O ７ An example of a crystal having a type structure is IGZO.

[0397] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments.

[0398] (Embodiment 5) This embodiment describes an application example of the memory cell 100 according to one aspect of the present invention.

[0399] <Example of Hierarchical Structure of Memory Devices> Generally, various memory devices are used in computers and other devices depending on the application. Figure 38 shows various memory devices in order of hierarchy. The higher the level of memory device, the faster the operating speed required, and the lower the level of memory device, the larger the storage capacity and the higher the recording density required. In Figure 38, from the top down, the layers are register, cache memory, main memory, and storage. Furthermore, the cache memory can have primary cache (L1), secondary cache (L2), and tertiary cache (L3), etc., from the top down. Note that although an example with a tertiary cache is shown here, it is possible to have even lower-level cache memory. The lowest-level cache memory is sometimes called LLC (Last Level Cache) or FLC (Final Level Cache). Also, for example, storage class memory can be placed between main memory and storage.

[0400] Registers integrated into arithmetic processing units (also called processors) such as the CPU (Central Processing Unit), GPU (Graphics Processing Unit), NPU (Neural Processing Unit), and TPU (Tensor Processing Unit) are used for temporary storage of the results of calculations performed by the core. They also have the function of holding configuration information for the arithmetic processing unit. Therefore, they are accessed frequently by the arithmetic processing unit. Consequently, fast operating speeds are required for registers.

[0401] Cache memory, for example, uses SRAM (Static Random Access Memory). Cache memory has the function of duplicating and storing a portion of the data held in main memory. By duplicating frequently used data, the speed of data access can be increased. Cache memory requires a faster operating speed than main memory.

[0402] Main memory can be, for example, DRAM (Dynamic Random Access Memory). Main memory has the function of holding programs and data read from storage. Main memory requires a larger storage capacity and higher recording density than cache memory.

[0403] Storage has the function of holding data that needs to be stored long-term, as well as various programs used by the processing unit. Therefore, storage requires a large storage capacity and high recording density. Storage can be, for example, an HDD (Hard Disk Drive) and an SSD (Solid State Drive) which is located above the HDD. As an SSD, a large-capacity, non-volatile storage device such as NAND flash memory (e.g., 3D NAND) can be used.

[0404] A memory device using a memory cell according to one aspect of the present invention has high soft error tolerance and is virtually free from soft errors. Therefore, since there is no need to perform error verification during reading, low power consumption and high-speed reading are possible.

[0405] A memory cell according to one aspect of the present invention is suitable for a storage device in which a cache memory is located, a register is located, and a main memory is located. That is, a memory cell according to one aspect of the present invention is suitable for target 1, which is a region that includes, in addition to the region in which the cache memory is located, the boundary region between the region in which the register is located and the region in which the cache memory is located, and the boundary region between the region in which the register is located and the region in which the main memory is located.

[0406] Therefore, for example, it is preferable to use a memory device using a memory cell according to one aspect of the present invention as at least a part of the cache memory (L1, L2, L3, LLC, FLC, etc.) of a CPU, GPU, and NPU. Also, for example, it is preferable to use a memory device using a memory cell according to one aspect of the present invention as at least a part of a register.

[0407] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments.

[0408] (Embodiment 6) This embodiment describes electronic components, electronic devices, etc., that can use the semiconductor device described in the above embodiment.

[0409] By using a semiconductor device according to one aspect of the present invention in various electronic devices, it is possible to miniaturize and reduce the power consumption of the electronic devices. Furthermore, since the semiconductor device according to one aspect of the present invention does not require error verification during readout, power consumption is low and heat generation from the circuit can be reduced. Therefore, adverse effects on the circuit itself, peripheral circuits, and modules due to such heat generation can be reduced. In addition, by using a semiconductor device according to one aspect of the present invention, it is possible to realize electronic devices that operate stably even in high-temperature environments. Therefore, the reliability of electronic devices can be improved.

[0410] <Electronic Components> Figure 39A shows a perspective view of a substrate (mounted substrate 704) on which electronic components 700 are mounted. The electronic component 700 shown in Figure 39A has a semiconductor device 710 inside a mold 711. Some details are omitted in Figure 39A to show the inside of the electronic component 700. The electronic component 700 has a land 712 on the outside of the mold 711. The land 712 is connected to an electrode pad 713, and the electrode pad 713 is connected to the semiconductor device 710 via a wire 714. The electronic component 700 is mounted on a printed circuit board 702, for example. Multiple such electronic components are combined and connected on the printed circuit board 702 to complete the mounted substrate 704.

[0411] Furthermore, a storage device 300 having a memory cell 100 according to one aspect of the present invention can be used as the semiconductor device 710. Therefore, the semiconductor device 710 can have a monolithic stacked configuration in which a plurality of element layers 20 are stacked. In a monolithic stacked configuration, the layers can be connected without using through-electrode technology such as TSV and bonding technology such as Cu-Cu direct bonding. By configuring a plurality of element layers in a monolithic stacked configuration, it is possible to increase the speed of operation of the interface portion between the plurality of element layers in particular.

[0412] Also, by adopting a monolithic stacked structure, it is possible to reduce the size of connection wirings and the like compared to the technology using through electrodes such as TSVs, and thus it is also possible to increase the number of connection pins.

[0413] Next, a perspective view of the electronic component 730 is shown in FIG. 39B. The electronic component 730 is an example of a SiP (System in Package) or an MCM (Multi Chip Module). The electronic component 730 includes an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 720 and a plurality of semiconductor devices 710 provided on the interposer 731.

[0414] In the electronic component 730, an example is shown in which a semiconductor device 710 using a storage device 300 having a memory cell 100 according to one aspect of the present invention is used as a high bandwidth memory (HBM: High Bandwidth Memory). In the electronic component 730, the semiconductor device 720 can be used for integrated circuits such as a CPU, a GPU, and an FPGA (Field Programmable Gate Array).

[0415] The package substrate 732 can use, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate. The interposer 731 can use, for example, a silicon interposer or a resin interposer.

[0416] The interposer 731 has a plurality of wirings and has a function of connecting a plurality of integrated circuits with different terminal pitches. The plurality of wirings are provided in a single layer or multiple layers. The interposer 731 also has a function of connecting an integrated circuit provided on the interposer 731 to an electrode provided on the package substrate 732. For these reasons, the interposer may be referred to as a "rewiring substrate" or an "intermediate substrate". In some cases, through electrodes are provided on the interposer 731 and used to connect the integrated circuit and the package substrate 732. In a silicon interposer, TSVs can also be used as the through electrodes.

[0417] In HBM, many wirings need to be connected to achieve a wide memory bandwidth. Therefore, for an interposer on which HBM is implemented, fine and high-density wiring formation is required. Thus, it is preferable to use a silicon interposer for the interposer on which HBM is implemented.

[0418] Also, in SiP, MCM, etc. using a silicon interposer, a decrease in reliability due to a difference in the coefficient of thermal expansion between the integrated circuit and the interposer is unlikely to occur. Also, since the silicon interposer has a high surface flatness, a connection failure between the integrated circuit provided on the silicon interposer and the silicon interposer is unlikely to occur. In particular, in a 2.5D package (2.5-dimensional implementation) in which a plurality of integrated circuits are arranged side by side on the interposer, it is preferable to use a silicon interposer.

[0419] Also, it is preferable to provide a heat sink (heat radiation plate) overlapping with the electronic component 730. By providing the heat sink, the operation of the electronic component can be stabilized and the reliability can be enhanced. When providing the heat sink, it is preferable to align the heights of the integrated circuits provided on the interposer 731. For example, in the electronic component 730 shown in the present embodiment, it is preferable to align the heights of the semiconductor device 710 and the semiconductor device 720.

[0420] In order to mount the electronic component 730 on another substrate, an electrode 733 can be provided at the bottom of the package substrate 732. FIG. 39B shows an example in which the electrode 733 is formed of solder balls. By providing solder balls in a matrix shape at the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be realized. Also, the electrode 733 can be formed of conductive pins. By providing conductive pins in a matrix shape at the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be realized.

[0421] The electronic component 730 can be mounted on other boards using various mounting methods, not limited to BGA and PGA. Examples of mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).

[0422] <Electronic Devices> One aspect of the present invention relates to a semiconductor device that can be used as a storage device for various electronic devices (e.g., information terminals, computers, smartphones, e-book readers, digital still cameras, video cameras, recording and playback devices, navigation systems, game consoles, etc.). It can also be used for image sensors, IoT (Internet of Things), healthcare-related equipment, etc. Here, "computer" includes tablet computers, notebook computers, desktop computers, and large computers such as server systems.

[0423] An example of an electronic device having a semiconductor device according to one aspect of the present invention will be described. Figures 40A to 40J and 41A to 41E illustrate how the electronic component 700 or electronic component 730 having the semiconductor device is included in each electronic device.

[0424] [Mobile Phone] The information terminal 5500 shown in Figure 40A is a mobile phone (smartphone), which is a type of information terminal. The information terminal 5500 has a housing 5510 and a display unit 5511. As an input interface, a touch panel is provided on the display unit 5511 and buttons are provided on the housing 5510.

[0425] The information terminal 5500 can store temporary files generated during application execution (for example, cache when using a web browser) by applying a semiconductor device according to one aspect of the present invention.

[0426] [Wearable Devices] Figure 40B also shows an information terminal 5900, which is an example of a wearable device. The information terminal 5900 includes a housing 5901, a display unit 5902, operation switches 5903 and 5904, a band 5905, and the like.

[0427] Similar to the information terminal 5500 described above, the wearable device can store temporary files generated during application execution by applying a semiconductor device according to one aspect of the present invention.

[0428] [Information Terminal] Figure 40C also shows a desktop information terminal 5300. The desktop information terminal 5300 has an information terminal body 5301, a display unit 5302, and a keyboard 5303.

[0429] The desktop information terminal 5300, like the information terminal 5500 described above, can store temporary files generated during application execution by applying a semiconductor device according to one aspect of the present invention.

[0430] In the above, smartphones, wearable devices, and desktop information terminals were used as examples of electronic devices and illustrated in Figures 40A to 40C, respectively. However, information terminals other than smartphones, wearable devices, and desktop information terminals can also be applied. Examples of information terminals other than smartphones, wearable devices, and desktop information terminals include PDAs (Personal Digital Assistants), notebook computers, and workstations.

[0431] [Electrical Appliances] Figure 40D also shows an electric refrigerator-freezer 5800 as an example of an electrical appliance. The electric refrigerator-freezer 5800 has a casing 5801, a refrigerator door 5802, a freezer door 5803, etc. For example, the electric refrigerator-freezer 5800 is an IoT-compatible electric refrigerator-freezer.

[0432] A semiconductor device according to one aspect of the present invention can be applied to an electric refrigerator 5800. The electric refrigerator 5800 can send and receive information such as the food stored in the electric refrigerator 5800 and the expiration date of that food to an information terminal or the like via the internet. The electric refrigerator 5800 can store temporary files generated when transmitting such information in the semiconductor device.

[0433] In this example, an electric refrigerator was described as an electrical appliance, but other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cooktops, water dispensers, heating and cooling appliances including air conditioners, washing machines, dryers, and audio-visual equipment.

[0434] [Game Console] Figure 40E also shows a portable game console 5200, which is an example of a game console. The portable game console 5200 has a housing 5201, a display unit 5202, buttons 5203, etc.

[0435] Furthermore, Figure 40F illustrates a home console 7500, which is an example of a game console. The home console 7500 has a main unit 7520 and a controller 7522. The controller 7522 can be connected to the main unit 7520 wirelessly or via a wired connection. Although not shown in Figure 40F, the controller 7522 may also be equipped with a display unit for displaying game images, and input interfaces other than buttons, such as a touch panel, a joystick, a rotary knob, or a sliding knob. Moreover, the controller 7522 is not limited to the shape shown in Figure 40F, and its shape can be changed in various ways depending on the genre of game. For example, in shooting games such as FPS (First Person Shooter), a controller with triggers as buttons and shaped like a gun can be used. Also, for example, in music games, a controller shaped like a musical instrument or musical equipment can be used. Furthermore, home game consoles can be designed to operate without controllers, instead incorporating cameras, depth sensors, microphones, and other features, allowing players to control the game using gestures or voice commands.

[0436] Furthermore, the video from the aforementioned game console can be output by display devices such as televisions, personal computer displays, game displays, and head-mounted displays.

[0437] By applying a semiconductor device according to one aspect of the present invention to a portable game console 5200 or a home game console 7500, a portable game console 5200 or a home game console 7500 with high soft error tolerance can be realized. Furthermore, by applying a semiconductor device according to one aspect of the present invention, the generation of Hamming codes necessary for data recovery from soft errors becomes unnecessary. Therefore, a highly reliable storage device can be realized without reducing the usable storage capacity. In addition, since error verification is not required during reading, low power consumption and high-speed reading can be achieved, and the operating speed of the portable game console 5200 and the home game console 7500 can be increased. Furthermore, because low power consumption reduces heat generation from the circuit, the impact of heat on the circuit itself, peripheral circuits, and modules can be reduced.

[0438] It should be noted that the electronic devices in one aspect of the present invention are not limited to portable game consoles and home console game consoles. Examples of electronic devices in one aspect of the present invention include arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.) and pitching machines for batting practice installed in sports facilities.

[0439] [Mobile Devices] The semiconductor device described in the above embodiment can be applied to a mobile device, such as an automobile, and the area around the driver's seat of an automobile.

[0440] Figure 40G shows an example of a mobile device, an automobile 5700.

[0441] The driver's seat area of ​​the 5700 automobile is equipped with an instrument panel that provides various information by displaying the speedometer, tachometer, mileage, fuel gauge, gear status, and air conditioning settings. Furthermore, a display device for showing this information can be installed around the driver's seat.

[0442] In particular, by displaying images from an imaging device (not shown) installed in the automobile 5700, the display device can compensate for obstructed views from pillars and other obstructions, as well as blind spots in the driver's seat, thereby enhancing safety. In other words, by displaying images from an imaging device installed on the outside of the automobile 5700, blind spots can be compensated for, and safety can be enhanced.

[0443] The semiconductor device described in the above embodiment can temporarily hold information, and therefore can be used, for example, to hold necessary temporary information in systems that perform autonomous driving, road guidance, and hazard prediction for the automobile 5700. The display device can be configured to display temporary information such as road guidance and hazard prediction. It can also be configured to hold video footage from a driving recorder installed in the automobile 5700.

[0444] While the above explanation uses automobiles as an example of a moving object, the definition of a moving object is not limited to automobiles. For example, other examples of moving objects include trains, monorails, ships, and flying objects (helicopters, unmanned aerial vehicles (drones), airplanes, rockets).

[0445] [Camera] The semiconductor device described in the above embodiment can be applied to a camera.

[0446] Figure 40H shows a digital camera 6240, which is an example of an imaging device. The digital camera 6240 has a housing 6241, a display unit 6242, an operation switch 6243, a shutter button 6244, etc., and a detachable lens 6246 is attached to the digital camera 6240. In this example, the digital camera 6240 is configured so that the lens 6246 can be removed from the housing 6241 and replaced, but in some cases the lens 6246 and housing 6241 are integrated. Furthermore, the digital camera 6240 can also be configured to have a strobe device, viewfinder, etc. attached separately.

[0447] By applying the semiconductor device described in the above embodiment to the digital camera 6240, a digital camera 6240 with low power consumption can be realized. Further, since the power consumption is low, heat generation from the circuit can be reduced, so that the influence on the circuit itself, the peripheral circuit, and the module due to heat generation can be minimized.

[0448] [Video Camera] The semiconductor device described in the above embodiment can be applied to a video camera.

[0449] FIG. 40I shows a video camera 6300 which is an example of an imaging device. The video camera 6300 includes a first housing 6301, a second housing 6302, a display unit 6303, an operation switch 6304, a lens 6305, a connection part 6306, and the like. The operation switch 6304 and the lens 6305 are provided on the first housing 6301, and the display unit 6303 is provided on the second housing 6302. The first housing 6301 and the second housing 6302 are connected by the connection part 6306, and the angle between the first housing 6301 and the second housing 6302 can be changed by the connection part 6306. It is also possible to configure the video on the display unit 6303 to be switched according to the angle between the first housing 6301 and the second housing 6302 at the connection part 6306.

[0450] When recording the video taken by the video camera 6300, it is necessary to perform encoding according to the data recording format. By using the semiconductor device described above, the video camera 6300 can hold temporary files generated during encoding.

[0451] [ICD] The semiconductor device described in the above embodiment can be applied to an implantable cardioverter defibrillator (ICD).

[0452] FIG. 40J is a schematic cross-sectional view showing an example of an ICD. The ICD main body 5400 has at least a battery 5401, electronic components 700, a regulator, a control circuit, an antenna 5404, a wire 5402 to the right atrium, and a wire 5403 to the right ventricle.

[0453] The ICD unit 5400 is surgically implanted in the body, and two wires are routed through the subclavian vein 5405 and superior vena cava 5406 of the human body so that the tip of one wire is placed in the right ventricle and the tip of the other wire is placed in the right atrium.

[0454] The ICD unit 5400 functions as a pacemaker, pacing the heart when the heart rate falls outside a specified range. If pacing does not improve the heart rate (e.g., rapid ventricular tachycardia, ventricular fibrillation), treatment with an electric shock is administered.

[0455] The ICD unit 5400 needs to constantly monitor the heart rate in order to properly perform pacing and electric shocks. Therefore, the ICD unit 5400 has a sensor for detecting the heart rate. In addition, the ICD unit 5400 can store heart rate data acquired by the sensor, the number of times pacing treatment was performed, the duration, etc., in the electronic component 700.

[0456] Furthermore, power can be received by the antenna 5404, and this power is used to charge the battery 5401. In addition, the ICD unit 5400 can be made safer by having multiple batteries. Specifically, even if some of the batteries in the ICD unit 5400 become unusable, the remaining batteries can still function, thus also functioning as an auxiliary power source.

[0457] Furthermore, in addition to the antenna 5404 that can receive power, it is also possible to have an antenna that can transmit physiological signals. For example, a system can be configured to monitor cardiac activity so that physiological signals such as pulse rate, respiratory rate, heart rate, and body temperature can be checked on an external monitoring device.

[0458] [Expansion device for PC] The semiconductor device described in the above embodiment can be applied to an expansion device for computers and information terminals such as PCs (Personal Computers).

[0459] Figure 41A shows an example of such an expansion device, a portable expansion device 6100 that attaches to a PC externally and is equipped with a chip capable of storing information. The expansion device 6100 can store information using the chip by connecting to a PC, for example, via USB (Universal Serial Bus). Although Figure 41A illustrates a portable form of the expansion device 6100, the expansion device according to one aspect of the present invention is not limited to this, and it is also possible to make a relatively large expansion device equipped with, for example, a cooling fan.

[0460] The expansion device 6100 comprises a housing 6101, a cap 6102, a USB connector 6103, and a circuit board 6104. The circuit board 6104 is housed in the housing 6101. The circuit board 6104 is provided with circuits for driving semiconductor devices and the like as described in the above embodiment. For example, electronic components 700 and a controller chip 6106 are mounted on the circuit board 6104. The USB connector 6103 functions as an interface for connecting to an external device.

[0461] [SD Card] The semiconductor device described in the above embodiment can be applied to an SD card that can be attached to electronic devices such as information terminals and digital cameras.

[0462] Figure 41B is a schematic diagram of the external appearance of an SD card, and Figure 41C is a schematic diagram of the internal structure of an SD card. The SD card 5110 has a housing 5111, a connector 5112, and a circuit board 5113. The connector 5112 functions as an interface for connecting to an external device. The circuit board 5113 is housed in the housing 5111. The circuit board 5113 is provided with a semiconductor device and a circuit for driving the semiconductor device. For example, an electronic component 700 and a controller chip 5115 are mounted on the circuit board 5113. Note that the circuit configurations of the electronic component 700 and the controller chip 5115 are not limited to those described above, and the circuit configurations can be changed as appropriate depending on the situation. For example, the writing circuit, load driver, and read circuit provided in the electronic component can be incorporated into the controller chip 5115 instead of the electronic component 700.

[0463] By providing electronic components 700 on the back side of the circuit board 5113, the capacity of the SD card 5110 can be increased. Furthermore, a wireless chip with wireless communication capabilities can be provided on the circuit board 5113. This allows for wireless communication between an external device and the SD card 5110, enabling the reading and writing of data to and from the electronic components 700.

[0464] [SSD] The semiconductor device described in the above embodiment can be applied to an SSD that can be attached to an electronic device such as an information terminal.

[0465] Figure 41D is a schematic diagram of the external appearance of the SSD, and Figure 41E is a schematic diagram of the internal structure of the SSD. The SSD 5150 has a housing 5151, a connector 5152, and a circuit board 5153. The connector 5152 functions as an interface for connecting to an external device. The circuit board 5153 is housed in the housing 5151. The circuit board 5153 is provided with a storage device and a circuit for driving the storage device. For example, electronic components 700, a memory chip 5155, and a controller chip 5156 are mounted on the circuit board 5153. The capacity of the SSD 5150 can be increased by also providing electronic components 700 on the back side of the circuit board 5153. Work memory is incorporated into the memory chip 5155. For example, a DRAM chip can be used for the memory chip 5155. The controller chip 5156 incorporates a processor, an ECC circuit, and the like. Furthermore, the circuit configurations of the electronic component 700, the memory chip 5155, and the controller chip 5156 are not limited to those described above, and can be changed as appropriate depending on the situation. For example, the controller chip 5156 can also be provided with memory that functions as work memory.

[0466] [Computer] The computer 5600 shown in Figure 42A is an example of a large computer (supercomputer) mainly used for scientific and technical calculations. Scientific and technical calculations require high-speed processing of enormous calculations, resulting in high power consumption and significant heat generation from the chips. For example, in data centers with multiple supercomputers, the amount of digital data used becomes extremely large. Specifically, the amount of digital data in the world is 10 ２４ (yotta) bytes, or 10 ３０ It is expected to exceed (quetta) bytes.

[0467] By applying a semiconductor device according to one aspect of the present invention to the computer 5600, a highly reliable computer 5600 with high soft error tolerance can be realized. Furthermore, by applying the semiconductor device according to one aspect of the present invention, the generation of Hamming codes necessary for data recovery from soft errors becomes unnecessary. In addition, since error verification is not required during reading, low power consumption and high-speed reading can be achieved, and the operating speed of the computer 5600 can be increased. Moreover, because low power consumption reduces heat generation from the circuit, the impact of heat on the circuit itself, peripheral circuits, and modules can be reduced. As a result, it is expected that the amount of digital data in the world will be reduced, and a significant contribution to measures against global warming can be made.

[0468] The computer 5600 contains multiple rack-mount type computers 5620 housed in a rack 5610. The computer 5620 can be configured, for example, as shown in the perspective view in Figure 42B. In Figure 42B, the computer 5620 has a motherboard 5630, which has multiple slots 5631 and multiple connection terminals. A PC card 5621 is inserted into a slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to the motherboard 5630.

[0469] The PC card 5621 shown in Figure 42C is an example of a processing board equipped with a CPU, GPU, storage device, etc. The PC card 5621 has a board 5622. The board 5622 also has connection terminals 5623, 5624, 5625, semiconductor device 5626, semiconductor device 5627, semiconductor device 5628, and connection terminal 5629. Although Figure 42C shows semiconductor devices other than semiconductor devices 5626, 5627, and 5628, you can refer to the descriptions of semiconductor devices 5626, 5627, and 5628 below for information on these semiconductor devices.

[0470] The connector 5629 has a shape that allows it to be inserted into slot 5631 of the motherboard 5630, and functions as an interface for connecting the PC card 5621 and the motherboard 5630. Examples of standards for the connector 5629 include PCIe.

[0471] Terminals 5623, 5624, and 5625 can serve as interfaces for, for example, power supply and signal input to the PC card 5621. They can also serve as interfaces for, for example, outputting signals calculated by the PC card 5621. Examples of standards for terminals 5623, 5624, and 5625 include USB, SATA (Serial ATA), and SCSI (Small Computer System Interface). When outputting video signals from terminals 5623, 5624, and 5625, examples of standards include HDMI (registered trademark).

[0472] The semiconductor device 5626 has terminals (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be electrically connected by inserting these terminals into sockets (not shown) provided on the board 5622.

[0473] The semiconductor device 5627 has multiple terminals, and the semiconductor device 5627 and the board 5622 can be electrically connected by, for example, reflow soldering, to the terminals on the wiring provided on the board 5622. Examples of semiconductor devices 5627 include FPGAs, GPUs, and CPUs. For example, an electronic component 730 can be used as the semiconductor device 5627.

[0474] The semiconductor device 5628 has multiple terminals, and the semiconductor device 5628 and the board 5622 can be electrically connected by, for example, reflow soldering, to the terminals on the wiring provided on the board 5622. Examples of the semiconductor device 5628 include a memory device. For example, an electronic component 700 can be used as the semiconductor device 5628.

[0475] Computer 5600 can also function as a parallel computer. By using Computer 5600 as a parallel computer, it is possible to perform large-scale calculations necessary for, for example, artificial intelligence training and inference.

[0476] [Space Equipment] A semiconductor device according to one aspect of the present invention can be used in space equipment such as devices for processing and storing information.

[0477] A semiconductor device according to one aspect of the present invention includes an OS transistor and exhibits minimal fluctuations in electrical characteristics due to radiation exposure. In other words, it has high resistance to radiation and is therefore suitable for environments where radiation may be incident. For example, a semiconductor device according to one aspect of the present invention is suitable for use in outer space.

[0478] Figure 43 shows an example of space equipment, specifically a satellite 6800. The satellite 6800 comprises a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. In Figure 43, a planet 6804 is shown as an example in outer space. Outer space refers to, for example, an altitude of 100 km or more, but as described herein, outer space includes the thermosphere, mesosphere, and stratosphere.

[0479] Furthermore, although not shown in Figure 43, it is possible to provide a battery management system (also called "BMS") or a battery control circuit with the secondary battery 6805. Using an OS transistor in the aforementioned battery management system or battery control circuit is preferable because it consumes little power and has high reliability even in outer space.

[0480] Furthermore, outer space is an environment with radiation levels more than 100 times higher than those on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, as well as particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0481] When sunlight shines on the solar panel 6802, the power necessary for the satellite 6800 to operate is generated. However, if, for example, the solar panel is not exposed to sunlight, or if the amount of sunlight shining on the solar panel is low, the amount of power generated will decrease. Therefore, there is a possibility that the power necessary for the satellite 6800 to operate may not be generated. To operate the satellite 6800 even under conditions of low power generation, it is advisable to equip the satellite 6800 with a secondary battery 6805. Note that solar panels are sometimes called solar cell modules.

[0482] The satellite 6800 can generate a signal. This signal is transmitted via antenna 6803, and can be received by, for example, a receiver on the ground or another satellite. By receiving the signal transmitted by satellite 6800, the position of the receiver that received the signal can be measured. Thus, satellite 6800 can constitute a satellite positioning system.

[0483] Furthermore, the control device 6807 has the function of controlling the artificial satellite 6800. The control device 6807 has one or more functions selected from, for example, a CPU, a GPU, and a memory device. Compared to Si transistors, OS transistors exhibit less variation in electrical characteristics due to radiation irradiation. A semiconductor device according to one aspect of the present invention is highly reliable even in environments where radiation may be incident, and is suitable as a memory element or memory device of the control device 6807. A semiconductor device according to one aspect of the present invention can be used, for example, in the control device 6807.

[0484] Furthermore, the satellite 6800 can be configured to include sensors. For example, by configuring it to include a visible light sensor, the satellite 6800 can have the function of detecting sunlight reflected off objects on the ground. Alternatively, by configuring it to include a thermal infrared sensor, the satellite 6800 can have the function of detecting thermal infrared radiation emitted from the Earth's surface. Thus, the satellite 6800 can function, for example, as an Earth observation satellite.

[0485] In this embodiment, an artificial satellite was used as an example of space equipment, but the invention is not limited to this. For example, a semiconductor device according to one aspect of the present invention is suitable for space equipment such as spacecraft, space capsules, and space probes.

[0486] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments.

[0487] 10: Element layer, 10[1]: Element layer, 10[k]: Element layer, 20: Element layer, 20[1]: Element layer, 20[k]: Element layer, 21: Drive circuit, 22: PSW, 23: PSW, 31: Peripheral circuit, 32: Control circuit, 33: Voltage generation circuit, 41: Peripheral circuit, 42: Row decoder, 43: Row driver, 44: Column decoder, 45: Column driver, 47: Input circuit, 48: Output circuit, 50: Layer, 100: Memory cell, 100[1,1]: Memory cell, 100[1,n]: Memory cell, 100[i,1]: Memory cell, 100[i,j]: Memory cell, 100[i,n] :memory cell, 100[m,1]:memory cell, 100[m,n]:memory cell, 100A:memory cell, 100B:memory cell, 100C:memory cell, 100D:memory cell, 100E:memory cell, 100F:memory cell, 100G:memory cell, 101:wiring, 101[1]:wiring, 102:wiring, 102[1]:wiring, 103:wiring, 103[1]:wiring, 104:wiring, 104[1]:wiring, 105:wiring, 105[1]:wiring, 106:wiring, 107:wiring, 110:first memory circuit, 110[1,1]:first memory circuit, 110[m,n]:first 1: Memory circuit, 120: Second memory circuit, 120[1,1]: Second memory circuit, 120[m,n]: Second memory circuit, 120a: Second memory circuit, 120b: Second memory circuit, 120c: Second memory circuit, 120d: Second memory circuit, 200: Memory cell array, 201: Insulating element layer, 205: Conductive layer, 205a: Conductive layer, 205b: Conductive layer, 214: Insulating layer, 216: Insulating layer, 220: Metal oxide, 220a: Metal oxide, 220b: Metal oxide, 222: Insulating layer, 224: Insulating layer, 241: Insulating layer, 241a: Insulating layer, 241b: Insulating layer, 242: Conductive layer, 242a: Conductive layer, 242b: Conductive layer, 245: Conductive layer, 245a: Conductive layer, 245b: Conductive layer, 250: Insulating layer, 254: Insulating layer, 255: Conductive layer, 256: Insulating layer, 257: Insulating layer, 258: Insulating layer, 259: Insulating layer, 260: Conductive layer, 260a: Conductive layer, 260b: Conductive layer, 261: Conductive layer, 262: Opening, 265: Conductive layer, 274: Insulating layer, 280: Insulating layer, 281: Insulating layer, 285: Insulating layer, 300: Memory device, 311: Insulating layer, 312: Insulating layer, 313: Conductive layer, 313[1]: Conductive layer, 313[2]: Conductive layer, 313[3]: Conductive layer, 314: Insulating layer,315: conductive layer, 315[1]: conductive layer, 315[2]: conductive layer, 315[3]: conductive layer, 316: insulating layer, 317: insulating layer, 317[1]: insulating layer, 317[2]: insulating layer, 317[3]: insulating layer, 317[4]: insulating layer, 318: semiconductor layer, 318[1]: semiconductor layer, 318[2]: semiconductor layer, 318[3]: semiconductor layer, 318[4]: semiconductor layer, 319: conductive layer, 319[1]: conductive layer, 319[2]: conductive layer, 319[3]: conductive layer, 319[4]: conductive layer, 320: insulating layer, 321: insulating layer, 322: conductive layer, 322[1]: conductive layer, 32 2[2]: conductive layer, 322[3]: conductive layer, 322[4]: conductive layer, 323: insulating layer, 324: insulating layer, 325: conductive layer, 325[1]: conductive layer, 325[2]: conductive layer, 325[3]: conductive layer, 325[4]: conductive layer, 326: conductive layer, 326[1]: conductive layer, 326[2]: conductive layer, 326[3]: conductive layer, 326[4]: conductive layer, 327: conductive layer, 327[1]: conductive layer, 327[2]: conductive layer, 327[3]: conductive layer, 328: conductive layer, 328[1]: conductive layer, 328[2]: conductive layer, 328[3]: conductive layer, 329: insulating layer, 330: conductive layer 331: Conductive layer, 332: Conductive layer, 333: Conductive layer, 334: Conductive layer, 335: Conductive layer, 336: Conductive layer, 337: Conductive layer, 338: Conductive layer, 339: Conductive layer, 340: Conductive layer, 341: Conductive layer, 342: Conductive layer, 371: Substrate, 373: Semiconductor region, 374a: Low resistance region, 374b: Low resistance region, 375: Insulating layer, 376: Conductive layer, 382: Insulating layer, 384: Insulating layer, 386: Conductive layer, 390: Insulating layer, 391: Insulating layer, 392: Conductive layer, 393: Insulating layer, 394: Insulating layer, 395: Conductive layer, 396: Insulating layer, 700: Electronic component, 702: Printer 704: Mounting board, 710: Semiconductor equipment, 711: Mold, 712: Land, 713: Electrode pad, 714: Wire, 720: Semiconductor equipment, 730: Electronic component, 731: Interposer, 732: Package board, 733: Electrode, 751: Transistor, 752: Transistor, 753: Transistor, 999: Radiation, 5110: SD card, 5111: Enclosure, 5112: Connector, 5113: Board, 5115: Controller chip, 5150: SSD, 5151: Enclosure, 5152: Connector, 5153: Board, 5155: Memory chip5156: Controller chip, 5200: Portable game console, 5201: Casing, 5202: Display unit, 5203: Button, 5300: Desktop information terminal, 5301: Main unit, 5302: Display unit, 5303: Keyboard, 5400: ICD main unit, 5401: Battery, 5402: Wire, 5403: Wire, 5404: Antenna, 5405: Subclavian vein, 5406: Superior vena cava, 5500: Information terminal, 5510: Casing, 5511: Display unit, 5600: Computer, 5610: Rack, 5620: Computer, 5621: PC card, 5622: Board, 5623: Connection 5624: Connection terminal, 5625: Connection terminal, 5626: Semiconductor device, 5627: Semiconductor device, 5628: Semiconductor device, 5629: Connection terminal, 5630: Motherboard, 5631: Slot, 5700: Automobile, 5800: Electric refrigerator / freezer, 5801: Enclosure, 5802: Door for refrigerator compartment, 5803: Door for freezer compartment, 5900: Information terminal, 5901: Enclosure, 5902: Display unit, 5903: Operation switch, 5904: Operation switch, 5905: Band, 6100: Expansion device, 6101: Enclosure, 6102: Cap, 6103: USB connector, 6104: Circuit board, 6106: Controller chip, 6240: Digital camera, 6241: Housing, 6242: Display unit, 6243: Operation switch, 6244: Shutter button, 6246: Lens, 6300: Video camera, 6301: First housing, 6302: Second housing, 6303: Display unit, 6304: Operation switch, 6305: Lens, 6306: Connection unit, 6800: Artificial satellite, 6801: Aircraft body, 6802: Solar panel, 6803: Antenna, 6804: Planet, 6805: Rechargeable battery, 6807: Control device, 7500: Home game console, 7520: Main unit, 752 2: Controller, ADDR: Signal, BL: Signal, BL[1]: Signal, BLB: Signal, BLB[1]: Signal, BW: Signal, CE: Signal, CL: Signal, CLK: Signal, Cs: Capacitive element, Csa: Capacitive element, Csb: Capacitive element, GW: Signal, INV: Inverter circuit, PL: Signal, PL[1]: Signal, PLH: Signal, PLL: Signal, QB: Node, RDA: Signal, SET: Signal, SET[1]: Signal, SN: Node, SNB: Node, T11: Period, T12: Period, T13: Period, T14: Period, T15: Period, T16: Period, T31: Period, T32: Period,T33: period, T34: period, T35: period, T36: period, Tr11: transistor, Tr12: transistor, Tr21: transistor, Tr22: transistor, Tr23: transistor, Tr24: transistor, Tr25: transistor, Tr26: transistor, TrP: transistor, TrQ: transistor, Vb: voltage, VDD: high power supply potential, VSS: low power supply potential, WAKE: signal, WDA: signal, WL: signal, WL[1]: signal,

Claims

It has a first memory circuit and a second memory circuit, The first memory circuit comprises a first inverter circuit, a second inverter circuit, a first transistor, and a second transistor. The output of the first inverter circuit is electrically connected to the input of the second inverter circuit and the first terminal of the first transistor. The output of the second inverter circuit is electrically connected to the input of the first inverter circuit and the first terminal of the second transistor. The second memory circuit comprises third to sixth transistors and capacitive elements. The first terminal of the third transistor is electrically connected to the output of the first inverter circuit, the input of the second inverter circuit, and the first terminal of the fourth transistor. The first terminal of the fifth transistor is electrically connected to the output of the second inverter circuit, the input of the first inverter circuit, and the first terminal of the sixth transistor. The second terminal of the third transistor is electrically connected to the first terminal of the capacitive element and the gate of the sixth transistor. The second terminal of the fifth transistor is electrically connected to the second terminal of the capacitive element and the gate of the fourth transistor. Each of the third and fifth transistors is a semiconductor device containing indium and oxygen in its channel-forming region. 　 In claim 1, Each of the first inverter circuit and the second inverter circuit is a semiconductor device having a transistor containing silicon in its channel formation region. 　 In claim 1 or claim 2, Each of the fourth and sixth transistors is a semiconductor device containing indium and oxygen in its channel-forming region. 　 In claim 1 or claim 2, Each of the fourth and sixth transistors is a semiconductor device containing silicon in its channel formation region. 　 In claim 4, A semiconductor device in which the fourth transistor and the sixth transistor are each p-type transistors. 　 In claim 1 or claim 2, The first memory circuit and the second memory circuit are semiconductor devices having overlapping regions. 　 It has a first memory circuit and a second memory circuit, The first memory circuit comprises a first inverter circuit, a second inverter circuit, a first transistor, and a second transistor. The output of the first inverter circuit is electrically connected to the input of the second inverter circuit and the first terminal of the first transistor. The output of the second inverter circuit is electrically connected to the input of the first inverter circuit and the first terminal of the second transistor. The second memory circuit has third to sixth transistors, The first terminal of the third transistor is electrically connected to the output of the first inverter circuit, the input of the second inverter circuit, and the first terminal of the fourth transistor. The first terminal of the fifth transistor is electrically connected to the output of the second inverter circuit, the input of the first inverter circuit, and the first terminal of the sixth transistor. The second terminal of the third transistor is electrically connected to the gate of the sixth transistor. The second terminal of the fifth transistor is electrically connected to the gate of the fourth transistor. Each of the third and fifth transistors is a semiconductor device that includes an oxide semiconductor in its channel formation region. 　 In claim 7, The aforementioned oxide semiconductor is a semiconductor device containing indium. 　 In claim 7 or claim 8, Each of the first inverter circuit and the second inverter circuit is a semiconductor device having a transistor containing silicon in its channel formation region. 　 In claim 7 or claim 8, Each of the fourth and sixth transistors is a semiconductor device containing silicon in its channel formation region. 　 In claim 7 or claim 8, Each of the fourth and sixth transistors is a semiconductor device containing an oxide semiconductor in its channel formation region. In claim 11, The aforementioned oxide semiconductor is a semiconductor device containing indium. 　 In claim 7 or claim 8, Having a capacitive element, The first terminal of the capacitive element is electrically connected to the second terminal of the third transistor and the gate of the sixth transistor. The second terminal of the capacitive element is electrically connected to the second terminal of the fifth transistor and the gate of the fourth transistor in a semiconductor device. 　 In claim 7 or claim 8, The first memory circuit and the second memory circuit are semiconductor devices having overlapping regions.

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