Semiconductor device

Abstract

Provided is a highly reliable semiconductor device. In this semiconductor device, a first conductive layer and a second conductive layer are located on a first insulating layer, a semiconductor layer is located between the first conductive layer and the second conductive layer, a first lateral surface of the first conductive layer and a second lateral surface of the second conductive layer face each other, the semiconductor layer is in contact with the first lateral surface and the second lateral surface, a second insulating layer is in contact with an upper surface of the first conductive layer, a third insulating layer is in contact with an upper surface of the second conductive layer, a fourth insulating layer is in contact with an upper surface of the semiconductor layer, a third conductive layer overlaps the upper surface of the semiconductor layer with the fourth insulating layer interposed therebetween, the semiconductor layer has a metal oxide, the first insulating layer has a function of gettering hydrogen, and each of the second insulating layer and the third insulating layer has a function of supplying oxygen and / or a function of blocking oxygen.

Description

Semiconductor equipment

[0001] One aspect of the present invention relates to a semiconductor device, a memory device, a display device, and an electronic device.

[0002] It should be noted that one aspect of the present invention is not limited to the above-mentioned technical field. Examples of technical fields of one aspect of the present invention disclosed herein include semiconductor devices, display devices, light-emitting devices, energy storage devices, memory devices, electronic devices, lighting devices, input devices, input / output devices, methods for driving them, or methods for manufacturing them. A semiconductor device refers to any device that can function by utilizing semiconductor properties.

[0003] In recent years, the development of semiconductor devices has progressed, and these devices are mainly used in LSIs (Large Scale Integration), CPUs (Central Processing Units), and memory. A CPU is an assembly of semiconductor elements that have semiconductor integrated circuits (at least transistors and capacitors) formed on chips by processing semiconductor wafers, and electrodes that serve as connection terminals are formed on them.

[0004] Semiconductor circuits (IC chips) such as LSIs, CPUs, and memory are mounted on circuit boards, such as printed circuit boards, and used as components in various electronic devices.

[0005] Furthermore, the technology of constructing transistors using semiconductor thin films formed on substrates with insulating surfaces is attracting attention. These transistors are widely applied in electronic devices such as integrated circuits and image display devices (also simply referred to as display devices). While silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors are attracting attention as other materials.

[0006] Transistors using oxide semiconductors are known to have extremely low leakage current in the non-conductive state. For example, Patent Document 1 discloses a low-power CPU that utilizes the characteristic of low leakage current of transistors using oxide semiconductors. Patent Document 2 also discloses a memory device that uses oxide semiconductors and can retain stored data for a long period of time.

[0007] Furthermore, Non-Patent Document 1 reports on a polycrystalline indium oxide film exhibiting high hole mobility and a transistor using it. Also, Non-Patent Document 2 reports on In ２ O ３ Its use in thin-film transistors has been reported.

[0008] Japanese Patent Publication No. 2012-257187 Japanese Patent Publication No. 2011-151383

[0009] Y. Magari et al. , “High-mobility hydrogenated polycrystalline In▲2▼O▲3▼(In▲2▼O▲3▼:H) thin-film transistors”, Nature Communications 13, 1078, (2022). Dhananjay and C. W. Chu, “Realization of In▲2▼O▲3▼ thin film transistors through reactive evaporation process” Appl. Phys. Lett. 91, 132111 (2007). Takashi Koida, "High-Mobility Transparent Conductive Film," National Institute of Advanced Industrial Science and Technology (AIST), AIST Photovoltaic Power Generation Research Results Presentation 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf>

[0010] One aspect of the present invention aims to provide a transistor with good electrical characteristics. One aspect of the present invention aims to provide a transistor with a large on-current. One aspect of the present invention aims to provide a transistor with low parasitic capacitance. One aspect of the present invention aims to provide a highly reliable transistor, semiconductor device, or memory device. One aspect of the present invention aims to provide a transistor, semiconductor device, or memory device that can be miniaturized or highly integrated. One aspect of the present invention aims to provide a semiconductor device or memory device with low power consumption. One aspect of the present invention aims to provide a memory device with a fast operating speed.

[0011] One aspect of the present invention aims to provide a semiconductor device having a novel configuration. Another aspect of the present invention aims to mitigate at least one of the problems of the prior art.

[0012] Furthermore, the description of these problems does not preclude the existence of other problems. Moreover, one aspect of the present invention does not need to solve all of these problems. Other problems can be identified from the description in the specification, drawings, claims, etc.

[0013] One aspect of the present invention comprises a first insulating layer, a second insulating layer, and a transistor, wherein the transistor comprises a semiconductor layer, a third insulating layer, a first conductive layer, a second conductive layer, and a third conductive layer, the first conductive layer, the second conductive layer and the second insulating layer being located on the first insulating layer, the second insulating layer being located between the first conductive layer and the second conductive layer, and the semiconductor layer having a first region in contact with the upper surface of the first conductive layer and a second region in contact with the upper surface of the second conductive layer A semiconductor device having two regions and a third region located between the first and second regions and on the second insulating layer, wherein the third insulating layer is in contact with the upper surface of the third region, the third conductive layer overlaps the third region with the third insulating layer in between, the semiconductor layer has a metal oxide, the first insulating layer has a hydrogen gettering function, and the second insulating layer has at least one of an oxygen supply function and an oxygen blocking function.

[0014] In the above embodiment, the second insulating layer comprises a first layer and a second layer on the first layer, the first layer comprises a region located between the first conductive layer and the second layer, a region located between the second conductive layer and the second layer, and a region located between the first insulating layer and the second layer, and it is preferable that the first layer and the second layer each have at least one of the functions of supplying oxygen and blocking oxygen.

[0015] In the above embodiment, the first insulating layer preferably contains hafnium and oxygen. Furthermore, the first insulating layer preferably contains hafnium oxide.

[0016] In the above embodiment, it is preferable that the first layer and the second layer each contain at least one of silicon and aluminum, and oxygen. It is also preferable that one of the first layer and the second layer contains silicon oxide and the other contains aluminum oxide.

[0017] In the above embodiment, it is preferable that the first conductive layer and the second conductive layer each contain indium, tin, and oxygen. It is also preferable that the first conductive layer and the second conductive layer each contain indium tin oxide.

[0018] In the above embodiment, it is preferable that the first conductive layer and the second conductive layer have nickel.

[0019] In the above embodiment, it is preferable to have a fourth insulating layer, the first insulating layer being located on the fourth insulating layer, and the fourth insulating layer comprising silicon and nitrogen. It is also preferable that the fourth insulating layer comprises silicon nitride.

[0020] In the above embodiment, the semiconductor layer preferably has indium oxide.

[0021] Alternatively, one aspect of the present invention comprises a first insulating layer, a second insulating layer, a third insulating layer, and a transistor, wherein the transistor comprises a semiconductor layer, a fourth insulating layer, a first conductive layer, a second conductive layer, and a third conductive layer, the first conductive layer and the second conductive layer are located on the first insulating layer, the semiconductor layer is located between the first conductive layer and the second conductive layer, the first side surface of the first conductive layer and the second side surface of the second conductive layer are facing each other, and the semiconductor layer has a first side surface and a second side surface The semiconductor device is configured such that the second insulating layer is in contact with the upper surface of the first conductive layer, the third insulating layer is in contact with the upper surface of the second conductive layer, the fourth insulating layer is in contact with the upper surface of the semiconductor layer, the third conductive layer overlaps with the upper surface of the semiconductor layer with the fourth insulating layer in between, the semiconductor layer has a metal oxide, the first insulating layer has a hydrogen gettering function, and the second and third insulating layers each have at least one of the functions of supplying oxygen and blocking oxygen.

[0022] In the above embodiment, the semiconductor layer has a first region in contact with the first side surface, a second region in contact with the second side surface, and a third region located between the first and second regions and covering the upper surface of the first insulating layer; the fourth insulating layer has a fourth region facing the first side surface with the first region in between, a fifth region facing the second side surface with the second region in between, and a sixth region facing the upper surface of the first insulating layer with the third region in between; the first and fourth regions are preferably sandwiched between the first conductive layer and the third conductive layer, and the second and fifth regions are preferably sandwiched between the second conductive layer and the third conductive layer.

[0023] In the above embodiment, the first insulating layer preferably contains hafnium and oxygen. Furthermore, the first insulating layer preferably contains hafnium oxide.

[0024] In the above embodiment, it is preferable that the second insulating layer and the third insulating layer have at least one of silicon and oxygen, and oxygen. It is also preferable that the second insulating layer and the third insulating layer have at least one of silicon oxide and aluminum oxide.

[0025] In the above embodiment, it is preferable that the first conductive layer and the second conductive layer contain indium, tin, and oxygen. It is also preferable that the first conductive layer and the second conductive layer contain indium tin oxide.

[0026] In the above embodiment, it is preferable that the first conductive layer and the second conductive layer have nickel.

[0027] In the above embodiment, it is preferable to have a fifth insulating layer, the first insulating layer being located on the fifth insulating layer, and the fifth insulating layer comprising silicon and nitrogen. Furthermore, it is preferable that the fifth insulating layer comprises silicon nitride.

[0028] In the above embodiment, it is preferable that there is a fifth insulating layer and a sixth insulating layer, the sixth insulating layer being located on the fifth insulating layer, the first insulating layer being located on the sixth insulating layer, the fifth insulating layer comprising silicon and nitrogen, the sixth insulating layer comprising silicon and oxygen, and the second and third insulating layers comprising aluminum and oxygen. Furthermore, it is preferable that the fifth insulating layer comprises silicon nitride. Furthermore, it is preferable that the sixth insulating layer comprises silicon oxide. Furthermore, it is preferable that the second and third insulating layers comprise aluminum oxide.

[0029] In the above embodiment, the semiconductor layer preferably contains indium and oxygen. Furthermore, the semiconductor layer preferably contains indium oxide.

[0030] According to one aspect of the present invention, a transistor with good electrical characteristics can be provided. According to one aspect of the present invention, a transistor with a large on-current can be provided. According to one aspect of the present invention, a transistor with low parasitic capacitance can be provided. According to one aspect of the present invention, a highly reliable transistor, semiconductor device, or memory device can be provided. According to one aspect of the present invention, a transistor, semiconductor device, or memory device that can be miniaturized or highly integrated can be provided. According to one aspect of the present invention, a semiconductor device or memory device with low power consumption can be provided. According to one aspect of the present invention, a memory device with a fast operating speed can be provided.

[0031] According to one aspect of the present invention, a semiconductor device having a novel configuration can be provided. According to one aspect of the present invention, at least one of the problems of the prior art can be mitigated.

[0032] Furthermore, the description of these effects does not preclude the existence of other effects. Moreover, one aspect of the present invention does not necessarily have to possess all of these effects. Other effects can be extracted from the description in the specification, drawings, claims, etc.

[0033] Figures 1A, 1B, and 1C are cross-sectional views showing examples of semiconductor device configurations. Figures 2A, 2B, and 2C are perspective views showing examples of semiconductor device configurations. Figure 3A is a top view showing an example of semiconductor device configuration. Figures 3B, 3C, 3D, and 3E are cross-sectional views showing examples of semiconductor device configurations. Figure 4A is a top view showing an example of semiconductor device configuration. Figures 4B, 4C, and 4D are cross-sectional views showing examples of semiconductor device configurations. Figures 5A, 5B, and 5C are perspective views showing examples of semiconductor device configurations. Figure 6A is a top view showing an example of semiconductor device configuration. Figures 6B, 6C, 6D, 6E, and 6F are cross-sectional views showing examples of semiconductor device configurations. Figure 7A is a top view showing an example of semiconductor device configuration. Figures 7B, 7C, and 7D are cross-sectional views showing examples of semiconductor device configurations. Figure 8A is a top view showing an example of semiconductor device configuration. Figures 8B, 8C, and 8D are cross-sectional views showing examples of semiconductor device configurations. Figure 9A is a top view showing an example of semiconductor device configuration. Figures 9B, 9C, and 9D are cross-sectional views showing an example of the configuration of a semiconductor device. Figure 9E is a perspective view showing an example of the configuration of a semiconductor device. Figure 10A is a top view showing an example of the configuration of a semiconductor device. Figure 10B is a cross-sectional view showing an example of the configuration of a semiconductor device. Figures 10C and 10D are perspective views showing an example of the configuration of a semiconductor device. Figure 11A is a top view showing an example of the configuration of a semiconductor device. Figure 11B is a cross-sectional view showing an example of the configuration of a semiconductor device. Figure 11C is a perspective view showing an example of the configuration of a semiconductor device. Figure 12A is a top view showing an example of the configuration of a semiconductor device. Figures 12B, 12C, and 12D are cross-sectional views showing an example of the configuration of a semiconductor device. Figure 13A is a top view showing an example of the configuration of a semiconductor device. Figures 13B, 13C, and 13D are cross-sectional views showing an example of the configuration of a semiconductor device. Figure 14A is a top view showing an example of the configuration of a semiconductor device. Figures 14B, 14C, and 14D are cross-sectional views showing an example of the configuration of a semiconductor device. Figure 15A is a top view showing an example of the configuration of a semiconductor device. Figures 15B, 15C, and 15D are cross-sectional views showing examples of semiconductor device configurations. Figure 16A is a top view showing an example of semiconductor device configuration. Figures 16B, 16C, 16D, and 16E are cross-sectional views showing examples of semiconductor device configurations. Figure 17A is a top view showing an example of semiconductor device configuration.Figures 17B, 17C, 17D, and 17E are cross-sectional views showing examples of semiconductor device configurations. Figure 18A is a top view showing an example of semiconductor device configuration. Figures 18B, 18C, and 18D are cross-sectional views showing examples of semiconductor device configurations. Figure 19A is a top view showing an example of semiconductor device configuration. Figures 19B, 19C, and 19D are cross-sectional views showing examples of semiconductor device configurations. Figure 20A is a top view showing an example of semiconductor device configuration. Figures 20B, 20C, and 20D are cross-sectional views showing examples of semiconductor device configurations. Figure 21A is a top view showing an example of semiconductor device configuration. Figures 21B, 21C, and 21D are cross-sectional views showing examples of semiconductor device configurations. Figure 22A is a top view showing an example of semiconductor device configuration. Figures 22B, 22C, and 22D are cross-sectional views showing examples of semiconductor device configurations. Figure 23A is a top view showing an example of semiconductor device configuration. Figures 23B, 23C, and 23D are cross-sectional views showing examples of semiconductor device configurations. Figures 24A and 24B are cross-sectional views showing examples of semiconductor device configurations. Figures 25A1, 25B1, 25C1, and 25D1 are cross-sectional views showing examples of semiconductor device manufacturing methods. Figures 25A2, 25B2, 25C2, and 25D2 are perspective views showing examples of semiconductor device manufacturing methods. Figures 26A1, 26B1, 26C1, and 26C3 are cross-sectional views showing examples of semiconductor device manufacturing methods. Figures 26A2, 26B2, and 26C2 are perspective views showing examples of semiconductor device manufacturing methods. Figures 27A1, 27B1, and 27C1 are cross-sectional views showing examples of semiconductor device manufacturing methods. Figures 27A2, 27B2, and 27C2 are perspective views showing examples of semiconductor device manufacturing methods. Figures 28A1, 28B1, 28C1, and 28C3 are cross-sectional views showing examples of semiconductor device manufacturing methods. Figures 28A2, 28B2, and 28C2 are perspective views showing examples of semiconductor device manufacturing methods. Figures 29A1, 29B1, and 29C1 are cross-sectional views showing examples of semiconductor device manufacturing methods. Figures 29A2, 29B2, and 29C2 are perspective views showing examples of semiconductor device manufacturing methods. Figures 30A1 and 30B1 are cross-sectional views showing examples of semiconductor device manufacturing methods. Figures 30A2 and 30B2 are perspective views showing examples of semiconductor device manufacturing methods. Figures 31A1, 31B1, 31C1, and 31C3 are cross-sectional views showing examples of semiconductor device manufacturing methods.Figures 31A2, 31B2, and 31C2 are perspective views showing examples of semiconductor device manufacturing methods. Figures 32A1 and 32A3 are cross-sectional views showing examples of semiconductor device manufacturing methods. Figure 32A2 is a perspective view showing an example of a semiconductor device manufacturing method. Figures 33A and 33B illustrate the carrier concentration dependence of Hall mobility. Figure 33C is a cross-sectional view illustrating an indium oxide film. Figure 34 is an example of a memory device configuration. Figures 35A and 35B are examples of memory device configurations. Figures 36A, 36B, 36C, and 36D are examples of memory device configurations. Figure 37 is an example of a memory device configuration. Figures 38A and 38B are examples of display device configurations. Figure 39 is an example of a display device configuration. Figures 40A, 40B, 40C, and 40D are examples of electronic device configurations. Figures 41A, 41B, 41C, 41D, 41E, and 41F show examples of the configuration of electronic equipment. Figures 42A, 42B, 42C, 42D, 42E, 42F, and 42G show examples of the configuration of electronic equipment. Figures 43A and 43B show examples of the configuration of electronic components. Figures 44A, 44B, and 44C show examples of the configuration of a large computer. Figures 45A and 45B are perspective views of a semiconductor device. Figure 46 is a perspective view of a semiconductor device.

[0034] The embodiments will be described below with reference to the drawings. However, it will be readily apparent to those skilled in the art that the embodiments can be implemented in many different ways, and their form and details can be modified in various ways without departing from the spirit and scope thereof. Accordingly, the present invention shall not be construed as being limited to the contents of the following embodiments.

[0035] In the invention described below, the same reference numerals are used in common across different drawings for identical parts or parts having similar functions, and repeated explanations are omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used, and reference numerals may not be assigned.

[0036] In the figures described herein, the size of each component, the thickness of the layers, or the area may be exaggerated for clarity. Therefore, the scale is not necessarily limited to those figures.

[0037] Furthermore, ordinal numbers such as "the first," "the second," etc., used in this specification are added to avoid confusion of constituent elements and do not imply any numerical limitation.

[0038] A transistor is a type of semiconductor device that can perform functions such as amplifying current or voltage, and switching operations that control conduction or non-conductivity. Transistors as used herein include IGFETs (Insulated Gate Field Effect Transistors) and thin-film transistors (TFTs).

[0039] Furthermore, the functions of "source" and "drain" may be reversed when transistors with different polarities are used, or when the direction of current changes during circuit operation. For this reason, in this specification, the terms "source" and "drain" may be used interchangeably.

[0040] Furthermore, in this specification, "electrically connected" includes cases where a connection is made via "something that has some kind of electrical function." Here, "something that has some kind of electrical function" is not particularly limited as long as it enables the exchange of electrical signals between the connected objects. For example, "something that has some kind of electrical function" includes electrodes or wiring, switching elements such as transistors, resistive elements, coils, and other elements with various functions.

[0041] In this specification, cases where two nodes are connected via an insulator, such as the dielectric of a capacitive element, the gate insulating film of a transistor, or an interlayer insulating film, are not included in the definition of "electrical connection."

[0042] In this specification, "heights match" refers to a configuration in which the heights from a reference surface (for example, a flat surface such as the substrate surface) are equal in a cross-sectional view. For example, if there are two layers with different heights (here referred to as layer A and layer B) with respect to the reference surface, the heights also match if the difference between the height of the top surface of layer A and the height of the top surface of layer B is 10 nm or less.

[0043] In this specification, "side edges coincide" means that, in a plan view, at least a portion of the contours of the stacked layers overlap. For example, in the case of two stacked layers (here referred to as layer A and layer B), if the shortest distance from the side edge of layer A to the side edge of layer B in a plan view is 10 nm or less, then the side edges also coincide.

[0044] In general, it can be difficult to clearly distinguish between "exact match" and "approximate match." Therefore, in this specification, "match" may include both exact matches and approximate matches.

[0045] In this specification, the top surface shape of a component refers to the contour shape of that component in a plan view. A plan view refers to a view from the direction normal to the surface on which the component is formed, or to the surface of the support (e.g., substrate) on which the component is formed.

[0046] In the following, expressions indicating direction, such as "up" and "down," will generally be used in accordance with the orientation shown in the drawings. However, for the purpose of simplifying explanations, the direction referred to as "up" or "down" in the specification may not always coincide with that of the drawings. For example, when explaining the stacking order (or formation order) of a laminate, even if the side on which the laminate is provided (the surface to be formed, the support surface, the adhesive surface, the flat surface, etc.) is located above the laminate in the drawing, the surface to be formed may be described as "down" and the laminate side as "up."

[0047] Furthermore, in this specification, the terms "film" and "layer" are interchangeable. For example, the term "insulating layer" may be interchangeable with the term "insulating film."

[0048] Furthermore, unless otherwise specified in this specification, off-current refers to the drain current when the transistor is in the off state (also called the non-conducting state or cutoff state). Unless otherwise specified, the off state refers to the state in an n-channel transistor where the voltage Vgs between the gate and source is lower than the threshold voltage Vth (in a p-channel transistor, it is higher than Vth).

[0049] In this specification and the like, space groups are expressed using the Short notation of the international notation (or Hermann-Mauguin symbol). Also, crystal planes and crystal orientations are expressed using Miller indices. In crystallography, the notations of space groups, crystal planes, and crystal orientations are represented by numbers with a bar above them. However, in this specification and the like, due to formatting constraints, instead of putting a bar above the numbers, a - (minus sign) may be attached before the numbers for expression. Also, individual orientations indicating directions within a crystal are represented by [ ], set orientations indicating all equivalent orientations are represented by < >, individual planes indicating crystal planes are represented by ( ), and set planes having equivalent symmetries are represented by {}, respectively.

[0050] In this specification and the like, the content ratio of a certain metal element in a metal oxide refers to the ratio of the number of atoms of that element to the total number of atoms of the metal elements contained in the metal oxide. For example, if a metal oxide contains metal element X, metal element Y, and metal element Z, and the number of atoms of metal element X, metal element Y, and metal element Z contained in the metal oxide are A Ｘ , A Ｙ , A Ｚ respectively, the content ratio of metal element X can be expressed as A Ｘ / (A Ｘ + A Ｙ + A Ｚ ). Also, when the ratio of the number of atoms (atomic ratio) of metal element X, metal element Y, and metal element Z in the metal oxide is B Ｘ : B Ｙ : B Ｚ respectively, the content ratio of metal element X can be expressed as B Ｘ / (B Ｘ + B Ｙ + B Ｚ ).

[0051] (Embodiment 1) In this embodiment, a semiconductor device of one aspect of the present invention and a method for manufacturing the same will be described. The semiconductor device of one aspect of the present invention includes a transistor.

[0052] A semiconductor device according to one aspect of the present invention includes a transistor, a first insulating layer, and a second insulating layer. The transistor includes a semiconductor layer, a first electrode, and a second electrode. One of the first electrode and the second electrode can function as a source electrode, and the other can function as a drain electrode.

[0053] In the fabrication of a semiconductor device according to one aspect of the present invention, it is preferable to form the first electrode and the second electrode before forming the semiconductor layer.

[0054] When the first and second electrodes are formed after the semiconductor layer has been formed, the etching process during the formation of the first and second electrodes may damage the semiconductor layer. By forming the first and second electrodes before forming the semiconductor layer (i.e., forming the semiconductor layer after the first and second electrodes have been formed), it may be possible to reduce damage to the semiconductor layer during the transistor manufacturing process.

[0055] The semiconductor layer can be formed so as to be in contact with the upper surface of the first electrode and the second electrode after they have been formed. Alternatively, the semiconductor layer can be formed so as to be in contact with the side surface of the first electrode and the second electrode after they have been formed.

[0056] The first insulating layer preferably has a hydrogen gettering function. As an insulating layer having a hydrogen gettering function, for example, an insulating layer having at least one of a hydrogen capture function and a hydrogen fixation function can be used. In an insulating layer having a hydrogen gettering function, the hydrogen concentration of the insulating layer increases after gettering is performed. Also, in a layer from which hydrogen has been removed by gettering, the hydrogen concentration of that layer decreases. The hydrogen concentration can be quantified using, for example, secondary ion mass spectrometry (SIMS). In the semiconductor device manufacturing process, gettering can be performed by providing an insulating layer having a gettering function near or in contact with a layer from which hydrogen is to be removed, and then performing a heat treatment or the like.

[0057] In a semiconductor device, the hydrogen concentration in the semiconductor layer can be reduced by configuring the first insulating layer to be located near the semiconductor layer or in contact with the semiconductor layer. In particular, when a metal oxide is used as the semiconductor layer, it is preferable to reduce the hydrogen in the channel formation region of the semiconductor layer as much as possible. Specifically, the hydrogen concentration in the channel formation region of a semiconductor obtained by SIMS is 1 × 10⁻⁶. ２０ atoms / cm ３ Less than 5 × 10 １９ atoms / cm ３ Less than, more preferably 1 × 10 １９ atoms / cm ３ Less than, more preferably 5 × 10 １８ atoms / cm ３ Less than 1 × 10 １８ atoms / cm ３ Less than 1 × 10 １７ atoms / cm ３ Less than.

[0058] The second insulating layer preferably has a region containing oxygen that is released by heating (hereinafter sometimes referred to as excess oxygen). In a semiconductor device, by configuring the second insulating layer to be in contact with the semiconductor layer or to be located near it, oxygen can be supplied to the semiconductor layer. When a metal oxide is used as the semiconductor layer, supplying oxygen can eliminate oxygen vacancies in the semiconductor layer (hereinafter referred to as V). Ｏ This can reduce (sometimes called) oxygen desorption. A material that desorbs oxygen by heating is, for example, a material in which the amount of oxygen desorption, converted to oxygen atoms, is 1.0 × 10¹⁶ in TDS (Thermal Desorption Spectroscopy) analysis. １８ atoms / cm ３ Preferably 1.0 × 10 １９ atoms / cm ３ More preferably 2.0 × 10 １９ atoms / cm ３ The above or 3.0 x 10 ２０ atoms / cm ３The material is as described above. Furthermore, the surface temperature of the film during the TDS analysis is preferably in the range of 100°C to 700°C or 100°C to 400°C.

[0059] Furthermore, the second insulating layer can also have barrier properties against oxygen. This can suppress the diffusion of oxygen contained in the semiconductor layer to other regions.

[0060] In this specification, barrier properties refer to the property of making it difficult for the corresponding substance to diffuse (also referred to as the property of making it difficult for the corresponding substance to permeate, the property of having low permeability to the corresponding substance, or the function of suppressing the diffusion of the corresponding substance). When hydrogen is described as the corresponding substance, it refers to, for example, hydrogen atoms, hydrogen molecules, and water molecules and OH − This refers to at least one substance that is bonded with hydrogen, such as [substance name]. Furthermore, when an impurity is listed as a corresponding substance, unless otherwise specified, it refers to an impurity in the channel-forming region or semiconductor layer, such as a hydrogen atom, hydrogen molecule, water molecule, nitrogen atom, nitrogen molecule, nitrogen oxide molecule (N ２ O, NO, NO ２ It refers to at least one substance, such as a copper atom. Furthermore, when oxygen is listed as a corresponding substance, it refers to at least one substance, such as an oxygen atom or an oxygen molecule.

[0061] An example of the arrangement of a first electrode, a second electrode, a semiconductor layer, a first insulating layer, and a second insulating layer in a semiconductor device according to one aspect of the present invention is shown below.

[0062] The configuration shown in Figure 1A includes an insulating layer 22, conductive layers 14a and 14b on the insulating layer 22, an insulating layer 15 on the insulating layer 22, and a semiconductor layer 11 in contact with the upper surface of the conductive layer 14a, the upper surface of the conductive layer 14b, and the upper surface of the insulating layer 15. The insulating layer 15 is located between the conductive layer 14a and the conductive layer 14b.

[0063] In Figure 1A, the first electrode, the second electrode, the semiconductor layer, the first insulating layer, and the second insulating layer described above can correspond to the conductive layer 14a, the conductive layer 14b, the semiconductor layer 11, the insulating layer 22, and the insulating layer 15, respectively.

[0064] Since the conductive layer 14a and conductive layer 14b are in contact with the lower surface of the semiconductor layer, the configuration shown in Figure 1A is sometimes called a bottom contact structure.

[0065] The insulating layer 15 can also have a laminated structure. As shown in Figure 1B, the insulating layer 15 can also have a laminated structure of insulating layer 15_1 and insulating layer 15_2 on insulating layer 15_1. Insulating layer 15_1 has a portion located between insulating layer 15_2 and conductive layer 14a, and a portion located between insulating layer 15_2 and conductive layer 14b. Insulating layer 15_1 also has a portion located between insulating layer 22 and insulating layer 15_2. For example, one or both of insulating layer 15_1 and insulating layer 15_2 can be an insulating layer having a region containing oxygen that is desorbed by heating. This can reduce oxygen vacancies in the semiconductor layer, for example. In addition, one or both of insulating layer 15_1 and insulating layer 15_2 can have barrier properties against oxygen. This can suppress the diffusion of oxygen contained in the semiconductor layer to other regions.

[0066] The configuration shown in Figure 1C includes an insulating layer 22, conductive layers 14a and 14b on the insulating layer 22, a semiconductor layer 11 on the insulating layer 22, an insulating layer 16a on the conductive layer 14a, and an insulating layer 16b on the conductive layer 14b. The semiconductor layer 11 is located between the conductive layers 14a and 14b and is in contact with their respective sides.

[0067] In Figure 1C, the first electrode, the second electrode, the semiconductor layer, and the first insulating layer described above can correspond to the conductive layer 14a, the conductive layer 14b, the semiconductor layer 11, and the insulating layer 22, respectively. The second insulating layer can also correspond to the insulating layer 16a and the insulating layer 16b.

[0068] Furthermore, the insulating layers 16a and 16b can have the function of mitigating parasitic capacitance between the conductive layer formed on top of them and the conductive layers 14a and 14b.

[0069] Furthermore, an insulating layer 29 can be provided on the insulating layer 22 in Figure 1C. In this case, the second insulating layer described above can correspond to the insulating layer 29. The conductive layer 14a, the conductive layer 14b, and the semiconductor layer 11 are each provided on the insulating layer 29. As the insulating layer 29, for example, an insulating layer having a region containing oxygen that is desorbed by heating can be used. This can reduce, for example, oxygen deficiency in the semiconductor layer.

[0070] [Example of Semiconductor Device Configuration 1] Figures 2A to 3D show a semiconductor device including the configuration shown in Figure 1B. Figure 2A is a perspective view of the semiconductor device, and Figure 3A is a top view of the semiconductor device shown in Figure 2A. The semiconductor devices shown in Figures 2A and 3A have a transistor 10. Figures 3B, 3C, and 3D are cross-sectional views corresponding to the cutting lines A1-A2, B1-B2, and B3-B4 in Figure 3A, respectively. Figure 3B corresponds to the cross-section in the channel length direction of the transistor 10, and Figures 3C and 3D correspond to the cross-section in the channel width direction, respectively. Note that in Figure 2A, the insulating layers 31 and 32 are shown as dotted lines and are made transparent to make other elements easier to see.

[0071] Figure 2B omits the insulating layers 31 and 32 from Figure 2A, and shows the conductive layer 13 as a dotted line, allowing it to be seen through and making other elements easier to view. Figure 2C exposes the cross-section by cutting a portion of Figure 2A.

[0072] The semiconductor device includes a substrate (not shown), an insulating layer 21 provided on the substrate, an insulating layer 22 provided on the insulating layer 21, a transistor 10 on the insulating layer 22, and an insulating layer 15 on the insulating layer 22. The transistor 10 includes a conductive layer 14a and a conductive layer 14b, a semiconductor layer 11 on the conductive layer 14a, the conductive layer 14b, and the insulating layer 15, an insulating layer 12 on the semiconductor layer 11, and a conductive layer 13 on the insulating layer 12. An insulating layer 31 is provided on the insulating layer 22 and the semiconductor layer 11, and an insulating layer 32 is provided on the insulating layer 31, the insulating layer 12, and the conductive layer 13. The insulating layer 12 and the conductive layer 13 are located within the openings of the insulating layer 31.

[0073] The semiconductor layer 11 functions as a semiconductor layer of the transistor 10. The conductive layers 14a and 14b function as one and the other source and drain electrodes of the transistor 10. The insulating layer 12 functions as a gate insulating layer of the transistor 10. The conductive layer 13 functions as a gate electrode of the transistor 10.

[0074] By using a metal oxide that functions as an oxide semiconductor as the semiconductor layer 11, the off-current of the transistor can be made extremely small. Furthermore, it is possible to achieve both a small off-current and high frequency characteristics in the transistor.

[0075] It is preferable that the semiconductor layer 11 is in contact with the upper surface of the conductive layer 14a and the upper surface of the conductive layer 14b. In this case, the transistor 10 shown in Figures 2A to 3D has conductive layers that function as source electrodes and drain electrodes, respectively, in contact with the lower surface of the semiconductor layer. The transistor 10 shown in Figures 2A to 3D can be called a transistor having a bottom contact structure.

[0076] In the semiconductor layer 11, the region overlapping with the conductive layer 14a (preferably the region in contact with the conductive layer 14a) and the region overlapping with the conductive layer 14b (preferably the region in contact with the conductive layer 14b) are preferably low-resistance regions. These two low-resistance regions can function as one or the other of the source region and drain region, respectively.

[0077] When a metal oxide is used as the semiconductor layer 11, a defect (hereinafter referred to as V) is a defect in which hydrogen is present in the oxygen vacancy. Ｏ The presence of a metal oxide (sometimes called H) can cause the metal oxide to function as a low-resistance region. Therefore, the source region and drain region of the semiconductor layer 11 are V Ｏ The concentration of H may be high. On the other hand, in the channel-forming region, V Ｏ and V Ｏ A low concentration of H is preferable. V in the channel formation region. Ｏ and V Ｏ By reducing the concentration of H, the electrical characteristics of the transistor can be stabilized, and its reliability can be improved.

[0078] By reducing the resistance of the source and drain regions of the semiconductor layer 11, the contact resistance with the conductive layers 14a and 14b can be reduced, thereby increasing the on-current of the transistor. Increasing the on-current of the transistor improves the frequency characteristics, enabling the realization of a semiconductor device with a high operating speed.

[0079] In transistor 10, in a plan view, the region between conductive layer 14a and conductive layer 14b overlaps with conductive layer 13. In semiconductor layer 11, at least a portion of the region overlapping with conductive layer 13 functions as a channel-forming region. Semiconductor layer 11 has a first region in contact with the upper surface of conductive layer 14a, a second region in contact with the upper surface of conductive layer 14b, and a third region located between the first and second regions. In Figure 3B, etc., the third region is in contact with the upper surface of insulating layer 15. The first region can function as either a source region or a drain region, the second region can function as the other source region or drain region, and the third region can function as a channel-forming region.

[0080] The insulating layer 12 is provided along the side surface of the opening in the insulating layer 31 and along the upper surface of the region in the semiconductor layer 11 that overlaps with the opening. Preferably, the insulating layer 12 is in contact with the upper surface of the region in the semiconductor layer 11 that overlaps with the opening in the insulating layer 31.

[0081] The conductive layer 13 is provided within the opening of the insulating layer 31 so as to fill the recess of the insulating layer 12. The upper surface of the conductive layer 13 is flattened and is roughly aligned with the upper surface of the insulating layer 31.

[0082] The insulating layer 15 is provided to fill the space between the conductive layer 14a and the conductive layer 14b. Preferably, the upper surfaces of the conductive layer 14a, the conductive layer 14b, and the insulating layer 15 are flattened. This allows the semiconductor layer 11 to be provided on the flattened conductive layer 14a, the conductive layer 14b, and the insulating layer 15. Since the flatness of the surface of the semiconductor layer 11 can be increased, for example, electric field concentration between the gate and source, or between the gate and drain can be mitigated.

[0083] The insulating layer 15 is located between the conductive layer 14a and the conductive layer 14b. In the configuration shown in Figures 2A to 3D, the insulating layer 15 is provided so as to be in contact with the side surface of the conductive layer 14a, the side surface of the conductive layer 14b, and the upper surface of the insulating layer 22.

[0084] In the configuration shown in Figure 3B, the insulating layer 15 has an insulating layer 15_1 and an insulating layer 15_2 on top of the insulating layer 15_1. The insulating layer 15_1 is provided along the side surface of the conductive layer 14a, the side surface of the conductive layer 14b, and the upper surface of the insulating layer 22, and the insulating layer 15_2 is provided to fill the recess of the insulating layer 15_1. The upper surface of the insulating layer 15_2 is flattened and is roughly the same height as the upper surfaces of the conductive layers 14a and 14b.

[0085] By using an insulating layer capable of hydrogen gettering as the insulating layer 22, excess hydrogen contained in the semiconductor layer 11 can be removed. In this case, the hydrogen contained in the semiconductor layer 11 may, for example, diffuse through the insulating layer 15 to reach the insulating layer 22. Alternatively, it may diffuse through the conductive layers 14a and 14b to reach the insulating layer 22.

[0086] Examples of insulators capable of hydrogen gettering include oxides having one or more selected from hafnium, magnesium, and aluminum. More specifically, examples include hafnium oxide, magnesium oxide, oxides containing one or both of hafnium and aluminum, etc.

[0087] By using an insulating layer 15 that has the function of supplying oxygen, oxygen is supplied to the semiconductor layer 11, and the V of the semiconductor layer 11 Ｏ This can reduce the V of the channel formation region. In particular, since the insulating layer 15 overlaps with the channel formation region of the semiconductor layer 11, Ｏ This can efficiently reduce the V of the channel formation region. In particular, since the insulating layer 15 overlaps with the channel formation region of the semiconductor layer 11, Ｏ It can efficiently reduce [the problem].

[0088] Examples of insulators that have the function of supplying oxygen include oxides having one or more silicon and aluminum, or oxynitrides having silicon. More specifically, examples include silicon oxide, silicon oxynitride, and aluminum oxide.

[0089] Furthermore, by using an insulating layer 15 that has barrier properties against oxygen, the diffusion of oxygen to the layer below the insulating layer 15 can be suppressed, thereby suppressing the formation of oxygen vacancies due to the desorption of oxygen from the semiconductor layer 11. In particular, by reducing oxygen vacancies in the channel formation region, the electrical characteristics of the transistor can be stabilized and reliability can be improved.

[0090] Examples of insulators having barrier properties against oxygen include oxides containing one or more aluminum and gallium. More specifically, examples include aluminum oxide and gallium oxide.

[0091] The insulating layer 15_1 can have either the function of supplying oxygen or the function of providing a barrier to oxygen, or both.

[0092] The insulating layer 15_2 can have either the function of supplying oxygen or the function of providing a barrier to oxygen, or both.

[0093] By using an insulating layer having barrier properties against oxygen as the insulating layer 15_1, oxidation of the conductive layer 14a and conductive layer 14b can be suppressed, thereby preventing a decrease in the conductivity of the conductive layer 14a and conductive layer 14b, as well as volume changes due to oxidation.

[0094] For example, aluminum oxide can be used for one of the insulating layers 15_1 and 15_2, and silicon oxide or silicon oxynitride can be used for the other.

[0095] More specifically, it is preferable to use silicon oxide or silicon oxynitride, which is an insulator that has the function of supplying oxygen, as the insulating layer 15_2 located closer to the semiconductor layer 11, and aluminum oxide, which is an insulator that has barrier properties against oxygen, as the insulating layer 15_1 covering the sides and bottom of the insulating layer 15_2, because this allows for efficient supply of oxygen to the semiconductor layer 11.

[0096] By using an insulating layer 21 that has barrier properties against hydrogen, the diffusion of hydrogen from the layer below the insulating layer 22 to the semiconductor layer 11 can be suppressed.

[0097] Examples of insulators having barrier properties against hydrogen include silicon nitrides, oxides containing one or more aluminum and tantalum, and so on. More specifically, examples include silicon nitride, aluminum oxide, and tantalum oxide, with silicon nitride being more preferred.

[0098] It is preferable to use an insulating layer 32 that has high barrier properties against oxygen, hydrogen, etc. This makes it possible to suppress the diffusion of impurities from the layer above the insulating layer 32 to the transistor 10.

[0099] The insulating layer 12 functions as the gate insulating layer of the transistor. It is preferable to use a high dielectric constant (high-k) material as the insulating layer 12. By increasing the relative dielectric constant of the insulating layer 12, it becomes possible to reduce the gate voltage applied during transistor operation while maintaining the physical thickness of the gate insulating layer. Furthermore, it becomes possible to thin the equivalent oxide thickness (EOT) of the insulator that functions as the gate insulating layer.

[0100] The insulating layer 31 functions as an interlayer insulating layer. By using a material with a low dielectric constant as the insulating layer 31, the parasitic capacitance that occurs between the wiring provided on the insulating layer 31 and the conductive layer of the transistor can be reduced.

[0101] By using an insulating layer 31 that has the function of supplying oxygen, oxygen can be supplied from the insulating layer 31 to the semiconductor layer 11. Therefore, oxygen vacancies in the semiconductor layer 11 can be reduced. Furthermore, by using an insulator that has barrier properties against oxygen as the insulating layer 31, the diffusion of oxygen from the semiconductor layer 11 to other layers can be suppressed, and the formation of oxygen vacancies in the semiconductor layer 11 can be suppressed. It is particularly preferable to suppress the formation of oxygen vacancies in the channel formation region of the semiconductor layer 11.

[0102] It is preferable to use materials with low contact resistance with the source region and drain region of the semiconductor layer 11 as conductive layers 14a and 14b.

[0103] The conductive layers 14a and 14b have one or more materials selected from, for example, metal elements, metal alloys, metal nitrides, metal alloy nitrides, etc. In the regions of the conductive layers 14a and 14b that are in contact with the semiconductor layer 11, it is preferable to use a material from among these materials that has low contact resistance with the semiconductor layer 11.

[0104] Furthermore, the conductive layers 14a and 14b have, for example, a conductive metal oxide (also called an oxide conductor). Examples of oxide conductors include oxides having one or more selected from indium, tin, zinc, and titanium. In addition to one or more selected from these elements, oxides containing silicon can also be used. More specifically, examples of metal oxides include indium tin oxide (In-Sn oxide, also called ITO), silicon-containing indium tin oxide (also called ITSO), indium zinc oxide (In-Zn oxide, also called IZO®), and indium titanium oxide (In-Ti oxide). Since oxide conductors can maintain their conductivity even when absorbing oxygen, the contact resistance with the semiconductor layer 11 can be reduced even when a metal oxide is used as the semiconductor layer 11.

[0105] In a semiconductor device according to one aspect of the present invention, ITO can be used for the conductive layer 14a and conductive layer 14b. By using ITO, the contact resistance with the semiconductor layer 11 can be reduced. Furthermore, when indium oxide is used as the semiconductor layer 11, for example, ITO can reduce the potential barrier between the semiconductor layer 11 and the source electrode and drain electrode. Also, depending on its composition, ITO has the same cubic crystal structure as indium oxide. Therefore, ITO may act as a nucleus to promote the crystal growth of indium oxide. This can, for example, increase the crystallinity of indium oxide. In this case, the crystal orientation of the first crystalline portion of the ITO and the second crystalline portion of the indium oxide on the first crystalline portion are approximately coincidental.

[0106] Furthermore, in a semiconductor device according to one embodiment of the present invention, nickel can be used for the conductive layer 14a and conductive layer 14b. Since nickel is not easily oxidized, even when it is provided in contact with an oxide or oxygen-containing layer, a decrease in conductivity due to oxidation is less likely to occur, and it can be suitably used as the conductive layer 14a and conductive layer 14b.

[0107] The conductive layers 14a and 14b may also have a laminated structure. Figure 3E shows an example in which the conductive layer 14a has a laminated structure of conductive layer 14a1 and conductive layer 14a2 on conductive layer 14a1, and the conductive layer 14b has a laminated structure of conductive layer 14b1 and conductive layer 14b2 on conductive layer 14b1.

[0108] When conductive layers 14a and 14b are arranged in a laminated structure, it is particularly preferable to use a material with low contact resistance with the semiconductor layer 11 for the layer in contact with the semiconductor layer 11 (conductive layer 14a2 and conductive layer 14b2 in Figure 3E). Furthermore, a material with higher conductivity than the layer in contact with the semiconductor layer 11 can be used for the layer not in contact with the semiconductor layer 11 (conductive layer 14a1 and conductive layer 14b1 in Figure 3E). This allows conductive layers 14a and 14b to function as highly conductive wiring or electrodes.

[0109] Furthermore, the layer that does not come into contact with the semiconductor layer 11 can be made of a material that suppresses the diffusion of impurities. For example, metal nitrides can be used.

[0110] The conductive layer 13 is preferably provided extending in the channel width direction, as shown in Figure 3A and the like. With this configuration, when multiple transistors are provided, the conductive layer 13 functions as wiring.

[0111] The conductive layer 13 has one or more materials selected from, for example, a metal element, a metal alloy, a metal nitride, a nitride of a metal alloy, etc. The conductive layer 13 may also have a laminated structure. Each layer of the laminated structure has one or more materials selected from, for example, a metal element, a metal alloy, a metal nitride, a nitride of a metal alloy, etc. One or more of the layers of the laminated structure may have, for example, an oxide conductor.

[0112] In one embodiment of the present invention, as shown in Figure 3C, the channel formation region of the semiconductor layer 11 can be surrounded by the electric field of the conductive layer 13, which can function as the gate of a transistor. Such a structure can be called a surrounded channel (S-channel) structure. By using an S-channel structure, for example, resistance to short-channel effects can be improved.

[0113] As shown in Figure 3C, the width W11 of the semiconductor layer 11 in the channel width direction of the transistor 10 is narrower than the width W15 of the insulating layer 15, and in Figure 3C, the side surface of the semiconductor layer 11 is located inward from the side surface of the insulating layer 15. In this configuration, the channel formation region of the semiconductor layer 11 can be provided only in the region that overlaps with the upper surface of the insulating layer 15.

[0114] As shown in Figure 3C, the insulating layer 12 and the conductive layer 13 are provided within the opening in the insulating layer 31. During etching to create the opening in the insulating layer 31, depending on the etching conditions, layers other than the insulating layer 31 may also be removed, as shown in the following modified examples.

[0115] Here, Figure 4A is a top view of a semiconductor device, Figure 4B is a cross-sectional view along the cutting line A1-A2 in Figure 4A, Figure 4C is a cross-sectional view along the cutting line B1-B2 in Figure 4A, and Figure 4D is a cross-sectional view along the cutting line B3-B4 in Figure 4A.

[0116] As shown in Figures 4A to 4C, when the width W11 is wider than the width W15, the semiconductor layer 11 may have a region that covers the side surface of the insulating layer 15, in addition to the region that overlaps with the upper surface of the insulating layer 15, and a region that covers the upper surface of the insulating layer 22. Also, as shown in Figure 4D, the semiconductor layer 11 has a region that covers the side surface of the conductive layer 14b. By covering the side surface of the conductive layer 14b, the contact area between the semiconductor layer 11 and the conductive layer is increased, which may reduce the resistance. The same applies to the conductive layer 14a, although it is not shown.

[0117] On the other hand, the configurations shown in Figures 3A to 3E allow for a smaller transistor footprint compared to the configurations shown in Figures 4A to 4D. This enables miniaturization of semiconductor devices.

[0118] In the semiconductor device shown in Figures 4A to 4C, the semiconductor layer 11 is in contact with the upper surface of the insulating layer 15, the side surface of the insulating layer 15, and the upper surface of the insulating layer 22, respectively.

[0119] Furthermore, in Figures 4A to 4D, the width of the conductive layer 14a and the width of the conductive layer 14b are narrower than that of the semiconductor layer 11, and the semiconductor layer 11 is in contact with the upper surface of the conductive layer 14a, the upper surface of the conductive layer 14b, the side surface of the conductive layer 14a, and the side surface of the conductive layer 14b, respectively.

[0120] [Example of Semiconductor Device Configuration 2-1] Figures 5A to 6D show a semiconductor device including the configuration shown in Figure 1C. Figure 5A is a perspective view of the semiconductor device, and Figure 6A is a top view of the semiconductor device shown in Figure 5A. The semiconductor devices shown in Figures 5A and 6A have a transistor 10. Figures 6B, 6C, and 6D are cross-sectional views corresponding to the cutting lines A1-A2, B1-B2, and B3-B4 in Figure 6A, respectively. Figure 6B corresponds to the cross-section in the channel length direction of the transistor 10, and Figures 6C and 6D correspond to the cross-section in the channel width direction, respectively. Note that in Figure 5A, the insulating layers 31 and 32 are shown as dotted lines and made transparent to make other elements easier to see.

[0121] Figure 5B omits the insulating layers 31, 32, and 13 of Figure 5A, and shows the insulating layers 17 and 18 as dotted lines to allow transparency, making the other elements easier to see. Figure 5C exposes the cross-section by cutting a part of Figure 5A.

[0122] The semiconductor device includes a substrate (not shown), an insulating layer 21 provided on the substrate, an insulating layer 29 on the insulating layer 21, an insulating layer 22 on the insulating layer 29, a transistor 10 on the insulating layer 22, an insulating layer 16a, and an insulating layer 16b. The transistor 10 includes a conductive layer 14a, a conductive layer 14b, and a semiconductor layer 11, as well as an insulating layer 12 and a conductive layer 13 on the semiconductor layer 11. The insulating layer 16a is located on the conductive layer 14a, and the insulating layer 16b is located on the conductive layer 14b. An insulating layer 17 is provided on the insulating layer 22, an insulating layer 31 is provided on the insulating layer 17, insulating layer 16a, and insulating layer 16b, and an insulating layer 32 is provided on the insulating layer 31, insulating layer 12, and conductive layer 13. The insulating layer 12 and the conductive layer 13 are located within the openings of the insulating layer 31. The conductive layer 14a, conductive layer 14b, and semiconductor layer 11, etc., are located within the opening of the insulating layer 17.

[0123] The semiconductor layer 11 functions as a semiconductor layer of the transistor 10. The conductive layers 14a and 14b function as one and the other source and drain electrodes of the transistor 10. The insulating layer 12 functions as a gate insulating layer of the transistor 10. The conductive layer 13 functions as a gate electrode of the transistor 10.

[0124] It is preferable to use a metal oxide that functions as an oxide semiconductor as the semiconductor layer 11.

[0125] It is preferable that the semiconductor layer 11 is in contact with the side surface of the conductive layer 14a and the side surface of the conductive layer 14b. In the semiconductor device shown in Figures 5A to 6D, the semiconductor layer 11 is in contact with the side surface of the insulating layer 16a and the side surface of the insulating layer 16b.

[0126] In the configuration shown in Figures 5A to 6D, the semiconductor layer 11 has a fourth region in contact with the side surface of the conductive layer 14a, a fifth region in contact with the side surface of the conductive layer 14b, and a sixth region located between the fourth and fifth regions. The insulating layer 12 is in contact with the upper surface of the sixth region. The conductive layer 13 overlaps with the sixth region with the insulating layer 12 in between.

[0127] In the semiconductor layer 11, the region facing the side surface of the conductive layer 14a and the region facing the side surface of the conductive layer 14b can function as one of the source region and the other of the drain region, respectively.

[0128] In the transistor 10 shown in Figures 5A to 6D, in a plan view, the region between the conductive layer 14a and the conductive layer 14b overlaps with the conductive layer 13. The semiconductor layer 11 is provided to cover the upper surface of the insulating layer 22, the side of the conductive layer 14a facing the conductive layer 14b, the side of the insulating layer 16a facing the insulating layer 16b, the side of the conductive layer 14b facing the conductive layer 14a, and the side of the insulating layer 16b facing the insulating layer 16a. In Figure 6B and the like, the first side of the conductive layer 14a and the second side of the conductive layer 14b face each other, and the semiconductor layer 11 has a first region in contact with the first side, a second region in contact with the second side, and a third region located between the first and second regions and covering the upper surface of the insulating layer 22. The third region is also in contact with, for example, the upper surface of the insulating layer 29. The insulating layer 12 is provided on the semiconductor layer 11 so as to cover the recesses of the semiconductor layer 11. The conductive layer 13 covers the recesses of the semiconductor layer 11 with the insulating layer 12 in between. The first region and the second region can function as one or the other of the source region and drain region, respectively. The third region can function as a channel formation region. In the semiconductor layer 11, the region between the source region and the drain region functions as the channel formation region. In a plan view, the channel formation region of the semiconductor layer 11 overlaps with the conductive layer 13.

[0129] Furthermore, the insulating layer 12 is provided along the side surface of the opening in the insulating layer 31. The conductive layer 13 is provided along the side surface of the opening in the insulating layer 31, with the insulating layer 12 in between. The upper surface of the conductive layer 13 is flattened and is roughly aligned with the upper surface of the insulating layer 31.

[0130] The insulating layer 16a has a portion located between the upper surface of the conductive layer 14a and the insulating layer 12. The insulating layer 16b also has a portion located between the upper surface of the conductive layer 14b and the insulating layer 12. By providing the insulating layer 16a, the distance between the conductive layer 14a and the conductive layer 13 can be increased, thereby reducing parasitic capacitance. Similarly, by providing the insulating layer 16b, the distance between the conductive layer 14b and the conductive layer 13 can be increased, thereby reducing parasitic capacitance.

[0131] By using insulating layers 16a and 16b that have the function of supplying oxygen, oxygen is supplied to the semiconductor layer 11, and the V of the semiconductor layer 11 Ｏ This can be reduced.

[0132] Furthermore, by using insulating layers having barrier properties against oxygen as insulating layers 16a and 16b, the desorption of oxygen from the semiconductor layer 11 can be suppressed. In addition, oxidation of the conductive layers 14a and 14b can be suppressed, thereby preventing a decrease in the conductivity of the conductive layers 14a and 14b, as well as volume changes due to oxidation.

[0133] By using an insulating layer 29 that has the function of supplying oxygen, oxygen is supplied to the semiconductor layer 11, and the V of the semiconductor layer 11 Ｏ This can be reduced.

[0134] Furthermore, an insulating layer having barrier properties against oxygen can be used as the insulating layer 29. This makes it possible to suppress the diffusion of oxygen into the layer provided below the insulating layer 15.

[0135] The insulating layer 17 is preferably made of a material with a high selectivity ratio during the etching process that forms openings in the insulating layer 31. This allows the insulating layer 17 to function as an etching stopper. Here, selectivity ratio refers to the ratio of etching rates to those of different materials. For example, if the etching rate of the insulating layer 31 is ER1 and the etching rate of the insulating layer 17 is ER2, a high selectivity ratio means that the value of ER1 / ER2 is high.

[0136] Furthermore, it is preferable that the etching rate of the insulating layer 16 is sufficiently slow during the planarization process of the insulating layer 17.

[0137] Based on the above, when silicon oxide is used as the insulating layer 31 and aluminum oxide is used as the insulating layer 16, it is preferable to use silicon nitride as the insulating layer 17.

[0138] The materials that can be used as insulating layer 22, insulating layer 21, insulating layer 32, insulating layer 31, and insulating layer 12 can be found by referring to the description in the previous example of configuration.

[0139] The semiconductor layer 11 is in contact with the side surface of the conductive layer 14a and the side surface of the conductive layer 14b. In the regions of the conductive layer 14a and conductive layer 14b that are in contact with the semiconductor layer 11, it is preferable to use a material with low contact resistance with the semiconductor layer 11.

[0140] The materials that can be used as conductive layer 14a and conductive layer 14b can be found by referring to the description in the previous example of configuration.

[0141] The conductive layers 14a and 14b can also have a laminated structure. Figure 6E shows an example in the configuration shown in Figure 6B in which the conductive layer 14a has a laminated structure of conductive layer 14a_1 and conductive layer 14a_2 on conductive layer 14a_1, and the conductive layer 14b has a laminated structure of conductive layer 14b_1 and conductive layer 14b_2 on conductive layer 14b_1. In the configuration shown in Figure 6E, the semiconductor layer 11 is in contact with both conductive layer 14a_1 and conductive layer 14a_2. Also, as shown in Figure 6F, by providing the lower conductive layers (conductive layer 14a_1 and conductive layer 14b_1) along the semiconductor layer 11, it is possible to have a configuration in which only one layer is in contact with the semiconductor layer 11, rather than multiple layers being in contact.

[0142] When conductive layers 14a and 14b are arranged in a laminated structure, it is particularly preferable to use a material with low contact resistance with the semiconductor layer 11 for the layer in contact with the semiconductor layer 11 (conductive layer 14a_1 and conductive layer 14b_1 in Figure 6E). Furthermore, a material with higher conductivity than the layer in contact with the semiconductor layer 11 can be used for the layer not in contact with the semiconductor layer 11 (conductive layer 14a_2 and conductive layer 14b_2 in Figure 6E). This allows conductive layers 14a and 14b to function as highly conductive wiring or electrodes.

[0143] Furthermore, the layer that does not come into contact with the semiconductor layer 11 can be made of a material that suppresses the diffusion of impurities. For example, metal nitrides can be used.

[0144] For materials that can be used as the conductive layer 13, refer to the description in the previous example configuration.

[0145] Figure 7A is a top view of a semiconductor device, Figure 7B is a cross-sectional view along the cutting line A1-A2 in Figure 7A, Figure 7C is a cross-sectional view along the cutting line B1-B2 in Figure 7A, and Figure 7D is a cross-sectional view along the cutting line B3-B4 in Figure 7A.

[0146] In the configurations shown in Figures 5A to 6D, an example is shown where the insulating layer 21, insulating layer 22, and insulating layer 29 are located in that order from the bottom layer. However, as shown in Figures 7A to 7D, it is also possible to have a configuration where the insulating layer 29 is located on the insulating layer 21, the insulating layer 22 is located on the insulating layer 29, and the conductive layer 14a, conductive layer 14b, and semiconductor layer 11 are located on the insulating layer 22. Since the semiconductor layer 11 can be provided in contact with the insulating layer 22, the effect of hydrogen gettering from the semiconductor layer 11 may be further enhanced.

[0147] Here, Figure 8A is a top view of a semiconductor device, Figure 8B is a cross-sectional view along the cutting line A1-A2 in Figure 8A, Figure 8C is a cross-sectional view along the cutting line B1-B2 in Figure 8A, and Figure 8D is a cross-sectional view along the cutting line B3-B4 in Figure 8A.

[0148] As shown in Figures 8A to 8D, a configuration without an insulating layer 29 is also possible. By not providing an insulating layer 29, the manufacturing process of the semiconductor device can be simplified. Furthermore, in the etching process during the processing of the conductive layers 14a and 14b, if the etching selectivity of the material used for the insulating layer 22 is high, the insulating layer 22 can function as an etching stopper. Here, a high selectivity means, for example, that if the etching rate of the conductive layers that become conductive layers 14a and 14b is ER3 and the etching rate of the insulating layer 22 is ER4, then a high selectivity means that the value of ER3 / ER4 is high. This means that the etching rate of the insulating layer 22 is sufficiently lower than the etching rate of the conductive film that becomes conductive layers 14a and 14b.

[0149] [Semiconductor Device Configuration Example 2-2] The semiconductor devices shown in Figures 9A to 9E differ from those in Figures 8A to 8D mainly in that they have an insulating layer 18. Figure 9A is a top view of the semiconductor device. The semiconductor device shown in Figure 9A has a transistor 10. Figures 9B, 9C, and 9D are cross-sectional views corresponding to the cutting lines A1-A2, B1-B2, and B3-B4 in Figure 9A, respectively. Figure 9E is a perspective view of the semiconductor device shown in Figure 9A. In Figure 9E, the insulating layer 18, insulating layer 31, and insulating layer 32 are shown as dotted lines and made transparent to make other elements easier to see.

[0150] The insulating layer in which the insulating layer 12 and the conductive layer 13 are embedded may have a laminated structure of insulating layer 18 and insulating layer 31, as shown in Figures 9A to 9E as an example. By using an insulating layer with higher oxygen barrier properties than insulating layer 31 as insulating layer 18, it may be possible to suppress the diffusion of oxygen from the layer above insulating layer 31 to conductive layer 14a and conductive layer 14b. If an insulating layer with high oxygen barrier properties is used as insulating layer 17, it may not be necessary to provide insulating layer 18.

[0151] In Figures 9A to 9E, an insulating layer 18 is located on insulating layers 17, 16a, and 16b, and an insulating layer 31 is located on insulating layer 18. Openings are provided in insulating layer 18 and insulating layer 31, and insulating layer 12 and conductive layer 13 are provided to fill these openings.

[0152] [Modification 1-1] In the semiconductor device shown in Figures 10A to 10C, the shape of the insulating layer 15_1 differs from that in Figures 2A to 3D, and the portion of the insulating layer 15_1 that is not covered by the semiconductor layer 11 has been removed.

[0153] Figure 10A is a top view of the semiconductor device, Figure 10B is a cross-sectional view along the cutting line B1-B2 in Figure 10A, and Figure 10C is a perspective view of the semiconductor device. The cross-sectional views along the cutting lines A1-A2 and B3-B4 in Figure 10A can be found in Figures 3B and 3D, respectively. Note that in Figure 10C, the insulating layer 12, conductive layer 13, insulating layer 31, and insulating layer 32 are omitted, and the semiconductor layer 11 is shown as a dotted line and is transparent.

[0154] Figure 10D shows the state before the insulating layer 15_1 is removed. The insulating layer 15_1 has a region that is not covered by the semiconductor layer 11. When the same material as the insulating layer 31 is used for the insulating layer 15_1, this region may be removed during etching to create an opening in the insulating layer 31. In Figure 10C, the region of the insulating layer 15_1 that is not covered by the semiconductor layer 11 has been removed.

[0155] In Figure 10C, the insulating layer 12 covers the side surface of the insulating layer 15_2.

[0156] [Modification 1-2] In the semiconductor device shown in Figures 11A to 11C, the shape of the insulating layer 15_2 differs from that in Figures 2A to 3D, and the portion of the insulating layer 15_2 that is not covered by the semiconductor layer 11 has been removed.

[0157] Figure 11A is a top view of the semiconductor device, Figure 11B is a cross-sectional view along the cutting line B1-B2 in Figure 11A, and Figure 11C is a perspective view of the semiconductor device. The cross-sectional views along the cutting lines A1-A2 and B3-B4 in Figure 11A can be found in Figures 3B and 3D, respectively. Note that in Figure 11C, the insulating layer 12, conductive layer 13, insulating layer 31, and insulating layer 32 are omitted, and the semiconductor layer 11 is shown as a dotted line and is transparent.

[0158] When the same material as the insulating layer 31 is used for the insulating layer 15_2, the area of ​​the insulating layer 15_2 not covered by the semiconductor layer 11 may be removed during etching to create an opening in the insulating layer 31. In the configurations shown in Figures 11A to 11C, the area of ​​the insulating layer 15_2 not covered by the semiconductor layer 11 is removed. The removed area is filled with the insulating layer 12, and the insulating layer 12 covers the side surface of the insulating layer 15_2, as shown in Figure 11B.

[0159] [Modification 1-3] Figure 12A is a top view of a semiconductor device, Figure 12B is a cross-sectional view of the cutting line A1-A2 in Figure 12A, Figure 12C is a cross-sectional view of the cutting line B1-B2 in Figure 12A, and Figure 12D is a cross-sectional view of the cutting line B3-B4 in Figure 12A.

[0160] The semiconductor device shown in Figures 12A to 12D has a different shape for the insulating layer 15 compared to Figures 2A to 3D, with widths W11 and W15 being approximately the same.

[0161] When the insulating layer 15 is a single-layer structure and uses the same material as the insulating layer 31, the area of ​​the insulating layer 15 not covered by the semiconductor layer 11 may be removed during etching to create an opening in the insulating layer 31. In this case, as shown in Figure 12C, the side surface of the insulating layer 15 can be configured to roughly coincide with the side surface of the semiconductor layer 11. Compared to the configuration shown in Figure 3C, the configuration shown in Figure 12C allows the conductive layer 13 covering the side surface of the insulating layer 15 to be closer to the semiconductor layer 11. Since the conductive layer 13 can surround the channel formation region of the semiconductor layer 11 at a closer position, the advantages of the S-channel structure can be further enhanced. In addition, the coverage of the thin film formed in a later process (for example, the insulating film that becomes the insulating layer 12) can be improved, and the yield during the manufacturing process can be improved.

[0162] [Modification 1-4] Figures 13A to 13D show an example configuration in which the insulating layer 31 is not provided. Figure 13B is a cross-sectional view of the cutting line A1-A2 in Figure 13A, Figure 13C is a cross-sectional view of the cutting line B1-B2 in Figure 13A, and Figure 13D is a cross-sectional view of the cutting line B3-B4 in Figure 13A.

[0163] Furthermore, Figures 14A to 14D differ from Figures 13A to 13D in that the region of the insulating layer 12 that is not covered by the conductive layer 13 is removed.

[0164] By omitting the insulating layer 31, the manufacturing process can sometimes be simplified. Furthermore, since damage to the semiconductor layer 11 due to etching during the formation of the openings in the insulating layer 31 is eliminated, the electrical characteristics of the transistor can be improved, and its reliability can be enhanced.

[0165] [Modification 2-1] The semiconductor layer 11 may also have regions provided on the insulating layer 16a and the insulating layer 16b.

[0166] The configurations shown in Figures 15A to 15D differ from those in Figures 8A to 8D, etc., mainly in that the semiconductor layer 11 is also provided on the upper surfaces of the insulating layers 16a and 16b. In addition, in Figures 15A to 15D, a portion of the semiconductor layer 11 is also provided on the insulating layer 17.

[0167] By providing the semiconductor layer 11 on the insulating layer 16a and the insulating layer 16b, the distance between the conductive layer 14a and the conductive layer 13, and the distance between the conductive layer 14b and the conductive layer 13 can be increased. Furthermore, by supplying oxygen to the region of the semiconductor layer 11 that is in contact with the upper surface of the insulating layer 16a and the region that is in contact with the upper surface of the insulating layer 16b, these regions can behave as a dielectric, for example, without having low resistance. Therefore, by providing the semiconductor layer 11 on the insulating layer 16a and the insulating layer 16b, it may be possible to reduce the parasitic capacitance between the conductive layer 14a or the conductive layer 14b and the conductive layer 13.

[0168] [Modification 2-2] Figure 16A is a top view of a semiconductor device, Figure 16B is a cross-sectional view of the cutting line A1-A2 in Figure 16A, Figure 16C is a cross-sectional view of the cutting line B1-B2 in Figure 16A, Figure 16D is a cross-sectional view of the cutting line B3-B4 in Figure 16A, and Figure 16E is a cross-sectional view of the cutting line B5-B6 in Figure 16A.

[0169] The configurations shown in Figures 16A to 16E differ from those in Figures 15A to 15D mainly in that the insulating layer 17 and the insulating layer 31 are not provided. Furthermore, because the insulating layer 17 and the insulating layer 31 are not provided, the conductive layer 13 covers the sides of the semiconductor layer 11, the sides of the conductive layer 14b, the sides of the insulating layer 16b, etc., as shown in the cross-sections of Figures 16B, 16E, etc.

[0170] [Modification 2-3] As shown in Figures 17A to 17E, the semiconductor layer 11 can also be configured to be in contact with both the side and top surfaces of the conductive layer 14a and the conductive layer 14b. This reduces the contact resistance between the semiconductor layer 11 and the conductive layer 14a or the conductive layer 14b.

[0171] Figure 17A is a top view of a semiconductor device, Figure 17B is a cross-sectional view of the cutting line A1-A2 in Figure 17A, Figure 17C is a cross-sectional view of the cutting line B1-B2 in Figure 17A, Figure 17D is a cross-sectional view of the cutting line B3-B4 in Figure 17A, and Figure 17E is a cross-sectional view of the cutting line B5-B6 in Figure 17A.

[0172] The configurations shown in Figures 17A to 17E differ from those in Figures 16A to 16E in that the shapes of the conductive layer 14a, conductive layer 14b, insulating layer 16a, and insulating layer 16b are different.

[0173] In Figures 17A to 17E, the insulating layer 16a is located on the conductive layer 14a. The conductive layer 14a has a region in contact with the lower surface of the insulating layer 16a and a region in contact with the first side surface of the insulating layer 16a. The first side surface of the insulating layer 16a faces the semiconductor layer 11 with the conductive layer 14a in between. The semiconductor layer 11 has a seventh region in contact with the side surface of the conductive layer 14a, an eighth region in contact with the upper surface of the conductive layer 14a, and a ninth region in contact with the upper surface of the insulating layer 16a.

[0174] In Figures 17A to 17E, the insulating layer 16b is located on the conductive layer 14b. The conductive layer 14b has a region in contact with the lower surface of the insulating layer 16b and a region in contact with the first side surface of the insulating layer 16b. The first side surface of the insulating layer 16b faces the semiconductor layer 11 with the conductive layer 14b in between. The semiconductor layer 11 has a tenth region in contact with the side surface of the conductive layer 14b, an eleventh region in contact with the upper surface of the conductive layer 14b, and a twelfth region in contact with the upper surface of the insulating layer 16a.

[0175] The first side surface of the insulating layer 16a and the first side surface of the insulating layer 16b face each other with the conductive layer 14a, the seventh region of the semiconductor layer 11, the insulating layer 12, the conductive layer 13, the tenth region of the semiconductor layer 11, and the conductive layer 14b sandwiched between them.

[0176] In the configurations shown in Figures 16A to 16E and Figures 17A to 17E, the insulating layer 17 and the insulating layer 31 are not provided, thus simplifying the manufacturing process.

[0177] [Example of semiconductor device configuration 3-1] The semiconductor device may also have a configuration that includes a first gate and a second gate.

[0178] The configuration shown in Figures 18A to 18D differs from the semiconductor device shown in Figures 2A to 3D mainly in that it has a conductive layer 23, an insulating layer 25, and an insulating layer 24.

[0179] Figure 18A is a top view of a semiconductor device, Figure 18B is a cross-sectional view along the cutting line A1-A2 in Figure 18A, Figure 18C is a cross-sectional view along the cutting line B1-B2 in Figure 18A, and Figure 18D is a cross-sectional view along the cutting line B3-B4 in Figure 18A.

[0180] An insulating layer 25 and a conductive layer 23 are provided on the insulating layer 24, and an insulating layer 21 is provided on the insulating layer 25 and on the conductive layer 23. The conductive layer 23 overlaps with the semiconductor layer 11 with insulating layers 21, 22, and 15 in between. The conductive layer 23 also overlaps with the conductive layer 13 with insulating layers 21, 22, 15, 11, and 22 in between.

[0181] The conductive layer 23 is provided so as to be embedded in the insulating layer 25.

[0182] The conductive layer 13 can function as a first gate (also called a front gate), and the conductive layer 23 can function as a second gate (also called a back gate).

[0183] Furthermore, insulating layers 21, 22, and 15 can function as gate insulating layers corresponding to the second gate.

[0184] The conductive layer 23 can be made of a material that can be used for the conductive layer 13. Furthermore, the conductive layer 23 may have a laminated structure.

[0185] [Example of semiconductor device configuration 3-2] Figures 19A to 20D show an example of conductive layers that function as plugs connecting conductive layer 14a and conductive layer 14b to a lower or upper layer.

[0186] Figures 19A to 19D show a configuration in which conductive layer 240a, conductive layer 240b, insulating layer 241a, and insulating layer 241b are added to Figures 18A to 18D.

[0187] In Figures 19A to 19D, openings are provided in insulating layers 24, 25, 21, and 22, and conductive layers 240a and 241a are provided within these openings. Insulating layer 241a is provided in contact with the side wall of the opening, and conductive layer 240a is provided inside insulating layer 241a. In addition, openings are formed in insulating layers 24, 25, 21, and 22, and conductive layers 240b and 241b are provided within these openings. Insulating layer 241b is provided in contact with the side wall of the opening, and conductive layer 240b is provided inside insulating layer 241b. Conductive layer 14a is provided in contact with conductive layer 240a, and conductive layer 14b is provided in contact with conductive layer 240b. Conductive layers 240a and 240b function as vias connecting wiring etc. provided in the lower layer of transistor 10 to the source or drain of transistor 10.

[0188] Figures 20A to 20D show a configuration in which conductive layer 270a, conductive layer 270b, insulating layer 271a, and insulating layer 271b are added to Figures 18A to 18D.

[0189] In Figures 20A to 20D, the insulating layer 32, insulating layer 31, and semiconductor layer 11 are provided with openings that reach the conductive layer 14a, and the conductive layer 270a and insulating layer 271a are provided within these openings. The insulating layer 271a is provided in contact with the side wall of the opening, and the conductive layer 270a is provided inside the insulating layer 271a. Furthermore, the insulating layer 32, insulating layer 31, and semiconductor layer 11 are provided with openings that reach the conductive layer 14b, and the conductive layer 270b and insulating layer 271b are provided within these openings. The insulating layer 271b is provided in contact with the side wall of the opening, and the conductive layer 270b is provided inside the insulating layer 271b. The conductive layers 270a and 270b function as vias connecting wiring etc. provided on the upper layer of the transistor 10 to the source or drain of the transistor 10.

[0190] In Figures 20A to 20D, the semiconductor layer 11 is provided with openings into which the conductive layer 270a, conductive layer 270b, etc., are embedded. However, it is also possible to have a configuration in which the semiconductor layer 11 does not have openings, and the upper surface of the semiconductor layer 11 is in contact with the conductive layer 270a, or the upper surface of the semiconductor layer 11 is in contact with the conductive layer 270b.

[0191] For example, conductive layers 240a and 240b are preferably made of conductive materials mainly composed of tungsten, copper, or aluminum. Furthermore, conductive layers 240a and 240b can also be arranged in a laminated structure.

[0192] The conductive layers 270a and 270b are preferably made of conductive materials mainly composed of tungsten, copper, or aluminum. Furthermore, the conductive layers 270a and 270b can also be arranged in a laminated structure.

[0193] As insulating layers 271a, 271b, 241a, and 241b, insulating layers having barrier properties against oxygen, insulating layers having barrier properties against hydrogen, etc., can be used as appropriate.

[0194] The conductive layers 240a, 240b, 270a, and 270b can each be configured as a two-layer laminated structure. For example, the lower conductive layer may be formed along the opening, and the upper conductive layer may be formed to fill the recess along the opening.

[0195] It is preferable to use a conductive material such as tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide for the lower layer, which has the function of suppressing the permeation of impurities such as water and hydrogen. Furthermore, it is preferable to use a conductive layer with a higher conductivity than the conductive layer used in the lower layer for the upper layer.

[0196] [Example of semiconductor device configuration 3-3] Figure 21A is a top view of a semiconductor device, Figure 21B is a cross-sectional view of the cutting line A1-A2 in Figure 21A, Figure 21C is a cross-sectional view of the cutting line B1-B2 in Figure 21A, and Figure 21D is a cross-sectional view of the cutting line B3-B4 in Figure 21A.

[0197] The configuration shown in Figures 21A to 21D differs from the semiconductor device shown in Figures 9A to 9E in that it has a conductive layer 23, an insulating layer 25, and an insulating layer 24. In Figures 21A to 21D, the conductive layer 13 can function as a first gate, and the conductive layer 23 can function as a second gate.

[0198] [Example of semiconductor device configuration 3-4] Figures 22A to 22D show a configuration in which conductive layer 240a, conductive layer 240b, insulating layer 241a, and insulating layer 241b are added to Figures 21A to 21D.

[0199] For conductive layer 240a, conductive layer 240b, insulating layer 241a, and insulating layer 241b, refer to the previous descriptions, for example, those shown in Figures 19A to 19D.

[0200] Figures 23A to 23D show a configuration in which conductive layer 270a, conductive layer 270b, insulating layer 271a, and insulating layer 271b are added to the configuration shown in Figures 21A to 21D.

[0201] In Figures 23A to 23D, the insulating layer 32, insulating layer 31, and insulating layer 16a are provided with openings that reach the conductive layer 14a, and the conductive layer 270a and insulating layer 271a are provided within these openings. The insulating layer 271a is provided in contact with the side wall of the opening, and the conductive layer 270a is provided inside the insulating layer 271a. In addition, the insulating layer 32, insulating layer 31, and insulating layer 16b are provided with openings that reach the conductive layer 14b, and the conductive layer 270b and insulating layer 271b are provided within these openings. The insulating layer 271b is provided in contact with the side wall of the opening, and the conductive layer 270b is provided inside the insulating layer 271b. The conductive layers 270a and 270b function as vias connecting wiring etc. provided on the upper layer of the transistor 10 to the source or drain of the transistor 10.

[0202] Regarding the materials that can be used for the conductive layer 270a, conductive layer 270b, insulating layer 271a, and insulating layer 271b, refer to the above descriptions, for example, the descriptions in Figures 20A to 20D.

[0203] [Example of Manufacturing Method 1-1] Below, an example of a method for manufacturing a semiconductor device having a transistor according to one aspect of the present invention will be described. Here, a semiconductor device having the transistor 10 illustrated in Figures 2A to 3D will be used as an example.

[0204] Figures 25A1, 25B1, 25C1, 25D1, 26A1, 26B1, 26C1, and 27A1 are schematic cross-sectional views of each stage of the example manufacturing method illustrated below, corresponding to the cutting line A1-A2 in Figure 3A. Figure 26C3 is a schematic cross-sectional view of each stage of the example manufacturing method illustrated below, corresponding to the cutting line B1-B2 in Figure 3A. Figures 25A2, 25B2, 25C2, 25D2, 26A2, 26B2, 26C2, and 27A2 are perspective views of each stage of the example manufacturing method illustrated below. Note that the perspective views are partially cut off. In addition, in the perspective views, only the outlines of some components (such as the insulating layer) are shown with dashed lines.

[0205] First, an insulating layer 21 is formed on a substrate (not shown), an insulating layer 22 is formed on the insulating layer 21, and a conductive layer 14 is formed on the insulating layer 22. Next, an opening that reaches the insulating layer 22 is formed in the conductive layer 14 (Figures 25A1 and 25A2).

[0206] Next, an insulating layer 15f1 is formed to cover the upper surface of the conductive layer 14, the side surface of the opening in the conductive layer 14, and the upper surface of the insulating layer 22 exposed within the opening. Subsequently, an insulating layer 15f2 is formed on top of the insulating layer 15f1 (Figures 25B1 and 25B2). At this time, it is preferable that the insulating layer 15f2 is formed to fill the opening in the conductive layer 14. By forming the insulating layer 15f1 using a method with high coverage, an insulating layer can be formed on the side surface of the conductive layer 14 at the opening and on the upper surface of the insulating layer 22 at the bottom of the opening with a film thickness distribution that has little variation. For example, the ALD method can be used.

[0207] Next, by removing the portion of insulating layer 15f1 and insulating layer 15f2 that covers the upper surface of the conductive layer 14, the upper surface of the conductive layer 14 is exposed, insulating layer 15_2 is formed from insulating layer 15f2, and insulating layer 15_1 is formed from insulating layer 15f1. A planarization treatment (also called CMP treatment) using the Chemical Mechanical Polishing (CMP) method can be used to form insulating layers 15_1 and insulating layer 15_2. By planarizing the upper surface of insulating layer 15f2, insulating layers 15f1 and insulating layer 15f2 can be left only within the openings of the conductive layer 14, thereby forming insulating layers 15_1 and insulating layer 15_2 (Figures 25C1 and 25C2).

[0208] Next, a semiconductor layer 11f is formed on the conductive layer 14 and the insulating layer 15 (Figures 25D1 and 25D2). The semiconductor layer 11f can be formed using, for example, the ALD method or the sputtering method. It is also possible to stack layers formed by the ALD method and layers formed by the sputtering method. Using the ALD method can, for example, reduce damage to the conductive layer 14. In addition, a mixed layer of the conductive layer 14 and the semiconductor layer 11f may be formed during the formation of the semiconductor layer 11f. Such a mixed layer may have low crystallinity, which may have an undesirable effect on the characteristics of the transistor. By forming the semiconductor layer 11f using the ALD method, the formation of a mixed layer of the conductive layer 14 and the semiconductor layer 11f can be suppressed. Furthermore, using the sputtering method may increase the crystallinity of the semiconductor layer 11.

[0209] After the formation of the semiconductor layer 11f, either or both of the following treatments can be performed: heat treatment and / or microwave plasma treatment. Details regarding the heat treatment and microwave plasma treatment will be described later.

[0210] Next, a portion of the semiconductor layer 11f is removed using a mask to form the semiconductor layer 11. Subsequently, the portion of the conductive layer 14 not covered by the semiconductor layer 11 is removed to form the conductive layer 14a and the conductive layer 14b (Figures 26A1 and 26A2). It is preferable that the length of the mask in the channel width direction (corresponding to the width W11 shown in Figure 3C) is smaller than the length of the insulating layer 15 in the channel width direction (corresponding to the width W15 shown in Figure 3C). This ensures that when removing the portion of the conductive layer 14 not covered by the semiconductor layer 11, the conductive layer 14 is reliably divided, and the conductive layer 14a and the conductive layer 14b can be formed. If the conductive layer 14 can be processed to form the conductive layer 14a and the conductive layer 14b, the length of the mask in the channel width direction can be the same as the length of the insulating layer 15 in the channel width direction.

[0211] In one embodiment of the present invention, a semiconductor device can form conductive layers 14 which will become conductive layers 14a and conductive layers 14b, and then form a semiconductor layer 11f which will become a semiconductor layer 11 on the conductive layer 14.

[0212] Next, an insulating layer 31 is formed on the semiconductor layer 11 and the insulating layer 22 (Figures 26B1 and 26B2).

[0213] The insulating layer 31 is preferably flattened on its upper surface using a CMP treatment or the like.

[0214] Next, the insulating layer 31 is processed to form an opening that reaches the semiconductor layer 11 (Figures 26C1, 26C2, and 26C3). At this point, a portion of the upper surface of the semiconductor layer 11 is exposed. The opening formed in the insulating layer 31 overlaps with the semiconductor layer 11.

[0215] In the case of a top contact structure, for example, a conductive layer 14 is formed on the semiconductor layer 11, and conductive layers 14a and 14b are formed by removing the portion of the conductive layer 14 that overlaps with the channel formation region of the semiconductor layer 11. More specifically, for example, an insulating layer 31 is formed on the conductive layer 14, an opening is formed in the insulating layer 31, and then the conductive layer 14 exposed within the opening is removed to form conductive layers 14a and 14b. However, during the processing of the conductive layer 14, depending on the combination of materials for the semiconductor layer 11 and the conductive layer 14, problems such as thinning of the semiconductor layer 11 or damage to the surface of the semiconductor layer 11 may occur. For example, when ITO is used as the conductive layer 14 and indium oxide is used as the semiconductor layer 11, such problems may occur depending on the etching conditions.

[0216] In one embodiment of the present invention, a semiconductor device is formed by first forming a conductive layer 14 which will become conductive layer 14a and conductive layer 14b, and then forming a semiconductor layer 11f on the conductive layer 14 which will become semiconductor layer 11. This has the advantage that the semiconductor layer 11 is less prone to defects caused by processing of the conductive layer 14. Furthermore, it has the advantage that the semiconductor layer 11f and the conductive layer 14 can be processed in a single operation.

[0217] Furthermore, when forming an opening in the insulating layer 31, there is a risk of defects such as thinning of the semiconductor layer 11 exposed within the opening, or damage to the surface of the semiconductor layer 11.

[0218] In one embodiment of the present invention, since the semiconductor layer 11 is in contact with the conductive layers 14a and 14b at its bottom or side, even if film loss or damage occurs on the upper surface of the semiconductor layer 11, the interface on the side in contact with the conductive layers 14a and 14b can be made into a high-quality semiconductor layer. Therefore, a transistor with excellent characteristics and reliability can be realized.

[0219] Furthermore, as shown in Figure 3A, when the width W15 of the insulating layer 15 is wider than the width W11 of the semiconductor layer 11, in the process of forming the opening of the insulating layer 31 shown in Figures 26C1, 26C2, and 26C3, the portion of the insulating layer 15 not covered by the semiconductor layer 11 will be exposed within the opening. Therefore, it is preferable that the insulating layer 15 is not etched under the etching conditions used to form the opening of the insulating layer 31. Thus, when silicon oxide is used as the insulating layer 15, for example, by using silicon nitride, aluminum oxide, etc., as the insulating layer 31, etching of the insulating layer 15 exposed within the opening can be suppressed.

[0220] Furthermore, if the insulating layer 15 is etched under etching conditions that form an opening in the insulating layer 31, a portion of the insulating layer 15 will be removed as shown in Figures 10A to 10D or Figures 11A to 11C.

[0221] Next, an insulating film, which will become the insulating layer 12, is formed to cover the opening formed in the insulating layer 31. Here, the insulating film is formed along the opening.

[0222] Next, a conductive film that will become the conductive layer 13 is formed. Then, the insulating film that will become the insulating layer 12 and the conductive film that will become the conductive layer 13 are polished by CMP treatment until the insulating layer 31 is exposed. In this way, the insulating layer 12 and the conductive layer 13 are formed in the opening that reaches the semiconductor layer 11.

[0223] Next, an insulating layer 32 is formed on the insulating layer 31.

[0224] Based on the above, the transistor 10 shown in Figures 3A to 3D can be manufactured.

[0225] Furthermore, it is preferable to perform a heat treatment between the formation of the semiconductor layer 11f and the formation of the conductive layer 13. For example, by performing a heat treatment at a temperature of 100°C to 700°C, oxygen can be supplied from the insulating layers such as the insulating layer 15 and insulating layer 31 to the semiconductor layer 11. In addition, by performing a heat treatment, the insulating layer 22 can getter excess hydrogen from the semiconductor layer 11.

[0226] The heat treatment is carried out, for example, in an atmosphere of nitrogen gas or an inert gas, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when heat treatment is carried out in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas content can be set to about 20%. The heat treatment may also be carried out under reduced pressure. Alternatively, after heat treatment in an atmosphere of nitrogen gas or an inert gas, heat treatment can be carried out again in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to replenish the oxygen that has been removed.

[0227] The gas used in the heat treatment is preferably highly purified. For example, the amount of water contained in the gas used in the heat treatment is preferably 1 ppb (0.001 ppm) or less, more preferably 0.1 ppb or less, and even more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent as much as possible from being incorporated into each layer constituting the semiconductor device.

[0228] In addition to or instead of heat treatment, microwave plasma treatment can also be performed.

[0229] In this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less. Microwave plasma processing refers to processing using a device that has a power supply that generates high-density plasma using microwaves, for example. Microwave plasma processing can also be called microwave-excited high-density plasma processing.

[0230] In some cases, the concentration of impurities in the semiconductor layer 11 can be reduced by performing microwave plasma treatment in an oxygen-containing atmosphere. Examples of such impurities include hydrogen and carbon.

[0231] Microwave plasma treatment is preferably carried out under reduced pressure, with a pressure of 10 Pa to 1000 Pa being preferred, more preferably 50 Pa to 700 Pa, and even more preferably 100 Pa to 400 Pa. The treatment temperature is preferably room temperature (25°C) to 750°C, more preferably 300°C to 500°C, and can be 400°C to 450°C.

[0232] When performing microwave plasma treatment, it is preferable to heat the substrate. It is preferable to heat the substrate to a temperature of room temperature (e.g., 25°C) or higher, 100°C or higher, 200°C or higher, 300°C or higher, or 400°C or higher, and 500°C or lower, or 450°C or lower.

[0233] Microwave plasma treatment can be performed using, for example, oxygen gas and argon gas. For example, the oxygen flow rate ratio (O) in microwave plasma treatment. ２ / ( O ２ The value of +Ar) is preferably greater than 0% and 10% or less, preferably between 0.5% and 5%, more preferably between 0.5% and 3%, and most preferably 1%.

[0234] By performing microwave plasma treatment in an oxygen-containing atmosphere, the oxygen gas can be plasma-generated using microwaves or high-frequency waves such as RF, and the oxygen radicals generated by the plasma-generated oxygen gas can act on the oxide semiconductor layer. Through the action of plasma, microwaves, oxygen radicals, etc., hydrogen can be added to oxygen vacancies in the oxide semiconductor layer to form defects (hereinafter referred to as V Ｏ V (sometimes called H) can be separated into oxygen vacancies and hydrogen, and the hydrogen impurity can be removed from the oxide semiconductor layer. In this way, the V contained in the oxide semiconductor layer can be separated into oxygen vacancies and hydrogen, and the hydrogen impurity can be removed from the oxide semiconductor layer. Ｏ H can be reduced. In addition, carbon that was bonded to oxygen or hydrogen can sometimes be removed at this time. In this way, impurities such as carbon or hydrogen can be reduced by microwave plasma treatment. Furthermore, by supplying the above oxygen radicals to oxygen vacancies formed in the oxide semiconductor layer, oxygen vacancies in the oxide semiconductor layer can be further reduced.

[0235] [Manufacturing Method Example 1-2] A method for forming an insulating layer 15 within the opening of the conductive layer 14 using a manufacturing process different from the manufacturing process shown in Figures 25A1 to 25C2 will be explained with reference to Figures 27B1 to 27C2.

[0236] Figures 27B1 and 27C1 are schematic cross-sectional views of each stage of the example manufacturing method illustrated below, corresponding to the cutting line A1-A2 in Figure 3A. Figures 27B2 and 27C2 are perspective views of each stage of the example manufacturing method illustrated below.

[0237] First, insulating layers 21 and 22 are formed sequentially on a substrate (not shown). Next, insulating layer 15 is formed. Note that insulating layer 15 will be thinned in subsequent steps, so at this stage, it is made thicker than the desired thickness. Next, a conductive layer 14 is formed so as to cover the sides and top surface of insulating layer 15 and the top surface of insulating layer 22 (Figures 27B1 and 27B2).

[0238] Next, the upper surfaces of the conductive layer 14 and the insulating layer 15 are flattened using CMP processing (Figures 27C1 and 27C2). This makes it possible to form the insulating layer 15 embedded in the opening of the conductive layer 14.

[0239] Subsequently, the transistor 10 shown in Figures 3A to 3D can be manufactured through the manufacturing process shown in Figures 25D1 to 27A2.

[0240] [Example of Manufacturing Method 2-1] Below, an example of a method for manufacturing a semiconductor device having a transistor according to one aspect of the present invention will be described. Here, a semiconductor device having the transistor 10 illustrated in Figures 8A to 8D will be used as an example.

[0241] Figures 28A1, 28B1, 28C1, 29A1, 29B1, 29C1, 30A1, and 30B1 are schematic cross-sectional views of each stage of the example manufacturing method illustrated below, corresponding to the cutting line A1-A2 in Figure 8A. Figure 28C3 is a schematic cross-sectional view of the same process as Figure 28C1 of the example manufacturing method illustrated below, corresponding to the cutting line B1-B2 in Figure 8A. Figures 28B2, 28C2, 29A2, 29B2, 29C2, 30A2, and 30B2 are perspective views of each stage of the example manufacturing method illustrated below. Note that the perspective views are partially cut off. In addition, in the perspective views, only the outlines of some components (such as the insulating layer) are shown with dashed lines.

[0242] First, an insulating layer 21 is formed on a substrate (not shown), and an insulating layer 22 is formed on the insulating layer 21. Next, a film that will become a conductive layer 14 and a film that will become an insulating layer 16 are formed sequentially on the insulating layer 22, and each film is processed to form the conductive layer 14 on the insulating layer 22 and the insulating layer 16 on the conductive layer 14 (Figures 28A1 and 28A2).

[0243] Next, a film that will become the insulating layer 17 is formed on the insulating layer 22 and the insulating layer 16. Subsequently, the insulating layer 17 is formed by planarizing the film (Figures 28B1 and 28B2). At this time, the portion of the film located on the insulating layer 16 is removed. This forms the conductive layer 14 and the insulating layer 16 embedded in the insulating layer 17.

[0244] Next, a portion of the insulating layer 16 is removed to form insulating layers 16a and 16b. Also, a portion of the conductive layer 14 is removed to form conductive layers 14a and 14b (Figures 28C1 to 28C3). In the cross-section shown in Figure 28C1, insulating layers 16a and 16b are spaced apart from each other, and the sides of insulating layer 16a and insulating layer 16b face each other. Also, in the cross-section shown in Figure 28C1, conductive layers 14a and 14b are spaced apart from each other, and the sides of conductive layers 14a and conductive layer 14b face each other.

[0245] Next, a semiconductor layer 11 is formed to cover the insulating layer 17, insulating layer 16a, insulating layer 16b, the side surface of insulating layer 16a, the side surface of insulating layer 16b, the side surface of conductive layer 14a, and the side surface of conductive layer 14b. Subsequently, a sacrificial layer 19 is formed on the semiconductor layer 11 (Figures 29A1 and 29A2). The sacrificial layer 19 is formed to fill the spaces between the spaced conductive layers 14a and 14b, and the spaces between the spaced insulating layers 16a and 16b.

[0246] Next, a planarization process is performed to remove the portions of the sacrificial layer 19 located on the insulating layer 16a, insulating layer 16b, and insulating layer 17, and then the portions of the semiconductor layer 11 located on the insulating layer 16a, insulating layer 16b, and insulating layer 17 are removed (Figures 29B1 and 29B2). As a result, the sacrificial layer 19 and the semiconductor layer 11 are formed between the insulating layer 16a and insulating layer 16b, and between the conductive layer 14a and conductive layer 14b. The sacrificial layer 19 is formed to fill the spaces between the insulating layer 16a and insulating layer 16b, and between the conductive layer 14a and conductive layer 14b.

[0247] Next, insulating layers 18 and 31 are formed sequentially on insulating layer 16a, insulating layer 16b, and insulating layer 17 (Figures 29C1 and 29C2). Subsequently, a mask is placed on insulating layer 31.

[0248] Next, using a mask placed on the insulating layer 31, openings are sequentially made in the insulating layer 31 and the insulating layer 18. This exposes the upper surface of the sacrificial layer 19, the upper surface of the insulating layer 16a, the upper surface of the insulating layer 16b, a part of the semiconductor layer 11, and the upper surface of the insulating layer 17 within the openings. Subsequently, the sacrificial layer 19 is removed (Figures 30A1 and 30A2). By removing the sacrificial layer 19, a semiconductor layer 11 having a recess on its upper surface is formed.

[0249] Here, it is preferable that the insulating layer 16a, insulating layer 16b, semiconductor layer 11, and insulating layer 17 have a high selectivity ratio under etching conditions such as those for insulating layer 31, insulating layer 18, and sacrificial layer 19. In particular, a high selectivity ratio with respect to the etching conditions of the sacrificial layer 19 is preferred. As an example, silicon oxide can be used for the sacrificial layer 19, aluminum oxide for insulating layers 16a and 16b, indium oxide for the semiconductor layer 11, and silicon nitride for the insulating layer 17.

[0250] Next, the insulating layer 12 and the conductive layer 13 are formed to fill the recesses on the sides of the openings in the insulating layer 31 and the insulating layer 18 and on the upper surface of the semiconductor layer 11 (Figures 30B1 and 30B2).

[0251] Based on the above, the transistor 10 shown in Figures 8A to 8D can be manufactured.

[0252] [Example of Manufacturing Method 2-2] Below, an example of a method for manufacturing a semiconductor device having a transistor according to one aspect of the present invention will be described. Here, a semiconductor device having the transistor 10 illustrated in Figures 17A to 17D will be used as an example.

[0253] Figures 31A1, 31B1, 31C1, and 32A1 are schematic cross-sectional views of each stage of the example manufacturing method illustrated below, corresponding to the cutting line A1-A2 in Figure 17A. Figures 31C3 and 32A3 are schematic cross-sectional views of each stage of the example manufacturing method illustrated below, corresponding to the cutting line B1-B2 in Figure 17A. Figures 31A2, 31B2, 31C2, and 32A2 are perspective views of each stage of the example manufacturing method illustrated below. Note that the perspective views are partially cut off. In addition, in the perspective views, only the outlines of some components (such as the insulating layer) are shown with dashed lines.

[0254] First, insulating layers 21 and 22 are formed sequentially on a substrate (not shown). Next, a sacrificial layer 20 is formed. Note that the sacrificial layer 20 will be thinned in subsequent steps, so it is made thicker than the desired thickness at this stage. Next, a conductive layer 14 is formed so as to cover the sides and top surface of the sacrificial layer 20 and the top surface of the insulating layer 22. Next, an insulating layer 16 is formed on the conductive layer 14 (Figures 31A1 and 31A2). Note that the depiction of the insulating layer 16 is omitted in Figure 31A2.

[0255] Here, sacrificial layers such as the sacrificial layer 20 are used, for example, in the manufacturing process of a semiconductor device to process other layers, and do not remain at the end of the manufacturing process.

[0256] Next, a planarization process is performed to remove the conductive layer 14 and insulating layer 16 from the sacrificial layer 20 (Figures 31B1 and 31B2). It is preferable to perform the planarization process so that the height of the upper surface of the sacrificial layer 20 and the upper surface of the insulating layer 16 are roughly the same. As a result, the sacrificial layer 20 is provided so as to be embedded in the opening of the conductive layer 14. Also, a part of the upper surface of the conductive layer 14 is exposed and not covered by the insulating layer 16.

[0257] Next, the sacrificial layer 20 is removed. Subsequently, a semiconductor layer 11f is formed to cover the upper surface of the insulating layer 16, the upper surface of the conductive layer 14, the side surface of the opening in the conductive layer 14, and the upper surface of the insulating layer 22 exposed within the opening (Figures 31C1 to 31C3).

[0258] Next, a mask is formed on the semiconductor layer 11f, and the semiconductor layer 11f is processed using the mask to form the semiconductor layer 11. Subsequently, using the same mask, or using the semiconductor layer 11 as a mask, the insulating layer 16 and the conductive layer 14 are processed in order to form the insulating layer 16a, insulating layer 16b, conductive layer 14a, and conductive layer 14b (Figures 32A1 to 32A3). The conductive layer 14a and conductive layer 14b are provided spaced apart from each other.

[0259] Next, the insulating layer 12, the conductive layer 13, and the insulating layer 32 are formed to create the transistor 10 shown in Figures 17A to 17E.

[0260] Thin films (insulating films, semiconductor films, and conductive films, etc.) that constitute semiconductor devices can be formed using sputtering, chemical vapor deposition (CVD), ALD, pulsed laser deposition (PLD), molecular beam epitaxy (MBE), vacuum deposition, and the like.

[0261] Sputtering methods include RF sputtering, which uses a high-frequency power supply; DC sputtering, which uses a DC power supply; and pulsed DC sputtering, which changes the voltage applied to the electrodes in a pulsed manner. There is also RF superimposed DC sputtering, which superimposes RF and DC. For film deposition using insulating targets, RF sputtering is preferable. DC sputtering is mainly used when depositing films using conductive targets. In addition to forming conductive films, DC sputtering can also form insulating films by performing reactive sputtering using pulsed DC sputtering. Specifically, pulsed DC sputtering can be used mainly when depositing compounds such as oxides, nitrides, and carbides using reactive sputtering. RF superimposed DC sputtering allows for control of the ion energy during film deposition and control of the target side potential. Therefore, compared to RF sputtering, damage during film deposition is reduced, and a higher quality film can be obtained.

[0262] Sputtering is a film deposition method that uses the deposition of particles emitted from a target, and it can be said that it is a film deposition method in which the deposition rate tends to be anisotropic.

[0263] For example, ionization sputtering can be used as a sputtering method. Ionization sputtering is a method in which sputtering particles generated from a target are ionized by RF or the like, and then deposited with high anisotropy due to self-bias, etc.

[0264] Furthermore, by using sputtering methods such as long-throw sputtering or collimated sputtering, it is possible to deposit films with higher anisotropy. Long-throw sputtering is a method that deposits films with high anisotropy by increasing the distance between the sputtering target and the substrate.

[0265] Furthermore, CVD methods can be classified into plasma CVD (PECVD), thermal CVD (TCD), and photo CVD (Photo CVD). They can also be further divided into metal CVD (MCCVD) and metal-organic CVD (MOCVD) depending on the source gas used.

[0266] Plasma CVD allows for the production of high-quality films at relatively low temperatures. Thermal CVD, on the other hand, does not use plasma, thus minimizing plasma damage to the workpiece. For example, wiring, electrodes, and components (transistors, capacitive elements, etc.) in semiconductor devices can be charged up by receiving charge from the plasma. This accumulated charge can damage these components. In contrast, thermal CVD, which does not use plasma, avoids such plasma damage, resulting in higher yields for semiconductor devices. Furthermore, thermal CVD produces films with fewer defects because it avoids plasma damage during deposition.

[0267] Furthermore, ALD methods that can be used include thermal ALD, which carries out the reaction of the precursor and reactant using only thermal energy, and PEALD (Plasma Enhanced ALD), which uses a plasma-excited reactant.

[0268] Furthermore, the ALD method allows for the deposition of atoms layer by layer, resulting in several advantages: the ability to deposit extremely thin films, films with high aspect ratios, films with fewer defects such as pinholes, films with excellent coverage, and films at low temperatures. The PEALD (Plasma Enhanced ALD) method, by utilizing plasma, allows for film deposition at even lower temperatures, which can be preferable in some cases. Note that precursors used in the ALD method may contain impurities such as carbon. Therefore, films formed by the ALD method may contain more impurities such as carbon compared to films formed by other deposition methods. The quantitative determination of impurities can be performed using X-ray photoelectron spectroscopy (XPS) or secondary ion mass spectrometry (SIMS). In one embodiment of the present invention, a metal oxide film formation method is used, but because it employs conditions of high substrate temperature during film formation and / or impurity removal treatment, the amount of carbon and chlorine contained in the film may be less than when the ALD method is used without applying these conditions.

[0269] Unlike film deposition methods where particles emitted from a target or the like are deposited, ALD and CVD are film deposition methods in which a film is formed by a reaction on the surface of the workpiece. Therefore, they are less affected by the shape of the workpiece and are film deposition methods that have good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of openings with a high aspect ratio. Furthermore, isotropic film deposition can be achieved by using the ALD method. The ALD method can also be described as a film deposition method with low anisotropy in deposition rate. However, because the ALD method has a relatively slow deposition rate, it is sometimes preferable to use it in combination with other film deposition methods such as sputtering or CVD, which have faster deposition rates. For example, when a metal oxide is formed as a laminated structure of a first metal oxide and a second metal oxide, one method is to deposit the first metal oxide using the sputtering method and then deposit the second metal oxide on the first metal oxide using the ALD method. For example, if the first metal oxide has a crystalline portion, the second metal oxide may grow crystals using the crystalline portion as a nucleus.

[0270] CVD and ALD methods allow for control of the composition of the resulting film by adjusting the flow rate ratio of the source gases. For example, CVD and ALD methods can deposit films of any composition by changing the flow rate ratio of the source gases. Furthermore, CVD and ALD methods can deposit films with continuously changing compositions by changing the flow rate ratio of the source gases during film deposition. When depositing films while changing the flow rate ratio of the source gases, the time required for film deposition can be shortened compared to depositing films using multiple deposition chambers, because time spent on transport and pressure adjustment is eliminated. Therefore, it may be possible to increase the productivity of semiconductor devices.

[0271] Furthermore, in the ALD method, films of any composition can be deposited by adjusting the amount of raw material gas introduced, the number of introductions (also called the number of pulses), and the time required for one pulse (also called the pulse duration). In addition, in the ALD method, films of any composition can be deposited by using multiple different types of precursors. Alternatively, when using multiple different types of precursors, films of any composition can be deposited by controlling the number of cycles for each precursor.

[0272] Furthermore, thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed by wet film deposition methods such as spin coating, dip coating, spray coating, inkjet, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, or knife coating.

[0273] Furthermore, lithography can be used to process the thin films that make up semiconductor devices. Alternatively, thin films can be processed by nanoimprint lithography, sandblasting, lift-off lithography, etc. In addition, island-shaped thin films can be directly formed by deposition methods using shielding masks such as metal masks.

[0274] There are two main lithography methods. One method involves forming a resist mask on the thin film to be processed, then processing the thin film by etching or other means, and finally removing the resist mask. The other method involves forming a photosensitive thin film, then exposing and developing it to process the thin film into the desired shape.

[0275] In lithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture thereof. Other light sources such as ultraviolet light, KrF laser light, or ArF laser light can also be used. Exposure can also be performed using immersion lithography. Furthermore, extreme ultraviolet (EUV) light or X-rays can be used as the light source for exposure. An electron beam can also be used instead of light for exposure. Using extreme ultraviolet light, X-rays, or an electron beam is preferable because it allows for extremely fine processing. Note that a photomask is not required when exposure is performed by scanning a beam such as an electron beam.

[0276] Thin film etching can be performed using methods such as dry etching, wet etching, ashing, plasma treatment, and reverse sputtering. Sandblasting can also be used for etching thin films.

[0277] For dry etching, for example, a gas containing halogens can be used as the etching gas.

[0278] As halogen-containing gases, etching gases containing one or more of fluorine, chlorine, and bromine can be used. Fluorocarbon gas, hydrofluorocarbon gas, SF ６ Gas, Cl ２ Gas, BCl ３ Gas, SiCl ４ Gas, or BBr ３ Gases can be used individually or in mixtures of two or more gases. Examples of fluorocarbon gases include C ｘ F ｙ A gas represented by (y ≤ 2x + 2) can be used. An example of a fluorocarbon gas that satisfies y = 2x + 2 is CF ４ , C ２ F ６ , C ３ F ８ , C ４ F １０ , C ５ F１２ Saturated fluorocarbon compounds such as these can be mentioned. Further, as the fluorocarbon gas satisfying y < 2x + 2, for example, C ２ F ４ , C ２ F ２ , C ３ F ７ , C ３ F ４ , C ４ F ８ , C ４ F ６ , C ４ F ４ , C ４ F ２ , C ５ F １０ , C ５ F ８ , C ５ F ６ , C ５ F ４ and other unsaturated fluorocarbon compounds can be mentioned. As the hydrofluorocarbon gas, CHF ３ gas, CH ２ F ２ gas, etc. can be mentioned.

[0279] Further, when using a gas containing a halogen as the etching gas, oxygen (O ２ ), carbon dioxide gas, nitrogen (N ２ ), helium gas, argon gas, hydrogen gas, or a hydrocarbon gas, etc. can be appropriately added.

[0280] Further, a gas containing no halogen gas and containing a hydrocarbon gas or hydrogen gas can be used as the etching gas.

[0281] As the hydrocarbon gas, for example, methane (CH ４ ), ethane (C ２ H ６ ), propane (C ３ H ８ ), butane (C ４ H １０ ), ethylene (C ２ H ４ ), propylene (C ３ H ６ ), acetylene (C ２ H２ ), and propine (C ３ H ４ ) one or more of these may be used.

[0282] Furthermore, when using hydrocarbon gases as etching gases, nitrogen gas, helium gas, argon gas, or hydrogen gas can be added as appropriate.

[0283] Furthermore, a capacitively coupled plasma (CCP) etching apparatus with parallel plate electrodes can be used as the dry etching apparatus. The capacitively coupled plasma etching apparatus with parallel plate electrodes can also be configured to apply a high-frequency voltage to one of the parallel plate electrodes. Alternatively, it can be configured to apply multiple different high-frequency voltages to one of the parallel plate electrodes. Alternatively, it can be configured to apply a high-frequency voltage of the same frequency to each of the parallel plate electrodes. Alternatively, it can be configured to apply high-frequency voltages of different frequencies to each of the parallel plate electrodes. Alternatively, a dry etching apparatus with a high-density plasma source can be used. For example, an inductively coupled plasma (ICP) etching apparatus can be used as a dry etching apparatus with a high-density plasma source. The etching apparatus can be appropriately configured according to the object to be etched.

[0284] <Semiconductor layer 11> The band gap of the metal oxide that functions as a semiconductor is preferably 2 eV or more, and more preferably 2.5 eV or more. By using a metal oxide with a large band gap, the off-current of the transistor can be reduced. A transistor having a metal oxide in the channel formation region in this way is called an OS transistor. Because OS transistors have a small off-current, the power consumption of the semiconductor device can be significantly reduced. In addition, because OS transistors have high frequency characteristics, the semiconductor device can be operated at high speed.

[0285] The semiconductor layer 11 preferably contains indium and oxygen. Specifically, for example, it is preferable to use indium oxide as the semiconductor layer 11. In particular, it is preferable to use a single-crystal indium oxide film. It is preferable to use a crystalline film for the semiconductor layer 11, and it is particularly preferable to use indium oxide with a single-crystal structure, but it is also possible to use indium oxide with a polycrystalline or microcrystalline structure. By using indium oxide with a single-crystal structure, carrier scattering at the grain boundaries can be suppressed, and a transistor with high field-effect mobility can be realized. Furthermore, a highly reliable transistor can be realized.

[0286] When using indium oxide with a polycrystalline structure, it is preferable that no grain boundaries are observed, at least in the channel-forming region. This allows indium oxide with a polycrystalline structure to achieve the same effects as indium oxide with a single-crystal structure.

[0287] In this specification, indium oxide having at least a crystalline portion or crystalline region in a film may be referred to as crystalline indium oxide (Crystal IO) or crystalline indium oxide (Crystalline IO). Examples of Crystal IO or Crystalline IO include single-crystal indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0288] In addition, a material having one or more of tin and zinc, and oxygen can be used as the semiconductor layer 11. Alternatively, a material having indium, one or more selected from zinc, titanium, gallium, aluminum, zinc, tin, and tungsten, and oxygen can be used. Furthermore, a material having zinc, one or both of gallium and aluminum, and oxygen can be used. Finally, a material having tin, gallium or aluminum, and oxygen can be used. Specifically, for example, as the semiconductor layer 11, tin oxide, zinc oxide, ITO, In-Zn oxide, In-Ti oxide, indium gallium oxide, indium gallium aluminum oxide, indium gallium tin oxide, indium tungsten oxide, gallium zinc oxide, aluminum zinc oxide, indium aluminum zinc oxide, indium tin zinc oxide, indium titanium zinc oxide, indium gallium zinc oxide, indium gallium tin zinc oxide, indium gallium aluminum zinc oxide, etc. can be used. Alternatively, ITSO, gallium tin oxide, aluminum tin oxide, etc., can also be used. When using these materials, it is preferable that the film has at least crystalline properties, and more preferably that it has a single-crystal structure.

[0289] <Insulating layer 12> Preferably, the insulating layer 12 has the function of capturing and fixing hydrogen. This makes it possible to reduce the hydrogen concentration in the channel formation region of the semiconductor layer 11. This makes it possible to make the channel formation region i-type or substantially i-type.

[0290] Examples of insulators having the function of capturing and fixing hydrogen include metal oxides having an amorphous structure. It is preferable to use a metal oxide such as magnesium oxide, or an oxide containing one or both of aluminum and hafnium, as the insulating layer 12. In such amorphous metal oxides, oxygen atoms have dangling bonds, and these dangling bonds may have the property of capturing or fixing hydrogen. In other words, amorphous metal oxides have a high ability to capture or fix hydrogen.

[0291] Furthermore, it is preferable to use a high-dielectric constant (high-k) material for the insulating layer 12. An example of a high-k material is an oxide containing either or both aluminum and hafnium. By using a high-k material for the insulating layer 12, it becomes possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulating layer. Additionally, it becomes possible to thin the equivalent oxide thickness (EOT) of the insulator functioning as the gate insulating layer.

[0292] It is preferable to use an oxide containing one or both of aluminum and hafnium as the insulating layer 12, more preferable to use an oxide having an amorphous structure that contains one or both of aluminum and hafnium, and even more preferable to use aluminum oxide having an amorphous structure.

[0293] The insulating layer 12 can be made into a laminated structure of two or more layers.

[0294] In the following, the insulating layer 12 is given a three-layer laminated structure, and will be referred to as insulating layer 12_1, insulating layer 12_2, and insulating layer 12_3 in order from the side closest to the semiconductor layer. As an example, Figure 24A shows an example in which, in the configuration shown in Figure 3B, etc., the insulating layer 12 and the conductive layer 13 are provided in order within the opening of the insulating layer 31, and the insulating layer 12 has a laminated structure of insulating layer 12_1, insulating layer 12_2, and insulating layer 12_3.

[0295] The insulating layer 12_2 preferably uses an insulator with a thermally stable structure, such as silicon oxide or silicon oxynitride. Furthermore, the insulating layer 12_2 preferably has a region containing oxygen that is desorbed by heating (hereinafter sometimes referred to as excess oxygen). By providing an insulating layer having a region containing excess oxygen near the semiconductor layer 11, oxygen is supplied to the channel formation region of the semiconductor layer 11, thereby eliminating oxygen deficiencies and V in the channel formation region. Ｏ H can be reduced. Silicon oxide or silicon oxynitride is suitable as an insulator because it easily forms regions containing excess oxygen.

[0296] It is preferable that the thickness of the insulating layer 12_1 be thin. By making the thickness of the insulating layer 12_1 thin, the oxygen contained in the insulating layer 12_2 is supplied to the channel formation region of the semiconductor layer 11, and oxygen deficiencies and V are formed in the channel formation region. Ｏ H can be reduced. The insulating layer 12_1 preferably has a region with a film thickness of 0.1 nm or more and 10 nm or less, preferably has a region with a film thickness of 0.1 nm or more and 5 nm or less, and more preferably has a region with a film thickness of 0.1 nm or more and 3 nm or less.

[0297] Since aluminum oxide and gallium oxide have barrier properties against oxygen, it is preferable that the insulating layer 12_1 having aluminum oxide or gallium oxide be thin. For example, the insulating layer 12_1 having aluminum oxide preferably has a region with a film thickness of 0.5 nm or more and 2.5 nm or less, more preferably has a region with a film thickness of 0.5 nm or more and 2 nm or less, and even more preferably has a region with a film thickness of 0.5 nm or more and 1.5 nm or less. The insulating layer 12_1 having gallium oxide preferably has a region with a film thickness of 0.5 nm or more and 10 nm or less, more preferably has a region with a film thickness of 0.5 nm or more and 5 nm or less, and even more preferably has a region with a film thickness of 0.5 nm or more and 3 nm or less.

[0298] Furthermore, oxygen vacancies and V in the channel formation region of the semiconductor layer 11 Ｏ If H is sufficiently reduced, it is preferable that the insulating layer 12_1 in contact with the channel-forming region has barrier properties against oxygen. This prevents oxygen contained in the channel-forming region from diffusing outward and suppresses the formation of oxygen vacancies in the channel-forming region. The insulating layer 12_1 preferably has a region with a film thickness of 1.5 nm or more and 15 nm or less, preferably has a region with a film thickness of 2 nm or more and 15 nm or less, and more preferably has a region with a film thickness of 3 nm or more and 15 nm or less.

[0299] For example, the insulating layer 12_1 having aluminum oxide preferably has a region with a film thickness of 1.5 nm or more and 10 nm or less, more preferably has a region with a film thickness of 2 nm or more and 10 nm or less, and even more preferably has a region with a film thickness of 3 nm or more and 10 nm or less. The insulating layer 12_1 having gallium oxide preferably has a region with a film thickness of 2 nm or more and 15 nm or less, more preferably has a region with a film thickness of 3 nm or more and 15 nm or less, and even more preferably has a region with a film thickness of 5 nm or more and 15 nm or less.

[0300] The insulating layer 12_3 preferably has barrier properties against oxygen. The insulating layer 12_3 is provided between the channel-forming region of the semiconductor layer 11 and the conductive layer 13, and between the insulating layer 31 and the conductive layer 13. With this configuration, oxygen contained in the channel-forming region of the semiconductor layer 11 can diffuse into the conductive layer 13, suppressing the formation of oxygen vacancies in the channel-forming region of the semiconductor layer 11. In addition, oxygen contained in the semiconductor layer 11 and oxygen contained in the insulating layer 31 can diffuse into the conductive layer 13, suppressing oxidation of the conductive layer 13. The insulating layer 12_3 preferably has lower oxygen permeability than at least the insulating layer 12_2. For example, it is preferable to use a silicon nitride film as the insulating layer 12_3. In this case, the insulating layer 12_3 contains at least nitrogen and silicon.

[0301] Furthermore, it is preferable that the insulating layer 12_3 has barrier properties against hydrogen. This prevents impurities such as hydrogen contained in the conductive layer 13 from diffusing into the semiconductor layer 11.

[0302] Furthermore, as shown in Figure 24B, the insulating layer 12 can also be made into a four-layer laminated structure. In the configuration shown in Figure 24B, in addition to the configuration shown in Figure 24A, an insulating layer 12_4 is provided between insulating layer 12_2 and insulating layer 12_3. In this case, the insulating layer 12_4 can be an insulator that has the function of capturing and fixing hydrogen. For example, an oxide containing one or both of aluminum and hafnium can be used as the insulating layer 12_4. By providing the insulating layer 12_4 between insulating layer 12_3 and insulating layer 12_2, hydrogen contained in the insulating layer 12_2 and the like can be captured and fixed more effectively.

[0303] Hafnium oxide has the function of capturing and fixing oxygen. Therefore, by using hafnium oxide in the insulating layer 12_4, excess oxygen contained in the semiconductor layer 11, the insulating layer 12_2, or near the interface between the semiconductor layer 11 and the insulating layer 12 can be captured and fixed. As a result, a positive shift in the threshold voltage caused by excess oxygen can be suppressed, and a highly reliable semiconductor device can be provided. In addition, oxidation of the conductive layer 13 can be suppressed.

[0304] Aluminum oxide, gallium oxide, and silicon oxide have lower hydrogen barrier properties compared to silicon nitride. Therefore, by using aluminum oxide or gallium oxide for insulating layer 12_1 and silicon oxide for insulating layer 12_2, hydrogen from the semiconductor layer 11 can be captured and fixed to the insulating layer 12_4 via insulating layers 12_1 and 12_2, thereby reducing the hydrogen concentration in the channel formation region of the semiconductor layer 11.

[0305] Furthermore, the above film configuration can also be viewed as a layered structure consisting of a film that can supply oxygen to a film adjacent to the indium oxide film (e.g., a silicon oxide film), a film that can getter hydrogen (e.g., a hafnium oxide film) on its outer periphery, and a film that suppresses the intrusion of oxygen and hydrogen (e.g., a silicon nitride film) on its outer periphery. With this configuration, oxygen deficiencies in the indium oxide film are compensated for by oxygen in the silicon oxide film. Also, hydrogen in the indium oxide film is captured by the hafnium oxide film through heat treatment or other means. In addition, the presence of the silicon nitride film results in a film configuration that minimizes the intrusion of oxygen and hydrogen from the outside. In other words, with the above film configuration, the indium oxide film becomes more i-type. Therefore, transistors having the above-described indium oxide film have high field-effect mobility and high reliability.

[0306] When the insulating layer 12 has a four-layer structure, it is generally preferable that insulating layer 12_1, insulating layer 12_2, insulating layer 12_4, and insulating layer 12_3 be made of aluminum oxide or gallium oxide, silicon oxide, hafnium oxide, and silicon nitride, respectively. Also, generally, the film thicknesses of insulating layer 12_1, insulating layer 12_2, insulating layer 12_4, and insulating layer 12_3 are 1 nm, 2 nm, 2 nm, and 1 nm, respectively. With such a configuration, good electrical characteristics can be maintained even when the transistor is miniaturized or highly integrated.

[0307] <Conductive Layer 13> The conductive layer 13 can, for example, have a two-layer laminated structure. It is preferable to use a conductive material that is resistant to oxidation, such as titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, or ruthenium oxide, or a conductive material that has the function of suppressing oxygen diffusion, as the layer located on the insulating layer 22 side. It is also preferable to use a low-resistance conductive material such as tungsten, copper, or aluminum as the upper layer. Figures 24A and 24B show an example in which the conductive layer 13 has a laminated structure of conductive layer 13_1 and conductive layer 13_2 on conductive layer 13_1.

[0308] <Insulating Layers> For insulating layers of a semiconductor device (insulating layer 21, insulating layer 22, insulating layer 15, insulating layer 12, insulating layer 31, insulating layer 32, insulating layer 29, insulating layer 17, insulating layer 271, insulating layer 241, etc.), it is preferable to use inorganic insulating films. Examples of inorganic insulating films include oxide insulating films, nitride insulating films, oxidative nitride insulating films, and nitride oxide insulating films. Examples of materials applicable to oxide insulating films include silicon oxide, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, cerium oxide, zinc gallium oxide, and hafnium aluminate. Examples of materials applicable to nitride insulating films include silicon nitride and aluminum nitride. Examples of materials applicable to oxidative nitride insulating films include silicon oxidative nitride films, aluminum oxidative nitride films, gallium oxidative nitride films, yttrium oxidative nitride films, and hafnium oxidative nitride films. Examples of materials applicable to nitride oxide insulating films include silicon nitride films and aluminum nitride films. Furthermore, organic insulating films can also be used for the insulating layer of semiconductor devices.

[0309] Examples of materials with a high dielectric constant include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium-zirconium oxide, oxides containing aluminum and hafnium, oxides containing aluminum and hafnium, oxides containing silicon and hafnium, oxides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0310] Examples of materials with low dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxide nitride, and silicon oxide nitride, as well as resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin. Other inorganic insulating materials with low dielectric constant include, for example, silicon oxide containing fluorine, silicon oxide containing carbon, and silicon oxide containing carbon and nitrogen. Also, for example, silicon oxide having vacancies can be used. These silicon oxides may also contain nitrogen.

[0311] Furthermore, a ferroelectric material can be used for the insulating layer of a semiconductor device. Examples of ferroelectric materials include metal oxides such as hafnium oxide, zirconium oxide, and hafnium-zirconium oxide. Another example of a ferroelectric material is a material obtained by adding element J1 (where element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to hafnium oxide. Here, the ratio of the number of hafnium atoms to the number of element J1 atoms can be set as appropriate. It is preferable that the ratio of the number of hafnium atoms to the number of element J1 atoms be 1:1 or close to it. Another example of a ferroelectric material is a material obtained by adding element J2 (where element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to zirconium oxide. Furthermore, the ratio of the number of zirconium atoms to the number of element J2 atoms can be set as appropriate; for example, a ratio of 1:1 or a value close to it is preferred. Also, as a material that can have ferroelectric properties, lead titanate (PbTiO) Ｘ Piezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), and barium titanate, can also be used.

[0312] Furthermore, metal nitrides containing element M1, element M2, and nitrogen can be cited as materials that may possess ferroelectric properties. Here, element M1 is one or more selected from aluminum, gallium, indium, etc. Element M2 is one or more selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. The ratio of the number of atoms of element M1 to the number of atoms of element M2 can be set as appropriate. Also, metal oxides containing element M1 and nitrogen may possess ferroelectric properties even without containing element M2. Furthermore, materials in which element M3 is added to the above-mentioned metal nitrides can be cited as materials that may possess ferroelectric properties. Element M3 is one or more selected from magnesium, calcium, strontium, zinc, cadmium, etc. Here, the ratio of the number of atoms of element M1, the number of atoms of element M2, and the number of atoms of element M3 can be set as appropriate.

[0313] Furthermore, SrTaO is an example of a material that may possess ferroelectric properties. ２ N, BaTaO ２ Perovskite-type oxynitrides such as N, and GaFeO with a κ-alumina structure. ３ These are some examples.

[0314] While the above explanation uses metal oxides and metal nitrides as examples, it is not limited to these. For example, metal oxynitrides obtained by adding nitrogen to the aforementioned metal oxides, or metal nitrogen oxides obtained by adding oxygen to the aforementioned metal nitrides, can also be used.

[0315] Furthermore, as materials that may possess ferroelectricity, for example, a mixture or compound consisting of multiple materials selected from the materials listed above can be used. Incidentally, since the crystal structure (properties) of the materials listed above may change not only depending on the film deposition conditions but also on various processes, in this specification, materials that exhibit ferroelectricity are not only called ferroelectrics, but also materials that may possess ferroelectricity.

[0316] Metal oxides containing either or both hafnium and zirconium can exhibit ferroelectric properties even in thin films of a few nanometers. Furthermore, metal oxides containing either or both hafnium and zirconium can exhibit ferroelectric properties even in minute areas. Therefore, the miniaturization of semiconductor devices can be achieved by using metal oxides containing either or both hafnium and zirconium.

[0317] In this specification, a layered structure of a material capable of ferroelectricity may be referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. Furthermore, a device having such a ferroelectric layer, metal oxide film, or metal nitride film may be referred to as a ferroelectric device in this specification.

[0318] Ferroelectricity is believed to manifest when oxygen or nitrogen in the crystals contained in the ferroelectric layer is displaced by an external electric field. Furthermore, the manifestation of ferroelectricity is presumed to depend on the crystal structure of the crystals contained in the ferroelectric layer. Therefore, for an insulating layer to exhibit ferroelectricity, it must contain crystals. In particular, it is preferable for the insulating layer to contain crystals having an orthorhombic crystal structure, as this is desirable for ferroelectricity to manifest. Examples of crystal structures for the crystals contained in the insulating layer include one or more selected from tetragonal, orthorhombic, monoclinic, and hexagonal systems. The insulating layer can also have an amorphous structure. In this case, the insulating layer can also have a composite structure having both an amorphous structure and a crystalline structure.

[0319] Furthermore, by adding a Group 3 element from the periodic table to an oxide containing one or both hafnium and zirconium, the oxygen vacancy concentration in the oxide increases, making it easier to form crystals with an orthorhombic crystal structure. This is preferable because it increases the proportion of crystals with an orthorhombic crystal structure and enhances remanent polarization. On the other hand, if too much Group 3 element is added, the crystallinity of the oxide may decrease, making it difficult to exhibit ferroelectric properties. Therefore, the content of Group 3 elements in an oxide containing one or both hafnium and zirconium is preferably 0.1 atomic% to 10 atomic%, more preferably 0.1 atomic% to 5 atomic%, and even more preferably 0.1 atomic% to 3 atomic%. Here, the content of Group 3 elements refers to the ratio of the number of Group 3 elements to the sum of the number of atoms of all metal elements contained in the layer. The Group 3 element is preferably one or more selected from scandium, lanthanum, and yttrium, and more preferably one or both of lanthanum and yttrium.

[0320] Furthermore, the electrical properties of a transistor using a metal oxide can be stabilized by surrounding it with an insulating layer that has the function of suppressing the permeation of impurities and oxygen. As an insulating layer that has the function of suppressing the permeation of impurities and oxygen, for example, an insulating layer containing one or more selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum can be used in a single layer or a multilayer configuration.

[0321] Specifically, materials that can function as an insulating layer to suppress the permeation of impurities and oxygen include oxides such as aluminum oxide, gallium oxide, magnesium oxide, hafnium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, and tantalum oxide; nitrides such as silicon nitride and aluminum nitride; and nitride oxides such as silicon nitride.

[0322] More specifically, materials that can function as an insulating layer to suppress the permeation of impurities such as water and hydrogen, and oxygen, include nitrides such as silicon nitride, aluminum nitride, titanium aluminum nitride, and titanium nitride, and nitride oxides such as silicon nitride. Other examples include metal oxides such as aluminum oxide, tantalum oxide, gallium oxide, magnesium oxide, hafnium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, and oxides containing aluminum and hafnium (hafnium aluminate).

[0323] Furthermore, an insulating layer having a region containing oxygen that is desorbed by heating (hereinafter sometimes referred to as excess oxygen) can be used as an insulating layer in contact with the oxide semiconductor layer or an insulating layer provided in the vicinity of the oxide semiconductor layer. For example, by having an insulating layer having a region containing excess oxygen in contact with the oxide semiconductor layer or located in the vicinity of the oxide semiconductor layer, the oxygen vacancies in the oxide semiconductor layer can be reduced. Examples of insulating layer materials that easily form regions containing excess oxygen include silicon oxide, silicon oxynitride, or silicon oxide having vacancies.

[0324] It is preferable to use a hydrogen barrier insulating layer for the insulating layer in contact with the oxide semiconductor layer, or an insulating layer provided near the oxide semiconductor layer. The hydrogen barrier properties of this insulating layer suppress the diffusion of hydrogen into the oxide semiconductor layer.

[0325] Examples of materials that can function as an insulating layer for capturing or fixing hydrogen include metal oxides such as hafnium oxides, magnesium oxides, aluminum oxides, aluminum and hafnium oxides (hafnium aluminate), and hafnium and silicon oxides (hafnium silicate). These metal oxides may also contain zirconium, for example, hafnium and zirconium oxides.

[0326] An insulating layer having the function of capturing or fixing hydrogen preferably has an amorphous structure. In metal oxides having an amorphous structure, some oxygen atoms have dangling bonds, thus having a high ability to capture or fix hydrogen. Therefore, by having an amorphous structure in the insulating layer, the function of capturing or fixing hydrogen can be enhanced. For example, an amorphous structure can be realized by adding silicon to the above metal oxide. For example, it is preferable to use an oxide containing hafnium and silicon (hafnium silicate).

[0327] By making the insulating layer amorphous, the formation of grain boundaries can be suppressed. Suppressing the formation of grain boundaries improves the flatness of the insulating layer. This makes the thickness distribution of the insulating layer more uniform, reducing areas with extremely thin thickness, and thus improving the dielectric strength of the insulating layer. Furthermore, the thickness distribution of the film provided on the insulating layer can be made more uniform. In addition, by suppressing the formation of grain boundaries in the insulating layer, leakage current caused by defect levels at the grain boundaries can be reduced. Therefore, the insulating layer can function as an insulating film with low leakage current.

[0328] Furthermore, the above insulating layer may have, in part, a crystalline region and / or a grain boundary.

[0329] Furthermore, the function of capturing or fixing a corresponding substance can also be described as the property of making the corresponding substance difficult to diffuse. Therefore, an insulating layer that has the function of capturing or fixing a corresponding substance may function as an insulating layer with barrier properties.

[0330] In this specification, the term "barrier insulating layer" refers to an insulating layer that possesses barrier properties. Furthermore, "barrier property" refers to the property of making it difficult for the corresponding substance to diffuse (also referred to as the property of making it difficult for the corresponding substance to permeate, the property of having low permeability to the corresponding substance, or the function of suppressing the diffusion of the corresponding substance). When hydrogen is described as a corresponding substance, it refers to, for example, a hydrogen atom, a hydrogen molecule, and water molecules and OH groups. −This refers to at least one substance that is bonded with hydrogen, such as [substance name]. Furthermore, when an impurity is listed as a corresponding substance, unless otherwise specified, it refers to an impurity in the channel-forming region or semiconductor layer, such as a hydrogen atom, hydrogen molecule, water molecule, nitrogen atom, nitrogen molecule, nitrogen oxide molecule (N ２ O, NO, NO ２ It refers to at least one substance, such as a copper atom. Furthermore, when oxygen is listed as a corresponding substance, it refers to at least one substance, such as an oxygen atom or an oxygen molecule.

[0331] Materials that can function as a barrier insulating layer against hydrogen include silicon nitride, silicon oxide nitride, aluminum oxide, tantalum oxide, gallium oxide, magnesium oxide, hafnium oxide, and the like.

[0332] Materials that can function as a barrier insulating layer against oxygen include oxides containing one or both aluminum and hafnium. Examples of oxides containing one or both aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate). Another example of a material for a barrier insulating layer against oxygen is magnesium oxide. Another example of a material for a barrier insulating layer against oxygen is oxides containing gallium. Examples of oxides containing gallium include gallium oxide and zinc gallium oxide. Another example of a material for a barrier insulating layer against oxygen is silicon nitride and silicon nitride oxide.

[0333] Organic materials can also be used as the insulating layer. Examples of organic materials that can be used include acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimidoamide resin, silicone resin, siloxane resin, benzocyclobutene resin, phenolic resin, or precursors of these resins. In addition, organic materials such as polyvinyl alcohol (PVA), polyvinyl butyral (PVB), polyvinylpyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, or alcohol-soluble polyamide resins can also be used.

[0334] Furthermore, as an organic material, for example, a photosensitive resin can be used. Examples of photosensitive resins include photosensitive resin compositions containing acrylic resins. Another example is a photoresist.

[0335] Furthermore, the photosensitive resin can be selected and used from a suitable material among positive-type and negative-type materials.

[0336] In this specification and other documents, the term "acrylic resin" may refer not only to polymethacrylate esters or methacrylic resins, but also to acrylic polymers in a broad sense.

[0337] <Conductive Layers> It is preferable to use a metal element selected from tungsten, copper, aluminum, chromium, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy composed of the aforementioned metal elements, or an alloy combining the aforementioned metal elements. It is also possible to use nitrides of alloys composed of the aforementioned metal elements, or oxides of such alloys. For example, it is preferable to use tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements like phosphorus, and silicides such as nickel silicide can also be used.

[0338] Furthermore, conductive materials containing nitrogen, such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum; conductive materials containing oxygen, such as oxides containing ruthenium oxide, strontium and ruthenium, or oxides containing lanthanum and nickel; and materials containing metallic elements such as titanium, tantalum, or ruthenium are preferred because they are conductive materials that are resistant to oxidation, conductive materials that have the function of suppressing oxygen diffusion, or materials that maintain conductivity even when absorbing oxygen. Examples of conductive materials containing oxygen include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, indium tin oxide containing titanium oxide, ITSO, indium zinc oxide, and indium zinc oxide containing tungsten oxide. In this specification, conductive films formed using conductive materials containing oxygen are sometimes referred to as oxide conductive films.

[0339] Conductive materials mainly composed of tungsten, copper, or aluminum are preferred because they have high conductivity.

[0340] Furthermore, multiple conductive layers formed from the above materials can be used in a laminated structure. For example, a laminated structure can be used that combines the aforementioned metal element material with an oxygen-containing conductive material. Alternatively, a laminated structure can be used that combines the aforementioned metal element material with a nitrogen-containing conductive material. Furthermore, a laminated structure can be used that combines the aforementioned metal element material with an oxygen-containing conductive material and a nitrogen-containing conductive material.

[0341] <Substrates> For example, insulating substrates, semiconductor substrates, or conductive substrates can be used as substrates for forming transistors. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, there are semiconductor substrates having insulating regions within the aforementioned semiconductor substrates, such as SOI (Silicon On Insulator) substrates. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, or conductive resin substrates. Alternatively, there are substrates having metal nitrides or metal oxides. Furthermore, there are substrates on which a conductor or semiconductor is provided on an insulating substrate, substrates on which a conductor or insulator is provided on a semiconductor substrate, and substrates on which a semiconductor or insulator is provided on a conductive substrate. Alternatively, substrates with elements mounted on them can be used. Elements mounted on the substrate include capacitive elements, resistive elements, switch elements, light-emitting elements, or memory elements.

[0342] The above describes the materials that can be used in the semiconductor device of this embodiment.

[0343] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0344] (Embodiment 2) This embodiment describes an indium oxide film that can be used in the semiconductor layer of a transistor according to one aspect of the present invention.

[0345] In this specification, indium oxide having at least a crystalline portion or crystalline region in the film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystal IO or crystalline IO include single-crystal indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0346] Indium oxide is a semiconductor material with completely different physical properties from oxide semiconductors such as In-Ga-Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0347] The carrier concentration dependence of the hole (Hall) mobility of indium oxide, silicon, and IGZO is described. Figure 33A shows silicon (Si) and indium oxide (InO Ｘ Figure 33B is a schematic diagram of the carrier concentration dependence of hole mobility with respect to IGZO.

[0348] First, as indicated by the arrows in Figure 33B, IGZO tends to exhibit higher hole mobility as the carrier concentration increases. On the other hand, as indicated by the arrows in Figure 33A, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases (see Non-Patent Literature 3). This trend is similar to that of silicon, where the lower the concentration of dopants (impurities) in the material, the less impurity scattering occurs and the higher the hole mobility. In other words, the higher the purity and intrinsic nature of indium oxide, the higher its hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to silicon. Note that the properties of indium oxide shown in Figure 33A are assumed to be those of a single crystal. Therefore, when indium oxide is not a single crystal (for example, polycrystalline), the properties may differ from those shown in Figure 33A.

[0349] In Figure 33A, the low carrier concentration range R1 exhibits extremely high hole mobility, making it a suitable carrier concentration range for, for example, the channel formation region of a transistor. For example, in the case of indium oxide, the carrier concentration range R1 is 1 × 10⁻⁶. １５ cm −３ This range includes, for example, 1 × 10 １４ cm −３ The above is 1 x 10 １８ cm −３ The range is as follows: By sufficiently reducing the carrier concentration, the hole mobility value can be increased to 270 cm⁻¹. ２ It can be expected to be raised to the level of / (V・s).

[0350] Furthermore, in indium oxide, the region where the carrier concentration is in the range R1 may contain elements that lower the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Other elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0351] On the other hand, the range R2 with high carrier concentration has low electrical resistance and can be said to be a suitable range of carrier concentration for applications such as the source and drain regions of a transistor, or resistors, or transparent conductive films. Range R2 is when the carrier concentration value is 1 × 10⁻⁶ ２０ cm −３ This range includes, for example, 1 × 10 １９ cm −３ The above is 1 x 10 ２２ cm −３ The range is as follows: By making the carrier concentration sufficiently high, the resistivity can be increased to 1 × 10⁻⁶. −４ It is expected that the level can be reduced to below Ω·cm.

[0352] In the case of indium oxide, the region where the carrier concentration is in the range R2 may contain elements that increase the carrier concentration. For example, it is preferable to include elements common to the source and drain electrodes of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use elements whose oxides are conductive or semiconducting. As for the supply method of elements that increase the carrier concentration, a method of forming a film containing the element and diffusing it, ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment can be used. In this specification, unless otherwise specified, the presence or absence of mass separation is not limited. For example, in this specification, a method of supplying ions by mass separation is called ion implantation, and a method of supplying ions without mass separation is called ion doping.

[0353] In this way, indium oxide uses regions with low carrier concentrations for the transistor's channel formation region and regions with high carrier concentrations for the transistor's source and drain regions. In other words, indium oxide can be said to be an oxide in which valence electron control is possible. In contrast, with IGZO, strain may be formed in the source and drain regions due to stress on the electrodes in contact with IGZO, and an n-type region may be formed. On the other hand, unlike IGZO, indium oxide allows for valence electron control, so it does not require the formation of strain in the film as in IGZO. Less strain in the film is expected to improve reliability. For example, by creating regions with carrier concentrations in the range R1 and range R2 shown in Figure 33A within the indium oxide film, a so-called n-i-n junction (a junction of an n-type region, an i-type region, and an n-type region) can be created. Valence electron control in silicon transistors is generally known. On the other hand, valence electron control in indium oxide transistors is a novel technological concept that would not normally be conceived.

[0354] By applying the above technical concept, the indium oxide transistor described herein has two or more, preferably three or more, more preferably four or more, and most preferably five of the following features (1) to (5): (1) High on-current (in other words, high mobility). (2) Low off-current. (3) Normally off is possible. (4) High reliability. (5) High cutoff frequency (fT). For example, the indium oxide transistor described herein has high mobility, low off-current, and is normally off. This transistor is different from a transistor that is high mobility and normally on.

[0355] In addition, the i-type nature of a semiconductor means that the Fermi level (Ef) and the intrinsic Fermi level (Ei) are the same (Ef = Ei). As shown in Figure 33B, in IGZO, the lower the carrier concentration, the lower the hole mobility. Therefore, when Ef = Ei is reached, there are no carriers left (in other words, the material has properties similar to an insulator), and it may cease to function as a transistor. On the other hand, in indium oxide, as shown in Figure 33A, the lower the carrier concentration, the higher the hole mobility, and when Ef = Ei is reached, the hole mobility is maximized. That is, transistors containing indium oxide can achieve high field-effect mobility by setting Ef = Ei. Furthermore, because transistors containing indium oxide have a low carrier concentration, they tend to be normally off. Therefore, transistors containing indium oxide can be normally off and achieve high field-effect mobility.

[0356] Note that "normally-off" refers to a state where no current flows through the transistor when no potential is applied to the gate or when the gate-source voltage is 0 V. Also, "normally-off" can be evaluated by the threshold voltage (Vth) or the shift value (Vsh) of the transistor. Unless otherwise specified, Vth shall be calculated by the constant current method. More specifically, Vth is the gate voltage (Vg) when the value of drain current (Id) × channel length (L) ÷ channel width (W) in the Id-Vg characteristics of the transistor becomes 1 nA (1×10 −９ A). Also, Vsh is the gate voltage (Vg) at the intersection of the tangent line with the maximum slope when the drain current (Id) in the Id-Vg characteristics of the transistor is expressed in logarithmic notation and the line of Id = 1 pA (1×10 −１２ A), or the Vg at the intersection of the line extrapolated from between two points where the slope becomes maximum when Id in the Id-Vg characteristics of the transistor is expressed in logarithmic notation and the line of Id = 1 pA. For example, if either one or both of Vth and Vsh are zero or positive values, it can be regarded as a normally-off transistor.

[0357] Also, in a transistor having indium oxide, in order to make the semiconductor i-type, that is, to realize Ef = Ei, the film structure in contact with the indium oxide film is important. For example, in a transistor having indium oxide, a film structure in which a silicon oxide film, a hafnium oxide film, and a silicon nitride film in contact with the indium oxide film are laminated can be cited. By adopting such a film structure, Ef = Ei can be achieved, and a highly reliable semiconductor device can be obtained.

[0358] In the above film structure, instead of the silicon oxide film, an oxygen-containing film such as a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, or a gallium oxide film can also be used. Also, in the above film structure, instead of the silicon nitride film, a silicon nitride oxide film, a silicon oxynitride film, etc. can also be used. Also, the hafnium oxide film located closer to the indium oxide film than the silicon nitride film functions as a hydrogen gettering site.

[0359] Furthermore, the above film configuration can also be viewed as a layered structure consisting of a film that can supply oxygen to the indium oxide film (e.g., a silicon oxide film), a film that can getter hydrogen (e.g., a hafnium oxide film), and a film that suppresses the intrusion of oxygen and hydrogen (e.g., a silicon nitride film). With this configuration, oxygen deficiencies in the indium oxide film are compensated for by oxygen in the silicon oxide film. Also, hydrogen in the indium oxide film is captured by the hafnium oxide film through heat treatment or other means. In addition, the silicon nitride film provides a film configuration that minimizes the intrusion of oxygen and hydrogen from the outside. In other words, by using the above film configuration, the indium oxide film can be made closer to type i. Therefore, transistors having the above-described indium oxide film have high field-effect mobility and high reliability.

[0360] Next, we will describe indium oxide films applied to transistors. Indium oxide films are preferably crystalline (i.e., they have crystal grains). Examples of films with crystal grains include single-crystal films, polycrystalline films, or amorphous films containing crystal grains (also called microcrystalline films). In particular, polycrystalline films are preferred for indium oxide films, and single-crystal films are more preferred. Single-crystal films do not have crystal grain boundaries. Impurities that inhibit carrier flow (typically insulating impurities, insulating oxides, etc.) tend to segregate at crystal grain boundaries. By using single-crystal films, carrier scattering at crystal grain boundaries can be suppressed, enabling the realization of transistors exhibiting high field-effect mobility. Furthermore, it has the excellent effect of suppressing variations in transistor characteristics caused by these crystal grain boundaries.

[0361] In addition, a polycrystalline film is preferable because it can reduce carrier scattering and exhibits high field-effect mobility as compared with a microcrystalline film or an amorphous film. When using a polycrystalline film, it is preferable to use a film in which the size of crystal grains is as large as possible and the grain boundaries are few. In a transistor to which a polycrystalline film of indium oxide is applied, when there are no grain boundaries in the channel formation region or no grain boundaries are observed, since the channel formation region is located within the single-crystal region included in the polycrystalline film, it can be regarded as a transistor to which single-crystal indium oxide is applied.

[0362] The crystallinity of indium oxide can be analyzed by, for example, X-ray diffraction (XRD: X-Ray Diffraction), transmission electron microscopy (TEM: Transmission Electron Microscope), or electron diffraction (ED: Electron Diffraction). Or, these may be combined in plurality for analysis.

[0363] In this specification and the like, a semiconductor layer in which no grain boundaries are observed in the channel formation region, a semiconductor layer in which the channel formation region is included in one crystal grain, or a semiconductor layer in which the directions of crystal axes are the same in at least two regions within the channel formation region can be called a single-crystal film. Also, in the channel formation region, a semiconductor layer in which, within one crystal grain, with a certain crystal axis or a certain crystal orientation as the axis of rotation, the directions of other crystal axes continuously change can be called a single-crystal film.

[0364] The channel formation region refers to a region of the semiconductor layer that overlaps (or faces) the gate electrode through the gate insulating layer and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, crystal grains, grain boundaries, crystal axes, crystal orientations, etc. in the channel formation region can be confirmed by cross-sectional observation including the semiconductor layer, the source electrode, and the drain electrode.

[0365] The indium oxide film in the channel-forming region is preferable to have a low impurity concentration. Impurities in the indium oxide film in the channel-forming region can act as a scattering source for carriers, and thus can cause a decrease in field-effect mobility. Furthermore, these impurities can also inhibit crystal growth in the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The concentration of these impurities in the indium oxide film is preferably 0.1% or less, and more preferably 0.01% (100 ppm) or less. Note that elements such as carbon and hydrogen may be present in the deposition gas or precursor during film formation, and may remain in the indium oxide film in higher concentrations than the impurities mentioned above.

[0366] Furthermore, the indium oxide film in the channel-forming region may contain elements that can become trivalent cations like indium, as long as their crystals maintain a cubic crystal structure (Bixbite type). Examples include Group 13 elements of the periodic table such as gallium and aluminum, and Group 3 elements of the periodic table. Since these elements mainly exist as trivalent cations in the oxide, the carrier concentration of indium oxide can be kept low.

[0367] Furthermore, the indium oxide film described herein has a high film density. Here, an indium oxide film applicable to one aspect of the present invention (here, In ２ O ３ The membrane density of ) is shown in Table 1.

[0368]

[0369] As shown in Table 1, the film density of the indium oxide film was evaluated at six levels, Sample 1 to Sample 6. In Table 1, Condition 1 is the substrate condition for the indium oxide film, where Sample 1 to Sample 3 are glass, Sample 4 is a SiOx film formed by sputtering, and Sample 5 and Sample 6 are yttria-stabilized zirconia (YSZ). Condition 2 is the film deposition condition for the indium oxide film, where Sample 1 to Sample 3 are deposited by sputtering (SP), and Sample 4 to Sample 6 are deposited by ALD. Furthermore, condition 3 is the heat treatment condition after indium oxide film deposition. Sample 1, Sample 4, and Sample 5 are without heat treatment (as-depo), Sample 2 is baked at 350°C in a CDA atmosphere, Sample 3 is baked at 650°C in a CDA atmosphere, and Sample 6 is baked at 250°C in a vacuum atmosphere.

[0370] In Table 1, CDA stands for Clean Dry Air. It is preferable that the hydrogen and water content in the atmosphere during the heat treatment after indium oxide film formation (corresponding to condition 3) be kept to a minimum. It is preferable to use a high-purity gas with a dew point of -60°C or lower, preferably -100°C or lower, as this atmosphere.

[0371] As shown in Table 1, the indium oxide film tends to have a higher film density when heat-treated compared to when it is not heat-treated (Sample 1, Sample 4, or Sample 5). This is because the heat treatment causes impurity elements (e.g., carbon, nitrogen, hydrogen, argon, etc.) to be removed from the film, resulting in a higher purity in the indium oxide film. Furthermore, as shown in Sample 5 and Sample 6, the indium oxide film on YSZ has a film density of 7.00 g / cm³. ３ It exceeds [value]. The theoretical value of the film density of the indium oxide film is 7.18 g / cm³. ３ In this specification, the range of film density for indium oxide films is 6.70 g / cm³. ３ 7.18g / cm or more ３ The following is preferred, preferably 6.90 g / cm³３ 7.18g / cm or more ３ The following, and more preferably 7.00 g / cm³ ３ 7.18g / cm or more ３ The following applies:

[0372] Furthermore, film density can be evaluated using methods such as Rutherford backscattering (RBS) or X-ray reflectivity (XRR). Differences in film density can sometimes be evaluated using transmission electron microscopy (TEM) images of the cross-section. In TEM observation, a high film density results in a darker (more intense) transmission electron (TE) image, while a low film density results in a fainter (brighter) transmission electron (TE) image.

[0373] By using such an indium oxide film in a transistor, the field-effect mobility of the transistor can be increased to 50 cm². ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ It can be set to (V・s) or more.

[0374] One of the characteristics of indium oxide films is that they have higher oxygen permeability (diffusivity) compared to IGZO films. As shown in Figure 33C, indium oxide films (InO Ｘ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and oxygen molecules (O) ２ It is released as water molecules (H) by reacting with hydrogen contained in the membrane. ２ It may also be released as O. Furthermore, oxygen deficiencies (V) can form in the membrane. Ｏ If oxygen atoms are present, diffusing oxygen atoms will fill the oxygen deficiency. Indium oxide films allow oxygen to diffuse easily, so they can be said to fill oxygen deficiencies more easily than IGZO films.

[0375] Thus, because indium oxide films are more likely to reduce oxygen vacancies in the film compared to IGZO films, applying such indium oxide films to transistors makes it possible to realize transistors with extremely high reliability.

[0376] Furthermore, as shown in Figure 33C, the indium oxide film diffuses hydrogen. Hydrogen diffusing into the indium oxide film from the outside permeates the film and forms hydrogen molecules (H ２ It is released as ) or by reacting with oxygen contained in the film, and released as water molecules. The above-mentioned oxygen and hydrogen diffuse through the indium oxide film by heat treatment. The temperature of the heat treatment is 200°C to 700°C, preferably 350°C to 650°C, and more preferably 400°C to 500°C.

[0377] Transistors using indium oxide films are storage-type transistors that use electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, in a transistor, the on-current or field-effect mobility of the transistor can be increased.

[0378] Table 2 shows single crystal indium oxide (here, In ２ O ３ The effective masses of indium oxide and single-crystal silicon (Si) are shown below. As shown in Table 2, indium oxide is characterized by a small effective electron mass and a large effective hole mass. Furthermore, the effective electron mass of indium oxide is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in transistors, transistors with high field-effect mobility and high frequency characteristics (also called f-characteristics) can be realized. In addition, because the effective hole mass is large, transistors with extremely low off-currents can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width is 1 fA (1 × 10⁻¹⁶) in an environment of 125°C. −１５ A) Less than or equal to, or 1aA (1 × 10 −１８ A) Less than or equal to 1aA (1 × 10) in a room temperature (25°C) environment. −１８ A) Less than or equal to, or 1zA (1 × 10⁻¹⁰ −２１A) The following is possible. Furthermore, as shown in Table 2, indium oxide has a smaller effective electron mass and a larger effective hole mass than silicon, so it may be possible to realize a transistor with higher field-effect mobility and lower off-current than a Si transistor.

[0379]

[0380] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. It is preferable to use a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with the indium oxide for the seed layer. This improves the crystallinity of the indium oxide film. A substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0381] One method for evaluating the degree of lattice mismatch is to use the following lattice mismatch value. The lattice mismatch Δa [%] of the crystals in the formed film (in this case, the indium oxide film) relative to the crystals in the seed layer is given by Δa = ((L １ -L ２ ) / L ２ It is calculated as ) × 100. Here L １ L is the length of the unit cell vector of the crystals in the formed film, or the lattice constant. ２ is the length of the unit cell vector of the crystal in the seed layer, or the lattice constant.

[0382] The lattice mismatch Δa between the seed layer and the indium oxide film is preferably small in absolute value, and most preferably zero. For example, Δa can be -5% or more and 5% or less, preferably -4% or more and 4% or less, more preferably -3% or more and 3% or less, and even more preferably -2% or more and 2% or less.

[0383] Here, the indium oxide crystal has a cubic structure (bixbite type). For example, yttria-stabilized zirconia (YSZ) crystals can have a cubic structure (fluorite type). The lattice mismatch of the indium oxide crystal with respect to the cubic YSZ crystal is in the range of -2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on a YSZ substrate.

[0384] Furthermore, the crystal structure of the seed layer and the crystal structure of the indium oxide film do not necessarily have to be the same in terms of crystal system or crystal orientation. For example, a film with a hexagonal or trigonal crystal structure can be used beneath an indium oxide film with a cubic crystal structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to crystal orientation necessary for epitaxial growth can be met. Examples of hexagonal or trigonal crystals include wurtzite-type structures and YbFe. ２ O ４ Type structure, Yb ２ Fe ３ O ７ These include type structures and their modified type structures. YbFe ２ O ４ Type structure or Yb ２ Fe ３ O ７ An example of a crystal with a crystalline structure is IGZO. Indium oxide single crystal films can be formed not only on YSZ substrates but also on insulating films. On the other hand, it is difficult to form silicon single crystal films on insulating films. Silicon crystals have a diamond structure. Thus, in terms of single crystals, indium oxide and silicon have similar properties. However, when comparing indium oxide and silicon from the perspective of whether single crystals can be formed on insulating films, they have different properties.

[0385] Here, we compare transistors with crystalline indium oxide films, transistors with IGZO (In, Ga, Zn compound oxide) films, and transistors with silicon (Si) films. This comparison is shown in Table 3.

[0386]

[0387] In Table 3, transistors with a crystalline indium oxide film are explicitly labeled as "Crystal IO (LSI)" for LSI applications. Hereafter, they may simply be referred to as "Crystal IO". Transistors with a Si film are explicitly labeled as "Si (LSI)" for LSI applications. Hereafter, they may simply be referred to as "Si". Transistors with an IGZO film are explicitly labeled as "IGZO (Display)" for Display applications. Hereafter, they may simply be referred to as "IGZO". In Table 3, ◎ represents +2 points, ○ represents +1 point, △ represents 0 points, and × represents -1 point. Total is the sum of the points for ◎, ○, △, and × shown in Table 3. A higher point value indicates better performance than a lower point value.

[0388] In Table 3, the first comparison item is minimal off-current, in which crystalline IO and IGZO are superior to Si. The second comparison item is on-current (Ion) characteristics, in which Si, crystalline IO, and IGZO have the highest characteristics. The third comparison item is reliability, in which crystalline IO and Si are superior to IGZO. The fourth comparison item is channel length miniaturization, in which crystalline IO and IGZO are superior to Si. In the channel length miniaturization item, VFET represents a vertical transistor, UFET represents a U-shaped transistor, and 3D structure represents a three-dimensional structure. The fifth comparison item is cutoff frequency, in which crystalline IO and Si are superior to IGZO. The sixth comparison item is improved integration density, in which Si is superior to crystalline IO and IGZO. Furthermore, the seventh comparison item is threshold voltage controllability (Vth controllability), in which Si is superior to crystalline IO and IGZO. The eighth comparison item is radiation resistance, in which crystalline IO and IGZO are superior to Si. The ninth comparison item is 3D (multi-stage) integrated structure, in which crystalline IO and IGZO are superior to Si. The tenth comparison item is the potential for self-heating, in which crystalline IO and IGZO are superior to Si.

[0389] As shown in Table 3, as the Total score, crystalline IO (LSI) is 8 points, and Si (LSI) and IGZO (Display) are each 4 points. Thus, the semiconductor device of one aspect of the present invention, particularly the semiconductor device having a crystalline indium oxide film, may replace the semiconductor device using Si.

[0390] This embodiment can be implemented in appropriate combination with at least a part thereof and other embodiments described in this specification.

[0391] (Embodiment 3) In this embodiment, a memory device of one aspect of the present invention will be described with reference to FIGS. 34 to 37. In this embodiment, a configuration example of a memory device in which a layer having memory cells is laminated on a layer provided with a drive circuit including a sense amplifier will be described.

[0392] A transistor included in the memory cell exemplified below can be applied to the transistor in which a channel is formed in a single crystal oxide semiconductor exemplified in Embodiment 2 (referred to as an OS transistor).

[0393] <Configuration Example of Memory Device> FIG. 34 shows a block diagram showing a configuration example of a memory device 480 according to one aspect of the present invention. The memory device 480 shown in FIG. 34 has a layer 420 and a laminated layer 470.

[0394] The layer 420 is a layer having Si transistors. In the layer 470, element layers 430[1] to 430[m] (m is an integer of 2 or more) are laminated and provided. The element layers 430[1] to 430[m] are layers having OS transistors. The layer 470 in which the layers having OS transistors are laminated can be laminated on the layer 420.

[0395] Elements such as the OS transistors and capacitor elements included in the element layers 430[1] to 430[m] constitute memory cells. FIG. 34 shows an example in which a plurality of memory cells 432 are arranged in a matrix of m rows and n columns (n is an integer of 2 or more) in the element layers 430[1] to 430[m].

[0396] In Figure 34, the memory cell 432 in the first row and first column is shown as memory cell 432[1,1], and the memory cell 432 in the mth row and nth column is shown as memory cell 432[m,n]. In this embodiment, an arbitrary row may be referred to as row i, and an arbitrary column may be referred to as column j. Therefore, i is an integer between 1 and m, and j is an integer between 1 and n. In this embodiment, the memory cell 432 in the ith row and jth column is shown as memory cell 432[i,j]. In this embodiment, when "i + α" (where α is a positive or negative integer) is used, "i + α" is not less than 1 and not greater than m. Similarly, when "j + α" is used, "j + α" is not less than 1 and not greater than n.

[0397] Figure 34 also illustrates, as an example, m wirings WL extending in the row direction, m wirings PL extending in the row direction, and n wirings BL extending in the column direction. In this embodiment, the first wiring WL (first row) is denoted as wiring WL[1], and the mth wiring WL (mth row) is denoted as wiring WL[m]. Similarly, the first wiring PL (first row) is denoted as wiring PL[1], and the mth wiring PL (mth row) is denoted as wiring PL[m]. Similarly, the first wiring BL (first column) is denoted as wiring BL[1], and the nth wiring BL (nth column) is denoted as wiring BL[n]. Note that the number of layers in element layers 430[1] to 430[m] and the number of wirings WL (and wirings PL) do not have to be the same.

[0398] Multiple memory cells 432 located in row i are electrically connected to the wiring WL (wiring WL[i]) and wiring PL (wiring PL[i]) in row i. Multiple memory cells 432 located in column j are electrically connected to the wiring BL (wiring BL[j]) in column j.

[0399] Wiring BL functions as a bit line for writing and reading data. Wiring WL functions as a word line for controlling the on or off state (conductive or non-conductive) of the access transistor, which functions as a switch. Wiring PL functions as a constant potential line connected to the capacitor. A separate wire can be provided to transmit the back gate potential.

[0400] The memory cells 432 in each of the element layers 430[1] to 430[m] are connected to the sense amplifier 446 via wiring BL. The wiring BL can be arranged in the parallel and perpendicular directions to the substrate surface on which layer 420 is provided. By configuring the wiring BL extending from the memory cells 432 in the element layers 430[1] to 430[m] with wiring arranged vertically in addition to wiring arranged horizontally on the substrate surface, the length of the wiring between the element layer 430 and the sense amplifier 446 can be shortened. The signal propagation distance between the memory cell and the sense amplifier can be shortened, and the resistance and parasitic capacitance of the bit line can be significantly reduced, thus reducing power consumption and signal delay. As a result, the power consumption and signal delay of the memory device 480 can be reduced. Furthermore, it becomes possible to operate even if the capacitance of the capacitor in the memory cell 432 is reduced. As a result, the memory device 480 can be miniaturized.

[0401] Layer 420 includes a PSW 471 (power switch), a PSW 472, and peripheral circuits 422. Peripheral circuits 422 include a drive circuit 440, a control circuit 473, and a voltage generation circuit 474. Each circuit in layer 420 is a circuit containing a Si transistor.

[0402] In the storage device 480, each circuit, each signal, and each voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or other signals may be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are external input signals, and signal RDA is an external output signal. Signal CLK is a clock signal.

[0403] Furthermore, signals BW, CE, and GW are control signals. Signal CE is the chip enable signal, signal GW is the global write enable signal, and signal BW is the byte write enable signal. Signal ADDR is the address signal. Signal WDA is the write data signal, and signal RDA is the read data signal. Signals PON1 and PON2 are power gating control signals. Signals PON1 and PON2 may be generated by the control circuit 473.

[0404] The control circuit 473 is a logic circuit that has the function of controlling the overall operation of the storage device 480. For example, the control circuit performs logical operations on signals CE, GW, and BW to determine the operating mode of the storage device 480 (e.g., write operation, read operation). Alternatively, the control circuit 473 generates a control signal for the drive circuit 440 so that this operating mode is executed.

[0405] The voltage generation circuit 474 has the function of generating a negative voltage. The signal WAKE has the function of controlling the input of the signal CLK to the voltage generation circuit 474. For example, when a high-level signal is applied to the signal WAKE, the signal CLK is input to the voltage generation circuit 474, and the voltage generation circuit 474 generates a negative voltage.

[0406] The drive circuit 440 is a circuit for writing and reading data to and from the memory cell 432. The drive circuit 440 includes a row decoder 442, a column decoder 444, a row driver 443, a column driver 445, an input circuit 447, an output circuit 448, and the aforementioned sense amplifier 446.

[0407] The row decoder 442 and column decoder 444 have the function of decoding the ADDR signal. The row decoder 442 is a circuit for specifying the row to access, and the column decoder 444 is a circuit for specifying the column to access. The row driver 443 has the function of selecting the wiring WL specified by the row decoder 442. The column driver 445 has the function of writing data to the memory cell 432, reading data from the memory cell 432, and holding the read data.

[0408] The input circuit 447 has the function of holding the signal WDA. The data held by the input circuit 447 is output to the column driver 445. The output data of the input circuit 447 is the data (Din) to be written to the memory cell 432. The data (Dout) read by the column driver 445 from the memory cell 432 is output to the output circuit 448. The output circuit 448 has the function of holding Dout. The output circuit 448 also has the function of outputting Dout to the outside of the storage device 480. The data output from the output circuit 448 is the signal RDA.

[0409] PSW 471 has the function of controlling the supply of VDD to the peripheral circuit 422. PSW 472 has the function of controlling the supply of VHM to the row driver 443. Here, the high power supply potential of the storage device 480 is VDD, and the low power supply potential is GND (ground potential). VHM is a high power supply potential used to raise the word line to a high level, and is higher than VDD. The on / off state of PSW 471 is controlled by signal PON1, and the on / off state of PSW 472 is controlled by signal PON2. In Figure 34, the number of power supply domains to which VDD is supplied in the peripheral circuit 422 is set to 1, but it can be multiple. In this case, a power switch can be provided for each power supply domain.

[0410] The element layers 430[1] to 430[m] can be layered on top of layer 420. Figure 35A shows a perspective view of a memory device 480 in which five (m=5) element layers 430[1] to 430[5] are layered on top of layer 420.

[0411] In Figure 35A, the element layer 430 provided as the first layer is shown as element layer 430[1], the element layer 430 provided as the second layer is shown as element layer 430[2], and the element layer 430 provided as the fifth layer is shown as element layer 430[5]. Also in Figure 35A, wiring WL and wiring PL extending in the X direction, and wiring BL and wiring BLB extending in the Y direction and Z direction (directions perpendicular to the substrate surface on which the drive circuit is provided) are shown. Wiring BLB is an inversion bit line. Note that, in order to make the drawing easier to read, some of the wiring WL and wiring PL of each element layer 430 have been omitted from the description.

[0412] Figure 35B shows a schematic diagram illustrating an example configuration of the wiring BL and sense amplifier 446 connected to the wiring BLB shown in Figure 35A, and the memory cells 432 having element layers 430[1] to 430[5] connected to the wiring BL and wiring BLB. A configuration in which multiple memory cells (memory cells 432) are electrically connected to one wiring BL and wiring BLB is also called a "memory string".

[0413] Figure 35B illustrates an example of the circuit configuration of a memory cell 432 connected to wiring BLB. The memory cell 432 has a transistor 437 and a capacitive element 438. The transistor 437, the capacitive element 438, and each wiring (BL, WL, etc.) may also be referred to as wiring BL[1] and wiring WL[1], for example, wiring BL and wiring WL.

[0414] In the memory cell 432, either the source or drain of transistor 437 is connected to wiring BL. The other source or drain of transistor 437 is connected to one electrode of capacitive element 438. The other electrode of capacitive element 438 is connected to wiring PL. The gate of transistor 437 is connected to wiring WL.

[0415] The wiring PL provides a constant potential to maintain the potential of the capacitive element 438. By connecting multiple wiring PLs together and using them as a single wire, the number of wires can be reduced.

[0416] In one aspect of the present invention, OS transistors are stacked, and wiring that functions as bit lines is arranged perpendicular to the substrate surface on which layer 420 is provided. In addition, the transistors 437 and capacitive elements 438 of the memory cell 432 are arranged in a parallel direction perpendicular to the substrate surface on which layer 420 is provided. By providing each element and each wiring perpendicular to the substrate surface, the length of the wiring between element layers can be shortened, and the density of elements provided per unit area can be increased. Therefore, a memory device with excellent memory capacity and reduced power consumption can be obtained.

[0417] [Example Configuration of Memory Cell 432 and Sense Amplifier 446] Figures 36A and 36B show the circuit diagram corresponding to the memory cell 432 described above, and the circuit block diagram corresponding to the said circuit diagram. As shown in Figures 36A and 36B, the memory cell 432 may be represented as a block in drawings, etc. Note that the wiring BL shown in Figures 36A and 36B can be similarly represented when replaced with wiring BLB.

[0418] Furthermore, Figures 36C and 36D show the circuit diagram corresponding to the sense amplifier 446 described above, and the circuit block diagram corresponding to said circuit diagram. The sense amplifier 446 includes a switch circuit 482, a precharge circuit 483, a precharge circuit 484, and an amplification circuit 485. In addition to wiring BL and wiring BLB, wiring SA_OUT and wiring SA_OUTB, which output the readout signal, are also shown.

[0419] As shown in Figure 36C, the switch circuit 482 includes, for example, N-type transistors 482_1 and 482_2. The N-type transistors 482_1 and 482_2 switch the conduction state of the wiring pair SA_OUT and SA_OUTB, and the wiring pair BL and BLB, according to the signal CSEL.

[0420] As shown in Figure 36C, the pre-charge circuit 483 is composed of N-type transistors 483_1 to 483_3. The pre-charge circuit 483 is a circuit for pre-charging wiring BL and wiring BLB to an intermediate potential VPRE corresponding to the potential VDD / 2, in accordance with the signal EQ.

[0421] The pre-charge circuit 484 is composed of P-type transistors 484_1 to 484_3, as shown in Figure 36C. The pre-charge circuit 484 is a circuit for pre-charging wiring BL and wiring BLB to an intermediate potential VPRE corresponding to the potential VDD / 2, in accordance with the signal EQB.

[0422] As shown in Figure 36C, the amplification circuit 485 consists of P-type transistors 485_1 and 485_2 and N-type transistors 485_3 and 485_4 connected to wiring SAP or wiring SAN. Wiring SAP or wiring SAN is wiring that has the function of providing VDD or VSS. The P-type transistors 485_1 and 485_2 and N-type transistors 485_3 and 485_4 are transistors that constitute an inverter loop.

[0423] Furthermore, Figure 36D shows a circuit block diagram corresponding to the sense amplifier 446 described in Figure 36C, etc. As shown in Figure 36D, the sense amplifier 446 may be represented as a block in drawings, etc.

[0424] Figure 37 is a circuit diagram of the storage device 480 shown in Figure 34. Figure 37 uses the circuit blocks described in Figures 36A to 36D to illustrate the circuit.

[0425] As shown in Figure 37, the layer 470, which includes the element layer 430 [m], has memory cells 432. The memory cells 432 shown in Figure 37 are connected, for example, to a pair of wiring BL[1] and wiring BLB[1], or wiring BL[2] and wiring BLB[2]. The memory cells 432 connected to wiring BL are memory cells on which data is written or read.

[0426] Wiring BL[1] and wiring BLB[1] are connected to sense amplifier 446[1], and wiring BL[2] and wiring BLB[2] are connected to sense amplifier 446[2]. Sense amplifiers 446[1] and 446[2] can read data according to the various signals described in Figure 36C.

[0427] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0428] (Embodiment 4) This embodiment describes an example of the configuration of a display device to which a transistor according to one aspect of the present invention can be applied.

[0429] Since the transistor according to one aspect of the present invention can be made extremely small, a display device to which the transistor according to one aspect of the present invention is applied can be an extremely high-resolution display device. For example, the display device according to one aspect of the present invention can be used in the display section of information terminals (wearable devices) such as wristwatches and bracelets, and in the display section of head-mounted displays (HMDs) such as VR devices such as head-mounted displays and AR devices such as glasses.

[0430] In one embodiment of the present invention, a display device can be provided with a drive circuit and a pixel circuit stacked on top of each other. In this case, the transistors constituting the pixels can be transistors in which channels are formed in a single-crystal oxide semiconductor, as exemplified in Embodiment 2.

[0431] [Display Module] Figure 38A shows a perspective view of the display module 580. The display module 580 includes a display device 500A and an FPC 590.

[0432] The display module 580 has substrates 591 and 592. The display module 580 has a display unit 581. The display unit 581 is an area for displaying an image.

[0433] Figure 38B shows a schematic perspective view illustrating the configuration of the substrate 591. A circuit section 582, a pixel circuit section 583 on the circuit section 582, and a pixel section 584 on the pixel circuit section 583 are stacked on the substrate 591. A terminal section 585 for connecting to the FPC 590 is provided in a portion of the substrate 591 that does not overlap with the pixel section 584. The terminal section 585 and the circuit section 582 are electrically connected by a wiring section 586, which is composed of multiple wires.

[0434] The pixel section 584 has a plurality of pixels 584a arranged periodically. An enlarged view of one pixel 584a is shown on the right side of Figure 38B. The pixel 584a has a light-emitting element 110R that emits red light, a light-emitting element 110G that emits green light, and a light-emitting element 110B that emits blue light.

[0435] The pixel circuit section 583 has a plurality of periodically arranged pixel circuits 583a. Each pixel circuit 583a is a circuit that controls the light emission of three light-emitting devices that one pixel 584a has. A single pixel circuit 583a may be configured to have three circuits that control the light emission of one light-emitting device. For example, each pixel circuit 583a may have at least one selection transistor, one current control transistor (drive transistor), and a capacitive element. In this case, a gate signal is input to the gate of the selection transistor, and a source signal is input to the source. This realizes an active matrix type display panel.

[0436] The circuit section 582 has circuits for driving each pixel circuit 583a of the pixel circuit section 583. For example, it is preferable to have one or both of a gate line drive circuit and a source line drive circuit. In addition, it may have at least one of the following: an arithmetic circuit, a memory circuit, and a power supply circuit. Furthermore, transistors provided in the circuit section 582 may constitute a part of the pixel circuit 583a. That is, the pixel circuit 583a may be composed of transistors in the pixel circuit section 583 and transistors in the circuit section 582.

[0437] The FPC 590 functions as wiring for supplying video signals and power potential, etc., to the circuit section 582 from an external source. An IC may also be mounted on the FPC 590.

[0438] The display module 580 can be configured such that one or both of the pixel circuit section 583 and the circuit section 582 are superimposed on the lower side of the pixel section 584, thereby making the aperture ratio (effective display area ratio) of the display section 581 extremely high. For example, the aperture ratio of the display section 581 can be 40% or more and less than 100%, preferably 50% or more and 95%, and more preferably 60% or more and 95%. Furthermore, it is possible to arrange the pixels 584a at an extremely high density, making the resolution of the display section 581 extremely high. For example, it is preferable that the pixels 584a in the display section 581 are arranged at a density of 2000 ppi or more, preferably 3000 ppi or more, more preferably 5000 ppi or more, and even more preferably 6000 ppi or more, with a resolution of 20000 ppi or less, or 30000 ppi or less.

[0439] Because such a display module 580 is extremely high-resolution, it can be suitably used in VR devices such as head-mounted displays, or in glasses-type AR devices. For example, even in a configuration where the display part of the display module 580 is viewed through lenses, the display module 580 has an extremely high-resolution display part 581, so even when the display part is magnified with lenses, pixels are not visible, allowing for a highly immersive display. Furthermore, the display module 580 is not limited to this, and can be suitably used in electronic devices with relatively small display parts. For example, it can be suitably used in the display part of wearable electronic devices such as wristwatches.

[0440] [Display device 500A] The display device 500A shown in Figure 39 has a substrate 301, a light-emitting element 110R, a light-emitting element 110G, a light-emitting element 110B, a capacitor 540, a transistor 310, and a transistor 10.

[0441] Transistor 310 is a transistor in which a channel is formed on a single-crystal substrate. Transistor 10 can also be the same transistor 10 as shown in the previous embodiment.

[0442] The transistor 310 is a transistor having a channel-forming region in the substrate 301. The substrate 301 can be a semiconductor substrate such as a single-crystal silicon substrate. The transistor 310 comprises a portion of the substrate 301, a conductive layer 311, a low-resistance region 312, an insulating layer 313, and an insulating layer 314. The conductive layer 311 functions as a gate electrode. The insulating layer 313 is located between the substrate 301 and the conductive layer 311 and functions as a gate insulating layer. The low-resistance region 312 is a region of the substrate 301 doped with impurities and functions as either a source or a drain. The insulating layer 314 is provided covering the side surface of the conductive layer 311.

[0443] Furthermore, an element isolation layer 315 is provided between two adjacent transistors 310 so as to be embedded in the substrate 301.

[0444] On the layer on which the transistor 310 is provided, insulating layers 24 to 32, the transistor 10, conductive layer 270a, insulating layer 271a, conductive layer 240b, and insulating layer 241b are provided via a wiring layer 316, an interlayer insulating layer, a conductive layer 317 provided within the interlayer insulating layer, etc.

[0445] The transistor 10 employs a configuration in which a semiconductor layer on which a channel is formed is sandwiched between two gates. The transistor may be driven by connecting the two gates and supplying them with the same signal. Alternatively, the threshold voltage of the transistor may be controlled by applying a potential to control the threshold voltage to one of the two gates and a potential to drive the other gate.

[0446] An insulating layer 564 is provided on the insulating layer 32. The insulating layer 564 functions as an interlayer insulating layer.

[0447] The conductive layer 270a, which functions as a plug that electrically connects to the conductive layer 14a, is provided so as to be embedded in the insulating layer 564, the insulating layer 32, and the insulating layer 31.

[0448] Furthermore, a capacitor 540 is provided on the insulating layer 564. The capacitor 540 has a conductive layer 541, a conductive layer 545, and an insulating layer 543 located between them. The conductive layer 541 functions as one electrode of the capacitor 540, the conductive layer 545 functions as the other electrode of the capacitor 540, and the insulating layer 543 functions as the dielectric of the capacitor 540.

[0449] The conductive layer 541 is embedded in an insulating layer 554 provided on an insulating layer 564. The conductive layer 541 is electrically connected to the conductive layer 14a of the transistor 10 by a conductive layer 270a. The insulating layer 543 is provided covering the conductive layer 541. The conductive layer 545 is provided in the region that overlaps with the conductive layer 541 via the insulating layer 543.

[0450] An insulating layer 555a is provided covering the capacitance 540, an insulating layer 555b is provided on top of the insulating layer 555a, and an insulating layer 555c is provided on top of the insulating layer 555b.

[0451] Insulating layers 555a, 555b, and 555c can each preferably be made of inorganic insulating films. For example, it is preferable to use silicon oxide films for insulating layers 555a and 555c, and silicon nitride films for insulating layer 555b. This allows insulating layer 555b to function as an etching protective film. In this embodiment, an example is shown in which a part of insulating layer 555c is etched and a recess is formed, but the insulating layer 555c does not necessarily have to have a recess.

[0452] A light-emitting element 110R, a light-emitting element 110G, and a light-emitting element 110B are provided on the insulating layer 555c.

[0453] The light-emitting element 110R has a pixel electrode 111R, an organic layer 112R, a common layer 114, and a common electrode 113. The light-emitting element 110G has a pixel electrode 111G, an organic layer 112G, a common layer 114, and a common electrode 113. The light-emitting element 110B has a pixel electrode 111B, an organic layer 112B, a common layer 114, and a common electrode 113. The common layer 114 and the common electrode 113 are provided in common to the light-emitting elements 110R, 110G, and 110B.

[0454] The organic layer 112R of the light-emitting element 110R contains at least a luminescent organic compound that emits red light. The organic layer 112G of the light-emitting element 110G contains at least a luminescent organic compound that emits green light. The organic layer 112B of the light-emitting element 110B contains at least a luminescent organic compound that emits blue light. The organic layers 112R, 112G, and 112B can each also be called EL layers and each contains at least a luminescent substance (luminescent layer).

[0455] The display device 500A has different light-emitting devices for each light-emitting color, resulting in minimal change in chromaticity between low-brightness and high-brightness illumination. Furthermore, because the organic layers 112R, 112G, and 112B are separated, crosstalk between adjacent sub-pixels can be suppressed even in high-resolution display panels. Therefore, a display panel with high resolution and high display quality can be realized.

[0456] An insulating layer 125, a resin layer 126, and a layer 128 are provided in the region between adjacent light-emitting elements.

[0457] The pixel electrodes 111R, 111G, and 111B of the light-emitting element are electrically connected to the conductive layer 14a of the transistor 10 by a plug 556 embedded in the insulating layer 555a, insulating layer 555b, and insulating layer 555c, a conductive layer 541 embedded in the insulating layer 554, and a conductive layer 270a. The height of the upper surface of the insulating layer 555c and the height of the upper surface of the plug 556 are the same. Various conductive materials can be used for the plug.

[0458] Furthermore, a protective layer 121 is provided on the light-emitting elements 110R, 110G, and 110B. The substrate 170 is bonded to the protective layer 121 by an adhesive layer 171.

[0459] There is no insulating layer covering the upper edge of the pixel electrode 111 between two adjacent pixel electrodes 111. Therefore, the spacing between adjacent light-emitting elements can be made extremely narrow. Consequently, a high-definition or high-resolution display device can be made.

[0460] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0461] (Embodiment 5) In this embodiment, an electronic device according to one aspect of the present invention will be described with reference to Figures 40A to 42G.

[0462] The electronic device of this embodiment has a display panel (display device) to which a transistor according to one aspect of the present invention is applied in the display unit. The display device according to one aspect of the present invention can be easily made high-definition and high-resolution, and can achieve high display quality. Therefore, it can be used in the display unit of various electronic devices.

[0463] Examples of electronic devices include television sets, desktop or laptop computers, computer monitors, digital signage, and large game machines such as pachinko machines, as well as other electronic devices with relatively large screens, digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, personal digital assistants, and audio playback devices.

[0464] In particular, a display panel according to one embodiment of the present invention can be used suitably in electronic devices having a relatively small display area because it can increase the resolution. Examples of such electronic devices include wristwatch-type and bracelet-type information terminals (wearable devices), as well as wearable devices that can be worn on the head, such as VR devices such as head-mounted displays, AR devices such as glasses, and MR devices.

[0465] A display panel according to one embodiment of the present invention preferably has an extremely high resolution such as HD (1280 x 720 pixels), FHD (1920 x 1080 pixels), WQHD (2560 x 1440 pixels), WQXGA (2560 x 1600 pixels), 4K (3840 x 2160 pixels), or 8K (7680 x 4320 pixels). In particular, a resolution of 4K, 8K, or higher is preferred. Furthermore, the pixel density (resolution) of the display panel according to one embodiment of the present invention is preferably 100 ppi or more, preferably 300 ppi or more, more preferably 500 ppi or more, more preferably 1000 ppi or more, more preferably 2000 ppi or more, more preferably 3000 ppi or more, more preferably 5000 ppi or more, and even more preferably 7000 ppi or more. By using a display panel having either high resolution or high detail, or both, it becomes possible to further enhance the sense of presence and depth. Furthermore, there are no particular limitations on the aspect ratio of the display panel in one embodiment of the present invention. For example, the display panel can support various aspect ratios such as 1:1 (square), 4:3, 16:9, and 16:10.

[0466] The electronic device of this embodiment may have sensors (including those with the function of detecting, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared radiation).

[0467] The electronic device of this embodiment can have a variety of functions. For example, it can have a function to display various information (still images, videos, text images, etc.) on the display unit, a touch panel function, a function to display a calendar, date or time, a function to execute various software (programs), a wireless communication function, a function to read programs or data recorded on a recording medium, and so on.

[0468] Figures 40A to 40D illustrate an example of a wearable device that can be worn on the head. These wearable devices have one or both functions: the ability to display AR content and / or VR content. In addition to AR and VR, these wearable devices may also have functions to display SR or MR content. By having an electronic device that has the ability to display at least one of the following content types, such as AR, VR, SR, and MR, it is possible to enhance the user's sense of immersion.

[0469] The electronic device 700A shown in Figure 40A and the electronic device 700B shown in Figure 40B each include a pair of display panels 751, a pair of housings 721, a communication unit (not shown), a pair of mounting units 723, a control unit (not shown), an imaging unit (not shown), a pair of optical members 753, a frame 757, and a pair of nose pads 758.

[0470] A display panel according to one embodiment of the present invention can be applied to the display panel 751. Therefore, an electronic device capable of displaying extremely high resolution can be created.

[0471] Electronic devices 700A and 700B can project an image displayed on the display panel 751 onto the display area 756 of the optical element 753. Because the optical element 753 is translucent, the user can see the image displayed on the display area superimposed on the transmitted image visible through the optical element 753. Therefore, electronic devices 700A and 700B are electronic devices capable of AR display.

[0472] Electronic devices 700A and 700B may be equipped with cameras capable of capturing images of the area in front of them as imaging units. Furthermore, electronic devices 700A and 700B may each be equipped with acceleration sensors such as gyro sensors to detect the orientation of the user's head and display an image corresponding to that orientation in the display area 756.

[0473] The communications unit has a wireless communication device, which can supply video signals and the like. Alternatively, instead of the wireless communication device, or in addition to the wireless communication device, it may be equipped with a connector to which a cable supplying video signals and power potential can be connected.

[0474] Furthermore, electronic devices 700A and 700B are equipped with batteries (not shown) that can be charged wirelessly, wired, or both.

[0475] The housing 721 may be equipped with a touch sensor module. The touch sensor module has the function of detecting when the outer surface of the housing 721 is touched. The touch sensor module can detect the user's tap or slide operations and perform various processes. For example, a tap operation can be used to pause or resume the video, and a slide operation can be used to fast forward or rewind. Furthermore, by providing a touch sensor module in each of the two housings 721, the range of operations can be expanded.

[0476] Various types of touch sensors can be applied to the touch sensor module. For example, various methods such as capacitive, resistive, infrared, electromagnetic induction, surface acoustic wave, and optical sensors can be used. In particular, it is preferable to apply a capacitive or optical sensor to the touch sensor module.

[0477] When using an optical touch sensor, a photoelectric conversion device (also called a photoelectric element) can be used as the light-receiving device (also called a photoelectric element). The active layer of the photoelectric conversion device can be made of either an inorganic semiconductor or an organic semiconductor, or both.

[0478] The electronic device 800A shown in Figure 40C and the electronic device 800B shown in Figure 40D each include a pair of display units 820, a housing 821, a communication unit 822, a pair of mounting units 823, a control unit 824, a pair of imaging units 825, and a pair of lenses 832.

[0479] A display panel according to one embodiment of the present invention can be applied to the display unit 820. Therefore, an electronic device capable of displaying extremely high resolution can be created. This allows the user to experience a high level of immersion.

[0480] The display unit 820 is located inside the housing 821 in a position visible through the lens 832. Furthermore, by displaying different images on a pair of display units 820, a three-dimensional display using parallax can be achieved.

[0481] Electronic devices 800A and 800B can each be described as electronic devices for VR. A user wearing electronic device 800A or electronic device 800B can view the image displayed on the display unit 820 through the lens 832.

[0482] It is preferable that electronic devices 800A and 800B each have a mechanism that allows adjustment of the left and right positions of the lens 832 and the display unit 820 so that they are in the optimal position according to the user's eye position. It is also preferable that they have a mechanism that adjusts the focus by changing the distance between the lens 832 and the display unit 820.

[0483] The attachment portion 823 allows the user to attach the electronic device 800A or 800B to their head. While the attachment portion 823 is exemplified in Figure 40C and other figures as resembling the temples (or arms) of eyeglasses, it is not limited to this. The attachment portion 823 only needs to be wearable by the user; for example, it may be helmet-shaped or band-shaped.

[0484] The imaging unit 825 has the function of acquiring external information. The data acquired by the imaging unit 825 can be output to the display unit 820. An image sensor can be used in the imaging unit 825. In addition, multiple cameras may be provided to accommodate multiple angles of view, such as telephoto and wide-angle.

[0485] Although an example with an imaging unit 825 is shown here, any distance measuring sensor (hereinafter also referred to as a detection unit) capable of measuring the distance to an object can be provided. In other words, the imaging unit 825 is one form of the detection unit. As the detection unit, for example, an image sensor or a distance image sensor such as LiDAR (Light Detection and Ranging) can be used. By using the image obtained by the camera and the image obtained by the distance image sensor, more information can be acquired, enabling more accurate gesture control.

[0486] The electronic device 800A may have a vibration mechanism that functions as a bone conduction earphone. For example, a configuration having such a vibration mechanism can be applied to one or more of the display unit 820, housing 821, and mounting unit 823. This allows users to enjoy video and audio simply by wearing the electronic device 800A, without needing separate audio equipment such as headphones, earphones, or speakers.

[0487] Electronic devices 800A and 800B may each have input terminals. Cables can be connected to the input terminals to supply video signals from video output devices, etc., and power for charging batteries provided in the electronic devices.

[0488] An electronic device according to one aspect of the present invention may have a function for wireless communication with an earphone 750. The earphone 750 has a communication unit (not shown) and has a wireless communication function. The earphone 750 can receive information (e.g., voice data) from the electronic device through its wireless communication function. For example, the electronic device 700A shown in Figure 40A has a function for transmitting information to the earphone 750 through its wireless communication function. Also, for example, the electronic device 800A shown in Figure 40C has a function for transmitting information to the earphone 750 through its wireless communication function.

[0489] Furthermore, the electronic device may have an earphone section. The electronic device 700B shown in Figure 40B has an earphone section 727. For example, the earphone section 727 and the control unit can be connected to each other by a wire. Part of the wiring connecting the earphone section 727 and the control unit may be located inside the housing 721 or the mounting section 723.

[0490] Similarly, the electronic device 800B shown in Figure 40D has an earphone unit 827. For example, the earphone unit 827 and the control unit 824 can be connected to each other by a wire. Part of the wiring connecting the earphone unit 827 and the control unit 824 may be located inside the housing 821 or the mounting unit 823. Also, the earphone unit 827 and the mounting unit 823 may have magnets. This allows the earphone unit 827 to be fixed to the mounting unit 823 by magnetic force, which is preferable as it makes storage easier.

[0491] Furthermore, the electronic device may have an audio output terminal to which earphones or headphones can be connected. The electronic device may also have an audio input terminal and / or an audio input mechanism. For example, a sound-collecting device such as a microphone can be used as the audio input mechanism. By having an audio input mechanism, the electronic device may be given the function of a so-called headset.

[0492] Thus, as one embodiment of the present invention, both eyeglass-type (electronic devices 700A and 700B, etc.) and goggle-type (electronic devices 800A and 800B, etc.) are preferred as electronic devices.

[0493] The electronic device 6500 shown in Figure 41A is a portable information terminal that can be used as a smartphone.

[0494] The electronic device 6500 includes a housing 6501, a display unit 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and a control device 6509. The display unit 6502 has a touch panel function. The control device 6509 includes, for example, one or more selected from a CPU, a GPU, and a storage device. A semiconductor device according to one aspect of the present invention can be applied to the display unit 6502, the control device 6509, etc. Using a semiconductor device according to one aspect of the present invention as the control device 6509 is preferable because it can reduce power consumption.

[0495] A display panel according to one embodiment of the present invention can be applied to the display unit 6502.

[0496] Figure 41B is a schematic cross-sectional view of the housing 6501 including the end on the microphone 6506 side.

[0497] A light-transmitting protective member 6510 is provided on the display side of the housing 6501, and the display panel 6511, optical member 6512, touch sensor panel 6513, printed circuit board 6517, battery 6518, etc. are arranged in the space enclosed by the housing 6501 and the protective member 6510.

[0498] The protective member 6510 is fixed to the display panel 6511, the optical member 6512, and the touch sensor panel 6513 by an adhesive layer (not shown).

[0499] In the area outside the display unit 6502, a portion of the display panel 6511 is folded back, and the FPC 6515 is connected to this folded portion. IC 6516 is mounted on the FPC 6515. The FPC 6515 is connected to terminals provided on the printed circuit board 6517.

[0500] A display device according to one embodiment of the present invention can be applied to the display panel 6511. As a result, an extremely lightweight electronic device can be realized. Furthermore, because the display panel 6511 is extremely thin, a large-capacity battery 6518 can be installed while keeping the thickness of the electronic device low. In addition, by folding back a part of the display panel 6511 and placing the connection part with the FPC 6515 on the back of the pixel section, an electronic device with a narrow bezel can be realized.

[0501] Figure 41C shows an example of a television system. The television system 7100 has a display unit 7000 incorporated into a housing 7101. Here, the housing 7101 is shown to be supported by a stand 7103.

[0502] The television device 7100 shown in Figure 41C can be operated using the operation switches on the housing 7101 and a separate remote control unit 7111. Alternatively, the display unit 7000 may be equipped with a touch sensor, and the television device 7100 can be operated by touching the display unit 7000 with a finger or the like. The remote control unit 7111 may have a display unit that displays information output from the remote control unit 7111. Channels and volume can be controlled and the image displayed on the display unit 7000 can be controlled using the operation keys or touch panel on the remote control unit 7111.

[0503] The television system 7100 is configured to include a receiver and a modem. The receiver can receive general television broadcasts. Furthermore, by connecting to a wired or wireless communication network via the modem, it is possible to perform one-way (from sender to receiver) or two-way (between sender and receiver, or between receivers, etc.) information communication.

[0504] Figure 41D shows an example of a notebook computer. The notebook computer 7200 includes a casing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, a control device 7216, etc. A display unit 7000 is incorporated into the casing 7211. The control device 7216 includes, for example, one or more selected from a CPU, a GPU, and a storage device. A semiconductor device according to one aspect of the present invention can be applied to the display unit 7000, the control device 7216, etc. Using a semiconductor device according to one aspect of the present invention as the control device 7216 is preferable because it can reduce power consumption.

[0505] Figures 41E and 41F show examples of digital signage.

[0506] The digital signage 7300 shown in Figure 41E includes a housing 7301, a display unit 7000, and a speaker 7303, etc. Furthermore, it may include LED lamps, operation keys (including a power switch or operation switch), connection terminals, various sensors, a microphone, etc.

[0507] Figure 41F shows a digital signage 7400 mounted on a cylindrical column 7401. The digital signage 7400 has a display unit 7000 that is provided along the curved surface of the column 7401.

[0508] The larger the display area 7000, the more information can be provided at once. Furthermore, a larger display area 7000 is more eye-catching, which can, for example, enhance the effectiveness of advertising.

[0509] Applying a touch panel to the display unit 7000 is preferable because it not only allows images or videos to be displayed on the display unit 7000, but also enables intuitive operation by the user. Furthermore, when used for purposes such as providing route information or traffic information, intuitive operation can enhance usability.

[0510] Furthermore, as shown in Figures 41E and 41F, it is preferable that the digital signage 7300 or digital signage 7400 can be linked wirelessly with an information terminal 7311 or information terminal 7411 such as a smartphone owned by the user. For example, the advertising information displayed on the display unit 7000 can be displayed on the screen of the information terminal 7311 or information terminal 7411. Also, the display on the display unit 7000 can be switched by operating the information terminal 7311 or information terminal 7411.

[0511] Furthermore, the digital signage 7300 or digital signage 7400 can be used to run games using the screen of the information terminal 7311 or information terminal 7411 as the control device (controller). This allows an unspecified number of users to participate in and enjoy the game simultaneously.

[0512] In Figures 41C to 41F, a display panel according to one embodiment of the present invention can be applied to the display unit 7000.

[0513] The electronic device shown in Figures 42A to 42G includes a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or operation switch), connection terminals 9006, a sensor 9007 (including a function to detect, detect, or measure force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared radiation), a microphone 9008, and the like.

[0514] The electronic devices shown in Figures 42A to 42G have various functions. For example, they may have functions to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date or time, a function to control processing by various software (programs), a wireless communication function, a function to read and process programs or data recorded on a recording medium, etc. However, the functions of electronic devices are not limited to these and can have various functions. Electronic devices may have multiple display units. Furthermore, electronic devices may be equipped with a camera, etc., and have functions to capture still images or videos and save them to a recording medium (external or built into the camera), a function to display the captured images on a display unit, etc.

[0515] Details of the electronic equipment shown in Figures 42A to 42G will be explained below.

[0516] Figure 42A is a perspective view showing a personal digital information terminal (PDI) 9101. The PDI 9101 can be used, for example, as a smartphone. The PDI 9101 may also be equipped with a speaker 9003, connection terminals 9006, sensors 9007, etc. The PDI 9101 can also display text and image information on multiple surfaces. Figure 42A shows an example where three icons 9050 are displayed. Information 9051, indicated by a dashed rectangle, can also be displayed on other surfaces of the display unit 9001. Examples of information 9051 include notifications of incoming emails, SNS messages, and phone calls, the subject of an email or SNS message, the sender's name, date and time, battery level, and signal strength. Alternatively, icons 9050 or the like may be displayed in the location where the information 9051 is displayed.

[0517] Figure 42B is a perspective view showing the personal digital assistant (PDA) 9102. The PDA 9102 has the function of displaying information on three or more sides of the display unit 9001. Here, an example is shown in which information 9052, information 9053, and information 9054 are displayed on different sides. For example, a user can check information 9053, which is displayed in a position that can be observed from above the PDA 9102, while the PDA 9102 is stored in the breast pocket of their clothing. The user can check the display without taking the PDA 9102 out of their pocket and decide, for example, whether or not to answer a call.

[0518] Figure 42C is a perspective view showing the tablet terminal 9103. The tablet terminal 9103 can run various applications, such as mobile phone calls, email, document viewing and creation, music playback, internet communication, and computer games. The tablet terminal 9103 has a display unit 9001, a camera 9002, a microphone 9008, and a speaker 9003 on the front of the housing 9000. The left side of the housing 9000 has operation keys 9005 as buttons for operation, and the bottom has connection terminals 9006.

[0519] Figure 42D is a perspective view showing a wristwatch-type personal information terminal 9200. The personal information terminal 9200 can be used, for example, as a smartwatch (registered trademark). The display unit 9001 has a curved display surface, allowing it to display information along the curved surface. The personal information terminal 9200 can also make hands-free calls by communicating with, for example, a wireless communication headset. Furthermore, the personal information terminal 9200 can transmit data to other information terminals and be charged via a connection terminal 9006. The charging operation may be performed by wireless power supply.

[0520] Figures 42E to 42G are perspective views showing a foldable portable information terminal 9201. Figure 42E shows the portable information terminal 9201 in an unfolded state, Figure 42G shows it in a folded state, and Figure 42F shows a perspective view of the state in between, transitioning from one of Figures 42E or 42G to the other. The portable information terminal 9201 offers excellent portability in its folded state and excellent readability of the display due to its seamless, wide display area in its unfolded state. The display unit 9001 of the portable information terminal 9201 is supported by three housings 9000 connected by hinges 9055. For example, the display unit 9001 can be bent with a radius of curvature of 0.1 mm to 150 mm.

[0521] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0522] (Embodiment 6) This embodiment describes an application example of a semiconductor device according to one aspect of the present invention. A semiconductor device according to one aspect of the present invention can be used, for example, in electronic components, electronic equipment, large computers, space equipment, and data centers (also referred to as Data Centers: DCs). Electronic components, electronic equipment, large computers, space equipment, and data centers using a semiconductor device according to one aspect of the present invention are effective in achieving high performance, such as low power consumption.

[0523] Electronic components and the like to which a semiconductor device according to one embodiment of the present invention is applied can be applied to the electronic device exemplified in Embodiment 6.

[0524] [Electronic Components] Figure 43A shows a perspective view of a substrate (mounted substrate 704) on which electronic components 700 are mounted. The electronic component 700 shown in Figure 43A has a semiconductor device 710 inside a mold 711. Some details are omitted in Figure 43A to show the inside of the electronic component 700. The electronic component 700 has a land 712 on the outside of the mold 711. The land 712 is electrically connected to an electrode pad 713, and the electrode pad 713 is electrically connected to the semiconductor device 710 via a wire 714. The electronic component 700 is mounted on a printed circuit board 702, for example. Multiple such electronic components are combined and electrically connected on the printed circuit board 702 to complete the mounted substrate 704.

[0525] Furthermore, the semiconductor device 710 includes a drive circuit layer 715 and a storage layer 716. The storage layer 716 has a configuration in which multiple memory cell arrays are stacked. The configuration in which the drive circuit layer 715 and the storage layer 716 are stacked can be a monolithic stack configuration. In a monolithic stack configuration, the layers can be connected without using through-electrode technologies such as TSV (Through Silicon Via) and bonding technologies such as Cu-Cu direct bonding. By monolithically stacking the drive circuit layer 715 and the storage layer 716, for example, a so-called on-chip memory configuration can be achieved in which memory is directly formed on the processor. By using an on-chip memory configuration, it is possible to speed up the operation of the interface portion between the processor and the memory.

[0526] Furthermore, by using an on-chip memory configuration, the size of connection wiring can be reduced compared to technologies using through-hole electrodes such as TSVs, making it possible to increase the number of connection pins. Increasing the number of connection pins enables parallel operation, which in turn improves the memory bandwidth (also called memory bandwidth).

[0527] Furthermore, it is preferable to form the multiple memory cell arrays in the memory layer 716 using OS transistors and to stack these multiple memory cell arrays monolithically. By configuring the multiple memory cell arrays in a monolithic stack, it is possible to improve either or both of the memory bandwidth and / or the memory access latency. Bandwidth is the amount of data transferred per unit time, and access latency is the time from access to the start of data exchange. In the case of a configuration using Si transistors in the memory layer 716, it is difficult to create a monolithic stack configuration compared to OS transistors. Therefore, in a monolithic stack configuration, OS transistors can be said to have a superior structure compared to Si transistors.

[0528] Furthermore, the semiconductor device 710 may also be referred to as a die. In this specification, a die refers to a chip piece obtained in the semiconductor chip manufacturing process by forming a circuit pattern on, for example, a disc-shaped substrate (also called a wafer) and cutting it into cubes. Examples of semiconductor materials that can be used for dies include silicon (Si), silicon carbide (SiC), or gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) is sometimes called a silicon die.

[0529] Next, a perspective view of the electronic component 730 is shown in Figure 43B. The electronic component 730 is an example of a SiP (System in Package) or MCM (Multi-Chip Module). The electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of semiconductor devices 710 are provided on the interposer 731.

[0530] Electronic component 730 shows an example of using semiconductor device 710 as a high-bandwidth memory (HBM). Furthermore, semiconductor device 735 can be used in integrated circuits such as CPUs, GPUs (Graphics Processing Units), or FPGAs (Field Programmable Gate Arrays).

[0531] The package substrate 732 can be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate. The interposer 731 can be, for example, a silicon interposer or a resin interposer.

[0532] The interposer 731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also functions to electrically connect integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer is sometimes called a "redistribution board" or "intermediate board". In addition, through electrodes may be provided on the interposer 731, and these through electrodes may be used to electrically connect the integrated circuits and the package substrate 732. Furthermore, in silicon interposers, TSVs can also be used as through electrodes.

[0533] In HBMs, many connections are necessary to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted requires fine and high-density wiring. For this reason, it is preferable to use a silicon interposer for mounting the HBM.

[0534] Furthermore, in SiP and MCM using silicon interposers, reliability degradation due to differences in expansion coefficients between the integrated circuit and the interposer is less likely to occur. In addition, because silicon interposers have high surface flatness, connection failures between the integrated circuit and the silicon interposer are less likely to occur. In particular, in 2.5D packages (2.5-dimensional packaging) where multiple integrated circuits are arranged side by side on the interposer, it is preferable to use a silicon interposer.

[0535] On the other hand, when electrically connecting multiple integrated circuits with different terminal pitches using silicon interposers and TSVs, space is required, such as the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 730, the width of the terminal pitch becomes a problem, and it may become difficult to provide the many wires necessary to achieve a wide memory bandwidth. For this reason, as mentioned above, a monolithic stacked configuration using OS transistors is preferable. A composite structure combining a memory cell array stacked using TSVs and a monolithic stacked memory cell array may also be used.

[0536] Alternatively, a heat sink (heat dissipation plate) may be provided on top of the electronic component 730. If a heat sink is provided, it is preferable to align the heights of the integrated circuits provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the heights of the semiconductor device 710 and the semiconductor device 735.

[0537] To mount the electronic component 730 onto another substrate, electrodes 733 may be provided at the bottom of the package substrate 732. Figure 43B shows an example in which the electrodes 733 are formed with solder balls. By providing solder balls in a matrix at the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, the electrodes 733 may be formed with conductive pins. By providing conductive pins in a matrix at the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0538] The electronic component 730 can be mounted on other boards using various mounting methods, not limited to BGA and PGA. Examples of mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).

[0539] [Large-scale computer] Figure 44A shows a perspective view of the large-scale computer 5600. The large-scale computer 5600 houses multiple rack-mount type computers 5620 in rack 5610. The large-scale computer 5600 may also be referred to as a supercomputer.

[0540] Figure 44B shows a perspective view of an example of a computer 5620. The computer 5620 has a motherboard 5630. The motherboard 5630 is provided with multiple slots 5631 and multiple connection terminals. A PC card 5621 is inserted into a slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are connected to the motherboard 5630.

[0541] Figure 44C shows an example of a PC card 5621. The PC card 5621 is a processing board equipped with, for example, a CPU, GPU, and memory device. The PC card 5621 has a board 5622 and connectors 5623, 5624, 5625, electronic components 5626, 5627, 5628, and 5629 mounted on the board 5622. Note that Figure 44C shows components other than electronic components 5626, 5627, and 5628.

[0542] The connector 5629 has a shape that allows it to be inserted into the slot 5631 of the motherboard 5630, and functions as an interface for connecting the PC card 5621 and the motherboard 5630. Examples of standards for the connector 5629 include PCIe.

[0543] Terminals 5623, 5624, and 5625 can serve as interfaces for, for example, power supply and signal input to the PC card 5621. They can also serve as interfaces for, for example, outputting signals calculated by the PC card 5621. Examples of standards for terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). When outputting video signals from terminals 5623, 5624, and 5625, examples of standards include HDMI (registered trademark).

[0544] The electronic component 5626 has terminals (not shown) for inputting and outputting signals, and by inserting these terminals into a socket (not shown) on the board 5622, the electronic component 5626 and the board 5622 can be electrically connected.

[0545] Electronic components 5627 and 5628 have multiple terminals, and these terminals can be mounted to the wiring provided on board 5622 by, for example, reflow soldering. Examples of electronic component 5627 include FPGAs, GPUs, and CPUs. For example, electronic component 730 can be used as electronic component 5627. Examples of electronic component 5628 include memory devices. For example, electronic component 700 can be used as electronic component 5628.

[0546] The 5600 mainframe computer can also function as a parallel computer. By using the 5600 mainframe computer as a parallel computer, it is possible to perform large-scale calculations necessary for, for example, artificial intelligence training and inference.

[0547] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0548] (Embodiment 7) A semiconductor device according to one aspect of the present invention will be described. Figure 45A is a schematic perspective view of a semiconductor device 610 according to one aspect of the present invention. Figure 45B is a schematic perspective view of a part of the semiconductor device 610. Figure 46 is a schematic perspective view illustrating the configuration of the semiconductor device 610.

[0549] In Figures 45A, 45B, and 46, the semiconductor device 610 has an element layer 670 below an element layer 620 which includes a substrate 622 that is a semiconductor substrate, and a support substrate 640 above the element layer 620 via an insulating layer 641. The element layer 620 has a plurality of transistors 621 which constitute a functional circuit 611. The element layer 670 has a plurality of transistors 671 which constitute a switch circuit 615. The transistors 671 function as switches to control the conduction and non-conductivity between an external power supply line and a conductive layer 672 which functions as a power line.

[0550] The transistor exemplified in Embodiment 1 can be used for transistor 671.

[0551] The transistor 621 in element layer 620 is formed on the front surface (also called the "first surface") of the substrate 622. The element layer 670 is formed on the back surface (the surface opposite to the front surface, also called the "second surface") of the substrate 622. Therefore, the transistor 671 in element layer 670 is formed on the second surface of the substrate 622.

[0552] In Figure 46, the functional circuit 611 is illustrated as a CPU 612, a GPU 613, and a memory 614.

[0553] Furthermore, the functional circuit 611 is not limited to the CPU 612, GPU 613, and memory 614, and one or more of these can be used. It is also possible to include circuits with other functions.

[0554] To improve the operating speed, mounting density, and power consumption of the semiconductor device 610, the functional circuit 611 requires miniaturization and thinning of transistors, wiring, etc., and reduction of the power supply potential. The switch circuit 615 can control the supply of voltage supplied from an external source to each circuit of the functional circuit 611, and to stop the supply. This makes it possible to stop the supply of power potential to circuits in standby mode, thereby reducing power consumption.

[0555] Furthermore, the transistors constituting the switch circuit 615 require high dielectric strength. One effective way to increase the dielectric strength of the transistors is to thicken the gate insulating film. Thus, transistors 621 and 671 require different performance characteristics. Therefore, different measures are needed to improve the characteristics of transistors 621 and 671.

[0556] Furthermore, miniaturization and thinning are required for the functional circuit 611. Therefore, if the switch circuit 615 is constructed using the same process node as the functional circuit 611, not only the routing wiring but also the wiring for supplying power (power lines) will become thinner, and sufficient power cannot be supplied to the functional circuit 611. In addition, if the wiring resistance increases due to miniaturization, uneven power potential is likely to occur within the functional circuit 611 due to voltage drop. In order to stably supply power to the functional circuit 611, it is preferable that the wiring constituting the switch circuit 615 has a lower wiring resistance than the wiring constituting the functional circuit 611. In particular, it is preferable that the wiring that functions as a power line has a lower wiring resistance than the wiring constituting the functional circuit 611. One means of reducing wiring resistance is to increase the cross-sectional area of ​​the conductive layer that functions as wiring. However, in order to increase the cross-sectional area of ​​the conductive layer, it is necessary to increase one or both of the width and height of the conductive layer. Thus, it is preferable to use different process nodes for the functional circuit 611 and the switch circuit 615.

[0557] In a semiconductor device 610 according to one aspect of the present invention, by providing the functional circuit 611 and the switch circuit 615 on different element layers, different improvement measures can be implemented in the functional circuit 611 and the switch circuit 615. Furthermore, the functional circuit 611 and the switch circuit 615 can be formed at different process nodes.

[0558] In one aspect of the present invention, a plurality of conductive layers 672 that function as power lines and a switch circuit 615 can be arranged below the functional circuit 611, thereby reducing the occupied area of ​​the semiconductor device 610. Furthermore, it is preferable that the element layer 670, which is superimposed on the element layer 620, be formed using thin-film formation techniques such as CVD or sputtering. Therefore, the transistor 671 included in the element layer 670 is preferably a thin-film transistor.

[0559] At least a portion of the multiple conductive layers 672 of the element layer 670 can function as power lines. Furthermore, if the element layer 670 has a clock signal generation circuit, at least a portion of the multiple conductive layers 672 can function as clock signal lines. It is also possible to supply either or both of the power supply and / or clock signal supplied from an external source to the functional circuit 611 of the element layer 620 via at least a portion of the multiple conductive layers 672.

[0560] For example, it is possible to manufacture a die (semiconductor chip) containing the functional circuit 611 and a die containing the switch circuit 615 separately, and then mechanically bond them together using 3D integration technology. However, with 3D integration technology, improving alignment accuracy is difficult because the two are bonded mechanically, and miniaturizing the bumps used to connect them is also difficult, making it difficult to narrow the pitch of the connection points. As a result, there was a challenge in shortening the wiring distance required to supply power to the necessary parts of the functional circuit 611.

[0561] According to one aspect of the present invention, an element layer 670 including a switch circuit 615 is formed on the back side of the substrate 622 using thin-film formation technology, photolithography technology, or the like. Therefore, the semiconductor device 610 according to one aspect of the present invention is a monolithically stacked semiconductor device.

[0562] By forming the element layer 670 using thin-film formation technology, high-precision alignment at the photolithography level can be achieved. Furthermore, conductive layers that function as power lines can be connected to the necessary locations of the functional circuit 611 over extremely short distances. Therefore, the necessary voltage of power can be supplied to the necessary locations of the functional circuit 611. In addition, in the semiconductor device 610 according to one aspect of the present invention, since the connection distance between the switch circuit 615 and the functional circuit 611 is short, power loss related to power transmission is reduced, and power consumption can be reduced.

[0563] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0564] ADDR: signal, BL: wiring, BLB: wiring, BW: signal, CE: signal, CLK: signal, CSEL: signal, EQ: signal, EQB: signal, GW: signal, PL: wiring, RDA: signal, SA_OUT: wiring, SA_OUTB: wiring, SAN: wiring, SAP: wiring, VPRE: intermediate potential, WAKE: signal, WDA: signal, WL: wiring, 10: transistor, 11: semiconductor layer, 11f: semiconductor layer, 12: insulating layer, 12_1: insulating layer, 12_2: insulating layer, 12_3: insulating layer, 12_4: insulating layer, 13: conductive layer, 13_1: conductive layer, 13_2: conductive layer, 14: conductive layer 14a: conductive layer, 14a_1: conductive layer, 14a_2: conductive layer, 14b: conductive layer, 14b_1: conductive layer, 14b_2: conductive layer, 15: insulating layer, 15_1: insulating layer, 15_2: insulating layer, 16: insulating layer, 16a: insulating layer, 16b: insulating layer, 17: insulating layer, 18: insulating layer, 19: sacrificial layer, 20: sacrificial layer, 21: insulating layer, 22: insulating layer, 23: conductive layer, 24: insulating layer, 25: insulating layer, 29: insulating layer, 31: insulating layer, 32: insulating layer, 110B: light-emitting element, 110G: light-emitting element, 110R: light-emitting element, 111B: pixel electrode, 111G: pixel electrode, 111R: pixel electrode , 112B: Organic layer, 112G: Organic layer, 112R: Organic layer, 113: Common electrode, 114: Common layer, 121: Protective layer, 125: Insulating layer, 126: Resin layer, 128: Layer, 170: Substrate, 171: Adhesive layer, 240a: Conductive layer, 240b: Conductive layer, 241a: Insulating layer, 241b: Insulating layer, 270a: Conductive layer, 270b: Conductive layer, 271a: Insulating layer, 271b: Insulating layer, 301: Substrate, 310: Transistor, 311: Conductive layer, 312: Low resistance region, 313: Insulating layer, 314: Insulating layer, 315: Element isolation layer, 316: Wiring layer, 317: Conductive layer, 420: Layer, 4 22: Peripheral circuitry, 430: Element layer, 432: Memory cell, 437: Transistor, 438: Capacitive element, 440: Drive circuitry, 442: Row decoder, 443: Row driver, 444: Column decoder, 445: Column driver, 446: Sense amplifier, 447: Input circuitry, 448: Output circuitry, 470: Layer, 471: PSW, 472: PSW, 473: Control circuitry, 474: Voltage generation circuitry, 480: Memory device, 482: Switch circuitry, 482_1: N-type transistor, 482_2: N-type transistor, 483: Precharge circuitry, 483_1: N-type transistor,483_3: N-type transistor, 484: Pre-charge circuit, 484_1: P-type transistor, 484_3: P-type transistor, 485: Amplifier circuit, 485_1: P-type transistor, 485_2: P-type transistor, 485_3: N-type transistor, 485_4: N-type transistor, 500A: Display device, 540: Capacitor, 541: Conductive layer, 543: Insulating layer, 545: Conductive layer, 554: Insulating layer, 555a: Insulating layer, 555b: Insulating layer, 555c: Insulating layer, 556: Plug, 564: Insulating layer, 580: Display module, 581: Display unit, 582: Circuit unit, 58 3: Pixel circuit section, 583a: Pixel circuit, 584: Pixel section, 584a: Pixel, 585: Terminal section, 586: Wiring section, 590: FPC, 591: Substrate, 592: Substrate, 610: Semiconductor device, 611: Functional circuit, 612: CPU, 613: GPU, 614: Memory, 615: Switch circuit, 620: Element layer, 621: Transistor, 622: Substrate, 640: Support substrate, 641: Insulating layer, 670: Element layer, 671: Transistor, 672: Conductive layer, 700: Electronic component, 700A: Electronic device, 700B: Electronic device, 702: Printed circuit board, 704: Mounting substrate, 710: Semiconductor device, 711: mold, 712: land, 713: electrode pad, 714: wire, 715: drive circuit layer, 716: memory layer, 721: housing, 723: mounting part, 727: earphone part, 730: electronic component, 731: interposer, 732: package substrate, 733: electrode, 735: semiconductor device, 750: earphone, 751: display panel, 753: optical component, 756: display area, 757: frame, 758: nose pad, 800A: electronic device, 800B: electronic device, 820: display part, 821: housing, 822: communication part, 823: mounting part, 824: control unit, 8 25: Imaging unit, 827: Earphone unit, 832: Lens, 5600: Large computer, 5610: Rack, 5620: Computer, 5621: PC card, 5622: Board, 5623: Connection terminal, 5624: Connection terminal, 5625: Connection terminal, 5626: Electronic component, 5627: Electronic component, 5628: Electronic component, 5629: Connection terminal, 5630: Motherboard, 5631: Slot, 6500: Electronic equipment, 6501: Enclosure, 6502: Display unit, 6503: Power button, 6504: Button, 6505: Speaker, 6506: Microphone, 6507: Camera, 6508: Light source,6509: Control device, 6510: Protective component, 6511: Display panel, 6512: Optical component, 6513: Touch sensor panel, 6515: FPC, 6516: IC, 6517: Printed circuit board, 6518: Battery, 7000: Display unit, 7100: Television equipment, 7101: Enclosure, 7103: Stand, 7111: Remote control unit, 7200: Notebook computer, 7211: Enclosure, 7212: Keyboard, 7213: Pointing device, 7214: External connection port, 7216: Control device, 7300: Digital signage, 7301: Enclosure Body, 7303: Speaker, 7311: Information terminal, 7400: Digital signage, 7401: Pillar, 7411: Information terminal, 9000: Enclosure, 9001: Display unit, 9002: Camera, 9003: Speaker, 9005: Operation keys, 9006: Connection terminal, 9007: Sensor, 9008: Microphone, 9050: Icon, 9051: Information, 9052: Information, 9053: Information, 9054: Information, 9055: Hinge, 9101: Portable information terminal, 9102: Portable information terminal, 9103: Tablet terminal, 9200: Portable information terminal, 9201: Portable information terminal,

Claims

It comprises a first insulating layer, a second insulating layer, and a transistor. The transistor comprises a semiconductor layer, a third insulating layer, a first conductive layer, a second conductive layer, and a third conductive layer. The first conductive layer, the second conductive layer, and the second insulating layer are located on the first insulating layer. The second insulating layer is located between the first conductive layer and the second conductive layer. The semiconductor layer has a first region in contact with the upper surface of the first conductive layer, a second region in contact with the upper surface of the second conductive layer, and a third region located between the first region and the second region and located on the second insulating layer. The third insulating layer is in contact with the upper surface of the third region. The third conductive layer overlaps with the third region with the third insulating layer in between. The semiconductor layer has a metal oxide, The first insulating layer has the function of getting hydrogen, A semiconductor device wherein the second insulating layer has at least one of the functions of supplying oxygen and blocking oxygen. 　 In claim 1, The second insulating layer comprises a first layer and a second layer on the first layer. The first layer has a region located between the first conductive layer and the second layer, a region located between the second conductive layer and the second layer, and a region located between the first insulating layer and the second layer. A semiconductor device wherein the first layer and the second layer each have at least one of the functions of supplying oxygen and blocking oxygen. 　 In claim 1, A semiconductor device having hafnium oxide as the first insulating layer. 　 In claim 2, A semiconductor device in which one of the first layer and the second layer has silicon oxide and the other has aluminum oxide. 　 In claim 1, A semiconductor device comprising the first conductive layer and the second conductive layer, each having indium tin oxide. 　 In claim 1, A semiconductor device wherein the first conductive layer and the second conductive layer each contain nickel. 　 In claim 1, It has a fourth insulating layer, The first insulating layer is located on the fourth insulating layer, The semiconductor device comprises a fourth insulating layer having silicon nitride. 　 In any one of claims 1 to 7, The semiconductor device comprises a semiconductor layer having indium oxide. 　 It comprises a first insulating layer, a second insulating layer, a third insulating layer, and a transistor. The transistor has a semiconductor layer, a fourth insulating layer, a first conductive layer, a second conductive layer, and a third conductive layer. The first conductive layer and the second conductive layer are located on the first insulating layer. The semiconductor layer is located between the first conductive layer and the second conductive layer. The first side surface of the first conductive layer and the second side surface of the second conductive layer face each other. The semiconductor layer is in contact with the first side surface and the second side surface, The second insulating layer is in contact with the upper surface of the first conductive layer. The third insulating layer is in contact with the upper surface of the second conductive layer. The fourth insulating layer is in contact with the upper surface of the semiconductor layer, The third conductive layer overlaps the upper surface of the semiconductor layer with the fourth insulating layer in between. The semiconductor layer has a metal oxide, The first insulating layer has the function of getting hydrogen, A semiconductor device wherein the second insulating layer and the third insulating layer each have at least one of the functions of supplying oxygen and blocking oxygen. 　 In claim 9, The semiconductor layer has a first region in contact with the first side surface, a second region in contact with the second side surface, and a third region located between the first region and the second region and covering the upper surface of the first insulating layer. The fourth insulating layer has a fourth region facing the first side surface with the first region in between, a fifth region facing the second side surface with the second region in between, and a sixth region facing the upper surface of the first insulating layer with the third region in between. The first region and the fourth region are sandwiched between the first conductive layer and the third conductive layer. The second region and the fifth region are sandwiched between the second conductive layer and the third conductive layer in a semiconductor device. 　 In claim 9, The semiconductor device wherein the first insulating layer comprises hafnium and oxygen. 　 In claim 9, A semiconductor device having a second insulating layer and a third insulating layer, each comprising at least one of silicon and aluminum, and oxygen. 　 In claim 9, A semiconductor device wherein the first conductive layer and the second conductive layer each contain indium, tin, and oxygen. 　 In claim 9, It has a fifth insulating layer, The first insulating layer is located on the fifth insulating layer, The semiconductor device comprises a fifth insulating layer made of silicon and nitrogen. 　 In claim 9, It has a fifth insulating layer and a sixth insulating layer, The sixth insulating layer is located on the fifth insulating layer, The first insulating layer is located on the sixth insulating layer, The fifth insulating layer comprises silicon and nitrogen, The sixth insulating layer comprises silicon and oxygen, A semiconductor device wherein the second insulating layer and the third insulating layer are made of aluminum and oxygen. 　 In any one of claims 9 to 15, The semiconductor device comprises a semiconductor layer containing indium and oxygen.

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