Silicon carbide semiconductor device, method for manufacturing silicon carbide semiconductor device, and power conversion device

Abstract

The present disclosure relates to a silicon carbide semiconductor device comprising: a p-type protective layer below a gate trench that has a bottom surface reaching the inside of an n-type first semiconductor layer; a p-type first pillar region that has a lower impurity concentration than the protective layer and reaches the n-type first semiconductor layer provided in a lower layer portion of the semiconductor layer from the bottom portion of the p-type protective layer; and an n-type second pillar region provided in the semiconductor layer between adjacent first pillar regions, wherein the second pillar region includes an n-type first impurity region in contact with the first pillar region, and an n-type second impurity region provided apart from the first pillar region and having an impurity concentration higher than that of the first impurity region, and the second impurity region is provided from a position closer to the first semiconductor layer than the bottom portion of the protective layer to the first semiconductor layer.

Description

Silicon carbide semiconductor device, method for manufacturing a silicon carbide semiconductor device, power conversion device

[0001] This disclosure relates to silicon carbide semiconductor devices, and more particularly to trench-type silicon carbide semiconductor devices.

[0002] Silicon carbide semiconductor devices, which use silicon carbide as a material, can achieve lower on-resistance and higher breakdown voltage than silicon semiconductor devices, and are therefore expected to be used as power semiconductor devices. For example, Figure 11 of Patent Document 1 discloses a trench gate type MOSFET (Metal Oxide Semiconductor Field Effect Transistor).

[0003] The MOSFET has a superjunction (SJ) structure in which a p-type semiconductor region is formed below the trench, a second semiconductor pillar region is formed below that, and a first semiconductor pillar region is formed adjacent to the second semiconductor pillar region. The first semiconductor pillar region has a first region with a low density that is in contact with the second semiconductor pillar region and a second region with a high density that is spaced apart from the second semiconductor pillar region.

[0004] Japanese Patent Publication No. 2023-141553

[0005] Conventional MOSFETs can form deep p-type and n-type pillars by high-energy ion implantation. However, high-energy implantation leads to a wider distribution of impurities, which tends to increase the JFET (Junction Field Effect Transistor) resistance near the bottom of the p-type pillar. Increasing the concentration of n-type pillars is effective in reducing JFET resistance, but high impurity concentrations make it difficult for the depletion layer to spread within the region, resulting in a high junction electric field and a high electric field at the bottom of the pillar.

[0006] Furthermore, when the pillar has a high concentration, there is a problem that the pressure resistance is more likely to decrease when the charge balance of the pillar is disrupted due to variations in the n-type and p-type impurity concentrations during manufacturing, compared to when the pillar has a low concentration.

[0007] Furthermore, in SJ circuits, when a bias is applied, the drift layer is uniformly depleted from the boundary between the p-type and n-type pillars, causing a rapid decrease in gate-drain capacitance with respect to voltage. This makes it easier for noise to be generated from the gate electrode, leading to malfunctions in semiconductor devices.

[0008] This disclosure is made to solve the above-mentioned problems and aims to provide a silicon carbide semiconductor device that can reduce JFET resistance while suppressing the electric field near the bottom of the pillar, thereby achieving both reduced on-resistance and suppressed breakdown voltage drop, and further suppressing a rapid decrease in capacitance with respect to drain voltage.

[0009] The silicon carbide semiconductor device according to this disclosure comprises: a semiconductor layer provided on a first main surface of a silicon carbide semiconductor substrate of a first conductivity type; a first semiconductor region of a first conductivity type selectively provided in the upper part of the semiconductor layer; a second semiconductor region of a second conductivity type provided in contact with the first semiconductor region; a third semiconductor region of a second conductivity type provided in contact with the bottom surfaces of the first and second semiconductor regions; a plurality of gate trenches provided so as to penetrate the first and third semiconductor regions in the thickness direction, with their bottom surfaces reaching into the semiconductor layer; a first main electrode electrically connected to the first and second semiconductor regions; a second main electrode provided on a second main surface of the silicon carbide semiconductor substrate opposite to the first main surface; and below the gate trenches The semiconductor semiconductor comprises a protective layer of a second conductivity type, a first pillar region of the second conductivity type having a lower impurity concentration than the protective layer, extending from the bottom of the protective layer to a first semiconductor layer of the first conductivity type provided in the lower part of the semiconductor layer, and a second pillar region of the first conductivity type provided in the semiconductor layer between adjacent first pillar regions, wherein the second pillar region has a first impurity region of the first conductivity type in contact with the first pillar region, and a second impurity region of the first conductivity type provided at a distance from the first pillar region and having a higher impurity concentration than the first impurity region, and the second impurity region is provided from a position closer to the first semiconductor layer than the bottom of the protective layer to the first semiconductor layer.

[0010] The silicon carbide semiconductor device described herein suppresses the electric field near the bottom of the pillar while reducing the JFET resistance, thereby achieving both reduced on-resistance and suppressed breakdown voltage drop. Furthermore, it can suppress the rapid decrease in capacitance with respect to the drain voltage, thereby suppressing the generation of noise.

[0011] Figure 1 is a cross-sectional view showing the configuration of a trench gate type MOSFET according to Embodiment 1 of this disclosure. Figure 2 is a diagram showing the concentration profiles in the depth direction of the low concentration layer and the high concentration layer. Figure 3 is a diagram showing the concentration profiles in the horizontal direction of the low concentration layer and the high concentration layer. Figure 4 is a cross-sectional view showing the manufacturing method of a trench gate type MOSFET according to Embodiment 1 of this disclosure. Figure 5 is a cross-sectional view showing the manufacturing method of a trench gate type MOSFET according to Embodiment 1 of this disclosure. Figure 6 is a cross-sectional view showing the manufacturing method of a trench gate type MOSFET according to Embodiment 1 of this disclosure. Figure 7 is a cross-sectional view showing the manufacturing method of a trench gate type MOSFET according to Embodiment 1 of this disclosure. Figure 8 is a cross-sectional view showing the manufacturing method of a trench gate type MOSFET according to Embodiment 1 of this disclosure. Figure 9 is a cross-sectional view showing the manufacturing method of a trench gate type MOSFET according to Embodiment 1 of this disclosure. Figure 10 is a cross-sectional view showing the manufacturing method of a trench gate type MOSFET according to Embodiment 1 of this disclosure. Figure 11 is a cross-sectional view showing a modified example 1 of the manufacturing method of a trench gate type MOSFET according to Embodiment 1 of this disclosure. Figure 12 is a cross-sectional view showing a modified example 1 of the manufacturing method of a trench gate type MOSFET according to Embodiment 1 of this disclosure. Figure 13 is a cross-sectional view showing a modified example 1 of the method for manufacturing a trench gate type MOSFET according to Embodiment 1 of this disclosure. Figure 14 is a cross-sectional view showing a modified example 2 of the method for manufacturing a trench gate type MOSFET according to Embodiment 1 of this disclosure. Figure 15 is a cross-sectional view showing a modified example 2 of the method for manufacturing a trench gate type MOSFET according to Embodiment 1 of this disclosure. Figure 16 is a cross-sectional view showing a modified example 2 of the method for manufacturing a trench gate type MOSFET according to Embodiment 1 of this disclosure. Figure 17 is a cross-sectional view showing the configuration of a trench gate type MOSFET according to Embodiment 2 of this disclosure. Figure 18 is a cross-sectional view showing the configuration of a trench gate type MOSFET according to Embodiment 3 of this disclosure. Figure 19 is a diagram illustrating the implantation angle of gradient ion implantation. Figure 20 is a cross-sectional view showing the configuration of a trench gate type MOSFET according to Embodiment 4 of this disclosure. Figure 21 is a block diagram showing the configuration of a power conversion system to which the power conversion device of Embodiment 5 of this disclosure is applied.

[0012] <Introduction> The diagrams used in the following explanation are schematic representations, and the relative sizes and positions of the images shown in different diagrams are not necessarily accurately represented and may be changed as appropriate. In addition, in the following explanation, similar components are denoted by the same reference numerals, and their names and functions are also the same. Therefore, detailed explanations of them may be omitted.

[0013] Furthermore, in the following description, terms such as "top," "bottom," "side," "bottom," "front," and "back" may be used to indicate specific positions and directions. These terms are used for convenience to facilitate understanding of the embodiments and do not relate to the actual directions in which they are implemented.

[0014] Furthermore, the term "MOS" was historically used to describe a metal / oxide / semiconductor junction structure, and is believed to be an acronym for Metal-Oxide-Semiconductor. However, in field-effect transistors (hereinafter simply referred to as "MOS transistors") that have a MOS structure, the materials for the gate insulating film or gate electrode have been improved in recent years due to integration or improvements in manufacturing processes.

[0015] For example, in MOS transistors, polycrystalline silicon has been adopted as the gate electrode material instead of metal, primarily from the viewpoint of forming the source and drain in a self-aligned manner. Also, from the viewpoint of improving electrical properties, high dielectric constant materials are used as the gate insulating film material, but these materials are not necessarily limited to oxides.

[0016] Therefore, the term "MOS" is not necessarily limited to metal / oxide / semiconductor layered structures, and this specification does not assume such a limitation. In other words, in light of common technical knowledge, "MOS" here has a broader meaning that includes not only an abbreviation derived from its etymology, but also layered structures of conductors / insulators / semiconductors.

[0017] Furthermore, in the following description, the conductivity types of impurities are generally defined as n-type as the "first conductivity type" and p-type as the "second conductivity type," but the reverse definition is also acceptable. In addition, while MOSFETs are used as examples in the following description, this disclosure is also applicable to insulated-gate bipolar transistors (IGBTs).

[0018] <Embodiment 1> <Device Configuration> Figure 1 is a cross-sectional view showing the configuration of a trench gate type MOSFET 100 of Embodiment 1 of the silicon carbide semiconductor device according to the present disclosure. As shown in Figure 1, the MOSFET 100 has a semiconductor layer 15 provided on an n-type silicon carbide semiconductor substrate 1, and has a plurality of gate trenches 8 provided within the semiconductor layer 15 that extend in a first direction (the depth direction of the paper in Figure 1).

[0019] The semiconductor layer 15 is composed of multiple semiconductor layers and impurity regions. Specifically, the semiconductor layer 15 comprises an n-type drift layer 9 provided on one main surface (first main surface) of the silicon carbide semiconductor substrate 17, an n-type pillar region 4 provided on the drift layer 9, and a p-type body region 5 provided on the pillar region 4. The upper part of the body region 5 has an n-type source region 6 in contact with the side surface of the gate trench 8 and a p-type body contact region 7 in contact with the source region 6.

[0020] The gate trench 8 has a gate insulating film 10 provided on the inner surface of the trench that extends from the outermost surface of the semiconductor layer 15, i.e., the outermost surface of the body region 5, through the source region 6 and the body region 5 to the pillar region 4, and a gate electrode 11 that fills the trench in which the gate insulating film 10 is formed.

[0021] An interlayer insulating film 14 is selectively formed on the outermost surface of the semiconductor layer 15 so as to cover the gate trench 8. A source electrode 12 is formed so as to cover the area where the interlayer insulating film 14 is not formed and the surface of the interlayer insulating film 14, and is in contact with the source region 6 and the body contact region 7. A drain electrode 13 is formed on the other main surface of the silicon carbide semiconductor substrate 17.

[0022] The semiconductor layer 15 is formed by epitaxially growing a silicon carbide semiconductor substrate 17, and the drift layer 9 is a semiconductor layer having an n-type impurity concentration lower than that of the silicon carbide semiconductor substrate 17.

[0023] The body contact region 7 is an impurity region having a p-type impurity concentration higher than that of the body region 5.

[0024] The source electrode 12 is a silicide of a metal such as Ni (nickel) or Ti (titanium) and the semiconductor layer 15, and forms an ohmic contact with the source region 6 and the body contact region 7. The drain electrode 13 is a metal electrode such as Ni.

[0025] In the MOSFET 100 of Embodiment 1, a p-type protection layer 2 is provided on the bottom surface of the gate trench 8, and a p-type pillar region 3 (first pillar region) is provided from the bottom surface of the protection layer 2 to the surface of the drift layer 9. The pillar region 3 is an impurity region having a p-type impurity concentration higher than that of the protection layer 2. And between adjacent pillar regions 3, there is an n-type pillar region 4 (second pillar region), and the pillar region 4 includes an n-type low concentration region 4a (first impurity region) in contact with the pillar region 3 and an n-type high concentration region 4b (second impurity region) separated from the pillar region 3. The high concentration region 4b is formed from a position closer to the drift layer 9 than the bottom of the protection layer 2 to the drift layer 9, and is composed of an n-type high concentration region 4b having an n-type impurity concentration higher than that of the low concentration region 4a.

[0026] Next, the impurity concentrations of each semiconductor layer and impurity region will be described. The n-type impurity concentration of the drift layer 9 is 1.0×10 １４ / cm ３ ~1.0×10 １７ / cm ３ and is set based on the breakdown voltage of the silicon carbide semiconductor device and the like.

[0027] The p-type impurity concentration of the body region 5 is 1.0×10 １４ / cm ３ ~1.0×10 １８ / cm ３ is set to. The n-type impurity concentration of the source region 6 is 1.0×10 １８ / cm３ ~1.0×10 ２１ / cm ３ is.

[0028] The p-type impurity concentration in the body contact region 7 is 1.0×10 １８ / cm ３ ~1.0×10 ２１ / cm ３ and to reduce the contact resistance with the source electrode 12, the p-type impurity concentration is made higher than that in the body region 5.

[0029] The p-type impurity concentration in the protective layer 2 is preferably 1.0×10 １４ / cm ３ ~1.0×10 ２０ / cm ３ and the concentration profile may not be uniform.

[0030] The impurity concentrations in the low-concentration region 4a and the high-concentration region 4b that make up the pillar region 4 are higher than the impurity concentration in the drift layer 9 and lower than the highest impurity concentration in the protective layer 2. And the impurity concentration in the high-concentration region 4b is higher than the impurity concentration in the low-concentration region 4a.

[0031] There may be a sharp impurity concentration difference at the boundary between the low-concentration region 4a and the high-concentration region 4b, or the impurity concentration may change gently. The concentration profile in the case where the impurity concentration changes gently is shown in FIG. 2.

[0032] FIG. 2 shows the concentration profile in the depth direction of the low-concentration region 4a and the high-concentration region 4b. The horizontal axis represents the distance in the depth direction, and the vertical axis represents the impurity concentration. Thus, the low-concentration region 4a has a substantially uniform impurity concentration, but the high-concentration region 4b has a profile in which the concentration gradually increases and eventually becomes uniform.

[0033] The position where the impurity concentration changes abruptly from the low-concentration region 4a to the high-concentration region 4b, or the position where the concentration gradient of the impurity concentration gradually starts to change with respect to the distance from the junction position between the pillar region 3 and the pillar region 4 as shown by the broken line in FIG. 2, is defined as the boundary between the low-concentration region 4a and the high-concentration region 4b.

[0034] Furthermore, if the impurity concentration increases gradually from the junction between pillar region 3 and pillar region 4 through the low-concentration region 4a to the side surface of the high-concentration region 4b, the boundary between the low-concentration region 4a and the high-concentration region 4b is set at a position where the impurity concentration is half of the peak value of the high-concentration region 4b. This is shown in Figure 3.

[0035] Figure 3 shows the horizontal concentration profiles of the low-concentration region 4a and the high-concentration region 4b, with the horizontal axis representing horizontal distance and the vertical axis representing impurity concentration. As can be seen, the impurity concentration increases gradually in both the low-concentration region 4a and the high-concentration region 4b, making the boundary difficult to discern. Therefore, as shown by the dashed line in Figure 3, the boundary is defined as the position where the impurity concentration is approximately half of the peak value of the high-concentration region 4b.

[0036] <Operation> Next, the operation of the MOSFET 100 will be briefly explained. In Figure 1, when a voltage above the threshold voltage is applied to the gate electrode 11, a region with inverted conductivity, i.e., an n-type channel, is formed in the body region 5 along the side surface of the gate trench 8. As a result, a current path of the same conductivity is formed between the source electrode 12 and the drain electrode 13, and the main current flows. This state, when a voltage above the threshold voltage is applied to the gate electrode 11, is the ON state of the MOSFET 100.

[0037] On the other hand, when a voltage below the threshold voltage is applied to the gate electrode 11, no channel is formed in the body region 5, and therefore no current path is formed as in the ON state. As a result, even if a voltage is applied between the drain electrode 13 and the source electrode 12, almost no current flows from the drain electrode 13 to the source electrode 12. This state, where the voltage of the gate electrode 11 is below the threshold voltage, is the OFF state of the MOSFET 100. In this way, the MOSFET 100 can switch between the ON state and the OFF state by controlling the voltage applied to the gate electrode 11.

[0038] <Manufacturing Method> The manufacturing method of the MOSFET 100 will be explained below using Figures 4 to 10, which are cross-sectional views showing the manufacturing process in order.

[0039] First, a silicon carbide semiconductor substrate 17 on which an n-type drift layer 9 is formed is prepared in the process shown in Figure 4. More specifically, an n-type drift layer 9 is formed on the silicon carbide semiconductor substrate 17 by epitaxial growth. The thickness of this drift layer 9 varies depending on the breakdown voltage of the MOSFET 100; if the breakdown voltage is 10 kV or less, it is several μm to several tens of μm, and the n-type impurity concentration is 1.0 × 10⁻⁶. １４ / cm ３ ~1.0 x 10 １７ / cm ３ It is formed in such a way.

[0040] Next, in the process shown in Figure 5, a source region 6, a body contact region 7, and a body region 5 are formed in the upper part of the drift layer 9 by ion implantation. When forming n-type impurity regions, ions such as N (nitrogen) or P (phosphorus) are implanted as donors, and when forming p-type impurity regions, ions such as Al (aluminum) or B (boron) are implanted as acceptors.

[0041] In this case, the n-type impurity concentration in source region 6 is 1.0 × 10⁻⁶. １８ / cm ３ ~1.0 x 10 ２１ / cm ３ The p-type impurity concentration in the body contact region 7 is 1.0 × 10⁻⁶. １８ / cm ３ ~1.0 x 10 ２１ / cm ３ The p-type impurity concentration in body region 5 is 1.0 × 10⁻⁶. １４ / cm ３ ~1.0 x 10 １８ / cm ３ Ion implantation is performed in such a manner.

[0042] Furthermore, the order in which each impurity region is formed does not matter, and all or some of the impurity regions can be formed by epitaxial growth instead of ion implantation.

[0043] Next, in the process shown in Figure 6, a trench 81 is formed by reactive ion etching (RIE) from the surface of the source region 6, penetrating the body region 5 and reaching the drift layer 9. Subsequently, a pillar region 3 is formed by ion implantation of p-type impurities into the bottom surface of the trench 81. Then, a protective layer 2 is formed by further ion implantation of p-type impurities into the upper layer of the pillar region 3. The formation of the pillar region 3 and the protective layer 2 can be carried out using an implantation mask 16 with an opening in the region corresponding to the trench 81, as shown in Figure 6. The energy of ion implantation to form impurity regions at deep positions in the drift layer 9, such as the pillar region 3, is approximately several hundred keV to 10 MeV.

[0044] Next, in the process shown in Figure 7, a first gradient ion implantation of n-type impurities is performed with an inclination toward the side wall of the trench 81, thereby forming a low-concentration region 4a of n-type impurities with a higher impurity concentration than the drift layer 9.

[0045] Next, in the process shown in Figure 8, a second gradient ion implantation is performed with higher energy than that used for forming the low-concentration region 4a, thereby forming a low-concentration region 4a near the bottom of the pillar region 3, and a high-concentration region 4b with a higher impurity concentration than the low-concentration region 4a at a position away from the pillar region 3, thereby forming the pillar region 4. Then, by rotating the silicon carbide semiconductor substrate 17 by 180° and performing the first gradient ion implantation in the process shown in Figure 7 and the second gradient ion implantation in the process shown in Figure 8, pillar regions 4 are also formed on the outside of the side walls of the opposing trenches.

[0046] The formation of pillar region 4 reduces the thickness of the drift layer 9, causing the bottom surfaces of pillar region 3, low-concentration region 4a, and high-concentration region 4b to come into contact with the drift layer 9.

[0047] When inclined injection, the injection mask 16 shown in Figure 6 may be used or removed. In either case, it is preferable that the injection angle θ of the inclined injection be equal to or smaller than the angle between the diagonal line from the upper end of one side of the injection mask 16 or trench 81 to the lower end of the opposing side of the gate trench 8 and the side. This allows for the formation of pillar regions 4 around the gate trench 8, protective layer 2, and pillar region 3.

[0048] Figure 9 is a diagram illustrating the injection angle θ described above, and corresponds to Figure 7. As shown in Figure 9, the injection angle should be within the range of the angle θ between the diagonal line shown by the dashed line and the side surface of the trench 81.

[0049] Next, in the process shown in Figure 10, a gate insulating film 10 is formed to cover the inner surface, i.e., the bottom and sides, of the trench 81, and a gate electrode 11 is formed to fill the trench 81 into which the gate insulating film 10 has been formed.

[0050] Subsequently, after removing the gate electrode 11 and gate insulating film 10 from the surface of the semiconductor layer 15, an interlayer insulating film 14 is formed to cover the gate electrode 11, thereby forming a gate trench 8. Furthermore, a source electrode 12 is formed so as to be in contact with the surface of the source region 6 and the surface of the body contact region 7, and a drain electrode 13 is formed on the back surface (second main surface) of the silicon carbide semiconductor substrate 17, thereby obtaining the MOSFET 100 shown in Figure 1.

[0051] The interlayer insulating film 14 may be formed on the surface of the semiconductor layer 15 as shown in Figure 1, or it may be embedded in the gate trench 8.

[0052] As described above, the manufacturing method makes it possible to form a locally high-concentration region 4b at a depth deeper than the protective layer 2 and separated from the pillar region 3.

[0053] <Modification of Manufacturing Method 1> The pillar region 3, pillar region 4 and protective layer 2 can also be formed in advance by ion implantation when forming the semiconductor layer 15. In this case, after the protective layer 2 is formed, the semiconductor layer is epitaxially grown on the protective layer 2 and then the trench 81 is formed.

[0054] This method will be explained using Figures 11 to 13. Figure 11 shows the formation of pillar regions 3 and protective layers 2 by ion implantation on a silicon carbide semiconductor substrate 17 on which an n-type drift layer 9 has been formed. Alternatively, pillar regions 4 may be formed by ion implantation of n-type impurities into the drift layer 9 beforehand, and then pillar regions 3 and protective layers 2 may be formed by ion implantation after patterning. This process is the same as the process of ion implanting p-type impurities into the bottom surface of the trench 81 shown in Figure 6, but the thickness of the drift layer 9 is thinner than that of the drift layer 9 shown in Figure 4.

[0055] Next, in the process shown in Figure 12, a semiconductor layer 41 is formed on the protective layer 2 by epitaxial growth. The n-type impurity concentration of the semiconductor layer 41 is the same as that of the drift layer 9. As a result of this process, the combined thickness of the drift layer 9 and the semiconductor layer 41 becomes the same as that of the drift layer 9 shown in Figure 4.

[0056] Next, in the process shown in Figure 13, a source region 6, a body contact region 7, and a body region 5 are formed in the upper part of the semiconductor layer 41 by ion implantation. The ion implantation conditions are the same as those described in the process shown in Figure 5. Subsequently, a trench 81 is formed by RIE, penetrating from the surface of the source region 6 through the body region 5 and reaching the semiconductor layer 41.

[0057] <Modification of Manufacturing Method 2> Pillar regions 3 and 4 can also be formed by repeating ion implantation and epitaxial growth of the semiconductor layer two or more times. This method will be explained using Figures 14 to 16.

[0058] Figure 14 shows a silicon carbide semiconductor substrate 17 on which an n-type drift layer 9 is formed. In this substrate, p-type impurities are ion-implanted into the surface of the epitaxially grown drift layer 9 to form pillar regions 31. Note that the thickness of the drift layer 9 is thinner than that of the drift layer 9 shown in Figure 4.

[0059] Next, in the process shown in Figure 15, an n-type semiconductor layer 41 is formed on the drift layer 9 by a second epitaxial growth, and p-type impurities are ion-implanted into the semiconductor layer 41 to form pillar regions 32. In this ion implantation, the pillar regions 32 are formed so that they reach the pillar regions 31. The thickness of the semiconductor layer 41 is thinner than that of the drift layer 9 shown in Figure 4.

[0060] Next, in the process shown in Figure 16, an n-type semiconductor layer 42 is formed on the semiconductor layer 41 by a third epitaxial growth, and p-type impurities are ion-implanted into the semiconductor layer 42 to form pillar regions 33. In this ion implantation, pillar regions 33 are formed so that they reach pillar region 32, and pillar region 3 is formed by pillar regions 31, 32, and 33. Alternatively, ion implantation of n-type impurities may be performed with each epitaxial growth to form pillar regions 4 in advance, and pillar region 3 may be formed by ion implantation after patterning. The total thickness of the drift layer 9, semiconductor layer 41, and semiconductor layer 42 is the same as that of the drift layer 9 shown in Figure 4. Subsequently, a protective layer 2 is formed by ion-implanting p-type impurities into the upper part of pillar region 3. Furthermore, a source region 6, a body contact region 7, and a body region 5 are formed in the upper part of the semiconductor layer 42 by ion implantation. The ion implantation conditions are the same as those described in the process shown in Figure 5. Subsequently, a trench 81 is formed by RIE, penetrating the body region 5 from the surface of the source region 6 to the semiconductor layer 41, and a protective layer 2 is formed on the upper part of the pillar region 33 by ion implantation of p-type impurities into the bottom surface of the trench 81.

[0061] <Effects> In the MOSFET 100 of Embodiment 1 described above, by providing a high-concentration region 4b, the JFET resistance near the bottom of the pillar region 3 is reduced, thereby reducing the on-resistance.

[0062] Furthermore, by forming the high-concentration region 4b locally at a location away from the pillar region 3, it is possible to avoid an increase in the electric field near the bottom of the pillar region 3 and a decrease in the breakdown voltage of the semiconductor device.

[0063] Thus, with MOSFET 100, it is possible to achieve both a reduction in on-resistance and suppression of voltage degradation, thereby improving the trade-off between on-resistance and voltage degradation.

[0064] Furthermore, when the MOSFET 100 is in the off state and a high bias is applied, pillar regions 3 and 4 become depleted. However, since the high-concentration region 4b has a higher impurity concentration than the surrounding region, the depletion layer spreads less and depletion becomes less likely. This suppresses a rapid decrease in gate-drain capacitance with respect to drain voltage, thereby suppressing noise generation.

[0065] <Embodiment 2> <Device Configuration> Figure 17 is a cross-sectional view showing the configuration of a trench gate type MOSFET 200 of Embodiment 2 of the silicon carbide semiconductor device according to the present disclosure. As shown in Figure 17, in addition to the configuration of the MOSFET 100 shown in Figure 1, the MOSFET 200 includes a high-concentration region 4c (third impurity region) in a part of the pillar region 4 that has a higher n-type impurity concentration than the drift layer 9. The high-concentration region 4c has a bottom surface that is at a depth that does not reach the bottom surface of the protective layer 2 from the bottom surface of the body region 5.

[0066] <Manufacturing Method> The manufacturing method for MOSFET 200 will be described below, with references to diagrams illustrating the manufacturing method for MOSFET 100 as appropriate.

[0067] First, a silicon carbide semiconductor substrate 17 with an n-type drift layer 9 formed on it is prepared in the process shown in Figure 4. The n-type impurity concentration in the drift layer 9 is the same as that of MOSFET 100. Next, n-type impurities are ion-implanted into the upper part of the drift layer 9 to form a high-concentration region 4c. After that, as explained using Figure 5, a source region 6, a body contact region 7, and a body region 5 are formed in the drift layer 9 above the high-concentration region 4c by ion implantation. The conditions for these ion implantations are the same as those for MOSFET 100.

[0068] Alternatively, following the manufacturing method in Embodiment 1, as explained with reference to Figure 6, a trench 81 is formed, and a protective layer 2 and pillar region 3 are formed by ion implantation of p-type impurities through the trench 81. Then, n-type impurities are ion implanted into the drift layer 9 of the mesa portion between the trenches 81 to form a high-concentration region 4c.

[0069] Subsequently, as explained with reference to Figure 7, a first gradient ion implantation of n-type impurities is performed through the side wall of the trench 81 to form a low-concentration region 4a.

[0070] Next, as explained using Figure 8, by performing a second gradient ion implantation with a higher implantation energy than that used for the formation of the low-concentration region 4a, a low-concentration region 4a is formed near the bottom of the pillar region 3, and a high-concentration region 4b with a higher impurity concentration than the low-concentration region 4a is formed at a location away from the pillar region 3. This forms a pillar region 4 having a low-concentration region 4a, a high-concentration region 4b, and a high-concentration region 4c.

[0071] In this method, since gradient ion implantation is performed on each side of the trench 81, the high-concentration region 4c receives more implantations than the low-concentration region 4a and the high-concentration region 4b, resulting in a higher impurity concentration.

[0072] <Effects> In the MOSFET 200 of Embodiment 2 described above, by providing a high-density region 4c having a depth that does not reach the bottom surface of the protective layer 2 from the bottom surface of the body region 5, the JFET resistance between the body region 5 and the protective layer can be reduced, and the JFET resistance between the pillar region 4 and the adjacent protective layer 2 can also be reduced.

[0073] Furthermore, when the MOSFET 200 is in the off state and a high bias is applied, the pillar region 3 becomes depleted, causing the electric field to concentrate on the bottom surface of the protective layer 2. However, by forming the high-concentration region 4c at a shallower position than the bottom surface of the protective layer 2, where a high electric field is likely to occur, the concentration of the electric field on the protective layer 2 can be suppressed, and a decrease in the breakdown voltage of the semiconductor device can be avoided.

[0074] Thus, with MOSFET 200, it is possible to achieve both a reduction in on-resistance and suppression of voltage drop, thereby improving the trade-off between on-resistance and voltage drop.

[0075] <Embodiment 3> <Device Configuration> Figure 18 is a cross-sectional view showing the configuration of a trench gate type MOSFET 300 of Embodiment 3 of the silicon carbide semiconductor device according to the present disclosure. As shown in Figure 18, in addition to the configuration of the MOSFET 100 shown in Figure 1, the MOSFET 300 includes a low-concentration region 4d (fourth impurity region) in which a part of the pillar region 4 has a lower n-type impurity concentration than the low-concentration region 4a. The low-concentration region 4d is formed to be at the same height as the high-concentration region 4b and to be in contact with the side surface of the high-concentration region 4b and the side surface of the pillar region 3.

[0076] Furthermore, the configuration is not limited to that shown in Figure 18. In addition to the MOSFET 200 configuration shown in Figure 17, a configuration with a low-concentration region 4d is also possible.

[0077] <Manufacturing Method> The manufacturing method for MOSFET 300 will be described below, with references to diagrams illustrating the manufacturing method for MOSFET 100 as appropriate.

[0078] After going through the process described with reference to Figures 4 to 7, as described with reference to Figure 8, a third gradient ion implantation is performed in which the amount of n-type impurities implanted when forming the high-concentration region 4b is lower than the amount of ions implanted when forming the low-concentration region 4a, and the implantation angle θ is set to the angle defined by the following formula (1), thereby forming a low-concentration region 4d between the high-concentration region 4b and the pillar region 3.

[0079]

[0080] In the above formula (1), Wm is the distance between adjacent trenches, dtr is the depth of the trench, and dp is the sum of the depths of the protective layer 2 and the pillar region 4. Figure 19 is a diagram with the distance Wm, depth dtr, and depth dp written on it.

[0081] Furthermore, the low-concentration region 4d can also be formed by ion implantation. That is, as explained with reference to Figure 11, after forming pillar regions 3 and protective layers 2 in the n-type drift layer 9 by ion implantation, a continuous low-concentration region 4d is formed between the pillar regions 3 by ion implantation, and then a high-concentration region 4b is formed by selectively adding n-type impurities to the continuous low-concentration region 4d by ion implantation. After that, the trench 81 is formed through the process explained with reference to Figures 12 and 13.

[0082] <Effects> In the MOSFET 300 of Embodiment 3 described above, by providing a low-concentration region 4d between the high-concentration region 4b and the pillar region 3, the n-type impurity concentration at the boundary between the high-concentration region 4b and the pillar region 3 can be reduced, thereby reducing the n-type impurity concentration implanted into the pillar region 3 during ion implantation and suppressing variations in the effective impurity concentration of the pillar region 3.

[0083] The device's breakdown voltage is maximized when the charges in pillar region 3 and pillar region 4 are equal, i.e., when the charge balance is achieved. However, in actual semiconductor devices, manufacturing variations can cause the pillar concentration to deviate from the design value or become non-uniform, resulting in a higher proportion of n-type impurities in pillar region 4 or a higher proportion of p-type impurities in pillar region 3. This causes variations in the charge balance, but by providing a low-concentration region 4d, the impurity concentration in pillar region 3 stabilizes, making it easier to maintain the desired carrier density and thus easier to achieve a charge balance between pillar region 3 and pillar region 4. This increases the robustness of the breakdown voltage against pillar concentration.

[0084] <Embodiment 4> <Device Configuration> Figure 20 is a cross-sectional view showing the configuration of a trench gate type MOSFET 400 of Embodiment 4 of the silicon carbide semiconductor device according to the present disclosure. As shown in Figure 20, in addition to the configuration of the MOSFET 100 shown in Figure 1, the pillar region 3 has a configuration that includes a pillar impurity region 3a (first pillar impurity region) having a lower p-type impurity concentration than the protective layer 2, and a pillar impurity region 3b (second pillar impurity region) having a lower p-type impurity concentration than the pillar impurity region 3a. The pillar impurity region 3b is formed from the bottom surface of the pillar impurity region 3a, which is closer to the drift layer 9 than the upper surface of the high-concentration region 4b, to the drift layer 9.

[0085] Furthermore, the configuration is not limited to that shown in Figure 20. In addition to the configurations of MOSFET 200 shown in Figure 17 or MOSFET 300 shown in Figure 18, the pillar region 3 can also be configured to include a pillar impurity region 3a and a pillar impurity region 3b.

[0086] <Manufacturing Method> The manufacturing method for MOSFET 400 will be described below, with references to diagrams illustrating the manufacturing method for MOSFET 100 as appropriate.

[0087] After the process described using Figures 4 to 6, as described using Figure 7, when forming the pillar region 3 by ion implantation of p-type impurities into the bottom surface of the trench 81, the amount of ion implantation in the region deeper than the high-concentration region 4b is made smaller than the amount of ion implantation in the shallower region, thereby forming the pillar impurity region 3b at a position lower than the upper surface of the high-concentration region 4b. Subsequently, the pillar region 3 is formed by ion implantation to create a pillar impurity region 3a on top of the pillar impurity region 3b.

[0088] <Effects> In the MOSFET 400 of Embodiment 4 described above, the JFET resistance around the pillar region can be reduced by lowering the p-type impurity concentration in the pillar impurity region 3b, which corresponds to the bottom of the pillar region 3.

[0089] <Modification> In embodiments 1 to 4 described above, the protective layer 2 was located at the bottom of the gate trench 8 and was in a floating state. However, the protective layer 2 may also be electrically connected to the source electrode 12.

[0090] As a result, when MOSFETs 100-400 are in the off state and a high bias is applied, the depletion layer can more easily follow the bias change, the protective effect on the bottom surface of the gate trench 8 is enhanced, and the electric field strength applied to the gate insulating film can be reduced. Furthermore, the switching speed is improved because the feedback capacitance is reduced, and the voltage drop due to displacement current in the protective layer 2 is reduced, improving breakdown withstand capability such as short-circuit withstand capability.

[0091] <Embodiment 5> This embodiment applies the silicon carbide semiconductor device described in Embodiments 1 to 4 above to a power conversion device. The silicon carbide semiconductor device described in Embodiments 1 to 4 is not limited to a specific power conversion device, but below, as Embodiment 5, the case in which it is applied to a three-phase inverter will be described.

[0092] Figure 21 is a block diagram showing the configuration of a power conversion system to which the power conversion device according to this embodiment is applied.

[0093] The power conversion system shown in Figure 21 consists of a power supply 800, a power conversion device 600, and a load 700. The power supply 800 is a DC power supply and supplies DC power to the power conversion device 600. The power supply 800 can be made up of various components, for example, a DC grid, a solar cell, or a storage battery. It may also be made up of a rectifier circuit or AC / DC converter connected to an AC grid. Alternatively, the power supply 800 may be made up of a DC / DC converter that converts DC power output from a DC grid into a predetermined power.

[0094] The power converter 600 is a three-phase inverter connected between the power supply 800 and the load 700. It converts the DC power supplied from the power supply 800 into AC power and supplies the AC power to the load 700. As shown in Figure 21, the power converter 600 includes a main conversion circuit 601 that converts DC power into AC power and outputs it, a drive circuit 602 that outputs drive signals to drive each switching element of the main conversion circuit 601, and a control circuit 603 that outputs control signals to the drive circuit 602 to control the drive circuit 602.

[0095] Load 700 is a three-phase motor driven by AC power supplied from power converter 600. Note that load 700 is not limited to a specific application; it is a motor installed in various electrical devices, such as hybrid vehicles, electric vehicles, railway vehicles, elevators, or air conditioning equipment.

[0096] The details of the power converter 600 are described below. The main conversion circuit 601 is equipped with switching elements and freewheeling diodes (not shown), and by switching the switching elements, it converts the DC power supplied from the power supply 800 into AC power and supplies it to the load 700. There are various specific circuit configurations for the main conversion circuit 601, but the main conversion circuit 601 according to this embodiment is a two-level three-phase full-bridge circuit and can be composed of six switching elements and six freewheeling diodes antiparallel to each switching element. Each switching element of the main conversion circuit 601 is a silicon carbide semiconductor device according to any of the embodiments 1 to 4 described above. The six switching elements are connected in series in pairs to form upper and lower arms, and each upper and lower arm constitutes each phase (U phase, V phase, W phase) of the full-bridge circuit. The output terminals of each upper and lower arm, i.e., the three output terminals of the main conversion circuit 601, are connected to the load 700.

[0097] The drive circuit 602 generates drive signals to drive the switching elements of the main conversion circuit 601 and supplies them to the control electrodes of the switching elements of the main conversion circuit 601. Specifically, according to the control signal from the control circuit 603, which will be described later, it outputs drive signals to turn on the switching elements and drive signals to turn off the switching elements to the control electrodes of each switching element. When the switching elements are kept in the ON state, the drive signal is a voltage signal (ON signal) that is greater than or equal to the threshold voltage of the switching elements, and when the switching elements are kept in the OFF state, the drive signal is a voltage signal (OFF signal) that is less than or equal to the threshold voltage of the switching elements.

[0098] The control circuit 603 controls the switching elements of the main converter circuit 601 so that the desired power is supplied to the load 700. Specifically, it calculates the time (on time) that each switching element of the main converter circuit 601 should be in the ON state based on the power to be supplied to the load 700. For example, the main converter circuit 601 can be controlled by PWM control, which modulates the on time of the switching elements according to the voltage to be output. The control circuit 603 then outputs a control command (control signal) to the drive circuit 602 so that an ON signal is output to the switching elements that should be in the ON state at each point in time, and an OFF signal is output to the switching elements that should be in the OFF state. The drive circuit 602 outputs an ON signal or an OFF signal as a drive signal to the control electrode of each switching element according to this control signal.

[0099] In the power conversion device according to this embodiment, a silicon carbide semiconductor device according to any of Embodiments 1 to 4 is applied as the switching element of the main conversion circuit 601, thereby achieving both a reduction in on-resistance and suppression of a decrease in breakdown voltage, and improving the trade-off between on-resistance and breakdown voltage.

[0100] Furthermore, when a high bias is applied while the silicon carbide semiconductor device is off, pillar regions 3 and 4 become depleted. However, since the high-concentration region 4b has a higher impurity concentration than the surrounding region, the depletion layer spreads less and is less prone to depletion. This suppresses the rapid decrease in gate-drain capacitance with respect to drain voltage, thereby suppressing noise generation.

[0101] In this embodiment, a two-level three-phase inverter was used as an example, but the invention is not limited to this and can be applied to various power conversion devices. In this embodiment, a two-level power conversion device is used, but a three-level or multi-level power conversion device may also be used, and when supplying power to a single-phase load, it can be applied to a single-phase inverter. Furthermore, when supplying power to a DC load, it can also be applied to a DC / DC converter or an AC / DC converter.

[0102] Furthermore, the aforementioned load is not limited to electric motors; for example, it can be used as a power supply for electrical discharge machining equipment, laser processing machines, induction cookers, or non-contact power supply systems. It can also be used as a power conditioner for solar power generation systems and energy storage systems.

[0103] Although this disclosure has been described in detail, the above description is illustrative in all respects and the disclosure is not limited thereto. It is understood that countless variations not illustrated may be conceivable without falling outside the scope of this disclosure.

[0104] Furthermore, within the scope of this disclosure, it is possible to freely combine each embodiment, or to modify or omit each embodiment as appropriate.

Claims

1. A semiconductor layer provided on a first main surface of a silicon carbide semiconductor substrate of a first conductivity type; a first semiconductor region of a first conductivity type selectively provided in the upper part of the semiconductor layer; a second semiconductor region of a second conductivity type provided in contact with the first semiconductor region; a third semiconductor region of a second conductivity type provided in contact with the bottom surfaces of the first and second semiconductor regions; a plurality of gate trenches provided so as to penetrate the first and third semiconductor regions in the thickness direction, with their bottom surfaces reaching into the semiconductor layer; a first main electrode electrically connected to the first and second semiconductor regions; a second main electrode provided on a second main surface of the silicon carbide semiconductor substrate opposite to the first main surface; a protective layer of a second conductivity type provided below the gate trenches; a first pillar region of a second conductivity type having a lower impurity concentration than the protective layer, extending from the bottom of the protective layer to the first semiconductor layer of a first conductivity type provided in the lower part of the semiconductor layer. A silicon carbide semiconductor device comprising at least a second pillar region of a first conductivity type provided in the semiconductor layer between adjacent first pillar regions, wherein the second pillar region has a first impurity region of a first conductivity type in contact with the first pillar region, and a second impurity region of a first conductivity type provided at a distance from the first pillar region and having a higher impurity concentration than the first impurity region, and the second impurity region is provided from a position closer to the first semiconductor layer than the bottom of the protective layer to the first semiconductor layer.

2. The silicon carbide semiconductor device according to claim 1, wherein the second pillar region further comprises a third impurity region of a first conductivity type having a higher impurity concentration than the first semiconductor layer, and the third impurity region has a bottom surface that does not reach the bottom surface of the protective layer from the bottom surface of the third semiconductor region.

3. The silicon carbide semiconductor device according to claim 1 or 2, wherein the second pillar region further comprises a third impurity region of a first conductivity type having a lower impurity concentration than the first impurity region, and the third impurity region is provided so as to be in contact with the side surface of the second impurity region and the side surface of the first pillar region.

4. The silicon carbide semiconductor device according to any one of claims 1 to 3, wherein the first pillar region comprises a first pillar impurity region of a second conductivity type having a lower impurity concentration than the protective layer, and a second pillar impurity region of a second conductivity type having a lower impurity concentration than the first pillar impurity region, and the second pillar impurity region is provided from the bottom surface of the first pillar impurity region, which is closer to the first semiconductor layer than the upper surface of the second impurity region, to the first semiconductor layer.

5. The silicon carbide semiconductor device according to any one of claims 1 to 4, wherein the protective layer is electrically connected to the first main electrode.

6. A method for manufacturing a silicon carbide semiconductor device according to claim 1, comprising: (a) forming a trench for the gate trench, and then ion implanting a second conductivity type impurity into the bottom surface of the trench to form the protective layer and the first pillar region; (b) after step (a), forming the first impurity region by first gradient ion implantation of the first conductivity type impurity through the side wall of the trench; and (c) after step (b), forming the second impurity region by second gradient ion implantation of the first conductivity type impurity through the side wall of the trench, wherein the second gradient ion implantation uses a higher implantation energy than the first gradient ion implantation.

7. A method for manufacturing a silicon carbide semiconductor device according to claim 3, comprising: (a) forming a trench for the gate trench, and then ion implanting a second conductivity type impurity into the bottom surface of the trench to form the protective layer and the first pillar region; (b) after step (a), forming the first impurity region by first gradient ion implantation of the first conductivity type impurity through the side wall of the trench; (c) after step (b), forming the second impurity region by second gradient ion implantation of the first conductivity type impurity through the side wall of the trench; and (d) after step (c), forming the third impurity region by third gradient ion implantation of the first conductivity type impurity through the side wall of the trench, wherein the third gradient ion implantation forms the third impurity region with a smaller ion implantation amount than the second gradient ion implantation.

8. A power conversion device comprising: a silicon carbide semiconductor device according to any one of claims 1 to 5, a main conversion circuit that converts and outputs input power; a drive circuit that outputs a drive signal to the silicon carbide semiconductor device for driving the silicon carbide semiconductor device; and a control circuit that outputs a control signal to the drive circuit for controlling the drive circuit.

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