Semiconductor device

Abstract

Provided is a semiconductor device comprising: gate-adjacent mesa parts each provided in contact with any of gate trench parts inside a semiconductor substrate; and inter-dummy mesa parts each sandwiched between two dummy trench parts inside the semiconductor substrate. The inter-dummy mesa parts each have a second conductivity type second region and a first conductivity type first region provided to be exposed on an upper surface. The total amount of second conductivity type impurities included in the second region in one of the inter-dummy mesa parts is smaller than the total amount of the second conductivity type impurities included in a contact region in one of the gate-adjacent mesa parts.

Description

Semiconductor device

[0001] The present invention relates to a semiconductor device.

[0002] Patent Document 1 discloses a semiconductor device including an "active mesa portion" and a "dummy mesa portion". Patent Document 2 discloses a semiconductor device including an "active trench gate" and a "dummy trench gate". Patent Document 3 discloses a semiconductor device including a "first mesa portion", a "second mesa portion", and a "third mesa portion". [Prior Art Documents] [Patent Documents] [Patent Document 1] JP-A-2023-120081 [Patent Document 2] Japanese Patent No. 7479315 [Patent Document 3] JP-A-2023-130251 Problems to be Solved

[0003] In a semiconductor device, it is preferable that the loss is small. General Disclosure

[0004] In one embodiment of the present invention, a semiconductor device is provided which is provided on a semiconductor substrate having an upper surface and a lower surface and a drift region of a first conductivity type, and comprises a transistor portion and a diode portion. The transistor portion of the semiconductor device may include one or more gate trench portions provided from the upper surface to the interior of the semiconductor substrate. The transistor portion of the semiconductor device may include a plurality of dummy trench portions provided from the upper surface to the interior of the semiconductor substrate. The transistor portion of the semiconductor device may include a gate-adjacent mesa portion provided in contact with any of the gate trench portions inside the semiconductor substrate. The transistor portion of the semiconductor device may include a dummy inter-mesa portion sandwiched between two dummy trench portions inside the semiconductor substrate. The gate-adjacent mesa portion of the semiconductor device may include a base region of a second conductivity type provided between the drift region and the upper surface. The gate-adjacent mesa portion of the semiconductor device may include an emitter region of a first conductivity type provided exposed on the upper surface. The gate-adjacent mesa portion of the semiconductor device may be provided exposed on the upper surface and may have a contact region of a second conductivity type with a higher concentration than the base region. The dummy-intermesa portion of the semiconductor device may have a first region of a first conductivity type provided exposed on the upper surface. The dummy-intermesa portion of the semiconductor device may have a second region of a second conductivity type provided exposed on the upper surface. The total amount of impurities of the second conductivity type contained in the second region of one of the dummy-intermesa portions of the semiconductor device may be less than the total amount of impurities of the second conductivity type contained in the contact region of one of the gate-adjacent mesa portions.

[0005] In the second region included in one of the dummy intermesa portions of the semiconductor device, the area of ​​the contact region with a higher density than the base region may be zero, or smaller than the area of ​​the contact region included in one of the gate-adjacent mesa portions.

[0006] In any of the above semiconductor devices, the dummy mesa portion and the gate-adjacent mesa portion may have an elongated length in the first direction of the upper surface. In any of the above semiconductor devices, a plurality of contact regions may be discretely arranged in the first direction in each of the dummy mesa portion and the gate-adjacent mesa portion. In any of the above semiconductor devices, the number of contact regions included in one dummy mesa portion may be less than the number of contact regions included in one gate-adjacent mesa portion.

[0007] In any of the above semiconductor devices, the dummy mesa portion and the gate-adjacent mesa portion may have a longitudinal length in the first direction of the upper surface. In any of the above semiconductor devices, a plurality of contact regions may be discretely arranged in the first direction in each of the dummy mesa portion and the gate-adjacent mesa portion. In any of the above semiconductor devices, the length of one contact region in the first direction in the dummy mesa portion may be shorter than the length of one contact region in the first direction in the gate-adjacent mesa portion.

[0008] In any of the above semiconductor devices, the area of ​​the first region included in one of the dummy intermesa portions on the upper surface may be smaller than the area of ​​the emitter region included in one of the gate-adjacent mesa portions.

[0009] In any of the above semiconductor devices, the dummy mesa portion and the gate-adjacent mesa portion may have an elongated length in the first direction of the upper surface. In the gate-adjacent mesa portion of any of the above semiconductor devices, a plurality of emitter regions may be discretely arranged in the first direction. In the dummy mesa portion of any of the above semiconductor devices, a plurality of first regions may be discretely arranged in the first direction. In any of the above semiconductor devices, the number of first regions included in one dummy mesa portion may be less than the number of emitter regions included in one gate-adjacent mesa portion.

[0010] The dummy mesa portion and the gate-adjacent mesa portion of any of the above semiconductor devices may have a longitudinal length in the first direction of the upper surface. In the gate-adjacent mesa portion of any of the above semiconductor devices, a plurality of emitter regions may be discretely arranged in the first direction. In the dummy mesa portion of any of the above semiconductor devices, a plurality of first regions may be discretely arranged in the first direction. The length of one first region in the dummy mesa portion of any of the above semiconductor devices in the first direction may be shorter than the length of one emitter region in the gate-adjacent mesa portion in the first direction.

[0011] The plurality of dummy trenches of any of the above semiconductor devices may be arranged side by side in the second direction on the upper surface. The dummy mesa portion of any of the above semiconductor devices may have a second region with a lower density than the contact region, located at a position facing the contact region provided in the gate-adjacent mesa portion in the second direction.

[0012] The dummy intermesa portion of any of the above semiconductor devices may have the first region at a position facing the emitter region provided in the gate-adjacent mesa portion in the second direction.

[0013] On the upper surface of any of the above semiconductor devices, the area of ​​the base region included in one of the dummy inter-mesa portions may be larger than the area of ​​the base region included in one of the gate-adjacent mesa portions.

[0014] The second region of any of the above semiconductor devices may have a lower concentration than the contact region.

[0015] The plurality of dummy trenches of any of the above semiconductor devices may be arranged side by side in the second direction on the upper surface. The second region of any of the above semiconductor devices may be located opposite the contact region provided in the gate-adjacent mesa in the second direction.

[0016] The first region of any of the above semiconductor devices may be located in a position facing the emitter region provided in the gate-adjacent mesa portion in the second direction.

[0017] The second region of any of the above semiconductor devices may be the base region.

[0018] The gate-adjacent mesa portion of any of the above semiconductor devices may have a first trench contact portion made of metal, which is provided in the contact region from the upper surface to the interior of the semiconductor substrate. The dummy-interval mesa portion of any of the above semiconductor devices may have a second trench contact portion made of metal, which is provided in the second region from the upper surface to a depth greater than the first trench contact portion.

[0019] Any of the above semiconductor devices may include an upper electrode provided above the semiconductor substrate. The dummy mesa portion of any of the above semiconductor devices may have a second trench contact portion that extends from the upper surface to the interior of the semiconductor substrate in the second region, is made of metal, and is connected to the upper electrode. The contact region of the gate-adjacent mesa portion of any of the above semiconductor devices may be connected to the upper electrode on the upper surface.

[0020] The second trench contact portion of any of the semiconductor devices described above may be formed to extend below the second region.

[0021] Any of the above semiconductor devices may include an upper electrode provided above the semiconductor substrate. The contact region of any of the above semiconductor devices may have a second conductivity type plug region that is located at a position where it connects to the upper electrode and has a higher density than other parts of the contact region. The density of the second region of any of the above semiconductor devices at the position where it connects to the upper electrode may be lower than that of the plug region.

[0022] The plurality of dummy trenches of any of the above semiconductor devices may be arranged side by side in the second direction of the upper surface. In the second direction of any of the above semiconductor devices, the width of the dummy intermesa portion in contact with the upper surface electrode may be greater than the width of the gate adjacent mesa portion in contact with the upper surface electrode.

[0023] The upper electrode of any of the above semiconductor devices has a titanium-containing barrier metal in the portion connected to the gate-adjacent mesa portion, but does not need to contain titanium in the portion connected to the dummy-intermesa portion.

[0024] The upper electrode of any of the above semiconductor devices has a plug portion containing tungsten in the portion that connects to the gate-adjacent mesa portion, but does not need to contain tungsten in the portion that connects to the dummy-intermesa portion.

[0025] Any of the above semiconductor devices may include an interlayer insulating film provided between the upper electrode and the semiconductor substrate. In any of the above semiconductor devices, two or more of the dummy inter-mesa portions may be arranged side by side in the second direction of the upper surface. Two or more of the dummy inter-mesa portions of any of the above semiconductor devices may be connected to the upper electrode by a common contact hole provided in the interlayer insulating film.

[0026] A second embodiment of the present invention provides a semiconductor device comprising a transistor portion and a diode portion, provided on a semiconductor substrate having an upper surface and a lower surface and a drift region of a first conductivity type. The transistor portion of the semiconductor device may include one or more gate trench portions provided from the upper surface to the interior of the semiconductor substrate. The transistor portion of the semiconductor device may include a plurality of dummy trench portions provided from the upper surface to the interior of the semiconductor substrate. The transistor portion of the semiconductor device may include a gate-adjacent mesa portion provided in contact with any of the gate trench portions inside the semiconductor substrate. The transistor portion of the semiconductor device may include a dummy inter-mesa portion sandwiched between two dummy trench portions inside the semiconductor substrate. The gate-adjacent mesa portion of the semiconductor device may include a base region of a second conductivity type provided between the drift region and the upper surface. The gate-adjacent mesa portion of the semiconductor device may include a contact region of a second conductivity type with a higher density than the base region, provided exposed on the upper surface. The plurality of dummy trenches of the semiconductor device may be arranged side by side in the second direction on the upper surface. The dummy mesa portion of the semiconductor device may have a first region of the first conductivity type at a position facing the contact region provided in the gate-adjacent mesa portion in the second direction.

[0027] The dummy mesa portion and the gate-adjacent mesa portion of any of the above semiconductor devices may have a longitudinal length in the first direction of the upper surface. The gate-adjacent mesa portion of any of the above semiconductor devices may have an emitter region of a first conductivity type with a higher density than the drift region on the upper surface. The dummy mesa portion of any of the above semiconductor devices may also have the first region at a position facing the emitter region provided in the gate-adjacent mesa portion in the second direction.

[0028] The first region of the dummy mesa portion of any of the above semiconductor devices may include the emitter region.

[0029] The first region of the dummy mesa portion of any of the above semiconductor devices may include the drift region.

[0030] The dummy intermesa portion of any of the above semiconductor devices may have the emitter region at a position facing the emitter region provided in the gate-adjacent mesa portion in the second direction, and the drift region at a position facing the contact region provided in the gate-adjacent mesa portion in the second direction.

[0031] The dummy mesa portion of any of the above semiconductor devices does not need to have the base region below the first region which is the drift region.

[0032] The dummy mesa portion of any of the above semiconductor devices may have a trench contact portion of conductive material that penetrates the emitter region.

[0033] A third embodiment of the present invention provides a semiconductor device comprising a transistor portion and a diode portion, provided on a semiconductor substrate having an upper surface and a lower surface and a drift region of a first conductivity type. The transistor portion of the semiconductor device may include one or more gate trench portions provided from the upper surface to the interior of the semiconductor substrate. The transistor portion of the semiconductor device may include a plurality of dummy trench portions provided from the upper surface to the interior of the semiconductor substrate. The transistor portion of the semiconductor device may include a dummy intergate mesa portion sandwiched between the gate trench portion and the dummy trench portion. The transistor portion of the semiconductor device may include a dummy intergate mesa portion sandwiched between two dummy trench portions. The dummy intergate mesa portion of the semiconductor device may include a base region of a second conductivity type provided between the drift region and the upper surface. The dummy intergate mesa portion of the semiconductor device may be provided exposed on the upper surface and may include a contact region of a second conductivity type with a higher density than the base region. On the upper surface of the semiconductor device described above, the area of ​​the contact region of the dummy inter-mesa portion may be 0, or smaller than the area of ​​the contact region of the dummy gate inter-mesa portion.

[0034] The plurality of dummy trenches of any of the above semiconductor devices may be arranged side by side in the second direction on the upper surface. The dummy inter-mesa portion of any of the above semiconductor devices may have a second region of a second conductivity type with a lower concentration than the contact region, at a position facing the contact region provided in the dummy inter-gate mesa portion in the second direction.

[0035] The dummy gate mesa portion of any of the above semiconductor devices may be provided exposed on the upper surface and may have an emitter region of a first conductivity type with a higher concentration than the drift region. The dummy gate mesa portion of any of the above semiconductor devices may also have a second region at a position facing the emitter region provided in the dummy gate mesa portion in the second direction.

[0036] It should be noted that the above summary of the invention does not enumerate all of its features. Furthermore, subcombinations of these features may also constitute an invention.

[0037] This is a top view showing an example of a semiconductor device 100 according to one embodiment of the present invention. This is a diagram showing the configuration of region A in Figure 1 according to a comparative example. This is a diagram showing an example of the a-a cross section in Figure 2. This is a diagram showing an example of the b-b cross section in Figure 2. This is a diagram showing an example of the c-c cross section in Figure 2. This is an enlarged cross-sectional view of the vicinity of the upper surface 21 on which the first mesa portion 61 is provided. This is an enlarged cross-sectional view of the vicinity of the upper surface 21 on which the mesa portion 60-1 is provided. This is an enlarged cross-sectional view of the vicinity of the upper surface 21 on which the mesa portion 60-1 is provided. This is an example of an enlarged view of region A according to the first embodiment. This is a diagram showing an example of the b-b cross section in the example of Figure 9. This is a diagram showing an example of the c-c cross section in the example of Figure 9. This is an example of an enlarged view of region A according to the second embodiment. This is a diagram showing an example of the a-a cross section in the example of Figure 12. This is a diagram showing an example of the c-c cross section in the example of Figure 12. This is an example of an enlarged view of region A according to the third embodiment. This is a diagram showing an example of the c-c cross section in the example of Figure 15. This is an example of an enlarged view of mesa portions 60-2 and 60-1 according to the fourth embodiment. This is a diagram showing an example of the c-c cross section in the example of Figure 17. This is an example of an enlarged view of region A according to the fifth embodiment. This is a diagram showing an example of the c-c cross section in the example of Figure 19. This is an example of an enlarged view of mesa portion 60-2 and mesa portion 60-1 according to the sixth embodiment. This is a diagram showing an example of the b-b cross section in the example of Figure 21. This is a diagram showing an example of the c-c cross section in the example of Figure 21. This is an example of an enlarged view of region A according to the seventh embodiment. This is a diagram showing an example of the c-c cross section in the example of Figure 24. This is an example of an enlarged view of region A according to the eighth embodiment. This is an example of an enlarged view of region A according to the ninth embodiment. This is a diagram showing an example of the b-b cross section in Figure 27. This is a diagram showing an example of the c-c cross section in Figure 27. This is a diagram showing an example of the a-a cross section where the trench contact portion 17 is provided. This is a diagram showing an example of the structure of the trench contact portion 17 provided in mesa portion 61. This is a diagram showing an example of the structure of the trench contact portion 17 provided in mesa portion 60-1. This is a diagram showing another example of the structure of the trench contact portion 17 provided in mesa portion 60-1. This is a diagram showing an example of the structure of the trench contact portion 17 provided in mesa portion 60-2. This figure shows another example of the structure of the trench contact portion 17 provided in the mesa portion 60-2.This figure shows an example of a b-b cross section in which a trench contact portion 17 is provided. This figure shows an example of the structure of a trench contact portion 17 provided in a mesa portion 60-1. This figure shows an example of a c-c cross section in which a trench contact portion 17 is provided. This is an example of an enlarged view of region A according to the 10th embodiment. This figure shows an example of a c-c cross section in Figure 39. This is an example of a b-b cross section according to the 11th embodiment. This is another example of a b-b cross section according to the 11th embodiment. This is an example of a b-b cross section according to the 12th embodiment. This is an example of a cross section of a semiconductor device 100 according to the 13th embodiment.

[0038] The present invention will be described below through embodiments, but these embodiments are not intended to limit the scope of the claims. Furthermore, not all combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0039] In this specification, one side of a semiconductor substrate parallel to its depth direction is referred to as "upper," and the other side as "lower." Of the two main surfaces of a substrate, layer, or other component, one surface is referred to as the upper surface, and the other surface as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the direction in which the semiconductor device is mounted.

[0040] In this specification, technical matters may be described using the Cartesian coordinate axes X, Y, and Z. The Cartesian coordinate axes merely specify the relative positions of components and do not limit any particular direction. For example, the Z axis does not limit the direction to height relative to the ground. Note that the +Z axis direction and the -Z axis direction are opposite directions. When the sign is not specified and only the Z axis direction is written, it means the direction parallel to the +Z axis and the -Z axis.

[0041] In this specification, the orthogonal axes parallel to the top and bottom surfaces of the semiconductor substrate are defined as the X and Y axes. The axis perpendicular to the top and bottom surfaces of the semiconductor substrate is defined as the Z axis. In this specification, the direction of the Z axis may be referred to as the depth direction. In this specification, the direction parallel to the top and bottom surfaces of the semiconductor substrate, including the X and Y axes, may be referred to as the horizontal direction.

[0042] When referred to as "identical" or "equal" in this specification, it may include cases with errors caused by manufacturing variations or the like. Such errors may be, for example, within 10%.

[0043] In this specification, the conductivity type of the doped region doped with impurities is described as P-type or N-type. In this specification, impurities may particularly mean either an N-type donor or a P-type acceptor in some cases, and may be described as dopants. In this specification, doping means introducing a donor or an acceptor into a semiconductor substrate to obtain a semiconductor showing an N-type conductivity type or a semiconductor showing a P-type conductivity type.

[0044] In this specification, the doping concentration means the concentration of donors or acceptors in the thermal equilibrium state. In this specification, the net doping concentration means the net concentration obtained by adding the donor concentration as the concentration of positive ions and the acceptor concentration as the concentration of negative ions, including the polarity of the charges. As an example, when the donor concentration is ND and the acceptor concentration is NA, the net doping concentration at an arbitrary position is ND - NA. In this specification, the net doping concentration may be simply described as the doping concentration.

[0045] When described as P+ type or N+ type in this specification, it means that the doping concentration is higher than that of P-type or N-type. When described as P- type or N- type, it means that the doping concentration is lower than that of P-type or N-type. Also, when described as P++ type or N++ type in this specification, it means that the doping concentration is higher than that of P+ type or N+ type.

[0046] When the concentration distribution of donors, acceptors or net doping has a peak, the peak value may be used as the concentration of donors, acceptors or net doping in the region. In cases where the concentration of donors, acceptors or net doping is substantially uniform, etc., the average value of the concentration of donors, acceptors or net doping in the region may be used as the concentration of donors, acceptors or net doping.

[0047] In each embodiment, an example is shown where the first conductivity type is N-type and the second conductivity type is P-type, but the first conductivity type may be P-type and the second conductivity type may be N-type. In this case, the conductivity types of the substrate, layer, region, etc. in each embodiment will have opposite polarities.

[0048] This specification adopts the SI unit system. In this specification, units of distance and length may be expressed in cm (centimeters). In such cases, calculations may be performed by converting to m (meters).

[0049] Figure 1 is a top view showing an example of a semiconductor device 100 according to one embodiment of the present invention. The semiconductor device 100 is provided on a semiconductor substrate 10. The semiconductor substrate 10 has an upper surface and a lower surface. In Figure 1, the positions of each component of the semiconductor device 100 are shown projected onto the upper surface of the semiconductor substrate 10. In Figure 1, only some components of the semiconductor device 100 are shown, and some components are omitted. For example, the semiconductor substrate 10 has an N-type drift region 18, which will be described later, but is omitted in Figure 1.

[0050] The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 is a substrate formed of a semiconductor material. The semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, or another substrate. In this example, the semiconductor substrate 10 is a silicon substrate. The semiconductor substrate 10 has edges 162 in a top view. In this specification, "top view" simply means viewing from the top side of the semiconductor substrate 10. In this example, the semiconductor substrate 10 has two pairs of edges 162 that face each other in a top view. In Figure 1, the X and Y axes are parallel to either edge 162. The Z axis is perpendicular to the top surface of the semiconductor substrate 10.

[0051] The semiconductor substrate 10 is provided with an active area 160. The active area 160 is a region in which the main current flows in the depth direction between the upper and lower surfaces of the semiconductor substrate 10 when the semiconductor device 100 is operating. An emitter electrode is provided above the active area 160, but it is omitted in Figure 1. The active area 160 may refer to the region that overlaps with the emitter electrode when viewed from above. Also, the region sandwiched between the active areas 160 when viewed from above may be included in the active area 160.

[0052] The active section 160 is provided with a transistor section 70 including transistor elements such as IGBTs (Insulated Gate Bipolar Transistors), and a diode section 80 including diode elements such as freewheeling diodes (FWDs). In the example shown in Figure 1, the transistor section 70 and the diode section 80 are alternately arranged along a predetermined second direction (the X-axis direction in this example) on the upper surface of the semiconductor substrate 10. The semiconductor device 100 in this example is a reverse-conducting IGBT (RC-IGBT). A boundary region is located between the transistor section 70 and the diode section 80 in the X-axis direction, but it is omitted in Figure 1.

[0053] In Figure 1, the region where the transistor section 70 is located is denoted by the symbol "I", and the region where the diode section 80 is located is denoted by the symbol "F". In this specification, a direction different from the second direction in a top view may be referred to as the first direction (Y-axis direction in Figure 1). The first direction may be perpendicular to the second direction. The transistor section 70 and the diode section 80 may each have their longitudinal length in the first direction. That is, the length of the transistor section 70 in the Y-axis direction is greater than its width in the X-axis direction. Similarly, the length of the diode section 80 in the Y-axis direction is greater than its width in the X-axis direction. The first direction of the transistor section 70 and the diode section 80 may be the same as the longitudinal direction of each trench section and the longitudinal direction of the mesa section, which will be described later.

[0054] The diode portion 80 has an N+ type cathode region 82, described later, in the region that is in contact with the lower surface of the semiconductor substrate 10. In this specification, the region in which the cathode region 82 is provided is referred to as the diode portion 80. In other words, the diode portion 80 is the region that overlaps with the cathode region 82 when viewed from above. A P+ type collector region 22 may be provided on the lower surface of the semiconductor substrate 10 in the region other than the cathode region 82. In this specification, an extension region 81, which is an extension of the diode portion 80 in the Y-axis direction to the gate wiring described later, may also be included in the diode portion 80. A collector region 22 is provided on the lower surface of the extension region 81.

[0055] The transistor section 70 has a P+ type collector region 22 in the region that is in contact with the lower surface of the semiconductor substrate 10. Furthermore, the transistor section 70 has a gate structure periodically arranged on the upper surface side of the semiconductor substrate 10, which includes an N type emitter region, a P type base region, a gate conductive portion, and a gate insulating film.

[0056] The semiconductor device 100 may have one or more pads on the semiconductor substrate 10. In this example, the semiconductor device 100 has a gate pad 164. The semiconductor device 100 may also have pads such as an anode pad, a cathode pad, and a current detection pad. Each pad is located near the edge 162. The vicinity of the edge 162 refers to the area between the edge 162 and the emitter electrode in a top view. When the semiconductor device 100 is mounted, each pad may be connected to an external circuit via wiring such as wires.

[0057] A gate potential is applied to the gate pad 164. The gate pad 164 is electrically connected to the conductive portion of the gate trench of the active portion 160. The semiconductor device 100 is provided with gate wiring that connects the gate pad 164 to the gate trench. In Figure 1, the gate wiring is hatched with diagonal lines.

[0058] The gate wiring in this example has an outer perimeter gate wiring 130 and an active-side gate wiring 131. The outer perimeter gate wiring 130 is positioned between the active portion 160 and the edge 162 of the semiconductor substrate 10 in a top view. In this example, the outer perimeter gate wiring 130 surrounds the active portion 160 in a top view. The area surrounded by the outer perimeter gate wiring 130 in a top view may be considered the active portion 160. Furthermore, a well region is formed below the gate wiring. The well region is a P-type region with a higher concentration than the base region, which will be described later, and is formed from the top surface of the semiconductor substrate 10 to a position deeper than the base region. The area surrounded by the well region in a top view may be considered the active portion 160.

[0059] The outer perimeter gate wiring 130 is connected to the gate pad 164. The outer perimeter gate wiring 130 is positioned above the semiconductor substrate 10. The outer perimeter gate wiring 130 may be a metal wiring containing aluminum or the like, and / or a wiring made of a semiconductor such as polysilicon doped with impurities.

[0060] The active gate wiring 131 is provided in the active section 160. By providing the active gate wiring 131 in the active section 160, variations in the wiring length from the gate pad 164 can be reduced for each region of the semiconductor substrate 10.

[0061] The outer periphery gate wiring 130 and the active side gate wiring 131 are connected to the gate trench portion of the active portion 160. The outer periphery gate wiring 130 and the active side gate wiring 131 are positioned above the semiconductor substrate 10. The outer periphery gate wiring 130 and the active side gate wiring 131 may be wiring made of metal wiring containing aluminum, etc., and / or semiconductors such as polysilicon doped with impurities.

[0062] The active gate wiring 131 may be connected to the outer gate wiring 130. In this example, the active gate wiring 131 extends in the X-axis direction from one outer gate wiring 130 to the other outer gate wiring 130 that sandwiches the active portion 160, crossing the active portion 160 approximately in the center in the Y-axis direction. When the active portion 160 is divided by the active gate wiring 131, the transistor portion 70 and the diode portion 80 may be arranged alternately in the X-axis direction in each divided region.

[0063] The semiconductor device 100 may include a temperature sensing unit (not shown) which is a PN junction diode made of polysilicon or the like, and a current detection unit (not shown) which simulates the operation of a transistor unit provided in the active unit 160.

[0064] In this example, the semiconductor device 100 includes an edge termination structure 90 between the active portion 160 and the edge 162 when viewed from above. The edge termination structure 90 in this example is located between the outer peripheral gate wiring 130 and the edge 162. The edge termination structure 90 mitigates electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure 90 may include at least one of a guard ring, a field plate, and a resurf, which are provided in an annular shape surrounding the active portion 160.

[0065] Figure 2 shows the configuration of region A in Figure 1, according to a comparative example. Region A includes a transistor section 70 and a diode section 80. As described above, the transistor section 70 and the diode section 80 are arranged side by side in the X-axis direction. In this example, the region of the transistor section 70 that is in contact with the diode section 80 is referred to as the boundary region 72.

[0066] As described above, the diode portion 80 has an N+ type cathode region 82 in the region that is in contact with the lower surface of the semiconductor substrate 10. The transistor portion 70 also has a P+ type collector region 22 in the region that is in contact with the lower surface of the semiconductor substrate 10.

[0067] The semiconductor device 100 comprises a plurality of gate trenches 40 and a plurality of dummy trenches 30. In this specification, the gate trenches 40 and dummy trenches 30 may be simply referred to as trenches. Each trench extends in the Y-axis direction and has a longitudinal length in the Y-axis direction. The plurality of trenches are arranged in a line in the X-axis direction. The plurality of trenches may be arranged in the X-axis direction at regular intervals. Some of the trenches may be arranged in the X-axis direction at different intervals than the other trenches.

[0068] Each trench extends from the upper surface of the semiconductor substrate 10 to the interior of the semiconductor substrate 10. Each trench has a conductive portion made of a conductive material such as polysilicon and an insulating film made of an insulating material such as an oxide film. The conductive portion is located inside the semiconductor substrate 10. The insulating film insulates the semiconductor substrate 10 from the conductive portion.

[0069] A gate voltage is applied to the conductive part of the gate trench section 40. In this example, the conductive part of the gate trench section 40 is electrically connected to the gate wiring described above. A voltage different from the gate voltage is applied to the conductive part of the dummy trench section 30. In this example, the conductive part of the dummy trench section 30 is electrically connected to the emitter electrode described above, and the emitter potential is applied.

[0070] The transistor section 70 comprises one or more gate trench sections 40 and a plurality of dummy trench sections 30. In this example, the transistor section 70 comprises a plurality of gate trench sections 40. In the X-axis direction, one or more dummy trench sections 30 may be provided between two gate trench sections 40. In the example of Figure 2, two dummy trench sections 30 are provided between two gate trench sections 40. In other examples, two gate trench sections 40 may be provided adjacent to each other in the X-axis direction. When two adjacent gate trench sections 40 are considered as one pair of gate trench sections 40, one or more dummy trench sections 30 may be provided between the two pairs of gate trench sections 40. The boundary region 72 may have one or more dummy trench sections 30. In this example, the boundary region 72 has two dummy trench sections 30.

[0071] Multiple mesa portions are provided in the semiconductor substrate 10. Each mesa portion is a region within the semiconductor substrate 10 that is sandwiched between two trench portions. In the Z-axis direction, the upper end of a mesa portion may be the upper surface of the semiconductor substrate 10. The lower end of a mesa portion may be at the same depth as the lower end of a trench portion. In this specification, the mesa portion of the diode portion 80 is referred to as mesa portion 61, the mesa portion of the boundary region 72 is referred to as mesa portion 62, and the mesa portion of the transistor portion 70 other than the boundary region 72 is referred to as mesa portion 60.

[0072] In this specification, a mesa portion 60 of the transistor portion 70 that is in contact with any of the gate trench portions 40 may be referred to as a gate-adjacent mesa portion. A gate-adjacent mesa portion is a mesa portion 60 sandwiched between the gate trench portion 40 and the dummy trench portion 30, or a mesa portion 60 sandwiched between two gate trench portions 40. In this specification, a mesa portion 60 sandwiched between the gate trench portion 40 and the dummy trench portion 30 may be referred to as a dummy gate-interconnection mesa portion. In the example in Figure 2, mesa portion 60-1 is both a gate-adjacent mesa portion and a dummy gate-interconnection mesa portion.

[0073] In this specification, among the mesa portions 60 of the transistor portion 70, the mesa portion 60 sandwiched between two dummy trench portions 30 may be referred to as the dummy inter-mesa portion. In the example in Figure 2, mesa portion 60-2 is the dummy inter-mesa portion.

[0074] In this example, the mesa portion 60 is provided with a P+ type contact region 15 exposed on the upper surface of the semiconductor substrate 10 and an N+ type emitter region 12. Multiple contact regions 15 may be discretely arranged in the Y-axis direction within the mesa portion 60. Multiple emitter regions 12 may be discretely arranged in the Y-axis direction within the mesa portion 60. In the example shown in Figure 2, the contact regions 15 and emitter regions 12 are arranged alternately in the Y-axis direction. Each of the contact regions 15 and emitter regions 12 may extend from one trench portion to the other in the X-axis direction.

[0075] In other examples, the contact region 15 and the emitter region 12 may be arranged side by side in the X-axis direction. In this case, each of the contact region 15 and the emitter region 12 may have a stripe shape with its longitudinal side in the Y-axis direction. The emitter region 12 may be provided in contact with the gate trench portion 40. The contact region 15 may be provided between the dummy trench portion 30 and the emitter region 12. The contact region 15 may be in contact with the dummy trench portion 30, and an emitter region 12 may also be provided between the contact region 15 and the dummy trench portion 30.

[0076] The boundary region 72 is provided to mitigate the effects of contact between the different structures of the transistor section 70 and the diode section 80, and the mesa section 62 has a structure different from the mesa section of the transistor section 70 other than the boundary region 72. In this example, a P+ type contact region 15 is provided exposed on the upper surface of the semiconductor substrate 10. In this example, the mesa section 62 does not have an emitter region 12. The mesa section 62 may have a structure in which the emitter region 12 of the mesa section 60 is replaced by the contact region 15. In other examples, the emitter region 12 may be replaced by the base region 14. Note that the mesa section 62 may have a structure other than those described above, and the boundary region 72 may not be provided.

[0077] The mesa portion 61 is provided with a P-type base region 14 exposed on the upper surface of the semiconductor substrate 10. The base region 14 functions as the anode region of the diode portion 80. The base region 14 is also provided below the emitter region 12 of the transistor portion 70. The base region 14 in the transistor portion 70 and the base region 14 in the diode portion 80 may have the same doping concentration or may have different doping concentrations.

[0078] The semiconductor device 100 includes an interlayer insulating film provided between the upper surface of the semiconductor substrate 10 and an upper electrode such as an emitter electrode. The interlayer insulating film is provided with contact holes 54 for connecting the semiconductor substrate 10 and the upper electrode. The inside of the contact holes 54 is filled with a conductive material such as metal that connects the semiconductor substrate 10 and the upper electrode.

[0079] The semiconductor device 100 has contact holes 54 in at least some of the mesa portions. In this example, the semiconductor device 100 has contact holes 54 in each of the mesa portions 60, 61, and 62. The contact region 15, emitter region 12, and base region 14 are connected to the upper electrode via the contact holes 54. The contact holes 54 are provided extending in the Y-axis direction and may have an elongation in the Y-axis direction.

[0080] Figure 3 shows an example of the a-a cross-section in Figure 2. The a-a cross-section is the XZ plane passing through mesa portions 61, 62, 60-1, and 60-2. As shown in Figure 2, the a-a cross-section passes through the emitter region 12 of mesa portion 60-1. The semiconductor device 100 in this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24 in this cross-section. The semiconductor substrate 10 also has an upper surface 21 and a lower surface 23.

[0081] The interlayer insulating film 38 is provided on the upper surface 21 of the semiconductor substrate 10. The interlayer insulating film 38 is a film that includes at least one layer of insulating film such as silicate glass with impurities such as boron or phosphorus added, a thermal oxide film, and other insulating films. The interlayer insulating film 38 is provided with contact holes 54 as described in Figure 2.

[0082] The emitter electrode 52 is provided above the interlayer insulating film 38. In this example, the emitter electrode 52 contacts the upper surface 21 of the semiconductor substrate 10 through a contact hole 54 in the interlayer insulating film 38. The collector electrode 24 is provided on the lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are made of a metallic material such as aluminum. A conductive material different from that of the emitter electrode 52 above the interlayer insulating film 38 may be provided inside the contact hole 54. In this specification, the direction connecting the emitter electrode 52 and the collector electrode 24 (Z-axis direction) is referred to as the depth direction. The emitter electrode 52 may have a titanium-containing barrier metal in the portion that contacts the upper surface 21 of the semiconductor substrate 10. The barrier metal may have a titanium nitride layer, or it may have a laminated structure of a titanium nitride layer and a titanium layer. The emitter electrode 52 may have a plug portion made of tungsten or the like that is filled inside the contact hole 54. The plug portion may also be provided in the trench contact portion 17, which will be described later.

[0083] The semiconductor substrate 10 has an N-type drift region 18. The drift region 18 is provided in the transistor portion 70, the diode portion 80, and the boundary region 72, respectively. In this example, the drift region 18 is provided over the entire semiconductor substrate 10 in the X-axis and Y-axis directions.

[0084] The mesa portion 60-1, which is a gate-adjacent mesa portion, has an emitter region 12 and a base region 14. The mesa portion 60-1 may further have a storage region 16. The mesa portion 60-2 in the comparative example has the same structure as the mesa portion 60-1.

[0085] The base region 14 is a P-shaped region provided between the drift region 18 and the upper surface 21. The base region 14 is in contact with the gate trench portion 40. The base region 14 may or may not be in contact with the dummy trench portion 30.

[0086] The emitter region 12 is an N+-type region with a higher concentration than the drift region 18, exposed on the upper surface 21. In this example, the emitter region 12 is located between the base region 14 and the upper surface 21. The emitter region 12 may be in contact with the base region 14. The emitter region 12 is electrically connected to the emitter electrode 52 via a contact hole 54.

[0087] The storage region 16 is provided between the base region 14 and the drift region 18. The storage region 16 is an N-type region with a higher concentration than the drift region 18. The storage region 16 may be in contact with the base region 14. The storage region 16 may be in contact with the drift region 18. The storage region 16 may be in contact with the gate trench 40. The storage region 16 may be provided continuously from one trench section to the other trench section that sandwiches the mesa section 60-1. By providing the storage region 16, the carrier injection promotion effect (IE effect) can be enhanced and the on-voltage can be reduced.

[0088] The mesa portion 62 has a contact region 15 and a base region 14. The contact region 15 is provided between the base region 14 and the upper surface 21. The contact region 15 is electrically connected to the emitter electrode 52 via a contact hole 54.

[0089] The mesa portion 61 has a base region 14. The base region 14 is electrically connected to the emitter electrode 52 via a contact hole 54. As described above, the base region 14 of the mesa portion 61 functions as the anode region of the diode portion 80.

[0090] Multiple gate trenches 40 and multiple dummy trenches 30 are provided on the upper surface 21 of the semiconductor substrate 10. Each trench extends from the upper surface 21 of the semiconductor substrate 10, through the base region 14, to below the base region 14. If a storage region 16 is provided, each trench extends to below the storage region 16. Each trench may extend to a depth that reaches the drift region 18.

[0091] As described above, the transistor section 70 is provided with a gate trench section 40 and a dummy trench section 30. In this example, the diode section 80 and the boundary region 72 are provided with a dummy trench section 30, but the gate trench section 40 is not provided. However, the boundary of the boundary region 72 on the transistor section 70 side may have a gate trench section 40, or a dummy trench section 30.

[0092] The gate trench portion 40 has a gate trench, a gate insulating film 42, and a gate conductive portion 44 provided on the upper surface 21 of the semiconductor substrate 10. The gate insulating film 42 is provided covering the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is provided inside the gate trench, on the inside of the gate insulating film 42. In other words, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0093] The gate conductive portion 44 may be longer than the base region 14 in the depth direction. The upper end position of the gate conductive portion 44 may be at the same depth as the upper surface 21, or it may be below the upper surface 21. The gate trench portion 40 in this cross-section is covered by an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The interlayer insulating film 38 may be provided inside the gate trench. The gate conductive portion 44 is electrically connected to the gate wiring. When a predetermined gate voltage is applied to the gate conductive portion 44, a channel formed by an electron inversion layer is formed on the surface layer of the interface in contact with the gate trench portion 40 in the base region 14.

[0094] The dummy trench portion 30 may have the same structure as the gate trench portion 40 in its cross-section. The dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 provided on the upper surface 21 of the semiconductor substrate 10. The dummy conductive portion 34 is electrically connected to the emitter electrode 52. The dummy insulating film 32 is provided covering the inner wall of the dummy trench. The dummy conductive portion 34 is provided inside the dummy trench and is provided inside the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed from the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 is formed from a conductive material such as polysilicon. The dummy conductive portion 34 may have the same length as the gate conductive portion 44 in the depth direction.

[0095] In this example, the gate trench portion 40 and the dummy trench portion 30 are covered by an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The bottom portions of the dummy trench portion 30 and the gate trench portion 40 may be curved (curved in cross-section) with a downward convex shape.

[0096] In both the transistor section 70 and the diode section 80, an N+ type buffer section 20 may be provided below the drift section 18. The doping concentration in the buffer section 20 is higher than the doping concentration in the drift section 18. The buffer section 20 may have a concentration peak with a higher doping concentration than the drift section 18. The doping concentration of the concentration peak refers to the doping concentration at the peak of the concentration peak. Furthermore, the doping concentration of the drift section 18 may be the average value of the doping concentration in a region where the doping concentration distribution is approximately flat. The doping concentration in the drift section 18 may be the same as the bulk donor concentration, or it may be higher than the bulk donor concentration.

[0097] The buffer region 20 may have two or more concentration peaks in the depth direction (Z-axis direction) of the semiconductor substrate 10. The concentration peaks of the buffer region 20 may be located at the same depth position as, for example, the chemical concentration peaks of hydrogen (proton) or phosphorus. The buffer region 20 may function as a field stop layer that prevents the depletion layer extending from the lower end of the base region 14 from reaching the P+ type collector region 22 and the N+ type cathode region 82.

[0098] In the transistor section 70, a P+ type collector region 22 is provided below the buffer region 20. The acceptor concentration of the collector region 22 is higher than that of the base region 14. The collector region 22 may contain the same acceptors as the base region 14, or it may contain different acceptors. The acceptors of the collector region 22 are, for example, boron.

[0099] In the diode section 80, an N+ type cathode region 82 is provided below the buffer region 20. The donor concentration in the cathode region 82 is higher than that of the drift region 18. The donor in the cathode region 82 is, for example, hydrogen or phosphorus. Note that the elements that act as donors and acceptors in each region are not limited to the examples described above.

[0100] Figure 4 shows an example of the b-b cross section in Figure 2. The b-b cross section is the XZ plane passing through mesa portion 61, mesa portion 62, mesa portion 60-1, and mesa portion 60-2. As shown in Figure 3, the b-b cross section passes through the contact region 15 of mesa portion 60-1.

[0101] The semiconductor device 100 in the b-b cross-section has a contact region 15 instead of an emitter region 12 compared to the semiconductor device 100 in the a-a cross-section. The other structures are the same as those of the semiconductor device 100 in the a-a cross-section. The contact region 15 is provided exposed on the upper surface 21 of the semiconductor substrate 10 and is a P+ type region with a higher concentration than the base region 14.

[0102] The arrows in Figure 4 schematically show the flow of holes when the diode section 80 is ON. When an off voltage is applied to the gate conductive section 44 and the transistor section 70 turns off, the diode section 80 turns ON, and current flows from the base region 14 to the cathode region 82 of the diode section 80. At this time, as shown by the arrows in Figure 4, holes injected from the p-type region of the transistor section 70 near the diode section 80 also flow to the cathode region 82. In this specification, when the conductivity type is described using lowercase n or p, such as n-type or p-type, it indicates that the conductivity type is n or p regardless of the concentration.

[0103] Figure 5 shows an example of a c-c cross-section in Figure 2. The c-c cross-section is the YZ plane passing through the mesa portion 60-2. As shown in Figure 5, the c-c cross-section passes through multiple contact regions 15 and multiple emitter regions 12. In Figure 5, the position of the upper surface of the interlayer insulating film 38 projected onto the c-c cross-section is shown by a dashed line.

[0104] As explained in Figure 2, in the comparative example, the mesa portion 60-2 has contact regions 15 and emitter regions 12 arranged alternately in the Y-axis direction. On the upper surface 21 of the semiconductor substrate 10, the contact regions 15 and emitter regions 12 may be arranged alternately in the Y-axis direction. The emitter regions 12 and contact regions 15 may be provided to the same depth in the Z-axis direction, or to different depths. In the example of Figure 5, the contact regions 15 are provided to a greater depth than the emitter regions 12. A part of the contact regions 15 may be provided below the emitter regions 12. As explained in Figure 2, the emitter electrode 52 is connected to multiple contact regions 15 and multiple emitter regions 12 via contact holes 54.

[0105] Figure 6 is an enlarged cross-sectional view of the vicinity of the upper surface 21 on which the first mesa portion 61 is provided. The emitter electrode 52 in this example includes a barrier metal portion 252, an upper portion 251, and a plug portion 256. The barrier metal portion 252 is provided above the upper surface 21 of the semiconductor substrate 10. The barrier metal portion 252 is provided at least on the bottom surface of the contact hole 54. The barrier metal portion 252 may be in contact with the semiconductor substrate 10. The barrier metal portion 252 may also be provided on the side surface of the contact hole 54. The barrier metal portion 252 may or may not be provided on the upper surface of the interlayer insulating film 38. The plug portion 256 is provided inside the contact hole 54 and is provided between the barrier metal portion 252 and the upper portion 251. The plug portion 256 may or may not be provided on the upper surface of the interlayer insulating film 38 via the barrier metal portion 252.

[0106] The barrier metal portion 252 is formed of a material with higher ion-blocking properties than the upper portion 251. This suppresses the penetration of ions from the package material into the semiconductor substrate 10. Alternatively, it is provided to suppress the reaction between the upper portion 251 or the plug portion 256 and the semiconductor substrate 10 and to improve adhesion. In this example, the barrier metal portion 252 contains titanium. The barrier metal portion 252 may contain a titanium nitride layer. The barrier metal portion 252 may be a laminated film of a titanium layer and a titanium nitride layer. In this example, the barrier metal portion 252 has a first layer 253 and a second layer 254. The first layer 253 is a titanium nitride layer provided in contact with the plug portion 256. The second layer 254 is a titanium layer provided between the first layer 253 and the semiconductor substrate 10. The barrier metal portion 252 may further have a silicide layer 255. The silicide layer 255 is formed at a position in contact with the semiconductor substrate 10. The silicide layer 255 is a layer in which a portion of the second layer 254 has been silicided. At the position where the barrier metal portion 252 is in contact with the upper surface 21 of the semiconductor substrate 10, the second layer 254 does not need to be entirely transformed into the silicide layer 255. Furthermore, if the intrusion of ions from the package material into the semiconductor substrate 10, or the reaction between the upper portion 251 or the plug portion 256 and the semiconductor substrate 10 is not a problem, the barrier metal portion 252 may not be provided.

[0107] The plug portion 256 is provided above the barrier metal portion 252. The plug portion 256 is formed of a material or manufacturing method that provides better embedding into the contact hole 54 than the upper portion 251. The plug portion 256 may contain a different metal than the barrier metal portion 252. For example, it may contain tungsten. If the contact hole 54 is sufficiently wide, the plug portion 256 may not be provided.

[0108] The upper portion 251 is provided above the barrier metal portion 252 via a plug portion 256. The upper portion 251 is also provided above the interlayer insulating film 38. The upper portion 251 is formed of a different material from the barrier metal portion 252. In this example, the upper portion 251 does not contain titanium. As an example, the upper portion 251 contains aluminum. The upper portion 251 may be an alloy of aluminum and silicon. Nickel or gold may be further laminated on top of the aluminum and silicon alloy.

[0109] In this example, the mesa portion 61 is provided in contact with the barrier metal portion 252 and has a P++ type plug region 221 with a higher doping concentration than the contact region 15. The plug region 221 may be provided as an extension in the Y-axis direction, or it may be discretely arranged in the Y-axis direction. By providing the plug region 221, the contact resistance between the base region 14 and the emitter electrode 52 can be reduced. If the barrier metal portion 252 is not provided, the plug region 221 may not be provided.

[0110] Figure 7 is an enlarged cross-sectional view of the vicinity of the upper surface 21 where the mesa portion 60-1 is provided. Figure 7 shows an XZ cross-section passing through the emitter region 12. In the mesa portion 60-1, the emitter electrode 52 may also have an upper portion 251, a plug portion 256, and a barrier metal portion 252. In the mesa portion 60-1, the emitter region 12 does not have a plug portion 221. However, in some areas, the plug portion 221 may be provided in an area shallower than the emitter region 12. The barrier metal portion 252 and the plug portion 256 are not required.

[0111] Figure 8 is an enlarged cross-sectional view of the vicinity of the upper surface 21 where the mesa portion 60-1 is provided. Figure 8 shows an XZ cross-section passing through the contact region 15. The plug region 221 is provided in a region shallower than the contact region 15. By providing the plug region 221, the contact resistance between the contact region 15 and the emitter electrode 52 can be reduced. The barrier metal portion 252 and the plug portion 256 do not need to be provided.

[0112] The mesa portion 60-2 may have the same structure as the mesa portion 60-1 shown in Figures 7 and 8. The mesa portion 62 may also be provided with a barrier metal portion 252 and a plug portion 256, or it may not be provided. The structures shown in Figures 6 to 8 may be applied to each embodiment in this specification.

[0113] Figure 9 is an example of an enlarged view of region A according to the first embodiment. Each embodiment of the semiconductor device 100 described herein differs from the semiconductor device 100 described in Figures 1 to 8 in the structure of at least one mesa portion 60-2. The structure other than the mesa portion 60-2 is the same as that of the semiconductor device 100 described in Figures 1 to 8. Of the mesa portions 60-2 of the transistor portion 70, the mesa portion 60-2 located closest to the diode portion 80 may have the structure described in each embodiment. Two or more mesa portions 60-2 in a single transistor portion 70 may have the structure described in each embodiment. All of the mesa portions 60-2 of the transistor portion 70 may have the structure described in this example.

[0114] The mesa portion 60-1 of each embodiment has a structure similar to any of the examples described in Figures 2 to 8. For example, the mesa portion 60-1 has an emitter region 12 exposed to the upper surface 21 and a contact region 15 exposed to the upper surface 21 and having a higher density than the base region 14. Although omitted in Figure 9, the mesa portion 60-1 has a base region 14 located below the emitter region 12 and the contact region 15, between the drift region 18 and the upper surface 21.

[0115] The mesa portion 60-2 according to the first to sixth embodiments has a first region of a first conductivity type (n) and a second region of a second conductivity type (p). The first and second regions are exposed on the upper surface of the semiconductor substrate 10. The first region may include an emitter region 12, a drift region 18, a storage region 16, or regions of other concentrations. The second region may include a contact region 15, or a region with a lower concentration than the contact region 15 (for example, a base region 14). In this example, the mesa portion 60-2 includes an emitter region 12 as the first region, and a contact region 15 and a base region 14 as the second region.

[0116] When the transistor 70 is turned on, holes injected from the collector region 22 reach the first region, and electrons are injected from the first region. Therefore, by providing the first region in the mesa region 60-2, the amount of electrons injected when the transistor 70 is turned on can be increased, thereby reducing on-loss.

[0117] In each embodiment of this specification, the total amount of impurities of the second conductivity type contained in the second region (p) in one mesa portion 60-2 may be less than the total amount of impurities of the second conductivity type contained in the contact region 15 in one mesa portion 60-1. The total amount of impurities (atoms) in each region corresponds to the total dose of p-type dopant injected into each region. The total dose is the dose per unit area (ions / cm²). ２ ) to the injection area (cm ２ The total amount of impurities in each region can be calculated by multiplying by the impurity concentration (atoms / cm³) at each position within the region. ３ The result may also be calculated by integrating in three directions: the X-axis, Y-axis, and Z-axis. The total amount of impurities in each region varies depending on the average impurity concentration in each region, the volume of each region, the area of ​​each region in a top view, etc.

[0118] In each embodiment of this specification, the area of ​​the contact region 15 with a higher concentration than the base region 14 in the second region (p) included in one mesa portion 60-2 is either zero or smaller than the area of ​​the contact region 15 included in one mesa portion 60-1. In the example of Figure 9, the mesa portion 60-2 includes a contact region 15, but its area is smaller than the contact region 15 in the mesa portion 60-1. The contact region 15 in the mesa portion 60 may refer to a P+-type region with a higher concentration than the base region 14, which is positioned between n-type regions on the upper surface 21. For example, the mesa portion 60 may have a P+-type region further outward than the outermost n-type region in the Y-axis direction. In this case, the P+-type region does not have to be treated as a contact region 15. The area of ​​the contact region 15 of one mesa portion 60-2 may be 90% or less, 70% or less, 50% or less, 30% or less, or 10% or less of the area of ​​the contact region 15 of one mesa portion 60-1.

[0119] In each embodiment, mesa portions 60-1 and 60-2 have an elongated length in the Y-axis direction of the upper surface 21. Each of mesa portions 60-1 and 60-2 may have a long side parallel to the Y-axis on the upper surface 21. The length of this long side is greater than the width of the mesa portion 60 in the X-axis direction.

[0120] In the example shown in Figure 9, multiple contact regions 15 are discretely arranged in the Y-axis direction in each of the mesa sections 60-1 and 60-2. In this case, the number of contact regions 15 in one mesa section 60-2 may be less than the number of contact regions 15 in one mesa section 60-1. This reduces the area of ​​the contact regions 15 in the mesa section 60-2, and thus reduces the amount of holes flowing from the mesa section 60-2 to the diode section 80. As a result, the reverse recovery loss of the semiconductor device 100 can be reduced. The number of contact regions 15 in one mesa section 60-2 may be 90% or less, 70% or less, 50% or less, 30% or less, or 10% or less of the number of contact regions 15 in one mesa section 60-1.

[0121] In the first to sixth embodiments, on the upper surface 21 of the semiconductor substrate 10, the area of ​​the base region 14 included in one mesa portion 60-2 is larger than the area of ​​the base region 14 included in one mesa portion 60-1. The area of ​​the base region 14 included in one mesa portion 60-1 may be 0. The area of ​​the base region 14 of one mesa portion 60-1 may be 90% or less, 70% or less, 50% or less, 30% or less, or 10% or less of the area of ​​the base region 14 of one mesa portion 60-2.

[0122] The mesa section 60-2 shown in Figure 9 replaces a portion of the contact area 15 in the structure of the mesa section 60-1 with a base area 14. In other words, the second area of ​​the mesa section 60-2 (for example, the base area 14) is located opposite the contact area 15 of the mesa section 60-1 in the X-axis direction. In this example, the mesa section 60-2 has a repeating pattern of contact area 15, emitter area 12, base area 14 and emitter area 12 arranged along the Y-axis direction.

[0123] In the example shown in Figure 9, the Y-axis length of the base region 14 of the mesa portion 60-2 is the same as the Y-axis length of the contact region 15 of the mesa portion 60-1. In other examples, the Y-axis length of the base region 14 of the mesa portion 60-2 may be shorter or longer than the Y-axis length of the contact region 15 of the mesa portion 60-1.

[0124] In the example shown in Figure 9, the length of the base region 14 of the mesa portion 60-2 in the Y-axis direction is the same as the length of the contact region 15 of the mesa portion 60-2 in the Y-axis direction. In other examples, the length of the base region 14 of the mesa portion 60-2 in the Y-axis direction may be shorter or longer than the length of the contact region 15 of the mesa portion 60-2 in the Y-axis direction.

[0125] The first region of the mesa portion 60-2 (emitter region 12 in this example) is located opposite the emitter region 12 of the mesa portion 60-1 in the X-axis direction. In the example of Figure 9, the Y-axis length of the emitter region 12 of the mesa portion 60-2 is the same as the Y-axis length of the emitter region 12 of the mesa portion 60-1. In other examples, the Y-axis length of the emitter region 12 of the mesa portion 60-2 may be shorter or longer than the Y-axis length of the emitter region 12 of the mesa portion 60-1. In this example, the mesa portion 60-2 can be created by replacing a part of the contact region 15 of the mesa portion 60-1 with the base region 14, thus avoiding complexity in manufacturing processes such as patterning.

[0126] Figure 10 shows an example of the b-b cross section in the example of Figure 9. The a-a cross section in the example of Figure 9 is the same as in the example of Figure 3. In Figure 9, the XZ cross section passing through the contact region 15 exposed on the upper surface 21 of the mesa portion 60-2 is the same as in the example of Figure 4. The b-b cross section passes through the contact region 15 of the mesa portion 60-1 and the base region 14 of the mesa portion 60-2. The structure other than the mesa portion 60-2 is the same as in the example of Figure 4. In this example, the base region 14 of the mesa portion 60-2 is exposed on the upper surface 21 in the cross section. The mesa portion 60-2 in the cross section does not have a contact region 15. With this configuration, the holes flowing from the mesa portion 60-2 to the diode portion 80 can be reduced.

[0127] Figure 11 shows an example of a c-c cross-section in the example shown in Figure 9. In this example, some of the contact regions 15 in the example shown in Figure 5 are not provided, and instead a base region 14 is provided. In this example, the mesa portion 60-2 has the base region 14 exposed on the upper surface 21 between the two emitter regions 12. The other structures are the same as in the example shown in Figure 5.

[0128] Figure 12 is an example of an enlarged view of region A according to the second embodiment. In the second and third embodiments, on the upper surface 21 of the semiconductor substrate 10, the area of ​​the first region (n) included in one mesa portion 60-2 is smaller than the area of ​​the emitter region 12 included in one mesa portion 60-1. The area of ​​the first region of one mesa portion 60-2 may be 90% or less, 70% or less, 50% or less, 30% or less, or 10% or less of the area of ​​the emitter region 12 of one mesa portion 60-1.

[0129] In the example shown in Figure 12, multiple first regions are discretely arranged in the Y-axis direction within the mesa portion 60-2. The number of first regions in one mesa portion 60-2 is less than the number of emitter regions 12 in one mesa portion 60-1. The number of first regions in one mesa portion 60-2 may be 90% or less, 70% or less, 50% or less, 30% or less, or 10% or less of the number of emitter regions 12 in one mesa portion 60-1.

[0130] In this example, the first region of the mesa section 60-2 is the emitter region 12. In this example, the mesa section 60-2 replaces a portion of the emitter region 12 of the mesa section 60-2 in the example of Figure 9 with a base region 14. In this example, the mesa section 60-2 has a repeating pattern of contact region 15, base region 14, contact region 15, and emitter region 12 arranged along the Y-axis.

[0131] In this example, one base region 14 of the mesa portion 60-2 is positioned opposite the two emitter regions 12 and one contact region 15 of the mesa portion 60-1 in the X-axis direction. In the example in Figure 12, the Y-axis length of the base region 14 of the mesa portion 60-2 is the same as the sum of the Y-axis lengths of the two emitter regions 12 and one contact region 15 of the mesa portion 60-1. However, the length of the base region 14 is not limited to this.

[0132] In this example, the area of ​​the emitter region 12 in the mesa portion 60-2 is reduced. This prevents the amount of electrons injected from the mesa portion 60-2 from becoming too large. Furthermore, by reducing the area of ​​the emitter region 12 in the mesa portion 60-2, the distance that holes travel below the emitter region 12 of the mesa portion 60-2 can be reduced, thereby suppressing latch-up in the mesa portion 60-2.

[0133] Figure 13 shows an example of the a-a cross-section in the example of Figure 12. The XZ cross-section passing through the emitter region 12 exposed on the upper surface 21 of the mesa portion 60-2 is the same as in the example of Figure 3. The a-a cross-section passes through the emitter region 12 of the mesa portion 60-1 and the base region 14 of the mesa portion 60-2. The structure other than the mesa portion 60-2 is the same as the a-a cross-section in Figure 3. Also in Figure 12, the XZ cross-section passing through the contact region 15 exposed on the upper surface 21 of the mesa portion 60-2 is the same as in the example of Figure 4. The b-b cross-section in the example of Figure 12 is the same as in the example of Figure 10. In this example, the mesa portion 60-2 has its base region 14 exposed on the upper surface 21 in the cross-section and does not have a contact region 15. With this configuration, the holes flowing from the mesa portion 60-2 to the diode portion 80 can be reduced.

[0134] Figure 14 shows an example of a c-c cross-section in the example shown in Figure 12. In this example, some of the contact regions 15 and emitter regions 12 in the example shown in Figure 5 are not provided, and instead a base region 14 is provided. In this example, as shown in Figure 12, the base region 14 is exposed on the upper surface 21 between the two contact regions 15 in the mesa portion 60-2. The other structures are the same as in the example shown in Figure 5.

[0135] Figure 15 is an example of an enlarged view of region A according to the third embodiment. In this example, the length of one first region in the mesa portion 60-2 in the Y-axis direction is shorter than the length of one emitter region 12 in the Y-axis direction in the mesa portion 60-1. The first region in this example is the emitter region 12. In the mesa portion 60-2, the emitter region 12 and the base region 14 are provided at positions facing the emitter region 12 of the mesa portion 60-1 in the X-axis direction. In other words, in the mesa portion 60-2, the base region 14 is provided in the portion where the length of the emitter region 12 in the Y-axis direction is shortened.

[0136] In this example, as in the example in Figure 12, the number of emitter regions 12 in one mesa section 60-2 may be less than the number of emitter regions 12 in one mesa section 60-1. In this example, mesa section 60-2 has base regions 14 in place of some of the emitter regions 12. Also, as in the example in Figure 9, the number of contact regions 15 in one mesa section 60-2 may be less than the number of contact regions 15 in one mesa section 60-1. In this example, mesa section 60-2 has base regions 14 in place of some of the contact regions 15.

[0137] In this example, the mesa section 60-2 has a repeating pattern of contact region 15, emitter region 12, base region 14, and emitter region 12 arranged along the Y-axis. In this example, one base region 14 of the mesa section 60-2 is provided over a longer area in the Y-axis direction than one emitter region 12 and two contact regions 15 of the mesa section 60-1. In this example, one base region 14 of the mesa section 60-2 is provided in an area facing a part of one emitter region 12, the entirety of one contact region 15, the entirety of one emitter region 12, the entirety of one contact region 15, and a part of one emitter region 12, which are arranged along the Y-axis in the mesa section 60-1. In this example as well, the flow of holes from the mesa section 60-2 to the diode section 80 can be reduced. As in this example, reducing the emitter region 12 in the mesa portion 60-2 can suppress latch-up in the mesa portion 60-2.

[0138] Figure 16 shows an example of a c-c cross section in the example of Figure 15. The XZ cross section passing through the emitter region 12 exposed on the upper surface 21 in the mesa portion 60-2 is the same as in the example of Figure 3. The a-a cross section is the same as in the example of Figure 13. The XZ cross section passing through the contact region 15 exposed on the upper surface 21 in the mesa portion 60-2 is the same as in the example of Figure 4. The b-b cross section is the same as in the example of Figure 10. In this example, some of the contact regions 15 and some of the emitter regions 12 in the example shown in Figure 5 are not provided, and instead a base region 14 is provided. In this example, in the mesa portion 60-2, the base region 14 is exposed on the upper surface 21 between two emitter regions 12. The length of the emitter region 12 adjacent to the base region 14 is shorter than the length of the emitter region 12 in the mesa portion 60-1. Furthermore, the Y-axis length of the base region 14 exposed on the upper surface 21 in the mesa portion 60-2 is longer than the one emitter region 12 and the two contact regions 15 of the mesa portion 60-1. The other structures are the same as in the example in Figure 5.

[0139] Figure 17 is an example of an enlarged view of mesa portions 60-2 and 60-1 according to the fourth embodiment. In this example, the length of one contact region 15 in the Y-axis direction in mesa portion 60-2 is shorter than the length of one contact region 15 in the Y-axis direction in mesa portion 60-1.

[0140] The mesa portion 60-2 is provided with a base region 14 that is in contact with the contact region 15 in the Y-axis direction. In the mesa portion 60-2, base regions 14 may be provided on both sides in the Y-axis direction for each contact region 15. The sum of the lengths in the Y-axis direction of one contact region 15 in the mesa portion 60-2 and the two base regions 14 that are in contact with the contact region 15 may be the same as the length in the Y-axis direction of one contact region 15 in the mesa portion 60-1. In other words, the mesa portion 60-2 has a configuration in which a portion of each contact region 15 is replaced with a base region 14 compared to the configuration of the mesa portion 60-1. In the mesa portion 60-2, a portion of the emitter region 12 may be further replaced with a base region 14. In this case, the base region 14 of the mesa portion 60-2 may be provided in a range that faces both a portion of the contact region 15 and a portion of the emitter region 12 of the mesa portion 60-1.

[0141] In this example, the mesa section 60-2 has a repeating pattern of a base region 14, a contact region 15, a base region 14, and an emitter region 12 arranged along the Y-axis. In the example in Figure 17, the number of contact regions 15 in one mesa section 60-2 is the same as the number of contact regions 15 in one mesa section 60-1. In this example as well, the number of contact regions 15 in one mesa section 60-2 may be less than the number of contact regions 15 in one mesa section 60-1. In this example as well, the number of holes flowing from the mesa section 60-2 to the diode section 80 can be reduced.

[0142] In the example shown in Figure 17, the contact region 15 of the mesa portion 60-2 is sandwiched between the base region 14. In other examples, the contact region 15 may sandwich the base region 14 of the mesa portion 60-2. In other words, the base region 14 and the contact region 15 of the mesa portion 60-2 may be swapped in their arrangement compared to the example in Figure 17. Also, in the mesa portion 60-2, one contact region 15 and one base region 14 may be placed between the two emitter regions 12.

[0143] Figure 18 shows an example of a c-c cross section in the example of Figure 17. The a-a cross section is the same as in the example of Figure 3. The b-b cross section is the same as in the example of Figure 10. Also, the XZ cross section passing through the contact region 15 exposed on the upper surface 21 in the mesa portion 60-2 is the same as in the example of Figure 4.

[0144] In this example, a contact region 15 is provided between the two emitter regions 12. However, it differs from the example in Figure 5 in that each contact region 15 is not in contact with the emitter region 12. A base region 14 is provided between the contact region 15 and the emitter region 12. The other structures are the same as in the example in Figure 5.

[0145] Figure 19 is an example of an enlarged view of region A according to the fifth embodiment. In the fifth and sixth embodiments, the mesa portion 60-2 has a first region (n) exposed to the upper surface 21 and a second region (p) exposed to the upper surface 21 and having a lower concentration than the contact region 15. The mesa portion 60-2 in the fifth and sixth embodiments does not have a contact region 15 sandwiched between the first regions.

[0146] In this example, the second region of the mesa portion 60-2 includes the base region 14 but does not include the contact region 15. The first region of the mesa portion 60-2 includes the emitter region 12. In this example, the area of ​​the base region 14 included in one mesa portion 60-2 is larger than the area of ​​the base region 14 included in one mesa portion 60-1. Also, the area of ​​the contact region 15 included in one mesa portion 60-2 is smaller than the area of ​​the contact region 15 included in one mesa portion 60-1. The area of ​​the contact region 15 included in the mesa portion 60-2 may be 0. Also, the area of ​​the emitter region 12 included in one mesa portion 60-2 is the same as the area of ​​the emitter region 12 included in one mesa portion 60-1.

[0147] The mesa section 60-2 has a second p-type region (base region 14 in this example) with a lower concentration than the contact region 15 of the mesa section 60-1, located opposite the contact region 15 in the X-axis direction. The mesa section 60-2 has a first n-type region (emitter region 12 in this example) located opposite the emitter region 12 of the mesa section 60-1 in the X-axis direction. The mesa section 60-2 in this example has a configuration in which all the contact regions 15 sandwiched between the emitter regions 12 are replaced with the base region 14 compared to the configuration of the mesa section 60-1. In the mesa section 60-2, a portion of the emitter region 12 may be further replaced with the base region 14. In this case, the base region 14 of the mesa section 60-2 may be provided in a range that faces both a portion of the contact region 15 and a portion of the emitter region 12 of the mesa section 60-1.

[0148] In this example, the mesa portion 60-2 has a repeating pattern of base region 14 and emitter region 12 arranged along the Y-axis. This example also reduces the amount of holes flowing from the mesa portion 60-2 to the diode portion 80.

[0149] Figure 20 shows an example of a c-c cross-section in the example of Figure 19. The a-a cross-section is the same as in the example of Figure 3. The b-b cross-section is the same as in the example of Figure 10. In this example, a base region 14 is provided instead of the contact region 15 in the example of Figure 5. Between the two emitter regions 12, the base region 14 is exposed on the upper surface 21 of the semiconductor substrate 10. The other structures are the same as in the example of Figure 5.

[0150] Figure 21 is an example of an enlarged view of mesa portion 60-2 and mesa portion 60-1 according to the sixth embodiment. Mesa portion 60-2 according to the sixth to ninth embodiments has a first region (n) at a position opposite the contact region 15 provided in mesa portion 60-1 in the X-axis direction. Mesa portion 60-2 may have a structure in which at least a part of the contact region 15 in mesa portion 60-1 is replaced by the first region.

[0151] In the example shown in Figure 21, the first region of the mesa portion 60-2 is the emitter region 12 and the drift region 18. The second region is the base region 14. In this example, the mesa portion 60-2 does not have a contact region 15 sandwiched between the first regions.

[0152] In this example, the mesa portion 60-2 has a base region 14 and an n-type first region (drift region 18 in this example) at a position opposite the contact region 15 of the mesa portion 60-1 in the X-axis direction. The drift region 18 may be sandwiched between the base region 14 in the Y-axis direction. The mesa portion 60-2 also has an n-type first region (emitter region 12 in this example) at a position opposite the emitter region 12 provided on the mesa portion 60-1 in the X-axis direction. In this example, the mesa portion 60-2 has an n-type first region (drift region 18 in Figure 21) instead of the contact region 15 compared to the structure of the mesa portion 60-2 in the example of Figure 17. Other structures may be the same as in the example of Figure 17.

[0153] In this example, the mesa portion 60-2 has a repeating pattern along the Y-axis, consisting of a base region 14, a drift region 18, another base region 14, and an emitter region 12. This example also reduces the amount of holes flowing from the mesa portion 60-2 to the diode portion 80.

[0154] Figure 22 shows an example of a b-b cross-section in the example of Figure 21. The a-a cross-section is the same as in the example of Figure 3. In Figure 21, the XZ cross-section passing through the base region 14 exposed on the upper surface 21 of the mesa portion 60-2 is the same as in the example of Figure 10. The mesa portion 60-2 in this example has a drift region 18 as an n-type first region exposed on the upper surface 21 of the semiconductor substrate 10. The mesa portion 60-2 does not have a base region 14 below the first region which is the drift region 18. The first region which is the drift region 18 may be directly connected to the drift region 18 below the trench portion, or it may be connected via the accumulation region 16. The base region 14 may have a higher concentration than the drift region 18. Even in this case, by not providing a base region 14 below the drift region 18, it is possible to prevent the base region 14 from diffusing and being exposed on the upper surface 21, and to easily expose the drift region 18 on the upper surface 21. The connection between the first region, the drift region 18, and the emitter electrode may be the same as the connection with the emitter region 12 shown in Figure 7. That is, it does not have a plug region 221 that contacts the emitter electrode 52. As a result, the drift region 18 exposed on the upper surface 21 is connected to the emitter electrode 52 via a Schottky connection.

[0155] Figure 23 shows an example of a c-c cross-section in the example shown in Figure 21. The emitter region 12 is surrounded by the emitter electrode 52 and the base region 14. Since the base region 14 is provided between the emitter region 12 and the drift region 18, electrical conductivity between the emitter region 12 and the drift region 18 can be prevented. In addition, the drift region 18 exposed on the upper surface 21 is connected to the emitter electrode 52 by a Schottky connection. This suppresses the flow of current through the drift region 18 exposed on the upper surface 21. Instead of the drift region 18 exposed on the upper surface 21, a first region with a higher concentration than the drift region 18 may be provided. However, this first region has a lower concentration than the emitter region 12.

[0156] Figure 24 is an example of an enlarged view of region A according to the seventh embodiment. The mesa portion 60-2 according to the seventh to ninth embodiments does not have a second region (p) sandwiched between the first region (n). The mesa portion 60-2 may not have a second region.

[0157] In this example, the mesa portion 60-2 has a drift region 18 at a position opposite the contact region 15 and emitter region 12 of the mesa portion 60-1 in the X-axis direction. The mesa portion 60-2 may have a structure in which the contact region 15 and emitter region 12 of the mesa portion 60-1 are replaced by the drift region 18. The mesa portion 60-2 may have one continuous drift region 18 exposed on the upper surface 21. In this example as well, the amount of holes flowing from the mesa portion 60-2 to the diode portion 80 can be reduced.

[0158] Figure 25 shows an example of the c-c cross section in the example of Figure 24. The b-b cross section is the same as in the example of Figure 22. The a-a cross section is similar to the structure in the example of Figure 13, but with the base region 14 of the mesa portion 60-2 replaced by a drift region 18. In this example, the mesa portion 60-2 has a drift region 18 instead of the contact region 15, emitter region 12, and base region 14 in the example of Figure 5. In this example as well, the base region 14 is not provided below the drift region 18.

[0159] Figure 26 is an example of an enlarged view of region A according to the eighth embodiment. In this example, the mesa portion 60-2 has a drift region 18 at a position opposite the contact region 15 of the mesa portion 60-1 in the X-axis direction. The mesa portion 60-2 has an emitter region 12 at a position opposite the emitter region 12 of the mesa portion 60-1. The mesa portion 60-2 in this example may have a structure in which the contact region 15 of the mesa portion 60-1 is replaced by the drift region 18.

[0160] The a-a cross section is the same as in the example in Figure 3. The b-b cross section is the same as in the example in Figure 22. The c-c cross section is similar to the structure in which the base region 14 in the example in Figure 20 is replaced with a drift region 18. This example also reduces the amount of holes flowing from the mesa portion 60-2 to the diode portion 80.

[0161] Figure 27 is an example of an enlarged view of region A according to the ninth embodiment. In this example, the mesa portion 60-2 has an emitter region 12 positioned opposite the contact region 15 and emitter region 12 of the mesa portion 60-1 in the X-axis direction. The mesa portion 60-2 may have a structure in which the contact region 15 of the mesa portion 60-1 is replaced with an emitter region 12. The mesa portion 60-2 may have one continuous emitter region 12 exposed on the upper surface 21. In this example as well, the flow of holes from the mesa portion 60-2 to the diode portion 80 can be reduced.

[0162] Figure 28 shows an example of the b-b cross-section of Figure 27. The a-a cross-section is the same as in the example in Figure 3. In this example, the mesa portion 60-2 has an emitter region 12 as a first region exposed on the upper surface 21 of the semiconductor substrate 10. The mesa portion 60-2 has a base region 14 between the emitter region 12 and the drift region 18. The mesa portion 60-2 may or may not have a storage region 16.

[0163] Figure 29 shows an example of the c-c cross-section of Figure 27. In this example, the mesa portion 60-2 has an emitter region 12 instead of the contact region 15 in the example of Figure 5.

[0164] Figure 30 shows an example of a cross-section a-a where the trench contact portion 17 is provided. The cross-section a-a in this example corresponds to the example in Figure 27. The trench contact portion 17 is formed of a conductive material from the upper surface 21 of the semiconductor substrate 10 to the interior. The trench contact portion 17 may be formed of the same material as the emitter electrode 52 above the upper surface 21 of the semiconductor substrate 10, or it may be formed of a different material.

[0165] The trench contact portion 17 is provided in at least one mesa portion. The trench contact portion 17 may be provided in mesa portion 60-1, mesa portion 60-2, mesa portion 61, or mesa portion 62. In this example, the trench contact portion 17 is provided in all mesa portions.

[0166] The trench contact portion 17 may be provided below the contact hole 54. The trench contact portion 17 may extend along the contact hole 54 in the Y-axis direction. By having the trench contact portion 17 on the emitter electrode 52, the distance that the hole travels across the semiconductor substrate 10 can be shortened, and latch-up can be prevented.

[0167] The trench contact portion 17 of the mesa portion 60-2 may be provided penetrating the emitter region 12. That is, the trench contact portion 17 may be provided from the upper surface 21 of the semiconductor substrate 10 down to below the emitter region 12. The lower end of the trench contact portion 17 may reach the base region 14 below the emitter region 12. The trench contact portion 17 of the mesa portion 60-1 may or may not be provided penetrating the emitter region 12. In the region where the contact region 15 is provided, the lower end of the trench contact portion 17 may be provided in the contact region 15, or it may reach the base region 14 below the contact region 15.

[0168] As in the ninth embodiment, when the entire or nearly entire mesa portion 60-2 is used as the emitter region 12, the base region 14 below the emitter region 12 becomes close to a floating state. When the transistor portion 70 is ON, the base region 14 and the emitter region 12 are in a PN sequential junction, and when a hole reaches the base region 14 from the collector region 22, the hole can flow through the emitter region 12 to the emitter electrode 52.

[0169] On the other hand, when the transistor section 70 is turned off, there is no p-type region in the mesa section 60-2 that is in contact with the emitter electrode 52. Therefore, holes near the mesa section 60-2 cannot pass from the mesa section 60-2 to the emitter electrode 52. Holes near the mesa section 60-2 will flow through the mesa section 60-1 to the emitter electrode 52, which may increase the possibility of latch-up, for example.

[0170] By providing a trench contact portion 17 in the mesa portion 60-2, when the transistor portion 70 is turned off, holes near the mesa portion 60-2 can be passed to the emitter electrode 52 through the trench contact portion 17. This reduces the possibility of latch-up and the like. In embodiments other than the ninth embodiment, the trench contact portion 17 described herein may also be provided. Furthermore, as in the example in Figure 9, latch-up can also be prevented by leaving a contact region 15 in the mesa portion 60-2.

[0171] Figure 31 shows an example of the structure of a trench contact portion 17 provided in the mesa portion 61. The trench contact portion 17 can be formed by forming a groove in the upper surface 21 of the semiconductor substrate 10 exposed by the contact hole 54 and filling the inside of the groove with a metal electrode. The trench contact portion 17 may be provided with an upper portion 251 of the emitter electrode 52, a plug portion 256, and a barrier metal portion 252. A plug region 221 may be provided in the semiconductor substrate 10 that is in contact with the lower end of the trench contact portion 17. The plug region 221 is a P++ type region with a higher concentration than the contact region 15. With this structure, the contact resistance between the base region 14 and the emitter electrode 52 can be reduced. The trench contact portion 17 and the plug region 221 can be applied to the base region 14 of the mesa portion 61 and mesa portion 60-2 of each embodiment.

[0172] Figure 32 shows an example of the structure of a trench contact portion 17 provided in the mesa portion 60-1. The trench contact portion 17 in this example has the same structure as the example in Figure 31. The trench contact portion 17 is provided down to below the emitter region 12. The emitter region 12 is in contact with the side surface of the trench contact portion 17. A plug region 221 in contact with the lower end of the trench contact portion 17 may or may not be provided. Since the side surface of the trench contact portion 17 and the emitter region 12 can be connected, the plug region 221 may be provided in contact with the lower end of the trench contact portion 17. The plug region 221 is not provided in contact with the side surface of the trench contact portion 17. However, in some areas, the plug region 221 may be provided in contact with the side surface of the trench contact portion 17.

[0173] Figure 33 shows another example of the structure of the trench contact portion 17 provided in the mesa portion 60-1. In this example, the lower end of the trench contact portion 17 is provided in the emitter region 12. The other structures may be the same as those described using Figure 32. Note that the trench contact portion 17 and plug region 221 described using Figures 32 and 33 can be applied to the emitter region 12 of the mesa portion 60-1 in each embodiment.

[0174] Figure 34 shows an example of the structure of a trench contact portion 17 provided in the mesa portion 60-2. In this example, the lower end of the trench contact portion 17 is located below the emitter region 12. Furthermore, a plug region 221 is provided in the semiconductor substrate 10 that is in contact with the lower end of the trench contact portion 17. With this structure, holes in the mesa portion 60-2 can be flowed to the emitter electrode 52.

[0175] Figure 35 shows another example of the structure of the trench contact portion 17 provided in the mesa portion 60-2. In this example, the lower end of the trench contact portion 17 is located in the emitter region 12. However, the plug region 221 at the lower end of the trench contact portion 17 extends below the emitter region 12 and is connected to the base region 14. With this structure, holes in the mesa portion 60-2 can be flowed to the emitter electrode 52. The trench contact portion 17 and plug region 221 described with reference to Figures 34 and 35 can be applied to the emitter region 12, which is the first region of the mesa portion 60-2 in each embodiment. Alternatively, the trench contact portion 17 and plug region 221 described with reference to Figures 32 and 33 may be applied to the emitter region 12, which is the first region of the mesa portion 60-2 in each embodiment. In the seventh and eighth embodiments, a similar trench contact portion 17 may be applied to the drift region 18, which is the first region of the mesa portion 60-2, by not providing a plug region 221.

[0176] Figure 36 shows an example of a cross-section b-b where a trench contact portion 17 is provided. The cross-section b-b in this example corresponds to the example in Figure 27. In the mesa portion 60-1, the lower end of the trench contact portion 17 is located in the contact area 15.

[0177] Figure 37 shows an example of the structure of a trench contact portion 17 provided on the mesa portion 60-1. In this example, the lower end of the trench contact portion 17 is located in the contact area 15. The plug area 221 at the lower end of the trench contact portion 17 is also provided inside the contact area 15. The lower end of the trench contact portion 17 may reach the base area 14, and the plug area 221 may also be formed on the side surface of the trench contact portion 17. The mesa portion 62 may be provided with a trench contact portion 17 and plug area 221 similar to those of the mesa portion 60-1, or with a trench contact portion 17 and plug area 221 similar to those of the mesa portion 61. Furthermore, the contact areas 15 of the mesa portions 60-1 and 60-2 in each embodiment may be provided with similar trench contact portions 17 and plug areas 221.

[0178] Figure 38 shows an example of a c-c cross-section in which a trench contact portion 17 is provided. The c-c cross-section in this example corresponds to the example in Figure 27. In Figure 38, the upper end position of the interlayer insulating film 38, the upper surface 21 of the semiconductor substrate 10, and the boundary position between the emitter region 12 and the base region 14 are indicated by dashed lines. As described above, the trench contact portion 17 is provided below the emitter region 12 and is connected to the base region 14. In Figure 38, the plug region 221 is omitted.

[0179] Figure 39 is an example of an enlarged view of region A according to the tenth embodiment. The mesa portion 60-2 according to the tenth embodiment does not have a contact region 15 sandwiched between the first region (n). The mesa portion 60-2 may not have a contact region 15.

[0180] As described above, the mesa portion 60-1, which is a mesa portion between dummy gates, is provided with a contact region 15 and an emitter region 12. A base region 14 is also provided below the contact region 15 and the emitter region 12.

[0181] In this example as well, on the upper surface 21 of the semiconductor substrate 10, the area of ​​the contact region 15 of the mesa portion 60-2 is 0, or smaller than the area of ​​the contact region 15 of the mesa portion 60-1. In this example, the mesa portion 60-2 has a second region (base region 14 in this example) with a lower density than the contact region 15, located opposite the contact region 15 of the mesa portion 60-1 in the X-axis direction. The b-b cross section in Figure 39 is the same as in the example in Figure 10. The mesa portion 60-2 also has a second region (base region in this example) located opposite the emitter region 12 of the mesa portion 60-1 in the X-axis direction. The a-a cross section in Figure 39 is the same as in the example in Figure 13.

[0182] In this example, the mesa portion 60-2 has a structure in which the contact region 15 and emitter region 12 of the mesa portion 60-1 are replaced with a base region 14. This example also reduces the amount of holes flowing from the mesa portion 60-2 to the diode portion 80.

[0183] Figure 40 shows an example of the c-c cross-section of Figure 39. In this example, the mesa portion 60-2 has a base region 14 instead of the contact region 15 and emitter region 12 in the example of Figure 5.

[0184] Figure 41 is an example of a b-b cross-section according to the 11th embodiment. In the semiconductor device 100 according to the 11th embodiment, the total amount of second conductivity type impurities contained in the second region (p) of one mesa portion 60-2 is smaller than the total amount of second conductivity type impurities contained in the contact region 15 of one mesa portion 60-1. In the 11th embodiment, the arrangement of each impurity region in mesa portions 60-1, mesa portion 60-2, mesa portion 61, and mesa portion 62 may be the same as in any of the examples described in Figures 1 to 40. The arrangement of each impurity region in Figure 41 is the same as in the comparative examples described in Figures 2 to 4. In the example of Figure 41, the arrangement of each impurity region in mesa portion 60-2 is the same as the arrangement of each impurity region in mesa portion 60-1, but the arrangement of each impurity region in mesa portion 60-2 may be different from the arrangement of each impurity region in mesa portion 60-1.

[0185] In this example, mesa portion 60-1 has a first trench contact portion 17-1, and mesa portion 60-2 has a second trench contact portion 17-2. Mesa portion 62 may be provided with a second trench contact portion 17-1. Mesa portion 61 may be provided with either a first trench contact portion 17-1 or a second trench contact portion 17-2. The structure of each trench contact portion 17 is the same as any of the trench contact portions 17 described herein. The trench contact portions 17 are made of metal. For example, the trench contact portion 17 may include a plug portion 256 and a barrier metal portion 252, as described in Figure 31, etc. The trench contact portion 17 may be made of the same material as the emitter electrode 52.

[0186] The first trench contact portion 17-1 is provided at least in the contact region 15, extending from the upper surface 21 of the semiconductor substrate 10 to the interior of the semiconductor substrate 10. The first trench contact portion 17-1 may also be provided in the emitter region 12. The first trench contact portion 17-1 in the mesa portion 60-1 may extend in the Y-axis direction over the entire area where the contact region 15 or the emitter region 12 is provided. The Y-axis length of the trench contact portion 17 in other mesa portions may be the same as the Y-axis length of the first trench contact portion 17-1 in the mesa portion 60-1.

[0187] The second trench contact portion 17-1 is provided in at least the second region (in this example, the contact region 15 of the mesa portion 60-2) from the upper surface 21 of the semiconductor substrate 10 to the interior of the semiconductor substrate 10. The second trench contact portion 17-2 may also be provided in the first region (in this example, the emitter region 12 of the mesa portion 60-2). The second trench contact portion 17-2 may extend in the Y-axis direction over the entire region where the contact region 15 or the emitter region 12 is provided.

[0188] The volume of the second trench contact portion 17-2, which is located inside the second region, may be larger than the volume of the first trench contact portion 17-1, which is located inside the contact region 15. By providing each trench contact portion 17, the volume of the second region or the contact region 15 is reduced. By increasing the volume of the second trench contact portion 17-2, the volume of the second region can be reduced. This reduces the volume of the contact region 15 in the mesa portion 60-2, and reduces the amount of holes flowing from the mesa portion 60-2 to the diode portion 80.

[0189] In this example, the second trench contact portion 17-2 is provided to a greater depth than the first trench contact portion 17-1. The width of the second trench contact portion 17-2 in the X-axis direction may be the same as, or greater than, the width of the first trench contact portion 17-1 in the X-axis direction. The length of the second trench contact portion 17-2 in the depth direction may be 1.1 times or more, 1.2 times or more, 1.5 times or more, or 2 times or more, the length of the first trench contact portion 17-1 in the depth direction.

[0190] In the example shown in Figure 41, the second trench contact portion 17-2 is located inside the second region (contact region 15 in this example) and does not reach the base region 14. In other examples, the second trench contact portion 17-2 may extend below the second region. For example, the second trench contact portion 17-2 may reach the base region 14. The second trench contact portion 17-2 does not need to be in contact with the accumulation region 16 or the drift region 18. The first trench contact portion 17-1 may be formed to be shallower than the contact region 15.

[0191] In this example, the side wall of the second trench contact portion 17-2 is in contact with the second region. This increases the contact area between the second trench contact portion 17-2 and the second region. The side wall of the first trench contact portion 17-1 may also be in contact with the contact region 15.

[0192] Figure 42 shows another example of the b-b cross-section according to the eleventh embodiment. In this example, the semiconductor device 100 does not have a first trench contact portion 17-1 in the mesa portion 60-1. Similarly, the mesa portion 61 does not need to have a trench contact portion 17. The other structures are the same as in the example in Figure 41.

[0193] The contact region 15 of the mesa portion 60-1 is connected to the emitter electrode 52 on the upper surface 21 of the semiconductor substrate 10. The upper surface of the contact region 15 and the upper surface 21 of the semiconductor substrate 10 are located at the same height. The emitter electrode 52 may include at least one of a plug portion 256 and a barrier metal portion 252. A plug region 221 may be provided in the portion of the mesa portion 60-1 that connects to the emitter electrode 52. In this example as well, the volume of the contact region 15 in the mesa portion 60-2 can be reduced, and the flow of holes from the mesa portion 60-2 to the diode portion 80 can be reduced.

[0194] Figure 43 is an example of a b-b cross-section according to the twelfth embodiment. The semiconductor device 100 in this example differs from the other examples described herein in the arrangement of plug regions 221 in each mesa. The structure other than the arrangement of plug regions 221 is the same as in any of the examples described herein unless otherwise specifically stated. The arrangement of impurity regions in Figure 43 is the same as in the example in Figure 41. In the example of Figure 43, trench contact portions 17 are not provided in each mesa, but trench contact portions 17 may be provided in each mesa, as in any of the examples described in Figures 1 to 42.

[0195] A plug region 221 is provided in the mesa portion 60-1. The characteristics and structure of the plug region 221, such as its concentration, are the same as those of the plug region 221 in any of the examples described herein. The plug region 221 is provided in at least the contact region 15. The emitter region 12 does not need to have a plug region 221.

[0196] In this example, the plug region 221 is located at a position where it connects to the emitter electrode 52 and is a region of second conductivity with a higher concentration than the rest of the contact region 15. The plug region 221 may be exposed on the upper surface 21 of the semiconductor substrate 10.

[0197] The mesa portion 60-2 does not have a plug region 221. In the second region of the mesa portion 60-2 (the contact region 15 in this example), the concentration at the position connected to the emitter electrode 52 is lower than that of the plug region 221. This configuration also reduces the total amount of p-type impurities in the second region, thereby reducing the amount of holes flowing from the mesa portion 60-2 to the diode portion 80.

[0198] The interlayer insulating film 38 is provided with a first contact hole 54-1 that exposes the mesa portion 60-1 and a second contact hole 54-2 that exposes the mesa portion 60-2. The first contact hole 54-1 may be provided for the mesa portions 61 and 62.

[0199] In the X-axis direction, the width W2 of the mesa portion 60-2 in contact with the emitter electrode 52 may be larger than the width W1 of the mesa portion 60-1 in contact with the emitter electrode 52. In this example, the width W2 of the second contact hole 54-2 is larger than the width W1 of the first contact hole 54-1. The width W2 may be 1.1 times or more, 1.2 times or more, or 1.5 times or more of the width W1.

[0200] If the width of the contact hole 54 increases due to manufacturing variations, the emitter electrode 52 may come into contact with the conductive part of the adjacent trench. The mesa portion 60-2 is sandwiched between the dummy trench portion 30. In the dummy trench portion 30, even if the emitter electrode 52 and the dummy conductive part 34 come into contact, it does not pose a major problem. For this reason, the width W2 of the second contact hole 54-2 can be made larger than the width W1 of the first contact hole 54-1. The contact hole 54-2 may expose at least a portion of the dummy trench portion 30.

[0201] By increasing the width W2 of the second contact hole 54-2, it becomes easier to fill the inside of the second contact hole 54-2 with the emitter electrode 52 without providing a plug portion such as tungsten, and it becomes easier to connect the emitter electrode 52 with the mesa portion 60-2. In this example, a connecting portion 257 is provided inside the first contact hole 54-1. The connecting portion 257 includes one or both of a plug portion 256 and a barrier metal portion 252. In contrast, a connecting portion 257 is not provided inside the second contact hole 54-2. The inside of the second contact hole 54-2 may be filled with a metal containing aluminum (the main body portion of the emitter electrode 52).

[0202] In this example, the emitter electrode 52 has a titanium-containing barrier metal portion 252 in the portion connected to the mesa portion 60-1, but does not need to contain titanium in the portion connected to the mesa portion 60-2. The portion connected to each mesa portion refers to the portion filled inside the contact hole 54. In addition, the emitter electrode 52 in this example has a tungsten-containing plug portion 256 in the portion connected to the mesa portion 60-1, but does not contain tungsten in the portion connected to the mesa portion 60-2.

[0203] If the barrier metal portion 252 is not provided inside the second contact hole 54-2, ohmic contact can be achieved between the emitter electrode 52 and the contact region 15 even without providing a plug region 221 in the mesa portion 60-2. For this reason, as described above, it becomes easier to omit the plug region 221 in the mesa portion 60-2.

[0204] Figure 44 is an example of a cross-section of the semiconductor device 100 according to the thirteenth embodiment. The cross-section in Figure 44 is at the same position as the b-b cross-section. However, the cross-section in Figure 44 includes one more mesa portion 60 of the transistor portion 70 than the b-b cross-section.

[0205] The semiconductor device 100 in this example differs from other examples described herein in the structure of the second contact hole 54-2 corresponding to the mesa portion 60-2. The structure other than the second contact hole 54-2 is the same as in any of the examples described herein unless otherwise specified. The arrangement of each impurity region in Figure 44 is the same as in the example in Figure 41. In the example in Figure 43, trench contact portions 17 are not provided in each mesa portion, but trench contact portions 17 similar to those in any of the examples described in Figures 1 to 43 may be provided in any of the mesa portions. Also, a plug region 221 is not provided in the mesa portion 60-2, but plug regions 221 may be provided in the other mesa portions.

[0206] In this example, two or more mesa portions 60-2 are arranged side by side in the X-axis direction. Furthermore, the two or more mesa portions 60-2 are connected to the emitter electrode 52 by a common second contact hole 54-2. The second contact hole 54-2 does not have a connecting portion 257.

[0207] In this example, the second contact hole 54-2 is provided across two or more mesa portions 60-2 in the X-axis direction. The second contact hole 54-2 may expose one or more dummy trench portions 30. These dummy trench portions 30 are connected to the emitter electrode 52 that is filled into the second contact hole 54-2. The dummy conductive portion 34 of the dummy trench portion 30 may be connected to the emitter electrode 52, or, if the interlayer insulating film 38 is embedded in the trench, the dummy conductive portion 34 and the emitter electrode 52 may not be connected. In this example, the width of the second contact hole 54-2 in the X-axis direction can be increased, making it easier to fill with a metal such as aluminum. This makes it easier to omit the plug region 221 in the mesa portion 60-2.

[0208] The second distance between the end of the second contact hole 54-2 in the X-axis direction and the dummy trench portion 30 may be the same as, or different from, the first distance between the end of the first contact hole 54-1 in the X-axis direction and the gate trench portion 40. Similar to the example in Figure 43, the second distance may be smaller than the first distance.

[0209] It should be noted that the execution order of operations, procedures, steps, and stages in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not explicitly stated as "before," "prior to," etc., and that these can be performed in any order unless the output of a previous process is used in a later process. Even if the operation flow in the claims, specifications, and drawings is described using phrases such as "first," "next," etc. for convenience, this does not mean that it is mandatory to perform the operations in that order.

[0210] 10... Semiconductor substrate, 12... Emitter region, 14... Base region, 15... Contact region, 16... Storage region, 17... Trench contact region, 18... Drift region, 20... Buffer region, 21... Top surface, 22... Collector region, 23... Bottom surface, 24... Collector electrode, 30... Dummy trench region, 32... Dummy insulating film, 34... Dummy conductive region, 38... Interlayer insulating film, 40... Gate trench region, 42... Gate insulating film, 44... Gate conductive region, 52... Emitter electrode, 54... Contact hole, 60... Mesa section, 61... Mesa section, 62... Mesa section, 70... Transistor section, 72... Boundary region, 80... Diode section, 81... Extension region, 82... Cathode region, 90... Edge termination structure section, 100... Semiconductor device, 130... Outer periphery gate wiring, 131... Active side gate wiring, 160... Active section, 162... Edge, 164... Gate pad, 221... Plug region, 251... Upper section, 252... Barrier metal section, 253... First layer, 254... Second layer, 255... Silicide layer, 256... Plug section, 257... Connection section

Claims

1. A semiconductor device provided on a semiconductor substrate having an upper surface and a lower surface and a drift region of a first conductivity type, comprising a transistor portion and a diode portion, wherein the transistor portion comprises one or more gate trench portions provided from the upper surface to the interior of the semiconductor substrate, a plurality of dummy trench portions provided from the upper surface to the interior of the semiconductor substrate, a gate-adjacent mesa portion provided in contact with any of the gate trench portions inside the semiconductor substrate, and a dummy-inter-mesa portion provided inside the semiconductor substrate between two dummy trench portions, wherein the gate-adjacent mesa portion comprises a base region of a second conductivity type provided between the drift region and the upper surface, an emitter region of a first conductivity type provided exposed on the upper surface, and a contact region of a second conductivity type with a higher density than the base region provided exposed on the upper surface, wherein the dummy-inter-mesa portion comprises a first region of a first conductivity type provided exposed on the upper surface, and a second region of a second conductivity type provided exposed on the upper surface. A semiconductor device in which the total amount of impurities of a second conductivity type contained in the second region of one dummy intermesa portion is smaller than the total amount of impurities of a second conductivity type contained in the contact region of one gate adjacent mesa portion.

2. The semiconductor device according to claim 1, wherein in the second region included in one of the dummy intermesa portions, the area of ​​the contact region with a higher density than the base region is zero, or smaller than the area of ​​the contact region included in one of the gate adjacent mesa portions.

3. The semiconductor device according to claim 2, wherein the dummy intermesa portion and the gate adjacent mesa portion have an elongated length in the first direction of the upper surface, and in each of the dummy intermesa portion and the gate adjacent mesa portion, a plurality of contact regions are discretely arranged in the first direction, and the number of contact regions included in one dummy intermesa portion is less than the number of contact regions included in one gate adjacent mesa portion.

4. The semiconductor device according to claim 2, wherein the dummy intermesa portion and the gate adjacent mesa portion have a longitudinal length in the first direction of the upper surface, and in each of the dummy intermesa portion and the gate adjacent mesa portion, a plurality of contact regions are discretely arranged in the first direction, and the length of one contact region in the dummy intermesa portion in the first direction is shorter than the length of one contact region in the gate adjacent mesa portion in the first direction.

5. The semiconductor device according to claim 2, wherein the area of ​​the first region included in one of the dummy intermesa portions on the upper surface is smaller than the area of ​​the emitter region included in one of the gate adjacent mesa portions.

6. The semiconductor device according to claim 5, wherein the dummy intermesa portion and the gate adjacent mesa portion have an elongation in the first direction of the upper surface, a plurality of emitter regions are discretely arranged in the first direction in the gate adjacent mesa portion, a plurality of first regions are discretely arranged in the first direction in the dummy intermesa portion, and the number of first regions included in one dummy intermesa portion is less than the number of emitter regions included in one gate adjacent mesa portion.

7. The semiconductor device according to claim 6, wherein the dummy intermesa portion and the gate adjacent mesa portion have a longitudinal length in the first direction of the upper surface, a plurality of emitter regions are discretely arranged in the first direction in the gate adjacent mesa portion, a plurality of first regions are discretely arranged in the first direction in the dummy intermesa portion, and the length of one first region in the first direction in the dummy intermesa portion is shorter than the length of one emitter region in the gate adjacent mesa portion in the first direction.

8. The semiconductor device according to claim 2, wherein the plurality of dummy trench portions are arranged side by side in a second direction on the upper surface, and the inter-dummy mesa portion has a second region with a lower concentration than the contact region, at a position facing the contact region provided in the gate-adjacent mesa portion in the second direction.

9. The semiconductor device according to claim 8, wherein the dummy inter-mesa portion has the first region positioned opposite the emitter region provided in the gate-adjacent mesa portion in the second direction.

10. The semiconductor device according to any one of claims 1 to 9, wherein the area of ​​the base region included in one of the dummy intermesa portions on the upper surface is greater than the area of ​​the base region included in one of the gate adjacent mesa portions.

11. The semiconductor device according to claim 1, wherein the second region has a lower concentration than the contact region.

12. The semiconductor device according to claim 11, wherein the plurality of dummy trench portions are arranged in a line in the second direction on the upper surface, and the second region is located opposite the contact region provided in the gate-adjacent mesa portion in the second direction.

13. The semiconductor device according to claim 12, wherein the first region is located in a position opposite the emitter region provided in the gate-adjacent mesa portion in the second direction.

14. The semiconductor device according to any one of claims 11 to 13, wherein the second region is the base region.

15. The semiconductor device according to claim 1, wherein the gate-adjacent mesa portion is provided in the contact region from the upper surface to the interior of the semiconductor substrate and has a first trench contact portion made of metal, and the dummy-intermesa portion is provided in the second region from the upper surface to a depth greater than the first trench contact portion and has a second trench contact portion made of metal.

16. The semiconductor device according to claim 1, further comprising an upper electrode provided above the semiconductor substrate, wherein the dummy intermesa portion is provided in the second region from the upper surface to the interior of the semiconductor substrate, is made of metal, and has a second trench contact portion connected to the upper electrode, and the contact region of the gate adjacent mesa portion is connected to the upper electrode on the upper surface.

17. The semiconductor device according to claim 15 or 16, wherein the second trench contact portion is formed to a lower extent than the second region.

18. The semiconductor device according to claim 1, further comprising an upper electrode provided above the semiconductor substrate, wherein the contact region is provided at a position connected to the upper electrode and has a second conductivity type plug region having a higher density than other parts of the contact region, and the density of the second region at the position connected to the upper electrode is lower than that of the plug region.

19. The semiconductor device according to claim 18, wherein the plurality of dummy trench portions are arranged side by side in a second direction on the upper surface, and in the second direction, the width of the inter-dummy mesa portion in contact with the upper electrode is greater than the width of the gate-adjacent mesa portion in contact with the upper electrode.

20. The semiconductor device according to claim 18 or 19, wherein the upper electrode has a titanium-containing barrier metal in the portion connected to the gate-adjacent mesa portion, and does not contain titanium in the portion connected to the dummy-intermesa portion.

21. The semiconductor device according to claim 18 or 19, wherein the upper electrode has a plug portion containing tungsten in the portion that connects to the gate-adjacent mesa portion, and the portion that connects to the dummy-intermesa portion does not contain tungsten.

22. The semiconductor device according to claim 18 or 19, further comprising an interlayer insulating film provided between the upper electrode and the semiconductor substrate, wherein two or more dummy inter-mesa portions are arranged side by side in a second direction on the upper surface, and the two or more dummy inter-mesa portions are connected to the upper electrode by a common contact hole provided in the interlayer insulating film.

23. A semiconductor device provided on a semiconductor substrate having an upper surface and a lower surface and having a drift region of a first conductivity type, comprising a transistor portion and a diode portion, wherein the transistor portion comprises one or more gate trench portions provided from the upper surface to the interior of the semiconductor substrate, a plurality of dummy trench portions provided from the upper surface to the interior of the semiconductor substrate, a gate-adjacent mesa portion provided in contact with any of the gate trench portions inside the semiconductor substrate, and a dummy-inter-mesa portion sandwiched between two dummy trench portions inside the semiconductor substrate, wherein the gate-adjacent mesa portion has a base region of a second conductivity type provided between the drift region and the upper surface, and a contact region of a second conductivity type with a higher density than the base region, the plurality of dummy trench portions are arranged side by side in a second direction on the upper surface, and the dummy-inter-mesa portion has a first region of a first conductivity type at a position facing the contact region provided in the gate-adjacent mesa portion in the second direction.

24. The semiconductor device according to claim 23, wherein the dummy intermesa portion and the gate adjacent mesa portion have an elongated length in the first direction of the upper surface, the gate adjacent mesa portion has an emitter region of a first conductivity type with a higher concentration than the drift region on the upper surface, and the dummy intermesa portion also has the first region at a position facing the emitter region provided in the gate adjacent mesa portion in the second direction.

25. The semiconductor device according to claim 24, wherein the first region of the dummy intermesa portion includes the emitter region.

26. The semiconductor device according to claim 24, wherein the first region of the dummy intermesa portion includes the drift region.

27. The semiconductor device according to claim 24, wherein the dummy intermesa portion has the emitter region at a position facing the emitter region provided in the gate adjacent mesa portion in the second direction, and the drift region at a position facing the contact region provided in the gate adjacent mesa portion in the second direction.

28. The semiconductor device according to claim 26 or 27, wherein the dummy intermesa portion does not have the base region below the first region which is the drift region.

29. The semiconductor device according to claim 25 or 27, wherein the dummy intermesa portion has a trench contact portion of conductive material provided through the emitter region.

30. A semiconductor device provided on a semiconductor substrate having an upper surface and a lower surface and a drift region of a first conductivity type, comprising a transistor portion and a diode portion, wherein the transistor portion comprises one or more gate trench portions provided from the upper surface to the interior of the semiconductor substrate, a plurality of dummy trench portions provided from the upper surface to the interior of the semiconductor substrate, a dummy intergate mesa portion sandwiched between the gate trench portion and the dummy trench portion, and a dummy intergate mesa portion sandwiched between two dummy trench portions, wherein the dummy intergate mesa portion comprises a base region of a second conductivity type provided between the drift region and the upper surface, and a contact region of a second conductivity type with a higher concentration than the base region, wherein on the upper surface, the area of ​​the contact region of the dummy intergate mesa portion is 0, or smaller than the area of ​​the contact region of the dummy intergate mesa portion.

31. The semiconductor device according to claim 30, wherein the plurality of dummy trench portions are arranged side by side in a second direction on the upper surface, and the dummy inter-mesa portion has a second region of a second conductivity type with a lower concentration than the contact region, at a position facing the contact region provided in the dummy inter-gate mesa portion in a second direction.

32. The semiconductor device according to claim 31, wherein the dummy gate mesa portion is provided exposed on the upper surface and has an emitter region of a first conductivity type with a higher concentration than the drift region, and the dummy gate mesa portion also has a second region at a position facing the emitter region provided in the dummy gate mesa portion in the second direction.

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