Semiconductor device

Abstract

This semiconductor device includes: an SiC chip that has a main surface having set therein an active region in which an element structure is formed and an outer peripheral region which is located around the active region; a first impurity region that exhibits a first conductivity type and that is formed in a surface layer portion of the main surface; a second impurity region that exhibits a second conductivity type, that has a first concentration, and that is formed in a surface layer portion of the first impurity region at the outer peripheral region; and a separation impurity region that separates the first impurity region from the second impurity region at the outer peripheral region and that has a second concentration lower than the first concentration.

Description

Semiconductor equipment Related applications

[0001] This application corresponds to Japanese Patent Application No. 2024-188782, filed with the Japan Patent Office on 28 October 2024, and the full disclosure of this application is incorporated herein by reference.

[0002] This disclosure relates to semiconductor devices.

[0003] Patent Document 1 discloses a semiconductor device comprising an n-type SiC epitaxial layer, a source metal on the SiC epitaxial layer, a passivation film made of an organic insulator arranged to cover the source metal, an end insulating film extending from a dicing region set at the end of the SiC epitaxial layer toward the source metal and positioned below the passivation film, and a metal-under insulating film positioned below the source metal, wherein the distance from the end of the dicing region in the end insulating film toward the passivation film is longer than the distance extending from the end of the passivation film toward the source metal in the end insulating film.

[0004] Japanese Patent Publication No. 2018-093209

[0005] [Summary] One embodiment of the present disclosure provides a semiconductor device comprising: a SiC chip having a main surface with an active region on which an element structure is formed and an outer peripheral region surrounding the active region; a first impurity region of a first conductivity type formed on the surface layer of the main surface; a second impurity region of a second conductivity type having a first concentration formed on the surface layer of the first impurity region in the outer peripheral region; and a separated impurity region having a second concentration lower than the first concentration, separating the first impurity region and the second impurity region in the outer peripheral region.

[0006] Figure 1 is a plan view showing a semiconductor device according to one embodiment of the present disclosure. Figure 2 is a cross-sectional view taken along the line II-II shown in Figure 1. Figure 3 is a perspective view showing an example of chip layout. Figure 4A is an enlarged plan view of the main part of the SiC chip. Figure 4B is a cross-sectional view taken along the line IVB-IVB shown in Figure 4A. Figure 5 is a plan view showing the main part of the active region. Figure 6 is a perspective view showing the main part of the active region. Figure 7 is a perspective view showing the main part of the active region. Figure 8 is a cross-sectional view showing the main part of the active region. Figure 9 is a perspective view showing a modified example of the device structure. Figure 10 is a perspective view showing a modified example of the device structure. Figure 11 is a plan view showing an example of the layout of the outer periphery structure. Figure 12 is a cross-sectional view taken along the line XII-XII shown in Figure 11. Figure 13 is a cross-sectional view taken along the line XIII-XIII shown in Figure 11. Figure 14 is a plan view showing an example of the layout of the outer periphery structure. Figure 15 is a plan view showing an example of the layout of the outer periphery structure. Figure 16 is a cross-sectional view taken along the line XVI-XVI shown in Figure 15. Figure 17 is a plan view showing an example of the layout of the outer perimeter structure. Figure 18 is a cross-sectional view showing a modified example of the outer perimeter structure. Figure 19 is a cross-sectional view showing a modified example of the outer perimeter structure. Figure 20 is a cross-sectional view showing a modified example of the outer perimeter structure. Figure 21 is a cross-sectional view showing a modified example of the outer perimeter structure. Figure 22 is a cross-sectional view showing a modified example of the outer perimeter structure. Figure 23 is a cross-sectional view showing a modified example of the outer perimeter structure. Figure 24 is a cross-sectional view showing a modified example of the outer perimeter structure. Figure 25 is a cross-sectional view showing a modified example of the outer perimeter structure. Figure 26 is a cross-sectional view showing a modified example of the outer perimeter structure.

[0007] [Detailed Description] Next, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0008] The embodiments will now be described in detail with reference to the attached drawings. The attached drawings are schematic diagrams and not strictly accurate; the scale, proportions, angles, etc., do not necessarily correspond. Corresponding structures in the attached drawings are denoted by the same reference numerals, and redundant descriptions are omitted or simplified. For structures whose descriptions are omitted or simplified, the description given before the omission or simplification applies.

[0009] Where the word "substantially" is used in this specification, it includes not only numerical values ​​(forms) that are equal to the numerical values ​​(forms) being compared, but also numerical errors (form errors) within a range of ±10% from the numerical values ​​(forms) being compared. In the following descriptions, words such as "first," "second," and "third" are used, but these are symbols attached to the names of each structure to clarify the order of explanation and are not intended to limit the names of each structure.

[0010] In the following description, the conductivity type of a semiconductor (impurity) is indicated using "p-type" or "n-type," but "p-type" may be referred to as the "first conductivity type" and "n-type" as the "second conductivity type." Of course, "n-type" may also be referred to as the "first conductivity type" and "p-type" as the "second conductivity type." "p-type" is the conductivity type due to trivalent elements, and "n-type" is the conductivity type due to pentavalent elements. Unless otherwise specified, trivalent elements are at least one of boron, aluminum, gallium, and indium. Unless otherwise specified, pentavalent elements are at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0011] (1) The overall configuration diagram 1 of the semiconductor device 1 is a plan view showing a semiconductor device 1 according to one embodiment of the present disclosure. Figure 2 is a cross-sectional view taken along the line II-II shown in Figure 1. Figure 3 is a perspective view showing an example of the layout of the chip 2. Figure 4A is an enlarged plan view of the main part of the SiC chip. Figure 4B is a cross-sectional view taken along the line IVB-IVB shown in Figure 4A.

[0012] Referring to Figures 1 to 3, the semiconductor device 1 includes a chip 2 containing a SiC single crystal. The chip 2 may also be referred to as a "SiC chip" or "semiconductor chip". In this embodiment, the chip 2 is made of a hexagonal SiC single crystal and is formed in a rectangular parallelepiped shape. The hexagonal SiC single crystal has multiple polytypes, including 2H (Hexagonal)-SiC single crystals, 4H-SiC single crystals, 6H-SiC single crystals, etc. In this embodiment, an example is shown in which the chip 2 is made of a 4H-SiC single crystal, but the chip 2 may be made of other polytypes.

[0013] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a rectangular shape in a plan view from the vertical direction Z (hereinafter simply referred to as "plan view"). The vertical direction Z is also the thickness direction of the chip 2 and the normal direction of the first main surface 3 (second main surface 4). The first main surface 3 and the second main surface 4 may be formed in a square or rectangular shape in a plan view.

[0014] The first main surface 3 and the second main surface 4 are preferably formed by the c-plane of the SiC single crystal. In this case, the first main surface 3 is preferably formed by the silicon plane ((0001) plane) of the SiC single crystal, and the second main surface 4 is preferably formed by the carbon plane ((000-1) plane) of the SiC single crystal.

[0015] With respect to the circumferential direction of the chip 2, starting from the first side surface 5A (counterclockwise in Figure 1), the second side surface 5B is connected to the first side surface 5A, the third side surface 5C is connected to the second side surface 5B, and the fourth side surface 5D is connected to the first side surface 5A and the third side surface 5C. The first side surface 5A and the third side surface 5C extend in a first direction X along the first main surface 3 and face a second direction Y that intersects (specifically orthogonal to) the first direction X. The second side surface 5B and the fourth side surface 5D extend in the second direction Y and face the first direction X.

[0016] In this configuration, the first direction X is the a-axis direction ([11-20] direction) of the SiC single crystal, and the second direction Y is the m-axis direction ([1-100] direction) of the SiC single crystal. Of course, the first direction X may be the m-axis direction of the SiC single crystal, and the second direction Y may be the a-axis direction of the SiC single crystal.

[0017] The XY plane, which includes the first direction X and the second direction Y, forms a horizontal plane perpendicular to the vertical direction Z. Hereafter, the axis extending along the vertical direction Z may be referred to as the "vertical axis." Also below, the first direction X and the second direction Y may be referred to as the "horizontal direction." The horizontal direction is also the direction extending along the first principal plane 3.

[0018] The semiconductor device 1 includes an n-type first semiconductor layer 6 formed in the surface layer portion of the second main surface 4. A drain potential as a first potential (high potential) is applied to the first semiconductor layer 6. The first semiconductor layer 6 may be referred to as a "semiconductor region (layer)", "base region (layer)", "drain region (layer)", or the like.

[0019] The first semiconductor layer 6 extends in a layer shape along the second main surface 4, and forms the second main surface 4 and the first to fourth side surfaces 5A to 5D. In this form, the first semiconductor layer 6 is composed of an n-type semiconductor layer. Specifically, the first semiconductor layer 6 is composed of a substrate (SiC substrate) including a SiC single crystal (semiconductor single crystal), and has the second main surface 4 and the first to fourth side surfaces 5A to 5D. In this form, the first semiconductor layer 6 is composed of a substrate made of a SiC single crystal (that is, a SiC substrate).

[0020] The first semiconductor layer 6 may have a peak value of an n-type impurity concentration of 1×10 １８ cm －３ or more and 1×10 ２１ cm －３ or less. The first semiconductor layer 6 preferably has a substantially constant n-type impurity concentration in the thickness direction.

[0021] The first semiconductor layer 6 may have a first thickness T1 of 10 μm or more and 500 μm or less. The first thickness T1 may have a value belonging to at least one of the ranges of 10 μm or more and 50 μm or less, 50 μm or more and 100 μm or less, 100 μm or more and 150 μm or less, 150 μm or more and 2,00 μm or less, 200 μm or more and 300 μm or less, 300 μm or more and 400 μm or less, and 400 μm or more and 500 μm or less.

[0022] The semiconductor device 1 includes an n-type second semiconductor layer 7 formed in the surface layer portion of the first main surface 3. The second semiconductor layer 7 may be referred to as a "semiconductor region (layer)", "drift region (layer)", or the like. The second semiconductor layer 7 extends in a layer shape along the first main surface 3, and forms the first main surface 3 and the first to fourth side surfaces 5A to 5D.

[0023] In this form, the second semiconductor layer 7 is composed of an n-type semiconductor layer. Specifically, the second semiconductor layer 7 is composed of an epitaxial layer (SiC epitaxial layer) containing a SiC single crystal (semiconductor single crystal). The second semiconductor layer 7 is composed of an epitaxial layer (i.e., SiC epitaxial layer) grown epitaxially starting from the first semiconductor layer 6.

[0024] The second semiconductor layer 7 has a lower end and an upper end. The lower end of the second semiconductor layer 7 is the starting point of crystal growth, and the upper end of the second semiconductor layer 7 is the end point of crystal growth. The lower end of the second semiconductor layer 7 is also the bottom of the second semiconductor layer 7. Since the second semiconductor layer 7 is continuously grown epitaxially from the first semiconductor layer 6, the lower end of the second semiconductor layer 7 coincides with the upper end of the first semiconductor layer 6.

[0025] The second semiconductor layer 7 includes an n-type drift region 8. In this form, the drift region 8 is formed by a part (n-type part) of the second semiconductor layer 7.

[0026] The boundary between the first semiconductor layer 6 and the second semiconductor layer 7 is not necessarily visible and can be evaluated and / or determined indirectly from other configurations and elements.

[0027] The n-type impurity concentration of the second semiconductor layer 7 (drift region 8) is preferably less than the n-type impurity concentration of the first semiconductor layer 6. The second semiconductor layer 7 may have a peak value of n-type impurity concentration of 1×10 １５ cm －３ or more and 5×10 １６ cm －３ or less. The n-type impurity concentration of the second semiconductor layer 7 may be substantially constant in the thickness direction. Of course, the n-type impurity concentration of the second semiconductor layer 7 may have a concentration gradient that gradually increases and / or decreases in the thickness direction (crystal growth direction) of the chip 2.

[0028] The second semiconductor layer 7 has a second thickness T2 less than the first thickness T1. The second thickness T2 may be 5 μm or more and 15 μm or less. The second thickness T2 may have a value belonging to at least one of the ranges of 5 μm or more and 7.5 μm or less, 7.5 μm or more and 10 μm or less, 10 μm or more and 12.5 μm or less, and 12.5 μm or more and 15 μm or less.

[0029] Referring to Figures 3, 4A, and 4B, the main surface 14 (substrate surface) of the first semiconductor layer 6 has an off-angle θoff, which is inclined at a predetermined angle in a predetermined off-direction Doff with respect to the c-plane of the SiC single crystal, and the direction of its normal vector n does not coincide with the direction of the c-axis (

[0001] axis). In other words, the c-axis ((0001) axis) of the SiC single crystal is inclined by an off-angle θoff from the vertical axis toward the off-direction Doff. Also, the c-plane of the SiC single crystal is inclined by an off-angle θoff with respect to the horizontal plane.

[0030] The off-direction Doff refers to the direction in which the normal n of the first semiconductor layer 6 is inclined with respect to the

[0001] axis, and is indicated by the direction of the vector obtained by projecting the normal n from the

[0001] axis onto the (0001) plane. In this embodiment, it is preferable that the direction of the projection vector of the normal n coincides with the a-axis ([11-20] axis), and the off-direction Doff is in the a-axis direction (first direction X) of the SiC single crystal. The off-angle θoff may be greater than 0° and less than or equal to 10°. The off-angle θoff may have a value that falls within any one of the following ranges: greater than 0° and less than or equal to 1°, 1° or more and less than or equal to 2.5°, 2.5° or more and less than or equal to 5°, 5° or more and less than or equal to 7.5°, and 7.5° or more and less than or equal to 10°.

[0031] The off-angle θoff is preferably 5° or less. The off-angle θoff is particularly preferably 2° or more and 4.5° or less. The off-angle θoff is typically set in the range of 4° ± 0.1°. Of course, this specification does not exclude the form in which the off-angle θoff is 0° (i.e., the form in which the main surface 14 is a just surface with respect to the c surface).

[0032] As a result, the first semiconductor layer 6 is formed from a flat terrace surface 30 composed of a (0001) plane and a stepped portion of the terrace surface 30 that is created when the first main surface 3 is tilted with respect to the (0001) plane (off angle θ). The stepped portion has a step surface 31 which is a (11-20) plane perpendicular to the [11-20] axis. The height of the stepped portion (step height h) corresponds to a layer 32 (bi-layer) of Si-C pairs in which a carbon atom is bonded to one silicon atom, and is 0.25 nm.

[0033] As shown in Figure 4B, the step surfaces 31 of each layer 32 are arranged regularly in the [11-20] axis direction while maintaining the width of the terrace surface 30. Also, as shown in Figure 4A, the step lines 33, which are the step edges of the step surfaces 31, are arranged parallel to the terrace surface 30 while maintaining a relationship perpendicular to the [11-20] axis direction (in other words, a relationship parallel to the [-1100] axis direction). The second semiconductor layer 7 is formed by crystal growth of each layer 32 laterally along the [11-20] axis direction while maintaining the terrace surfaces 30 and step surfaces 31 of the first semiconductor layer 6.

[0034] The semiconductor device 1 includes an active region 9 set on the chip 2. The active region 9 is set in the inner part of the chip 2, spaced apart from the periphery (first to fourth side surfaces 5A to 5D) of the chip 2 in a plan view. The active region 9 is set in a polygonal shape (a quadrilateral shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view. Preferably, the planar area of ​​the active region 9 is 50% to 90% of the planar area of ​​the first main surface 3.

[0035] The semiconductor device 1 includes an outer peripheral region 10 set outside the active region 9 on the chip 2. The outer peripheral region 10 is located in the area between the periphery of the chip 2 and the active region 9 in a plan view. In a plan view, the outer peripheral region 10 extends in a band shape along the active region 9 and is set in a polygonal ring (a quadrilateral ring in this embodiment) surrounding the active region 9.

[0036] Referring to Figures 2 and 3, the semiconductor device 1 includes a plurality of trench electrode-type trench structures 11 formed on the first main surface 3 in the active region 9. The trench structures 11 may also be referred to as "gate structures," "trench gate structures," etc. A gate potential is applied to the plurality of trench structures 11 as a control potential. The plurality of trench structures 11 provide an MIS (Metal Insulator Semiconductor) transistor structure Tr in the active region 9.

[0037] The multiple trench structures 11 are arranged at intervals from the periphery of the active region 9 inward. In this configuration, the multiple trench structures 11 are arranged at intervals in the second direction Y and each is formed in a strip shape extending in the first direction X. In other words, the multiple trench structures 11 are arranged at intervals in the m-axis direction and each extends in the a-axis direction.

[0038] Furthermore, in this configuration, the multiple trench structures 11 are arranged in a stripe-like pattern extending in the a-axis direction (first direction X). The multiple trench structures 11 are formed with gaps between them from the lower end of the second semiconductor layer 7 (first semiconductor layer 6) toward the first main surface 3, and face the first semiconductor layer 6 with a portion of the second semiconductor layer 7 in between.

[0039] The semiconductor device 1 includes a plurality of p-type bottom wells 12 formed horizontally spaced apart within the second semiconductor layer 7 of the active region 9. Specifically, each of the plurality of bottom wells 12 is formed at the bottom of the trench structure 11.

[0040] The semiconductor device 1 includes p-type field relaxation rings 15 formed on the surface layer of the first main surface 3 in the outer peripheral region 10 (the peripheral edge of the first main surface 3). The number of field relaxation rings 15 is typically between 3 and 8. The multiple field relaxation rings 15 are formed in an electrically floating state and relax the electric field within the chip 2 at the peripheral edge of the first main surface 3. The number, width, depth, and p-type impurity concentration of the field relaxation rings 15 are arbitrary and can take various values ​​depending on the electric field to be relaxed. The field relaxation rings 15 may also be called "field regions," "field rings," "guard rings," etc.

[0041] Referring to Figure 3, the multiple field relaxation rings 15 are formed at intervals in the region between the periphery of the tip 2 and the active region 9. The multiple field relaxation rings 15 are formed in a band shape that extends along the active region 9 in a plan view. In this embodiment, the multiple field relaxation rings 15 are formed in an annular shape (specifically, a square annular shape) that surrounds the active region 9 in a plan view.

[0042] Referring to Figure 2, the semiconductor device 1 includes a p-type peripheral impurity region 34 formed on the surface layer of the first main surface 3 in the outer peripheral region 10 (the peripheral edge of the first main surface 3). The peripheral impurity region 34 is formed in an electrically floating state to prevent discharge on the first main surface 3 side of the chip 2.

[0043] Referring to Figure 2, the semiconductor device 1 includes a p-type separation impurity region 35 formed on the surface layer of the first main surface 3 in the outer peripheral region 10 (periphery of the first main surface 3). The separation impurity region 35 is formed in an electrically floating state, physically separating the peripheral impurity region 34 from the drift region 8 and preventing contact between the peripheral impurity region 34 and the drift region 8.

[0044] A detailed explanation of the peripheral impurity region 34 and the separated impurity region 35 will be given later with reference to Figures 11 to 26. Also, in Figure 3, the peripheral impurity region 34 and the separated impurity region 35 are omitted.

[0045] The semiconductor device 1 includes an interlayer insulating film 16 that covers the first main surface 3. The interlayer insulating film 16 may also be called an "insulating film," "interlayer film," or "intermediate insulating film." The interlayer insulating film 16 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0046] Referring to Figure 1, the semiconductor device 1 includes a gate pad 17 disposed on an interlayer insulating film 16. The gate pad 17 is an electrode to which a gate potential is applied from the outside. The gate pad 17 may also be called a "gate pad electrode," "first pad electrode," etc. The gate pad 17 may have a laminated structure including a Ti-based metal film and an Al-based metal film stacked in this order from the interlayer insulating film 16 side.

[0047] In this embodiment, the gate pad 17 is positioned on the portion of the interlayer insulating film 16 that covers the active region 9. The gate pad 17 may also be positioned at a distance from the outer peripheral region 10 toward the active region 9. In this embodiment, the gate pad 17 is positioned on the periphery of the active region 9 in a plan view.

[0048] Figure 1 shows an example in which the gate pad 17 is positioned in a region along the center of the second side surface 5B at the periphery of the active region 9. The gate pad 17 may also be positioned in a region along the center of any of the first to fourth side surfaces 5A to 5D. The gate pad 17 may be positioned at any corner of the active region 9 in a plan view. Alternatively, the gate pad 17 may be positioned in the center of the active region 9 in a plan view. In this embodiment, the gate pad 17 is formed in a rectangular shape in a plan view.

[0049] The semiconductor device 1 includes at least one (or more in this embodiment) gate wiring 18 drawn from a gate pad 17 onto an interlayer insulating film 16. The gate wiring 18 may be referred to as "wiring," "wiring electrode," "finger electrode," "gate finger," etc. The plurality of gate wirings 18 may have a laminated structure including a Ti-based metal film and an Al-based metal film stacked in this order from the interlayer insulating film 16 side. In this embodiment, the plurality of gate wirings 18 include a first gate wiring 18A and a second gate wiring 18B.

[0050] The first gate wiring 18A is drawn out from the gate pad 17 toward the first side surface 5A and extends in a line along the periphery of the active region 9. The first gate wiring 18A is electrically connected to one end of the plurality of trench structures 11.

[0051] The second gate wiring 18B is drawn out from the gate pad 17 toward the third side surface 5C and extends in a line along the periphery of the active region 9. The second gate wiring 18B is electrically connected to the other ends of the multiple trench structures 11.

[0052] The semiconductor device 1 includes a source pad 19 disposed on the interlayer insulating film 16 at a distance from the gate pads 17 and gate wiring 18. The source pad 19 is an electrode to which a source potential is applied from the outside. The source pad 19 may also be called a "source pad electrode," "second pad electrode," etc. The source pad 19 may have a laminated structure including a Ti-based metal film and an Al-based metal film stacked in this order from the interlayer insulating film 16 side.

[0053] The source pad 19 is positioned on the portion of the interlayer insulating film 16 that covers the active region 9. The source pad 19 may be positioned at a distance from the outer peripheral region 10 toward the active region 9. In this embodiment, the source pad 19 is formed in a polygonal shape with a recess that is recessed along the gate pad 17 in a plan view. Of course, the source pad 19 may be formed in a rectangular shape in a plan view.

[0054] The semiconductor device 1 includes a drain pad 20 covering the second main surface 4. The drain pad 20 is an electrode to which a drain potential is applied from the outside. The drain pad 20 may also be referred to as the "drain pad electrode," "third pad electrode," etc. The drain pad 20 forms ohmic contact with the first semiconductor layer 6 exposed from the second main surface 4. In other words, the drain pad 20 is electrically connected to the drift region 8 via the first semiconductor layer 6.

[0055] The drain pad 20 may cover the entire area of ​​the second main surface 4 so as to be continuous with the periphery (first to fourth side surfaces 5A to 5D) of the chip 2. Alternatively, the drain pad 20 may cover the second main surface 4 with a gap inward from the periphery of the chip 2 so as to expose the periphery of the chip 2.

[0056] The breakdown voltage that can be applied between the source pad 19 and the drain pad 20 (between the first main surface 3 and the second main surface 4) may be 500V or more and 3000V or less. The breakdown voltage may have a value that falls within any one of the following ranges: 500V or more and 1000V or less, 1000V or more and 1500V or less, 1500V or more and 2000V or less, 2000V or more and 2500V or more and 3000V or less.

[0057] (2) Detailed structural diagram 5 of the active region 9 of the semiconductor device 1 is a plan view showing the main part of the active region 9. Figures 6 and 7 are perspective views showing the main part of the active region 9. Figure 6 shows a cross-section that appears near the center in the extending direction of the trench 22, and Figure 7 shows a cross-section that appears near the end 61 in the extending direction of the trench 22. Figure 8 is a cross-sectional view showing the main part of the active region 9, and corresponds to the perspective view of Figure 6.

[0058] Referring to FIGS. 6 to 8, the semiconductor device 1 includes a p-type body region 21 formed in the surface layer portion of the drift region 8. In this embodiment, the body region 21 is formed in a layer shape extending along the first main surface 3. The body region 21 may be formed over the entire surface layer portion of the drift region 8 and may be exposed from the first to fourth side surfaces 5A to 5D. The body region 21 is formed at a distance from the lower end of the second semiconductor layer 7 toward the first main surface 3 side.

[0059] The body region 21 may have a peak value of a p-type impurity concentration of 1×10 １５ cm －３ or more and 1×10 １８ cm －３ or less. The p-type impurity concentration of the body region 21 is preferably adjusted by at least one trivalent element. The trivalent element of the body region 21 may be at least one of boron, aluminum, gallium, and indium.

[0060] As described above, the semiconductor device 1 includes the trench structure 11. Referring to FIG. 5, each trench structure 11 has a trench width WT in the array direction. The trench width WT is preferably less than the second thickness T2 (see FIG. 3) of the second semiconductor layer 7. The trench width WT may be 0.2 μm or more and 1.5 μm or less.

[0061] The trench structure 11 has a trench depth DT in the vertical direction Z. The trench depth DT is preferably less than the second thickness T2 of the second semiconductor layer 7. The trench depth DT is preferably larger than the trench width WT. That is, it is preferable that the plurality of trench structures 11 each have an aspect ratio DT / WT extending in a vertically long columnar shape. The aspect ratio DT / WT is the ratio of the trench width WT to the trench depth DT. The aspect ratio DT / WT may be, for example, 1 or more and 5 or less, and preferably 1 or more and 3 or less. The trench depth DT may be 0.5 μm or more and 3.0 μm or less.

[0062] Referring to Figures 6 and 7, the multiple trench structures 11 are arranged in the second direction Y with a trench pitch PT spacing between them. Preferably, the trench pitch PT is less than the second thickness T2 of the second semiconductor layer 7. The trench pitch PT may be 0.5 μm or more and 6.0 μm or less.

[0063] Each trench structure 11 includes a trench 22, a trench insulating film 23, and an embedded conductive layer 24. The trench 22 may be referred to as an "element trench," "gate trench," etc. The trench insulating film 23 may be referred to as an "element insulating film," "gate insulating film," etc. The embedded conductive layer 24 may be referred to as an "embedded electrode," "gate electrode," etc.

[0064] The trenches 22 are formed on the first main surface 3 and define the inner surface of the trench structure 11 (the side surfaces 25 and bottom surface 26 shown in Figures 6 to 8). Preferably, the bottom surface 26 of the trenches 22 has a flat, extending portion. Between adjacent trenches 22, a mesa portion 27 is formed by a part of the second semiconductor layer 7. The mesa portion 27 provides a unit cell UC of the trench gate type transistor. The mesa portion 27 may also be called an "element mesa portion".

[0065] As shown in Figure 5, the multiple trench structures 11 (multiple trenches 22) and multiple mesa portions 27 are strip-shaped extending along the first direction X and are arranged alternately in the second direction Y. The multiple trenches 22 and multiple mesa portions 27 are arranged in a stripe pattern as a whole. The mesa width WM of the mesa portions 27 is preferably wider than the trench width WT. The mesa width WM may be 0.4 μm or more and 3.0 μm or less.

[0066] The trench insulating film 23 covers the inner surface of the trench 22. The trench insulating film 23 may contain at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the trench insulating film 23 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the trench insulating film 23 contains a silicon oxide film made of the oxide of the chip 2.

[0067] The embedded conductive layer 24 is embedded in the trench 22 and faces the channel with the trench insulating film 23 in between. In this embodiment, the embedded conductive layer 24 faces the body region 21 with the trench insulating film 23 in between. The embedded conductive layer 24 may contain p-type or n-type conductive polysilicon.

[0068] As described above, the semiconductor device 1 includes a bottom well 12. The bottom well 12 is formed at the bottom of the trench structure 11. More specifically, the bottom well 12 is formed at the bottom of the trench 22. The bottom well 12 is exposed from the bottom surface 26 of the trench 22 and is in contact with the trench insulating film 23. Therefore, the upper end of the bottom well 12 is exposed to the bottom surface 26 of the trench structure 11 (trench 22). The bottom well 12 mitigates the electric field applied to the bottom of the trench 22. The bottom well 12 may also be referred to as an "electric field relaxation region," "electric field relaxation layer," "bottom electric field relaxation region," "bottom electric field relaxation layer," etc.

[0069] The bottom well 12 faces the embedded conductive layer 24 via the trench insulating film 23 in the depth direction of the trench 22. At the bottom of the trench 22, the trench insulating film 23 is sandwiched between the embedded conductive layer 24 and the bottom well 12.

[0070] The bottom well 12 is formed at the bottom of the trench 22 over its entire length in the direction of extension of the trench 22 and is formed in a strip shape extending in the direction of extension of the trench 22. Referring to Figure 8, the bottom well 12 is formed in the width direction of the trench 22, straddling one end of the trench 22 and the other end of the trench 22. In this embodiment, the bottom well 12 has one side formed in the depth direction of the trench 22 that is substantially coplanar with one side 25 in the width direction of the trench 22, and the other side formed in the width direction of the trench 22 that is substantially coplanar with the other side 25 in the width direction of the trench 22.

[0071] The impurity concentration in the bottom well 12 may be higher than the impurity concentration in the body region 21. The bottom well 12 may be, for example, 1 × 10⁻⁶ １８ cm －３ The above 1 x 10 ２１ cm －３The following p-type impurity concentrations may be present as peak values. Preferably, the p-type impurity concentration in the bottom well 12 is adjusted by at least one trivalent element. The trivalent element in the bottom well 12 may be at least one of boron, aluminum, gallium, and indium.

[0072] Multiple bottom wells 12 overlap with multiple trench structures 11 in the depth direction of the trench 22. Specifically, multiple bottom wells 12 overlap with multiple trench structures 11 in a one-to-one correspondence in the thickness direction of the chip 2. In this configuration, each of the multiple bottom wells 12 is connected to the bottom surface 26 of the corresponding trench structure 11. Therefore, the multiple bottom wells 12 are arranged in the second direction Y with a spacing of trench pitch PT.

[0073] The bottom well 12 has a relaxation depth DR in the vertical direction Z. The relaxation depth DR is preferably 0.1 μm or more and 1.5 μm or less. Each of the multiple bottom wells 12 has a relaxation width WR in the direction of arrangement. The relaxation width WR may be 0.2 μm or more and 1.5 μm or less.

[0074] The semiconductor device 1 includes a source region 28 in the surface layer of the first main surface 3. The source region 28 is formed in the region between the plurality of trench structures 11. The source region 28 is formed in the surface layer of the body region 21.

[0075] In this configuration, multiple source regions 28 are formed across the width of the mesa portion 27, extending from one side 25 to the other side 25 (one side 25 and the other side 25 of the trench 22). The multiple source regions 28 are arranged at intervals along the extending direction of the trench 22 in each mesa portion 27. As a result, multiple channel sections CH are arranged at intervals in the second direction Y (the extending direction of the trench 22) in each mesa portion 27. In the channel sections CH, channels are formed on both sides of the trench 22's side 25 in the second direction Y of the mesa portion 27.

[0076] The source region 28 has a higher n-type impurity concentration (peak value) than the second semiconductor layer 7 (drift region 8). The source region 28 has a concentration of 1 × 10⁻⁶１８ cm －３ The above 1 x 10 ２１ cm －３ The following n-type impurity concentrations may be present as peak values.

[0077] The semiconductor device 1 includes a body contact region 29 in the surface layer of the first main surface 3. The body contact region 29 is formed in the region between the plurality of trench structures 11. The body contact region 29 is formed adjacent to the source region 28 in the surface layer of the body region 21.

[0078] In this configuration, multiple body contact areas 29 are formed across the width of the mesa portion 27, extending from one side surface 25 to the other side surface 25 of the mesa portion 27. In each mesa portion 27, multiple source areas 28 and multiple body contact areas 29 are arranged alternately along the extending direction of the trench 22. Each source area 28 and each body contact area 29 is exposed from both sides 25 of the trench 22 (both sides 25 of the mesa portion 27).

[0079] Referring to Figure 7, the semiconductor device 1 further includes a contact well 62 and a connection region 63 near the end 61 of the trench 22.

[0080] The contact well 62 is a p-shaped region that extends in a line across multiple trenches 22 below the trench 22, connecting multiple bottom wells 12 to each other.

[0081] The impurity concentration in the contact well 62 may be equal to the impurity concentration in the bottom well 12. The impurity concentration in the contact well 62 may be higher than the impurity concentration in the body region 21. For example, the contact well 62 may have an impurity concentration of 1 × 10⁻⁶. １８ cm －３ The above 1 x 10 ２１ cm －３ The following p-type impurity concentrations may be present as peak values.

[0082] The connection region 63 is a p-type region that electrically connects the body region 21 and the bottom well 12 (contact well 62). The connection region 63 extends along the inner surface of the trench 22 from the body region 21 to the bottom well 12 (contact well 62). As a result, the bottom well 12 is electrically connected to the body region 21 via the contact well 62 and the connection region 63, and is fixed at the source potential. Therefore, as shown in Figure 8, the semiconductor device 1 includes a body diode 13 with the bottom well 12 as the anode and the second semiconductor layer 7 (drift region 8) as the cathode.

[0083] As described above, the semiconductor device 1 includes an interlayer insulating film 16 on the first main surface 3. A plurality of contact openings 41 are formed in the interlayer insulating film 16. The plurality of contact openings 41 include a plurality of contact openings 41 (not shown) that expose a plurality of trench structures 11 (embedded conductive layers 24), and a plurality of contact openings 41 that expose a plurality of source regions 28. The plurality of contact openings 41 for the source regions 28 are formed in the region between the plurality of trench structures 11, and expose a plurality of source regions 28 and a plurality of body contact regions 29.

[0084] Referring to Figure 8, the semiconductor device 1 includes a main surface electrode 42. The main surface electrode 42 is formed on the first main surface 3 so as to cover the interlayer insulating film 16. In other words, the main surface electrode 42 is supported by the interlayer insulating film 16. The main surface electrode 42 has a laminated structure including a barrier layer 43 and a main body layer 44, which are stacked in this order from the first main surface 3 side.

[0085] The barrier layer 43 is formed in a film-like manner along the inner surfaces of the first main surface 3 and the contact opening 41. The barrier layer 43 is in ohmic contact with the first main surface 3. The barrier layer 43 may include at least one of the following: a Ti layer, a Pd layer, a Cr layer, a V layer, a Mo layer, a W layer, a Pt layer, and a Ni layer.

[0086] The main body layer 44 is formed on the barrier layer 43. The main body layer 44 covers the entire main surface of the barrier layer 43. The main body layer 44 is electrically connected to the source region 28 and the body contact region 29 via the barrier layer 43. Therefore, the main surface electrode 42 in the semiconductor device 1 may include the aforementioned source pad 19. Although not shown in the figures, the main surface electrode 42 in the semiconductor device 1 may include the aforementioned gate pad 17 and gate wiring 18. The bottom well 12 is fixed to the source potential via the body contact region 29 and the body region 21.

[0087] The main body layer 44 includes at least one of the following: a pure Al layer (an Al layer consisting of Al with a purity of 99% or more), an AlSi alloy layer, an AlCu alloy layer, and an AlSiCu alloy layer.

[0088] The semiconductor device 1 includes a main surface insulating film 45 that covers the main surface electrode 42. The main surface insulating film 45 is formed in a film-like manner along the main surface of the main surface electrode 42. The main surface insulating film 45 covers and protects the main surface electrode 42. The main surface insulating film 45 may also be called a "main surface protective film," "surface protective film," "passivation film," etc.

[0089] The main surface insulating film 45 may contain a photosensitive resin. The photosensitive resin may be negative or positive type. The main surface insulating film 45 may contain at least one of polyimide, polyamide, and polybenzoxazole. The main surface insulating film 45 may contain at least one of silicon oxide film, silicon nitride film, and silicon oxynitride film. In this embodiment, the main surface insulating film 45 is a single layer of polyimide film.

[0090] (3) First Modified Element Structure Figure 9 is a perspective view showing the first modified element structure. Referring to Figure 9, the element structure formed in the active region 9 of the semiconductor device 1 may be a planar gate type vertical transistor structure Tr.

[0091] The semiconductor device 1 includes a plurality of p-type body regions 76 formed in the active region 9. In this embodiment, the plurality of body regions 76 are arranged with spacing in the second direction Y and are each formed in a strip shape extending in the first direction X. The plurality of body regions 76 are arranged in a stripe shape as a whole. Each body region 76 provides a unit cell UC of a planar gate type transistor. Each unit cell UC may be the smallest unit that functions as an MIS transistor, comprising at least a body region 76 and a source region 77 (described later).

[0092] Multiple body regions 76 are, for example, 1 × 10 １５ cm －３ The above 1 x 10 １８ cm －３ The following p-type impurity concentrations may be present as peak values.

[0093] The semiconductor device 1 includes one or more n-type source regions 77 formed on the surface of each of the multiple body regions 76 in the active region 9. In this embodiment, multiple (two in this embodiment) source regions 77 are formed at intervals on the surface of each body region 76. The multiple source regions 77 have an n-type impurity concentration higher than the n-type impurity concentration of the drift region 8. The multiple source regions 77 have a density of 1 × 10⁻⁶ １８ cm －３ The above 1 x 10 ２１ cm －３ The following n-type impurity concentrations may be present as peak values.

[0094] The multiple source regions 77 may each extend in a strip-like manner along the extending direction of the corresponding body region 76. Of course, the multiple source regions 77 may be formed at intervals along the extending direction of the corresponding body region 76. The multiple source regions 77 are formed at intervals from the bottom of the corresponding body region 76 toward the first main surface 3, and at intervals from the periphery of the corresponding body region 76 toward the inward side. The multiple source regions 77 define a channel region 78 along the first main surface 3 at the periphery of the body region 76.

[0095] The semiconductor device 1 includes one or more p-type body contact regions 79 formed on the surface of each of the multiple body regions 76 in the active region 9. In this configuration, one body contact region 79 is formed in the region between multiple adjacent source regions 77 on the surface of each body region 76.

[0096] Multiple body contact regions 79 have a higher p-type impurity concentration (peak value) than the p-type impurity concentration (peak value) of multiple body regions 76. Multiple body contact regions 79 have a concentration of 1 × 10⁻⁶ １８ cm －３ The above 1 x 10 ２１ cm －３ The following p-type impurity concentrations may be present as peak values.

[0097] The multiple body contact regions 79 may each extend in a strip-like manner along the extending direction of the corresponding body region 76. Of course, the multiple body contact regions 79 may be formed at intervals along the extending direction of the corresponding body region 76. The multiple body contact regions 79 are formed at intervals from the bottom of the corresponding body region 76 toward the first main surface 3, and at intervals from the peripheral edge of the corresponding body region 76 toward the inside.

[0098] The semiconductor device 1 includes a plurality of planar electrode type gate structures 80 arranged on the first main surface 3 in the active region 9. The gate structures 80 may also be referred to as "planar structures" or "planar gate structures". The plurality of gate structures 80 are spaced apart on the first main surface 3 so as to overlap at least one channel region 78 in the stacking direction. The plurality of gate structures 80 are assigned a gate potential as a control potential. The plurality of gate structures 80 control the inversion and non-inversion of channels (current paths) within the body region 76 in response to the gate potential.

[0099] In this embodiment, the multiple gate structures 80 are arranged at intervals in the second direction Y and are each formed in a strip shape extending in the first direction X. In this embodiment, the multiple gate structures 80 are each positioned to straddle two adjacent body regions 76 and cover multiple source regions 77 located within one and the other body region 76, respectively.

[0100] Each of the multiple gate structures 80 has a stacked structure including a gate insulating film 81 disposed on the first main surface 3 and a gate electrode 82 disposed on the gate insulating film 81. The gate insulating film 81 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the gate insulating film 81 has a single-layer structure made of a silicon oxide film. The gate insulating film 81 may include a silicon oxide film made of the oxide of the chip 2. The gate electrode 82 may include p-type or n-type conductive polysilicon.

[0101] The contact opening 41 of the interlayer insulating film 16 exposes the source region 77 and the body contact region 79.

[0102] (4) Second Modified Element Structure Figure 10 is a perspective view showing a second modified element structure. Referring to Figure 10, the element structure formed in the active region 9 of the semiconductor device 1 may be a Schottky barrier diode (SBD).

[0103] The interlayer insulating film 16 has a diode opening 37 that exposes a portion of the drift region 8 as a diode region 36. The diode opening 37 may be formed in a rectangular shape with four sides parallel to the first to fourth sides 5A to 5D of the chip 2 in a plan view.

[0104] The aforementioned main surface electrode 42 is formed on the interlayer insulating film 16. The main surface electrode 42 extends from above the insulating layer into the diode opening 37. The main surface electrode 42 is electrically connected to the diode region 36 within the diode opening 37. The main surface electrode 42 is not particularly limited as long as it is a metal that forms a Schottky junction by bonding with n-type SiC, for example, titanium (Ti), molybdenum (Mo), palladium (Pd), platinum (Pt), etc. can be used. More specifically, the main surface electrode 42 forms a Schottky junction with the diode region 36. This forms a Schottky barrier diode SBD in which the main surface electrode 42 is the anode and the diode region 36 is the cathode. The aforementioned main surface insulating film 45 (not shown) is formed on the interlayer insulating film 16.

[0105] (5) Detailed structural description of the peripheral structure 38 including the peripheral impurity region 34 and the separated impurity region 35 in the peripheral region 10 will be given with reference to Figures 11 to 17 of the detailed structure of the peripheral region 1. The peripheral structure 38 described below can be applied to any of the peripheral structures of the trench gate structure (Figures 5 to 8), the planar gate structure (Figure 9), and the Schottky barrier diode (Figure 10).

[0106] Figure 11 is a plan view showing an example layout of the outer perimeter structure 38. Figure 12 is a cross-sectional view along the line XII-XII shown in Figure 11. Figure 13 is a cross-sectional view along the line XIII-XIII shown in Figure 11. In Figure 11, for clarity, only the components necessary for explaining the outer perimeter structure 38 are selectively extracted and shown.

[0107] Referring to Figure 11, the semiconductor device 1 includes a peripheral structure 38 formed in the outer peripheral region 10, which includes a peripheral impurity region 34 and a separated impurity region 35. The peripheral structure 38 may also be an impurity region exposed from the first to fourth side surfaces 5A to 5D of the chip 2.

[0108] The peripheral impurity region 34 is formed in an annular shape surrounding the active region 9 in a plan view. In this configuration, the peripheral impurity region 34 is formed in an endless annular shape. The peripheral impurity region 34 is a rectangular annular shape along the first to fourth side surfaces 5A to 5D of the tip 2 and is exposed from both the first main surface 3 and the first to fourth side surfaces 5A to 5D (see Figures 12 and 13). The peripheral impurity region 34 has a first upper surface 39 that forms part of the first main surface 3 and a first lateral surface 40 that forms part of the first to fourth side surfaces 5A to 5D.

[0109] Referring to Figures 12 and 13, in this embodiment, the first upper surface 39 and the first lateral surface 40 are connected at the corners 46 between the first main surface 3 and the first to fourth side surfaces 5A to 5D. As a result, an L-shaped exposed surface of the peripheral impurity region 34 is formed at the corners 46 of the chip 2, extending around the entire circumference of the outer edge of the chip 2.

[0110] The peripheral impurity region 34 includes a first peripheral region 47 extending along a first direction X and a second peripheral region 48 extending along a second direction Y. In this embodiment, a pair of first peripheral regions 47 facing the second direction Y and a pair of second peripheral regions 48 facing the first direction X provide a peripheral impurity region 34 that is rectangular in shape in plan view.

[0111] Referring to Figure 11, the width W1 of the first peripheral region 47 may be the same as the width W2 of the second peripheral region 48. The peripheral impurity region 34 may have a uniform width around the entire circumference of the outer edge of the chip 2. The widths W1 and W2 may be, for example, 1 μm or more and 60 μm or less.

[0112] The impurity concentration in the peripheral impurity region 34 may be higher than the impurity concentration in the body regions 21 and 76. The impurity concentration in the peripheral impurity region 34 may be higher than the impurity concentration in the drift region 8. The impurity concentration in the peripheral impurity region 34 may be higher than the impurity concentration in the bottom well 12. The impurity concentration in the peripheral impurity region 34 may be higher than the impurity concentration in the body contact regions 29 and 79.

[0113] The peripheral impurity region 34 is, for example, 1 × 10⁻⁶ ２０ cm －３ The above 1 x 10 ２１ cm－３ The following p-type impurity concentrations may be present as peak values. Preferably, the p-type impurity concentration in the peripheral impurity region 34 is adjusted by at least one trivalent element. The trivalent element in the peripheral impurity region 34 may be at least one of boron, aluminum, gallium, and indium.

[0114] The separation impurity region 35 is formed in an annular shape surrounding the active region 9 in a plan view. In this configuration, the separation impurity region 35 is formed in an endless annular shape. The separation impurity region 35 is formed around the entire outer edge of the tip 2.

[0115] The separated impurity region 35 is a rectangular ring along the first to fourth sides 5A to 5D of the tip 2, and covers the sides and bottom of the peripheral impurity region 34. Referring to Figures 12 and 13, the separated impurity region 35 is in contact with the sides of the peripheral impurity region 34 in the lateral direction along the first main surface 3, and in contact with the bottom of the peripheral impurity region 34 in the longitudinal direction along the thickness direction of the tip 2. As a result, the portion of the peripheral impurity region 34 inside the tip 2 is surrounded by the separated impurity region 35, preventing contact between the peripheral impurity region 34 and the drift region 8.

[0116] The peripheral impurity region 34 is physically separated from the drift region 8 by the separated impurity region 35. The separated impurity region 35 may also be called a "stress relaxation region" or "stress relaxation layer" as it alleviates the difference between the stress generated in the peripheral impurity region 34 and the stress generated in the drift region 8.

[0117] Referring to Figures 12 and 13, in this embodiment, the separated impurity region 35 is formed in a cross-sectional L-shape within the chip 2, extending from the first main surface 3 toward the first to fourth side surfaces 5A to 5D, along the peripheral impurity region 34. In this embodiment, it integrally includes a separated side portion 49 that extends in the vertical direction along the thickness direction of the chip 2 and is in contact with the side of the peripheral impurity region 34, and a separated bottom portion 50 that extends in the horizontal direction along the first main surface 3 and is in contact with the bottom of the peripheral impurity region 34.

[0118] The separation side portion 49 is exposed from the first main surface 3, and the separation bottom portion 50 is exposed from the first to fourth side portions 5A to 5D. The separation impurity region 35 includes an annular second upper surface 51 that is exposed from the first main surface 3 and surrounds the active region 9, and a second lateral surface 52 that is physically separated from the second upper surface 51 and surrounds the tip 2 along the first to fourth side portions 5A to 5D. The second upper surface 51 is part of the separation side portion 49, and the second lateral surface 52 is part of the separation bottom portion 50.

[0119] Referring to Figure 11, the semiconductor device 1 has a first upper surface 39 surrounding a second upper surface 51, and in a plan view, it has a p-type double ring structure 53 consisting of the first upper surface 39 and the second upper surface 51. Referring to Figures 12 and 13, the semiconductor device 1 has a first lateral surface 40 stacked on a second lateral surface 52, and in a side view, it has a p-type double layer stacked structure 54 consisting of the first lateral surface 40 and the second lateral surface 52.

[0120] The separated impurity region 35 includes a first separation region 55 extending along a first direction X and a second separation region 56 extending along a second direction Y. In this embodiment, the first separation region 55 extends along the [11-20] direction and the second separation region 56 extends along the [1-100] direction. A pair of first separation regions 55 facing the second direction Y and a pair of second separation regions 56 facing the first direction X provide a rectangular annular separated impurity region 35 in plan view.

[0121] Referring to Figure 11, the width W4 of the second separation region 56 may be wider than the width W3 of the first separation region 55. For example, the width W3 may be 1 μm or more and 50 μm or less, and the width W4 may be 1 μm or more and 60 μm or less. In this embodiment, the difference between the widths W3 and W4 is due to the difference between the width W3' of the second upper surface 51 of the first separation region 55 and the width W4' of the second upper surface 51 of the second separation region 56. In other words, the width W4' may be wider than the width W3'.

[0122] The impurity concentration in the separated impurity region 35 is lower than the impurity concentration in the peripheral impurity region 34. Preferably, the impurity concentration in the separated impurity region 35 is higher than the impurity concentration in the drift region 8. Preferably, the impurity concentration in the separated impurity region 35 is lower than the impurity concentration in the peripheral impurity region 34 and higher than the impurity concentration in the drift region 8. The impurity concentration in the separated impurity region 35 may be higher than the impurity concentration in the body regions 21 and 76. The impurity concentration in the separated impurity region 35 may be higher than the impurity concentration in the bottom well 12. The impurity concentration in the separated impurity region 35 may be higher than the impurity concentration in the body contact regions 29 and 79.

[0123] The separated impurity region 35 is, for example, 1 × 10⁻⁶ １８ cm －３ The above 1 x 10 １９ cm －３ The following p-type impurity concentrations may be present as peak values. Preferably, the p-type impurity concentration in the separated impurity region 35 is adjusted by at least one trivalent element. The trivalent element in the peripheral impurity region 34 may be at least one of boron, aluminum, gallium, and indium.

[0124] Referring to Figures 12 and 13, the interlayer insulating film 16 covers the separated impurity region 35 and the peripheral impurity region 34. In this configuration, the interlayer insulating film 16 extends from the active region 9 across the boundary 57 between the separated impurity region 35 and the peripheral impurity region 34, covering the first main surface 3 to the first to fourth side surfaces 5A to 5D of the chip 2. The interlayer insulating film 16 has an end face 58 that is flush with the first to fourth side surfaces 5A to 5D of the chip 2. Although not shown, a portion of the peripheral impurity region 34 may be selectively exposed if the end face 58 of the interlayer insulating film 16 is located inside the first to fourth side surfaces 5A to 5D.

[0125] Referring to Figures 12 and 13, the main surface insulating film 45 covers at least a portion of the first main surface 3. "The main surface insulating film 45 covers the first main surface 3" is synonymous with the main surface insulating film 45 facing the first main surface 3 in the thickness direction of the chip 2. "The main surface insulating film 45 covers the first main surface 3" includes both cases: when the main surface insulating film 45 directly covers the first main surface 3 (covering it in contact with the first main surface 3), and when the main surface insulating film 45 indirectly covers it (covering it without contact with the first main surface 3). For example, the main surface insulating film 45 may indirectly cover the first main surface 3 via the interlayer insulating film 16.

[0126] In this configuration, the main surface insulating film 45 covers the entire separated impurity region 35 and a portion of the peripheral impurity region 34. The main surface insulating film 45 has an end 59 located away from the first to fourth sides 5A to 5D of the chip 2 towards the active region 9. In Figure 11, the position of the end face 60 of the main surface insulating film 45 is shown by a dashed line. The main surface insulating film 45 crosses the boundary 57 between the separated impurity region 35 and the peripheral impurity region 34 from the active region 9, and has an end face 60 directly above the peripheral impurity region 34. As a result, the peripheral impurity region 34 is exposed from the main surface insulating film 45 in a plan view (it is not covered by the main surface insulating film 45).

[0127] Figure 14 is a plan view showing an example layout of the outer perimeter structure 38. Referring to Figure 14, the width W4 of the second separation region 56 may be the same as the width W3 of the first separation region 55.

[0128] Figure 15 is a plan view showing an example layout of the outer peripheral structure 38. Figure 16 is a cross-sectional view along the line XVI-XVI shown in Figure 15. Referring to Figure 15, the separated impurity region 35 may have only the second separated region 56 of the first separated region 55 and may not have the first separated region 55. In this case, as shown in Figure 16, the sides and bottom of the peripheral impurity region 34 (first peripheral region 47) on the first side surface 5A and the third side surface 5C of the chip 2 may be in contact with the drift region 8.

[0129] Figure 17 is a plan view showing an example layout of the outer peripheral structure 38. Referring to Figure 17, the separation impurity region 35 may be divided into a plurality of regions spaced apart along the outer peripheral edge of the tip 2. The plurality of separation impurity regions 35 may collectively surround the active region 9.

[0130] (6) Effects of the semiconductor device 1 In the semiconductor device 1, the SiC single crystal constituting the second semiconductor layer 7 contains various crystal defects. These crystal defects include, for example, basal plane dislocations. Basal plane dislocations are distributed, for example, in the first semiconductor layer 6 (SiC substrate) or near the interface between the first semiconductor layer 6 and the second semiconductor layer 7, and may be stacked by expansion toward the first main surface 3, forming stacking faults. One example of a cause of basal plane dislocations is stress generated inside the second semiconductor layer 7 (epitaxial layer).

[0131] In semiconductor device 1, the source-drain voltage may exceed 1000V. A slight voltage drop occurs in the thickness direction between the first main surface 3 and the second main surface 4 of the drift region 8, but they are basically at the same potential. Therefore, if the drift region 8 is exposed on the first main surface 3 of the outer peripheral region 10, discharge may occur between the outer peripheral region 10 and the active region 9 of the chip 2, for example, during operation of semiconductor device 1 or during the pre-completion inspection process.

[0132] To prevent this discharge, a peripheral impurity region 34 is formed on the outer edge of the chip 2, and the impurity concentration at the outer edge is locally increased. However, when a peripheral impurity region 34 is formed by implanting impurity ions at a high concentration, basal plane dislocations are more likely to occur in the second semiconductor layer 7 due to stress caused by the implantation defects.

[0133] Therefore, the peripheral impurity region 34 is surrounded by a separation impurity region 35 with a lower concentration than the peripheral impurity region 34, thereby physically separating the peripheral impurity region 34 from the drift region 8. This makes it possible to mitigate the difference between the stress generated in the peripheral impurity region 34 and the stress generated in the drift region 8. As a result, the generation of basal plane dislocations can be suppressed, thereby improving the reliability of the device.

[0134] Furthermore, in semiconductor device 1, since the off-direction Doff is in the a-axis direction ([11-20] axis) of the SiC single crystal, basal plane dislocations tend to occur along the m-axis direction ([1-100] direction). Therefore, of the first and second separation regions 55 and 56, the width W4 of the second separation region 56 along the m-axis direction ([1-100] direction) is made wider than the width W3 of the first separation region 55 (see Figure 11). This effectively suppresses the generation of basal plane dislocations.

[0135] For similar reasons, if the second separation region 56 is formed, the effect of suppressing the generation of basal dislocations can be sufficiently expressed even if the first separation region 55 is not formed (see Figure 15).

[0136] (7) Modified Outer Peripheral Structure 38 Figures 18 to 26 are cross-sectional views showing modified outer peripheral structure 38. Figures 18 to 26 show cross-sections corresponding to Figure 12. In the configurations shown in Figures 18 to 26 below, the sides and bottom of the peripheral impurity region 34 are surrounded by the separated impurity region 35, so that the generation of basal plane dislocations in the second semiconductor layer 7 can be suppressed.

[0137] Referring to Figure 18, the end portion 59 of the main surface insulating film 45 may be positioned away from the separated impurity region 35 towards the active region 9. This means that the main surface insulating film 45 does not have to face either the peripheral impurity region 34 or the separated impurity region 35 in the thickness direction of the chip 2.

[0138] Referring to Figure 19, the main surface insulating film 45 extends from the active region 9 across the boundary 57 between the separated impurity region 35 and the peripheral impurity region 34, covering the first main surface 3 to the first to fourth side surfaces 5A to 5D of the chip 2. The main surface insulating film 45 covers the entire separated impurity region 35 and the peripheral impurity region 34. The end face 60 of the main surface insulating film 45 is flush with the first to fourth side surfaces 5A to 5D of the chip 2 and the end face 58 of the interlayer insulating film 16.

[0139] Referring to Figure 20, the chip 2 includes a recess 65 formed on the first main surface 3 in the outer peripheral region 10, having a bottom surface 64 that exposes at least the peripheral impurity region 34. In this embodiment, the recess 65 is formed around the entire circumference of the outer peripheral edge of the chip 2. The recess 65 may also be a lateral open recess with the ends on the first to fourth side surfaces 5A to 5D of the chip 2 open and a side surface 66 on the opposite side.

[0140] The semiconductor device 1 includes a mesa portion 67 formed inside the recess 65. The mesa portion 67 is a portion surrounded by the annular recess 65 in plan view, and may be a projection that protrudes from the bottom surface 64 of the recess 65. In this embodiment, the mesa portion 67 may be positioned away from the separated impurity region 35 towards the active region 9. As a result, the entire first upper surface 39 of the peripheral impurity region 34 and the second upper surface 51 of the separated impurity region 35 are exposed from the bottom surface 64 of the recess 65. Furthermore, a third upper surface 68, which is part of the drift region 8, is exposed on the bottom surface 64 of the recess 65, further inside the second upper surface 51.

[0141] The main surface insulating film 45 selectively covers the mesa portion 67, out of the recess 65 and the mesa portion 67. In this configuration, the main surface insulating film 45 has an end face 60 at the side surface of the mesa portion 67 (the side surface 66 of the recess 65).

[0142] Referring to Figure 21, the mesa portion 67 may straddle the boundary between the separated impurity region 35 and the drift region 8. In this embodiment, the side surface 66 of the mesa portion 67 is located directly above the separated impurity region 35. The second upper surface 51 of the separated impurity region 35 is partially exposed from the bottom surface 64 of the recess 65 and the remainder is exposed from the upper surface of the mesa portion 67.

[0143] The main surface insulating film 45 covers both the mesa portion 67 and the recess 65. In this configuration, the end face 60 of the main surface insulating film 45 is located directly above the separated impurity region 35.

[0144] Referring to Figure 22, the mesa portion 67 may straddle the boundary 57 between the peripheral impurity region 34 and the separated impurity region 35. In this embodiment, the side surface 66 of the mesa portion 67 is located directly above the peripheral impurity region 34. The first upper surface 39 of the peripheral impurity region 34 is partially exposed from the bottom surface 64 of the recess 65 and the remainder is exposed from the upper surface of the mesa portion 67.

[0145] The main surface insulating film 45 covers both the peripheral impurity region 34 and the separated impurity region 35 on the mesa portion 67. In this configuration, the main surface insulating film 45 has an end face 60 at the side surface of the mesa portion 67 (the side surface 66 of the recess 65).

[0146] Referring to Figure 23, the main surface insulating film 45 covers both the mesa portion 67 and the recess 65. In this configuration, the end face 60 of the main surface insulating film 45 is located directly above the peripheral impurity region 34.

[0147] Referring to Figure 24, the side surface 66 of the recess 65 may be tapered and inclined with respect to the first main surface 3. The tapered side surface 66 may be formed around the entire circumference of the outer edge of the tip 2.

[0148] Referring to Figure 25, the main surface insulating film 45 may be a multilayer film comprising at least a first film 69 and a second film 70. The first film 69 and the second film 70 may be formed from different insulating materials. For example, the first film 69 may be a silicon oxide film and the second film 70 may be a polyimide film. When the main surface insulating film 45 is a multilayer film, the first film 69 may be called an interlayer insulating film and the second film 70 may be called a passivation film. The second film 70 may have the same thickness as the first film 69 or a different thickness. In this embodiment, it is preferable that the second film 70 is thicker than the first film 69. The main surface insulating film 45 may be a multilayer film with the second film 70 as the outermost film, or it may be a multilayer film in which an insulating film such as a third film is further laminated on the second film 70.

[0149] Referring to Figure 26, the separated impurity region 35 does not necessarily have to be a p-type region; it may be an n-type separated impurity region 71 having an impurity concentration lower than that of the peripheral impurity region 34.

[0150] The impurity concentration in the separated impurity region 71 is preferably higher than the impurity concentration in the drift region 8. The impurity concentration in the separated impurity region 71 is preferably lower than the impurity concentration in the peripheral impurity region 34 and higher than the impurity concentration in the drift region 8. The impurity concentration in the separated impurity region 71 may be higher than the impurity concentrations in the body regions 21 and 76. The impurity concentration in the separated impurity region 71 may be higher than the impurity concentration in the bottom well 12. The impurity concentration in the separated impurity region 71 may be higher than the impurity concentrations in the body contact regions 29 and 79. The separated impurity region 71 is, for example, 1 × 10 １８ cm －３ The above 1 x 10 １９ cm －３ The following n-type impurity concentrations may be present as peak values.

[0151] While embodiments of this disclosure have been described, this disclosure can also be implemented in other forms.

[0152] For example, in each of the above embodiments, trench-gate type MISFETs, planar-gate type MISFETs, and Schottky barrier diodes were shown as examples of device structures. The semiconductor device 1 may also include JFETs (Junction Field Effect Transistors) as other device structures.

[0153] In each of the above-described embodiments, a structure may be adopted in which the conductivity type of the "n-type" semiconductor region is inverted to "p-type," and the conductivity type of the "p-type" semiconductor region is inverted to "n-type." The specific configuration in this case can be obtained by replacing "n-type" with "p-type" and simultaneously replacing "p-type" with "n-type" in the above description and attached drawings.

[0154] In each of the above-described embodiments, a p-type collector region may be formed on the surface layer of the second main surface 4 of the chip 2. In this case, the transistor structure Tr includes an IGBT (Insulated Gate Bipolar Transistor) structure instead of a MISFET structure. The specific configuration in this case is obtained by replacing the "source" of the MISFET structure with the "emitter" of the IGBT structure and the "drain" of the MISFET structure with the "collector" of the IGBT structure, as described above. In this case, the chip 2 may have a single-layer structure made of an n-type semiconductor substrate.

[0155] The following are examples of features extracted from this specification and drawings. The alphanumeric characters in parentheses below represent the corresponding components in the embodiments described above, but this is not intended to limit the scope of each Clause to the embodiments. The term "semiconductor device" in the following items may be replaced with "SiC semiconductor device," "wide bandgap semiconductor device," "semiconductor switching device," "semiconductor rectifier," "MISFET device," "IGBT device," "diode device," etc., as needed.

[0156] [Note 1-1] A SiC chip (2) having a main surface (3) on which an active region (9) on which an element structure is formed and an outer peripheral region (10) surrounding the active region (9) are set; a semiconductor device (1) comprising: a first impurity region (7, 8) of a first conductivity type formed on the surface layer of the main surface (3); a second impurity region (34) of a second conductivity type having a first concentration formed on the surface layer of the first impurity region (7, 8) in the outer peripheral region (10); and a separated impurity region (35) having a second concentration lower than the first concentration, separating the first impurity region (7, 8) and the second impurity region (34) in the outer peripheral region (10).

[0157] [Note 1-2] The main surface (3) is a surface inclined with an off angle θ in a first direction (X) which is a predetermined off direction with respect to the (0001) surface, and the separated impurity region (35) is formed at least along a second direction (Y) which intersects the first direction (X) in a plan view, the semiconductor device (1) according to Note 1-1.

[0158] [Note 1-3] The semiconductor device (1) described in Note 1-2, wherein the first direction (X) is the [11-20] direction and the second direction (Y) is the [1-100] direction.

[0159] [Appendix 1-4] The semiconductor device (1) according to Appendix 1-2 or Appendix 1-3, wherein the separated impurity region (35) is formed along the first direction (X) and the second direction (Y) over the entire circumference of the outer edge of the SiC chip (2).

[0160] [Appendix 1-5] The SiC chip (2) is formed in a rectangular shape in plan view, having a pair of first sides (5A, 5C) along the first direction (X) and a pair of second sides (5B, 5D) along the second direction (Y), and the separated impurity region (35) has a pair of first separated regions (55) along the pair of first sides (5A, 5C) and a pair of second separated regions (56) along the pair of second sides (5B, 5D), and the width (W4) of the second separated region (56) is wider than the width (W3) of the first separated region (55), as described in any one of Appendix 1-2 to 1-4.

[0161] [Appendix 1-6] The semiconductor device (1) according to any one of Appendix 1-2 to 1-4, wherein the SiC chip (2) is formed in a rectangular shape in plan view, having a pair of first sides (5A, 5C) along the first direction (X) and a pair of second sides (5B, 5D) along the second direction (Y), and the separated impurity region (35) is formed along the pair of first sides (5A, 5C) and not along the pair of second sides (5B, 5D).

[0162] [Appendix 1-7] The semiconductor device (1) according to any one of Appendix 1-1 to 1-4, wherein the SiC chip (2) has a pair of first sides (5A, 5C) along the [11-20] direction and a pair of second sides (5B, 5D) along the [1-100] direction, the separated impurity region (35) has a pair of first separated regions (55) along the pair of first sides (5A, 5C) and a pair of second separated regions (56) along the pair of second sides (5B, 5D), and the width (W4) of the second separated region (56) is wider than the width (W3) of the first separated region (55).

[0163] [Appendix 1-8] The semiconductor device (1) according to any one of Appendix 1-1 to 1-4, wherein the SiC chip (2) has a pair of first sides (5A, 5C) along the [11-20] direction and a pair of second sides (5B, 5D) along the [1-100] direction, and the separated impurity region (35) is formed along the pair of first sides (5A, 5C) and not along the pair of second sides (5B, 5D).

[0164] [Appendix 1-9] The semiconductor device (1) according to any one of the appendices 1-1 to 1-8, further comprising a main surface insulating film (45) that covers at least a portion of the main surface (3).

[0165] [Appendix 1-10] The semiconductor device (1) according to Appendix 1-9, wherein the main surface insulating film (45) covers the entire separated impurity region (35).

[0166] [Note 1-11] The semiconductor device (1) according to Note 1-9, wherein the main surface insulating film (45) has an end (59) located away from the side surface of the SiC chip (2) toward the active region (9), and the second impurity region (34) is exposed from the main surface insulating film (45) in a plan view.

[0167] [Appendix 1-12] The semiconductor device (1) described in Appendix 1-9, wherein the main surface insulating film (45) covers the main surface (3) from the active region (9) to the side surface (5A to 5D) of the SiC chip (2).

[0168] [Appendix 1-13] A semiconductor device (1) according to any one of Appendix 1-9 to 1-12, comprising: a main surface electrode (42) electrically connected to the element structure; and an interlayer insulating film (16) disposed between the main surface insulating film (45) and the SiC chip (2) and supporting the main surface electrode (42), wherein the interlayer insulating film (16) covers the separated impurity region (35) and the second impurity region (34).

[0169] [Appendix 1-14] The semiconductor device (1) according to any one of Appendix 1-9 to 1-13, wherein the main surface insulating film (45) includes at least one of an oxide film, a nitride film, and a polyimide film.

[0170] [Appendix 1-15] The semiconductor device (1) according to Appendix 1-14, wherein the main surface insulating film (45) includes a single layer film of any one of an oxide film, a nitride film, and a polyimide film.

[0171] [Appendix 1-16] The semiconductor device (1) according to any one of Appendix 1-9 to 1-15, wherein the SiC chip (2) includes a recess (65) formed on the main surface (3) in the outer peripheral region (10) and having a bottom surface (64) in which at least the second impurity region (34) is exposed.

[0172] [Appendix 1-17] The semiconductor device (1) according to Appendix 1-16, wherein the recess (65) has a tapered side surface (66) that is inclined with respect to the main surface (3).

[0173] [Appendix 1-18] The semiconductor device (1) according to Appendix 1-16 or Appendix 1-17, wherein the recess (65) includes a lateral open recess (65) having an open end on the side (5A to 5D) side of the SiC chip (2) and a side (66) on the opposite side.

[0174] [Appendix 1-19] The semiconductor device (1) according to any one of Appendix 1-16 to 1-18, wherein the SiC chip (2) includes a mesa portion (67) formed inside the recess (65), and the main surface insulating film (45) covers the mesa portion (67) and the recess (65).

[0175] [Appendix 1-20] The separated impurity region (35) is an impurity region of the first conductivity type or the second conductivity type, according to any one of the appendices 1-1 to 1-19, semiconductor device (1).

[0176] 1... Semiconductor device, 2... Chip, 3... First main surface, 4... Second main surface, 5A... First side surface, 5B... Second side surface, 5C... Third side surface, 5D... Fourth side surface, 6... First semiconductor layer, 7... Second semiconductor layer, 8... Drift region, 9... Active region, 10... Outer peripheral region, 11... Trench structure, 12... Bottom well, 13... Body diode, 14... Main surface, 15... Field relaxation ring, 16... Interlayer insulating film, 17... Gate pad, 18... Gate wiring, 18A... First gate wiring, 18B... Second gate wiring, 19... Source pad, 20... Drain pad, 21... Body region, 22... Trench, 23... Trench insulating film, 24... Embedded conductive layer, 25... Side surface, 26... Bottom surface, 27... Mesa region, 28... Source region, 29... Body contact region, 30... Terrace surface, 31... Step surface, 32... Layer, 33... Step line, 34... Peripheral impurity region, 35... Separated impurity region, 36... Die 37... Diode region, 38... Outer periphery structure, 39... First upper surface, 40... First lateral surface, 41... Contact opening, 42... Main surface electrode, 43... Barrier layer, 44... Main body layer, 45... Main surface insulating film, 46... Corner, 47... First peripheral region, 48... Second peripheral region, 49... Separation side, 50... Separation bottom, 51... Second upper surface, 52... Second lateral surface, 53... Double ring structure, 54... Double layer stacked structure, 55... First separation region, 56... Second Separation region, 57...boundary, 58...end face, 59...end, 60...end face, 61...end, 62...contact well, 63...connection region, 64...bottom face, 65...recess, 66...side, 67...mesa region, 68...third upper surface, 69...first film, 70...second film, 71...separation impurity region, 76...body region, 77...source region, 78...channel region, 79...body contact region, 80...gate structure, 81...gate insulating film, 82...gate electrode

Claims

A SiC chip having a main surface in which an active region on which an element structure is formed and an outer peripheral region surrounding the active region are defined, A first impurity region of the first conductivity type formed on the surface layer of the main surface, In the outer peripheral region, a second impurity region of a second conductivity type having a first concentration is formed on the surface of the first impurity region, A semiconductor device comprising a first impurity region and a second impurity region separated in the outer peripheral region, and including a separated impurity region having a second concentration lower than the first concentration. 　 The main surface is a surface inclined with an off angle θ in a first direction which is a predetermined off direction with respect to the (0001) surface, The semiconductor device according to claim 1, wherein the separated impurity region is formed at least along a second direction that intersects the first direction in a plan view. 　 The first direction is the [11-20] direction, The semiconductor device according to claim 2, wherein the second direction is the [1-100] direction. 　 The semiconductor device according to claim 2 or 3, wherein the separated impurity region is formed along the first and second directions over the entire circumference of the outer edge of the SiC chip. 　 The SiC chip is formed in a rectangular shape in plan view, having a pair of first sides along the first direction and a pair of second sides along the second direction. The separated impurity region comprises a pair of first separation regions along the pair of first side surfaces and a pair of second separation regions along the pair of second side surfaces. The semiconductor device according to any one of claims 2 to 4, wherein the width of the second separation region is wider than the width of the first separation region. 　 The SiC chip is formed in a rectangular shape in plan view, having a pair of first sides along the first direction and a pair of second sides along the second direction. The semiconductor device according to any one of claims 2 to 4, wherein the separated impurity region is formed along the pair of first sides and not along the pair of second sides. 　 The SiC chip has a pair of first surfaces aligned along the [11-20] direction and a pair of second surfaces aligned along the [1-100] direction. The separated impurity region comprises a pair of first separation regions along the pair of first side surfaces and a pair of second separation regions along the pair of second side surfaces. The semiconductor device according to any one of claims 1 to 4, wherein the width of the second separation region is wider than the width of the first separation region. 　 The SiC chip has a pair of first surfaces aligned along the [11-20] direction and a pair of second surfaces aligned along the [1-100] direction. The semiconductor device according to any one of claims 1 to 4, wherein the separated impurity region is formed along the pair of first sides and not along the pair of second sides. 　 The semiconductor device according to any one of claims 1 to 8, further comprising a main surface insulating film that covers at least a portion of the main surface. 　 The semiconductor device according to claim 9, wherein the main surface insulating film covers the entire separated impurity region. 　 The main surface insulating film has an end portion located away from the side surface of the SiC chip towards the active region. The semiconductor device according to claim 9, wherein the second impurity region is exposed from the main surface insulating film in a plan view. 　 The semiconductor device according to claim 9, wherein the main surface insulating film covers the main surface from the active region to the side surface of the SiC chip. 　 The element structure comprises a main surface electrode electrically connected to the above element structure, It includes an interlayer insulating film disposed between the main surface insulating film and the SiC chip, which supports the main surface electrode, The semiconductor device according to any one of claims 9 to 12, wherein the interlayer insulating film covers the separated impurity region and the second impurity region. 　 The semiconductor device according to any one of claims 9 to 13, wherein the main surface insulating film comprises at least one of an oxide film, a nitride film, and a polyimide film. 　 The semiconductor device according to claim 14, wherein the main surface insulating film comprises a single layer film selected from an oxide film, a nitride film, and a polyimide film. 　 The semiconductor device according to any one of claims 9 to 15, wherein the SiC chip includes a recess formed on the main surface in the outer peripheral region, having a bottom surface in which at least the second impurity region is exposed. 　 The semiconductor device according to claim 16, wherein the recess has a tapered side surface that is inclined with respect to the main surface. 　 The semiconductor device according to claim 16 or 17, wherein the recess includes a lateral open recess having an open end on the side of the SiC chip and a side on the opposite side. 　 The SiC chip includes a mesa portion formed inside the recess, The semiconductor device according to any one of claims 16 to 18, wherein the main surface insulating film covers the mesa portion and the recess. 　 The semiconductor device according to any one of claims 1 to 19, wherein the separated impurity region is an impurity region of a first conductivity type or a second conductivity type.

Images