Semiconductor device and method for manufacturing semiconductor device

Abstract

This semiconductor device comprises: a chip having a main surface; a semiconductor region of a first conductivity type formed in a surface layer portion of the main surface and made of an epitaxial layer; an active region provided in a portion inside of the main surface; an outer peripheral region provided in a peripheral portion of the main surface and surrounding the periphery of the active region; a device structure formed in the active region; a first field region of a second conductivity type formed in a surface layer portion of the semiconductor region in the outer peripheral region at an interval from the main surface in the depth direction of the chip; and a surface region of the first conductivity type formed in the surface layer portion of the semiconductor region in the outer peripheral region and sandwiching the first field region between the surface region and the semiconductor region in the depth direction of the chip, the surface region containing impurities of the second conductivity type.

Description

Semiconductor Device and Method of Manufacturing the Same Related Application

[0001] This application corresponds to Japanese Patent Application No. 2024-192346 filed with the Japan Patent Office on October 31, 2024, and the entire disclosure of this application is incorporated herein by reference.

[0002] This disclosure relates to a semiconductor device and a method of manufacturing the same.

[0003] In the semiconductor device disclosed in Patent Document 1 (US8294235B2), a p

[0004] region is embedded in the surface layer portion of the n-type epitaxial layer. The p － region is sandwiched between a region (n-type epitaxial layer) on the surface side of the p － region and a region (n-type epitaxial layer) on the back side of the p － region. That is, an n-p-n sandwich structure is formed in the surface layer portion of the n-type epitaxial layer. The p － region is exposed on the side surface of the chip.

[0004] U.S. Patent No. 8294235

[0005] [Summary] One embodiment of this disclosure includes a chip having a main surface, a first-conductive-type semiconductor region formed of an epitaxial layer on the surface layer portion of the main surface, an active region provided in an inner portion of the main surface, an outer peripheral region provided at a peripheral portion of the main surface and surrounding the active region, a device structure formed in the active region, a second-conductive-type first field region formed in the surface layer portion of the semiconductor region in the outer peripheral region with a space in the depth direction of the chip from the main surface, and a first-conductive-type surface region formed in the surface layer portion of the semiconductor region in the outer peripheral region and facing the first field region with the first field region sandwiched in the depth direction of the chip between the semiconductor region, the surface region being a region containing second-conductive-type impurities, and provides a semiconductor device.

[0006] One embodiment of the present disclosure provides a method for manufacturing a semiconductor device, comprising the steps of: forming a first epitaxial layer of a first conductivity type on a semiconductor substrate of a first conductivity type; forming a second epitaxial layer of a first conductivity type having a wafer main surface and a higher concentration of first conductivity type impurities than the first epitaxial layer on the first epitaxial layer; and a first ion implantation step of implanting ions of a second conductivity type from the wafer main surface toward the first epitaxial layer such that the concentration of second conductivity type impurities in a first region of the first epitaxial layer exceeds the concentration of first conductivity type impurities, thereby forming a first field region of a second conductivity type in the first region of the first epitaxial layer.

[0007] Figure 1 is a plan view showing a semiconductor device according to the first embodiment of the present disclosure. Figure 2 is a cross-sectional view taken along the line II-II shown in Figure 1. Figure 3 is a plan view showing an example of a chip layout. Figure 4 is a perspective view showing an example of a chip layout. Figure 5 is an enlarged plan view showing a key part of the first main surface shown in Figure 3. Figure 6 is an enlarged plan view showing a key part of the first main surface shown in Figure 3. Figure 7 is a cross-sectional view taken along the line VII-VII shown in Figure 5. Figure 8 is a cross-sectional view taken along the line VIII-VIII shown in Figure 5. Figure 9 is a cross-sectional view showing the cross-sectional structure of the outer peripheral region along the line IX-IX shown in Figure 1. Figure 10 is an enlarged cross-sectional view of a region shown in Figure 9. Figure 11 is a plan view showing an example of a chip layout. Figure 12 is a graph showing an example of a concentration gradient of p-type impurities (first embodiment example) in the region along the line XII-XII shown in Figure 10. Figure 13 is a graph showing an example of a concentration gradient of n-type impurities in the region along the line XII-XII shown in Figure 10. Figure 14 is a schematic diagram showing a wafer used in the manufacture of the semiconductor device. Figure 15A is a cross-sectional view showing the manufacturing method of the semiconductor device. Figure 15B is a cross-sectional view showing a process after Figure 15A. Figure 15C is a cross-sectional view showing a process after Figure 15B. Figure 15D is a cross-sectional view showing a process after Figure 15C. Figure 15E is a cross-sectional view showing a process after Figure 15D. Figure 15F is a cross-sectional view showing a process after Figure 15E. Figure 15G is a cross-sectional view showing a process after Figure 15F. Figure 16A is a graph showing a second example of the p-type impurity concentration gradient of the chip, corresponding to Figure 12. Figure 16B is a graph showing a third example of the p-type impurity concentration gradient of the chip, corresponding to Figure 12. Figure 16C is a graph showing a fourth example of the p-type impurity concentration gradient of the chip, corresponding to Figure 12. Figure 17 is a cross-sectional view showing the field region and surface region according to the first modified example. Figure 18 is a cross-sectional view showing the cross-sectional structure of the outer peripheral region according to the second embodiment of this disclosure, and corresponds to Figure 10. Figure 19 is a graph showing an example of the concentration gradient of p-type impurities in the region along the XIX-XIX line shown in Figure 18 (fifth embodiment example). Figure 20A is a cross-sectional view showing the manufacturing method of the semiconductor device. Figure 20B is a cross-sectional view showing a process after Figure 20A. Figure 20C is a cross-sectional view showing a process after Figure 20B.FIG. 20D is a cross-sectional view showing a process after FIG. 20C. FIG. 20E is a cross-sectional view showing a process after FIG. 20D. FIG. 21A is a graph showing a sixth exemplary form of the concentration gradient of p-type impurities in a chip, and is a figure corresponding to FIG. 19. FIG. 21B is a graph showing a seventh exemplary form of the concentration gradient of p-type impurities in a chip, and is a figure corresponding to FIG. 19. FIG. 22 is a cross-sectional view showing a field region and a surface region according to a second modification. FIG. 23 is a cross-sectional view showing a main part of a semiconductor device according to a third embodiment of the present disclosure. FIG. 24 is a cross-sectional view showing the main part of the semiconductor device. FIG. 25 is a cross-sectional view showing a main part of a semiconductor device according to a fourth embodiment of the present disclosure.

[0008] [Detailed Description] Next, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0009] The accompanying drawings are all schematic diagrams, not strictly illustrated, and scales, ratios, angles, etc. do not necessarily match. The same reference numerals are assigned to corresponding structures among the accompanying drawings, and duplicate explanations are omitted or simplified. For structures with explanations omitted or simplified, the explanations made before the omission or simplification are applicable.

[0010] When the term "substantially" is used in this specification, this term includes not only a numerical value (form) that is substantially equal to the numerical value (form) of the comparison target, but also a numerical error (form error) within a range of ±10% based on the numerical value (form) of the comparison target. In the following description, terms such as "first", "second", "third", etc. are used, but these are symbols attached to the names of each structure for the purpose of clarifying the order of explanation, and are not attached with the intention of limiting the name of each structure.

[0011] In the following description, the conductivity type of a semiconductor (impurity) is indicated using "p-type" or "n-type," but "p-type" may be referred to as the "first conductivity type" and "n-type" as the "second conductivity type." Alternatively, "n-type" may be referred to as the "first conductivity type" and "p-type" as the "second conductivity type." "p-type" is a conductivity type resulting from a trivalent element, and "n-type" is a conductivity type resulting from a pentavalent element. The trivalent element is at least one of boron, aluminum, gallium, and indium. The pentavalent element is at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0012] Figure 1 is a plan view showing a semiconductor device 1A according to the first embodiment of the present disclosure. Figure 2 is a cross-sectional view taken along the line II-II shown in Figure 1. Figure 3 is a plan view showing an example of the layout of the chip 2. Figure 4 is a perspective view showing an example of the layout of the chip 2.

[0013] Semiconductor device 1A is a semiconductor switching device having an insulated gate type transistor structure Tr as an example of a device structure. The transistor structure Tr has a trench gate type vertical structure.

[0014] Referring to Figures 1 to 4, the semiconductor device 1A includes a chip 2 formed in a hexahedral shape (specifically, a rectangular parallelepiped shape). In this embodiment, the chip 2 includes a single crystal of a wide-bandgap semiconductor. In other words, the semiconductor device 1A is a "wide-bandgap semiconductor device". The chip 2 may also be referred to as a "semiconductor chip," "wide-bandgap semiconductor chip," etc.

[0015] Wide-bandgap semiconductors are semiconductors that have a bandgap greater than that of silicon (Si). Examples of wide-bandgap semiconductors include gallium nitride (GaN), silicon carbide (SiC), and diamond (C). In this configuration, chip 2 is a "SiC chip" containing a hexagonal SiC single crystal as an example of a wide-bandgap semiconductor. In other words, semiconductor device 1A is a "SiC semiconductor device".

[0016] Hexagonal SiC single crystals have multiple polytypes, including 2H (Hexagonal)-SiC single crystals, 4H-SiC single crystals, and 6H-SiC single crystals. In this embodiment, an example is shown in which chip 2 contains a 4H-SiC single crystal, but chip 2 may also contain other polytypes.

[0017] The chip 2 has a first main surface (main surface) 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connected to the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a rectangular shape in a plan view from the vertical direction Z (hereinafter simply referred to as "plan view"). The vertical direction Z is also the thickness direction of the chip 2 and the normal direction of the first main surface 3 (second main surface 4). The first main surface 3 and the second main surface 4 may be formed in a square or rectangular shape in a plan view.

[0018] The first main surface 3 and the second main surface 4 are preferably formed by the c-plane of the SiC single crystal. In this case, the first main surface 3 is preferably formed by the silicon plane ((0001) plane) of the SiC single crystal, and the second main surface 4 is preferably formed by the carbon plane ((000-1) plane) of the SiC single crystal.

[0019] The first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3 and face a second direction Y that intersects the first direction X along the first main surface 3. Specifically, the second direction Y is perpendicular to the first direction X. The third side surface 5C and the fourth side surface 5D extend in the second direction Y and face the first direction X.

[0020] In this configuration, the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y is the a-axis direction ([11-20] direction) of the SiC single crystal. Alternatively, the first direction X may be the a-axis direction of the SiC single crystal, and the second direction Y may be the m-axis direction of the SiC single crystal. Hereafter, the direction extending along the first principal surface 3 may be referred to as the "horizontal direction". The horizontal direction is also the XY plane (horizontal plane) formed by the first direction X and the second direction Y, and is perpendicular to the vertical direction Z.

[0021] The XY plane, which includes the first direction X and the second direction Y, forms a horizontal plane perpendicular to the vertical direction Z. Hereafter, the axis extending along the vertical direction Z may be referred to as the "vertical axis." Also below, the first direction X and the second direction Y may be referred to as the "horizontal direction." The horizontal direction is also the direction extending along the first principal plane 3.

[0022] Referring to Figure 4, the chip 2 (first main surface 3 and second main surface 4) has an off-angle α that is inclined at a predetermined angle in a predetermined off-direction with respect to the c-plane of the SiC single crystal. In other words, the c-axis ((0001) axis) of the SiC single crystal is inclined by an off-angle α from the vertical line along the vertical direction Z in the off-direction. Also, the c-plane of the SiC single crystal is inclined by an off-angle α with respect to the horizontal plane.

[0023] The off-direction is preferably the a-axis direction of the SiC single crystal (the second direction Y in this embodiment). The off-angle α may be greater than 0° and less than or equal to 10°. The off-angle α may have a value that falls within at least one of the following ranges: greater than 0° and less than or equal to 1°, 1° or more and less than or equal to 2.5°, 2.5° or more and less than or equal to 5°, 5° or more and less than or equal to 7.5°, and 7.5° or more and less than or equal to 10°.

[0024] The off-angle α is preferably 5° or less. The off-angle α is particularly preferably 2° or more and 4.5° or less. The off-angle α is typically set in the range of 4° ± 0.1°. This specification does not exclude a configuration in which the off-angle α is 0° (i.e., a configuration in which the first principal surface 3 is just plane to the c-plane).

[0025] The first to fourth sides 5A to 5D may have a length of 0.5 mm or more and 20 mm or less in a plan view. The length of the first to fourth sides 5A to 5D may be a value that falls within one of the following ranges: 0.5 mm or more and 1 mm or less, 1 mm or more and 2 mm or less, 2 mm or more and 5 mm or less, 5 mm or more and 10 mm or less, 10 mm or more and 15 mm or less, and 15 mm or more and 20 mm or less. The length of the first to fourth sides 5A to 5D may be 5 mm or more.

[0026] Referring to Figures 2 and 4, the semiconductor device 1A includes an n-type first semiconductor region 6 formed on the surface layer of the second main surface 4. A drain potential, which is a first potential (high potential), is applied to the first semiconductor region 6. The first semiconductor region 6 may also be referred to as the "base region (layer)", "semiconductor region (layer)", "drain region (layer)", etc.

[0027] The first semiconductor region 6 extends in layers along the second main surface 4 and is exposed from the second main surface 4 and the first to fourth side surfaces 5A to 5D. In this embodiment, the first semiconductor region 6 consists of an n-type semiconductor layer. Specifically, the first semiconductor region 6 consists of a substrate (SiC substrate) containing a SiC single crystal (semiconductor single crystal), and forms the second main surface 4 and the first to fourth side surfaces 5A to 5D. The first semiconductor region 6 (substrate) has the aforementioned off-direction and off-angle α (Figure 4).

[0028] The first semiconductor region 6 may have a thickness T1 (Figure 4) of 10 μm or more and 500 μm or less. The thickness T1 (Figure 4) of the first semiconductor region 6 may have a value that falls within at least one of the following ranges: 10 μm or more and 50 μm or less, 50 μm or more and 100 μm or less, 100 μm or more and 150 μm or less, 150 μm or more and 200 μm or less, 200 μm or more and 300 μm or less, 300 μm or more and 400 μm or more and 500 μm or less.

[0029] The semiconductor device 1A includes an n-type second semiconductor region 7 formed on the surface layer of the first main surface 3. The second semiconductor region 7 is an example of a semiconductor region. The second semiconductor region 7 may also be referred to as a "semiconductor region (layer)," "drift region (layer)," etc. The second semiconductor region 7 has an n-type impurity concentration less than that of the first semiconductor region 6. In a cross-sectional view, the second semiconductor region 7 is formed in the region on the first main surface 3 side relative to the first semiconductor region 6 and is electrically connected to the first semiconductor region 6.

[0030] The second semiconductor region 7 extends in layers along the first main surface 3 and is exposed from the first main surface 3 and the first to fourth side surfaces 5A to 5D. In this configuration, the second semiconductor region 7 consists of an n-type semiconductor layer. Specifically, the second semiconductor region 7 consists of an epitaxial layer (SiC epitaxial layer) containing a SiC single crystal (semiconductor single crystal), forming the first main surface 3 and the first to fourth side surfaces 5A to 5D.

[0031] The second semiconductor region 7 (epitaxial layer) has the aforementioned off-direction and off-angle (Figure 4). Preferably, the second semiconductor region 7 has a thickness T2 (Figure 4) that is less than the thickness T1 of the first semiconductor region 6. The thickness T2 of the second semiconductor region 7 may be greater than the thickness T1 of the first semiconductor region 6.

[0032] The thickness T2 of the second semiconductor region 7 (Figure 4) may be 5 μm or more and 15 μm or less. The thickness T2 of the second semiconductor region 7 may have a value that falls within at least one of the following ranges: 5 μm or more and 7.5 μm or less, 7.5 μm or more and 10 μm or less, 10 μm or more and 12.5 μm or less, and 12.5 μm or more and 15 μm or less.

[0033] Referring to Figures 2 to 4, the semiconductor device 1A includes an active region 8 set on the chip 2. The active region 8 includes a device structure (transistor structure Tr) and is the region where output current (drain current) is generated. The active region 8 is set in the inner part of the chip 2, spaced apart from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3.

[0034] The active region 8 is set to a polygonal shape (a quadrilateral in this embodiment) having four sides parallel to the periphery of the tip 2 in a plan view. The ratio of the planar area of ​​the active region 8 to the planar area of ​​the first main surface 3 (area ratio) may be 0.5 or more and 0.95 or less. The area ratio may also be 0.5 or more and 0.6 or less, 0.6 or more and 0.7 or less, 0.7 or more and 0.8 or less, 0.8 or more and 0.9 or less, or 0.9 or more and 0.95 or less.

[0035] The semiconductor device 1A includes an outer peripheral region 9 set outside the active region 8 on the chip 2. The outer peripheral region 9 is a region that does not include the device structure (transistor structure Tr). The outer peripheral region 9 is set at the periphery of the chip 2. In other words, the outer peripheral region 9 is located in the region between the periphery of the chip 2 and the active region 8 in a plan view. In a plan view, the outer peripheral region 9 extends in a band shape along the active region 8 and is set in a polygonal ring (a quadrilateral ring in this form) that surrounds the active region 8.

[0036] The semiconductor device 1A includes a plurality of trench-type (trench electrode-type) trench gate structures 15 formed in the active region 8. The trench gate structures 15 may also be referred to as "trench structures," "trench gate structures," etc.

[0037] Multiple trench gate structures 15 are formed in the inner part of the first main surface 3, spaced apart from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3, and are not formed in the outer peripheral region 9. In a plan view, the multiple trench gate structures 15 are arranged spaced apart in the first direction X (= m-axis direction) and each extends in a strip-like manner in the second direction Y (= a-axis direction). In a plan view, the multiple trench gate structures 15 are arranged in a stripe-like manner extending in the second direction Y.

[0038] The semiconductor device 1A includes a p-type outer well region 40 formed in the outer peripheral region 9. The outer well region 40 includes a terminal region 42 and a plurality of field regions 43.

[0039] Referring to Figures 3 and 4, the terminal region 42 is a rectangular annular region demarcated by a thick solid line and a thick dashed line. The terminal region 42 has a portion extending in a first direction X and a portion extending in a second direction Y. In this embodiment, the terminal region 42 is formed as a polygonal annular shape (a rectangular annular shape in this embodiment) with four sides parallel to the periphery of the chip 2 in a plan view, and surrounds a plurality of trench gate structures 15.

[0040] The terminal region 42 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter-circular arc shape). In this embodiment, the terminal region 42 is formed in the outer peripheral region 9 and surrounds the active region 8.

[0041] Referring to Figures 3 and 4, each of the field regions 43 has a portion extending in a first direction X and a portion extending in a second direction Y. In this embodiment, each field region 43 is formed as a polygonal ring (a quadrilateral ring in this embodiment) with four sides parallel to the periphery of the chip 2 in a plan view, and surrounds the terminal region 42. In other words, the multiple field regions 43 are formed at intervals from one another and surround the active region.

[0042] Each of the multiple field regions 43 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably in a quarter-circular arc shape). In this embodiment, the multiple field regions 43 are arranged in the outer peripheral region 9 with a gap between them and the terminal region 42.

[0043] Referring to Figure 2, the semiconductor device 1A includes a main surface insulating film 45 (see also Figures 9 and 10) that selectively covers the first main surface 3. The main surface insulating film 45 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. It is preferable that the main surface insulating film 45 contains the same type of insulating material as the first insulating film 17. In this embodiment, the main surface insulating film 45 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the main surface insulating film 45 includes a silicon oxide film made of the oxide of the chip 2.

[0044] The main surface insulating film 45 (see also Figures 9 and 10) is connected to the first insulating film 17 of the multiple trench gate structures 15 in the active region 8, exposing the first embedded electrodes 18 of the multiple trench gate structures 15.

[0045] The main surface insulating film 45 (see also Figures 9 and 10) covers the second semiconductor region 7, the termination region 42, the outer contact region 41, and the field region 43 in the outer peripheral region 9. In this embodiment, the main surface insulating film 45 is continuous with the first to fourth side surfaces 5A to 5D at the peripheral edge of the first main surface 3. The main surface insulating film 45 may be formed with a gap inward from the peripheral edge of the first main surface 3, exposing the peripheral edge of the first main surface 3 (the second semiconductor region 7).

[0046] Referring to Figures 1 and 2, the semiconductor device 1A includes an insulating interlayer film 47 formed on the first main surface 3. The interlayer film 47 may also be called an "insulating film," "interlayer insulating film," or "intermediate insulating film." The interlayer film 47 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. It is preferable that the interlayer film 47 includes a silicon oxide film.

[0047] The semiconductor device 1A includes a source electrode 51 disposed on the first main surface 3. The source electrode 51 is a terminal electrode to which a source potential is applied from the outside. The source electrode 51 may also be called a "source pad electrode," "first pad electrode," "first main surface electrode," "first terminal electrode," etc. The source electrode 51 is disposed on the portion of the interlayer film 47 that covers the active region 8.

[0048] Referring to Figure 1, in this embodiment, the source electrode 51 has a first pad portion 51a, a second pad portion 51b, and a third pad portion 51c. The first pad portion 51a has a relatively large surface area and forms the main body of the source electrode 51. In this embodiment, the first pad portion 51a is formed in a polygonal shape (a quadrilateral shape in this embodiment) with four sides parallel to the periphery of the tip 2 in a plan view, and is offset towards the fourth side surface 5D with respect to the central part of the first main surface 3.

[0049] The second pad portion 51b has a flat area less than that of the first pad portion 51a and extends in a strip-like (square-shaped) manner from one end of the first pad portion 51a in the second direction Y (the end on the first side surface 5A side) toward the third side surface 5C. The third pad portion 51c has a flat area less than that of the first pad portion 51a and extends in a strip-like (square-shaped) manner from the other end of the first pad portion 51a in the second direction Y (the end on the second side surface 5B side) toward the third side surface 5C, and faces the second pad portion 51b in the second direction Y.

[0050] The flat area of ​​the third pad portion 51c may be approximately equal to the flat area of ​​the second pad portion 51b. The flat area of ​​the third pad portion 51c may be larger than the flat area of ​​the second pad portion 51b, or it may be smaller than the flat area of ​​the second pad portion 51b. Either or both of the second pad portion 51b and the third pad portion 51c may be used as terminal portions for current monitoring.

[0051] The source electrode 51 does not necessarily have both the second pad portion 51b and the third pad portion 51c at the same time. The source electrode 51 may have only one of the second pad portion 51b and the third pad portion 51c. The source electrode 51 may consist only of the first pad portion 51a and not have both the second pad portion 51b and the third pad portion 51c.

[0052] The semiconductor device 1A includes source wiring 56 arranged around the source electrode 51 on the interlayer film 47. The source wiring 56 is supplied with the same potential (source potential) as the potential supplied to the source electrode 51 (source potential). The source wiring 56 may also be referred to as "termination electrode (wiring)", "wiring", "first wiring", "finger electrode", "source finger", etc.

[0053] The source wiring 56 has a wiring width less than the electrode width of the source electrode 51 and is selectively routed on the interlayer film 47. In this configuration, the source wiring 56 is led out from the source electrode 51 (first pad portion 51a) to the fourth side surface 5D. The source wiring 56 is led out from the active region 8 to the outer peripheral region 9.

[0054] The source wiring 56 extends in a strip shape along the periphery of the first main surface 3 (the periphery of the active region 8). In this embodiment, the source wiring 56 is formed in a polygonal ring shape (a quadrilateral ring shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and surrounds the inner part of the first main surface 3 (active region 8). The source wiring 56 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter-circular arc shape). The source wiring 56 may be ended or endless.

[0055] The semiconductor device 1A includes a gate electrode 57 disposed on the first main surface 3. The gate electrode 57 is a terminal electrode to which a gate potential is applied from the outside. The gate electrode 57 may also be referred to as the "second pad electrode," "second main surface electrode," "second terminal electrode," etc.

[0056] The gate electrode 57 is positioned at a distance from the source electrode 51 on the portion of the interlayer film 47 that covers the active region 8. In this configuration, the gate electrode 57 is positioned in the region on the third side surface 5C side with respect to the first pad portion 51a and faces the first pad portion 51a in the first direction X. The gate electrode 57 is interposed in the region between the second pad portion 51b and the third pad portion 51c and faces both the second pad portion 51b and the third pad portion 51c in the second direction Y.

[0057] The gate electrode 57 is formed in a polygonal shape (a quadrilateral in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view. The gate electrode 57 has a planar area less than that of the source electrode 51. The gate electrode 57 has a planar area less than that of the first pad portion 51a. The gate electrode 57 may also have a planar area less than that of the second pad portion 51b (third pad portion 51c).

[0058] The semiconductor device 1A includes gate wiring 58 drawn out from the gate electrode 57 onto the first main surface 3. The gate wiring 58 may also be referred to as "wiring," "second wiring," "finger electrode," "gate finger," etc. The gate wiring 58 transmits the gate potential applied to the gate electrode 57 to other regions.

[0059] The gate wiring 58 is drawn out from the gate electrode 57 onto the portion of the interlayer film 47 that covers the active region 8, and is routed in the region between the source electrode 51 and the source wiring 56, spaced apart from the source electrode 51 and the source wiring 56.

[0060] The gate wiring 58 has a portion that extends in a strip shape in a first direction X and a portion that extends in a strip shape in a second direction Y in a plan view, and intersects (specifically orthogonally) with the ends (both ends in this embodiment) of the plurality of trench gate structures 15. In this embodiment, the gate wiring 58 is formed in an end-band shape having four sides parallel to the periphery of the first main surface 3, and surrounds the source electrode 51.

[0061] Referring to Figure 2, the semiconductor device 1A includes a drain electrode 59 that covers the second main surface 4. The drain electrode 59 is a terminal electrode to which a drain potential is applied from the outside. The drain electrode 59 may also be referred to as the "third pad electrode," "third main surface electrode," "third terminal electrode," etc.

[0062] The drain electrode 59 is electrically connected to the first semiconductor region 6. The drain electrode 59 may cover the entire area of ​​the second main surface 4 so as to be continuous with the periphery of the second main surface 4 (first to fourth side surfaces 5A to 5D). The drain electrode 59 may partially cover the second main surface 4 so as to expose the periphery of the second main surface 4.

[0063] The breakdown voltage that can be applied between the source electrode 51 and the drain electrode 59 (between the first main surface 3 and the second main surface 4) may be 500V or more and 3000V or less. The breakdown voltage may have a value that falls within at least one of the following ranges: 500V or more and 750V or less, 750V or more and 1000V or less, 1000V or more and 1250V or less, 1250V or more and 1500V or less, 1500V or more and 1750V or less, 1750V or more and 2000V or less, 2000V or more and 2250V or less, 2250V or more and 2500V or less, 2500V or more and 2750V or more and 3000V or less.

[0064] Figure 5 is an enlarged plan view showing a key part of the first main surface 3 shown in Figure 3. Figure 6 is an enlarged plan view showing a key part of the first main surface 3 shown in Figure 3. Figure 7 is a cross-sectional view along the line VII-VII shown in Figure 5. Figure 8 is a cross-sectional view along the line VIII-VIII shown in Figure 5. Figure 9 is a cross-sectional view showing the cross-sectional structure of the outer peripheral region 9 along the line IX-IX shown in Figure 1. Figure 10 is an enlarged cross-sectional view of a region shown in Figure 9. Figure 11 is a plan view showing an example of the layout of the chip 2.

[0065] Referring to FIGS. 5 to 11, the transistor structure Tr formed in the active region 8 of the semiconductor device 1A and the configuration within the outer peripheral region 9 will be described.

[0066] The semiconductor device 1A includes a p-type body region 10 formed in the surface layer portion of the first main surface 3 in the active region 8 (the inner part of the first main surface 3). The body region 10 may be referred to as an "impurity region", a "channel region", etc. A source potential may be applied to the body region 10. The source potential may be a reference potential that serves as a reference for circuit operation. The reference potential may be a ground potential. The body region 10 has a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor region 7. The body region 10 has, for example, a p-type impurity concentration of 1×10 １７ cm －３ or more and 1×10 １８ cm －３ or less as a peak value.

[0067] Referring to FIG. 9, the body region 10 is formed in the inner part of the first main surface 3 at a distance from the periphery of the first main surface 3 (the first to fourth side surfaces 5A to 5D) and is not formed in the outer peripheral region 9. In this form, the body region 10 is formed over the entire active region 8. The body region 10 is formed in the surface layer portion of the second semiconductor region 7 and extends in a layer shape along the first main surface 3.

[0068] Referring to FIGS. 7 to 9, the body region 10 is formed at a distance from the bottom portion (the first semiconductor region 6) of the second semiconductor region 7 toward the first main surface 3 side and faces the first semiconductor region 6 with a part of the second semiconductor region 7 interposed therebetween. The body region 10 is formed at a distance from the depth position of the middle portion of the second semiconductor region 7 toward the first main surface 3 side.

[0069] The body region 10 is formed in the region on the first main surface 3 side relative to the second semiconductor region 7 in a cross-sectional view, and is electrically connected to the second semiconductor region 7. The body region 10 forms a pn junction (body diode) with the second semiconductor region 7. When a reverse bias voltage is applied, the body region 10 expands a depletion layer in the second semiconductor region 7. The depletion layer, starting from the body region 10, expands horizontally and in the thickness direction within the second semiconductor region 7.

[0070] Referring to Figures 5 to 7, the semiconductor device 1A includes an n-type source region 11 formed on the surface of the first main surface 3 in the active region 8. A source potential is applied to the source region 11. The source region 11 has a higher n-type impurity concentration than the n-type impurity concentration of the second semiconductor region 7. The n-type impurity concentration of the source region 11 is higher than the p-type impurity concentration of the body region 10.

[0071] The source region 11 is formed in the inner part of the first main surface 3, spaced apart from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3, and is not formed in the outer peripheral region 9. The source region 11 may also be formed inward from the periphery of the body region 10, spaced apart. The source region 11 is formed on the surface layer of the body region 10 and extends in layers along the first main surface 3.

[0072] The source region 11 is formed at a distance from the bottom of the body region 10 toward the first main surface 3, and faces the second semiconductor region 7 across a portion of the body region 10. In a cross-sectional view, the source region 11 is formed in the region toward the first main surface 3 relative to the body region 10 and is electrically connected to the body region 10.

[0073] Referring to Figures 7 and 8, the semiconductor device 1A includes a plurality of trench gate structures 15 formed in the inner part of the first main surface 3. The trench gate structures 15 may also be referred to as "trench structures," "gate structures," etc. A gate potential (gate signal) is applied to the plurality of trench gate structures 15 as a control potential. The plurality of trench gate structures 15 control the inversion and non-inversion of channels within the body region 10 in response to the gate potential.

[0074] Multiple trench gate structures 15 are formed in the inner part of the first main surface 3, spaced apart from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3, and are not formed in the outer peripheral region 9. In a plan view, the multiple trench gate structures 15 are arranged spaced apart in the first direction X (= m-axis direction) and each extends in a strip-like manner in the second direction Y (= a-axis direction). In a plan view, the multiple trench gate structures 15 are arranged in a stripe-like manner extending in the second direction Y.

[0075] The extension direction of the multiple trench gate structures 15 coincides with the off-direction of the SiC single crystal. With respect to the second direction Y, both ends of the multiple trench gate structures 15 may be located in the region between the periphery of the body region 10 and the periphery of the source region 11. The multiple trench gate structures 15 may be arranged at intervals in the second direction Y in a plan view and each may extend in a strip shape in the first direction X.

[0076] Multiple trench gate structures 15 penetrate the body region 10 and the source region 11 so as to reach the second semiconductor region 7. The multiple trench gate structures 15 are formed at intervals from the depth position at the bottom of the second semiconductor region 7 toward the first main surface 3, and face the first semiconductor region 6 with a portion of the second semiconductor region 7 in between.

[0077] The multiple trench gate structures 15 may be formed at intervals from the depth position of the middle part of the second semiconductor region 7 toward the first main surface 3, or they may be located toward the bottom of the second semiconductor region 7 relative to the depth position of the middle part of the second semiconductor region 7. The multiple trench gate structures 15 are formed substantially perpendicular to the first main surface 3. The multiple trench gate structures 15 may be formed in a tapered shape toward the bottom of the second semiconductor region 7.

[0078] The side walls (long sides) of the multiple trench gate structures 15 are formed by the m-plane ((1-100) plane) of the SiC single crystal. The side walls (long sides) of the multiple trench gate structures 15 may also be formed by the a-plane ((11-20) plane) of the SiC single crystal depending on the direction of extension of the trench gate structure 15. The bottom walls of the multiple trench gate structures 15 are formed by the c-plane (Si plane) of the SiC single crystal. It is preferable that the bottom walls of the multiple trench gate structures 15 extend substantially flat along the horizontal direction. The bottom walls of the multiple trench gate structures 15 may be curved in an arc toward the second main surface 4. The inclination angle (absolute value) of the side walls (long sides) of the trench gate structures 15 with respect to the vertical line may be 85° or more and 95° or less.

[0079] The trench gate structure 15 may have a width of 0.1 μm or more and 2 μm or less. The trench gate structure 15 may have a depth of 0.1 μm or more and 3 μm or less. The depth of the trench gate structure 15 is the depth when the first main surface 3 is used as the reference. The trench gate structure 15 may have an aspect ratio of 1 or more and 3 or less. The aspect ratio of the trench gate structure 15 is the ratio of the depth of the trench gate structure 15 to the width of the trench gate structure 15. The aspect ratio is preferably 1.5 or more and 2.5 or less.

[0080] Each of the multiple trench gate structures 15 includes a first trench 16, a first insulating film 17, and a first embedded electrode 18. The first trench 16 is formed on the first main surface 3 and defines the wall surfaces (side walls and bottom walls) of the trench gate structure 15.

[0081] The first insulating film 17 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the first insulating film 17 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the first insulating film 17 includes a silicon oxide film made of the oxide of the chip 2. The first insulating film 17 covers the wall surface of the first trench 16. The first insulating film 17 may have a thickness of 10 nm to 150 nm.

[0082] The first embedded electrode 18 is embedded in the first trench 16 with the first insulating film 17 in between. The first embedded electrode 18 may contain either or both p-type conductive polysilicon and n-type conductive polysilicon. The first embedded electrode 18 faces the second semiconductor region 7, the body region 10, and the source region 11 with the first insulating film 17 in between.

[0083] The first embedded electrode 18 has an electrode surface exposed from the first trench 16. The electrode surface is located on the bottom wall side of the first trench 16 with respect to the height position of the first main surface 3. The electrode surface is located on the first main surface 3 side with respect to the depth position of the bottom of the source region 11. The electrode surface has a recess that tapers inward toward the bottom wall of the first trench 16.

[0084] The semiconductor device 1A includes gate well regions 25 formed in the region below each of the multiple trench gate structures 15 within the chip 2 (second semiconductor region 7) of the active region 8. A source potential is applied to the gate well regions 25. The gate well regions 25 have a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor region 7. The p-type impurity concentration of the gate well regions 25 may be higher than or lower than the p-type impurity concentration of the body region 10. The p-type impurity (trivalent element) in the gate well regions 25 is preferably aluminum.

[0085] Multiple gate well regions 25 are formed within the second semiconductor region 7, spaced apart from each other in the horizontal direction (first direction X), in regions below (specifically, directly below) the multiple trench gate structures 15. The multiple gate well regions 25 are formed in the thickness range between the bottom of the second semiconductor region 7 and the bottom walls of the multiple trench gate structures 15, and overlap with the multiple trench gate structures 15 in a one-to-one correspondence in the thickness direction.

[0086] The multiple gatewell regions 25 each extend in a strip-like manner in the second direction Y, following the extension direction of the corresponding trench gate structure 15 in a plan view. In other words, the multiple gatewell regions 25 are arranged in a stripe-like pattern extending in the second direction Y in a plan view.

[0087] The extension directions of the multiple gatewell regions 25 coincide with the off-direction of the SiC single crystal. The multiple gatewell regions 25 may also extend in a first direction X depending on the extension direction of the multiple trench gate structures 15. In this case, the multiple gatewell regions 25 intersect (specifically orthogonally) in the off-direction.

[0088] Multiple gate well regions 25 are formed at intervals from the bottom of the second semiconductor region 7 towards the bottom wall side of the multiple trench gate structures 15, and face the first semiconductor region 6 across a portion of the second semiconductor region 7. Each of the multiple gate well regions 25 has an upper end located on the bottom wall side of the corresponding trench gate structure 15, and a bottom (well bottom) located on the bottom side (second main surface 4 side) of the second semiconductor region 7.

[0089] The upper ends of the multiple gate well regions 25 are formed with a gap between them, extending from the bottom of the body region 10 towards the bottom wall of the corresponding trench gate structure 15. The upper ends of the multiple gate well regions 25 may be connected to the bottom wall of the corresponding trench gate structure 15. The upper ends of the multiple gate well regions 25 may have portions that run along the side walls of the corresponding trench gate structure 15. The upper ends of the multiple gate well regions 25 may be formed with a gap between them, extending from the bottom wall of the corresponding trench gate structure 15 towards the bottom of the second semiconductor region 7.

[0090] Multiple gate well regions 25 include bulging portions 25a. The bulging portions 25a extend horizontally in an arc shape from the region directly below the corresponding trench gate structure 15 to both sides of the corresponding trench gate structure 15. Each of the multiple gate well regions 25 is formed in a tapering shape from the bulging portion 25a toward the well bottom 25b.

[0091] The gatewell region 25 may have a width greater than the width of the trench gate structure 15, or a width less than the width of the trench gate structure 15. The width of the gatewell region 25 may be 0.1 μm or more and 2 μm or less.

[0092] The gatewell region 25 may have a depth less than the depth of the trench gate structure 15, or a depth greater than the depth of the trench gate structure 15. The depth of the gatewell region 25 is the depth of the gatewell region 25 when the bottom wall of the trench gate structure 15 is used as the reference point. The depth of the gatewell region 25 may be greater than 0 μm and 5 μm or less.

[0093] The gatewell region 25 may have an aspect ratio greater than 0 and less than or equal to 2. The aspect ratio of the gatewell region 25 is the ratio of the depth of the gatewell region 25 to the width of the gatewell region 25.

[0094] The gate well region 25 forms a pn junction with the second semiconductor region 7. When a reverse bias voltage is applied, the gate well region 25 expands a depletion layer in the second semiconductor region 7. The depletion layer, originating from the gate well region 25, expands in the horizontal and thickness directions, mitigating the electric field for the active region 8 (trench gate structure 15).

[0095] Referring to Figures 5, 6, and 8, the semiconductor device 1A includes a plurality of gate contact regions 27 formed within the chip 2 (second semiconductor region 7) in the active region 8. A source potential is applied to the gate contact regions 27.

[0096] The gate contact region 27 has a higher p-type impurity concentration than the n-type impurity concentration of the second semiconductor region 7. The p-type impurity concentration in the gate contact region 27 is higher than the p-type impurity concentration in the body region 10. The p-type impurity concentration in the gate contact region 27 is higher than the p-type impurity concentration in the gate well region 25.

[0097] Multiple gate contact regions 27 are formed in regions along multiple trench gate structures 15 at intervals from each other. The multiple gate contact regions 27 are formed in a one-to-many correspondence with the multiple trench gate structures 15. The multiple gate contact regions 27 are formed at intervals in the second direction Y, following the extending direction of the corresponding trench gate structure 15.

[0098] With respect to one trench gate structure 15 and the other, the multiple gate contact regions 27 along one trench gate structure 15 are opposite the multiple gate contact regions 27 along the other trench gate structure 15 in the first direction X when viewed from above. In other words, the multiple gate contact regions 27 are arranged in a matrix with spacing in the first direction X and the second direction Y when viewed from above.

[0099] One set of gate contact regions 27 may be facing the region between the other set of gate contact regions 27 in a plan view in the first direction X. In other words, the set of gate contact regions 27 may be arranged in a staggered pattern with spacing between them in the first direction X and the second direction Y in a plan view.

[0100] In this embodiment, the multiple gate contact regions 27 extend in a strip-like manner along the multiple trench gate structures 15 in a plan view. The lengths of the multiple gate contact regions 27 in the second direction Y may be equal to or different from each other. The lengths of the multiple gate contact regions 27 in the second direction Y are adjusted according to the channel area to be formed.

[0101] The channel area is the total area of ​​the portion of the source region 11 exposed by the multiple gate contact regions 27. In other words, the channel area increases or decreases in proportion to the increase or decrease in the ratio of the total planar area of ​​the multiple gate contact regions 27. It is preferable that the total planar area of ​​the multiple gate contact regions 27 is less than the channel area.

[0102] In other words, in the region between a pair of adjacent trench gate structures 15, it is preferable that the total planar area of ​​the multiple gate contact regions 27 is less than the planar area of ​​the source region 11. With such a configuration, the increase in resistance (on-resistance) caused by short channels is suppressed.

[0103] The length of the gate contact region 27 may be greater than or less than the width of the trench gate structure 15. The length of the gate contact region 27 may be greater than or less than the pitch of the trench gate structure 15. The length of the gate contact region 27 may be greater than or less than the pitch of two adjacent trench gate structures 15.

[0104] The spacing between the multiple gate contact regions 27 may be greater than or less than the width of the trench gate structure 15. The spacing between the gate contact regions 27 may be greater than or less than the pitch of the trench gate structure 15. The spacing between the gate contact regions 27 may be greater than or less than the pitch of two adjacent trench gate structures 15.

[0105] Multiple gate contact regions 27 are interposed in the regions between the bottom walls of multiple trench gate structures 15 and the bottoms of multiple gate well regions 25. Each of the gate contact regions 27 is connected to the corresponding bottom wall of the trench gate structure 15 and the corresponding gate well region 25.

[0106] Multiple gate contact regions 27 increase the concentration of p-type impurities at the upper end of the corresponding gate well region 25. The gate contact regions 27 extend from the region directly below the trench gate structure 15 to both sides of the trench gate structure 15 and have extensions that extend along the side walls of the trench gate structure 15.

[0107] The horizontal (first direction X) thickness of the portion of the gate contact region 27 that runs along the side wall of the trench gate structure 15 (extension) may be less than the vertical Z thickness of the portion of the gate contact region 27 that runs along the bottom wall of the trench gate structure 15.

[0108] The extension of the gate contact region 27 is electrically connected to the body region 10 at the surface layer of the first main surface 3, and the corresponding gate well region 25 is electrically connected to the body region 10. This suppresses the gate well region 25 from becoming electrically detached, and improves the electrical response characteristics of the gate well region 25.

[0109] The gate contact region 27 has an upper end exposed from the first main surface 3. In this embodiment, the upper end of the gate contact region 27 is exposed from the side wall of the first trench 16 at the opening end of the first trench 16. The upper end of the gate contact region 27 may extend horizontally in the surface layer of the body region 10.

[0110] Referring to Figures 7 to 9, the second semiconductor region 7 of the semiconductor device 1A includes a first epitaxial layer 71. The first epitaxial layer 71 is formed over the entire area of ​​the second semiconductor region 7 in a plan view and is exposed from the first to fourth side surfaces 5A to 5D.

[0111] The first epitaxial layer 71 may also be referred to as a "low-concentration layer," "low-concentration epitaxial layer," "low-concentration region," "base region," etc. The thickness of the first epitaxial layer 71 may be, for example, 0.5 μm or more and 20 μm or less. Preferably, the thickness of the first epitaxial layer 71 is 1 μm or more and 10 μm or less.

[0112] The n-type impurity concentration of the first epitaxial layer 71 is preferably less than the n-type impurity concentration of the first semiconductor region 6. The first epitaxial layer 71 is 1 × 10⁻⁶ １６ cm －３ The above 1 x 10 １７ cm －３ The following n-type impurity concentrations may be present as peak values. The n-type impurity concentration of the first epitaxial layer 71 may be approximately constant in the thickness direction. Of course, the n-type impurity concentration of the first epitaxial layer 71 may have a concentration gradient that gradually increases and / or decreases in the thickness direction (crystal growth direction) of the chip 2.

[0113] Referring to Figure 9, the outermost trench gate structure 15 among the multiple trench gate structures 15 is the terminal trench gate structure 15A. In this configuration, the multiple trench gate structures 15 arranged in a stripe shape extending along the second direction Y have one terminal trench gate structure 15A formed at each end of both sides of the first direction X (the third side surface 5C side and the fourth side surface 5D side) (see also Figures 3 and 4). Figure 9 shows the terminal trench gate structure 15A on the fourth side surface 5D side. This is a boundary trench that forms the outer peripheral boundary 19, which is the boundary between the active region 8 and the outer peripheral region 9. The terminal trench gate structure 15A has the same structure as the remaining trench gate structures 15, except for its arrangement in the stripe.

[0114] Referring to Figures 2 and 9, the semiconductor device 1A includes a p-type outer well region 40 formed on the surface layer of the first main surface 3 in the outer peripheral region 9. A source potential is applied to the outer well region 40. The outer well region 40 has a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor region 7.

[0115] The p-type impurity concentration in the outer well region 40 is less than the p-type impurity concentration in the gate well region 25. The p-type impurity concentration in the outer well region 40 is less than the p-type impurity concentration in the gate contact region 27.

[0116] The p-type impurity concentration in the outer well region 40 may be approximately equal to the p-type impurity concentration in the gate well region 25. The p-type impurity concentration in the outer well region 40 may be higher than the p-type impurity concentration in the gate well region 25, or it may be lower than the p-type impurity concentration in the gate well region 25.

[0117] The p-type impurity concentration in the outer well region 40 may be approximately equal to the p-type impurity concentration in the body region 10. It may also be higher than the p-type impurity concentration in the body region 10, or lower than the p-type impurity concentration in the body region 10.

[0118] As described above, the outer well region 40 includes a termination region 42 and a plurality of field regions 43. The termination region 42 and the field regions 43 may be referred to as the "first outer well region" and the "second outer well region," respectively. Alternatively, the termination region 42 and the plurality of field regions 43 may be collectively referred to as the "outer well region." The termination region 42 may be referred to as the "termination well region," the "JTE region (Junction Termination Extension region)," etc. The field regions 43 may be referred to as the "guard region," the "field limit region," etc.

[0119] A source potential is applied to the termination region 42. The termination region 42 has a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor region 7.

[0120] Referring mainly to Figure 9, the termination region 42 is formed on the surface of the second semiconductor region 7 and is electrically connected to the second semiconductor region 7. The termination region 42 is formed with a gap from the bottom of the second semiconductor region 7 toward the first main surface 3 and faces the first semiconductor region 6 across a part of the second semiconductor region 7. Preferably, the termination region 42 is formed with a gap from the depth position of the middle part of the second semiconductor region 7 toward the first main surface 3.

[0121] The terminal region 42 is formed deeper than the gatewell region 25 along the outer peripheral boundary 19. The depth of the terminal region 42 may be, for example, greater than 0 μm and 4 μm or less. The terminal region 42 may also be approximately the same depth as the gatewell region 25.

[0122] The termination region 42 expands a depletion layer in the second semiconductor region 7 when a reverse bias voltage is applied. The depletion layer, starting from the termination region 42, expands in the horizontal and thickness directions, mitigating the electric field near the outer peripheral boundary 19 between the active region 8 and the outer peripheral region 9.

[0123] The terminal region 42 of the semiconductor device 1A includes a stacked structure of a first region 12 and a second region 13. The stacked structure may be a two-layer structure including a lower layer consisting of the first region 12 and an upper layer consisting of the second region 13. The first region 12 may be referred to as the "base region," "base layer," etc. The second region 13 may be referred to as the "high-density region," "high-density layer," "outer body region," etc.

[0124] The first region 12 is formed away from the first main surface 3, on the second main surface 4 side of the bottom of the body region 10. The first region 12 is formed in a layered manner extending along the first main surface 3 at a position away from the first main surface 3 on the second main surface 4 side. The first region 12 is formed over the entire surface layer on the second main surface 4 side of the end region 42 and may be exposed from the first side of the end region 42.

[0125] The first region 12 may be formed so as to cross the bottom of the first trench 16 in the thickness direction of the second semiconductor region 7. The first region 12 may have an upper part on the first main surface 3 side and a lower part on the second main surface 4 side with respect to the bottom of the first trench 16.

[0126] The p-type impurity concentration in the first region 12 may be lower than the p-type impurity concentration in the gate contact region 27. The p-type impurity concentration in the first region 12 may be higher than the p-type impurity concentration in the gate well region 25, or lower than the p-type impurity concentration in the gate well region 25. The p-type impurity concentration in the first region 12 may be lower than the p-type impurity concentration in the body region 10. The first region 12 is 1 × 10 １６ cm －３ The above 1 x 10 １７ cm －３ The following p-type impurity concentrations may be present as peak values.

[0127] The second region 13 is formed on the side of the first main surface 3 that is lower than the bottom of the body region 10 and is exposed from the first main surface 3. The second region 13 is formed in a layered manner that extends along the first main surface 3. The second region 13 may be formed over the entire surface layer of the end region 42 on the side of the first main surface 3 and may be exposed from the side of the end region 42. As a result, the end region 42 may have a layered structure in which the annular first region 12 and the annular second region 13 are stacked.

[0128] Referring to Figure 11, the second region 13 may be an outer body region extended from the body region 10 toward the outer peripheral region 9. In this embodiment, the second region 13 extends outward from the body region 10 between adjacent trench gate structures 15 and is formed in an annular shape surrounding a plurality of striped trench gate structures 15. In Figure 11, the second region 13 (outer body region) is shown with hatching.

[0129] The second region 13 may be formed in the thickness direction of the second semiconductor region 7 on the side of the first main surface 3 that is below the bottom of the first trench 16. The p-type impurity concentration of the second region 13 may be lower than the p-type impurity concentration of the gate contact region 27. The p-type impurity concentration of the second region 13 may be higher than or lower than the p-type impurity concentration of the gate well region 25. In this embodiment, the p-type impurity concentration of the second region 13 is equal to the p-type impurity concentration of the body region 10. The second region 13 is 1 × 10 １７ cm －３ The above 1 x 10 １８ cm －３ The following p-type impurity concentrations may be present as peak values.

[0130] Referring to Figure 9, the semiconductor device 1A includes a p-type outer contact region 41 formed on the surface layer of the first main surface 3 in the outer peripheral region 9. A source potential is applied to the outer contact region 41. The outer contact region 41 has a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor region 7. The p-type impurity concentration of the outer contact region 41 is higher than the p-type impurity concentration of the second region 13 of the body region 10 and the termination region 42.

[0131] The p-type impurity concentration in the outer contact region 41 is higher than the p-type impurity concentration in the gatewell region 25. The p-type impurity concentration in the outer contact region 41 may be approximately equal to the p-type impurity concentration in the gatewell region 25. The p-type impurity concentration in the outer contact region 41 may be lower than the p-type impurity concentration in the gatewell region 25.

[0132] The p-type impurity concentration in the outer contact region 41 may be approximately equal to the p-type impurity concentration in the gate contact region 27. The p-type impurity concentration in the outer contact region 41 may be higher than or lower than the p-type impurity concentration in the gate contact region 27.

[0133] The outer contact region 41 is formed on the surface of the terminal region 42. That is, the outer contact region 41 is formed in the thickness range between the first main surface 3 and the bottom of the terminal region 42. In this embodiment, the outer contact region 41 is selectively formed at the upper end of the terminal region 42. The outer contact region 41 is selectively formed on the surface of the second region 13 of the terminal region 42. The outer contact region 41 is formed on the first main surface 3 side with respect to the boundary between the first region 12 and the second region 13, and away from the boundary. The p-type impurity concentration of the terminal region 42 is increased, improving the electrical response speed of the terminal region 42.

[0134] The outer contact region 41 extends in a strip shape along the end trench gate structure 15A in the second direction Y. The outer contact region 41 extends in a strip shape across the multiple trench gate structures 15 in the first direction X.

[0135] In this embodiment, the outer contact region 41 is formed as a polygonal ring (a quadrangular ring in this embodiment) having four sides parallel to the periphery of the tip 2 in a plan view, and surrounds the inner portion (active region 8) of the first main surface 3. The outer contact region 41 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter-circular arc shape).

[0136] Multiple outer contact regions 41 may be formed at intervals following the extending direction of the end trench gate structure 15A and the direction traversing the multiple trench gate structures 15.

[0137] The outer contact region 41 has a width less than the width of the terminal region 42 and is formed within the terminal region 42. The outer contact region 41 has an inner edge on the inner side (active region 8 side) of the first main surface 3 and an outer edge on the peripheral side of the first main surface 3.

[0138] In this embodiment, the inner edge of the outer contact region 41 is connected to the terminal trench gate structure 15A. In this embodiment, the inner edge of the outer contact region 41 is connected to the corresponding gate well region 25. The inner edge of the outer contact region 41 extends along the terminal trench gate structure 15A (outer peripheral boundary 19) in the thickness direction of the second semiconductor region 7 and is connected to the corresponding gate well region 25. The terminal region 42 is electrically connected to the body region 10 via the corresponding gate well region 25.

[0139] The outer contact region 41 has a width greater than the width of the gate well region 25. The width of the outer contact region 41 is greater than the width of the terminal trench gate structure 15A. The width of the outer contact region 41 may be less than the width of the terminal region 42. The width of the outer contact region 41 may be greater than 0 μm and 300 μm or less.

[0140] The outer contact region 41 has an upper end located on the first main surface 3 side and a bottom located on the bottom side of the terminal region 42. The upper end of the outer contact region 41 is exposed from the first main surface 3. The bottom of the outer contact region 41 is located on the first main surface 3 side with respect to the depth position of the bottom of the gate well region 25.

[0141] The bottom of the outer contact region 41 is located on the first main surface 3 side with respect to the depth position of the bottom of the terminal region 42. The bottom of the outer contact region 41 may be located on the first main surface 3 side with respect to the depth position of the bottom of the body region 10, or it may be located on the bottom side of the terminal region 42. The depth (thickness) of the outer contact region 41 may be greater than 0 μm and 1 μm or less.

[0142] Referring to Figures 9 and 10, the multiple field regions 43 are formed on the surface of the second semiconductor region 7 and are electrically connected to the second semiconductor region 7. The multiple field regions 43 are formed at intervals from the bottom of the second semiconductor region 7 toward the first main surface 3 and face the first semiconductor region 6 across a portion of the second semiconductor region 7. Preferably, the multiple field regions 43 are formed at intervals from the depth position of the middle part of the second semiconductor region 7 toward the first main surface 3.

[0143] The number of field regions 43 is arbitrary. The number of field regions 43 may be between 1 and 15. The number of field regions 43 may be 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, or 15. Typically, the number of field regions 43 is between 1 and 10. In this embodiment, semiconductor device 1A includes, as an example, 4 field regions 43.

[0144] Referring to Figure 10, the multiple field regions 43 may have a width W1 less than the width of the terminal region 42. The width W1 of the multiple field regions 43 may be smaller than the width of the trench gate structure 15, or larger than the width of the trench gate structure 15. The width W1 of the field regions 43 may be smaller than the width of the gate well region 25, or larger than the width of the gate well region 25.

[0145] The width W1 of the field region 43 may be greater than 0 μm and 5 μm or less. The width W1 of the field region 43 may have a value that falls within at least one of the following ranges: greater than 0 μm and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, 1.75 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0146] In this configuration, the widths W1 of the multiple field regions 43 are approximately equal to each other. The widths W1 of the multiple field regions 43 are arbitrary and can take various values ​​depending on the electric field to be mitigated. The widths W1 of the multiple field regions 43 may also be different from each other.

[0147] The width W1 of the multiple field regions 43 may increase sequentially toward the periphery of the first main surface 3. The width W1 of the multiple field regions 43 may increase toward the periphery of the first main surface 3 in units of two or more groups, each containing two or more field regions 43.

[0148] The width W1 of the multiple field regions 43 may decrease sequentially toward the periphery of the first main surface 3. The width W1 of the multiple field regions 43 may decrease toward the periphery of the first main surface 3 in units of two or more groups, each containing two or more field regions 43.

[0149] The spacing between multiple field regions 43 may be less than or equal to the width W1 of each field region 43. Preferably, the spacing between multiple field regions 43 is less than the width W1 of each field region 43. As shown in Figure 10, the spacing between multiple field regions 43 may be greater than the width W1 of each field region 43.

[0150] In this configuration, the spacing between the multiple field regions 43 is approximately equal to each other. The spacing between the multiple field regions 43 is arbitrary and can take various values ​​depending on the electric field to be relaxed. The spacing between the multiple field regions 43 may also be different from each other.

[0151] The spacing between the multiple field regions 43 may increase sequentially toward the periphery of the first main surface 3. The spacing between the multiple field regions 43 may also increase toward the periphery of the first main surface 3 in units of two or more groups, each containing two or more field regions 43.

[0152] The spacing between the multiple field regions 43 may decrease sequentially toward the periphery of the first main surface 3. The spacing between the multiple field regions 43 may decrease toward the periphery of the first main surface 3 in units of two or more groups, each containing two or more field regions 43.

[0153] The spacing of the field regions 43 may be greater than 0 μm and less than or equal to 5 μm. The spacing may have a value that falls within at least one of the following ranges: greater than 0 μm and less than or equal to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm.

[0154] The ratio of the spacing between field areas 43 to the width W1 of the field area 43 (spacing ratio) may be 0.1 or more and 5 or less. The spacing ratio may have a value that belongs to at least one of the following ranges: 0.1 or more and 0.5 or less, 0.5 or more and 1 or less, 1 or more and 1.5 or less, 1.5 or more and 2 or less, 2 or more and 2.5 or less, 2.5 or more and 3 or less, 3 or more and 3.5 or less, 3.5 or more and 4 or more and 4 or more and 4.5 or less, and 4.5 or more and 5 or less.

[0155] The multiple field regions 43 expand a depletion layer in the second semiconductor region 7 when a reverse bias voltage is applied. The depletion layer originating from the multiple field regions 43 expands in the horizontal and thickness directions and integrates with the depletion layer originating from the terminal region 42. The multiple field regions 43 extend the depletion layer originating from the terminal region 42 toward the periphery of the first main surface 3, thereby mitigating the electric field at the peripheral portion (outer peripheral region 9) of the first main surface 3.

[0156] Referring to Figures 9 and 10, in the outer peripheral region 9, a second epitaxial layer 72 is formed on the surface layer of the second semiconductor region 7 of the semiconductor device 1A. In other words, in the outer peripheral region 9, the second semiconductor region 7 includes a laminated structure of a first epitaxial layer 71 and a second epitaxial layer 72 formed on the first epitaxial layer 71. The second epitaxial layer 72 may also be referred to as a "high-density layer," "high-density epitaxial layer," "high-density region," etc.

[0157] The second epitaxial layer 72 is in contact with the terminal region 42 and is formed in a layered manner extending along the first main surface 3. In a plan view, the second epitaxial layer 72 is formed over the entire outer peripheral region 9 and is exposed from the first to fourth side surfaces 5A to 5D.

[0158] The thickness of the second epitaxial layer 72 may be, for example, greater than 0 μm and 2 μm or less. The thickness of the second epitaxial layer 72 may have a value that falls within at least one of the following ranges: greater than 0 μm and 0.2 μm or less, 0.2 μm or more and 0.4 μm or less, 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, 0.8 μm or more and 1 μm or less, 1 μm or more and 1.2 μm or less, 1.2 μm or more and 1.4 μm or less, 1.4 μm or more and 1.6 μm or less, 1.6 μm or more and 1.8 μm or less, and 1.8 μm or more and 2 μm or less.

[0159] The n-type impurity concentration in the second epitaxial layer 72 is higher than that in the first epitaxial layer 71. １６ cm －３ The above 1 x 10 １８ cm －３ The following n-type impurity concentrations may be present as peak values. The n-type impurity concentration of the second epitaxial layer 72 may be approximately constant in the thickness direction. Of course, the n-type impurity concentration of the second epitaxial layer 72 may have a concentration gradient that gradually increases and / or decreases in the thickness direction (crystal growth direction) of the chip 2.

[0160] The concentration ratio of the peak value of the n-type impurity concentration in the second epitaxial layer 72 to the peak value of the n-type impurity concentration in the first epitaxial layer 71 may be greater than 1 and 10 or less. This concentration ratio may have a value that falls within at least one of the following ranges: greater than 1 and 2 or less, 2 to 3 or less, 3 to 4 or less, 4 to 5 or less, 5 to 6 or less, 6 to 7 or less, 7 to 8 or less, 8 to 9 or less, and 9 to 10 or less.

[0161] Referring to Figure 10, in this configuration, each of the multiple field regions 43 includes a p-type first field region 62. The first field region 62 is embedded in the surface layer of the second semiconductor region 7. In other words, in the outer peripheral region 9, multiple p-type first field regions 62 are formed on the surface layer of the second semiconductor region 7, spaced apart from the first main surface 3 towards the second main surface 4 (in the depth direction of the chip 2).

[0162] Multiple first field regions 62 are formed in the first epitaxial layer 71. Multiple first field regions 62 are not formed in the second epitaxial layer 72. One first field region 62 will be described below.

[0163] The first field region 62 has a p-type impurity concentration that is higher than the n-type impurity concentration of the second semiconductor region 7. The p-type impurity concentration of the first field region 62 may be approximately equal to the p-type impurity concentration of the terminal region 42 (Figure 9, etc.). The p-type impurity concentration of the first field region 62 may be higher than the p-type impurity concentration of the terminal region 42, or it may be lower than the p-type impurity concentration of the terminal region 42.

[0164] The p-type impurity concentration in the first field region 62 may be lower than the p-type impurity concentration in the gate contact region 27 (Figure 8, etc.). The p-type impurity concentration in the first field region 62 may be higher than the p-type impurity concentration in the gate well region 25 (Figure 8, etc.), or lower than the p-type impurity concentration in the gate well region 25. The p-type impurity concentration in the first field region 62 may be higher than the p-type impurity concentration in the body region 10 (Figure 8, etc.), or lower than the p-type impurity concentration in the body region 10.

[0165] In this configuration, the p-type impurity concentrations in the multiple first field regions 62 are approximately equal to each other. The p-type impurity concentrations in the multiple first field regions 62 are arbitrary and can take various values ​​depending on the electric field to be relaxed. The p-type impurity concentrations in the multiple first field regions 62 may also be different from each other.

[0166] The first field region 62 has a first upper end portion 62a on the side of the first main surface 3 and a first lower end portion 62b on the opposite side. The first field region 62 is in contact with the surface region 63, which will be described later.

[0167] The first upper end portion 62a is positioned at a distance from the first main surface 3 toward the second main surface 4 (in the depth direction of the chip 2). The first upper end portion 62a extends horizontally along the first main surface 3. The first upper end portion 62a is located at the boundary portion 73 between the first epitaxial layer 71 and the second epitaxial layer 72. The first upper end portion 62a forms a pn junction with the surface region 63.

[0168] The first upper end portion 62a is located on the first main surface 3 side with respect to the depth position of the bottom of the trench gate structure 15. The first upper end portion 62a is located on the first main surface 3 side with respect to the depth position of the bottom of the gate well region 25. The first upper end portion 62a is located on the first main surface 3 side with respect to the depth position of the bottom of the body region 10.

[0169] The first upper end portion 62a may be at the same depth as the bottom of the trench gate structure 15, or it may be located on the first main surface 3 side with respect to the depth of the bottom of the trench gate structure 15. The first upper end portion 62a may be at the same depth as the bottom of the gate well region 25, or it may be located on the first main surface 3 side with respect to the depth of the bottom of the gate well region 25. The first upper end portion 62a may be at the same depth as the bottom of the body region 10, or it may be located on the first main surface 3 side with respect to the depth of the bottom of the body region 10.

[0170] In this configuration, the depth position of the first upper end portion 62a is the same as the depth position of the boundary portion 73 between the first epitaxial layer 71 and the second epitaxial layer 72. In other words, the depth D1 of the first upper end portion 62a is equal to the thickness of the second epitaxial layer 72.

[0171] The depth D1 of the first upper end portion 62a may be, for example, greater than 0 μm and 2 μm or less. The depth D1 of the first upper end portion 62a may have a value that falls within at least one of the following ranges: greater than 0 μm and 0.2 μm or less, 0.2 μm or more and 0.4 μm or less, 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, 0.8 μm or more and 1 μm or less, 1 μm or more and 1.2 μm or less, 1.2 μm or more and 1.4 μm or less, 1.4 μm or more and 1.6 μm or less, 1.6 μm or more and 1.8 μm or less, and 1.8 μm or more and 2 μm or less.

[0172] The first lower end portion 62b extends horizontally along the first main surface 3 and forms a pn junction with the first epitaxial layer 71. The first lower end portion 62b is located on the bottom side of the second semiconductor region 7 with respect to the depth position of the bottom of the trench gate structure 15. The first lower end portion 62b is located on the bottom side of the second semiconductor region 7 with respect to the depth position of the bottom of the gate well region 25. The first lower end portion 62b is located on the bottom side of the second semiconductor region 7 with respect to the depth position of the bottom of the body region 10. The first lower end portion 62b is located on the bottom side of the second semiconductor region 7 with respect to the depth position of the boundary portion 73 between the second epitaxial layer 72 and the first epitaxial layer 71.

[0173] The depth D2 of the first lower end portion 62b may be, for example, greater than 0 μm and 4 μm or less. The depth D2 of the first lower end portion 62b may have a value that falls within at least one of the following ranges: greater than 0 μm and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, 1.75 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, and 3.5 μm or more and 4 μm or less.

[0174] The depth D2 of the first lower end portion 62b may be approximately equal to the depth of the terminal region 42. The depth D2 of the first lower end portion 62b may be deeper than the depth of the bottom of the terminal region 42, or it may be shallower than the depth of the bottom of the terminal region 42.

[0175] The first field region 62 includes a first side portion 62c connecting the first upper end portion 62a and the first lower end portion 62b. In this embodiment, the first side portion 62c is perpendicular to the first upper end portion 62a and the first lower end portion 62b. That is, the first side portion 62c extends along the vertical direction (has a vertical plane).

[0176] The first field region 62 has a first thickness T4. The first thickness T4 of the first field region 62 is less than (thinner than) the depth (thickness) of the end region 42. The first thickness T4 of the first field region 62 may be the same as the depth (thickness) of the end region 42, or it may be thicker than the depth (thickness) of the end region 42.

[0177] The first thickness T4 of the first field region 62 may be, for example, greater than 0 μm and 3 μm or less. The first thickness T4 of the first field region 62 may have a value that falls within at least one of the following ranges: greater than 0 μm and 0.2 μm or less, 0.2 μm or more and 0.4 μm or less, 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, 0.8 μm or more and 1 μm or less, 1 μm or more and 1.2 μm or less, 1.2 μm or more and 1.4 μm or less, 1.4 μm or more and 1.6 μm or less, 1.6 μm or more and 1.8 μm or less, 1.8 μm or more and 2 μm or less, 2 μm or more and 2.2 μm or less, 2.2 μm or more and 2.4 μm or less, 2.4 μm or more and 2.6 μm or less, 2.6 μm or more and 2.8 μm or less, and 2.8 μm or more and 3 μm or less.

[0178] The multiple first field regions 62 extend a depletion layer in the second semiconductor region 7 when a reverse bias voltage is applied. The depletion layer originating from the multiple first field regions 62 expands horizontally and in the thickness direction, integrating with the depletion layer originating from the terminal region 42. The multiple first field regions 62 extend the depletion layer originating from the terminal region 42 toward the periphery of the first main surface 3, mitigating the electric field at the peripheral portion (outer peripheral region 9) of the first main surface 3.

[0179] In this configuration, the depths D2 of the first lower ends 62b of the multiple first field regions 62 (hereinafter referred to as "depths D2 of the multiple first lower ends 62b") are approximately equal to each other. The depths D2 of the multiple first lower ends 62b are arbitrary and can take various values ​​depending on the electric field to be relaxed. The depths D2 of the multiple first lower ends 62b may be different from each other.

[0180] The depth D2 of the multiple first lower end portions 62b may increase sequentially toward the peripheral edge of the first main surface 3. The depth D2 of the multiple first lower end portions 62b may increase toward the peripheral edge of the first main surface 3 in units of two or more groups, each containing two or more first field regions 62.

[0181] The depth D2 of the multiple first lower end portions 62b may decrease sequentially toward the periphery of the first main surface 3. The depth D2 of the multiple first lower end portions 62b may decrease toward the periphery of the first main surface 3 in units of two or more groups, each containing two or more first field regions 62.

[0182] In this embodiment, the first thickness T4 of the multiple first field regions 62 is approximately equal to one another. The first thickness T4 of the multiple first field regions 62 is arbitrary and can take various values ​​depending on the electric field to be relaxed. The first thickness T4 of the multiple first field regions 62 may be different from one another.

[0183] The first thickness T4 of the multiple first field regions 62 may increase sequentially toward the peripheral edge of the first main surface 3. The first thickness T4 of the multiple first field regions 62 may increase toward the peripheral edge of the first main surface 3 in units of two or more groups, each containing two or more first field regions 62.

[0184] The first thickness T4 of the multiple first field regions 62 may decrease sequentially toward the peripheral edge of the first main surface 3. The first thickness T4 of the multiple first field regions 62 may decrease toward the peripheral edge of the first main surface 3 in units of two or more groups, each containing two or more first field regions 62.

[0185] Each of the multiple first field regions 62 (field regions 43) is formed in this configuration as a polygonal ring (a quadrilateral ring in this configuration) with four sides parallel to the periphery of the chip 2 in a plan view, and surrounds the terminal region 42. The multiple first field regions 62 are formed at intervals from each other and surround the active region 8 (Figures 3 and 4).

[0186] The first field region 62 (field region 43) is formed in an electrically floating state. A source potential may be applied to the first field region 62 (field region 43).

[0187] Referring to Figure 10, the semiconductor device 1A includes a plurality of n-type surface regions 63 formed between the first main surface 3 and a plurality of first field regions 62. The plurality of surface regions 63 are formed in a one-to-one correspondence with the plurality of first field regions 62. The plurality of surface regions 63 are formed in the surface layer of the second semiconductor region 7 in the outer peripheral region 9.

[0188] The surface region 63 is formed in the second epitaxial layer 72. The surface region 63 is not formed in the first epitaxial layer 71. The surface region 63 is the region that sandwiches the corresponding first field region 62 between itself and the first epitaxial layer 71 in the vertical direction Z (depth direction of the chip 2). An n-p-n sandwich structure is formed by one surface region 63, the first field region 62, and the first epitaxial layer 71. One surface region 63 will be described below.

[0189] The surface region 63 has a second upper end portion 63a on the first main surface 3 side and a second lower end portion 63b on the opposite side.

[0190] The second upper end portion 63a extends horizontally along the first main surface 3 and is exposed from the first main surface 3. The second upper end portion 63a is located on the first main surface 3 side with respect to the depth position of the bottom of the trench gate structure 15. The second upper end portion 63a is located on the first main surface 3 side with respect to the depth position of the bottom of the gate well region 25. The second upper end portion 63a is located on the first main surface 3 side with respect to the depth position of the bottom of the body region 10.

[0191] The second lower end portion 63b extends horizontally along the first main surface 3 and forms a pn joint with the first field region 62. The second lower end portion 63b is located at the boundary portion 73 between the first epitaxial layer 71 and the second epitaxial layer 72.

[0192] The second lower end portion 63b is in contact with the first upper end portion 62a of the first field region 62. Therefore, the depth position of the second lower end portion 63b coincides with the depth position of the first upper end portion 62a. That is, the depth of the second lower end portion 63b is depth D1.

[0193] In this configuration, the depth of the second lower end portion 63b is the same as the depth of the boundary portion 73 between the first epitaxial layer 71 and the second epitaxial layer 72. In other words, the depth of the second lower end portion 63b is equal to the thickness of the first epitaxial layer 71.

[0194] The second lower end portion 63b is located on the first main surface 3 side with respect to the depth position of the bottom of the trench gate structure 15. The second lower end portion 63b is located on the first main surface 3 side with respect to the depth position of the bottom of the gate well region 25. The second lower end portion 63b is located on the first main surface 3 side with respect to the depth position of the bottom of the body region 10.

[0195] The second lower end portion 63b may be at the same depth as the bottom of the trench gate structure 15, or it may be located on the first main surface 3 side with respect to the depth of the bottom of the trench gate structure 15. The second lower end portion 63b may be at the same depth as the bottom of the gate well region 25, or it may be located on the first main surface 3 side with respect to the depth of the bottom of the gate well region 25. The second lower end portion 63b may be at the same depth as the bottom of the body region 10, or it may be located on the first main surface 3 side with respect to the depth of the bottom of the body region 10.

[0196] The surface region 63 includes a second side portion 63c connecting the second upper end portion 63a and the second lower end portion 63b. In this embodiment, the second side portion 63c is perpendicular to the second upper end portion 63a and the second lower end portion 63b. That is, the second side portion 63c extends along the vertical direction (has a vertical plane).

[0197] The surface region 63 has a thickness T3. The thickness T3 of the surface region 63 is less than (thinner than) the depth (thickness of) the end region 42. The thickness T3 of the surface region 63 may be the same as the depth (thickness of) the end region 42, or it may be thicker than the depth (thickness of the end region 42).

[0198] In this configuration, the thickness T3 of the surface region 63 is less than (thinner than) the depth of the terminal region 42 (thickness of the terminal region 42). The thickness T3 of the surface region 63 may be the same as the depth of the terminal region 42 (thickness of the terminal region 42), or it may be thicker than the depth of the surface region 63 (thickness of the terminal region 42).

[0199] The thickness T3 of the surface region 63 may be, for example, greater than 0 μm and 2 μm or less. The thickness T3 of the first field region 62 may have a value that falls within at least one of the following ranges: greater than 0 μm and 0.2 μm or less, 0.2 μm or more and 0.4 μm or less, 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, 0.8 μm or more and 1 μm or less, 1 μm or more and 1.2 μm or less, 1.2 μm or more and 1.4 μm or less, 1.4 μm or more and 1.6 μm or less, 1.6 μm or more and 1.8 μm or less, and 1.8 μm or more and 2 μm or less.

[0200] Each of the multiple surface regions 63 is formed in this configuration as a polygonal ring (a quadrilateral ring in this configuration) with four sides parallel to the periphery of the chip 2 in a plan view, and surrounds the terminal region 42. The multiple surface regions 63 are formed with intervals between them and surround the active region 8 (Figures 3 and 4).

[0201] The surface region 63 is n-type, consisting of an n-type epitaxial layer (second epitaxial layer 72). The peak value of the n-type impurity concentration in the surface region 63 is higher than the peak value of the n-type impurity concentration in the first epitaxial layer 71.

[0202] The surface region 63 is a region containing p-type impurities. Throughout the entire surface region 63, the concentration of n-type impurities in the surface region 63 is higher than the concentration of p-type impurities in the surface region 63.

[0203] The following describes in detail the concentration gradients of n-type and p-type impurities in the impurity region within chip 2.

[0204] The numerical values ​​for impurity concentrations, etc., shown below are examples to explain the basic configuration of the first field region 62 (field region 43), the surface region 63, and the first epitaxial layer 71 based on the concentration gradient. These values ​​are not intended to uniquely limit the configuration of the first field region 62 (field region 43), the surface region 63, and the first epitaxial layer 71. Impurity concentrations, thicknesses, etc., are adjusted to various values ​​depending on the injection conditions (dose amount, injection temperature, injection energy, etc.) for trivalent or pentavalent elements. Also, the term "concentration gradient" may be completely replaced with the term "concentration profile."

[0205] Figure 12 (Example of First Embodiment) is a graph showing an example of the concentration gradient 123 of p-type impurities in the region along the XII-XII line shown in Figure 10. Figure 13 is a graph showing an example of the concentration gradient 120 of n-type impurities in the region along the XII-XII line shown in Figure 10. From the viewpoint of comparing the concentration of p-type impurities in tip 2 with the concentration of n-type impurities in tip 2, in Figure 12, the concentration gradient 120 of n-type impurities is shown as a dashed line in addition to the concentration gradient 123 of p-type impurities.

[0206] The concentration gradient 123 shown in Figure 12 is the concentration gradient of p-type impurities when crossing the surface region 63 and the first field region 62 in the depth direction from the first main surface 3 to the chip 2. In Figure 13, the vertical axis shows the n-type impurity concentrations in the surface region 63, the first field region 62, and the first epitaxial layer 71, and the horizontal axis shows the depth in the thickness direction of the second semiconductor region 7 with the first main surface 3 as the reference (zero point).

[0207] Figure 12 shows the concentration gradient 123 of p-type impurities when a predetermined trivalent element (aluminum in this case) is introduced into the second semiconductor region 7 in a random direction with a predetermined injection energy. The random direction is a direction that is not parallel (or nearly parallel) to the axial channel of the second semiconductor region 7 (for example, the vertical direction Z).

[0208] The concentration gradient 123 of the p-type impurity includes an increasing portion 65, a peak portion 66 (peak value P1), and a decreasing portion 67.

[0209] The gradually increasing portion 65 is the portion that forms the boundary portion 64 between the first field region 62 and the surface region 63 (the first upper end portion 62a of the first field region 62 and the second lower end portion 63b of the surface region 63), and is the portion in which the p-type impurity concentration gradually increases at a relatively steep rate from the second upper end portion 63a of the surface region 63 toward the first lower end portion 62b of the first field region 62 up to the peak portion 66.

[0210] The peak portion 66 is the part that has the peak value P1 (maximum value) of the p-type impurity concentration. The peak portion 66 is also a convex main concentration transition portion that includes a series of concentration changes (inflection points) where the p-type impurity concentration changes from increasing (increasing trend) to decreasing (decreasing trend).

[0211] In the example shown in Figure 12, the peak portion 66 is set at a depth position in the first field region 62 (first epitaxial layer 71). In other words, the concentration gradient 123 of p-type impurities has a peak value P1 in the first field region 62. In the example shown in Figure 12, for example, the peak value P1 (maximum value) of the p-type impurity concentration is approximately 1 × 10⁻¹⁶. １７ cm －３ That's fine.

[0212] The tapering portion 67 is the portion that forms the first lower end portion 62b of the first field region 62. The p-type impurity concentration in the tapering portion 67 is 1 × 10⁻⁶. １５ cm －３ It is gradually decreasing to that point.

[0213] The concentration gradient 120 shown in Figure 13 is the concentration gradient 120 of n-type impurities when traversing the surface region 63 and the first field region 62 in the depth direction from the first main surface 3 to the chip 2. In Figure 13, the vertical axis shows the n-type impurity concentrations of the surface region 63, the first field region 62, and the first epitaxial layer 71, and the horizontal axis shows the depth in the thickness direction of the second semiconductor region 7 with the first main surface 3 as the reference (zero point).

[0214] Referring to Figure 13, in the depth direction of the second semiconductor region 7, the first field region 62 (field region 43) is a p-type impurity region, but it has a background concentration gradient of n-type impurities. More specifically, the second semiconductor region 7 is replaced by various impurity regions in the target region by ion implantation after epitaxial growth, but the n-type impurity ions added during the epitaxial growth of the second semiconductor region 7 remain at the concentration at the time of growth. As a result, the second semiconductor region 7 provides an n-type background concentration within a range that does not impair the characteristics (electrical behavior) of the various impurity regions. On the other hand, even if n-type or p-type impurity ions are implanted into the second semiconductor region 7, if the amount is small, the characteristics of the second semiconductor region 7 are maintained in that region, and the second semiconductor region 7 remains. As described above, the second semiconductor region 7 has a stacked structure of the first epitaxial layer 71 and the second epitaxial layer 72 in the outer peripheral region 9.

[0215] The n-type impurity concentration gradient 120 in tip 2 in Figure 13 includes a high-concentration section 121 and a low-concentration section 122. The second epitaxial layer 72 provides a higher n-type background concentration than the first epitaxial layer 71. The n-type impurity concentration gradient 120 includes a high-concentration section 121 in the second epitaxial layer 72 and a low-concentration section 122 in the first epitaxial layer 71. The n-type impurity concentration gradient 120 in tip 2 in Figure 13 is shown by a dashed line in Figure 12.

[0216] The n-type impurity concentration in the high-concentration section 121 is relatively higher than the n-type impurity concentration in the low-concentration section 122. For example, the n-type impurity concentration in the high-concentration section 121 is 5 × 10⁻⁶. １６ cm －３ The above 1 x 10 １８ cm －３ The following is true: The n-type impurity concentration in the low-concentration section 122 is 1 × 10⁻⁶. １６ cm －３ The above 1 x 10 １７ cm －３ The following may also apply: In the example in Figure 13 (and Figure 12), the n-type impurity concentration in the high-concentration section 121 is 1 × 10⁻⁶. １７ cm －３Therefore, the n-type impurity concentration in the low-concentration section 122 is 1 × 10⁻⁶. １６ cm －３ That is the case.

[0217] In the n-type impurity concentration gradient 120, the n-type impurity concentrations in the high-concentration section 121 and the low-concentration section 122 may be approximately constant in the thickness direction (depth direction) of the chip 2. Of course, in the n-type impurity concentration gradient 120, the n-type impurity concentrations in the high-concentration section 121 and the low-concentration section 122 may gradually increase and / or decrease in the thickness direction (crystal growth direction) of the chip 2.

[0218] Referring to Figure 12, the concentration gradient 123 of p-type impurities includes a peak 66 in the low-concentration section 122. The peak 66 corresponds to the n-type impurity concentration (for example, 1 × 10⁻⁶) in the low-concentration section 122. １６ cm －３ It has a higher peak value P1 than ).

[0219] Therefore, in the low-concentration section 122, a region is formed where the p-type impurity concentration exceeds the n-type impurity concentration. This region exhibits the characteristics (electrical behavior) of the p-type impurity region. This region is the first field region 62, which is the p-type impurity region.

[0220] On the other hand, throughout the entire depth region of the high-concentration section 121, the concentration gradient 123 of p-type impurities is equal to the n-type impurity concentration in the high-concentration section 121 (for example, 1 × 10⁻⁶). １７ cm －３ It is lower than ). Therefore, in the high-concentration section 121, a region is formed throughout the depth direction where the p-type impurity concentration is lower than the n-type impurity concentration. This region exhibits the characteristics (electrical behavior) of the n-type impurity region. This region is the surface region 63, which is the n-type impurity region.

[0221] The high-concentration section 121 of the n-type impurity concentration gradient 120 corresponds to the gradually increasing section 65 of the p-type impurity concentration gradient 123. Since a surface region 63 is formed in the portion corresponding to the gradually increasing section 65, the surface region 63 includes a region having a p-type impurity concentration gradient that increases as it moves from the first main surface 3 toward the first field region 62.

[0222] Referring to Figures 5 to 8, the semiconductor device 1A includes a plurality of source openings 49 formed in the interlayer film 47 in the active region 8. In Figure 9, the source openings 49 are omitted for clarity. The plurality of source openings 49 are formed in the portion of the interlayer film 47 that covers the active region 8. In this embodiment, the plurality of source openings 49 are each formed in regions between a plurality of adjacent trench gate structures 15, exposing a plurality of source regions 11 and a plurality of gate contact regions 27, respectively.

[0223] The source electrode 51 enters from above the interlayer film 47 into a plurality of source openings 49 and is electrically connected to a plurality of source regions 11 and a plurality of gate contact regions 27 within the plurality of source openings 49.

[0224] Referring to Figure 9, the semiconductor device 1A includes at least one (one in this embodiment) outer opening 50 formed in the interlayer film 47 in the outer peripheral region 9. The outer opening 50 penetrates the main surface insulating film 45 and the interlayer film 47, exposing the outer contact region 41. In a plan view, the outer opening 50 extends in a strip shape along the outer contact region 41.

[0225] In this configuration, the outer opening 50 is formed in a polygonal ring shape (specifically, a quadrilateral ring shape) that surrounds the inner portion (active region 8) of the first main surface 3 along the outer contact region 41 in a plan view. The outer opening 50 may have an opening end that is curved in an arc shape.

[0226] Figure 14 is a schematic diagram showing a wafer 150 used in the manufacture of semiconductor device 1A. Referring to Figure 14, the wafer 150 is the substrate for the chip 2 and contains a SiC single crystal. The wafer 150 is formed in the shape of a flat disc. Of course, the wafer 150 may also be formed in the shape of a flat rectangular parallelepiped. The wafer 150 has a first wafer main surface 151 on one side, a second wafer main surface 152 on the other side, and a wafer side surface 153 connecting the first wafer main surface 151 and the second wafer main surface 152.

[0227] The first wafer main surface 151 corresponds to the first main surface 3 of the chip 2 (Figure 2, etc.), and the second wafer main surface 152 corresponds to the second main surface 4 of the chip 2 (Figure 2, etc.). The first wafer main surface 151 and the second wafer main surface 152 are formed by the c-plane of a SiC single crystal. The first wafer main surface 151 is formed by the silicon plane of the SiC single crystal, and the second wafer main surface 152 is formed by the carbon plane of the SiC single crystal. The wafer 150 (first wafer main surface 151 and second wafer main surface 152) has the aforementioned off-direction and off-angle.

[0228] The wafer 150 has markings 154 on the wafer side surface 153 that indicate the crystal orientation of the SiC single crystal. The markings 154 may include either an orientation flat or an orientation notch, or both. An orientation flat consists of a notch that is cut out in a straight line in a plan view. An orientation notch consists of a notch that is cut out in a concave shape (for example, tapered shape) toward the center of the first wafer main surface 151 in a plan view.

[0229] The marker 154 may include either or both a first orientation flat extending in the m-axis direction and a second orientation flat extending in the a-axis direction. The marker 154 may also include either or both an orientation notch recessed in the m-axis direction and an orientation notch recessed in the a-axis direction.

[0230] The wafer 150 includes a second semiconductor region 7 (Figure 15C, described later) in the region (surface layer) on the first wafer main surface 151 side. The second semiconductor region 7 is formed in layers extending along the first wafer main surface 151. In this configuration, the second semiconductor region 7 consists of an epitaxial layer (specifically, a SiC epitaxial layer). The second semiconductor region 7 has a laminated structure in which the second epitaxial layer 72 is formed on the first epitaxial layer 71 (Figure 15C, described later).

[0231] The wafer 150 includes a first semiconductor region 6 (as shown in Figure 15A below) in the region (surface layer) on the second wafer main surface 152 side. The first semiconductor region 6 is formed in layers extending along the second main surface 4 and is electrically connected to the first semiconductor region 6. In this embodiment, the first semiconductor region 6 consists of the wafer body. In other words, in this embodiment, the wafer 150 consists of an epitaxial wafer (so-called epiwafer) having a laminated structure including the wafer body and an epitaxial layer.

[0232] For example, the wafer 150 has multiple device regions 155 and multiple cutting lines 156 marked by alignment marks or the like. Each device region 155 corresponds to a semiconductor device 1A. The multiple device regions 155 are each set in a rectangular shape when viewed from above.

[0233] In this configuration, the multiple device regions 155 are arranged in a matrix along the first direction X and the second direction Y in a plan view. The multiple device regions 155 are each spaced inward from the periphery of the first wafer main surface 151 in a plan view. The multiple cutting lines 156 are arranged in a grid pattern extending along the first direction X and the second direction Y to demarcate the multiple device regions 155.

[0234] Figures 15A to 15G are cross-sectional views showing the manufacturing method of the semiconductor device 1A. Figures 15A to 15G show a cross-section of a part of the outer peripheral region 9.

[0235] As shown in Figure 15A, a semiconductor substrate (SiC substrate) is prepared as the first n-type semiconductor region 6. Then, as shown in Figure 15B, a first epitaxial layer 71 is stacked on the first semiconductor region 6 by epitaxial growth, and then, as shown in Figure 15C, a second epitaxial layer 72 is formed on the first epitaxial layer 71 by epitaxial growth. This forms a second semiconductor region 7 including a stacked structure of the first epitaxial layer 71 and the second epitaxial layer 72 formed on the first epitaxial layer 71. The first wafer main surface 151 is formed on the second epitaxial layer 72, thereby forming the aforementioned wafer 150.

[0236] The formation of the first field region 62 (field region 43) will be described below. The formation of the first field region 62 may be carried out in relation to (simultaneously with or before / after) the formation of the terminal region 42, which is a p-type region. The formation of the first field region 62 may be carried out in relation to (simultaneously with or before / after) the formation of the gatewell region 25, which is a p-type region.

[0237] As shown in Figure 15D, a first mask 160 having a predetermined opening 161 is placed on the first wafer main surface 151 of the wafer 150. The first mask 160 may be an inorganic mask (for example, a silicon oxide film) or an organic mask (mask). The opening 161 exposes the area that forms the first field region 62 (field region 43) and covers the other areas.

[0238] Next, p-type impurities are implanted from the main surface 151 of the first wafer toward the first epitaxial layer 71 by ion implantation via the first mask 160 (first ion implantation step). This introduces p-type impurities into the second semiconductor region 7 (Figure 15D).

[0239] The ion implantation method may be a random ion implantation method. In the random ion implantation step, p-type impurities may be implanted in a single step at the target depth position of the second semiconductor region 7. The p-type impurity implantation step may include a step of implanting p-type impurities multiple times at the target depth position of the second semiconductor region 7 in the single-step implantation step.

[0240] Furthermore, the ion implantation method may be channeling ion implantation. Moreover, the ion implantation method may be both channeling ion implantation and random ion implantation.

[0241] In the ion implantation method, at least one of the implantation energy and dose (impurity concentration) of the implanted p-type impurity is adjusted so that in the low-concentration section 122 (Figure 12), the concentration gradient 123 of the p-type impurity includes a peak portion 66 having a peak value P1 (Figure 12) that exceeds the n-type impurity concentration, and in the high-concentration section 121 (Figure 12), the p-type impurity concentration is lower than the n-type impurity concentration throughout the depth direction.

[0242] By implanting p-type impurities using the ion implantation method, a region where the p-type impurity concentration exceeds the n-type impurity concentration is formed in the low-concentration section 122, and this region becomes the first field region 62. As a result, multiple p-type first field regions 62 (field regions 43) are formed in the first epitaxial layer 71.

[0243] Furthermore, by implanting p-type impurities using the ion implantation method, n-type impurity regions containing p-type impurities are formed in the high-concentration section 121, and these regions become surface regions 63. As a result, multiple n-type surface regions 63 are formed in the second epitaxial layer 72.

[0244] Subsequently, in the active region 8 (Figure 2), a plurality of trench gate structures 15 (Figure 9) are formed in the second semiconductor region.

[0245] Next, referring to Figure 15E, a main surface insulating film 45 is formed to cover the main surface 151 of the first wafer.

[0246] Next, referring to Figure 15F, an interlayer film 47 is formed on the main surface 151 of the first wafer. As a result, the interlayer film 47 is laminated on the main surface insulating film 45. In addition, multiple trench gate structures (Figure 9) are covered by the interlayer film 47. The interlayer film 47 may be formed by the CVD method.

[0247] Next, the source electrode 51 (see Figure 1), source wiring 56 (see Figure 1), gate electrode 57 (see Figure 1), and gate wiring 58 (see Figure 1) are formed on the interlayer film 47. The source electrode 51, source wiring 56, gate electrode 57, and gate wiring 58 may be formed by sputtering or vapor deposition.

[0248] Next, referring to Figure 15G, a drain electrode 59 is formed on the second wafer main surface 152. The drain electrode 59 may be formed by sputtering or vapor deposition. Then, the wafer 150 is cut along the planned cutting line 156, and a plurality of semiconductor devices 1A are cut out. The semiconductor device 1A is manufactured through the process including the above.

[0249] Figure 16A is a graph showing a second example of the concentration gradient 124 of p-type impurities in tip 2, and corresponds to Figure 12.

[0250] The second embodiment shown in Figure 16A differs from the first embodiment shown in Figure 12 in that the tip 2 has a p-type impurity concentration gradient 124 instead of a p-type impurity concentration gradient 123. The p-type impurity concentration gradient 124 has a concentration gradient unique to the impurity region formed by the random injection method. In Figure 16A, as in Figure 12, the n-type impurity concentration gradient 120 is shown together with the p-type impurity concentration gradient 124 of the tip 2 using a dashed line.

[0251] The concentration gradient 124 of p-type impurities includes a rapid increase section 68, a peak section 69 (peak value P1), and a sharp decrease section 70. The rapid increase section 68 is the part where the impurity concentration rapidly increases from the first main surface 3 toward the peak section 69. The sharp decrease section 70 is the part where the impurity concentration rapidly decreases from the peak section 69 toward the second main surface 4.

[0252] The concentration gradient 124 of p-type impurities includes a peak 69 in the low-concentration section 122. The peak 69 corresponds to the n-type impurity concentration (for example, 1 × 10⁻⁶) in the low-concentration section 122. １６ cm －３ It has a higher peak value P1 than ).

[0253] Therefore, in the low-concentration section 122, a region is formed where the p-type impurity concentration exceeds the n-type impurity concentration. This region exhibits the characteristics (electrical behavior) of the p-type impurity region. This region is the first field region 62, which is the p-type impurity region.

[0254] On the other hand, throughout the entire depth region of the high-concentration section 121, the concentration gradient 124 of p-type impurities is equal to the n-type impurity concentration in the high-concentration section 121 (for example, 1 × 10⁻⁶). １７ cm －３ It is lower than ). Therefore, in the high-concentration section 121, a region is formed throughout the depth direction where the p-type impurity concentration is lower than the n-type impurity concentration. This region exhibits the characteristics (electrical behavior) of the n-type impurity region. This region is the surface region 63, which is the n-type impurity region.

[0255] The high-concentration section 121 of the n-type impurity concentration gradient 120 corresponds to the sharp increase section 68 of the p-type impurity concentration gradient 124. Since a surface region 63 is formed in the portion corresponding to the sharp increase section 68, the surface region 63 has a p-type impurity concentration gradient that increases as it moves from the first main surface 3 toward the first field region 62.

[0256] Figure 16B is a graph showing a third example of the concentration gradient 125 of p-type impurities in tip 2, and corresponds to Figure 12.

[0257] The third embodiment shown in Figure 16B differs from the first embodiment shown in Figure 12 in that the tip 2 has a p-type impurity concentration gradient 125 instead of a p-type impurity concentration gradient 123. The p-type impurity concentration gradient 125 has a concentration gradient unique to the impurity region formed by the channeling injection method. In Figure 16B, as in Figure 12, the n-type impurity concentration gradient 120 is shown together with the p-type impurity concentration gradient 125 of the tip 2 using a dashed line.

[0258] The p-type impurity concentration gradient 125 has a concentration gradient that includes a gradually increasing portion 81, a peak portion 82, a slow-growing portion 83, and a gradually decreasing portion 84 from the first main surface 3 to the second main surface 4. The gradually increasing portion 81 is the part in which the p-type impurity concentration gradually increases at a relatively steep rate from the first main surface 3 towards the second main surface 4 to the peak portion 82.

[0259] The peak portion 82 is the portion having the peak value P1 (maximum value) of the p-type impurity concentration. The peak portion 82 is also a convex main concentration transition portion that includes a series of concentration changes (inflection points) where the p-type impurity concentration changes from increasing (increasing trend) to decreasing (decreasing trend). In the third embodiment example shown in Figure 16B, the peak portion 82 of the concentration gradient 125 of p-type impurities corresponds to the high-concentration section 121 of the concentration gradient 120 of n-type impurities.

[0260] The slow-reducing portion 83 is formed in the region closer to the second main surface 4 than the peak portion 82, and is a portion where the impurity concentration gradually decreases at a relatively slow rate. In other words, the slow-reducing portion 83 is a portion that maintains a constant p-type impurity concentration within a certain depth range, and forms the main body of the first field region 62. The p-type impurity concentration in the slow-reducing portion 83 gradually decreases within a concentration range lower than the p-type impurity concentration in the peak portion 82.

[0261] The slow-down portion 83 is defined by a portion having a concentration reduction rate of 50% or less in a thickness range of at least 1 μm. In this example, the slow-down portion 83 has a thickness of 0.7 μm to 1.5 μm and has a concentration reduction rate of 50% or less in that thickness range. In this example, the p-type impurity concentration of the slow-down portion 83 is 4.5 × 10⁻⁶. １６ cm －３ The above 9 x 10 １６ cm －３ The concentrations fall within the following range.

[0262] The gradually decreasing portion 84 is the portion that forms the first lower end portion 62b of the first field region 62. The gradually decreasing portion 84 has a higher concentration reduction rate than the concentration reduction rate in the slow portion 83, and is the portion where the p-type impurity concentration gradually decreases from the slow portion 83 toward the second main surface 4. The concentration reduction rate per unit thickness in the gradually decreasing portion 84 is greater than the concentration reduction rate per unit thickness in the slow portion 83. The p-type impurity concentration in the gradually decreasing portion 84 is 1 × 10⁻⁶ from the slow portion 83. １５ cm －３ It is gradually decreasing to that point.

[0263] The concentration gradient 125 of p-type impurities includes a peak 82 in the high-concentration section 121. The peak 82 corresponds to the n-type impurity concentration (for example, 1 × 10⁻⁶) in the high-concentration section 121. １７ cm －３ It has a lower peak value P1 than ).

[0264] On the other hand, in the slow region 83 included in the p-type impurity concentration gradient 125, the p-type impurity concentration exceeds the n-type impurity concentration in the low-concentration section 122. Therefore, a region is formed in the low-concentration section 122 where the p-type impurity concentration exceeds the n-type impurity concentration. This region exhibits the characteristics (electrical behavior) of the p-type impurity region. This region is the first field region 62, which is the p-type impurity region.

[0265] On the other hand, throughout the entire depth region of the high-concentration section 121, the concentration gradient 125 of p-type impurities is equal to the n-type impurity concentration in the high-concentration section 121 (for example, 1 × 10⁻⁶). １７ cm －３It is lower than ). Therefore, in the high-concentration section 121, a region is formed throughout the depth direction where the p-type impurity concentration is lower than the n-type impurity concentration. This region exhibits the characteristics (electrical behavior) of the n-type impurity region. This region is the surface region 63, which is the n-type impurity region.

[0266] The high-concentration section 121 of the n-type impurity concentration gradient 120 corresponds to the gradually increasing section 81 of the p-type impurity concentration gradient 125. Since a surface region 63 is formed in the portion corresponding to the gradually increasing section 81, a part of the surface region 63 (the surface layer) has a p-type impurity concentration gradient that increases as it moves from the first main surface 3 toward the first field region 62.

[0267] Figure 16C is a graph showing a fourth example of the concentration gradient 125 of p-type impurities in tip 2, and corresponds to Figure 12.

[0268] The fourth embodiment shown in Figure 16C differs from the third embodiment shown in Figure 16B in that the peak portion 82 of the concentration gradient 125 of p-type impurities corresponds to the low-concentration section 122 of the concentration gradient 120 of n-type impurities. In Figure 16C, as in Figure 12, the concentration gradient 120 of n-type impurities is shown together with the concentration gradient 125 of p-type impurities in the tip 2 using a dashed line.

[0269] In the fourth embodiment, the concentration gradient 125 of p-type impurities includes a peak 82 in the low-concentration section 122. The peak 82 corresponds to the n-type impurity concentration (e.g., 1 × 10⁻⁶) in the low-concentration section 122. １６ cm －３ It has a higher peak value P1 than ).

[0270] Therefore, in the low-concentration section 122, a region is formed where the p-type impurity concentration exceeds the n-type impurity concentration. This region exhibits the characteristics (electrical behavior) of the p-type impurity region. This region is the first field region 62, which is the p-type impurity region.

[0271] On the other hand, throughout the entire depth region of the high-concentration section 121, the concentration gradient 125 of p-type impurities is equal to the n-type impurity concentration in the high-concentration section 121 (for example, 1 × 10⁻⁶). １７ cm －３It is lower than ). Therefore, in the high-concentration section 121, a region is formed throughout the depth direction where the p-type impurity concentration is lower than the n-type impurity concentration. This region exhibits the characteristics (electrical behavior) of the n-type impurity region. This region is the surface region 63, which is the n-type impurity region.

[0272] The high-concentration section 121 of the n-type impurity concentration gradient 120 corresponds to the gradually increasing section 81 of the p-type impurity concentration gradient 125. Since a surface region 63 is formed in the portion corresponding to the gradually increasing section 81, the surface region 63 has a p-type impurity concentration gradient that increases as it moves from the first main surface 3 toward the first field region 62.

[0273] Figure 17 is a cross-sectional view showing the field region 43 and surface region 63 according to the first modified example.

[0274] The first field region 62 (field region 43) according to the first modified example is formed in a mesa shape in cross-sectional view, having a first side portion 62c that slopes so as to narrow in width (width W1, width W3) from the first upper end portion 62a to the first lower end portion 62b (W1 < W3). In this embodiment, the first side portion 62c slopes from the first upper end portion 62a to the first lower end portion 62b.

[0275] The surface region 63 in the first modified example is formed in a mesa shape in cross-sectional view, having a second side portion 63c that slopes so as to narrow in width (width W2, width W3) from the second upper end portion 63a to the second lower end portion 63b (W3 < W2). In this embodiment, the second side portion 63c slopes from the second upper end portion 63a to the second lower end portion 63b.

[0276] Based on the above, the first embodiment provides the following effects and advantages.

[0277] In the outer peripheral region 9, a p-type first field region 62 and an n-type surface region 63 are formed on the surface layer of the second semiconductor region 7. The surface region 63 sandwiches the corresponding first field region 62 between itself and the first epitaxial layer 71 in the vertical direction Z (depth direction of the chip 2). The surface region 63 contains p-type impurities. By forming the first field region 62 and the surface region 63, an n-p-n sandwich structure can be realized by the surface region 63, the first field region 62, and the first epitaxial layer 71.

[0278] Conventionally, a method has been commonly used to form an n-p-n sandwich structure in the surface layer of the second semiconductor region 7 in the outer peripheral region 9 by introducing p-type impurities and then regrowing the epitaxial layer.

[0279] However, successfully regrowing the epitaxial layer may incur significant costs and require extensive processes. In particular, if chip 2 is a SiC chip, the presence of the SiC chip's off-angle (off-angle α (Figure 4)) may exacerbate such problems (resulting in significant costs, etc.).

[0280] A wafer 150 having a stacked structure of a first epitaxial layer 71 and a high-concentration second epitaxial layer 72 is prepared. Then, p-type ions (impurities) are injected from the main surface 151 of the first wafer toward the first epitaxial layer 71 to form a p-type first field region 62 in the first epitaxial layer 71. As a result, an n-p-n sandwich structure can be formed on the surface of the second semiconductor region 7 in the outer peripheral region 9 without regrowing the epitaxial layer.

[0281] In other words, a configuration in which the first field region 62 is formed in the outer peripheral region 9 with a gap between it and the first main surface 3 in the depth direction of the chip 2 can be easily realized.

[0282] Furthermore, in this configuration, since the second epitaxial layer 72 is a high-concentration n-type region, even if p-type ions are implanted into the second epitaxial layer 72 from the first main surface 3 side, it is relatively difficult for a p-type region to form in the second epitaxial layer 72. As a result, the depth position of the first upper end portion 62a of the first field region 62 coincides with the boundary portion 73 between the first epitaxial layer 71 and the second epitaxial layer 72. This makes it possible to precisely control the depth position of the first upper end portion 62a of the first field region 62 by controlling the thickness of the first epitaxial layer 71.

[0283] Furthermore, since p-type regions are relatively unlikely to form in the highly concentrated n-type second epitaxial layer 72, the formation of p-type regions in unintended areas can be suppressed or prevented.

[0284] Figure 18 is a cross-sectional view showing the cross-sectional structure of the outer peripheral region 9 according to the second embodiment of this disclosure, and corresponds to Figure 10. In the semiconductor device 1B according to the second embodiment of this disclosure, the same reference numerals are used for components that are common to the semiconductor device 1A according to the first embodiment, and their descriptions are omitted.

[0285] The difference between semiconductor device 1B and semiconductor device 1A is that in semiconductor device 1B, each of the multiple field regions 43 includes a p-type first field region 62 and a p-type second field region 87.

[0286] Multiple second field regions 87 are formed in the second epitaxial layer 72. These multiple second field regions 87 are not formed in the first epitaxial layer 71. One second field region 87 will be described below.

[0287] The second field region 87 has a higher p-type impurity concentration than the first field region 62. In this configuration, the p-type impurity concentrations of the multiple second field regions 87 are approximately equal to each other. The p-type impurity concentrations of the multiple second field regions 87 are arbitrary and can take various values ​​depending on the electric field to be relaxed. The p-type impurity concentrations of the multiple second field regions 87 may be different from each other.

[0288] The second field region 87 has a third upper end portion 87a on the side of the first main surface 3 and a third lower end portion 87b on the opposite side. The second field region 87 is sandwiched in the vertical direction Z by the first surface region 91 and the second surface region 92. The second field region 87 is in contact with both the first surface region 91 and the second surface region 92.

[0289] The third upper end portion 87a is located at a depth position spaced apart from the first main surface 3 toward the second main surface 4. The third upper end portion 87a extends horizontally along the first main surface 3. The third upper end portion 87a forms a pn joint with the first surface region 91.

[0290] The depth D3 of the third upper end portion 87a may be, for example, greater than 0 μm and 0.7 μm or less. The depth D3 of the third upper end portion 87a may have a value that falls within at least one of the following ranges: greater than 0 μm and 0.1 μm or less, 0.1 μm or more and 0.2 μm or less, 0.2 μm or more and 0.3 μm or less, 0.3 μm or more and 0.4 μm or less, 0.4 μm or more and 0.5 μm or less, 0.5 μm or more and 0.6 μm or less, and 0.6 μm or more and 0.7 μm or less.

[0291] The third lower end portion 87b is located at a depth position spaced apart from the depth position of the boundary portion 73 between the first epitaxial layer 71 and the second epitaxial layer 72 toward the first main surface 3. The third lower end portion 87b extends horizontally along the first main surface 3. The third lower end portion 87b forms a pn junction with the second surface region 92.

[0292] The depth D4 of the third lower end portion 87b may be, for example, greater than 0 μm and 1.4 μm or less. The depth D4 of the third lower end portion 87b may have a value that falls within at least one of the following ranges: greater than 0 μm and 0.2 μm or less, 0.2 μm or more and 0.4 μm or less, 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, 0.8 μm or more and 1 μm or less, 1 μm or more and 1.2 μm or less, and 1.2 μm or more and 1.4 μm or less.

[0293] The second field region 87 includes a third side portion 87c connecting the third upper end portion 87a and the third lower end portion 87b. In this embodiment, the third side portion 87c is perpendicular to the third upper end portion 87a and the third lower end portion 87b. That is, the third side portion 87c extends along the vertical direction (has a vertical plane).

[0294] The second field region 87 has a second thickness T5. The second thickness T5 of the second field region 87 may be, for example, greater than 0 μm and 1 μm or less. The second thickness T5 of the second field region 87 may have a value that falls within at least one of the following ranges: greater than 0 μm and 0.1 μm or less, 0.1 μm or more and 0.2 μm or less, 0.2 μm or more and 0.3 μm or less, 0.3 μm or more and 0.4 μm or less, 0.4 μm or more and 0.5 μm or less, 0.5 μm or more and 0.6 μm or less, 0.6 μm or more and 0.7 μm or less, 0.7 μm or more and 0.8 μm or less, 0.8 μm or more and 0.9 μm or less, and 0.9 μm or more and 1 μm or less.

[0295] The multiple second field regions 87 expand a depletion layer in the second semiconductor region 7 when a reverse bias voltage is applied. The depletion layer originating from the multiple second field regions 87 expands horizontally and in the thickness direction, integrating with the depletion layer originating from the termination region 42 and the depletion layer originating from the first field region 62. Similar to the first field region 62, the multiple second field regions 87 extend the depletion layer originating from the termination region 42 toward the periphery of the first main surface 3, thereby mitigating the electric field at the periphery (outer peripheral region 9) of the first main surface 3.

[0296] The depth D4 of the multiple third lower end portions 87b may increase sequentially toward the peripheral edge of the first main surface 3. The depth D4 of the multiple third lower end portions 87b may increase toward the peripheral edge of the first main surface 3 in units of two or more groups, each containing two or more second field regions 87.

[0297] The depth D4 of the multiple third lower end portions 87b may decrease sequentially toward the peripheral edge of the first main surface 3. The depth D4 of the multiple third lower end portions 87b may decrease toward the peripheral edge of the first main surface 3 in units of two or more groups, each containing two or more second field regions 87.

[0298] In this embodiment, the second thickness T5 of the multiple second field regions 87 is approximately equal to one another. The second thickness T5 of the multiple second field regions 87 is arbitrary and can take various values ​​depending on the electric field to be relaxed. The second thickness T5 of the multiple second field regions 87 may be different from one another.

[0299] The second thickness T5 of the multiple second field regions 87 may increase sequentially toward the periphery of the first main surface 3. The second thickness T5 of the multiple second field regions 87 may increase toward the periphery of the first main surface 3 in units of two or more groups, each containing two or more second field regions 87.

[0300] The second thickness T5 of the multiple second field regions 87 may decrease sequentially toward the periphery of the first main surface 3. The second thickness T5 of the multiple second field regions 87 may decrease toward the periphery of the first main surface 3 in units of two or more groups, each containing two or more second field regions 87.

[0301] Each of the multiple second field regions 87 is formed in this configuration as a polygonal ring (a quadrilateral ring in this configuration) with four sides parallel to the periphery of the chip 2 in a plan view, and surrounds the terminal region 42. The multiple second field regions 87 are formed at intervals from each other and surround the active region 8 (Figures 3 and 4).

[0302] The second field region 87 is formed in an electrically floating state. A source potential may be applied to the second field region 87.

[0303] Referring to Figure 18, another difference between semiconductor device 1B and semiconductor device 1A is that each of the multiple surface regions 63 includes an n-type first surface region 91 and an n-type second surface region 92 that are spaced apart from each other in the vertical direction Z.

[0304] Each of the multiple first surface regions 91 is formed between the multiple first field regions 62 and the multiple second field regions 87. The multiple first surface regions 91 are formed in a one-to-one correspondence with the multiple first field regions 62 and the multiple second field regions 87.

[0305] The first surface region 91 is formed in the second epitaxial layer 72. The first surface region 91 is the region that sandwiches the corresponding first field region 62 between itself and the first epitaxial layer 71 in the vertical direction Z (the depth direction of the chip 2). In other words, the first surface region 91 is the region sandwiched in the vertical direction Z by the corresponding first field region 62 and the corresponding second field region 87.

[0306] The first surface region 91 has a fourth upper end portion 91a on the first main surface 3 side and a fourth lower end portion 91b on the opposite side. The first surface region 91 is in contact with both the first field region 62 and the second field region 87.

[0307] The fourth upper end portion 91a is located at a depth position spaced apart from the depth position of the boundary portion 73 between the first epitaxial layer 71 and the second epitaxial layer 72 toward the first main surface 3. The fourth upper end portion 91a is at the same depth position as the third lower end portion 87b of the second field region 87. The fourth upper end portion 91a extends horizontally along the first main surface 3. The fourth upper end portion 91a forms a pn junction with the second field region 87.

[0308] The fourth lower end portion 91b is located at the same depth as the boundary portion 73 between the first epitaxial layer 71 and the second epitaxial layer 72. The fourth lower end portion 91b is at the same depth as the first upper end portion 62a of the first field region 62. The fourth lower end portion 91b extends horizontally along the first main surface 3. The fourth lower end portion 91b forms a pn junction with the first field region 62.

[0309] The first surface region 91 includes a fourth side portion connecting the fourth upper end portion 91a and the fourth lower end portion 91b. In this embodiment, the fourth side portion is perpendicular to the fourth upper end portion 91a and the fourth lower end portion 91b. That is, the fourth side portion extends along the vertical direction (has a vertical plane).

[0310] The thickness of the first surface region 91 is greater than (thicker than) both the second thickness T5 of the first field region 62 and the thickness of the second surface region 92. The thickness of the first surface region 91 may be the same as at least one of the second thickness T5 of the first field region 62 and the thickness of the second surface region 92, or it may be less than (thinner than) at least one of the second thickness T5 of the first field region 62 and the thickness of the second surface region 92.

[0311] The first surface region 91 is n-type, consisting of an n-type epitaxial layer (second epitaxial layer 72). The peak value of the n-type impurity concentration in the first surface region 91 is higher than the peak value of the n-type impurity concentration in the first epitaxial layer 71.

[0312] The first surface region 91 is a region containing p-type impurities. Throughout the entire first surface region 91, the concentration of n-type impurities in the first surface region 91 is higher than the concentration of p-type impurities in the first surface region 91.

[0313] The second surface region 92 is formed in the second epitaxial layer 72. The second surface region 92 is the region that sandwiches the corresponding second field region 87 between itself and the first surface region 91 in the vertical direction Z (the depth direction of the chip 2). In other words, the second surface region 92 is the region sandwiched in the vertical direction Z by the corresponding second field region 87 and the first main surface 3.

[0314] The second surface region 92 has a fifth upper end portion 92a on the first main surface 3 side and a fifth lower end portion 92b on the opposite side. The second surface region 92 is in contact with the second field region 87.

[0315] The fifth upper end portion 92a extends horizontally along the first main surface 3 and is exposed from the first main surface 3.

[0316] The fifth lower end portion 92b is located at a depth position that is spaced apart from the first main surface 3 toward the second main surface 4. The fifth lower end portion 92b is at the same depth position as the third upper end portion 87a of the second field region 87. The fifth lower end portion 92b extends horizontally along the first main surface 3. The fifth lower end portion 92b forms a pn junction with the second field region 87.

[0317] The second surface region 92 includes a fifth side portion connecting the fifth upper end portion 92a and the fifth lower end portion 92b. In this embodiment, the fifth side portion is perpendicular to the fifth upper end portion 92a and the fifth lower end portion 92b. That is, the fifth side portion extends along the vertical direction (has a vertical plane).

[0318] The thickness of the second surface region 92 may be the same as the second thickness T5 of the first field region 62. The thickness of the second surface region 92 may be greater (thicker) than the second thickness T5 of the first field region 62, or less (thinner) than the second thickness T5 of the first field region 62.

[0319] The second surface region 92 is n-type, consisting of an n-type epitaxial layer (second epitaxial layer 72). The peak value of the n-type impurity concentration in the second surface region 92 is higher than the peak value of the n-type impurity concentration in the first epitaxial layer 71.

[0320] The second surface region 92 is a region containing p-type impurities. Throughout the entire second surface region 92, the concentration of n-type impurities in the second surface region 92 is higher than the concentration of p-type impurities in the second surface region 92.

[0321] The following describes in detail the concentration gradients of n-type and p-type impurities in the impurity region within chip 2.

[0322] The numerical values ​​for impurity concentrations, etc., shown below are examples for explaining the basic configuration of the first field region 62 and the second field region 87 (field region 43), the first surface region 91 and the second surface region 92 (surface region 63), and the first epitaxial layer 71 (second semiconductor region 7) based on the concentration gradient. These values ​​are not intended to uniquely limit the configuration of the first field region 62 and the second field region 87 (field region 43), the first surface region 91 and the second surface region 92 (surface region 63), and the first epitaxial layer 71 (second semiconductor region 7). Impurity concentrations, thicknesses, etc., are adjusted to various values ​​depending on the injection conditions (dose amount, injection temperature, injection energy, etc.) for trivalent or pentavalent elements. Also, the term "concentration gradient" may be completely replaced with the term "concentration profile."

[0323] Figure 19 is a graph showing an example (fifth form example) of the concentration gradient 130 of p-type impurities in the region along the XIX-XIX line shown in Figure 18. In Figure 12, the concentration gradient 120 of n-type impurities is shown as a dashed line, along with the concentration gradient 130 of n-type impurities.

[0324] The concentration gradient 130 shown in Figure 19 is the concentration gradient of p-type impurities when traversing the second surface region 92, the second field region 87, the first surface region 91, and the first field region 62 in the depth direction from the first main surface 3 to the chip 2.

[0325] In the second embodiment, a field region 43 is formed by implanting p-type impurities into the second semiconductor region 7 in two stages. In these two stages of implantation, p-type impurities are implanted at different depth positions. Therefore, the concentration gradient of p-type impurities in the second semiconductor region 7 includes the concentration gradient of p-type impurities introduced in the first stage and the concentration gradient of p-type impurities introduced in the second stage. The combined concentration gradient of these two forms the concentration gradient 130 of p-type impurities in the second semiconductor region 7.

[0326] In the example shown in Figure 19, the concentration gradient 123 of the p-type impurity can be mapped to the concentration gradient of the p-type impurity introduced in the first stage. In this case, the concentration gradient 126 of the p-type impurity can be mapped to the concentration gradient of the p-type impurity introduced in the second stage.

[0327] Conversely, the concentration gradient 126 of the p-type impurity may be mapped to the concentration gradient of the p-type impurity introduced in the first stage. In this case, the concentration gradient 123 of the p-type impurity may be mapped to the concentration gradient of the p-type impurity introduced in the second stage.

[0328] In the example shown in Figure 19, the concentration gradient 126 of p-type impurities has a concentration gradient unique to the impurity region formed by the random injection method. The concentration gradient 126 of p-type impurities includes a rapid increase section 101, a peak section 102 (peak value P2), and a sharp decrease section 103. The rapid increase section 101 is the portion where the impurity concentration rapidly increases from the first main surface 3 towards the peak section 102.

[0329] The peak portion 102 is the portion having the peak value P2 (maximum value) of the p-type impurity concentration. The peak portion 102 is also a convex main concentration transition portion that includes a series of concentration changes (inflection points) where the p-type impurity concentration changes from increasing (increasing trend) to decreasing (decreasing trend).

[0330] In the example shown in Figure 19, the peak portion 102 is set at a depth position in the second field region 87 (second epitaxial layer 72). In other words, the concentration gradient 126 of p-type impurities has a peak value P2 in the second field region 87. In the example shown in Figure 19, for example, the peak value P2 (maximum value) of the p-type impurity concentration is approximately 6 × 10⁻¹⁰. １７ cm －３ That's fine.

[0331] In other words, the peak portion 102 of the p-type impurity concentration gradient 126 is located at a shallower position than the peak portion 66 of the p-type impurity concentration gradient 123. Furthermore, the peak value P2 of the p-type impurity concentration gradient 126 is higher than the peak value P1 of the p-type impurity concentration gradient 123.

[0332] The abrupt reduction section 103 is the portion that forms the third lower end portion 87b of the second field region 87. The p-type impurity concentration in the abrupt reduction section 103 is 1 × 10⁻⁶. １５ cm －３ It is gradually decreasing to that point.

[0333] The concentration gradient 123 of p-type impurities has already been explained in relation to Figure 12, so a detailed explanation will be omitted.

[0334] The concentration gradient 130 of p-type impurities shown in Figure 19 includes a first peak 141 and a second peak 142. The first peak 141 is the portion having the peak value P3 (maximum value) of the p-type impurity concentration. The first peak 141 is located at the same depth as the peak 102 of the p-type impurity concentration gradient 126. The peak value P3 is approximately the same as the peak value P2 of the peak 102.

[0335] The second peak portion 142 is the portion having the peak value P4 (maximum value) of the p-type impurity concentration. The second peak portion 142 is located at the same depth as the peak portion 66 of the p-type impurity concentration gradient 123. The peak value P4 of the second peak portion 142 is the same as the peak value P1 of the peak portion 66.

[0336] The first peak portion 141 of the p-type impurity concentration gradient 130 is located at a shallower depth than the second peak portion 142 of the p-type impurity concentration gradient 130. Furthermore, the peak value P3 of the first peak portion 141 is higher than the peak value P4 of the second peak portion 142.

[0337] Referring to Figure 19, the concentration gradient 130 of p-type impurities includes a second peak 142 in the low-concentration section 122. The second peak 142 corresponds to the n-type impurity concentration (for example, 1 × 10⁻⁶) in the low-concentration section 122. １６ cm －３ It has a higher peak value P4 than ).

[0338] Therefore, in the low-concentration section 122, a region is formed where the p-type impurity concentration exceeds the n-type impurity concentration. This region exhibits the characteristics (electrical behavior) of the p-type impurity region. This region is the first field region 62, which is the p-type impurity region.

[0339] Furthermore, the concentration gradient 130 of p-type impurities includes a first peak portion 141 in the high-concentration section 121. The first peak portion 141 corresponds to the n-type impurity concentration (for example, 1 × 10⁻⁶) in the high-concentration section 121. １７ cm －３ It has a higher peak value P3 than ).

[0340] Therefore, in the high-concentration section 121, a region is formed where the p-type impurity concentration exceeds the n-type impurity concentration. This region exhibits the characteristics (electrical behavior) of the p-type impurity region. This region is the second field region 87, which is the p-type impurity region.

[0341] On the other hand, in the high-concentration section 121, a region is formed where the p-type impurity concentration is lower than the n-type impurity concentration. This region exhibits the characteristics (electrical behavior) of the n-type impurity region. This region is the first surface region 91, which is an n-type region, and the second surface region 92, which is an n-type region. The first surface region 91 is located on the first main surface 3 side with respect to the second field region 87. The second surface region 92 is located on the first field region 62 side (second main surface 4 side) with respect to the second field region 87.

[0342] The second surface region 92 corresponds to the sharp increase in the concentration gradient 130 of p-type impurities (the sharp increase 101 in the concentration gradient 126). Since the surface region 63 is formed in the portion corresponding to the sharp increase in the concentration gradient 130 (the sharp increase 101), the second surface region 92 has a concentration gradient of p-type impurities that increases as you move from the first main surface 3 toward the first field region 62.

[0343] Figures 20A to 20E are cross-sectional views showing the manufacturing method of the semiconductor device 1B. Figures 20A to 20E show a cross-section of a part of the outer peripheral region 9.

[0344] A wafer 150 having a second semiconductor region 7 is formed by the method described in Figures 15A to 15C. The second semiconductor region 7 has a laminated structure in which a second epitaxial layer 72 is formed on a first epitaxial layer 71.

[0345] Then, referring to Figure 20A, a first mask 160 having a predetermined opening 161 is placed on the first wafer main surface 151 of the wafer 150. The first mask 160 may be an inorganic mask (for example, a silicon oxide film) or an organic mask (mask). The opening 161 exposes the area that forms the first field region 62 (field region 43) and covers the other areas.

[0346] Next, p-type impurities are implanted from the main surface 151 of the first wafer toward the first epitaxial layer 71 by ion implantation via the first mask 160 (first stage implantation, first ion implantation step). This introduces p-type impurities into the second semiconductor region 7.

[0347] The ion implantation method may be a random ion implantation method. In the random ion implantation step, p-type impurities may be implanted in a single step at the target depth position of the second semiconductor region 7. The p-type impurity implantation step may include a step of implanting p-type impurities multiple times at the target depth position of the second semiconductor region 7 in the single-step implantation step.

[0348] Furthermore, the ion implantation method may be channeling ion implantation. Moreover, the ion implantation method may be both channeling ion implantation and random ion implantation.

[0349] In the ion implantation method (first stage), at least one of the implantation energy and dose (impurity concentration) of the implanted p-type impurity is adjusted so that in the low-concentration section 122 (Figure 19), the concentration gradient 130 of p-type impurities includes a peak portion 66 having a peak value P1 (Figure 19) that exceeds the n-type impurity concentration (the concentration gradient 130 of p-type impurities includes a second peak portion 142 having a peak value P4 (Figure 19) that exceeds the n-type impurity concentration in the low-concentration section 122 (Figure 19)), and in the entire depth direction of the high-concentration section 121 (Figure 19), the p-type impurity concentration is lower than the n-type impurity concentration.

[0350] By implanting p-type impurities using the ion implantation method (first stage), a region where the p-type impurity concentration exceeds the n-type impurity concentration is formed in the low-concentration section 122, and this region becomes the first field region 62. As a result, multiple p-type first field regions 62 (field regions 43) are formed in the first epitaxial layer 71.

[0351] Furthermore, the implantation of p-type impurities by the ion implantation method (first stage) forms n-type impurity regions containing p-type impurities in the high-concentration section 121, and these regions become surface regions 63. As a result, multiple n-type surface regions 63 are formed in the second epitaxial layer 72.

[0352] Next, referring to Figure 20B, p-type impurities are implanted from the main surface 151 of the first wafer toward the first epitaxial layer 71 by ion implantation through the same first mask 160 (second stage implantation, second ion implantation step). This introduces p-type impurities into the second semiconductor region 7 (Figure 20A).

[0353] The ion implantation method may be a random ion implantation method. In the random ion implantation step, p-type impurities may be implanted in a single step at the target depth position of the second semiconductor region 7. The p-type impurity implantation step may include a step of implanting p-type impurities multiple times at the target depth position of the second semiconductor region 7 in the single-step implantation step.

[0354] Furthermore, the ion implantation method may be channeling ion implantation. Moreover, the ion implantation method may be both channeling ion implantation and random ion implantation.

[0355] In the ion implantation method (second stage), at least one of the implantation energy and dose (impurity concentration) of the implanted p-type impurity is adjusted so that the concentration gradient 126 of the p-type impurity includes a peak portion 102 having a peak value P2 (Figure 19) that exceeds the n-type impurity concentration in the high-concentration section 121 (Figure 19) (and the concentration gradient 130 of the p-type impurity includes a first peak portion 141 having a peak value P3 (Figure 19) that exceeds the n-type impurity concentration in the high-concentration section 121 (Figure 19)).

[0356] By implanting p-type impurities using the ion implantation method (second stage), a region where the p-type impurity concentration exceeds the n-type impurity concentration is formed in the high-concentration section 121, and this region becomes the second field region 87. As a result, multiple p-type second field regions 87 (field regions 43) are formed in the second epitaxial layer 72.

[0357] Furthermore, the formation of the second field region 87 divides the surface region 63 into a first surface region 91 located on the first main surface 3 side relative to the second field region 87, and a second surface region 92 located on the first field region 62 side (second main surface 4 side) relative to the second field region 87.

[0358] Subsequently, in the active region 8, a plurality of trench gate structures 15 (Figure 9) are formed in the second semiconductor region.

[0359] Next, referring to Figure 20C, a main surface insulating film 45 is formed to cover the main surface 151 of the first wafer.

[0360] Next, referring to Figure 20D, an interlayer film 47 is formed on the main surface 151 of the first wafer. This results in the interlayer film 47 being laminated onto the main surface insulating film 45. Furthermore, multiple trench gate structures (Figure 9) are covered by the interlayer film 47. The interlayer film 47 may be formed by CVD.

[0361] Next, the source electrode 51 (see Figure 1), source wiring 56 (see Figure 1), gate electrode 57 (see Figure 1), and gate wiring 58 (see Figure 1) are formed on the interlayer film 47. The source electrode 51, source wiring 56, gate electrode 57, and gate wiring 58 may be formed by sputtering or vapor deposition.

[0362] Next, referring to Figure 20E, a drain electrode 59 is formed on the second wafer main surface 152. The drain electrode 59 may be formed by sputtering or vapor deposition. Then, the wafer 150 is cut along the planned cutting line 156, and a plurality of semiconductor devices 1B are cut out. The semiconductor device 1B is manufactured through the process including the above.

[0363] The second field region 87 may be formed (Figure 20B, second ion implantation step), and then the first field region 62 may be formed (Figure 20A, first ion implantation step).

[0364] In this case, the implantation of p-type impurities by ion implantation (first stage) causes the second semiconductor region 7 to have a concentration gradient 126 of p-type impurities (Figure 19). Then, the implantation of p-type impurities by ion implantation (second stage) combines with the concentration gradient 123 of p-type impurities (Figure 19) to cause the second semiconductor region 7 to have a concentration gradient 130 (Figure 19).

[0365] Figure 21A is a graph showing a sixth example of the concentration gradient 131 of p-type impurities in tip 2, and corresponds to Figure 19.

[0366] The concentration gradient 131 shown in Figure 21A is the concentration gradient of p-type impurities when traversing the second surface region 92, the second field region 87, the first surface region 91, and the first field region 62 in the depth direction from the first main surface 3 to the chip 2.

[0367] The sixth embodiment shown in Figure 21A differs from the fifth embodiment shown in Figure 19 in that the tip 2 has a p-type impurity concentration gradient 124 instead of a p-type impurity concentration gradient 123. The p-type impurity concentration gradient 124 has already been explained in relation to Figure 16A, so a detailed explanation will be omitted.

[0368] In the example shown in Figure 21A, the concentration gradient 124 of the p-type impurity can be mapped to the concentration gradient of the p-type impurity introduced in the first stage. In this case, the concentration gradient 126 of the p-type impurity can be mapped to the concentration gradient of the p-type impurity introduced in the second stage.

[0369] Conversely, the concentration gradient 126 of the p-type impurities may be mapped to the concentration gradient of the p-type impurities introduced in the first stage. In this case, the concentration gradient 124 of the p-type impurities may be mapped to the concentration gradient of the p-type impurities introduced in the second stage.

[0370] The concentration gradient 131 of p-type impurities shown in Figure 21A includes a first peak 143 and a second peak 144. The first peak 143 is the portion having the peak value P3 (maximum value) of the p-type impurity concentration. The first peak 143 is located at the same depth as the peak 102 of the p-type impurity concentration gradient 126. The peak value P3 is approximately the same as the peak value P2 of the peak 102.

[0371] The second peak portion 144 is the portion having the peak value P4 (maximum value) of the p-type impurity concentration. The second peak portion 144 is located at the same depth as the peak portion 69 of the p-type impurity concentration gradient 124. The peak value P4 of the second peak portion 144 is the same as the peak value P1 of the peak portion 69.

[0372] The first peak portion 143 of the p-type impurity concentration gradient 131 is located at a shallower depth than the second peak portion 144 of the p-type impurity concentration gradient 131. Furthermore, the peak value P3 of the first peak portion 143 is higher than the peak value P4 of the second peak portion 144.

[0373] Referring to Figure 21A, the concentration gradient 131 of p-type impurities includes a second peak 144 in the low-concentration section 122. The second peak 144 corresponds to the n-type impurity concentration (for example, 1 × 10⁻¹⁶) in the low-concentration section 122. １６ cm －３ It has a higher peak value P4 than ).

[0374] Therefore, in the low-concentration section 122, a region is formed where the p-type impurity concentration exceeds the n-type impurity concentration. This region exhibits the characteristics (electrical behavior) of the p-type impurity region. This region is the first field region 62, which is the p-type impurity region.

[0375] Furthermore, the concentration gradient 131 of p-type impurities includes a first peak portion 143 in the high-concentration section 121. The first peak portion 143 corresponds to the n-type impurity concentration (for example, 1 × 10⁻⁶) in the high-concentration section 121. １７ cm －３ It has a higher peak value P3 than ).

[0376] Therefore, in the high-concentration section 121, a region is formed where the p-type impurity concentration exceeds the n-type impurity concentration. This region exhibits the characteristics (electrical behavior) of the p-type impurity region. This region is the second field region 87, which is the p-type impurity region.

[0377] On the other hand, in the high-concentration section 121, a region is formed where the p-type impurity concentration is lower than the n-type impurity concentration. This region exhibits the characteristics (electrical behavior) of the n-type impurity region. This region is the first surface region 91, which is an n-type region, and the second surface region 92, which is an n-type region. The first surface region 91 is located on the first main surface 3 side with respect to the second field region 87. The second surface region 92 is located on the first field region 62 side (second main surface 4 side) with respect to the second field region 87.

[0378] The second surface region 92 corresponds to the sharp increase in the concentration gradient 131 of p-type impurities (the sharp increase in the concentration gradient 126, portion 101). Since the surface region 63 is formed in the portion corresponding to the sharp increase in the concentration gradient 131 (the sharp increase in portion 101), the second surface region 92 has a concentration gradient of p-type impurities that increases as you move from the first main surface 3 toward the first field region 62.

[0379] Figure 21B is a graph showing a seventh example of the concentration gradient 132 of p-type impurities in tip 2, and corresponds to Figure 19.

[0380] The concentration gradient 132 shown in Figure 21B is the concentration gradient of p-type impurities when traversing the second surface region 92, the second field region 87, the first surface region 91, and the first field region 62 in the depth direction from the first main surface 3 to the chip 2.

[0381] The seventh embodiment shown in Figure 21B differs from the fifth embodiment shown in Figure 19 in that the tip 2 has a p-type impurity concentration gradient 125 instead of a p-type impurity concentration gradient 123. The p-type impurity concentration gradient 125 has already been explained in relation to Figure 16B, so a detailed explanation will be omitted.

[0382] In the example shown in Figure 21B, the concentration gradient 125 of the p-type impurity can be mapped to the concentration gradient of the p-type impurity introduced in the first stage. Furthermore, the concentration gradient 126 of the p-type impurity can be mapped to the concentration gradient of the p-type impurity introduced in the second stage.

[0383] Conversely, the concentration gradient 126 of the p-type impurities may be associated with the concentration gradient of the p-type impurities introduced in the first stage. Alternatively, the concentration gradient 125 of the p-type impurities may be associated with the concentration gradient of the p-type impurities introduced in the second stage.

[0384] The concentration gradient 132 of p-type impurities shown in Figure 21B includes a first peak 145 and a second peak 146. The first peak 145 is the portion having the peak value P3 (maximum value) of the p-type impurity concentration. The first peak 145 is located at the same depth as the peak 102 of the p-type impurity concentration gradient 126. The peak value P3 is approximately the same as the peak value P2 of the peak 102.

[0385] The second peak portion 146 is the portion having the peak value P4 (maximum value) of the p-type impurity concentration. The second peak portion 146 is located at the same depth as the peak portion 69 of the p-type impurity concentration gradient 125. The peak value P4 of the second peak portion 146 is the same as the peak value P1 of the peak portion 69.

[0386] The first peak portion 145 of the p-type impurity concentration gradient 132 is located at a shallower depth than the second peak portion 146 of the p-type impurity concentration gradient 132. Furthermore, the peak value P3 of the first peak portion 145 is higher than the peak value P4 of the second peak portion 146.

[0387] Referring to Figure 21B, the concentration gradient 132 of p-type impurities includes a second peak 146 in the high-concentration section 121. The second peak 146 corresponds to the n-type impurity concentration (for example, 1 × 10⁻⁶) in the high-concentration section 121. １７ cm －３ It has a lower peak value P4 than ).

[0388] On the other hand, in the slow region 83 included in the p-type impurity concentration gradient 125 (p-type impurity concentration gradient 132), the p-type impurity concentration exceeds the n-type impurity concentration in the low-concentration section 122. Therefore, a region is formed in the low-concentration section 122 where the p-type impurity concentration exceeds the n-type impurity concentration. This region exhibits the characteristics (electrical behavior) of the p-type impurity region. This region is the first field region 62, which is the p-type impurity region.

[0389] Furthermore, the concentration gradient 132 of p-type impurities includes a first peak portion 145 in the high-concentration section 121. The first peak portion 145 corresponds to the n-type impurity concentration (for example, 1 × 10⁻⁶) in the high-concentration section 121. １７ cm －３ It has a higher peak value P3 than ).

[0390] Therefore, in the high-concentration section 121, a region is formed where the p-type impurity concentration exceeds the n-type impurity concentration. This region exhibits the characteristics (electrical behavior) of the p-type impurity region. This region is the second field region 87, which is the p-type impurity region.

[0391] On the other hand, in the high-concentration section 121, a region is formed where the p-type impurity concentration is lower than the n-type impurity concentration. This region exhibits the characteristics (electrical behavior) of the n-type impurity region. This region is the first surface region 91, which is an n-type region, and the second surface region 92, which is an n-type region. The first surface region 91 is located on the first main surface 3 side with respect to the second field region 87. The second surface region 92 is located on the first field region 62 side (second main surface 4 side) with respect to the second field region 87.

[0392] The second surface region 92 corresponds to the sharp increase in the concentration gradient 132 of p-type impurities (the sharp increase in the concentration gradient 126, portion 101). Since the surface region 63 is formed in the portion corresponding to the sharp increase in the concentration gradient 132 (the sharp increase in portion 101), the second surface region 92 has a concentration gradient of p-type impurities that increases as you move from the first main surface 3 toward the first field region 62.

[0393] Figure 22 is a cross-sectional view showing the field region 43 and the surface region 63 according to a second modification of the second embodiment.

[0394] In the second modified example, the first field region 62 is formed in a mesa shape in cross-section, having a first side portion 62c that slopes so as to narrow in width (width W1, width W3) from the first upper end portion 62a to the first lower end portion 62b (W1 < W3). In this embodiment, the first side portion 62c slopes from the first upper end portion 62a to the first lower end portion 62b.

[0395] The second field region 87 in the second modified example is formed in a mesa shape in cross-sectional view, having a third side portion 87c that slopes so as to narrow in width (width W4, width W5) from the third upper end portion 87a to the third lower end portion 87b (W4 < W5). In this embodiment, the third side portion 87c slopes from the third upper end portion 87a to the third lower end portion 87b.

[0396] In the second modified example, the first surface region 91 is formed in a mesa shape in cross-sectional view, having a fourth side portion 91c that slopes so as to narrow in width (width W3, width W4) from the fourth upper end portion 91a to the fourth lower end portion 91b (W3 < W4). The fourth side portion 91c connects the fourth upper end portion 91a and the fourth lower end portion 91b. In this second modified example, the fourth side portion 91c slopes from the fourth upper end portion 91a to the fourth lower end portion 91b.

[0397] As described above, the second embodiment provides the following effects in addition to those described in the first embodiment.

[0398] In this configuration, a p-type second field region 87 is formed in the second epitaxial layer 72 by implanting p-type ions into the second epitaxial layer 72. Since p-type regions are relatively difficult to form in the second epitaxial layer 72 with a high concentration of n-type ions, p-type regions can be formed only in the desired region. Therefore, the third upper end portion 87a and the third lower end portion 87b of the second field region 87 can be controlled with high precision.

[0399] Furthermore, in this configuration, the field region comprises a first field region 62 and a second field region 87 formed with a gap between them vertically. While the high-concentration second field region 87 has the effect of effectively relaxing the electric field, there is a risk of crystal defects being generated by pn bonds. By forming the low-concentration first field region 62 with a narrow gap between it and the second field region 87, pn bonds can be kept away, thereby suppressing the generation of crystal defects. In other words, the electric field can be effectively relaxed while suppressing the generation of crystal defects.

[0400] Figure 23 is a cross-sectional view of the main part of the semiconductor device 1C according to the second embodiment of this disclosure. Figure 23 mainly shows a cross-section of the region spanning the active region 8 and the outer peripheral region 9. Figure 24 is a cross-sectional view showing the main part of the semiconductor device 1C, and shows a cross-section at the same position as in Figure 10.

[0401] Referring to Figure 23, semiconductor device 1C has a configuration in which the configuration of the multiple gate structures related to semiconductor device 1A has been changed. More specifically, semiconductor device 1C includes a planar gate structure 200 instead of a trench gate structure 15 as a gate structure.

[0402] Prior to describing the planar gate structure 200, the semiconductor device 1C includes a plurality of p-type body regions 201 formed on the surface layer of the first main surface 3 in the active region 8. The plurality of body regions 201 are arranged with spacing in the first direction X and are each formed in a strip shape extending in the second direction Y. In other words, the plurality of body regions 201 are arranged in a stripe shape extending in the second direction Y.

[0403] Multiple body regions 201 are formed at intervals from the bottom of the second semiconductor region 7 toward the first main surface 3, and face the first semiconductor region 6 with a portion of the second semiconductor region 7 in between. Preferably, the multiple body regions 201 are formed at intervals from the middle of the second semiconductor region 7 toward the first main surface 3. Multiple body regions 201 are exposed from the first main surface 3.

[0404] The multiple body regions 201 are formed to be shallower than the terminal region 42 and the field region 43. The multiple body regions 201 may also be formed to be deeper than the outer contact region 41.

[0405] The semiconductor device 1C includes n-type source regions 202 formed on the surface of each of the multiple body regions 201. The source regions 202 have a higher n-type impurity concentration than the n-type impurity concentration of the first semiconductor region 6. A source potential is applied to the source regions 202.

[0406] The semiconductor device 1C includes a plurality of p-type channel regions 203 formed on the surface layer of the first main surface 3. The plurality of channel regions 203 are each partitioned in the surface layer of the plurality of body regions 201 in the region between the ends of the plurality of body regions 201 and the periphery of the source region 202. In this embodiment, the plurality of channel regions 203 are arranged with spacing in the first direction X and are each formed in a strip shape extending in the second direction Y. In other words, the plurality of channel regions 203 are arranged in a stripe shape extending in the second direction Y.

[0407] Each planar gate structure 200 is positioned on at least one channel region 203. In this embodiment, each planar gate structure 200 is positioned across the region between two adjacent body regions 201 and straddles the two body regions 201, covering a plurality of channel regions 203. Specifically, each planar gate structure 200 is positioned across the source region 202 on one body region 201 and the source region 202 on the other body region 201, covering a portion of the source region 202 and the channel regions 203.

[0408] The planar gate structure 200 has a stacked structure including an insulating film 204 and a gate electrode 205. The insulating film 204 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this form, the insulating film 204 has a single-layer structure made of a silicon oxide film. The insulating film 204 particularly preferably includes a silicon oxide film made of the oxide of chip 2.

[0409] The insulating film 204 covers the first main surface 3 in a film shape and is disposed on at least one channel region 203. In this form, the insulating film 204 is disposed so as to straddle two adjacent body regions 201 and covers a plurality of channel regions 203.

[0410] Specifically, the insulating film 204 is disposed so as to straddle the source region 202 on one body region 201 side and the source region 202 on the other body region 201 side, and covers a part of the source region 202 and the channel region 203.

[0411] The gate electrode 205 is disposed on the insulating film 204 and faces at least one channel region 203 with the insulating film 204 interposed therebetween. A gate potential as a control potential is applied to the gate electrode 205. The gate electrode 205 controls the inversion and non-inversion of at least one channel region 203 in response to the gate potential.

[0412] The gate electrode 205 includes a semiconductive polycrystal having conductivity. The gate electrode 205 may include either one or both of a p-type conductive polysilicon and an n-type conductive polysilicon. The conductivity type of the gate electrode 205 is adjusted according to the gate threshold voltage to be achieved. The gate electrode 205 may be referred to as a "polysilicon gate", a "poly gate", or the like.

[0413] The semiconductor device 1C includes a low-concentration region 206 laminated on the first epitaxial layer 71. The low-concentration region 206 is a part of the second semiconductor region 7. The low-concentration region 206 is formed laterally to the body region 201 between the first epitaxial layer 71 and the first main surface 3. The low-concentration region 206 is in contact with the body region 201 and is formed in a layer shape extending along the first main surface 3. The body region 201 crosses the boundary between the first epitaxial layer 71 and the low-concentration region 206 in the thickness direction of the second semiconductor region 7 and contacts both side portions of the first epitaxial layer 71 and the low-concentration region 206.

[0414] It is preferable that the n-type impurity concentration of the low-concentration region 206 is lower than the n-type impurity concentration of the first epitaxial layer 71. The n-type impurity concentration of the low-concentration region 206 may be substantially constant in the thickness direction. Of course, the n-type impurity concentration of the low-concentration region 206 may have a concentration gradient that gradually increases and / or decreases in the thickness direction (crystal growth direction) of the chip 2.

[0415] The termination region 42 is formed deeper than the plurality of body regions 201 along the outer peripheral boundary portion 19 between the active region 8 and the outer peripheral region 9. The termination region 42 may be approximately the same depth as the plurality of body regions 201.

[0416] More specifically, the body region 201 includes a well side portion 201a extending in the thickness direction of the second semiconductor region 7 and a well bottom portion 201b extending from the well side portion 201a in the direction along the first main surface 3. The termination region 42 is in contact with the well side portion 201a.

[0417] Referring to FIG. 24, the plurality of field regions 43 are arranged at intervals outward from the termination region 42 in the outer peripheral region 9, similar to the semiconductor device 1A according to the first embodiment. In this embodiment, each field region 43 is formed in a polygonal ring shape (in this embodiment, a square ring shape) having four sides parallel to the periphery of the chip 2 in a plan view and surrounds the termination region 42.

[0418] The plurality of field regions 43 each include a p-type first field region 62. The first field region 62 is embedded in the surface layer portion of the second semiconductor region 7.

[0419] The semiconductor device 1C includes a plurality of n-type surface regions 63 formed between the first main surface 3 and a plurality of first field regions 62. The plurality of surface regions 63 are formed in a one-to-one correspondence with the plurality of first field regions 62.

[0420] Semiconductor device 1C provides the same effects and benefits as those described in relation to semiconductor device 1A according to the first embodiment.

[0421] The semiconductor device 1C may be fitted with the first to fourth embodiments and the first modification of the semiconductor device 1A according to the first embodiment, as well as the fifth to seventh embodiments and the second modification of the semiconductor device 1B according to the second embodiment.

[0422] Figure 25 is a cross-sectional view of a main part of a semiconductor device 1D according to the fourth embodiment of this disclosure. Figure 25 corresponds to Figure 2.

[0423] Referring to Figure 25, semiconductor device 1D has a modified configuration of the device structure related to semiconductor device 1A. More specifically, semiconductor device 1D has a Schottky barrier diode 300 (Schottky Barrier Diode structure) in the active region 8 instead of an insulated gate type transistor structure Tr as a device structure.

[0424] The semiconductor device 1D, like the semiconductor device 1A, includes a chip 2, a first semiconductor region 6, a second semiconductor region 7, an active region 8, a peripheral region 9, and a plurality of field regions 43.

[0425] The semiconductor device 1D includes an interlayer insulating film 301 that selectively covers the first main surface 3. The interlayer insulating film 301 may have a single-layer structure or a multilayer structure that includes at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the interlayer insulating film 301 has a single-layer structure that includes a silicon oxide film.

[0426] The interlayer insulating film 301 covers a plurality of field regions 43 in the outer peripheral region 9. In this embodiment, the interlayer insulating film 301 is continuous with the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3. Of course, the interlayer insulating film 301 may be formed with a gap inward from the periphery of the first main surface 3, exposing the second semiconductor region 7 from the periphery of the first main surface 3.

[0427] The interlayer insulating film 301 has a contact opening 302 that exposes the active region 8. In this configuration, the contact opening 302 has an opening wall surface located above the anode region 304 and exposes the entire active region 8 and the inner edge of the innermost of the multiple field regions 43.

[0428] The semiconductor device 1D includes a Schottky electrode 303 that covers the first main surface 3 in the active region 8. The Schottky electrode 303 is formed as an anode pad. The Schottky electrode 303 is spaced inward from the periphery of the chip 2. In a plan view, the Schottky electrode 303 is formed in a polygonal shape (a quadrilateral shape in this embodiment) along the periphery of the chip 2.

[0429] The Schottky electrode 303 enters the contact opening 302 from above the interlayer insulating film 301 and is electrically connected to the first main surface 3 and the anode region 304 within the contact opening 302. The Schottky electrode 303 forms a Schottky junction with the first main surface 3. As a result, a Schottky barrier diode structure 300 is formed in the active region 8 as a device structure.

[0430] The semiconductor device 1D includes a pad electrode 305 that covers the second main surface 4. The pad electrode 305 is formed as a cathode pad. The pad electrode 305 forms ohmic contact with the first semiconductor region 6 exposed from the second main surface 4. In other words, the pad electrode 305 is electrically connected to the anode region 304.

[0431] The pad electrode 305 may cover the entire area of ​​the second main surface 4 so as to be continuous with the periphery (first to fourth side surfaces 5A to 5D) of the tip 2. Alternatively, the pad electrode 305 may cover the second main surface 4 with a gap inward from the periphery of the tip 2 so as to expose the periphery of the tip 2.

[0432] The breakdown voltage that can be applied between the Schottky electrode 303 and the pad electrode 305 (between the first main surface 3 and the second main surface 4) may be 500V or more and 3000V or less. The breakdown voltage may have a value that falls within any one of the following ranges: 500V or more and 1000V or less, 1000V or more and 1500V or less, 1500V or more and 2000V or less, 2000V or more and 2500V or more and 3000V or less.

[0433] The Schottky electrode 303 is mechanically and electrically connected to the second semiconductor region 7 and the anode region 304 on the first main surface 3. In this case, the Schottky electrode 303 forms a Schottky junction with the anode region 304.

[0434] In semiconductor device 1D, similar to semiconductor device 1A according to the first embodiment, each of the multiple field regions 43 includes a p-type first field region 62. The first field region 62 is embedded in the surface layer of the second semiconductor region 7.

[0435] The semiconductor device 1D includes a plurality of n-type surface regions 63 formed between the first main surface 3 and a plurality of first field regions 62. The plurality of surface regions 63 are formed in a one-to-one correspondence with the plurality of first field regions 62.

[0436] The semiconductor device 1D provides the same effects and benefits as those described in relation to the semiconductor device 1A according to the first embodiment.

[0437] The semiconductor device 1D may be fitted with the first to fourth embodiments and the first modification of the semiconductor device 1A according to the first embodiment, as well as the fifth to seventh embodiments and the second modification of the semiconductor device 1B according to the second embodiment.

[0438] The embodiments described above (including variations) can be implemented in other forms. For example, in each of the embodiments described above, a chip 2 containing a SiC single crystal was used. However, the chip 2 may also contain a silicon single crystal. Similarly, the first semiconductor region 6 may contain a silicon single crystal. Similarly, the second semiconductor region 7 may contain a silicon single crystal.

[0439] In each of the above-described embodiments, a structure may be adopted in which the conductivity type of the "n-type" semiconductor region is inverted to "p-type," and the conductivity type of the "p-type" semiconductor region is inverted to "n-type." The specific configuration in this case can be obtained by replacing "n-type" with "p-type" and simultaneously replacing "p-type" with "n-type" in the above description and attached drawings.

[0440] In the first to third embodiments, a p-type collector region may be formed on the surface layer of the second main surface 4 of the chip 2. In this case, the transistor structure Tr includes an IGBT (Insulated Gate Bipolar Transistor) structure instead of a MISFET structure. The specific configuration in this case is obtained by replacing the "source" of the MISFET structure with the "emitter" of the IGBT structure and the "drain" of the MISFET structure with the "collector" of the IGBT structure, as described above. In this case, the chip 2 may have a single-layer structure made of an n-type semiconductor substrate.

[0441] The following are examples of features extracted from this specification and drawings. The alphanumeric characters in parentheses below represent the corresponding components in each of the embodiments described above, but this is not intended to limit the scope of each Clause to the embodiments. The term "semiconductor device" in the following items may be replaced with "semiconductor device," "wide bandgap semiconductor device," "semiconductor switching device," "semiconductor rectifier," "MISFET device," "IGBT device," "diode device," etc., as needed.

[0442] [Supplementary Note 1-1] A chip (2) having a main surface (3), a first-conductivity-type semiconductor region (7) formed in the surface layer portion of the main surface (3) and consisting of epitaxial layers (71, 72), an active region (8) provided in the inner portion of the main surface (3), an outer peripheral region (9) provided at the peripheral edge of the main surface (3) and surrounding the active region (8), a device structure (Tr, 300) formed in the active region (8), a second-conductivity-type first field region (62) formed in the surface layer portion of the semiconductor region (7) in the outer peripheral region (9) with a gap in the depth direction of the chip (2) from the main surface (3), and a first-conductivity-type surface region (63) formed in the surface layer portion of the semiconductor region (7) in the outer peripheral region (9) and sandwiching the first field region (62) in the depth direction of the chip (2) between the semiconductor region (7), the surface region (63) being a region containing second-conductivity-type impurities. A semiconductor device (1A, 1B, 1C, 1D).

[0443] [Supplementary Note 1-2] The chip (2) has a concentration gradient (123, 124, 125, 130, 131, 132) of second-conductivity-type impurities. The semiconductor device (1A, 1B, 1C, 1D) according to Supplementary Note 1-1, wherein the concentration gradient (123) increases from the main surface (3) side toward the first field region (62) side in at least a part of the surface region (63).

[0444] [Supplementary Note 1-3] The semiconductor device (1A, 1B, 1C, 1D) according to Supplementary Note 1-2, wherein the concentration gradients (123, 124, 125, 130, 131, 132) include peak portions (66, 69, 82, 142, 144) in the first field region (62).

[0445] [Supplementary Note 1-4] The semiconductor device (1A, 1B, 1C, 1D) according to any one of Supplementary Notes 1-1 to 1-3, wherein the first-conductivity-type impurity concentration in the surface region (63) is higher than the first-conductivity-type impurity concentration in the semiconductor region (7).

[0446] [Appendix 1-5] The semiconductor device (1A, 1B, 1C, 1D) according to any one of Appendix 1-1 to 1-4, wherein the semiconductor region (7) includes a first epitaxial layer (71) and a second epitaxial layer (72) laminated on the first epitaxial layer (71) and having a higher concentration of first conductivity type impurities than the first epitaxial layer (71), the first field region (62) is formed on the first epitaxial layer (71), and the surface region (63) is formed on the second epitaxial layer (72).

[0447] [Note 1-6] The semiconductor device (1A, 1B, 1C, 1D) described in Note 1-5, wherein the concentration ratio of the first conductivity type impurity concentration of the second epitaxial layer (72) to the first conductivity type impurity concentration of the first epitaxial layer (71) is greater than 1 and 10 or less.

[0448] [Appendix 1-7] The semiconductor device (1B) according to Appendix 1-5 or Appendix 1-6, further comprising a second field region (87) of a second conductivity type formed in the second epitaxial layer (72) in the outer peripheral region (9) and facing the first field region (62) with a portion of the second epitaxial layer (72) in between, wherein the surface region (63) includes a first surface region (91) formed in the second epitaxial layer (72) and sandwiched in the depth direction of the chip (2) by the first field region (62) and the second field region (87), and a second surface region (92) formed in the second epitaxial layer (72) and formed in the region between the second field region (87) and the main surface (3).

[0449] [Appendix 1-8] The semiconductor device (1B) according to Appendix 1-7, wherein the concentration of the second conductivity type impurity in the second field region (87) is higher than the concentration of the second conductivity type impurity in the first field region (62).

[0450] [Appendix 1-9] The semiconductor device (1B) according to Appendix 1-7 or Appendix 1-8, wherein the chip (2) has a concentration gradient (130, 131, 132) of a second conductivity type impurity, and the concentration gradient (130, 131, 132) increases in the second surface region (92) from the main surface (3) side toward the second field region (87) side.

[0451] [Note 1-10] The semiconductor device (1B) according to Note 1-9, wherein the concentration gradient (130, 131, 132) includes a first peak portion (141, 143, 145) in the second field region (87).

[0452] [Appendix 1-11] The semiconductor device (1B) according to Appendix 1-10, wherein the concentration gradient (130, 131) includes a second peak portion (142, 144) in the first field region (52) having a peak value (P4) smaller than the peak value (P3) in the first peak portion (141, 143).

[0453] [Appendix 1-12] The semiconductor device (1B) according to any one of Appendix 1-7 to 1-11, wherein the second field region (87) has a second thickness (T5) that is smaller than the first thickness (T4) in the depth direction of the chip (2) of the first field region (62).

[0454] [Appendix 1-13] The semiconductor device (1A, 1B, 1C, 1D) according to any one of Appendix 1-1 to 1-12, wherein the first field region (62) includes a plurality of annular first field regions (62) formed at intervals from each other and surrounding the active region (8), and the surface region (63) includes a plurality of annular surface regions (63) formed at intervals from each other and surrounding the active region (8).

[0455] [Appendix 1-14] The semiconductor device (1A, 1B, 1C, 1D) according to any one of the appendices 1-1 to 1-13, wherein the chip (2) further has sides (5A to 5D), the semiconductor region (7) is exposed on the sides (5A to 5D), and the outermost of the plurality of first field regions (62) is formed at a distance from the sides (5A to 5D).

[0456] [Appendix 1-15] The semiconductor device (1A, 1B, 1C, 1D) described in any one of the appendices 1-1 to 1-14, wherein the first field region (62) is in an electrically floating state.

[0457] [Appendix 1-16] The semiconductor device (1A, 1B, 1C, 1D) described in any one of the appendices 1-1 to 1-15, wherein the chip (2) includes a SiC chip.

[0458] [Appendix 1-17] A method for manufacturing a semiconductor device (1A, 1B, 1C, 1D), comprising: a step of forming a first epitaxial layer (71) of a first conductivity type on a semiconductor substrate (6) of a first conductivity type; a step of forming a second epitaxial layer (72) of a first conductivity type on the first epitaxial layer (71), having a wafer main surface (151) and having a higher concentration of first conductivity type impurities than the first epitaxial layer (71); and a first ion implantation step of implanting ions of a second conductivity type from the wafer main surface (151) toward the first epitaxial layer (71) such that the concentration of second conductivity type impurities in a portion of the first epitaxial layer (71) exceeds the concentration of first conductivity type impurities, thereby forming a first field region (62) of a second conductivity type in the first epitaxial layer (71).

[0459] [Appendix 1-18] A method for manufacturing a semiconductor device (1B) according to Appendix 1-17, further comprising a second ion implantation step of implanting ions of a second conductivity type from the wafer main surface (151) toward the second epitaxial layer (72) such that the concentration of second conductivity type impurities in a portion of the second epitaxial layer (72) exceeds the concentration of first conductivity type impurities, thereby forming a second field region (87) of the second conductivity type in the second epitaxial layer (72).

[0460] [Appendix 1-19] A method for manufacturing a semiconductor device (1B) as described in Appendix 1-18, wherein the second ion implantation step is performed after the first ion implantation step.

[0461] [Appendix 1-20] A method for manufacturing a semiconductor device (1B) according to Appendix 1-18 or Appendix 1-19, wherein the first ion implantation step includes implanting ions of a second conductivity type from the wafer main surface (151) toward the first epitaxial layer (71) via a mask (160), and the second ion implantation step includes implanting ions of a second conductivity type from the wafer main surface (151) toward the second epitaxial layer (72) via the mask (160).

[0462] [Appendix 1-21] The semiconductor device (1A, 1B) according to any one of Appendix 1-1 to 1-16, wherein the device structure (Tr) includes a second conductivity type body region (10) formed on the surface of the semiconductor region (7), a first conductivity type source region (11) formed on the surface of the body region (10), and a plurality of trench gate structures (15) having a plurality of gate trenches (16) arranged in a stripe pattern that penetrate the source region (11) and the body region (10) and reach the semiconductor region (7), a gate insulating film (17) formed on the inner surface of the plurality of gate trenches (16), and gate electrodes (57) embedded in the plurality of gate trenches (16) via the gate insulating film (17).

[0463] [Appendix 1-22] The semiconductor device (1C) according to any one of Appendix 1-1 to 1-16, wherein the device structure (Tr) includes a plurality of planar gate structures (200) having a plurality of gate electrodes (205) arranged in a stripe pattern on the main surface (3), and a gate insulating film (204) between the plurality of gate electrodes (205) and the main surface (3), a plurality of second conductivity type body regions (201) formed on the surface layer of the semiconductor region (7) and facing the gate electrodes (205), and a first conductivity type source region (202) formed on the surface layer of each of the body regions (201). [Note 1-23] The semiconductor device (1D) according to any one of Notes 1-1 to 1-16, wherein the device structure (300) includes a Schottky barrier diode (300) which includes a second conductivity type anode region (304) formed on the surface of the semiconductor region (7) and a Schottky electrode (303) Schottky bonded to the anode region (304). [Note 1-24] A method for manufacturing a semiconductor device (1A to 1D) according to any one of Notes 1-17 to 1-20, wherein the first ion implantation step includes a step of implanting a second conductivity type ion by random ion implantation. [Note 1-25] A method for manufacturing a semiconductor device (1A to 1D) according to any one of Notes 1-17 to 1-20, wherein the first ion implantation step includes a step of implanting a second conductivity type ion by channeling ion implantation. [Appendix 1-26] The method for manufacturing a semiconductor device (1B) according to Appendix 1-18, wherein the first ion implantation step includes a step of implanting ions of a second conductivity type by random ion implantation, and the second ion implantation step includes a step of implanting ions of a second conductivity type by random ion implantation. [Appendix 1-27] The method for manufacturing a semiconductor device (1B) according to Appendix 1-18, wherein the first ion implantation step includes a step of implanting ions of a second conductivity type by channeling ion implantation, and the second ion implantation step includes a step of implanting ions of a second conductivity type by random ion implantation.

[0464] 1A...Semiconductor device, 1B...Semiconductor device, 1C...Semiconductor device, 1D...Semiconductor device, 2...Chip, 3...First main surface, 4...Second main surface, 5A...First side surface, 5B...Second side surface, 5C...Third side surface, 5D...Fourth side surface, 6...First semiconductor region, 7...Second semiconductor region (semiconductor region), 8...Active region, 9...Peripheral region, 10...Body region, 11...Source region, 12...First region, 13...Second region, 15...Trench gate structure, 15A...End trench gate structure, 16...First trench, 17...First insulating film, 18...First embedded electrode, 19...Peripheral boundary, 25...Gate well region, 25a...Bulge , 25b...well bottom, 27...gate contact region, 40...outer well region, 41...outer contact region, 42...termination region, 43...field region, 45...main surface insulating film, 47...interlayer film, 49...source opening, 50...outer opening, 51...source electrode, 51a...first pad portion, 51b...second pad portion, 51c...third pad portion, 56...source wiring, 57...gate electrode, 58...gate wiring, 59...drain electrode, 62...first field region, 62a...first upper end, 62b...first lower end, 62c...first side portion, 63...surface region, 63a...second upper end, 63b ...Second lower end, 63c...Second side, 64...Boundary, 65...Gradual increase, 66...Peak, 67...Gradual decrease, 68...Sudden increase, 69...Peak, 70...Sharp decrease, 71...First epitaxial layer, 72...Second epitaxial layer, 73...Boundary, 81...Gradual increase, 82...Peak, 83...Slow decrease, 84...Gradual decrease, 87...Second field region, 87a...Third upper end, 87b...Third lower end, 87c...Third side, 91...First surface region, 91a...Fourth upper end, 91b...Fourth lower end, 91c...Fourth side, 92...Second surface region, 92a...Fifth upper end, 92b...Fifth lower end, 101...Sharp decrease Increased section, 102...Peak section, 103...Sudden decrease section, 120...Concentration gradient, 121...High concentration section, 122...Low concentration section, 123...Concentration gradient, 124...Concentration gradient, 125...Concentration gradient, 126...Concentration gradient, 130...Concentration gradient, 131...Concentration gradient, 132...Concentration gradient, 141...First peak section, 142...Second peak section, 143...First peak section, 144...Second peak section, 145...First peak section, 146...Second peak section, 150...Wafer, 151...First wafer main surface, 152...Second wafer main surface, 153...Wafer side surface, 154...Marker, 155...Device region, 156...Planned cutting line,160...First mask, 161...Aperture, 200...Planar gate structure, 201...Body region, 201a...Well side, 201b...Well bottom, 202...Source region, 203...Channel region, 204...Insulating film, 205...Gate electrode, 206...Low concentration region, 300...Schottky barrier diode (device structure), 301...Interlayer insulating film, 302...Contact aperture, 303...Schottky electrode, 304...Anode region, 305...Pad electrode, D1...Depth, D2...Depth, D3...Depth, D4...Depth, P1...Peak value, P2...Peak value, P3...Peak value, P4...Peak value, T1...Thickness, T2...Thickness, T3...Thickness, T4...First thickness, T5...Second thickness, Tr...Transistor structure (device structure), X...First direction, Y...Second direction, Z...Vertical direction, α...Off-angle

Claims

1. A semiconductor device comprising: a chip having a main surface; a semiconductor region of a first conductivity type formed on the surface layer of the main surface and consisting of an epitaxial layer; an active region provided on the inner part of the main surface; an outer peripheral region provided on the periphery of the main surface and surrounding the active region; a device structure formed within the active region; a first field region of a second conductivity type formed on the surface layer of the semiconductor region in the outer peripheral region at a distance from the main surface in the depth direction of the chip; and a surface region formed on the surface layer of the semiconductor region in the outer peripheral region, which is a surface region of a first conductivity type that sandwiches the first field region between itself and the semiconductor region in the depth direction of the chip and contains a second conductivity type impurity.

2. The semiconductor device according to claim 1, wherein the chip has a concentration gradient of a second conductivity type impurity, and the concentration gradient increases in at least a portion of the surface region from the main surface side toward the first field region side.

3. The semiconductor device according to claim 2, wherein the concentration gradient includes a peak portion in the first field region.

4. The semiconductor device according to any one of claims 1 to 3, wherein the concentration of the first conductivity type impurity in the surface region is higher than the concentration of the first conductivity type impurity in the semiconductor region.

5. The semiconductor device according to any one of claims 1 to 4, wherein the semiconductor region includes a first epitaxial layer and a second epitaxial layer laminated on the first epitaxial layer and having a higher concentration of first conductivity type impurities than the first epitaxial layer, the first field region is formed on the first epitaxial layer, and the surface region is formed on the second epitaxial layer.

6. The semiconductor device according to claim 5, wherein the concentration ratio of the first conductivity type impurity concentration of the second epitaxial layer to the concentration of the first conductivity type impurity concentration of the first epitaxial layer is greater than 1 and less than or equal to 10.

7. The semiconductor device according to claim 5 or 6, further comprising a second field region of a second conductivity type formed in the second epitaxial layer in the outer peripheral region and facing the first field region with a portion of the second epitaxial layer in between, wherein the surface region comprises a first surface region formed in the second epitaxial layer and sandwiched in the depth direction of the chip by the first field region and the second field region, and a second surface region formed in the second epitaxial layer and formed in the region between the second field region and the main surface.

8. The semiconductor device according to claim 7, wherein the concentration of the second conductivity type impurity in the second field region is higher than the concentration of the second conductivity type impurity in the first field region.

9. The semiconductor device according to claim 7 or 8, wherein the chip has a concentration gradient of a second conductivity type impurity, and the concentration gradient increases in the second surface region from the main surface side toward the second field region side.

10. The semiconductor device according to claim 9, wherein the concentration gradient includes a first peak in the second field region.

11. The semiconductor device according to claim 10, wherein the concentration gradient includes a second peak portion having a peak value smaller than the peak value in the first peak portion in the first field region.

12. The semiconductor device according to any one of claims 7 to 11, wherein the second field region has a second thickness smaller than the first thickness in the depth direction of the chip in the first field region.

13. The semiconductor device according to any one of claims 1 to 12, wherein the first field region includes a plurality of annular first field regions formed at intervals from each other and surrounding the active region, and the surface region includes a plurality of annular surface regions formed at intervals from each other and surrounding the active region.

14. The semiconductor device according to any one of claims 1 to 13, wherein the chip further has a side surface, the semiconductor region is exposed on the side surface, and the outermost of the plurality of first field regions is formed at a distance from the side surface.

15. The semiconductor device according to any one of claims 1 to 14, wherein the first field region is electrically floating.

16. The semiconductor device according to any one of claims 1 to 15, wherein the chip includes a SiC chip.

17. A method for manufacturing a semiconductor device, comprising the steps of: preparing a wafer in which a first epitaxial layer of a first conductivity type is formed on a semiconductor substrate of a first conductivity type, a second epitaxial layer of a first conductivity type having a higher concentration of first conductivity type impurities than the first epitaxial layer is formed on the first epitaxial layer, and the wafer main surface is formed on the second epitaxial layer; and a first ion implantation step of implanting ions of a second conductivity type from the wafer main surface toward the first epitaxial layer such that the concentration of second conductivity type impurities in a portion of the first epitaxial layer exceeds the concentration of first conductivity type impurities, thereby forming a first field region of a second conductivity type on the first epitaxial layer.

18. A method for manufacturing a semiconductor device according to claim 17, further comprising a second ion implantation step of implanting ions of a second conductivity type from the main surface of the wafer toward the second epitaxial layer such that the concentration of second conductivity type impurities in a portion of the second epitaxial layer exceeds the concentration of first conductivity type impurities, thereby forming a second field region of the second conductivity type in the second epitaxial layer.

19. The method for manufacturing a semiconductor device according to claim 18, wherein the second ion implantation step is performed after the first ion implantation step.

20. A method for manufacturing a semiconductor device according to claim 18 or 19, wherein the first ion implantation step includes implanting ions of a second conductivity type from the main surface of the wafer toward the first epitaxial layer via a mask, and the second ion implantation step includes implanting ions of a second conductivity type from the main surface of the wafer toward the second epitaxial layer via the mask.

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