Low-complexity linear feedback shift register for cyclic redundancy check encoding and decoding

Abstract

Cyclic redundancy check (CRC) algorithms are utilized in digital communication and storage systems for error detection. CRC encoding and decoding may be implemented using linear feedback shift registers (LFSRs). To achieve high throughput, a parallel LFSR may be implemented by registers using feedback matrix and pre-processing matrix multiplication. In conventional architectures, a feedback matrix may be decided by look-ahead computations of an FSR, and the corresponding matrix multiplication may contribute to a significant portion of the overall complexity of the LFSR. The methods described herein are provide for searching over a wide range of powers of a companion matrix describing the parallel LFSR in order to minimize the logic gate count required for the feedback matrix multiplication.

Description

LOW-COMPLEXITY LINEAR FEEDBACK SHIFT REGISTER FOR CYCLIC REDUNDANCY CHECK ENCODING AND DECODINGCROSS REFERENCE TO RELATED APPLICATIONS

[0001] The present application is a continuation application of U. S. Patent. Application No.63 / 712,874, filed on October 28, 2024, which is hereby incorporated by reference in its entirety.GO VERNMENT LICENSE RIGHTS

[0002] This invention was made with government support under Award No. 2011785 awarded by the National Science Foundation. The government has certain rights in the invention.BACKGROUND

[0003] Cyclic redundancy check (CRC) algorithms are widely used in many digital communication and storage systems for detecting data corruption, ensuring the reliable transfer of data.BRIEF SUM ARY

[0004] Cyclic redundancy check (CRC) algorithms are widely used in many digital communication and storage systems for detecting data corruption, ensuring the reliable transfer of data. In general, a CRC encoder-decoder of a sender (e.g., an originating computing device) may utilize a CRC algorithm to encode data to be transmitted to a receiver (e.g., a receiving computing device), where a CRC encoder-decoder of the receiver may use the CRC algorithm to decode the data in order to determine if the data has been transmitted with errors or corruption (e.g., errors caused by transmission interference). On the sender’s side, the CRC encoderdecoder may perform polynomial division using the data to be transmitted (e.g., binary data) and a divisor (e.g., a binary string decided by a generator polynomial) to compute parity bits, which are remainder values derived from the binary- division. The CRC encoder-decoder may append the parity bits to the data to be transmitted. On the receiver’s side, the CRC encoder-decoder may perform a similar binary division using the data with the appended parity bits and the same divisor (e.g., the same generator polynomial). If the CRC encoder-decoder determines that a remainder value of the binary division is zero, the receiver determines that no errors or datacorruption has occurred. In the event that a remainder value is a non-zero value, the receiver determines that an error or data corruption has occurred.

[0005] Linear feedback shift registers (LFSRs) may be used to implement CRC encoding and decoding and may be configured to compute remainders (e.g., CRC code) of polynomial divisions. In the encoding (e g., generation) and decoding of CRC codes, parities are generated as a remainder of dividing a data polynomial (e.g., a binary polynomial representation of data to be transferred, aka. a message polynomial) by a generator polynomial. Such computations can be carried out by using LFSRs, and LFSRs with a high level of parallelism are needed to meet the high-speed requirements of many practical systems. A conventional parallel LFSR may be understood as a shift register that comprises registers whose state is a linear function (e.g., an exclusive-or (XOR) function) of a previous state of the registers. In some examples, a P -parallel LFSR may be developed by applying look-ahead computations to derive the states of data registers after P clock cycles. Such designs may advantageously lead to a shorter critical path (e.g., the longest sequence of computations between any pair of registers) and a lower complexity compared to those derived by other parallel process algorithms (e.g., unfolding algorithms), especially for larger P. In some such examples, the value of P of a P-parallel LFSR may indicate a degree of parallelism of the P -parallel LFSR. Additionally or alternatively, in some examples, a P-parallel LFSR may process P input data bits during each clock cycle of a corresponding processor of a respective computing device utilizing the P-parallel LFSR.

[0006] In some conventional systems, a parallel LFSR based on register state look-ahead utilizes binary matrix multiplications for pre-processing the input of data and updating register states in a feedback loop. For example, in some conventional systems, a register state transformation is used to modify both feedback and pre-processing matrices at the cost of additional post-processing matrix multiplication. In such a system, the data path of multiplying the feedback matrix may be reduced to one XOR gate by using companion-like transformation matrices. However, such transformations may lead to the use of more logic gates in the preprocessing and post-processing matrix multiplications. To mitigate these technical challenges, some conventional systems may endeavor to reduce the overall number of XOR gates by searching for transformation matrices in a triangular form or by searching for inverse transformation matrices to achieve a lower logic gate count and / or reduce the power consumption of a device employing such parallel LFSRs.

[0007] For conventional LFSRs, data input may be added to a most significant tap bit of the LFSR. For a CRC with a generator polynomial of degree w, shifting the input to the least significant tap makes up to w columns of a corresponding pre-processing matrix consist of one single non-zero entry each. Accordingly, the pre-processing matrix multiplication may be simplified and, in some cases, may be completely eliminated when P < w. The same preprocessing matrix can be achieved by using the feedback matrix as the inverse transformation matrix. While conventional LFSR implementations may endeavor to reduce a number of logic gates (e.g., XOR gates), conventional LFSR implementations do not optimize a corresponding feedback matrix, the multiplication of which may contribute to a significant portion of the overall complexity of the LFSR, especially when P is smaller.

[0008] To improve upon conventional systems and techniques for CRC encoding and decoding, an alternative feedback matrix construction that reduces the complexity of parallel LFSRs is provided herein. As will be described in further detail herein, the feedback matrix of conventional P -parallel LFSRs may be defined as Ap, where A is a companion matrix determined by a CRC generator polynomial. In contrast to conventional LFSRs used in CRC encoding and decoding, the methods and systems described herein allow the feedback matrix to be ', where I is an alternative feedback matrix power value (e.g., an integer value) from a search range associated with a particular CRC algorithm (e.g., CRC-32), by interpreting the input data polynomial in a different way. By searching over the range of I, alternative feedback matrices of much lower complexity may be found. Additionally, the methods and systems described herein do not impact the corresponding pre-processing matrix of the LFSR and the LFSR input tap may still be shifted, resulting in further reduction in complexity. For example, in a case in which the parallelism of a respective LFSR equals the degree of a respective generator polynomial, the methods and systems described herein may reduce an XOR logic gate count by 18%-53% and achieve shorter critical path for various CRC algorithms (e.g., CRC-32, CRC-16, and / or the like).

[0009] The implementation of a low-complexity LFSR for CRC encoding and decoding that is described herein may provide a number of technical benefits. For example, the low-complexity LFSR for CRC encoding and decoding may result in higher data throughput for various hardware components associated with computing devices. This may be achieved in part by the fact that the implementation of the low-complexity LFSR described herein reduces a number of requiredlogic gates (e.g., XOR gates) as compared to conventional techniques and hardware designs. Additionally, the implementation of the low-complexity P-parallel LFSR described herein may improve the clock rate of a respective computing device. Furthermore, the reduction of required logic gates (e.g., XOR gates) may advantageously reduce the required size (e.g., area) of various hardware components. As a result, the form factor and / or material requirements for various computing devices may be advantageously reduced. Finally, due to the increased efficiency and data throughput, as well as the reduction in hardware requirements (e.g., materials, components, area), the examples described herein may reduce the overall power consumption of a respective computing device (e.g., a smartphone, laptop computer, and / or the like) while ensuring the correctness of transferred data.BRIEF DESCRIPTION OF THE FIGURES

[0010] Having described certain examples in general terms above, reference will now be made to the accompanying drawings, which are not necessarily drawn to scale. Some examples may include fewer or more components than those shown in the figures.

[0011] FIG. 1 illustrates a system in which some examples may be used for incorporating a low-complexity parallel LFSR system.

[0012] FIG. 2 illustrates a schematic block diagram of example circuitry embodying a system device that may perform various operations in accordance with some examples described herein.

[0013] FIG. 3 illustrates a schematic block diagram of example circuitry' embodying a user device that may perform and / or benefit from various operations in accordance with some examples described herein

[0014] FIG. 4A illustrates an example architecture for a serial LFSR in accordance with some examples described herein.

[0015] FIG. 4B illustrates an example architecture for a parallel LFSR in accordance with some examples described herein.

[0016] FIG. 5 illustrates a table detailing CRC generator polynomials and corresponding search ranges for a low-complexity P-parallel LFSR in accordance with some examples described herein.

[0017] FIG. 6 illustrates a table detailing hardware complexity comparisons of a best prior parallel LFSR to a low-complexity P- parallel LFSR where P ~ w in accordance with some examples described herein.

[0018] FIG. 7 illustrates a table detailing hardware complexity comparisons of a best prior parallel LFSR to a low-complexity P -parallel LFSR where P ~~ 2w in accordance with some examples described herein.

[0019] FIG. 8 illustrates an example flowchart for configuring CRC encoding-decoding circuitry based on a low-complexity P -parallel linear feedback shift register in accordance with some examples described herein.DETAILED DESCRIPTION

[0020] Some examples will now be described more fully hereinafter with reference to the accompanying figures, in which some, but not necessarily all, examples are shown. Because inventions described herein may be embodied in many different forms, the invention should not be limited solely to the examples set forth herein: rather, these examples are provided so that this disclosure wall satisfy applicable legal requirements.

[0021] The term “user device” and “computing device” refers to any one or all of programmable logic controllers (PLCs), programmable automation controllers (PACs), industrial computers, desktop computers, personal data assistants (PDAs), laptop computers, tablet computers, smart books, palm-top computers, personal computers, smartphones, wearable devices (such as headsets, smartwatches, and / or the like), and similar electronic devices equipped with at least a processor and any other physical components necessarily to perform the various operations described herein. Devices such as smartphones, laptop computers, tablet computers, and wearable devices are generally referred to as mobile devices.

[0022] The term “’server” or “server device” refers to any computing device capable of functioning as a server, such as a master exchange server, web server, mail server, document server, or any other type of server. A server may be a dedicated computing device or a server module (e.g., an application) hosted by a computing device that causes the computing device to operate as a server.

[0023] Examples described herein may be implemented using any of a variety of computing devices or servers. To this end, FIG. 1 illustrates an example environment 100 within whichsvarious examples may operate. As illustrated, a low-complexity parallel LFSR system 102 may receive and / or transmit information via communications network 104 (e.g., a telecommunications network (e.g,, 5G network), wide area network (WAN), local area network (LAN), wireless Internet network, and / or the like capable of facilitating remote network communications) with any number of other devices, such as one or more user device(s) 106. The low-complexity parallel LFSR system 102 may be implemented as one or more computing devices or servers, which may be composed of a series of components. Particular components of the low-complexity parallel LFSR system 102 are described in greater detail below with reference to apparatus 200 in connection with FIG. 2.

[0024] In various examples, the low-complexity parallel LFSR system 102 may be associated with an enterprise (e.g., a telecommunications enterprise and / or the like) and may be configured to manage various processes for said enterprise. For example, the low-complexity parallel LFSR system 102 may be configured to manage, execute, initiate, and / or otherwise facilitate one or more matrix generation processes, CRC encoding or decoding processes, user and / or user account identification processes, data ingestion processes, data management processes, and / or the like for a respective enterprise.

[0025] In some examples, various users associ ted with an enterprise may interact with the low-complexity parallel LFSR system 102 via a software application instance, where the software application instance may be configured to facilitate one or more of the various processes described herein. In various examples, the software application instance associated with the low-complexity parallel LFSR system 102 may be installed and / or downloaded to a computing device and may present one or more user interface configurations to a respective user. As such, the software application instance associated with the low-complexity parallel LFSR system 102 may be configured to guide a user through the various steps operations described herein. The low-complexity parallel LFSR system 102 (described previously with reference to FIG. 1) may be embodied by one or more computing devices or servers, shown as apparatus 200 in FIG. 2. The apparatus 200 may be configured to execute various operations described above in connection with FIG. 1 and below in connection with FIGS. 4A-4B, and 5-8. As illustrated in FIG. 2, the apparatus 200 may include processor 202, memory' 204, communications hardware 206, and / or low-complexity parallel LFSR management circuitry 208, each of which will be described in greater detail below'.

[0026] The processor 202 (and / or co-processor or any other processor assisting or otherwise associated with the processor) may be in communication with the memory 204 via a bus for passing information amongst components of the apparatus 200. The processor 202 may be embodied in a number of different ways and may, for example, include one or more processing devices configured to perform independently. Furthermore, the processor 202 may include one or more processors configured in tandem via a bus to enable independent execution of software instructions, pipelining, and / or multithreading. The use of the term “processor 202” may be understood to include a single core processor, a multi-core processor, multiple processors of the apparatus 200, remote or “cloud” processors, or any combination thereof.

[0027] The processor 202 may be configured to execute software instructions stored in the memory' 204 or otherwise accessible to the processor 202. In some cases, the processor may be configured to execute hard-coded functionality. As such, whether configured by hardware or software methods, or by a combination of hardware with software, the processor 202 represents an entity (e.g., physically embodied in circuitry) capable of performing operations according to various examples of the present invention while configured accordingly. Alternatively, as another example, when the processor 202 is embodied as an executor of software instructions, the software instructions may specifically configure the processor 202 to perform the algorithms and / or operations described herein when the software instructions are executed.

[0028] The memory 204 is non-transitory and may include, for example, one or more volatile and / or non-volatile memories. In other words, for example, the memory' 204 may be an electronic storage device (e.g., a computer-readable storage medium). The memory 204 may be configured to store information, data, content, applications, software instructions, and / or the like for enabling the apparatus 200 to carry' out various functions in accordance with examples contemplated herein.

[0029] The communications hardware 206 may be any means such as a device or circuitry embodied in either hardware or a combination of hardware and software that is configured to receive and / or transmit data from / to a network (e.g., communications network 104) and / or any other device, circuitry, or module in communication with the apparatus 200. In this regard, the communications hardware 206 may include, for example, a network interface for enabling communications with a wired or wireless communication network. For example, the communications hardware 206 may include one or more network interface cards, antennas,buses, switches, routers, modems, and supporting hardware and / or software, or any other device suitable for enabling communications via a network. Furthermore, the communications hardware 206 may include the processing circuitry for causing transmission of such signals to a network or for handling receipt of signals received from a network.

[0030] The communications hardware 206 may further be configured to provide output to a user and, in some examples, to receive an indication of user input. In this regard, the communications hardware 206 may comprise a user interface, such as a display, and may further comprise the components that govern use of the user interface, such as a web browser, software application instance, dedicated user device, and / or the like. In some examples, the communications hardware 206 may include a keyboard, a mouse, a touch screen, touch areas, soft keys, a microphone, a camera, a speaker, and / or other input / output mechanisms. The communications hardware 206 may utilize the processor 202 to control one or more functions of one or more of these user interface elements through software instructions (e.g., application software and / or system software, such as firmware) stored on a memory (e.g., memory 204) accessible to the processor 202.

[0031] In addition, the apparatus 200 further comprises low-complexity parallel LFSR management circuitry 208. In some examples, the low-complexity parallel LFSR management circuitry’ 208 may be configured to facilitate the execution of one or more operations for an enterprise associated with the low-complexity parallel LFSR system 102. As such, the low-complexity parallel LFSR management circuitry' 208 may utilize the communications hardware 206 to gather data from, or transmit data to, a variety of sources (e.g., user device, telecommunications servers, third-party server systems, and / or any storage devices associated with the low-complexity parallel LFSR system 102), and / or exchange data with a user.Additionally, the low-complexity parallel LFSR management circuitry 208 may utilize processor 202, memory 204, and / or any other hardware component included in the apparatus 200 to perform these operations, as described in connection with FIGS. 4A-4B, and 5-8 below.

[0032] Furthermore, in various examples, the low-complexity parallel LFSR management circuitry 208 may be configured to leverage the processor 202, the memory 204, and / or the communications hardware 206 to generate, cause transmission of, and / or cause display of a plurality of interactive user interface elements on a user interface associated with a software application instance associated with the low-complexity parallel LFSR system 102 on acomputing device. The plurality of interactive user interface elements may be configured as one or more interactive text fields, text input lines, buttons, selectable images, hyperlinks, radio buttons, sliders, embedded multimedia modules, maps, charts, graphs, prompts, notifications, banners, instructions, and / or the like configured to initiate execution of one or more commands (e.g., executable software instructions) designed to facilitate the capture of one or more portions of user input.

[0033] In various examples, a respective user device 106 may be embodied by one or more computing devices or servers, shown as apparatus 300 in FIG. 3. The apparatus 300 may be configured to execute various operations described above in connection with FIG. 1 and / or below in connection with FIGS. 4A-4B, and 5-8. As illustrated in FIG. 3, the apparatus 300 may include processor 302, memory 304, communications hardware 306, and / or CRC encodingdecoding circuitry 308, each of which will be described in greater detail below. In various examples, a respective user device 106 may be embodied by any computing devices known in the art. In some examples, the respective user device 106 need not be an independent device but may be peripheral devices communicatively coupled to other computing devices.

[0034] The processor 302 (and / or co-processor or any other processor assisting or otherwise associated with the processor) may be in communication with the memory 304 via a bus for passing information amongst components of the apparatus 300. The processor 302 may be embodied in a number of different ways and may, for example, include one or more processing devices configured to perform independently. Furthermore, the processor 302 may include one or more processors confi ured in tandem via a bus to enable independent execution of software instructions, pipelining, and / or multithreading. The use of the term “processor 302” may be understood to include a single core processor, a multi -core processor, multiple processors of the apparatus 300, remote or “cloud” processors, or any combination thereof.

[0035] The processor 302 may be configured to execute software instructions stored in the memory 304 or otherwise accessible to the processor 302. In some cases, the processor 302 may be configured to execute hard-coded functionality. As such, whether configured by hardware or software methods, or by a combination of hardware with software, the processor 302 represents an entity' (e.g., physically embodied in circuitry) capable of performing operations according to various examples of the present invention while configured accordingly. Alternatively, as another example, when the processor 302 is embodied as an executor of software instructions,the software instructions may specifically configure the processor 302 to perform the algorithms and / or operations described herein when the software instructions are executed.

[0036] The memory 304 is non-transitory and may include, for example, one or more volatile and / or non-volatile memories. In other words, for example, the memory 304 may be an electronic storage device (e.g., a computer readable storage medium). The memory 304 may be configured to store information, data, content, applications, software instructions, and / or the like for enabling the apparatus 300 to carry out various functions in accordance with examples contemplated herein.

[0037] The communications hardware 306 may be any means such as a device or circuitry embodied in either hardware or a combination of hardware and software that is configured to receive and / or transmit data from / to a network (e.g., communications network 104) and / or any other device, circuitry, or module in communication with the apparatus 300. In this regard, the communications hardware 306 may include, for example, a network interface for enabling communications with a wired or wireless communication network. For example, the communications hardware 306 may include one or more network interface cards, antennas, buses, switches, routers, modems, and supporting hardware and / or software, or any other device suitable for enabling communications via a network. Furthermore, the communications hardware 306 may include the processing circuitry for causing transmission of such signals to a network or for handling receipt of signals received from a network.

[0038] The communications hardware 306 may further be configured to provide output to a user and, in some examples, to receive an indication of user input. In this regard, the communications hardware 306 may comprise a user interface, such as a display, and may further comprise the components that govern use of the user interface, such as a web browser, software application instance, dedicated user device, and / or the like. In some examples, the communications hardware 306 may include a keyboard, a mouse, a touch screen, touch areas, soft keys, a microphone, a camera, a speaker, and / or other input / output mechanisms. The communications hardware 306 may utilize the processor 302 to control one or more functions of one or more of these user interface elements through software instructions (e.g., application software and / or system software, such as firmware) stored on a memory (e.g., memory 304) accessible to the processor 302,

[6039] In addition, the apparatus 300 further comprises CRC encoding-decoding circuitry 308. In some examples, the CRC encoding-decoding circuitry' 308 may be configured to facilitate the execution of one or more operations for a user device (e.g., user device 106). For example, the CRC encoding-decoding circuitry' 308 may be configured to execute one or more CRC processes configured to encode various data to be transferred to a receiving device (e.g., a different computing device), where encoding the data to be transferred comprises computing a CRC code (e.g., a remainder (set of parity bits) determined based on polynomial division) based on one or more portions of the data to be transferred and a respective, predetermined generator polynomial. Additionally, in some examples, the CRC encoding-decoding circuitry' 308 may be configured to append a generated CRC code, and / or the like to a data message comprising data to be transferred to a receiving device.

[0040] Additionally or alternatively, the CRC encoding-decoding circuitry 308 may be configured to execute one or more CRC processes configured to decode various data (e.g., data messages comprising an appended CRC code, and / or the like) received from a sending device (e.g., a different computing device), where decoding the data comprises computing a remainder value using at least a predetermined generator polynomial. As such, the CRC encoding-decoding circuitry'- 308 may leverage a low-complexity P-parallel LFSR configured according to the various methods described herein in order to facilitate the encoding and / or decoding of CRC codes associated with outgoing and / or incoming data, respectively. In some examples, the CRC encoding-decoding circuitry 308 may be embodied by a standalone CRC encoder-decoder (e.g., a purpose-built hardware component (e.g., an FPGA, IC, MCU and / or the like)) associated with a respective user device 106. In other examples, the CRC encoding-decoding circuitry' 308 may be embodied by the main processing circuitry (e.g., a core processor) of a respective user device 106.

[0041] As such, the CRC encoding-decoding circuitry' 308 may utilize the communications hardware 306 to gather data from, or transmit data to, a variety of sources (e.g., user device, telecommunications servers, third-party server systems, and / or any storage devices associated with the low-complexity parallel LFSR system 102), and / or exchange data with a user.Additionally, the CRC encoding-decoding circuitry 308 may utilize processor 302, memory 304, and / or any other hardware component included in the apparatus 300 to perform these operations, as described in connection with FIGS. 4A-4B, and 5-8 below

[0042] FIGS. 4A and 4B illustrate various example architectures for LFSRs. Specifically, FIG. 4A illustrates an example architecture for a serial LFSR, and FIG. 4B illustrates an example architecture for a parallel LFSR in accordance with some examples described herein.

[0043] A CRC algorithm that adds vv - n — k parity bits to a k-bit data string to form a n-bit codeword can be specified by a generator polynomial g x) -g±x + gQ, where gw-lt,gltg0are either ‘1’ or ‘O’. Let d(x) and p(x) be the polynomial representations of the data string and parities, respectively. In CRC encoding, the parity polynomial is computed as follows:(x) = d(x) xAvv mod g xEquation 1where ‘mod’ denotes modular reduction. In CRC decoding, the same polynomial division as in Equation 1 is carried out over a received data polynomial and the received parity polynomial to check if a corresponding remainder polynomial matches the received parity polynomial.

[0044] Polynomial divisions in CRC encoding and decoding can be carried out by using LFSRs. FIG. 4A shows a serial LFSR architecture. The coefficients of d(x) are sent to the most significant tap on the right side, one coefficient in each clock cycle, starting from the most significant coefficient. After the last data coefficient is processed, the coefficients of p(x) are available in the registers (e.g., registers 402A, and 402B, through 402\..: aad-402.-,

[0045] Let r(t) ~,r0(t)]' represent the state of the vv registers and u(t) be the input in clock cycle t, where denotes transpose. From FIG. 4A,r(t 4- 1) = A x r(t)h+ b x u(t)Equation 2whereand b - [gw-i» > gi> goK- Such an A matrix may be referred to as a companion matrix. By substituting Equation 2 back to itself for P times, the formula for the state updating of the LFSR that processes P inputs in each clock cycle may be derived asEquation 3Accordingly, a P- parallel LFSR can be constructed as in FIG. 4B. Such an architecture takes [k / P] clock cycles to compute the remainder for CRC encoding or decoding. The binary Apmay be referred to as the feedback matrix and the binary Bpmay be referred to as the pre-processing matrix.

[0046] Some conventional designs have endeavored to reduce the logic gate counts of the matrix multiplications in Equation 3. Among such conventional designs, one or more designs are configured to shift the input tap and may achieve a relatively low' complexity. When the input is shifted by j taps, the b in Equation 2 may be replaced by b;, which has a single nonzero entry in the (w — j)-th position. Accordingly, the BPin Equation 3 from a look-ahead computation may become Bp ~. To generate the same p(x) as inEquation 1, / zeros need to be padded to the data polynomial, d(x), in order to scale it by in the division. Byshifting the input to the least significant tap, up to w columns of the pre-processing matrix consist of one single non-zero entry each. When P < w, the pre-processing matrix multiplication may be eliminated.

[0047] However, conventional techniques (e.g., shifting the input tap as described above) do not change the feedback matrix, Ap. The multiplication of this matrix contributes to a significant part of the overall gate count. To lower the complexity, examples described herein are configured to determine and utilize an alternative feedback matrix and modify the interpretation of an input data string accordingly for parity computation. The pre-processing matrix is unaffected by the examples described herein such that the complexity of the pre-processing matrix may still be reduced (e.g., by shifting the input tap).

[0048] Instead of the conventional feedback matrix Ap, the example described herein utilize an alternative feedback matrix A{, where I is an integer. Let(x) and r^(x) denote the polynomial representations of uP(t and r(trespectively. Multiplying r(t) with A corresponds to computing (x)x mod g(x). Hence, multiplying'with A can be interpreted as r^(x)xJmod g x). The i-th (0 < i < P) column, counting from the right, in Bp1is the vector representation of xw~^+lmod (x). Hence, the product of Bp1and uP(t) is equivalent toUp)x)xw Jmod g(x). Using these polynomial representations, the examples described herein ca ' out the following computations according to Equation 3, assuming H°) is initially zero.

[0049] At cl ock cy cl e 0:At clock cycle 1:Equation 4

[0050] For a P -parallel LFSR, the degree o) is P - 1. From Equation 4, some coefficients of u^(x) will be XORed to those of Up "^(x) if I < P. If a pair of data coefficients that are XORed are both ‘T, then the XOR result is zero. If all the other data coefficients are ‘O’, then the parity polynomial p(x), which equals the r^'(x) in the last clock cycle, is zero. As such, there is a codeword of weight two. Hence, the minimum error distance (e.g., minimum Hamming distance) of the CRC algorithm is two and some of the error patterns wdth weight two are undetectable. In order to increase the minimum error distance of the CRC algorithm, none of the input data should be directly XORed in the iterative register state updating process. This means that I needs to be at least P since deg ~ P — 1. Let 5 be thesmallest integer such that xsmod g x) ~ 1. This s is also the smallest integer such that As~ I. Hence, I < s. If I > s — w, then deg^U °'(x)xw~Jx^ ~ P - 1 + w - / + I > P - 1 + w -- / + s ■■■■ w + 1 = P - j + s. Additionally, deg^ °',(x)xw“Jx < P ■■■■ 1 +■ w ■■■■ j + s. Takinginto account that xsmod g(x) = 1, xscan be taken out and P - j <<P - 1 4- w - j. As a result, some coefficients ofwill be XORed to those of tip ' (x) in Equation 4, which also causes the minimum error distance of the CRC algorithms to be two. In summary’, P < I < s — w can be searched to find the A;with the lowest complexity. As shown in FIG. 5, Table 500 lists the commonly used CRC generator polynomials along with the corresponding search ranges for I.

[0051] In some examples, the i-th (0 < i < pc / P]) group of P data bits is mapped to the coefficients of up'l)(x)jnEquation 4, where k is the total number of data bits. Each group is separated by I degrees and the coefficients in between are zeros. As a result, the degree of the data polynomial in the proposed design, denoted by d'-(x), equals that ofEquation 5Therefore, the degree of the data polynomial changes with P and increases with I. To guarantee the detection of errors with a given weight for a respective CRC algorithm, there is a limit on the length of maximum length of the input data. This maximum length may be used to evaluate the performance of CRC algorithms and it is referred to as the maximum protected data length herein. Although the examples described herein interpret the input data as the coefficients of a much longer polynomial, each group of data, coefficients may have one or more zeros in between.

[0052] The maximum protected data lengths for most conventional CRC algorithms decrease for larger minimum distance requirement (e.g., minimum error distance requirements, Hamming distance requirements). For the examples described herein, simulations have been carried out to find the achievable protected data length by increasing the number of non-zero data bits one at a time to determine whether there is any valid codeword whose number of non-zero bits is less than the minimum error distance. Most CRC algorithms can support significantly longer data lengths compared to application requirements, especially those with longer generator polynomials. For instance, the IEEE 802.3 standard that uses the CRC-32 algorithm (e.g., as shown in Table 500 of FIG. 5) only requires a data string length of around 12000 bits for minimum error distance of four. However, the maximum protected data length for the CRC-32 algorithm with the same minimum error distance of four is 91,607 bits.

[0053] In some examples, a low-complexity P -parallel LFSR may be implemented using a same or similar architecture as illustrated in FIG. 4B, where the Apmatrix (e.g., the feedback matrix) in this figure is replaced by (e.g., an alternative feedback matrix). In some such examples, the low-complexity parallel LFSR management circuitry 208 may be configured to search over P < I < s - w, in order to determine a matrixwith the lowest complexity. Insome examples, if the low-complexity parallel LFSR management circuitry 208 determines that s - MZ is a very large number (e.g., such as in the case of CRC-32) and an exhaustive search cannot be completed within a predetermined amount of time (e.g., within 5 minutes, 30 minutes, I hour, or any other predetermined amount of time), the low-complexity parallel LFSR management circuitry 208 may carry out a partial search instead, where the partial search may be a shortened search. As described herein, when an alternative feedback matrix A1is used, an input tap shifting approach may be employed such that the pre-processing matrix BP(e.g., as shown in FIG. 4B) may be replaced by Bp '. As a result, the method described herein reduces the complexity of the feedback matrix multiplication while maintaining a simple pre-processing matrix, and hence leads to a lower gate count compared to various other conventional LFSR implementations for CRC encoding and decoding.

[0054] In examples in which P < w, the multiplication of Bp7does not require XOR gates, and the multiplication of A1decides the critical path. Since the alternative feedback matrix A;is substantially simpler than conventional implementations, the required matrix ultiplication may have a shorter critical path than that of the feedback matrix Apused in conventional parallel LFSR designs. In examples in which P > w, the critical path of the low-complexity P -parallel LFSR is decided by the maximum data path of the alternative feedback matrix A' and Bp multiplications.

[0055] FIGS. 6-7 illustrate hardware complexity comparisons of a respective example conventional parallel LFSR and a respective example low-complexity P -parallel LFSR that were analyzed for various parallelisms and CRC algorithms. Results related to the achievable maximum protected data length are also presented.

[0056] Specifically, FIG. 6 illustrates a table 600 detailing a comparison of the hardware complexities of an example conventional parallel LFSR 602 and an example low-complexity P-parallel LFSR 604 in which P ~ w, where w is the degree of a corresponding generator polynomial g(x). For matrix multiplication, the number of XORs needed is estimated as the sum of the amount of 1’s in each row of the matrix minus one. In some examples, the data path is derived assuming the 1 ’s are XORed in a tree structure. In the case of P ~ w, the lowest complexity for the pre-processing matrix may be achieved by shifting the input by P taps to aleast significant tap on the left side of the low-complexity P -parallel LFSR (e.g., low-complexity P-parallel LFSR 604).

[0057] Bp’'17-' is an identity matrix, and hence does not require any logic gates to implement. In some examples, the low-complexity parallel LFSR management circuitry 208 may be configured to execute one or more simulations in order to determine an alternative feedback matrix A' having a lowest complexity (e.g., requiring a least amount of XOR gates) within a corresponding search range (e.g., corresponding search ranges as presented with reference to table 500). It can be observed from table 600 that the alternative feedback matrix A' used an example low-complexity P-parallel LFSR (e.g., low-complexity P-parallel LFSR 604) has a much lower gate count than the feedback matrix Apassociated with a conventional parallel LFSR (e.g., conventional parallel LFSR 602). A w-bit register and a w-bit adder have similar areas as 3 and w XOR gates, respectively. The total number of XORs needed by a respective parallel LFSR may be estimated from this assumption. For example, as shown in table 600 of FIG. 6, an example low-complexity P-parallel LFSR (e.g., low-complexity P-parallel LFSR 604) may achieve an 18% - 53% reduction in the total number of XOR gates compared to an example conventional parallel LFSR (e.g., conventional parallel LFSR 602). When P = w, the critical path of a respective parallel LFSR is the data path of the corresponding feedback matrix multiplication plus one. Since the alternative feedback matrix A£in the example low-complexity P-parallel LFSR (e.g., low-complexity P-parallel LFSR 604) has much shorter data path compared to the feedback matrix Apof the example conventional parallel LFSR (e.g., conventional parallel LFSR 602), table 600 illustrates that the example low-complexity P-parallel LFSR can achieve a shorter critical path compared to the example conventional parallel LFSR.

[0058] Furthermore, the protected data lengths that can be achieved by an example low-complexity P-parallel LFSR (e.g., low-complexity P-parallel LFSR 604) are listed in table 600. In some examples, although the data bits associated with a low-complexity P-parallel LFSR (e.g., low-complexity P-parallel LFSR 604) are mapped to data coefficients of higher degrees, the data bits between groups of P bits are zeros. As a result, the protected data length is not reduced to levels that violate modern telecommunications standards despite the much higher degree of the data polynomial. As i t is shown in table 600, for CRC-32, an example low-complexity P-parallel LFSR (e.g., low'-complexity P-parallel LFSR 604) can still effectivelyprotect data strings of 12000 bits and reach a minimum distance of 4 as required by the IEEE 802.3 standard.

[0059] Turning to FIG. 7, table 700 details a comparison of the hardware complexities of an example conventional parallel LFSR 702 and an example low-complexity P-parallel LFSR 704 in which P 2w. In some examples, values of the I of an example low-complexity P -parallel LFSR (e.g., low-complexity P -parallel LFSR 704) are searched over the range of [P,s — w]. Because the optimal Fs found for the case of P - w as shown in table 600 are all larger than 2iv, the same Fs are also optimal for the case of P ~ 2w.. Additionally, the corresponding preprocessing matrix based on shifting the input tap to the left-most tap still has the lowest complexity in the case of P = 2w. However, the dimension of the corresponding pre-processing matrix is now w x 2w and requires logic gates (e.g., XOR gates) to implement. As a result and as shown in table 700, the savings achieved by the example low-complexity P-parallel LFSR (e.g., low-complexity P-parallel LFSR 704) in terms of the number of XOR gates may be less significant compared to the case of P = w for the example low-complexity P-parallel LFSR (e.g., low-complexity P-parallel LFSR 604) shown in table 600. As such, in some examples, using a larger P may not necessarily reduce the achievable length of protected data. As shown in table 700, in the examples of CRC-16 and CRC-12, the achievable protected data length of the example low-complexity P-parallel LFSR (e.g., low-complexity P-parallel LFSR 704) in which P ~ 2iv is longer than that for the example low-complexity P-parallel LFSR (e.g., low-complexity P-parallel LFSR 604) in which P - w as shown in table 600.

[0060] In this regard, an example low-complexity P-parallel LFSR may achieve the highest percentage of complexity reduction when P ~ w. When P > w, the corresponding preprocessing matrix has P — iv columns with more than one non-zero entries. Hence, the matrix multiplication related to the pre-processing matrix contributes to a significant portion of the overall LFSR complexity as the value of P increases. However, when P < w. the pre-processing matrix multiplication does not require any logic gates to implement, thus the complexity of the feedback matrix multiplication may determine the overall complexity of the low-complexity P-parallel LFSR.

[0061] FIG. 8 illustrates an example flowchart 800 comprising example operations for configuring CRC encoding-decoding circuitry based on a low-complexity P-parallel linear feedback shift register.

[0062] The operations illustrated in FIGS. 8 illustrate a computer-implemented method that may, for example, be performed by a system device (e.g., server, etc.) of the low-complexity parallel LFSR system 102 shown in FIG. 1, which may in turn be embodied by an apparatus 200, which is shown and described in connection with FIG. 2. To perform the operations described below, the apparatus 200 may utilize one or more of processor 202, memory 204, communications hardware 206, low-complexity parallel LFSR management circuitry' 208, and / or any combination thereof. It will be understood that user interactions with the low-complexity parallel LFSR system 102 may occur directly via communications hardware 206 or may instead be facilitated by a separate computing device (e.g., a user device 106, as shown in FIG. 1), and which may have physical componentry' for facilitating such user interactions.

[0063] As show'll by operation 802, the apparatus 200 may include means, such as low-complexity parallel LFSR management circuitry 208, and / or the like for determining a preprocessing matrix (e.g., pre-processing matrix BPas described with reference to FIG. 4B).

[0064] At operation 804, the apparatus 200 may include means, such as low-complexity' parallel LFSR management circuitry 208, and / or the like for determining an alternative feedback matrix. In some examples, the alternative feedback matrix may be determined based in part on a particular CRC algorithm (e.g., CRC-32, CRC-16, or the like) prior to the generation of a respective low-complexity P-parallel LFSR. Once the particular CRC algorithm has been determined, the low-complexity parallel LFSR management circuitry 208 may be configured to determine a search range for an alternative feedback matrix power I related to the alternative feedback matrix. As described herein, the search range may be defined as P < I < s - w, where s is a smallest integer such that for a companion matrix A, Asis an identity matrix, and where w is equivalent to a degree of a generator polynomial associated with the CRC algorithm.

[0065] Additionally, in some examples, the low-complexity parallel LFSR management circuitry 208 may be configured to determine, based on executing a search with respect to the search range, a value of the alternative feedback matrix power I. In some such examples, the value may be a value for which a fewest amount of logic gates (e.g., XOR gates) are required to complete matrix multiplication computations related to the alternative feedback matrix. As described herein, the alternative feedback matrix is equivalent to A1.

[0066] In some examples, the low-complexity parallel LFSR management circuitry’ 208 may determine that a difference of s ■■■■ w exceeds a predetermined threshold. In some such examplesand as described herein, in response to determining that a difference of s — w exceeds a predetermined threshold, the low-complexity parallel LFSR management circuitry 208 may be configured to execute a partial search with respect to the search range, where the partial search is associated with a shorter duration of time relative to the search. In such examples, the low-complexity parallel LFSR management circuitry’ 208 may be configured to determine, based on executing the partial search, the value of the alternative feedback matrix power I.

[0067] At operation 806, the apparatus 200 may include means, such as low-complexity parallel LFSR management circuitry 208, and / or the like for generating, based in part on the preprocessing matrix and the alternative feedback matrix, a low-complexity P-parallel LFSR. As described herein, in some examples, the low-complexity P -parallel linear feedback shift register may have an architecture similar to the one illustrated in FIG. 4B, where the conventional feedback matrix Apis replaced with the alternative feedback matrix, A.

[0068] In some examples, the low-complexity parallel LFSR management circuitry 208 may be configured to determine, based on the CRC algorithm, an achievable protected data length associated with the low-complexity P -parallel linear feedback shift register. In some such examples, the achievable protected data length may be determined by incrementing non-zero data bits to determine existence of a valid codeword comprising a number of non-zero bits that is less than a predetermined minimum error distance.

[0069] At operation 808, the apparatus 200 may include means, such as low-complexity parallel LFSR management circuitry 208, and / or the like for configuring CRC encodingdecoding circuitry based on the low-complexity P-parallel linear feedback shift register. For example, the low-complexity parallel LFSR management circuitry 208 may be configured to facilitate the programming, formatting, construction, and / or development of one or more components associated with the CRC encoder-decoder circuitry (e.g., CRC encoding-decoding circuitry' 308). In some such examples, the CRC encoding-decoding circuitry (e.g., CRC encoding-decoding circuitry / 308) may be associated with (e.g., embodied by, integrated with, communicably couple to) a respective user device (e.g., user device 106).

[0070] In this regard, in some embodiments, the CRC encoding-decoding circuitry' (e.g., CRC encoding-decoding circuitry 308) may be configured to generate, based on a data. polynomial associated with an input data string, a parity polynomial. In such embodiments, the CRC encoding-decoding circuitry / (e.g., CRC encoding-decoding circuitry 308) may beconfigured to cause transmission (e.g., in conjunction with communications hardware 306) of the data polynomial and the parity polynomial to a CRC encoder-decoder.

[0071] Additionally or alternatively, in some examples, the CRC encoding-decoding circuitry' (e.g., CRC encoding-decoding circuitry' 308) may be configured to receive (e.g., from a different computing device) a data polynomial and a parity polynomial, where the parity polynomial is generated based on the data polynomial. In some such examples, the CRC encoding-decoding circuitry (e.g., CRC encoding-decoding circuitry 308) may be configured to determine, whether the parity polynomial matches a remainder polynomial, where the remainder polynomial is determined based on a polynomial division of the data polynomial and the parity polynomial. In such examples, the polynomial division of the data polynomial and the parity polynomial may be executed at least in part by the low-complexity P-parallel linear feedback shift register.CONCLUSION

[0072] Methods for implementing a low-complexity P-parallel LFSR architecture using an alternative feedback matrix have been described herein. Unlike conventional parallel LFSRs whose feedback matrix is decided by the corresponding parallelism and / or generator polynomial, systems described herein search over a wide range of matrices in order to determine an alternative feedback matrix leading an improved (e.g., lower complexity) P-parallel LFSR. Furthermore, while the input data may be interpreted as coefficients of a polynomial having relatively higher degrees, the achievable protected data length is not adversely reduced and implementing the low-complexity P-parallel LFSR described herein for CRC encoding and decoding still satisfies the requirements of the IEEE standards. Additionally, the low-complexity P-parallel LFSR described herein does not affect pre-processing matrix multiplication such that the complexity of the low-complexity P-parallel LFSR may still be further reduced (e.g., by implementing input tap shifting techniques).

[0073] Many modifications and other examples of the inventions set forth herein will come to mind to one skilled in the art to which these inventions pertain having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Therefore, it is to be understood that the inventions are not to be limited to the specific examples disclosed and that modifications and other examples are intended to be included within the scope of the appended claims. Moreover, although the foregoing descriptions and the associated drawings describeexamples in the context of certain example combinations of elements and / or functions, it should be appreciated that different combinations of elements and / or functions may be provided by alternative examples without departing from the scope of the appended claims. In this regard, for example, different combinations of elements and / or functions than those explicitly described above are also contemplated as may be set forth in some of the appended claims. Although specific terms are employed herein, they are used in a generic and descriptive sense only and not for purposes of limitation.

Claims

CLAIMSWhat is claimed is:

1. A method comprising:determining a pre-processing matrix,determining an alternative feedback matrix A1generating, based in part on the pre-processing matrix and the alternative feedback matrix, a low-complexity P -parallel linear feedback shift register, andconfiguring cyclic redundancy check (CRC) encoding-decoding circuitry based on the low-complexity P-parallel linear feedback shift register.

2. The method of claim 1, wherein P represents a number of input data bits to be processed during a given clock cycle, and wherein determining the alternative feedback matrixA comprises determining a value of an alternative feedback matrix power L wherein the value of the alternative feedback matrix power I is not limited to P.

3. The method of claim 2, wherein determining the value of the alternative feedback matrix power I compri ses searching over a predetermined range of integers.

4. The method of any one of claims 2 or 3, wherein the value of the alternative feedback matrix power I is a value for which a fewest amount of exciusive-or (XOR) gates are required for matrix multiplication computations related to the alternative feedback matrix / .

5. The method of any one of claims 2-4, wherein the value of the alternative feedback matrix power I is a value which reduces a critical path associated with a CRC algorithm.

6. The method of claim 1, wherein the CRC encoding-decoding circuitry is configured to:generate, based on a data polynomial associated with an input data string, a parity polynomial; andcause transmission of the data polynomial and the parity polynomial to a user device7. The method of claim 1, wherein the CRC encoding-decoding circuitry is configured to: receive a data polynomial and a parity polynomial, wherein the parity polynomial is generated based on the data polynomial, anddetermine whether the parity polynomial matches a remainder polynomial, wherein the remainder polynomial is determined based on a polynomial division of the data polynomial and the parity polynomial.

8. A non-transitory computer-readable storage medium storing software instructions that, when executed by a processor of an apparatus, causes the apparatus to:determine a pre-processing matrix;determine an alternative feedback matrix Al,generate, based in part on the pre-processing matrix and the alternative feedback matrix, a low-complexity P-parallel linear feedback shift register; andconfigure cyclic redundancy check (CRC) encoding-decoding circuitry' based on the low-complexity P-parallel linear feedback shift register.

9. The non-transitory computer-readable storage medium of claim 8, wherein P represents a number of input data bits to be processed during a given clock cycle, and wherein determining the alternative feedback matrix A1comprises determining a value of an alternative feedback matrix power I, wherein the value of the alternative feedback matrix power I is not limited to P.

10. The non-transitory computer-readable storage medium of claim 9, wherein determining the value of the alternative feedback matrix power I comprises searching over a predetermined range of integers.

11. The non-transitory computer-readable storage medium of any one of claims 9 or 10, wherein the value of the alternative feedback matrix power I is a value for which a fewest amount of exclusive-or (XOR) gates are required for matrix multiplication computations related to the alternative feedback matrix A1.

12. The non-transitory computer-readable storage medium of any one of claims 9-11, wherein the value of the alternative feedback matrix power I is a value which reduces a critical path associated with a CRC algorithm.

13. The non-transitory computer-readable storage medium of claim 8, wherein the CRC encoding-decoding circuitry is configured to:generate, based on a data polynomial associated with an input data string, a parity polynomial; andcause transmission of the data polynomial and the parity polynomial to a user device.

14. The non-transitory computer-readable storage medium of claim 8, wherein the CRC encoding-decoding circuitry’ is configured to:receive a data polynomial and a parity polynomial, wherein the parity polynomial is generated based on the data polynomial; anddetermine whether the parity polynomial matches a remainder polynomial, wherein the remainder polynomial is determined based on a polynomial division of the data polynomial and the parity polynomial.

15. A system comprising:low-complexity parallel linear feedback shift register (LFSR) management circuitry configured to:determine a pre-processing matrix,determine an alternative feedback matrix A1,'generate, based in part, on the pre-processing matrix and the alternative feedback matrix, a low-complexity P -parallel LFSR; andconfigure cyclic redundancy check (CRC) encoding-decoding circuitry' based on the low-complexity P -parallel LFSR.

16. The system of claim 15, wherein P represents a number of input data bits to be processed during a given clock cycle, and wherein determining the alternative feedback matrixA1comprises determining a value of an alternative feedback matrix power I, wherein the value of the alternative feedback matrix power I is not limited to P.

17. The system of claim 16, wherein determining the value of the alternative feedback matrix power I comprises searching over a predetermined range of integers.

18. The system of any one of claims 16 or 17, wherein the value of the alternative feedback matrix power I is a value for which a fewest amount of exclusive-or (XOR) gates are required for matrix multiplication computations related to the alternative feedback matrix / .

19. The system of any one of claims 16-18, wherein the value of the alternative feedback matrix power I is a value which reduces a critical path associated with a CRC algorithm.

20. The system of claim 15, wherein the CRC encoding-decoding circuitry is configured to:generate, based on a data polynomial associated with an input data string, a parity polynomial; andcause transmission of the data polynomial and the parity polynomial to a user device.

Images